repo_name
stringlengths 6
79
| path
stringlengths 6
236
| copies
int64 1
472
| size
int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
| ratio
float64 1.51
17.5
| autogenerated
bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
EliasLuiz/TCC | Leon3/lib/testgrouppolito/pr/async_dprc.vhd | 1 | 18,022 | ------------------------------------------------------------------------------
-- Copyright (c) 2014, Pascal Trotta - Testgroup (Politecnico di Torino)
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright notice, this
-- list of conditions and the following disclaimer in the documentation and/or other
-- materials provided with the distribution.
--
-- THIS SOURCE CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-- OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
-----------------------------------------------------------------------------
-- Entity: async_dprc
-- File: async_dprc.vhd
-- Author: Pascal Trotta (TestGroup research group - Politecnico di Torino)
-- Contacts: [email protected] www.testgroup.polito.it
-- Description: dprc async mode (see the DPR IP-core user manual for operations details).
-- Last revision: 08/10/2014
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.DMA2AHB_Package.all;
library testgrouppolito;
use testgrouppolito.dprc_pkg.all;
library techmap;
use techmap.gencomp.all;
entity async_dprc is
generic (
technology : integer := virtex4; -- Target technology
fifo_depth : integer := 9); -- true FIFO depth = 2**fifo_depth
port (
rstn : in std_ulogic; -- Asynchronous Reset input (active low)
clkm : in std_ulogic; -- Clock input
clk100 : in std_ulogic; -- 100 MHz Clock input
dmai : out DMA_In_Type; -- dma signals input
dmao : in DMA_Out_Type; -- dma signals output
icapi : out icap_in_type; -- icap input signals
icapo : in icap_out_type; -- icap output signals
apbregi : in dprc_apbregin_type; -- values from apb registers (control, address, rm_reset)
apbcontrol : out dprc_apbcontrol_type; -- control signals for apb register
rm_reset : out std_logic_vector(31 downto 0)); -- Reconfigurable modules reset (1 bit for each different reconfigurable partition);
end async_dprc;
architecture async_dprc_rtl of async_dprc is
type icap_state is (IDLE, START, READ_LENGTH, WRITE_ICAP, WRITE_ICAP_VERIFY, END_CONFIG, ABORT, ICAP_ERROR_LATENCY);
signal pstate, nstate : icap_state;
type ahb_state is (IDLE_AHB, START_AHB, GRANTED, WAIT_WRITE_END, BUS_CNTL_ERROR, FIFO_FULL, ICAP_ERROR);
signal present_state, next_state : ahb_state;
-- fifo types
type ififo_type is record
wen : std_ulogic;
waddress : std_logic_vector(fifo_depth downto 0);
waddress_gray : std_logic_vector(fifo_depth downto 0);
idata : std_logic_vector(31 downto 0);
full : std_ulogic;
end record;
type ofifo_type is record
ren : std_ulogic;
raddress : std_logic_vector(fifo_depth downto 0);
raddress_gray : std_logic_vector(fifo_depth downto 0);
odata : std_logic_vector(31 downto 0);
empty : std_ulogic;
end record;
-- cdc control signals for async_dprc
type cdc_async is record
start : std_ulogic;
stop : std_ulogic;
icap_errn : std_ulogic;
icap_end : std_ulogic;
end record;
signal fifo_in, regfifo_in : ififo_type;
signal fifo_out, regfifo_out : ofifo_type;
signal raddr_sync, waddr_sync : std_logic_vector(fifo_depth downto 0);
signal cdc_ahb, rcdc_ahb, cdc_icap, rcdc_icap : cdc_async;
type regs_ahb is record
c_grant : std_logic_vector(19 downto 0);
c_ready : std_logic_vector(19 downto 0);
c_latency : std_logic_vector(2 downto 0);
rm_reset : std_logic_vector(31 downto 0);
address : std_logic_vector(31 downto 0);
rst_persist : std_ulogic;
end record;
type regs_icap is record
c_bitstream : std_logic_vector(19 downto 0);
c_latency : std_logic_vector(2 downto 0);
end record;
signal reg, regin : regs_ahb;
signal regicap, reginicap :regs_icap;
signal rstact : std_ulogic;
begin
-- fixed signals
dmai.Data <= (others => '0');
dmai.Beat <= HINCR;
dmai.Size <= HSIZE32;
dmai.Store <= '0'; --Only read transfer requests
dmai.Reset <= not(rstn);
dmai.Address <= reg.address;
rm_reset <= reg.rm_reset;
icapi.idata <= fifo_out.odata;
fifo_in.idata <= dmao.Data;
fifo_in.wen <= dmao.Ready;
-------------------------------
-- ahb bus clock domain
-------------------------------
ahbcomb: process(raddr_sync, regfifo_in, fifo_in, rcdc_ahb, cdc_ahb, reg, present_state, rstn, rstact, apbregi, dmao)
variable vfifo_in : ififo_type;
variable vcdc_ahb : cdc_async;
variable regv : regs_ahb;
variable raddr_sync_decoded : std_logic_vector(fifo_depth downto 0);
begin
apbcontrol.timer_clear <= '0';
apbcontrol.status_clr <= '0';
dmai.Request <= '0';
dmai.Burst <= '0';
dmai.Lock <= '0';
apbcontrol.status_value <= (others=>'0');
apbcontrol.status_en <= '0';
apbcontrol.control_clr <= '0';
apbcontrol.timer_en <= '0';
rstact <= '0';
regv := reg;
vcdc_ahb := rcdc_ahb;
vcdc_ahb.start := '0';
vcdc_ahb.stop := '0';
-- initialize fifo signals
vfifo_in.waddress := regfifo_in.waddress;
vfifo_in.full := '0';
-- fifo full generation
gray_decoder(raddr_sync,fifo_depth,raddr_sync_decoded);
if (vfifo_in.waddress(fifo_depth)=raddr_sync_decoded(fifo_depth) and (vfifo_in.waddress(fifo_depth-1 downto 0)-raddr_sync_decoded(fifo_depth-1 downto 0))>(2**fifo_depth-16)) then
vfifo_in.full := '1';
elsif (vfifo_in.waddress(fifo_depth)/= raddr_sync_decoded(fifo_depth) and (raddr_sync_decoded(fifo_depth-1 downto 0)-vfifo_in.waddress(fifo_depth-1 downto 0))<16) then
vfifo_in.full := '1';
end if;
case present_state is
when IDLE_AHB =>
if (apbregi.control(19 downto 0)/=X"00000") then
next_state <= START_AHB;
apbcontrol.timer_clear <= '1'; -- clear timer register
apbcontrol.status_clr <= '1'; -- clear status register
regv.c_grant := apbregi.control(19 downto 0);
regv.c_ready := apbregi.control(19 downto 0);
regv.address := apbregi.address;
vcdc_ahb.start := '1'; -- start icap write controller
else
next_state <= IDLE_AHB;
end if;
when START_AHB =>
if (dmao.Grant and dmao.Ready)='1' then
next_state <= GRANTED;
else
next_state <= START_AHB;
end if;
dmai.Request <= '1'; -- Request data
dmai.Burst <= '1'; -- Burst transfer
dmai.Lock <= '1'; -- Locked transfer
vcdc_ahb.start := '1'; -- start icap write controller
when GRANTED =>
if (regv.c_grant=0) then -- if the number of granted requests is equal to the bitstream words, no more requests are needed
next_state <= WAIT_WRITE_END;
elsif (vfifo_in.full='1') then
next_state<=FIFO_FULL;
else
next_state <= GRANTED;
dmai.Request <= '1'; -- Request data
dmai.Burst <= '1'; -- Burst transfer
dmai.Lock <= '1'; -- Locked transfer
end if;
when FIFO_FULL =>
if ((regv.c_grant=regv.c_ready) and (vfifo_in.full='0')) then
next_state <= GRANTED;
else
next_state <= FIFO_FULL;
end if;
when WAIT_WRITE_END =>
if (cdc_ahb.icap_end='1') then
next_state <= IDLE_AHB;
regv.rst_persist := '0';
apbcontrol.status_value(3 downto 0) <= "1111";
apbcontrol.status_en <= '1'; -- Write Status Register
apbcontrol.control_clr <= '1'; -- Clear Control Register
vfifo_in.waddress := (others=>'0');
else
next_state <= WAIT_WRITE_END;
end if;
when BUS_CNTL_ERROR =>
next_state <= IDLE_AHB;
regv.rst_persist := '1';
apbcontrol.status_value(3 downto 0) <= "0100";
apbcontrol.status_en <= '1'; -- Write Status Register
apbcontrol.control_clr <= '1'; -- Clear Control Register
vfifo_in.waddress := (others=>'0');
vcdc_ahb.stop := '1';
when ICAP_ERROR =>
next_state <= IDLE_AHB;
regv.rst_persist := '1';
apbcontrol.status_value(3 downto 0) <= "1000";
apbcontrol.status_en <= '1'; -- Write Status Register
apbcontrol.control_clr <= '1'; -- Clear Control Register
vfifo_in.waddress := (others=>'0');
end case;
if (present_state/=IDLE_AHB) and (cdc_ahb.icap_errn='0') then
next_state <= ICAP_ERROR;
end if;
if (present_state/=IDLE_AHB) then
apbcontrol.timer_en <= '1'; -- Enable timer
rstact <= '1';
if dmao.Ready='1' then
regv.c_ready:=regv.c_ready-1;
end if;
if dmao.Grant='1' then
regv.c_grant:=regv.c_grant-1;
regv.address:=regv.address+4;
end if;
end if;
if (dmao.Fault or dmao.Retry)='1' then
next_state <= BUS_CNTL_ERROR;
vcdc_ahb.stop := '1';
end if;
-- write fifo
if fifo_in.wen = '1' then
vfifo_in.waddress := vfifo_in.waddress +1;
end if;
gray_encoder(vfifo_in.waddress,vfifo_in.waddress_gray);
-- latched fifo write address
fifo_in.waddress <= vfifo_in.waddress;
fifo_in.waddress_gray <= vfifo_in.waddress_gray;
-- update fifo full
fifo_in.full <= vfifo_in.full;
-- reconfigurable modules synchrounous reset generation (active high)
for i in 0 to 31 loop
regv.rm_reset(i) := not(rstn) or (apbregi.rm_reset(i) and (rstact or regv.rst_persist));
end loop;
-- registers assignment
cdc_ahb.start <= vcdc_ahb.start;
cdc_ahb.stop <= vcdc_ahb.stop;
regin <= regv;
end process;
ahbreg: process(clkm,rstn)
begin
if rstn='0' then
regfifo_in.waddress <= (others =>'0');
regfifo_in.waddress_gray <= (others =>'0');
rcdc_ahb.start <= '0';
rcdc_ahb.stop <= '0';
present_state <= IDLE_AHB;
reg.rm_reset <= (others=>'0');
reg.c_grant <= (others=>'0');
reg.c_ready <= (others=>'0');
reg.c_latency <= (others=>'0');
reg.address <= (others=>'0');
reg.rst_persist <= '0';
elsif rising_edge(clkm) then
regfifo_in <= fifo_in;
rcdc_ahb <= cdc_ahb;
present_state <= next_state;
reg <= regin;
end if;
end process;
-------------------------------
-- synchronization registers
-------------------------------
-- input d is already registered in the source clock domain
syn_gen0: for i in 0 to fifo_depth generate -- fifo addresses
syncreg_inst0: syncreg generic map (tech => technology, stages => 2)
port map(clk => clk100, d => regfifo_in.waddress_gray(i), q => waddr_sync(i));
syncreg_inst1: syncreg generic map (tech => technology, stages => 2)
port map(clk => clkm, d => regfifo_out.raddress_gray(i), q => raddr_sync(i));
end generate;
-- CDC control signals
syncreg_inst2: syncreg generic map (tech => technology, stages => 2)
port map(clk => clkm, d => rcdc_icap.icap_errn, q => cdc_ahb.icap_errn);
syncreg_inst3: syncreg generic map (tech => technology, stages => 2)
port map(clk => clkm, d => rcdc_icap.icap_end, q => cdc_ahb.icap_end);
syncreg_inst4: syncreg generic map (tech => technology, stages => 2)
port map(clk => clk100, d => rcdc_ahb.start, q => cdc_icap.start);
syncreg_inst5: syncreg generic map (tech => technology, stages => 2)
port map(clk => clk100, d => rcdc_ahb.stop, q => cdc_icap.stop);
-------------------------------
-- icap clock domain
-------------------------------
icapcomb: process(waddr_sync, regfifo_out, fifo_out, cdc_icap, pstate, regicap, icapo)
variable vfifo_out : ofifo_type;
variable vcdc_icap : cdc_async;
variable vregicap : regs_icap;
begin
icapi.cen <= '1';
icapi.wen <= '1';
vcdc_icap.icap_end := '0';
vcdc_icap.icap_errn := '1';
vregicap := regicap;
-- initialize fifo signals
vfifo_out.raddress := regfifo_out.raddress;
vfifo_out.empty := '0';
vfifo_out.ren := '0';
-- fifo empty generation
gray_encoder(vfifo_out.raddress,vfifo_out.raddress_gray);
if (vfifo_out.raddress_gray=waddr_sync) then
vfifo_out.empty := '1';
end if;
case pstate is
when IDLE =>
if (cdc_icap.start='1') then
nstate <= START;
else
nstate <= IDLE;
end if;
when START =>
if (fifo_out.empty='0') then
vfifo_out.ren := '1';
nstate <= READ_LENGTH;
else
nstate <= START;
end if;
icapi.wen <= '0';
when READ_LENGTH =>
nstate <= WRITE_ICAP;
vregicap.c_bitstream := fifo_out.odata(19 downto 0);
if (fifo_out.empty='0') then
vfifo_out.ren := '1';
end if;
icapi.wen <= '0';
when WRITE_ICAP =>
if (icapo.odata(7) = '1') then -- if the ICAP is correctly initialized, then monitor ICAP status
nstate <= WRITE_ICAP_VERIFY;
elsif (vregicap.c_bitstream=0) then
nstate <= ICAP_ERROR_LATENCY;
elsif (fifo_out.empty='0') then
nstate <= WRITE_ICAP;
vfifo_out.ren := '1';
else
nstate <= WRITE_ICAP;
end if;
icapi.wen <= '0';
icapi.cen <= not(regfifo_out.ren); --1 cycle latency with respect to fifo_out.ren
when WRITE_ICAP_VERIFY =>
if (icapo.odata(7) = '0') then -- verify ICAP status for configuration errors
nstate <= ABORT;
vcdc_icap.icap_errn:='0'; -- signal icap error to the ahb clock domain
elsif (vregicap.c_bitstream=0) then
nstate <= ICAP_ERROR_LATENCY;
elsif (fifo_out.empty='0') then
nstate <= WRITE_ICAP_VERIFY;
vfifo_out.ren := '1';
else
nstate <= WRITE_ICAP_VERIFY;
end if;
icapi.wen <= '0';
icapi.cen <= not(regfifo_out.ren); --1 cycle latency with respect to fifo_out.ren
when END_CONFIG =>
nstate <= IDLE;
vfifo_out.raddress := (others=>'0');
vcdc_icap.icap_end := '1';
when ABORT =>
if (vregicap.c_latency=4) then
nstate <= IDLE;
vregicap.c_latency := (others=>'0');
else
nstate <= ABORT;
vregicap.c_latency := vregicap.c_latency+1;
end if;
icapi.cen <= '0'; -- continue abort sequence
vcdc_icap.icap_errn:='0'; -- signal icap error to the ahb clock domain
vfifo_out.raddress := (others=>'0');
when ICAP_ERROR_LATENCY =>
if (icapo.odata(7) = '0') then -- verify ICAP status for configuration errors
nstate <= ABORT;
vregicap.c_latency := (others=>'0');
vcdc_icap.icap_errn:='0'; -- signal icap error to the ahb clock domain
elsif (vregicap.c_latency=4) then
nstate <= END_CONFIG;
vregicap.c_latency := (others=>'0');
vcdc_icap.icap_end := '1';
else
nstate <= ICAP_ERROR_LATENCY;
vregicap.c_latency := vregicap.c_latency+1;
end if;
icapi.wen <= '0';
end case;
if (cdc_icap.stop='1') then
nstate <= ABORT;
vregicap.c_latency := (others=>'0');
vfifo_out.ren := '1';
end if;
-- read fifo
if vfifo_out.ren = '1' then
vfifo_out.raddress := vfifo_out.raddress +1;
end if;
if regfifo_out.ren = '1' then
vregicap.c_bitstream := vregicap.c_bitstream -1; -- because fifo introduces 1-cycle latency on output data
end if;
-- latched fifo read address
fifo_out.raddress <= vfifo_out.raddress;
fifo_out.raddress_gray <= vfifo_out.raddress_gray;
-- update fifo empty
fifo_out.empty <= vfifo_out.empty;
cdc_icap.icap_errn <= vcdc_icap.icap_errn;
cdc_icap.icap_end <= vcdc_icap.icap_end;
reginicap <= vregicap;
fifo_out.ren <= vfifo_out.ren;
end process;
icapreg: process(clk100,rstn)
begin
if rstn='0' then
regfifo_out.raddress <= (others =>'0');
regfifo_out.raddress_gray <= (others =>'0');
regfifo_out.ren <= '0';
regicap.c_bitstream <= (others =>'0');
regicap.c_latency <= (others =>'0');
rcdc_icap.start <= '0';
rcdc_icap.stop <= '0';
elsif rising_edge(clk100) then
regfifo_out <= fifo_out;
pstate <= nstate;
regicap <= reginicap;
rcdc_icap <= cdc_icap;
end if;
end process;
ram0 : syncram_2p generic map ( tech => technology, abits => fifo_depth, dbits => 32, sepclk => 1) -- 2**fifo_depth 32-bit data RAM
port map (clk100, fifo_out.ren, fifo_out.raddress(fifo_depth-1 downto 0), fifo_out.odata, clkm, fifo_in.wen, fifo_in.waddress(fifo_depth-1 downto 0), fifo_in.idata);
end async_dprc_rtl;
| gpl-3.0 | 6007967af8a8e6b348549a0fd1a2bdf0 | 0.587837 | 3.74211 | false | false | false | false |
pwsoft/fpga_examples | quartus/chameleon/chameleon1_gigatron/chameleon1_gigatron.vhd | 1 | 9,419 | -- -----------------------------------------------------------------------
--
-- Turbo Chameleon
--
-- Multi purpose FPGA expansion for the Commodore 64 computer
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2021 by Peter Wendrich ([email protected])
-- http://www.syntiac.com/chameleon.html
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
--
-- Part of the Gigatron emulator.
-- Toplevel for Chameleon V1 hardware.
--
-- -----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- -----------------------------------------------------------------------
architecture rtl of chameleon1 is
-- System settings
constant clk_ticks_per_usec : integer := 100;
constant resetCycles : integer := 255;
-- Clocks
signal sysclk : std_logic;
signal clk_150 : std_logic;
-- Clocks enables
signal ena_1mhz : std_logic;
signal ena_1khz : std_logic;
-- System control signals
signal reset_btn : std_logic;
signal reset : std_logic;
signal reset_trig : std_logic;
signal reboot_trig : std_logic;
signal no_clock : std_logic;
signal docking_station : std_logic;
signal ir : std_logic;
-- SPI controller
signal flash_cs_n : std_logic;
signal spi_req : std_logic;
signal spi_ack : std_logic;
signal spi_d : unsigned(7 downto 0);
signal spi_q : unsigned(7 downto 0);
-- PHI 2
signal phi : std_logic;
signal phi_mode : std_logic;
signal phi_cnt : unsigned(7 downto 0);
signal end_of_phi_0 : std_logic;
signal end_of_phi_1 : std_logic;
signal phi_post_1 : std_logic;
signal phi_post_2 : std_logic;
signal phi_post_3 : std_logic;
signal phi_post_4 : std_logic;
-- LEDs
signal led_green : std_logic;
signal led_red : std_logic;
-- PS/2 Keyboard
signal ps2_keyboard_clk_in : std_logic;
signal ps2_keyboard_dat_in : std_logic;
signal ps2_keyboard_clk_out : std_logic;
signal ps2_keyboard_dat_out : std_logic;
-- PS/2 Mouse
signal ps2_mouse_clk_in: std_logic;
signal ps2_mouse_dat_in: std_logic;
signal ps2_mouse_clk_out: std_logic;
signal ps2_mouse_dat_out: std_logic;
-- USB debugging
signal usart_rx : std_logic;
signal usb_remote_reset : std_logic;
signal reconfig_request : std_logic;
signal reconfig_slot : unsigned(3 downto 0);
signal flashslot : unsigned(4 downto 0);
signal usb_req : std_logic;
signal usb_ack : std_logic;
signal usb_we : std_logic;
signal usb_a : unsigned(31 downto 0);
signal usb_d : unsigned(7 downto 0);
signal usb_q : unsigned(7 downto 0);
-- Docking station
signal docking_joystick1 : unsigned(6 downto 0);
signal docking_joystick2 : unsigned(6 downto 0);
signal docking_joystick3 : unsigned(6 downto 0);
signal docking_joystick4 : unsigned(6 downto 0);
signal docking_keys : unsigned(63 downto 0);
signal docking_restore_n : std_logic;
-- Audio output (sigma delta)
signal audio : std_logic;
begin
sigma_l <= audio;
sigma_r <= audio;
-- -----------------------------------------------------------------------
-- Clocks and PLL
-- -----------------------------------------------------------------------
pllInstance : entity work.pll8
port map (
inclk0 => clk8m,
c0 => sysclk,
c1 => ram_clk,
c2 => open,
c3 => open,
locked => open
);
-- -----------------------------------------------------------------------
-- 1 Mhz and 1 Khz clocks
-- -----------------------------------------------------------------------
my1Mhz : entity work.chameleon_1mhz
generic map (
clk_ticks_per_usec => 100
)
port map (
clk => sysclk,
ena_1mhz => ena_1mhz,
ena_1mhz_2 => open
);
my1Khz : entity work.chameleon_1khz
port map (
clk => sysclk,
ena_1mhz => ena_1mhz,
ena_1khz => ena_1khz
);
-- -----------------------------------------------------------------------
-- Reset
-- -----------------------------------------------------------------------
reset_blk : block
signal reset_request : std_logic;
begin
reset_inst : entity work.gen_reset
generic map (
resetCycles => resetCycles
)
port map (
clk => sysclk,
enable => ena_1khz,
button => reset_request,
reset => reset
);
reset_request <= reset_trig or usb_remote_reset;
end block;
-- -----------------------------------------------------------------------
-- Gigatron entity
-- -----------------------------------------------------------------------
gigatron_top_blk : block
signal hsync : std_logic;
signal vsync : std_logic;
begin
gigatron_top_inst : entity work.gigatron_top
generic map (
clk_ticks_per_usec => clk_ticks_per_usec
)
port map (
clk => sysclk,
reset => reset,
flashslot => flashslot,
-- SPI interface
spi_cs_n => flash_cs_n,
spi_req => spi_req,
spi_ack => spi_ack,
spi_d => spi_d,
spi_q => spi_q,
-- SDRAM interface
ram_data => ram_d,
ram_addr => ram_a,
ram_ba => ram_ba,
ram_we => ram_we,
ram_ras => ram_ras,
ram_cas => ram_cas,
ram_ldqm => ram_ldqm,
ram_udqm => ram_udqm,
-- Keyboard and joystick
ps2_keyboard_clk_in => ps2_keyboard_clk_in,
ps2_keyboard_dat_in => ps2_keyboard_dat_in,
ps2_keyboard_clk_out => ps2_keyboard_clk_out,
ps2_keyboard_dat_out => ps2_keyboard_dat_out,
joystick => docking_joystick1,
-- LEDs
led_green => led_green,
led_red => led_red,
-- Audio
audio => audio,
-- Video
red => red,
grn => grn,
blu => blu,
hsync => hsync,
vsync => vsync
);
hsync_n <= not hsync;
vsync_n <= not vsync;
end block;
-- -----------------------------------------------------------------------
-- Button debounce
-- -----------------------------------------------------------------------
chameleon_buttons_inst : entity work.chameleon_buttons
port map (
clk => sysclk,
ena_1khz => ena_1khz,
menu_mode => '0',
button_l => (not usart_cts),
button_m => (not freeze_btn),
button_r => (not reset_btn),
button_config => X"0",
reset => reset_trig,
boot => reboot_trig,
freeze => open,
menu => open
);
-- -----------------------------------------------------------------------
-- USB communication
-- -----------------------------------------------------------------------
usb_inst : entity work.chameleon_usb
generic map (
remote_reset_enabled => true
)
port map (
clk => sysclk,
req => usb_req,
ack => usb_ack,
we => usb_we,
a => usb_a,
d => usb_d,
q => usb_q,
reconfig => reboot_trig,
reconfig_slot => X"0",
flashslot => flashslot,
serial_clk => usart_clk,
serial_rxd => usart_tx,
serial_txd => usart_rx,
serial_cts_n => usart_rts,
remote_reset => usb_remote_reset
);
usb_ack <= usb_req;
-- -----------------------------------------------------------------------
-- Chameleon I/O
-- -----------------------------------------------------------------------
chameleon_io_inst : entity work.chameleon_io
generic map (
enable_docking_station => true,
enable_cdtv_remote => true,
enable_c64_joykeyb => true,
enable_c64_4player => false,
enable_raw_spi => false
)
port map (
-- Clocks
clk => sysclk,
clk_mux => sysclk,
ena_1mhz => ena_1mhz,
reset => reset,
no_clock => no_clock,
docking_station => docking_station,
-- Chameleon FPGA pins
-- C64 Clocks
phi2_n => phi2_n,
dotclock_n => dotclk_n,
-- C64 cartridge control lines
io_ef_n => ioef,
rom_lh_n => romlh,
-- SPI bus
spi_miso => spi_miso,
-- CPLD multiplexer
mux_clk => mux_clk,
mux => mux,
mux_d => mux_d,
mux_q => mux_q,
-- USB microcontroller (To RX of micro)
to_usb_rx => usart_rx,
-- SPI chip-selects
mmc_cs_n => '1',
flash_cs_n => flash_cs_n,
rtc_cs => '0',
-- SPI controller (enable_raw_spi must be set to false)
spi_speed => '1', -- select fast speed for flash access
spi_req => spi_req,
spi_ack => spi_ack,
spi_d => spi_d,
spi_q => spi_q,
-- LEDs
led_green => led_green,
led_red => led_red,
ir => ir,
-- PS/2 Keyboard
ps2_keyboard_clk_out => ps2_keyboard_clk_out,
ps2_keyboard_dat_out => ps2_keyboard_dat_out,
ps2_keyboard_clk_in => ps2_keyboard_clk_in,
ps2_keyboard_dat_in => ps2_keyboard_dat_in,
-- PS/2 Mouse
ps2_mouse_clk_out => ps2_mouse_clk_out,
ps2_mouse_dat_out => ps2_mouse_dat_out,
ps2_mouse_clk_in => ps2_mouse_clk_in,
ps2_mouse_dat_in => ps2_mouse_dat_in,
-- Buttons
button_reset_n => reset_btn,
-- Joysticks
joystick1 => docking_joystick1,
joystick2 => docking_joystick2,
joystick3 => docking_joystick3,
joystick4 => docking_joystick4,
-- Keyboards
keys => docking_keys,
restore_key_n => docking_restore_n
);
end architecture;
| lgpl-2.1 | 97d7aa3b11316a01a445d0ad62ae7b97 | 0.544962 | 3.207014 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/pci/pcitrace/pcitrace.vhd | 1 | 7,763 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pcitrace
-- File: pcitrace.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: PCI trace buffer
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.pci.all;
entity pcitrace is
generic (
depth : integer range 6 to 12 := 8;
iregs : integer := 1;
memtech : integer := DEFMEMTECH;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#f00#
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
pciclk : in std_ulogic;
pcii : in pci_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end;
architecture rtl of pcitrace is
constant REVISION : amba_version_type := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_PCITRACE, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
type reg_type is record
sample : std_ulogic;
armed : std_ulogic;
busy : std_ulogic;
timeout : std_logic_vector(depth-1 downto 0);
admask : std_logic_vector(31 downto 0);
adpattern : std_logic_vector(31 downto 0);
sigmask : std_logic_vector(15 downto 0);
sigpattern : std_logic_vector(15 downto 0);
count : std_logic_vector(7 downto 0);
end record;
type pci_reg_type is record
sample : std_ulogic;
armed : std_ulogic;
sync : std_ulogic;
start : std_ulogic;
timeout : std_logic_vector(depth-1 downto 0);
baddr : std_logic_vector(depth-1 downto 0);
count : std_logic_vector(7 downto 0);
end record;
signal r, rin : reg_type;
signal csad, csctrl : std_ulogic;
signal pr, prin : pci_reg_type;
signal bufout : std_logic_vector(47 downto 0);
signal pciad : std_logic_vector(31 downto 0);
signal vcc : std_ulogic;
signal pcictrlin, pcictrl : std_logic_vector(15 downto 0);
begin
vcc <= '1';
comb: process(pcii, apbi, rst, r, pr, bufout)
variable v : reg_type;
variable rdata : std_logic_vector(31 downto 0);
variable paddr : std_logic_vector(3 downto 0);
variable vcsad, vcssig : std_ulogic;
begin
v := r; vcsad := '0'; vcssig := '0'; rdata := (others => '0');
v.sample := r.armed and not pr.armed; v.busy := pr.sample;
if (r.sample and pr.armed) = '1' then v.armed := '0'; end if;
--registers
paddr := apbi.paddr(15) & apbi.paddr(4 downto 2);
if apbi.penable = '1' then
if (apbi.pwrite and apbi.psel(pindex)) = '1' then
case paddr is
when "0000" => v.admask := apbi.pwdata;
when "0001" => v.sigmask := apbi.pwdata(15 downto 0);
when "0010" => v.adpattern := apbi.pwdata;
when "0011" => v.sigpattern := apbi.pwdata(15 downto 0);
when "0100" => v.timeout := apbi.pwdata(depth-1 downto 0);
when "0101" => v.armed := '1';
when "0111" => v.count := apbi.pwdata(7 downto 0);
when others =>
if apbi.paddr(15 downto 14) = "10" then vcsad := '1';
elsif apbi.paddr(15 downto 14) = "11" then vcssig := '1'; end if;
end case;
end if;
case paddr is
when "0000" => rdata := r.admask;
when "0001" => rdata(15 downto 0) := r.sigmask;
when "0010" => rdata := r.adpattern;
when "0011" => rdata(15 downto 0) := r.sigpattern;
when "0100" => rdata(depth-1 downto 0) := r.timeout;
when "0101" => rdata(0) := r.busy;
when "0110" => rdata(3 downto 0) := conv_std_logic_vector(depth, 4);
when "0111" =>
rdata(depth-1+16 downto 16) := pr.baddr;
rdata(15 downto 0) := pr.count & r.count;
when others =>
if apbi.paddr(15 downto 14) = "10" then
vcsad := '1'; rdata := bufout(31 downto 0);
elsif apbi.paddr(15 downto 14) = "11" then
vcssig := '1'; rdata(15 downto 0) := bufout(47 downto 32);
end if;
end case;
end if;
if rst = '0' then
v.sample := '0'; v.armed := '0'; v.admask := (others => '0');
v.sigmask := (others => '0'); v.adpattern := (others => '0');
v.sigpattern := (others => '0'); v.timeout := (others => '0');
end if;
csad <= vcsad; csctrl <= vcssig; apbo.prdata <= rdata; rin <= v;
end process;
comb2 : process(r, pr, pciclk, pcii, pcictrl, rst)
variable v : pci_reg_type;
constant z : std_logic_vector(47 downto 0) := (others => '0');
begin
v := pr; v.sync := (r.sample and not pr.armed);
if (pr.sample = '1') then
v.baddr := pr.baddr + 1;
if ((((pcii.ad & pcictrl) xor (r.adpattern & r.sigpattern)) and (r.admask & r.sigmask)) = z) then
if pr.count = "00000000" then v.start := '0';
else v.count := pr.count -1; end if;
end if;
if (pr.start = '0') then
v.timeout := pr.timeout - 1;
if (v.timeout(depth-1) and not pr.timeout(depth-1)) = '1' then
v.sample := '0'; v.armed := '0';
end if;
end if;
end if;
if pr.sync = '1' then
v.start := '1'; v.sample := '1'; v.armed := '1';
v.timeout := r.timeout; v.count := r.count;
end if;
if rst = '0' then
v.sample := '0'; v.armed := '0'; v.start := '0';
v.timeout := (others => '0'); v.baddr := (others => '0');
v.count := (others => '0');
end if;
prin <= v;
end process ;
pcictrlin <= pcii.rst & pcii.idsel & pcii.frame & pcii.trdy & pcii.irdy &
pcii.devsel & pcii.gnt & pcii.stop & pcii.lock & pcii.perr &
pcii.serr & pcii.par & pcii.cbe;
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
apbo.pirq <= (others => '0');
seq: process (clk)
begin
if clk'event and clk = '1' then r <= rin; end if;
end process seq;
pseq: process (pciclk)
begin
if pciclk'event and pciclk = '1' then pr <= prin; end if;
end process ;
ir : if iregs = 1 generate
pseq: process (pciclk)
begin
if pciclk'event and pciclk = '1' then
pcictrl <= pcictrlin; pciad <= pcii.ad;
end if;
end process ;
end generate;
noir : if iregs = 0 generate
pcictrl <= pcictrlin; pciad <= pcii.ad;
end generate;
admem : syncram_2p generic map (tech => memtech, abits => depth, dbits => 32, sepclk => 1)
port map (clk, csad, apbi.paddr(depth+1 downto 2), bufout(31 downto 0),
pciclk, pr.sample, pr.baddr, pciad);
ctrlmem : syncram_2p generic map (tech => memtech, abits => depth, dbits => 16, sepclk => 1)
port map (clk, csctrl, apbi.paddr(depth+1 downto 2), bufout(47 downto 32),
pciclk, pr.sample, pr.baddr, pcictrl);
end;
| gpl-3.0 | 4126a2b359f0e599263c2b13db80083d | 0.578256 | 3.336055 | false | false | false | false |
pwsoft/fpga_examples | rtl/ttl/ttl_7430.vhd | 1 | 1,833 | -- -----------------------------------------------------------------------
--
-- Syntiac VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2018 by Peter Wendrich ([email protected])
-- http://www.syntiac.com
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
-- 8-input NAND gate
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.ttl_pkg.all;
-- -----------------------------------------------------------------------
entity ttl_7430 is
generic (
latency : integer := 1
);
port (
emuclk : in std_logic;
p1 : in ttl_t;
p2 : in ttl_t;
p3 : in ttl_t;
p4 : in ttl_t;
p5 : in ttl_t;
p6 : in ttl_t;
p11 : in ttl_t;
p12 : in ttl_t;
p8 : out ttl_t
);
end entity;
architecture rtl of ttl_7430 is
signal p8_loc : ttl_t;
begin
p8_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p8_loc, q => p8);
p8_loc <= not(p1 and p2 and p3 and p4 and p5 and p6 and p11 and p12);
end architecture;
| lgpl-2.1 | 8b0232ce96c67fd4bec543cb465edd44 | 0.545554 | 3.629703 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/memctrl/ftsrctrl.in.vhd | 1 | 1,006 | -- PROM/SRAM controller
constant CFG_SRCTRLFT : integer := CONFIG_SRCTRLFT;
constant CFG_SRCTRLFT_APBEN : integer := CONFIG_SRCTRLFT_APBEN;
constant CFG_SRCTRLFT_PROMWS : integer := CONFIG_SRCTRLFT_PROMWS;
constant CFG_SRCTRLFT_RAMWS : integer := CONFIG_SRCTRLFT_RAMWS;
constant CFG_SRCTRLFT_IOWS : integer := CONFIG_SRCTRLFT_IOWS;
constant CFG_SRCTRLFT_RMW : integer := CONFIG_SRCTRLFT_RMW;
constant CFG_SRCTRLFT_EDAC : integer := CONFIG_SRCTRLFT_EDAC;
constant CFG_SRCTRLFT_NETLIST : integer := CONFIG_SRCTRLFT_NETLIST;
constant CFG_SRCTRLFT_8BIT : Integer := CONFIG_SRCTRLFT_8BIT;
constant CFG_SRCTRLFT_SRBANKS : Integer := CFG_SR_CTRLFT_SRBANKS;
constant CFG_SRCTRLFT_BANKSZ : Integer := CFG_SR_CTRLFT_BANKSZ;
constant CFG_SRCTRLFT_ROMBANKS : Integer := CFG_SR_CTRLFT_ROMBANKS;
constant CFG_SRCTRLFT_ROMBANKSZ : Integer := CFG_SR_CTRLFT_ROMBANKSZ;
constant CFG_SRCTRLFT_ROMBANKSZDEF : Integer := CFG_SR_CTRLFT_ROMBANKSZDEF;
| gpl-3.0 | 22cc168301d918c3f490ff2167cb7f9b | 0.718688 | 3.353333 | false | true | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/leon3v3/leon3sh.vhd | 1 | 6,893 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: leon3sh
-- File: leon3sh.vhd
-- Author: Jan Andersson, Aeroflex Gaisler
-- Description: Top-level LEON3 component
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
entity leon3sh is
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 63 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
cached : integer := 0; -- cacheability table
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0;
rex : integer range 0 to 1 := 0;
altwin : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
fpui : out grfpu_in_type;
fpuo : in grfpu_out_type
);
end;
architecture rtl of leon3sh is
signal gnd, vcc : std_logic;
begin
gnd <= '0'; vcc <= '1';
leon3x0 : leon3x
generic map (
hindex => hindex,
fabtech => fabtech,
memtech => memtech,
nwindows => nwindows,
dsu => dsu,
fpu => fpu,
v8 => v8,
cp => cp,
mac => mac,
pclow => pclow,
notag => notag,
nwp => nwp,
icen => icen,
irepl => irepl,
isets => isets,
ilinesize => ilinesize,
isetsize => isetsize,
isetlock => isetlock,
dcen => dcen,
drepl => drepl,
dsets => dsets,
dlinesize => dlinesize,
dsetsize => dsetsize,
dsetlock => dsetlock,
dsnoop => dsnoop,
ilram => ilram,
ilramsize => ilramsize,
ilramstart => ilramstart,
dlram => dlram,
dlramsize => dlramsize,
dlramstart => dlramstart,
mmuen => mmuen,
itlbnum => itlbnum,
dtlbnum => dtlbnum,
tlb_type => tlb_type,
tlb_rep => tlb_rep,
lddel => lddel,
disas => disas,
tbuf => tbuf,
pwd => pwd,
svt => svt,
rstaddr => rstaddr,
smp => smp,
iuft => 0,
fpft => 0,
cmft => 0,
iuinj => 0,
ceinj => 0,
cached => cached,
clk2x => 0,
netlist => 0,
scantest => scantest,
mmupgsz => mmupgsz,
bp => bp,
npasi => npasi,
pwrpsr => pwrpsr,
rex => rex,
altwin => altwin)
port map (
clk => gnd,
gclk2 => clk,
gfclk2 => clk,
clk2 => clk,
rstn => rstn,
ahbi => ahbi,
ahbo => ahbo,
ahbsi => ahbsi,
ahbso => ahbso,
irqi => irqi,
irqo => irqo,
dbgi => dbgi,
dbgo => dbgo,
fpui => fpui,
fpuo => fpuo,
clken => vcc
);
end;
| gpl-3.0 | a47e1baa49cfd0e3a78ef1a6195c6a4a | 0.464384 | 3.975202 | false | false | false | false |
hoglet67/CoPro6502 | src/T6502/T65_Pack.vhd | 1 | 5,969 | -- ****
-- T65(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 303 ost(ML) July 2014
-- "magic" constants converted to vhdl types
-- Ver 300 Bugfixes by ehenciak added
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- 65xx compatible microprocessor core
--
-- Version : 0246
--
-- Copyright (c) 2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t65/
--
-- Limitations :
--
-- File history :
--
library IEEE;
use IEEE.std_logic_1164.all;
package T65_Pack is
constant Flag_C : integer := 0;
constant Flag_Z : integer := 1;
constant Flag_I : integer := 2;
constant Flag_D : integer := 3;
constant Flag_B : integer := 4;
constant Flag_1 : integer := 5;
constant Flag_V : integer := 6;
constant Flag_N : integer := 7;
type T_Set_BusA_To is
(
Set_BusA_To_DI,
Set_BusA_To_ABC,
Set_BusA_To_X,
Set_BusA_To_Y,
Set_BusA_To_S,
Set_BusA_To_P,
Set_BusA_To_DONTCARE
);
type T_Set_Addr_To is
(
Set_Addr_To_S,
Set_Addr_To_AD,
Set_Addr_To_PBR,
Set_Addr_To_BA
);
type T_Write_Data is
(
Write_Data_DL,
Write_Data_ABC,
Write_Data_X,
Write_Data_Y,
Write_Data_S,
Write_Data_P,
Write_Data_PCL,
Write_Data_PCH,
Write_Data_DONTCARE
);
type T_ALU_OP is
(
ALU_OP_OR, --"0000"
ALU_OP_AND, --"0001"
ALU_OP_EOR, --"0010"
ALU_OP_ADC, --"0011"
ALU_OP_EQ1, --"0100" EQ1 does not change N,Z flags, EQ2/3 does.
ALU_OP_EQ2, --"0101"Not sure yet whats the difference between EQ2&3. They seem to do the same ALU op
ALU_OP_CMP, --"0110"
ALU_OP_SBC, --"0111"
ALU_OP_ASL, --"1000"
ALU_OP_ROL, --"1001"
ALU_OP_LSR, --"1010"
ALU_OP_ROR, --"1011"
ALU_OP_BIT, --"1100"
ALU_OP_EQ3, --"1101"
ALU_OP_DEC, --"1110"
ALU_OP_INC, --"1111"
ALU_OP_UNDEF--"----"--may be replaced with any?
);
component T65_MCode
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816
IR : in std_logic_vector(7 downto 0);
MCycle : in std_logic_vector(2 downto 0);
P : in std_logic_vector(7 downto 0);
LCycle : out std_logic_vector(2 downto 0);
ALU_Op : out T_ALU_Op;
Set_BusA_To : out T_Set_BusA_To;-- DI,A,X,Y,S,P
Set_Addr_To : out T_Set_Addr_To;-- PC Adder,S,AD,BA
Write_Data : out T_Write_Data;-- DL,A,X,Y,S,P,PCL,PCH
Jump : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel
BAAdd : out std_logic_vector(1 downto 0); -- None,DB Inc,BA Add,BA Adj
BreakAtNA : out std_logic;
ADAdd : out std_logic;
AddY : out std_logic;
PCAdd : out std_logic;
Inc_S : out std_logic;
Dec_S : out std_logic;
LDA : out std_logic;
LDP : out std_logic;
LDX : out std_logic;
LDY : out std_logic;
LDS : out std_logic;
LDDI : out std_logic;
LDALU : out std_logic;
LDAD : out std_logic;
LDBAL : out std_logic;
LDBAH : out std_logic;
SaveP : out std_logic;
ALUmore : out std_logic;
Write : out std_logic
);
end component;
component T65_ALU
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816
Op : in T_ALU_Op;
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
P_In : in std_logic_vector(7 downto 0);
P_Out : out std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0)
);
end component;
end;
| gpl-3.0 | f844548e706f0dcf8362cea893423e53 | 0.572458 | 3.428489 | false | false | false | false |
ARC-Lab-UF/UAA | src/delay.vhd | 1 | 2,887 | -- Copyright (c) 2015 University of Florida
--
-- This file is part of uaa.
--
-- uaa is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- uaa is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with uaa. If not, see <http://www.gnu.org/licenses/>.
-- Greg Stitt
-- University of Florida
--
-- Entity: delay
-- Description: This entity delays an input by a specified number of cycles,
-- while also allowing stalls and specific output values on reset.
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Generic Descriptions
-- cycles : The length of the delay in cycles (required)
-- width : The width of the input signal (required)
-- init : An initial value (of width bits) for the first "cycles" output
-- after a reset (required)
-------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Port Description
-- clk : clock
-- rst : reset
-- en : enable (active high), '0' stalls the delay pipeline
-- input : The input to be delayed
-- output : The input after "cycles" pass (assuming no stalls from en='0')
-------------------------------------------------------------------------------
entity delay is
generic(cycles : natural;
width : positive;
init : std_logic_vector);
port( clk : in std_logic;
rst : in std_logic;
en : in std_logic;
input : in std_logic_vector(width-1 downto 0);
output : out std_logic_vector(width-1 downto 0));
end delay;
architecture FF of delay is
type reg_array is array (0 to cycles-1) of std_logic_vector(width-1 downto 0);
signal regs : reg_array;
begin -- BHV
U_CYCLES_GT_0 : if cycles > 0 generate
process(clk, rst)
begin
if (rst = '1') then
for i in 0 to cycles-1 loop
regs(i) <= init;
end loop;
elsif (clk'event and clk = '1') then
if (en = '1') then
regs(0) <= input;
end if;
for i in 0 to cycles-2 loop
if (en = '1') then
regs(i+1) <= regs(i);
end if;
end loop;
end if;
end process;
output <= regs(cycles-1);
end generate U_CYCLES_GT_0;
U_CYCLES_EQ_0 : if cycles = 0 generate
output <= input;
end generate U_CYCLES_EQ_0;
end FF;
| gpl-3.0 | 76183eccb0b42ace84876aaa44baf0aa | 0.559058 | 4.015299 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-altera-ep3c25/testbench.vhd | 1 | 10,980 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- Altera Cyclone-III LEON3 Demonstration design test bench
-- Copyright (C) 2007 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library cypress;
use cypress.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 8; -- rom data width (8/32)
romdepth : integer := 23; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 20; -- ram address depth
srambanks : integer := 1 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal clkout, pllref : std_ulogic;
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(25 downto 0);
signal data : std_logic_vector(31 downto 0);
signal romsn : std_ulogic;
signal iosn : std_ulogic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal dsuen, dsutx, dsurx, dsubren, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal error : std_logic;
signal gpio : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal ssram_cen : std_logic;
signal ssram_wen : std_logic;
signal ssram_bw : std_logic_vector (0 to 3);
signal ssram_oen : std_ulogic;
signal ssram_clk : std_ulogic;
signal ssram_adscn : std_ulogic;
signal ssram_adsp_n : std_ulogic;
signal ssram_adv_n : std_ulogic;
signal datazz : std_logic_vector(3 downto 0);
-- ddr memory
signal ddr_clk : std_logic;
signal ddr_clkb : std_logic;
signal ddr_clkin : std_logic;
signal ddr_cke : std_logic;
signal ddr_csb : std_logic;
signal ddr_web : std_ulogic; -- ddr write enable
signal ddr_rasb : std_ulogic; -- ddr ras
signal ddr_casb : std_ulogic; -- ddr cas
signal ddr_dm : std_logic_vector (1 downto 0); -- ddr dm
signal ddr_dqs : std_logic_vector (1 downto 0); -- ddr dqs
signal ddr_ad : std_logic_vector (12 downto 0); -- ddr address
signal ddr_ba : std_logic_vector (1 downto 0); -- ddr bank address
signal ddr_dq : std_logic_vector (15 downto 0); -- ddr data
signal plllock : std_ulogic;
signal txd1, rxd1 : std_ulogic;
--signal txd2, rxd2 : std_ulogic;
-- for smc lan chip
signal eth_aen : std_ulogic; -- for smsc eth
signal eth_readn : std_ulogic; -- for smsc eth
signal eth_writen : std_ulogic; -- for smsc eth
signal eth_nbe : std_logic_vector(3 downto 0); -- for smsc eth
signal eth_datacsn : std_ulogic;
constant lresp : boolean := false;
signal sa : std_logic_vector(14 downto 0);
signal sd : std_logic_vector(31 downto 0);
-- ATA signals
signal ata_rst : std_logic;
signal ata_data : std_logic_vector(15 downto 0);
signal ata_da : std_logic_vector(2 downto 0);
signal ata_cs0 : std_logic;
signal ata_cs1 : std_logic;
signal ata_dior : std_logic;
signal ata_diow : std_logic;
signal ata_iordy : std_logic;
signal ata_intrq : std_logic;
signal ata_dmack : std_logic;
signal cf_gnd_da : std_logic_vector(10 downto 3);
signal cf_atasel : std_logic;
signal cf_we : std_logic;
signal cf_power : std_logic;
signal cf_csel : std_logic;
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
ddr_clkin <= not clk after ct * 1 ns;
rst <= dsurst;
dsubren <= '1'; rxd1 <= '1';
address(0) <= '0';
-- ddr_dqs <= (others => 'L');
d3 : entity work.leon3mp generic map (fabtech, memtech, padtech, clktech,
ncpu, disas, dbguart, pclow )
port map (rst, clk, error,
address(25 downto 1), data, romsn, oen, writen, open,
ssram_cen, ssram_wen, ssram_bw, ssram_oen,
ssram_clk, ssram_adscn, iosn,
ddr_clk, ddr_clkb, ddr_cke, ddr_csb, ddr_web, ddr_rasb,
ddr_casb, ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
dsubren, dsuact, rxd1, txd1, gpio);
-- ddr0 : mt46v16m16
-- generic map (index => -1, fname => sdramfile)
-- port map(
-- Dq => ddr_dq(15 downto 0), Dqs => ddr_dqs(1 downto 0), Addr => ddr_ad,
-- Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke,
-- Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
-- Dm => ddr_dm(1 downto 0));
ddr0 : ddrram
generic map(width => 16, abits => 13, colbits => 9, rowbits => 13,
implbanks => 1, fname => sdramfile, density => 1)
port map (ck => ddr_clk, cke => ddr_cke, csn => ddr_csb,
rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web,
dm => ddr_dm, ba => ddr_ba, a => ddr_ad, dq => ddr_dq,
dqs => ddr_dqs);
datazz <= "HHHH";
ssram_adsp_n <= '1'; ssram_adv_n <= '1';
ssram0 : cy7c1380d generic map (fname => sramfile)
port map(
ioDq(35 downto 32) => datazz, ioDq(31 downto 0) => data,
iAddr => address(20 downto 2), iMode => gnd,
inGW => vcc, inBWE => ssram_wen, inADV => ssram_adv_n,
inADSP => ssram_adsp_n, inADSC => ssram_adscn,
iClk => ssram_clk,
inBwa => ssram_bw(3), inBwb => ssram_bw(2),
inBwc => ssram_bw(1), inBwd => ssram_bw(0),
inOE => ssram_oen, inCE1 => ssram_cen,
iCE2 => vcc, inCE3 => gnd, iZz => gnd);
-- 16 bit prom
prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile)
port map (address(romdepth downto 1), data(31 downto 16),
gnd, gnd, romsn, writen, oen);
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= buskeep(data), (others => 'H') after 250 ns;
sd <= buskeep(sd), (others => 'H') after 250 ns;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, oen, writen, open);
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
| gpl-3.0 | ba465ee8fdf5bd0dbde3912245eb2436 | 0.582149 | 3.061054 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/eth/wrapper/greth_gen.vhd | 1 | 13,910 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: greth_gen
-- File: greth_gen.vhd
-- Author: Marko Isomaki
-- Description: Generic Ethernet MAC
------------------------------------------------------------------------------
library ieee;
library grlib;
use ieee.std_logic_1164.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library eth;
use eth.ethcomp.all;
entity greth_gen is
generic(
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 64 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 31 := 0;
rmii : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 2 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
edclsepahbg : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
maxsize : integer;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--edcl ahb mst in
ehgrant : in std_ulogic;
ehready : in std_ulogic;
ehresp : in std_logic_vector(1 downto 0);
ehrdata : in std_logic_vector(31 downto 0);
--edcl ahb mst out
ehbusreq : out std_ulogic;
ehlock : out std_ulogic;
ehtrans : out std_logic_vector(1 downto 0);
ehaddr : out std_logic_vector(31 downto 0);
ehwrite : out std_ulogic;
ehsize : out std_logic_vector(2 downto 0);
ehburst : out std_logic_vector(2 downto 0);
ehprot : out std_logic_vector(3 downto 0);
ehwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--irq
irq : out std_logic;
--ethernet input signals
rmii_clk : in std_ulogic;
tx_clk : in std_ulogic;
tx_dv : in std_ulogic;
rx_clk : in std_ulogic;
rxd : in std_logic_vector(3 downto 0);
rx_dv : in std_ulogic;
rx_er : in std_ulogic;
rx_col : in std_ulogic;
rx_en : in std_ulogic;
rx_crs : in std_ulogic;
mdio_i : in std_ulogic;
phyrstaddr : in std_logic_vector(4 downto 0);
mdint : in std_ulogic;
--ethernet output signals
reset : out std_ulogic;
txd : out std_logic_vector(3 downto 0);
tx_en : out std_ulogic;
tx_er : out std_ulogic;
mdc : out std_ulogic;
mdio_o : out std_ulogic;
mdio_oe : out std_ulogic;
--scantest
testrst : in std_ulogic;
testen : in std_ulogic;
testoen : in std_ulogic;
edcladdr : in std_logic_vector(3 downto 0);
edclsepahb : in std_ulogic;
edcldisable : in std_ulogic;
speed : out std_ulogic
);
end entity;
architecture rtl of greth_gen is
function getfifosize(edcl, fifosize, ebufsize : in integer) return integer is
begin
if (edcl = 1) then
return ebufsize;
else
return fifosize;
end if;
end function;
constant fabits : integer := log2(fifosize);
type szvct is array (0 to 6) of integer;
constant ebuf : szvct := (64, 128, 128, 256, 256, 256, 256);
constant eabits : integer := log2(edclbufsz) + 8;
constant bufsize : std_logic_vector(2 downto 0) :=
conv_std_logic_vector(log2(edclbufsz), 3);
constant ebufsize : integer := ebuf(log2(edclbufsz));
constant txfifosize : integer := getfifosize(edcl, fifosize, ebufsize);
constant txfabits : integer := log2(txfifosize);
--rx ahb fifo
signal rxrenable : std_ulogic;
signal rxraddress : std_logic_vector(10 downto 0);
signal rxwrite : std_ulogic;
signal rxwdata : std_logic_vector(31 downto 0);
signal rxwaddress : std_logic_vector(10 downto 0);
signal rxrdata : std_logic_vector(31 downto 0);
--tx ahb fifo
signal txrenable : std_ulogic;
signal txraddress : std_logic_vector(10 downto 0);
signal txwrite : std_ulogic;
signal txwdata : std_logic_vector(31 downto 0);
signal txwaddress : std_logic_vector(10 downto 0);
signal txrdata : std_logic_vector(31 downto 0);
--edcl buf
signal erenable : std_ulogic;
signal eraddress : std_logic_vector(15 downto 0);
signal ewritem : std_ulogic;
signal ewritel : std_ulogic;
signal ewaddressm : std_logic_vector(15 downto 0);
signal ewaddressl : std_logic_vector(15 downto 0);
signal ewdata : std_logic_vector(31 downto 0);
signal erdata : std_logic_vector(31 downto 0);
begin
ethc0: grethc
generic map(
ifg_gap => ifg_gap,
attempt_limit => attempt_limit,
backoff_limit => backoff_limit,
mdcscaler => mdcscaler,
enable_mdio => enable_mdio,
fifosize => fifosize,
nsync => nsync,
edcl => edcl,
edclbufsz => edclbufsz,
macaddrh => macaddrh,
macaddrl => macaddrl,
ipaddrh => ipaddrh,
ipaddrl => ipaddrl,
phyrstadr => phyrstadr,
rmii => rmii,
oepol => oepol,
scanen => scanen,
mdint_pol => mdint_pol,
enable_mdint => enable_mdint,
multicast => multicast,
edclsepahbg => edclsepahbg,
ramdebug => ramdebug,
maxsize => maxsize,
gmiimode => gmiimode
)
port map(
rst => rst,
clk => clk,
--ahb mst in
hgrant => hgrant,
hready => hready,
hresp => hresp,
hrdata => hrdata,
--ahb mst out
hbusreq => hbusreq,
hlock => hlock,
htrans => htrans,
haddr => haddr,
hwrite => hwrite,
hsize => hsize,
hburst => hburst,
hprot => hprot,
hwdata => hwdata,
--edcl ahb mst in
ehgrant => ehgrant,
ehready => ehready,
ehresp => ehresp,
ehrdata => ehrdata,
--edcl ahb mst out
ehbusreq => ehbusreq,
ehlock => ehlock,
ehtrans => ehtrans,
ehaddr => ehaddr,
ehwrite => ehwrite,
ehsize => ehsize,
ehburst => ehburst,
ehprot => ehprot,
ehwdata => ehwdata,
--apb slv in
psel => psel,
penable => penable,
paddr => paddr,
pwrite => pwrite,
pwdata => pwdata,
--apb slv out
prdata => prdata,
--irq
irq => irq,
--rx ahb fifo
rxrenable => rxrenable,
rxraddress => rxraddress,
rxwrite => rxwrite,
rxwdata => rxwdata,
rxwaddress => rxwaddress,
rxrdata => rxrdata,
--tx ahb fifo
txrenable => txrenable,
txraddress => txraddress,
txwrite => txwrite,
txwdata => txwdata,
txwaddress => txwaddress,
txrdata => txrdata,
--edcl buf
erenable => erenable,
eraddress => eraddress,
ewritem => ewritem,
ewritel => ewritel,
ewaddressm => ewaddressm,
ewaddressl => ewaddressl,
ewdata => ewdata,
erdata => erdata,
--ethernet input signals
rmii_clk => rmii_clk,
tx_clk => tx_clk,
tx_dv => tx_dv,
rx_clk => rx_clk,
rxd => rxd(3 downto 0),
rx_dv => rx_dv,
rx_er => rx_er,
rx_col => rx_col,
rx_en => rx_en,
rx_crs => rx_crs,
mdio_i => mdio_i,
phyrstaddr => phyrstaddr,
mdint => mdint,
--ethernet output signals
reset => reset,
txd => txd(3 downto 0),
tx_en => tx_en,
tx_er => tx_er,
mdc => mdc,
mdio_o => mdio_o,
mdio_oe => mdio_oe,
--scantest
testrst => testrst,
testen => testen,
testoen => testoen,
edcladdr => edcladdr,
edclsepahb => edclsepahb,
edcldisable => edcldisable,
speed => speed);
-------------------------------------------------------------------------------
-- FIFOS ----------------------------------------------------------------------
-------------------------------------------------------------------------------
nft : if ft = 0 generate
tx_fifo0 : syncram_2p generic map(tech => memtech, abits => txfabits,
dbits => 32, sepclk => 0)
port map(clk, txrenable, txraddress(txfabits-1 downto 0), txrdata, clk,
txwrite, txwaddress(txfabits-1 downto 0), txwdata);
rx_fifo0 : syncram_2p generic map(tech => memtech, abits => fabits,
dbits => 32, sepclk => 0)
port map(clk, rxrenable, rxraddress(fabits-1 downto 0), rxrdata, clk,
rxwrite, rxwaddress(fabits-1 downto 0), rxwdata);
end generate;
ft1 : if ft /= 0 generate
tx_fifo0 : syncram_2pft generic map(tech => memtech, abits => txfabits,
dbits => 32, sepclk => 0, ft => ft)
port map(clk, txrenable, txraddress(txfabits-1 downto 0), txrdata, clk,
txwrite, txwaddress(txfabits-1 downto 0), txwdata);
rx_fifo0 : syncram_2pft generic map(tech => memtech, abits => fabits,
dbits => 32, sepclk => 0, ft => ft)
port map(clk, rxrenable, rxraddress(fabits-1 downto 0), rxrdata, clk,
rxwrite, rxwaddress(fabits-1 downto 0), rxwdata);
end generate;
-------------------------------------------------------------------------------
-- EDCL buffer ram ------------------------------------------------------------
-------------------------------------------------------------------------------
edclramnft : if (edcl /= 0) and (edclft = 0) generate
r0 : syncram_2p generic map (memtech, eabits, 16) port map(
clk, erenable, eraddress(eabits-1 downto 0), erdata(31 downto 16), clk,
ewritem, ewaddressm(eabits-1 downto 0), ewdata(31 downto 16));
r1 : syncram_2p generic map (memtech, eabits, 16) port map(
clk, erenable, eraddress(eabits-1 downto 0), erdata(15 downto 0), clk,
ewritel, ewaddressl(eabits-1 downto 0), ewdata(15 downto 0));
end generate;
edclramft1 : if (edcl /= 0) and (edclft /= 0) generate
r0 : syncram_2p generic map (memtech, eabits, 16, 0, 0, ft) port map(
clk, erenable, eraddress(eabits-1 downto 0), erdata(31 downto 16), clk,
ewritem, ewaddressm(eabits-1 downto 0), ewdata(31 downto 16));
r1 : syncram_2p generic map (memtech, eabits, 16, 0, 0, ft) port map(
clk, erenable, eraddress(eabits-1 downto 0), erdata(15 downto 0), clk,
ewritel, ewaddressl(eabits-1 downto 0), ewdata(15 downto 0));
end generate;
end architecture;
| gpl-3.0 | 5c9bf1275ad409a1d0ec0b34243af0ff | 0.514522 | 4.138649 | false | false | false | false |
hoglet67/CoPro6502 | src/RAM/RAM_32K.vhd | 1 | 983 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity RAM_32K is
port (
clk : in std_logic;
we_uP : in std_logic;
ce : in std_logic;
addr_uP : in std_logic_vector (14 downto 0);
D_uP : in std_logic_vector (7 downto 0);
Q_uP : out std_logic_vector (7 downto 0));
end;
architecture BEHAVIORAL of RAM_32K is
type ram_type is array (32767 downto 0) of std_logic_vector (7 downto 0);
signal RAM : ram_type := (32767 downto 0 => X"ff");
attribute RAM_STYLE : string;
attribute RAM_STYLE of RAM : signal is "BLOCK";
begin
process (clk)
begin
if rising_edge(clk) then
if (we_UP = '1' and ce = '1') then
RAM(conv_integer(addr_uP(14 downto 0))) <= D_up;
end if;
Q_up <= RAM(conv_integer(addr_uP(14 downto 0)));
end if;
end process;
end BEHAVIORAL;
| gpl-3.0 | bb94b62220eeb4ffd66488e82047b35d | 0.542218 | 3.378007 | false | false | false | false |
pedabraham/MDSM | crs/BaseDeTiempo2.vhd | 1 | 1,045 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
---------------------------------------------------
entity BasedeTiempo2 is
port(
clk : in std_logic;
rst_in : in std_logic;
rst_out : out std_logic
);
end BasedeTiempo2;
---------------------------------------------------
architecture Behavioral of BasedeTiempo2 is
-------------------Signals-------------------------
signal N_S : std_logic_vector(3 downto 0);
signal P_S : std_logic_vector(3 downto 0);
-------------------Process-------------------------
begin
comb : process(P_S)
begin
if(P_S = "11101110011010110010100000000") then
--if(P_S = "0011") then
N_S <= (others => '0');
rst_out <= '1';
else
N_S <= P_S + '1';
rst_out <= '0';
end if;
end process comb;
sequ : process(clk,rst_in,rst_in)
begin
if( rst_in = '1' ) then
P_S <= (others => '0');
elsif ( clk'event AND clk = '1') then
P_S <= N_S;
end if;
end process sequ;
end Behavioral; | mit | 28ac37b4daa2fcce015b0f72cd1e2c2f | 0.491866 | 3.037791 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-avnet-eval-xc4vlx25/testbench.vhd | 1 | 9,564 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- modified by Thomas Ameseder, Gleichmann Electronics 2004, 2005 to
-- support the use of an external AHB slave and different HPE board versions
------------------------------------------------------------------------------
-- further adapted from Hpe_compact to Hpe_mini (Feb. 2005)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.config.all; -- configuration
use work.debug.all;
use std.textio.all;
library grlib;
use grlib.stdlib.all;
use grlib.stdio.all;
use grlib.devices.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 10; -- system clock period
romwidth : integer := 16; -- rom data width (8/32)
romdepth : integer := 16 -- rom address depth
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(22 downto 0);
signal data : std_logic_vector(31 downto 0);
signal romsn : std_logic_vector(1 downto 0);
signal oen : std_ulogic;
signal writen : std_ulogic;
signal iosn : std_ulogic;
-- ddr memory
signal ddr_clk : std_logic;
signal ddr_clkb : std_logic;
signal ddr_clk_fb : std_logic;
signal ddr_cke : std_logic;
signal ddr_csb : std_logic;
signal ddr_web : std_ulogic; -- ddr write enable
signal ddr_rasb : std_ulogic; -- ddr ras
signal ddr_casb : std_ulogic; -- ddr cas
signal ddr_dm : std_logic_vector (1 downto 0); -- ddr dm
signal ddr_dqs : std_logic_vector (1 downto 0); -- ddr dqs
signal ddr_ad : std_logic_vector (12 downto 0); -- ddr address
signal ddr_ba : std_logic_vector (1 downto 0); -- ddr bank address
signal ddr_dq : std_logic_vector (15 downto 0); -- ddr data
signal brdyn : std_ulogic;
signal bexcn : std_ulogic;
signal wdog : std_ulogic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal rtsn, ctsn : std_ulogic;
signal error : std_logic;
signal pio : std_logic_vector(15 downto 0);
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal plllock : std_ulogic;
-- pulled up high, therefore std_logic
signal txd1, rxd1 : std_logic;
signal etx_clk, erx_clk, erx_dv, erx_er, erx_col, erx_crs, etx_en, etx_er : std_logic := '0';
signal erxd, etxd : std_logic_vector(3 downto 0) := (others => '0');
signal emdc, emdio : std_logic; --dummy signal for the mdc,mdio in the phy which is not used
constant lresp : boolean := false;
signal resoutn : std_logic;
signal dsubren : std_ulogic;
signal dsuactn : std_ulogic;
begin
dsubren <= not dsubre;
-- clock and reset
clk <= not clk after ct * 1 ns;
rst <= '1', '0' after 1000 ns;
dsuen <= '0'; dsubre <= '0'; rxd1 <= 'H';
address(0) <= '0';
ddr_dqs <= (others => 'L');
d3 : entity work.leon3mp
port map (
resetn => rst,
resoutn => resoutn,
clk_100mhz => clk,
errorn => error,
address => address(22 downto 1),
data => data(31 downto 16),
testdata => data(15 downto 0),
ddr_clk0 => ddr_clk,
ddr_clk0b => ddr_clkb,
ddr_clk_fb => ddr_clk_fb,
ddr_cke0 => ddr_cke,
ddr_cs0b => ddr_csb,
ddr_web => ddr_web,
ddr_rasb => ddr_rasb,
ddr_casb => ddr_casb,
ddr_dm => ddr_dm,
ddr_dqs => ddr_dqs,
ddr_ad => ddr_ad,
ddr_ba => ddr_ba,
ddr_dq => ddr_dq,
sertx => dsutx,
serrx => dsurx,
rtsn => rtsn,
ctsn => ctsn,
dsuen => dsuen,
dsubre => dsubre,
dsuact => dsuactn,
oen => oen,
writen => writen,
iosn => iosn,
romsn => romsn(0),
emdio => emdio,
etx_clk => etx_clk,
erx_clk => erx_clk,
erxd => erxd,
erx_dv => erx_dv,
erx_er => erx_er,
erx_col => erx_col,
erx_crs => erx_crs,
etxd => etxd,
etx_en => etx_en,
etx_er => etx_er,
emdc => emdc
);
ddr_clk_fb <= ddr_clk;
-- u1 : mt46v16m16
-- generic map (index => -1, fname => sdramfile)
-- port map(
-- Dq => ddr_dq(15 downto 0), Dqs => ddr_dqs(1 downto 0), Addr => ddr_ad,
-- Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke,
-- Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
-- Dm => ddr_dm(1 downto 0));
ddr0 : ddrram
generic map(width => 16, abits => 13, colbits => 9, rowbits => 13,
implbanks => 1, fname => sdramfile, density => 1)
port map (ck => ddr_clk, cke => ddr_cke, csn => ddr_csb,
rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web,
dm => ddr_dm, ba => ddr_ba, a => ddr_ad, dq => ddr_dq,
dqs => ddr_dqs);
prom0 : for i in 0 to (romwidth/8)-1 generate
sr0 : sram generic map (index => i+4, abits => romdepth, fname => promfile)
port map (address(romdepth downto 1), data(31-i*8 downto 24-i*8), romsn(0),
writen, oen);
end generate;
-- phy0 : if CFG_GRETH > 0 generate
-- p0 : phy
-- port map(rst, led_cfg, open, etx_clk, erx_clk, erxd, erx_dv,
-- erx_er, erx_col, erx_crs, etxd, etx_en, etx_er, emdc);
-- end generate;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 5 us;
assert (to_X01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure;
end process;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, oen, writen, brdyn);
data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#ef#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
--
-- txc(dsutx, 16#80#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end;
| gpl-3.0 | 02e30621ecf334b93a901136326c529f | 0.527499 | 3.522652 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-asic/leon3mp.vhd | 1 | 18,188 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2013 Aeroflex Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.config.all;
library techmap;
use techmap.gencomp.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
scantest : integer := CFG_SCAN
);
port (
resetn : in std_ulogic;
clksel : in std_logic_vector(1 downto 0);
clk : in std_ulogic;
lock : out std_ulogic;
errorn : inout std_ulogic;
wdogn : inout std_ulogic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
cb : inout std_logic_vector(7 downto 0);
sdclk : out std_ulogic;
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_ulogic; -- sdram write enable
sdrasn : out std_ulogic; -- sdram ras
sdcasn : out std_ulogic; -- sdram cas
sddqm : out std_logic_vector (3 downto 0); -- sdram dqm
dsutx : out std_ulogic; -- DSU tx data / scanout
dsurx : in std_ulogic; -- DSU rx data / scanin
dsuen : in std_ulogic;
dsubre : in std_ulogic; -- DSU break / scanen
dsuact : out std_ulogic; -- DSU active / NT
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
txd2 : out std_ulogic; -- UART2 tx data
rxd2 : in std_ulogic; -- UART2 rx data
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_ulogic;
writen : out std_ulogic;
read : out std_ulogic;
iosn : out std_ulogic;
romsn : out std_logic_vector (1 downto 0);
brdyn : in std_ulogic;
bexcn : in std_ulogic;
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
i2c_scl : inout std_ulogic;
i2c_sda : inout std_ulogic;
spi_miso : in std_ulogic;
spi_mosi : out std_ulogic;
spi_sck : out std_ulogic;
spi_slvsel : out std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
prom32 : in std_ulogic;
spw_clksel : in std_logic_vector(1 downto 0);
spw_clk : in std_ulogic;
spw_rxd : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxs : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txd : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txs : out std_logic_vector(0 to CFG_SPW_NUM-1);
gtx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(7 downto 0);
erx_dv : in std_ulogic;
etx_clk : in std_ulogic;
etxd : out std_logic_vector(7 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
emdint : in std_ulogic;
emdio : inout std_logic;
emdc : out std_ulogic;
testen : in std_ulogic;
trst : in std_ulogic;
tck : in std_ulogic;
tms : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic
);
end;
architecture rtl of leon3mp is
signal lresetn : std_ulogic;
signal lclksel : std_logic_vector (1 downto 0);
signal lclk : std_ulogic;
signal llock : std_ulogic;
signal lerrorn : std_ulogic;
signal laddress : std_logic_vector(27 downto 0);
signal ldatain : std_logic_vector(31 downto 0);
signal ldataout : std_logic_vector(31 downto 0);
signal ldataen : std_logic_vector(31 downto 0);
signal lcbin : std_logic_vector(7 downto 0);
signal lcbout : std_logic_vector(7 downto 0);
signal lcben : std_logic_vector(7 downto 0);
signal lsdclk : std_ulogic;
signal lsdcsn : std_logic_vector (1 downto 0);
signal lsdwen : std_ulogic;
signal lsdrasn : std_ulogic;
signal lsdcasn : std_ulogic;
signal lsddqm : std_logic_vector (3 downto 0);
signal ldsutx : std_ulogic;
signal ldsurx : std_ulogic;
signal ldsuen : std_ulogic;
signal ldsubre : std_ulogic;
signal ldsuact : std_ulogic;
signal ltxd1 : std_ulogic;
signal lrxd1 : std_ulogic;
signal ltxd2 : std_ulogic;
signal lrxd2 : std_ulogic;
signal lramsn : std_logic_vector (4 downto 0);
signal lramoen : std_logic_vector (4 downto 0);
signal lrwen : std_logic_vector (3 downto 0);
signal loen : std_ulogic;
signal lwriten : std_ulogic;
signal lread : std_ulogic;
signal liosn : std_ulogic;
signal lromsn : std_logic_vector (1 downto 0);
signal lbrdyn : std_ulogic;
signal lbexcn : std_ulogic;
signal lwdogn : std_ulogic;
signal lgpioin : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal lgpioout : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal lgpioen : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal li2c_sclout : std_ulogic;
signal li2c_sclen : std_ulogic;
signal li2c_sclin : std_ulogic;
signal li2c_sdaout : std_ulogic;
signal li2c_sdaen : std_ulogic;
signal li2c_sdain : std_ulogic;
signal lspi_miso : std_ulogic;
signal lspi_mosi : std_ulogic;
signal lspi_sck : std_ulogic;
signal lspi_slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal lprom32 : std_ulogic;
signal lspw_clksel : std_logic_vector (1 downto 0);
signal lspw_clk : std_ulogic;
signal lspw_rxd : std_logic_vector(0 to CFG_SPW_NUM-1);
signal lspw_rxs : std_logic_vector(0 to CFG_SPW_NUM-1);
signal lspw_txd : std_logic_vector(0 to CFG_SPW_NUM-1);
signal lspw_txs : std_logic_vector(0 to CFG_SPW_NUM-1);
signal lgtx_clk : std_ulogic;
signal lerx_clk : std_ulogic;
signal lerxd : std_logic_vector(7 downto 0);
signal lerx_dv : std_ulogic;
signal letx_clk : std_ulogic;
signal letxd : std_logic_vector(7 downto 0);
signal letx_en : std_ulogic;
signal letx_er : std_ulogic;
signal lerx_er : std_ulogic;
signal lerx_col : std_ulogic;
signal lerx_crs : std_ulogic;
signal lemdint : std_ulogic;
signal lemdioin : std_logic;
signal lemdioout : std_logic;
signal lemdioen : std_logic;
signal lemdc : std_ulogic;
signal ltesten : std_ulogic;
signal ltrst : std_ulogic;
signal ltck : std_ulogic;
signal ltms : std_ulogic;
signal ltdi : std_ulogic;
signal ltdo : std_ulogic;
signal ltdoen : std_ulogic;
-- Use for ASIC
--constant padvoltage : integer := x33v;
--constant padlevel : integer := ttl;
-- Use for FPGA
constant padvoltage : integer := x18v;
constant padlevel : integer := cmos;
begin
-- TODO: Move PAD options to 'xconfig'
pads0 : entity work.pads
generic map (
padtech => CFG_PADTECH,
padlevel => padlevel,
padstrength => 10,
jtag_padfilter => pullup,
testen_padfilter => pulldown,
resetn_padfilter => schmitt,
clk_padfilter => 0,
spw_padstrength => 12,
jtag_padstrength => 6,
uart_padstrength => 6,
dsu_padstrength => 6,
padvoltage => padvoltage,
spw_input_type => CFG_SPW_INPUT,
oepol => padoen_polarity(CFG_PADTECH)
)
port map (
---------------------------
--to chip boundary
---------------------------
resetn => resetn ,
clksel => clksel ,
clk => clk ,
lock => lock ,
errorn => errorn ,
address => address ,
data => data ,
cb => cb ,
sdclk => sdclk ,
sdcsn => sdcsn ,
sdwen => sdwen ,
sdrasn => sdrasn ,
sdcasn => sdcasn ,
sddqm => sddqm ,
dsutx => dsutx ,
dsurx => dsurx ,
dsuen => dsuen ,
dsubre => dsubre ,
dsuact => dsuact ,
txd1 => txd1 ,
rxd1 => rxd1 ,
txd2 => txd2 ,
rxd2 => rxd2 ,
ramsn => ramsn ,
ramoen => ramoen ,
rwen => rwen ,
oen => oen ,
writen => writen ,
read => read ,
iosn => iosn ,
romsn => romsn ,
brdyn => brdyn ,
bexcn => bexcn ,
wdogn => wdogn ,
gpio => gpio ,
i2c_scl => i2c_scl ,
i2c_sda => i2c_sda ,
spi_miso => spi_miso ,
spi_mosi => spi_mosi ,
spi_sck => spi_sck ,
spi_slvsel => spi_slvsel,
prom32 => prom32 ,
spw_clksel => spw_clksel,
spw_clk => spw_clk ,
spw_rxd => spw_rxd ,
spw_rxs => spw_rxs ,
spw_txd => spw_txd ,
spw_txs => spw_txs ,
gtx_clk => gtx_clk ,
erx_clk => erx_clk ,
erxd => erxd ,
erx_dv => erx_dv ,
etx_clk => etx_clk ,
etxd => etxd ,
etx_en => etx_en ,
etx_er => etx_er ,
erx_er => erx_er ,
erx_col => erx_col ,
erx_crs => erx_crs ,
emdint => emdint ,
emdio => emdio ,
emdc => emdc ,
testen => testen ,
trst => trst ,
tck => tck ,
tms => tms ,
tdi => tdi ,
tdo => tdo ,
------------------------- ---
--to core
----------------------------
lresetn => lresetn ,
lclksel => lclksel ,
lclk => lclk ,
llock => llock ,
lerrorn => lerrorn ,
laddress => laddress ,
ldatain => ldatain ,
ldataout => ldataout ,
ldataen => ldataen ,
lcbin => lcbin ,
lcbout => lcbout ,
lcben => lcben ,
lsdclk => lsdclk ,
lsdcsn => lsdcsn ,
lsdwen => lsdwen ,
lsdrasn => lsdrasn ,
lsdcasn => lsdcasn ,
lsddqm => lsddqm ,
ldsutx => ldsutx ,
ldsurx => ldsurx ,
ldsuen => ldsuen ,
ldsubre => ldsubre ,
ldsuact => ldsuact ,
ltxd1 => ltxd1 ,
lrxd1 => lrxd1 ,
ltxd2 => ltxd2 ,
lrxd2 => lrxd2 ,
lramsn => lramsn ,
lramoen => lramoen ,
lrwen => lrwen ,
loen => loen ,
lwriten => lwriten ,
lread => lread ,
liosn => liosn ,
lromsn => lromsn ,
lbrdyn => lbrdyn ,
lbexcn => lbexcn ,
lwdogn => lwdogn ,
lgpioin => lgpioin ,
lgpioout => lgpioout ,
lgpioen => lgpioen ,
li2c_sclout => li2c_sclout,
li2c_sclen => li2c_sclen ,
li2c_sclin => li2c_sclin ,
li2c_sdaout => li2c_sdaout,
li2c_sdaen => li2c_sdaen ,
li2c_sdain => li2c_sdain ,
lspi_miso => lspi_miso ,
lspi_mosi => lspi_mosi ,
lspi_sck => lspi_sck ,
lspi_slvsel => lspi_slvsel,
lprom32 => lprom32 ,
lspw_clksel => lspw_clksel,
lspw_clk => lspw_clk ,
lspw_rxd => lspw_rxd ,
lspw_rxs => lspw_rxs ,
lspw_txd => lspw_txd ,
lspw_txs => lspw_txs ,
lgtx_clk => lgtx_clk ,
lerx_clk => lerx_clk ,
lerxd => lerxd ,
lerx_dv => lerx_dv ,
letx_clk => letx_clk ,
letxd => letxd ,
letx_en => letx_en ,
letx_er => letx_er ,
lerx_er => lerx_er ,
lerx_col => lerx_col ,
lerx_crs => lerx_crs ,
lemdint => lemdint ,
lemdioin => lemdioin ,
lemdioout => lemdioout ,
lemdioen => lemdioen ,
lemdc => lemdc ,
ltesten => ltesten ,
ltrst => ltrst ,
ltck => ltck ,
ltms => ltms ,
ltdi => ltdi ,
ltdo => ltdo ,
ltdoen => ltdoen
);
-- ASIC Core
core0 : entity work.core
generic map (
fabtech => CFG_FABTECH,
memtech => CFG_MEMTECH,
padtech => CFG_PADTECH,
clktech => CFG_CLKTECH,
disas => CFG_DISAS,
dbguart => CFG_DUART,
pclow => CFG_PCLOW,
scantest => CFG_SCAN,
bscanen => CFG_BOUNDSCAN_EN,
oepol => padoen_polarity(CFG_PADTECH)
)
port map (
----------------------------
-- ASIC Ports/Pads
----------------------------
resetn => lresetn ,
clksel => lclksel ,
clk => lclk ,
lock => llock ,
errorn => lerrorn ,
address => laddress ,
datain => ldatain ,
dataout => ldataout ,
dataen => ldataen ,
cbin => lcbin ,
cbout => lcbout ,
cben => lcben ,
sdclk => lsdclk ,
sdcsn => lsdcsn ,
sdwen => lsdwen ,
sdrasn => lsdrasn ,
sdcasn => lsdcasn ,
sddqm => lsddqm ,
dsutx => ldsutx ,
dsurx => ldsurx ,
dsuen => ldsuen ,
dsubre => ldsubre ,
dsuact => ldsuact ,
txd1 => ltxd1 ,
rxd1 => lrxd1 ,
txd2 => ltxd2 ,
rxd2 => lrxd2 ,
ramsn => lramsn ,
ramoen => lramoen ,
rwen => lrwen ,
oen => loen ,
writen => lwriten ,
read => lread ,
iosn => liosn ,
romsn => lromsn ,
brdyn => lbrdyn ,
bexcn => lbexcn ,
wdogn => lwdogn ,
gpioin => lgpioin ,
gpioout => lgpioout ,
gpioen => lgpioen ,
i2c_sclout => li2c_sclout,
i2c_sclen => li2c_sclen ,
i2c_sclin => li2c_sclin ,
i2c_sdaout => li2c_sdaout,
i2c_sdaen => li2c_sdaen ,
i2c_sdain => li2c_sdain ,
spi_miso => lspi_miso ,
spi_mosi => lspi_mosi ,
spi_sck => lspi_sck ,
spi_slvsel => lspi_slvsel,
prom32 => lprom32 ,
spw_clksel => lspw_clksel,
spw_clk => lspw_clk ,
spw_rxd => lspw_rxd ,
spw_rxs => lspw_rxs ,
spw_txd => lspw_txd ,
spw_txs => lspw_txs ,
gtx_clk => lgtx_clk ,
erx_clk => lerx_clk ,
erxd => lerxd ,
erx_dv => lerx_dv ,
etx_clk => letx_clk ,
etxd => letxd ,
etx_en => letx_en ,
etx_er => letx_er ,
erx_er => lerx_er ,
erx_col => lerx_col ,
erx_crs => lerx_crs ,
emdint => lemdint ,
emdioin => lemdioin ,
emdioout => lemdioout ,
emdioen => lemdioen ,
emdc => lemdc ,
testen => ltesten ,
trst => ltrst ,
tck => ltck ,
tms => ltms ,
tdi => ltdi ,
tdo => ltdo ,
tdoen => ltdoen ,
----------------------------
-- BSCAN
----------------------------
chain_tck => OPEN ,
chain_tckn => OPEN ,
chain_tdi => OPEN ,
chain_tdo => '0',
bsshft => OPEN ,
bscapt => OPEN ,
bsupdi => OPEN ,
bsupdo => OPEN ,
bsdrive => OPEN ,
bshighz => OPEN
);
-- BSCAN
-- TODO: ADD BSCAN
end;
| gpl-3.0 | 3ac3f7795aeae27178cc607affa87b1c | 0.463822 | 3.690747 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-xilinx-ml50x/testbench.vhd | 1 | 13,438 | -----------------------------------------------------------------------------
-- LEON Demonstration design test bench
-- Copyright (C) 2004 - 2015 Cobham Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library cypress;
use cypress.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
transtech : integer := CFG_TRANSTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 10; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 18; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal sys_clk : std_logic := '0';
signal sys_rst_in : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
constant slips : integer := 11;
signal bus_error : std_logic_vector (1 downto 0);
signal sram_flash_addr : std_logic_vector(23 downto 0);
signal address : std_logic_vector(24 downto 0);
signal sram_flash_data, data : std_logic_vector(31 downto 0);
signal sram_cen : std_logic;
signal sram_bw : std_logic_vector (3 downto 0);
signal sram_oen : std_ulogic;
signal flash_oen : std_ulogic;
signal sram_flash_we_n : std_ulogic;
signal flash_cen : std_logic;
signal flash_adv_n : std_logic;
signal sram_clk : std_ulogic;
signal sram_clk_fb : std_ulogic;
signal sram_mode : std_ulogic;
signal sram_adv_ld_n : std_ulogic;
signal iosn : std_ulogic;
signal ddr_clk : std_logic_vector(1 downto 0);
signal ddr_clkb : std_logic_vector(1 downto 0);
signal ddr_cke : std_logic_vector(1 downto 0);
signal ddr_csb : std_logic_vector(1 downto 0);
signal ddr_odt : std_logic_vector(1 downto 0);
signal ddr_web : std_ulogic; -- ddr write enable
signal ddr_rasb : std_ulogic; -- ddr ras
signal ddr_casb : std_ulogic; -- ddr cas
signal ddr_dm : std_logic_vector (7 downto 0); -- ddr dm
signal ddr_dqsp : std_logic_vector (7 downto 0); -- ddr dqs
signal ddr_dqsn : std_logic_vector (7 downto 0); -- ddr dqs
signal ddr_rdqs : std_logic_vector (7 downto 0); -- ddr dqs
signal ddr_ad : std_logic_vector (13 downto 0); -- ddr address
signal ddr_ba : std_logic_vector (1+CFG_DDR2SP downto 0); -- ddr bank address
signal ddr_dq : std_logic_vector (63 downto 0); -- ddr data
signal ddr_dq2 : std_logic_vector (63 downto 0); -- ddr data
signal txd1 : std_ulogic; -- UART1 tx data
signal rxd1 : std_ulogic; -- UART1 rx data
signal txd2 : std_ulogic; -- UART2 tx data
signal rxd2 : std_ulogic; -- UART2 rx data
signal gpio : std_logic_vector(12 downto 0); -- I/O port
signal led : std_logic_vector(12 downto 0); -- I/O port
signal phy_mii_data: std_logic; -- ethernet PHY interface
signal phy_tx_clk : std_ulogic;
signal phy_rx_clk : std_ulogic;
signal phy_rx_data : std_logic_vector(7 downto 0);
signal phy_dv : std_ulogic;
signal phy_rx_er : std_ulogic;
signal phy_col : std_ulogic;
signal phy_crs : std_ulogic;
signal phy_tx_data : std_logic_vector(7 downto 0);
signal phy_tx_en : std_ulogic;
signal phy_tx_er : std_ulogic;
signal phy_mii_clk : std_ulogic;
signal phy_rst_n : std_ulogic;
signal phy_int : std_ulogic := '0';
signal phy_gtx_clk : std_ulogic;
signal sgmii_rx_n : std_ulogic;
signal sgmii_rx_p : std_ulogic;
signal sgmii_rx_n_d : std_ulogic;
signal sgmii_rx_p_d : std_ulogic;
signal sgmii_tx_n : std_ulogic;
signal sgmii_tx_p : std_ulogic;
signal ps2_keyb_clk: std_logic;
signal ps2_keyb_data: std_logic;
signal ps2_mouse_clk: std_logic;
signal ps2_mouse_data: std_logic;
signal usb_csn, usb_rstn : std_logic;
signal iic_scl_main, iic_sda_main : std_logic;
signal iic_scl_video, iic_sda_video : std_logic;
signal tft_lcd_data : std_logic_vector(11 downto 0);
signal tft_lcd_clk_p : std_logic;
signal tft_lcd_clk_n : std_logic;
signal tft_lcd_hsync : std_logic;
signal tft_lcd_vsync : std_logic;
signal tft_lcd_de : std_logic;
signal tft_lcd_reset_b : std_logic;
signal sysace_mpa : std_logic_vector(6 downto 0);
signal sysace_mpce : std_ulogic;
signal sysace_mpirq : std_ulogic;
signal sysace_mpoe : std_ulogic;
signal sysace_mpwe : std_ulogic;
signal sysace_d : std_logic_vector(15 downto 0);
--pcie--
signal cor_sys_reset_n : std_logic := '1';
signal ep_sys_clk_p : std_logic;
signal ep_sys_clk_n : std_logic;
signal rp_sys_clk : std_logic;
signal cor_pci_exp_txn : std_logic_vector(CFG_NO_OF_LANES-1 downto 0) := (others => '0');
signal cor_pci_exp_txp : std_logic_vector(CFG_NO_OF_LANES-1 downto 0) := (others => '0');
signal cor_pci_exp_rxn : std_logic_vector(CFG_NO_OF_LANES-1 downto 0) := (others => '0');
signal cor_pci_exp_rxp : std_logic_vector(CFG_NO_OF_LANES-1 downto 0) := (others => '0');
--pcie end--
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk_200_p : std_ulogic := '0';
signal clk_200_n : std_ulogic := '1';
signal clk_33 : std_ulogic := '0';
signal clk_125_p : std_ulogic := '0';
signal clk_125_n : std_ulogic := '1';
signal rst_125 : std_ulogic;
constant lresp : boolean := false;
begin
-- clock and reset
sys_clk <= not sys_clk after ct * 1 ns;
sys_rst_in <= '0', '1' after 200 ns;
clk_200_p <= not clk_200_p after 2.5 ns;
clk_200_n <= not clk_200_n after 2.5 ns;
clk_125_p <= not clk_125_p after 4 ns;
clk_125_n <= not clk_125_n after 4 ns;
clk_33 <= not clk_33 after 15 ns;
rxd1 <= 'H'; gpio(11) <= 'L';
sram_clk_fb <= sram_clk;
ps2_keyb_data <= 'H'; ps2_keyb_clk <= 'H';
ps2_mouse_clk <= 'H'; ps2_mouse_data <= 'H';
iic_scl_main <= 'H'; iic_sda_main <= 'H';
iic_scl_video <= 'H'; iic_sda_video <= 'H';
sysace_d <= (others => 'H'); sysace_mpirq <= 'L';
cpu : entity work.leon3mp
generic map ( fabtech, memtech, padtech, transtech, ncpu, disas, dbguart, pclow )
port map ( sys_rst_in, sys_clk, clk_200_p, clk_200_n, clk_33, sram_flash_addr,
sram_flash_data, sram_cen, sram_bw, sram_oen, sram_flash_we_n,
flash_cen, flash_oen, flash_adv_n,sram_clk, sram_clk_fb, sram_mode,
sram_adv_ld_n, iosn,
ddr_clk, ddr_clkb, ddr_cke, ddr_csb, ddr_odt, ddr_web,
ddr_rasb, ddr_casb, ddr_dm, ddr_dqsp, ddr_dqsn, ddr_ad, ddr_ba, ddr_dq,
txd1, rxd1, txd2, rxd2, gpio, led, bus_error,
phy_gtx_clk, phy_mii_data, phy_tx_clk, phy_rx_clk,
phy_rx_data, phy_dv, phy_rx_er, phy_col, phy_crs,
phy_tx_data, phy_tx_en, phy_tx_er, phy_mii_clk, phy_rst_n, phy_int,
sgmii_rx_n, sgmii_rx_p, sgmii_tx_n, sgmii_tx_p, clk_125_n, clk_125_p,
ps2_keyb_clk, ps2_keyb_data, ps2_mouse_clk, ps2_mouse_data,
usb_csn, usb_rstn,
iic_scl_main, iic_sda_main,
iic_scl_video, iic_sda_video,
tft_lcd_data, tft_lcd_clk_p, tft_lcd_clk_n, tft_lcd_hsync,
tft_lcd_vsync, tft_lcd_de, tft_lcd_reset_b,
sysace_mpa, sysace_mpce, sysace_mpirq, sysace_mpoe,
sysace_mpwe, sysace_d, cor_pci_exp_txp, cor_pci_exp_txn, cor_pci_exp_rxp,
cor_pci_exp_rxn, ep_sys_clk_p, ep_sys_clk_n, cor_sys_reset_n
);
ddr0 : ddr2ram
generic map(width => 64, abits => 13, babits =>2, colbits => 10, rowbits => 13,
implbanks => 1, fname => sdramfile, speedbin=>1, density => 2,
lddelay => 100 us * CFG_MIG_DDR2)
port map (ck => ddr_clk(0), ckn => ddr_clkb(0), cke => ddr_cke(0), csn => ddr_csb(0),
odt => ddr_odt(0), rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web,
dm => ddr_dm, ba => ddr_ba(1 downto 0), a => ddr_ad(12 downto 0), dq => ddr_dq2,
dqs => ddr_dqsp, dqsn =>ddr_dqsn);
nodqdel : if (CFG_MIG_DDR2 = 1) generate
ddr2delay : delay_wire
generic map(data_width => ddr_dq'length, delay_atob => 0.0, delay_btoa => 0.0)
port map(a => ddr_dq, b => ddr_dq2);
end generate;
dqdel : if (CFG_MIG_DDR2 = 0) generate
ddr2delay : delay_wire
generic map(data_width => ddr_dq'length, delay_atob => 0.0, delay_btoa => 5.5)
port map(a => ddr_dq, b => ddr_dq2);
end generate;
sram01 : for i in 0 to 1 generate
sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
port map (sram_flash_addr(sramdepth downto 1), sram_flash_data(15-i*8 downto 8-i*8),
sram_cen, sram_bw(i+2), sram_oen);
end generate;
sram23 : for i in 2 to 3 generate
sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
port map (sram_flash_addr(sramdepth downto 1), sram_flash_data(47-i*8 downto 40-i*8),
sram_cen, sram_bw(i-2), sram_oen);
end generate;
prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile)
port map (sram_flash_addr(romdepth-1 downto 0), sram_flash_data(15 downto 0),
gnd, gnd, flash_cen, sram_flash_we_n, flash_oen);
gmii_phy: if CFG_GRETH_SGMII = 0 generate
phy_mii_data <= 'H';
p0: phy
generic map (address => 7)
port map(phy_rst_n, phy_mii_data, phy_tx_clk, phy_rx_clk, phy_rx_data,
phy_dv, phy_rx_er, phy_col, phy_crs, phy_tx_data, phy_tx_en,
phy_tx_er, phy_mii_clk, phy_gtx_clk);
end generate;
sgmii_phy: if CFG_GRETH_SGMII /= 0 generate
-- delaying rx line
sgmii_rx_p <= transport sgmii_rx_p_d after 0.8 ns * slips;
sgmii_rx_n <= transport sgmii_rx_n_d after 0.8 ns * slips;
rst_125 <= not phy_rst_n;
sp0: ser_phy
generic map(
address => 7,
extended_regs => 1,
aneg => 1,
fd_10 => 1,
hd_10 => 1,
base100_t4 => 1,
base100_x_fd => 1,
base100_x_hd => 1,
base100_t2_fd => 1,
base100_t2_hd => 1,
base1000_x_fd => 1,
base1000_x_hd => 1,
base1000_t_fd => 1,
base1000_t_hd => 1,
fabtech => virtex5,
memtech => virtex5
)
port map(
rstn => phy_rst_n,
clk_125 => clk_125_p,
rst_125 => rst_125,
eth_rx_p => sgmii_rx_p_d,
eth_rx_n => sgmii_rx_n_d,
eth_tx_p => sgmii_tx_p,
eth_tx_n => sgmii_tx_n,
mdio => phy_mii_data,
mdc => phy_mii_clk
);
end generate;
i0: i2c_slave_model
port map (iic_scl_main, iic_sda_main);
iuerr : process
begin
wait for 5000 ns;
if to_x01(bus_error(0)) = '0' then wait on bus_error; end if;
assert (to_x01(bus_error(0)) = '0')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= sram_flash_data(15 downto 0) & sram_flash_data(31 downto 16);
address <= sram_flash_addr & '0';
test0 : grtestmod
port map ( sys_rst_in, sys_clk, bus_error(0), sram_flash_addr(20 downto 1), data,
iosn, flash_oen, sram_bw(0), open);
sram_flash_data <= buskeep(sram_flash_data), (others => 'H') after 250 ns;
-- ddr_dq <= buskeep(ddr_dq), (others => 'H') after 250 ns;
data <= buskeep(data), (others => 'H') after 250 ns;
end ;
| gpl-3.0 | 65623c4d525867c6c933ad9392aadc43 | 0.589299 | 3.130212 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/can/can_mc.vhd | 1 | 6,392 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: can_oc
-- File: can_oc.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB interface for the OpenCores CAN MAC
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.can.all;
entity can_mc is
generic (
slvndx : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#FF0#;
irq : integer := 0;
memtech : integer := DEFMEMTECH;
ncores : integer range 1 to 8 := 1;
sepirq : integer range 0 to 1 := 0;
syncrst : integer range 0 to 2 := 0;
ft : integer range 0 to 1 := 0);
port (
resetn : in std_logic;
clk : in std_logic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
can_rxi : in std_logic_vector(0 to 7);
can_txo : out std_logic_vector(0 to 7)
);
attribute sync_set_reset of resetn : signal is "true";
end;
architecture rtl of can_mc is
constant REVISION : amba_version_type := ncores-1;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_CANAHB, 0, REVISION, irq),
4 => ahb_iobar(ioaddr, iomask), others => zero32);
type ahbregs is record
hsel : std_ulogic;
hwrite : std_ulogic;
hwrite2 : std_ulogic;
htrans : std_logic_vector(1 downto 0);
haddr : std_logic_vector(10 downto 0);
hwdata : std_logic_vector(7 downto 0);
herr : std_ulogic;
hready : std_ulogic;
ws : std_logic_vector(1 downto 0);
irqi : std_logic_vector(ncores-1 downto 0);
irqo : std_logic_vector(ncores-1 downto 0);
end record;
subtype cdata is std_logic_vector(7 downto 0);
type cdataarr is array (0 to 7) of cdata;
signal data_out : cdataarr;
signal reset : std_logic;
signal irqo : std_logic_vector(ncores-1 downto 0);
signal cs : std_logic_vector(7 downto 0);
signal vcc, gnd : std_ulogic;
signal r, rin : ahbregs;
--attribute sync_set_reset : string;
attribute sync_set_reset of reset : signal is "true";
begin
gnd <= '0'; vcc <= '1'; reset <= not resetn;
comb : process(ahbsi, r, resetn, data_out, irqo)
variable v : ahbregs;
variable hresp : std_logic_vector(1 downto 0);
variable lcs, dataout : std_logic_vector(7 downto 0);
variable irqvec : std_logic_vector(NAHBIRQ-1 downto 0);
variable hwdata : std_logic_vector(31 downto 0);
begin
v := r;
hwdata := ahbreadword(ahbsi.hwdata, r.haddr(4 downto 2));
if (r.hsel = '1' ) and (r.ws /= "11") then v.ws := r.ws + 1; end if;
if ahbsi.hready = '1' then
v.hsel := ahbsi.hsel(slvndx);
v.haddr := ahbsi.haddr(10 downto 0);
v.htrans := ahbsi.htrans;
v.hwrite := ahbsi.hwrite;
v.herr := orv(ahbsi.hsize) and ahbsi.hwrite;
v.ws := "00";
end if;
v.hready := (r.hsel and r.ws(1) and not r.ws(0)) or not resetn
or (ahbsi.hready and not ahbsi.htrans(1)) or not v.hsel;
v.hwrite2 := r.hwrite and r.hsel and r.htrans(1) and r.ws(1)
and not r.ws(0) and not r.herr;
if (r.herr and r.ws(1)) = '1' then hresp := HRESP_ERROR;
else hresp := HRESP_OKAY; end if;
case r.haddr(1 downto 0) is
when "00" => v.hwdata := hwdata(31 downto 24);
when "01" => v.hwdata := hwdata(23 downto 16);
when "10" => v.hwdata := hwdata(15 downto 8);
when others => v.hwdata := hwdata(7 downto 0);
end case;
if ncores > 1 then
if r.hsel = '1' then lcs := decode(r.haddr(10 downto 8));
else lcs := (others => '0'); end if;
dataout := data_out(conv_integer(r.haddr(10 downto 8)));
else dataout := data_out(0); lcs := "0000000" & r.hsel; end if;
-- Interrupt goes to low when appeard and is normal high
-- but the irq controller from leon is active high and the interrupt should appear only
-- for 1 Clk cycle,
v.irqi := irqo; v.irqo:= (r.irqi and not irqo);
irqvec := (others => '0');
if sepirq = 1 then irqvec(ncores-1+irq downto irq) := r.irqo;
else irqvec(irq) := orv(r.irqo); end if;
ahbso.hirq <= irqvec;
ahbso.hrdata <= ahbdrivedata(dataout);
cs <= lcs;
ahbso.hresp <= hresp; rin <= v;
end process;
reg : process(clk)
begin if clk'event and clk = '1' then r <= rin; end if; end process;
cgen : for i in 0 to 7 generate
c0 : if i < ncores generate
cmod : can_mod generic map (memtech, syncrst, ft)
port map (reset, clk, cs(i), r.hwrite2, r.haddr(7 downto 0), r.hwdata,
data_out(i), irqo(i), can_rxi(i), can_txo(i), ahbsi.testen);
end generate;
c1 : if i >= ncores generate
can_txo(i) <= '0'; data_out(i) <= (others => '0');
end generate;
end generate;
ahbso.hconfig <= hconfig;
ahbso.hindex <= slvndx;
ahbso.hsplit <= (others => '0');
ahbso.hready <= r.hready;
-- pragma translate_off
bootmsg : report_version
generic map (
"can_oc" & tost(slvndx) &
": SJA1000 Compatible CAN MAC, #cores " & tost(REVISION+1) & ", irq " & tost(irq));
-- pragma translate_on
end;
| gpl-3.0 | 76fee8be8e611b3bf35276032d80521f | 0.591677 | 3.481481 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/misc/ahb_mst_iface.vhd | 1 | 5,219 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: ahb_mst_iface
-- File: ahb_mst_iface.vhd
-- Author: Marko Isomaki - Aeroflex Gaisler
-- Description: General AHB master interface for DMA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
library gaisler;
use gaisler.misc.all;
entity ahb_mst_iface is
generic(
hindex : integer;
vendor : integer;
device : integer;
revision : integer);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
msti : in ahb_mst_iface_in_type;
msto : out ahb_mst_iface_out_type
);
end entity;
architecture rtl of ahb_mst_iface is
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( vendor, device, 0, revision, 0),
others => zero32);
type reg_type is record
bg : std_ulogic; --bus granted
ba : std_ulogic; --bus active
bb : std_ulogic; --1kB burst boundary detected
retry : std_ulogic;
error : std_ulogic;
end record;
signal r, rin : reg_type;
begin
comb : process(rst, r, msti, ahbmi) is
variable v : reg_type;
variable htrans : std_logic_vector(1 downto 0);
variable hbusreq : std_ulogic;
variable hwrite : std_ulogic;
variable haddr : std_logic_vector(31 downto 0);
variable hwdata : std_logic_vector(31 downto 0);
variable vretry : std_ulogic;
variable vready : std_ulogic;
variable verror : std_ulogic;
variable vgrant : std_ulogic;
variable hsize : std_logic_vector(2 downto 0);
begin
v := r; htrans := HTRANS_IDLE; vready := '0'; vretry := '0';
verror := '0'; vgrant := '0';
hsize := HSIZE_WORD;
hwdata := msti.data;
hbusreq := msti.req;
if hbusreq = '1' then htrans := HTRANS_NONSEQ; end if;
haddr := msti.addr; hwrite := msti.write;
if (msti.req and r.ba and not r.retry) = '1' then
htrans := HTRANS_SEQ;
end if;
if (msti.req and r.bg and ahbmi.hready and not r.retry) = '1' then
vgrant := '1';
end if;
--1 kB burst boundary
if ahbmi.hready = '1' then
if haddr(9 downto 2) = "11111111" then
v.bb := '1';
else
v.bb := '0';
end if;
end if;
if (r.bb = '1') and (htrans /= HTRANS_IDLE) then
htrans := HTRANS_NONSEQ;
end if;
if r.ba = '1' then
if ahbmi.hready = '1' then
case ahbmi.hresp is
when HRESP_OKAY => vready := '1';
when HRESP_SPLIT | HRESP_RETRY => vretry := '1';
when HRESP_ERROR => verror := '1';
when others => null;
end case;
end if;
end if;
if (r.ba = '1') and
((ahbmi.hresp = HRESP_RETRY) or (ahbmi.hresp = HRESP_SPLIT))
then v.retry := not ahbmi.hready; else v.retry := '0'; end if;
if (r.ba = '1') and
(ahbmi.hresp = HRESP_ERROR)
then v.error := not ahbmi.hready; else v.error := '0'; end if;
if (r.retry or r.error) = '1' then htrans := HTRANS_IDLE; end if;
if ahbmi.hready = '1' then
v.bg := ahbmi.hgrant(hindex);
if (htrans = HTRANS_NONSEQ) or (htrans = HTRANS_SEQ) then
v.ba := r.bg;
else
v.ba := '0';
end if;
end if;
if rst = '0' then
v.bg := '0'; v.ba := '0'; v.bb := '0';
end if;
rin <= v;
msto.data <= ahbreadword(ahbmi.hrdata);
msto.error <= verror;
msto.retry <= vretry;
msto.ready <= vready;
msto.grant <= vgrant;
ahbmo.htrans <= htrans;
ahbmo.hsize <= hsize;
ahbmo.hbusreq <= hbusreq;
ahbmo.haddr <= haddr;
ahbmo.hwrite <= hwrite;
ahbmo.hwdata <= ahbdrivedata(hwdata);
end process;
regs : process(clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process;
ahbmo.hlock <= '0';
ahbmo.hburst <= HBURST_INCR;
ahbmo.hprot <= "0011";
ahbmo.hconfig <= hconfig;
ahbmo.hindex <= hindex;
ahbmo.hirq <= (others => '0');
end architecture;
| gpl-3.0 | dccd0229633aa0582ac61412222736b1 | 0.565626 | 3.601794 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/misc/svgactrl.vhd | 1 | 27,591 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: svgactrl
-- File: svgactrl.vhd
-- Author: Hans Soderlund
-- Modified: Jiri Gaisler, Edvin Catovic, Jan Andersson
-- Contact: [email protected]
-- Description: SVGA Controller core
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.misc.all;
entity svgactrl is
generic(
length : integer := 384; -- FIFO length in 32-bit words
part : integer := 128; -- FIFO-part length in 32-bit words
memtech : integer := DEFMEMTECH;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
hindex : integer := 0;
hirq : integer := 0;
clk0 : integer := 40000;
clk1 : integer := 20000;
clk2 : integer := 15385;
clk3 : integer := 0;
burstlen : integer range 2 to 8 := 8;
ahbaccsz : integer := 32;
asyncrst : integer range 0 to 1 := 0 -- Enable async. reset of VGA CD
);
port (
rst : in std_logic; -- Synchronous reset
clk : in std_logic;
vgaclk : in std_logic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
vgao : out apbvga_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
clk_sel : out std_logic_vector(1 downto 0);
arst : in std_ulogic := '1' -- Asynchronous reset
);
end ;
architecture rtl of svgactrl is
constant REVISION : amba_version_type := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_SVGACTRL, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
-- Calculates the required number of address bits for 32 bit buffer
function addrbits return integer is
begin
for i in 1 to 30 loop
if (2**i >= length) then return(i);
end if;
end loop;
return(30);
end function addrbits;
constant WPAC : integer := ahbaccsz/32; -- Words Per AHB Access.
constant FIFO_DW : integer := ahbaccsz; -- FIFO data width
constant FIFOCNTR : integer := log2(WPAC);
constant ABITS : integer := addrbits - FIFOCNTR; -- FIFO address bits
constant FIFOCNTL : integer := addrbits - 1;
subtype FIFO_CNT_R is natural range FIFOCNTL downto FIFOCNTR;
constant BURSTL : integer := burstlen + 1;
constant BURSTR : integer := log2(ahbaccsz/8);
type register_type is array (1 to 5) of std_logic_vector(31 downto 0);
type state_type is (running, not_running, reset);
type read_type is record
read_pointer : std_logic_vector(FIFOCNTL downto 0);
read_pointer_out : std_logic_vector(FIFOCNTL downto 0);
sync : std_logic_vector(2 downto 0);
data_out : std_logic_vector(23 downto 0);
lock : std_logic;
index : std_logic_vector(1 downto 0);
read_pointer_clut : std_logic_vector(7 downto 0);
hcounter : std_logic_vector(15 downto 0);
vcounter : std_logic_vector(15 downto 0);
fifo_ren : std_logic;
fifo_en : std_logic;
hsync : std_logic ;
vsync : std_logic ;
csync : std_logic ;
blank : std_logic ;
hsync2 : std_logic ;
vsync2 : std_logic ;
csync2 : std_logic ;
blank2 : std_logic ;
end record;
type control_type is record
int_reg : register_type;
state : state_type;
enable : std_logic;
reset : std_logic;
sync_c : std_logic_vector(2 downto 0);
sync_w : std_logic_vector(2 downto 0);
write_pointer_clut : std_logic_vector(7 downto 0);
datain_clut : std_logic_vector(23 downto 0);
write_en_clut : std_logic;
address : std_logic_vector(31 downto 0);
start : std_logic;
write_pointer : integer range 0 to length/WPAC;
ram_address : integer range 0 to length/WPAC;
data : std_logic_vector(FIFO_DW-1 downto 0);
level : integer range 0 to part/WPAC + 1;
status : integer range 0 to 3;
hpolarity : std_ulogic;
vpolarity : std_ulogic;
func : std_logic_vector(1 downto 0);
clk_sel : std_logic_vector(1 downto 0);
end record;
type sync_regs is record
s1 : std_logic_vector(2 downto 0);
s2 : std_logic_vector(2 downto 0);
s3 : std_logic_vector(2 downto 0);
end record;
signal t,tin : read_type;
signal r,rin : control_type;
signal sync_w : sync_regs;
signal sync_ra : sync_regs;
signal sync_rb : sync_regs;
signal sync_c : sync_regs;
signal read_status : std_logic_vector(2 downto 0);
signal write_status : std_logic_vector(2 downto 0);
signal write_en : std_logic;
signal res_mod :std_logic;
signal en_mod : std_logic;
signal fifo_en : std_logic;
signal dmai : ahb_dma_in_type;
signal dmao : ahb_dma_out_type;
signal equal : std_logic;
signal hmax : std_logic_vector(15 downto 0);
signal hfporch : std_logic_vector(15 downto 0);
signal hsyncpulse : std_logic_vector(15 downto 0);
signal hvideo : std_logic_vector(15 downto 0);
signal vmax : std_logic_vector(15 downto 0);
signal vfporch : std_logic_vector(15 downto 0);
signal vsyncpulse : std_logic_vector(15 downto 0);
signal vvideo : std_logic_vector(15 downto 0);
signal write_pointer_clut : std_logic_vector(7 downto 0);
signal read_pointer_clut : std_logic_vector(7 downto 0);
signal read_pointer_fifo : std_logic_vector((ABITS-1) downto 0);
signal write_pointer_fifo : std_logic_vector((ABITS-1) downto 0);
signal datain_clut : std_logic_vector(23 downto 0);
signal dataout_clut : std_logic_vector(23 downto 0);
signal dataout_fifo : std_logic_vector((FIFO_DW-1) downto 0);
signal datain_fifo : std_logic_vector((FIFO_DW-1) downto 0);
signal write_en_clut, read_en_clut : std_logic;
signal vcc : std_logic;
signal read_en_fifo, write_en_fifo : std_logic;
begin
vcc <= '1';
ram0 : syncram_2p
generic map (
tech => memtech,
abits => ABITS,
dbits => FIFO_DW,
sepclk => 1)
port map (
rclk => vgaclk,
renable => read_en_fifo,
raddress => read_pointer_fifo,
dataout => dataout_fifo,
wclk => clk,
write => write_en_fifo,
waddress => write_pointer_fifo,
datain => datain_fifo);
clutram : syncram_2p
generic map (
tech => memtech,
abits => 8,
dbits => 24,
sepclk => 1)
port map (
rclk => vgaclk,
renable => read_en_clut,
raddress => read_pointer_clut,
dataout => dataout_clut,
wclk => clk,
write => write_en_clut,
waddress => write_pointer_clut,
datain => datain_clut);
ahb_master : ahbmst generic map (hindex, hirq, VENDOR_GAISLER,
GAISLER_SVGACTRL, 0, 3, 1)
port map (rst, clk, dmai, dmao, ahbi, ahbo);
apbo.pirq <= (others => '0');
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
control_proc : process(r,rst,sync_c,apbi,fifo_en,write_en,read_status,dmao,res_mod,sync_w)
variable v : control_type;
variable apbrdata : std_logic_vector(31 downto 0);
variable apbwrite : std_logic;
variable we_fifo : std_logic;
begin
v := r; v.write_en_clut := '0'; apbrdata := (others =>'0'); we_fifo := '0';
---------------------------------------------------------------------------
-- Control. Handles the APB accesses and stores the internal registers
---------------------------------------------------------------------------
apbwrite := apbi.psel(pindex) and apbi.pwrite and apbi.penable;
case apbi.paddr(5 downto 2) is
when "0000" =>
-- Status register
if apbwrite = '1' then
v.enable := apbi.pwdata(0);
v.reset := apbi.pwdata(1);
v.hpolarity := apbi.pwdata(8);
v.vpolarity := apbi.pwdata(9);
v.func := apbi.pwdata(5 downto 4);
v.clk_sel := apbi.pwdata(7 downto 6);
end if;
apbrdata(9 downto 0) := r.vpolarity & r.hpolarity & r.clk_sel &
r.func & fifo_en & '0' & r.reset & r.enable;
when "1010" =>
-- CLUT access register
if apbwrite = '1' then
v.datain_clut := apbi.pwdata(23 downto 0);
v.write_pointer_clut := apbi.pwdata(31 downto 24);
v.write_en_clut := '1';
end if;
when "0001" =>
-- Video length register
if apbwrite = '1' then v.int_reg(1) := apbi.pwdata; end if;
apbrdata := r.int_reg(1);
when "0010" =>
-- Front porch register
if apbwrite = '1' then v.int_reg(2) := apbi.pwdata; end if;
apbrdata := r.int_reg(2);
when "0011" =>
-- Sync length register
if apbwrite = '1' then v.int_reg(3) := apbi.pwdata; end if;
apbrdata := r.int_reg(3);
when "0100" =>
-- Line length register
if apbwrite = '1' then v.int_reg(4) := apbi.pwdata; end if;
apbrdata := r.int_reg(4);
when "0101" =>
-- Framebuffer memory position register
if apbwrite = '1' then v.int_reg(5) := apbi.pwdata; end if;
apbrdata := r.int_reg(5);
-- Dynamic clock registers 0 - 3
when "0110" => apbrdata := conv_std_logic_vector(clk0,32);
when "0111" => apbrdata := conv_std_logic_vector(clk1,32);
when "1000" => apbrdata := conv_std_logic_vector(clk2,32);
when "1001" => apbrdata := conv_std_logic_vector(clk3,32);
when others =>
end case;
---------------------------------------------------------------------------
-- Control state machine
---------------------------------------------------------------------------
case r.state is
when running =>
if r.enable = '0' then
v.sync_c := "011";
v.state := not_running;
end if;
when not_running =>
if r.enable = '1' then
v.sync_c := "001";
v.state := reset;
end if;
when reset =>
if sync_c.s3 = "001" then
v.sync_c := "010";
v.state := running;
end if;
end case;
---------------------------------------------------------------------------
-- Control reset
---------------------------------------------------------------------------
if r.reset = '1' or rst = '0' then
v.state := not_running;
v.enable := '0';
v.int_reg := (others => (others => '0'));
v.sync_c := "011";
v.reset := '0';
v.clk_sel := "00";
end if;
---------------------------------------------------------------------------
-- Write part. This part reads from the memory framebuffer and places the
-- data in the designated fifo specified from the generic.
---------------------------------------------------------------------------
v.start := '0';
if write_en = '0' then
if (r.start or not dmao.active) = '1' then v.start := '1'; end if;
-- AHB access and FIFO write
if dmao.ready = '1' then
v.data := ahbreaddata(dmao.rdata, r.address(4 downto 2),
conv_std_logic_vector(log2(FIFO_DW/8), 3));
v.ram_address := v.write_pointer;
v.write_pointer := v.write_pointer + 1; we_fifo := '1';
if v.write_pointer = length/WPAC then
v.write_pointer := 0;
end if;
v.level := v.level + 1;
if dmao.haddr = (9 downto 0 => '0') then
v.address := (v.address(31 downto 10) + 1) & dmao.haddr;
else
v.address := v.address(31 downto 10) & dmao.haddr;
end if;
if (dmao.haddr(BURSTL downto 0) =
((BURSTL downto BURSTR => '1') & zero32(BURSTR-1 downto 0))) then
v.start := '0';
end if;
end if;
-- FIFO sync
v.sync_w := v.sync_w and read_status;
if v.level >= (part/WPAC-1) then
if read_status(r.status) = '1' and v.sync_w(r.status) = '0' and v.level = part/WPAC then
v.level := 0;
if r.status = 0 then
v.sync_w(2) := '1';
else
v.sync_w(r.status -1) := '1';
end if;
v.status := v.status + 1;
if v.status = 3 then
v.status := 0;
end if;
else
v.start := '0';
end if;
end if;
end if;
---------------------------------------------------------------------------
--- Write reset part
---------------------------------------------------------------------------
if res_mod = '0' or write_en = '1' then
if dmao.active = '0' then v.address := r.int_reg(5); end if;
v.start := '0';
v.sync_w := "000";
v.status := 1;
v.ram_address := 0;
v.write_pointer := 0;
v.level := 0;
end if;
if (r.start and dmao.active and not dmao.ready) = '1' then
v.start := '1';
end if;
---------------------------------------------------------------------------
-- Drive process outputs
---------------------------------------------------------------------------
rin <= v;
sync_c.s1 <= v.sync_c;
sync_w.s1 <= r.sync_w;
res_mod <= sync_c.s3(1);
en_mod <= sync_c.s3(0);
write_status <= sync_w.s3;
hvideo <= r.int_reg(1)(15 downto 0);
vvideo <= r.int_reg(1)(31 downto 16);
hfporch <= r.int_reg(2)(15 downto 0);
vfporch <= r.int_reg(2)(31 downto 16);
hsyncpulse <= r.int_reg(3)(15 downto 0);
vsyncpulse <= r.int_reg(3)(31 downto 16);
hmax <= r.int_reg(4)(15 downto 0);
vmax <= r.int_reg(4)(31 downto 16);
apbo.prdata <= apbrdata;
dmai.wdata <= (others => '0');
dmai.burst <= '1';
dmai.irq <= '0';
dmai.size <= conv_std_logic_vector(log2(ahbaccsz/8), 3);
dmai.write <= '0';
dmai.busy <= '0';
dmai.start <= r.start and r.enable;
dmai.address <= r.address;
write_pointer_fifo <= conv_std_logic_vector(v.ram_address, ABITS);
write_pointer_clut <= r.write_pointer_clut;
datain_fifo <= v.data;
datain_clut <= r.datain_clut;
write_en_clut <= r.write_en_clut;
clk_sel <= r.clk_sel;
write_en_fifo <= we_fifo;
end process;
read_proc : process(t, res_mod, en_mod, write_status, dataout_fifo, sync_rb,
dataout_clut, vmax, hmax, hvideo, hfporch, hsyncpulse,
vvideo, vfporch, vsyncpulse, sync_ra, r)
variable v : read_type;
variable inc_pointer : std_logic;
variable fifo_word : std_logic_vector(31 downto 0);
variable rpo1 : std_logic_vector(1 downto 0);
variable rpo2 : std_logic_vector(2 downto 0);
begin
v := t; fifo_word := (others => '0');
rpo1 := (others => '0'); rpo2 := (others => '0');
v.vsync2 := t.vsync; v.hsync2 := t.hsync; v.csync2 := t.csync;
v.blank2 := t.blank;
---------------------------------------------------------------------------
-- Sync signals generation
---------------------------------------------------------------------------
if en_mod = '0' then
-- vertical counter
if (t.vcounter = vmax ) and (t.hcounter = hmax ) then
v.vcounter := (others => '0');
elsif t.hcounter = hmax then
v.vcounter := t.vcounter + 1;
end if;
-- horizontal counter
if t.hcounter < hmax then v.hcounter := t.hcounter + 1;
else v.hcounter := (others => '0'); end if;
-- generate hsync
if t.hcounter < (hvideo+hfporch+hsyncpulse) and (t.hcounter > (hvideo+hfporch-1)) then
v.hsync := r.hpolarity;
else v.hsync := not r.hpolarity; end if;
-- generate vsync
if t.vcounter <= (vvideo+vfporch+vsyncpulse) and (t.vcounter > (vvideo+vfporch)) then
v.vsync := r.vpolarity;
else v.vsync := not r.vpolarity; end if;
--generate csync & blank signal
v.csync := not (v.hsync xor v.vsync);
v.blank := not t.fifo_ren;
--generate fifo_ren signal
if (t.hcounter = (hmax-1) and t.vcounter = vmax) or
(t.hcounter = (hmax-1) and t.vcounter < vvideo) then
v.fifo_ren := '0';
elsif t.hcounter = (hvideo-1) and t.vcounter <= vvideo then
v.fifo_ren := '1';
end if;
--generate fifo_en signal
if t.vcounter = vmax then
v.fifo_en := '0';
elsif t.vcounter = vvideo and t.hcounter = (hvideo-1) then
v.fifo_en := '1';
end if;
else
-- Prevent uninitialized fifo_en signal that leads to uninitialized
-- bit in APB status register
v.fifo_en := '1';
end if;
if r.func /= "01" then -- do not delay strobes when not using CLUT
v.vsync2 := v.vsync; v.hsync2 := v.hsync; v.csync2 := v.csync;
v.blank2 := v.blank;
end if;
---------------------------------------------------------------------------
-- Sync reset
---------------------------------------------------------------------------
if res_mod = '0' then
v.hcounter := hmax;
v.vcounter := vmax - 1;
v.hsync := r.hpolarity;
v.vsync := r.vpolarity;
v.blank := '0';
v.fifo_ren := '1';
v.fifo_en := '1';
end if;
---------------------------------------------------------------------------
-- Read from fifo.
---------------------------------------------------------------------------
inc_pointer := '0';
if t.fifo_en = '0' then
-- Fifo sync
if ((t.read_pointer_out = zero32(t.read_pointer_out'range) or
t.read_pointer_out = conv_std_logic_vector(part, FIFOCNTL+1) or
t.read_pointer_out = conv_std_logic_vector(2*part, FIFOCNTL+1)) and
t.fifo_ren = '0' and v.index = "00") then
case t.sync is
when "111" | "011" =>
if write_status(0) = '1' then
v.sync := "110"; v.lock := '0';
else v.lock := '1'; end if;
when "110" =>
if write_status(1) = '1' then
v.sync := "101"; v.lock := '0';
else v.lock := '1'; end if;
when "101" =>
if write_status(2) = '1' then
v.sync := "011"; v.lock := '0';
else v.lock := '1'; end if;
when others => null;
end case;
end if;
-------------------------------------------------------------------------
-- FIFO read and CLUT access
-------------------------------------------------------------------------
if t.fifo_ren = '0' and v.lock = '0' then
if FIFO_DW = 32 then
fifo_word(FIFO_DW-1 downto 0) := dataout_fifo(FIFO_DW-1 downto 0);
elsif FIFO_DW = 64 then
if t.read_pointer_out(0) = '0' then
fifo_word(FIFO_DW/2-1 downto 0) :=
dataout_fifo(FIFO_DW-1 downto FIFO_DW/2);
else
fifo_word(FIFO_DW/2-1 downto 0) :=
dataout_fifo(FIFO_DW/2-1 downto 0);
end if;
elsif FIFO_DW = 128 then
rpo1 := t.read_pointer_out(1 downto 0);
case rpo1 is
when "00" =>
fifo_word(FIFO_DW/4-1 downto 0) :=
dataout_fifo(FIFO_DW-1 downto 3*(FIFO_DW/4));
when "01" =>
fifo_word(FIFO_DW/4-1 downto 0) :=
dataout_fifo(3*(FIFO_DW/4)-1 downto 2*(FIFO_DW/4));
when "10" =>
fifo_word(FIFO_DW/4-1 downto 0) :=
dataout_fifo(2*(FIFO_DW/4)-1 downto 1*(FIFO_DW/4));
when others =>
fifo_word(FIFO_DW/4-1 downto 0) :=
dataout_fifo((FIFO_DW/4)-1 downto 0);
end case;
elsif FIFO_DW = 256 then
rpo2 := t.read_pointer_out(2 downto 0);
case rpo2 is
when "000" =>
fifo_word(FIFO_DW/8-1 downto 0) :=
dataout_fifo(FIFO_DW-1 downto 7*(FIFO_DW/8));
when "001" =>
fifo_word(FIFO_DW/8-1 downto 0) :=
dataout_fifo(7*(FIFO_DW/8)-1 downto 6*(FIFO_DW/8));
when "010" =>
fifo_word(FIFO_DW/8-1 downto 0) :=
dataout_fifo(6*(FIFO_DW/8)-1 downto 5*(FIFO_DW/8));
when "011" =>
fifo_word(FIFO_DW/8-1 downto 0) :=
dataout_fifo(5*(FIFO_DW/8)-1 downto 4*(FIFO_DW/8));
when "100" =>
fifo_word(FIFO_DW/8-1 downto 0) :=
dataout_fifo(4*(FIFO_DW/8)-1 downto 3*(FIFO_DW/8));
when "101" =>
fifo_word(FIFO_DW/8-1 downto 0) :=
dataout_fifo(3*(FIFO_DW/8)-1 downto 2*(FIFO_DW/8));
when "110" =>
fifo_word(FIFO_DW/8-1 downto 0) :=
dataout_fifo(2*(FIFO_DW/8)-1 downto 1*(FIFO_DW/8));
when others =>
fifo_word(FIFO_DW/8-1 downto 0) :=
dataout_fifo((FIFO_DW/8)-1 downto 0);
end case;
end if;
case r.func is
when "01" =>
if t.index = "00" then
v.read_pointer_clut := fifo_word(31 downto 24);
v.index := "01";
elsif t.index = "01" then
v.read_pointer_clut := fifo_word(23 downto 16);
v.index := "10";
elsif t.index = "10" then
v.read_pointer_clut := fifo_word(15 downto 8);
v.index := "11";
else
v.read_pointer_clut := fifo_word(7 downto 0);
v.index := "00"; inc_pointer := '1';
end if;
v.data_out := dataout_clut;
when "10" =>
if t.index = "00" then
v.data_out := fifo_word(31 downto 27) & "000" &
fifo_word(26 downto 21) & "00" &
fifo_word(20 downto 16) & "000";
v.index := "01";
else
v.data_out := fifo_word(15 downto 11) & "000" &
fifo_word(10 downto 5) & "00" &
fifo_word(4 downto 0) & "000";
v.index := "00"; inc_pointer := '1';
end if;
when "11" =>
v.data_out := fifo_word(23 downto 0);
v.index := "00"; inc_pointer := '1';
when others =>
v.data_out := (23 downto 0 => '1');
v.index := "00"; inc_pointer := '1';
end case;
else
v.data_out := (others => '0');
end if;
if inc_pointer = '1' then
v.read_pointer_out := t.read_pointer;
v.read_pointer := t.read_pointer + 1;
if v.read_pointer(FIFO_CNT_R) = conv_std_logic_vector(length/WPAC, ABITS) then
v.read_pointer := (others => '0');
end if;
if v.read_pointer_out(FIFO_CNT_R) = conv_std_logic_vector(length/WPAC, ABITS) then
v.read_pointer_out := (others => '0');
end if;
end if;
else
v.data_out := (others => '0');
end if;
---------------------------------------------------------------------------
-- FIFO read reset
---------------------------------------------------------------------------
if res_mod = '0' or t.fifo_en = '1' then
v.sync := "111";
v.read_pointer_out := (others => '0');
v.read_pointer := conv_std_logic_vector(1, ABITS+FIFOCNTR);
v.data_out := (others => '0');
v.lock := '1';
v.index := "00";
v.read_pointer_clut := (others => '0');
end if;
---------------------------------------------------------------------------
-- Assign outputs
---------------------------------------------------------------------------
tin <= v;
sync_ra.s1 <= t.sync;
sync_rb.s1 <= t.fifo_en & "00";
read_status <= sync_ra.s3;
write_en <= sync_rb.s3(2);
fifo_en <= t.fifo_en;
read_pointer_clut <= v.read_pointer_clut;
read_pointer_fifo <= v.read_pointer_out(FIFO_CNT_R);
read_en_fifo <= not v.fifo_ren;
read_en_clut <= not v.fifo_ren and not r.func(1) and r.func(0);
vgao.video_out_r <= t.data_out(23 downto 16);
vgao.video_out_g <= t.data_out(15 downto 8);
vgao.video_out_b <= t.data_out(7 downto 0);
vgao.hsync <= t.hsync2;
vgao.vsync <= t.vsync2;
vgao.comp_sync <= t.csync2;
vgao.blank <= t.blank2;
vgao.bitdepth <= r.func;
end process;
-----------------------------------------------------------------------------
-- Registers in system clock domain
-----------------------------------------------------------------------------
proc_clk : process(clk)
begin
if rising_edge(clk) then
r <= rin; -- Control
sync_ra.s2 <= sync_ra.s1; -- Write
sync_ra.s3 <= sync_ra.s2; -- Write
sync_rb.s2 <= sync_rb.s1; -- Write
sync_rb.s3 <= sync_rb.s2; -- Write
end if;
end process;
-----------------------------------------------------------------------------
-- Registers in video clock domain
-----------------------------------------------------------------------------
proc_vgaclk : process(arst, vgaclk)
begin
if asyncrst = 1 and arst = '0' then
t.fifo_en <= '1';
sync_c.s2 <= "011";
sync_c.s3 <= "011";
elsif rising_edge(vgaclk) then
t <= tin; -- Read
sync_c.s2 <= sync_c.s1; -- Control
sync_c.s3 <= sync_c.s2; -- Control
sync_w.s2 <= sync_w.s1; -- Read
sync_w.s3 <= sync_w.s2; -- Read
end if;
end process;
-- Boot message
-- pragma translate_off
bootmsg : report_version
generic map (
"svgactrl" & tost(pindex) & ": SVGA controller rev " &
tost(REVISION) & ", FIFO length: " & tost(length) &
", FIFO part length: " & tost(part) &
", FIFO address bits: " & tost(ABITS) &
", AHB access size: " & tost(ahbaccsz) & " bits");
-- pragma translate_on
end;
| gpl-3.0 | 21f0be28a005b1fdf932f2aaa4bd5a5a | 0.482259 | 3.684696 | false | false | false | false |
pwsoft/fpga_examples | quartus/chameleon/chameleon_v5_hwtest/chameleon_v5_hwtest_top.vhd | 1 | 36,637 | -- -----------------------------------------------------------------------
--
-- Turbo Chameleon
--
-- Multi purpose FPGA expansion for the commodore 64 computer
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2019 by Peter Wendrich ([email protected])
-- All Rights Reserved.
--
-- http://www.syntiac.com/chameleon.html
--
-- -----------------------------------------------------------------------
--
-- Turbo Chameleon 64 hardware test for version 5 hardware.
--
-- -----------------------------------------------------------------------
--
-- Hardware test can be executed when plug'ed into a C64, standalone or with docking-station.
-- In C64 mode the machine will startup normally as the Chameleon will be invisible to the machine.
-- The address-bus of the Chameleon is completely tri-stated in the hardware test.
-- The hardware test can also be used to test the docking-station. Additional icons become
-- visible when the docking station is connected.
--
--
-- Connect PS/2 keyboard
-- Connect PS/2 3 button/wheel mouse
-- Connect custom IEC test cable
-- Connections are made between IEC bus and VGA monitor detection lines as follows:
-- IEC CLK -> SDA (VGA)
-- IEC DAT -> SLC (VGA)
-- IEC ATN -> ID0 (VGA)
-- IEC SRQ -> ID2 (VGA)
--
-- For docking station testing additional hardware required:
-- C64 keyboard
-- Amiga 500 keyboard
-- Joystick with 9 pin connector or amiga mouse
--
-- -----------------------------------------------------------------------
-- Screen layout
--
-- Top left corner:
-- top row 3x blue represent buttons on the Chameleon
-- middle row 3x yellow represent the state of the PS/2 mouse buttons
-- bottom row left (green): solid if C64 detected, otherwise open
-- bottom row middle (green): solid if docking-station detected, otherwise open
-- bottom row right (red): flashes when a IR signal is detected.
-- Rest of top:
-- Color bars (32 steps for each primary color) and then combined to form gray-scale/white.
-- Running bar in middle:
-- Checking SDRAM memory (memory ok if green), turns red on error.
-- Left bottom:
-- IEC test patterns
-- Middle/Right bottom (only visible with docking-station):
-- Top is last scancode received from Amiga keyboard plus a single block representing reset next to it.
-- Next row is joysticks (from left to right port 4,3,2,1)
-- Below that is 8 by 8 matrix of C64 keyboard on the side is the restore-key state.
--
-- -----------------------------------------------------------------------
-- Chameleon hardware test
--
-- * Press 3 push buttons in sequence and check the blue rectangles in left upper corner
-- * Check LEDs flashing alternating off, red, green and both
-- * Check Num lock and Caps lock flashing on keyboard in sync with LEDs on Chameleon
-- * Check color bars in right upper corner
-- - Should be smooth (32 steps) colors in red, green, blue and gray/white.
-- * Move mouse and check yellow cursor follows movement
-- * Press middle mouse button on mouse, feedback on yellow rectangles
-- * Press left (mouse) button to play test sound on left channel
-- * Press right (mouse) button to play test sound on right channel
-- * Check result of SDRAM memory test (horizontal bar in the center of the screen)
-- * Wait until green/white progress bar has done one complete sequence.
-- If bar stops and turns red the memory test failed. Check the SDRAM!
-- * Check IEC test pattern (needs custom test cable connected)
-- Pattern in left lower corner should look like this:
-- # # # #
-- O # # #
-- # O # #
-- # # O #
-- # # # O
-- O O O O
-- See only open boxes in column? Possibly short to gnd.
-- See only closed boxes in column? Possibly a broken wire / bad solder.
-- See two open boxes in row 1-4? Possibly a short in breakout cable between IEC pins.
--
-- See this pattern? Most likely only VGA cable connected. Check custom IEC test cable is used.
-- O O # #
-- O O # #
-- O O # #
-- O O # #
-- O O # #
-- O O # #
--
-- All tests done
--
-- -----------------------------------------------------------------------
-- Docking-station hardware/software test
--
-- Connect Amiga keyboard
-- * Check LEDs flashing alternating off, drive, power and both
-- * Press 1/! key scancode should be 0000000#
-- * Release key scancode should be #000000#
-- * Press and release F10 key scancode should be ##0##00#
-- * Press CTRL+AMIGA+AMIGA and the single block next to the scancode should open.
--
-- Connect C64 keyboard
-- * No key pressed the 8 by 8 matrix should be all '#'
-- * Press single keys and observe only one hole in 8 by 8 matrix.
-- * Press restore key. The block on the right side 8 by 8 matrix should open.
--
-- Connect joystick to each joystick port.
-- The joysticks are represented by 4 groups of 7 blocks on the lower/right side
-- of the screen. From top to bottom the groups of blocks belong to port 1, 2, 3 then 4.
-- * Press Up. The most right block in a group should open.
-- * Press Down. The block second from the right in a group should open.
-- * Press Left. The block third from the right in a group should open.
-- * Press Right. The block third from the left in a group should open.
-- * Press fire. The block second from the left in a group should open.
-- * Press second fire (or right Amiga mouse button). The most left block in a group should open.
--
--
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- -----------------------------------------------------------------------
entity chameleon_v5_hwtest_top is
generic (
resetCycles: integer := 131071
);
port (
-- Clocks
clk8 : in std_logic;
phi2_n : in std_logic;
dotclock_n : in std_logic;
-- Bus
romlh_n : in std_logic;
ioef_n : in std_logic;
-- Buttons
freeze_n : in std_logic;
-- MMC/SPI
spi_miso : in std_logic;
mmc_cd_n : in std_logic;
mmc_wp : in std_logic;
-- MUX CPLD
mux_clk : out std_logic;
mux : out unsigned(3 downto 0);
mux_d : out unsigned(3 downto 0);
mux_q : in unsigned(3 downto 0);
-- USART
usart_tx : in std_logic;
usart_clk : in std_logic;
usart_rts : in std_logic;
usart_cts : in std_logic;
-- SDRam
sd_clk : out std_logic;
sd_data : inout unsigned(15 downto 0);
sd_addr : out unsigned(12 downto 0);
sd_we_n : out std_logic;
sd_ras_n : out std_logic;
sd_cas_n : out std_logic;
sd_ba_0 : out std_logic;
sd_ba_1 : out std_logic;
sd_ldqm : out std_logic;
sd_udqm : out std_logic;
-- Video
red : out unsigned(4 downto 0);
grn : out unsigned(4 downto 0);
blu : out unsigned(4 downto 0);
nHSync : out std_logic;
nVSync : out std_logic;
-- Audio
sigmaL : out std_logic;
sigmaR : out std_logic
);
end entity;
-- -----------------------------------------------------------------------
architecture rtl of chameleon_v5_hwtest_top is
constant version_str : string := "20190514";
type state_t is (TEST_IDLE, TEST_FILL, TEST_FILL_W, TEST_CHECK, TEST_CHECK_W, TEST_ERROR);
-- System clocks
signal sysclk : std_logic;
signal clk_150 : std_logic;
signal sd_clk_loc : std_logic;
signal clk_locked : std_logic;
signal ena_1mhz : std_logic;
signal ena_1khz : std_logic;
signal ena_1sec : std_logic;
signal no_clock : std_logic;
signal reset_button_n : std_logic;
-- Global signals
signal reset : std_logic;
signal end_of_pixel : std_logic;
signal end_of_frame : std_logic;
-- RAM Test
signal state : state_t := TEST_IDLE;
signal noise_bits : unsigned(7 downto 0);
-- MUX
signal mux_clk_reg : std_logic := '0';
signal mux_reg : unsigned(3 downto 0) := (others => '1');
signal mux_d_reg : unsigned(3 downto 0) := (others => '1');
-- LEDs
signal led_green : std_logic;
signal led_red : std_logic;
-- IR
signal ir : std_logic := '1';
-- PS/2 Keyboard
signal ps2_keyboard_clk_in : std_logic;
signal ps2_keyboard_dat_in : std_logic;
signal ps2_keyboard_clk_out : std_logic;
signal ps2_keyboard_dat_out : std_logic;
signal keyboard_trigger : std_logic;
signal keyboard_scancode : unsigned(7 downto 0);
-- PS/2 Mouse
signal ps2_mouse_clk_in: std_logic;
signal ps2_mouse_dat_in: std_logic;
signal ps2_mouse_clk_out: std_logic;
signal ps2_mouse_dat_out: std_logic;
signal mouse_present : std_logic;
signal mouse_active : std_logic;
signal mouse_trigger : std_logic;
signal mouse_left_button : std_logic;
signal mouse_middle_button : std_logic;
signal mouse_right_button : std_logic;
signal mouse_delta_x : signed(8 downto 0);
signal mouse_delta_y : signed(8 downto 0);
signal cursor_x : signed(11 downto 0) := to_signed(0, 12);
signal cursor_y : signed(11 downto 0) := to_signed(0, 12);
signal sdram_req : std_logic := '0';
signal sdram_ack : std_logic;
signal sdram_we : std_logic := '0';
signal sdram_a : unsigned(24 downto 0) := (others => '0');
signal sdram_d : unsigned(7 downto 0);
signal sdram_q : unsigned(7 downto 0);
-- VGA
signal currentX : unsigned(11 downto 0);
signal currentY : unsigned(11 downto 0);
signal hsync : std_logic;
signal vsync : std_logic;
signal iec_cnt : unsigned(2 downto 0);
signal iec_reg : unsigned(3 downto 0);
signal iec_result : unsigned(23 downto 0);
signal vga_id : unsigned(3 downto 0);
signal video_amiga : std_logic := '0';
-- Sound
signal sigma_l_reg : std_logic := '0';
signal sigma_r_reg : std_logic := '0';
-- Docking station
signal docking_station : std_logic;
signal docking_version : std_logic;
signal docking_keys : unsigned(63 downto 0);
signal docking_restore_n : std_logic;
signal docking_irq : std_logic;
signal irq_n : std_logic;
signal joystick1 : unsigned(6 downto 0);
signal joystick2 : unsigned(6 downto 0);
signal joystick3 : unsigned(6 downto 0);
signal joystick4 : unsigned(6 downto 0);
signal docking_amiga_reset_n : std_logic;
signal docking_amiga_scancode : unsigned(7 downto 0);
-- MIDI
signal midi_txd : std_logic;
signal midi_rxd : std_logic;
signal midi_data : unsigned(63 downto 0);
procedure drawunsigned(signal video : inout std_logic; x : signed; y : signed; xpos : integer; ypos : integer; t : unsigned) is
variable index : integer;
variable nibble : unsigned(3 downto 0);
variable pixels : unsigned(0 to 63);
begin
if (x >= xpos) and ((x - xpos) < 2*t'length)
and (y >= ypos) and ((y - ypos) < 8) then
pixels := (others => '0');
index := (t'length/4-1) - to_integer(x-xpos) / 8;
nibble := t(index*4+3 downto index*4);
case nibble is
when X"0" => pixels := X"1C22222A22221C00";
when X"1" => pixels := X"0818080808081C00";
when X"2" => pixels := X"1C22020408103E00";
when X"3" => pixels := X"1C22020C02221C00";
when X"4" => pixels := X"0C14243E04040E00";
when X"5" => pixels := X"3E20203C02221C00";
when X"6" => pixels := X"1C20203C22221C00";
when X"7" => pixels := X"3E02040810101000";
when X"8" => pixels := X"1C22221C22221C00";
when X"9" => pixels := X"1C22221E02021C00";
when X"A" => pixels := X"1C22223E22222200";
when X"B" => pixels := X"3C22223C22223C00";
when X"C" => pixels := X"1C22202020221C00";
when X"D" => pixels := X"3C22222222223C00";
when X"E" => pixels := X"3E20203C20203E00";
when X"F" => pixels := X"3E20203C20202000";
when others =>
null;
end case;
video <= pixels(to_integer(y - ypos) * 8 + (to_integer(x - xpos) mod 8));
end if;
end procedure;
procedure drawtext(signal video : inout std_logic; x : signed; y : signed; xpos : integer; ypos : integer; t : string) is
variable ch : character;
variable pixels : unsigned(0 to 63);
begin
if (x >= xpos) and ((x - xpos) < 8*t'length)
and (y >= ypos) and ((y - ypos) < 8) then
pixels := (others => '0');
ch := t(1 + (to_integer(x-xpos) / 8));
case ch is
when ''' => pixels := X"0808000000000000";
when '.' => pixels := X"00000000000C0C00";
-- when '/' => pixels := X"0002040810204000";
when '0' => pixels := X"1C22222A22221C00";
when '1' => pixels := X"0818080808081C00";
when '2' => pixels := X"1C22020408103E00";
when '3' => pixels := X"1C22020C02221C00";
when '4' => pixels := X"0C14243E04040E00";
when '5' => pixels := X"3E20203C02221C00";
when '6' => pixels := X"1C20203C22221C00";
when '7' => pixels := X"3E02040810101000";
when '8' => pixels := X"1C22221C22221C00";
when '9' => pixels := X"1C22221E02021C00";
when ':' => pixels := X"000C0C000C0C0000";
when 'A' => pixels := X"1C22223E22222200";
when 'B' => pixels := X"3C22223C22223C00";
when 'C' => pixels := X"1C22202020221C00";
when 'D' => pixels := X"3C22222222223C00";
when 'E' => pixels := X"3E20203C20203E00";
when 'F' => pixels := X"3E20203C20202000";
when 'G' => pixels := X"1C22202E22221C00";
when 'H' => pixels := X"2222223E22222200";
when 'I' => pixels := X"1C08080808081C00";
when 'K' => pixels := X"2222243824222200";
when 'L' => pixels := X"1010101010101E00";
when 'M' => pixels := X"4163554941414100";
when 'N' => pixels := X"22322A2A26222200";
when 'O' => pixels := X"1C22222222221C00";
when 'P' => pixels := X"1C12121C10101000";
when 'R' => pixels := X"3C22223C28242200";
when 'S' => pixels := X"1C22201C02221C00";
when 'T' => pixels := X"3E08080808080800";
when 'U' => pixels := X"2222222222221C00";
when 'V' => pixels := X"2222221414080800";
when 'W' => pixels := X"4141412A2A141400";
when 'Y' => pixels := X"2222140808080800";
when others =>
null;
end case;
video <= pixels(to_integer(y - ypos) * 8 + (to_integer(x - xpos) mod 8));
end if;
end procedure;
procedure box(signal video : inout std_logic; x : signed; y : signed; xpos : integer; ypos : integer; value : std_logic) is
begin
if (abs(x - xpos) < 5) and (abs(y - ypos) < 5) and (value = '1') then
video <= '1';
elsif (abs(x - xpos) = 5) and (abs(y - ypos) < 5) then
video <= '1';
elsif (abs(x - xpos) < 5) and (abs(y - ypos) = 5) then
video <= '1';
end if;
end procedure;
begin
nHSync <= not hsync;
nVSync <= not vsync;
-- -----------------------------------------------------------------------
-- Clocks and PLL
-- -----------------------------------------------------------------------
pllInstance : entity work.pll8
port map (
inclk0 => clk8,
c0 => sysclk,
c1 => open,
c2 => clk_150,
c3 => sd_clk_loc,
locked => clk_locked
);
sd_clk <= sd_clk_loc;
-- -----------------------------------------------------------------------
-- Reset
-- -----------------------------------------------------------------------
myReset : entity work.gen_reset
generic map (
resetCycles => resetCycles
)
port map (
clk => sysclk,
enable => '1',
button => '0',
reset => reset
);
-- -----------------------------------------------------------------------
-- 1 Mhz and 1 Khz clocks
-- -----------------------------------------------------------------------
my1Mhz : entity work.chameleon_1mhz
generic map (
clk_ticks_per_usec => 100
)
port map (
clk => sysclk,
ena_1mhz => ena_1mhz,
ena_1mhz_2 => open
);
my1Khz : entity work.chameleon_1khz
port map (
clk => sysclk,
ena_1mhz => ena_1mhz,
ena_1khz => ena_1khz
);
ena1sec_inst : entity work.chameleon_1khz
port map (
clk => sysclk,
ena_1mhz => ena_1khz,
ena_1khz => ena_1sec
);
-- -----------------------------------------------------------------------
-- SDRAM Controller
-- -----------------------------------------------------------------------
sdramInstance : entity work.chameleon_sdram
generic map (
casLatency => 3,
colAddrBits => 9,
rowAddrBits => 13,
enable_cpu6510_port => true
)
port map (
clk => clk_150,
reserve => '0',
sd_data => sd_data,
sd_addr => sd_addr,
sd_we_n => sd_we_n,
sd_ras_n => sd_ras_n,
sd_cas_n => sd_cas_n,
sd_ba_0 => sd_ba_0,
sd_ba_1 => sd_ba_1,
sd_ldqm => sd_ldqm,
sd_udqm => sd_udqm,
cpu6510_req => sdram_req,
cpu6510_ack => sdram_ack,
cpu6510_we => sdram_we,
cpu6510_a => sdram_a,
cpu6510_d => sdram_d,
cpu6510_q => sdram_q,
debugIdle => open,
debugRefresh => open
);
-- -----------------------------------------------------------------------
-- Memory test
-- -----------------------------------------------------------------------
myNoise : entity work.fractal_noise
generic map (
dBits => 25,
qBits => 8
)
port map (
d => sdram_a,
q => noise_bits
);
process(sysclk)
begin
if rising_edge(sysclk) then
case state is
when TEST_IDLE =>
sdram_a <= (others => '0');
sdram_we <= '0';
state <= TEST_FILL;
when TEST_FILL =>
sdram_req <= not sdram_req;
sdram_we <= '1';
sdram_d <= noise_bits;
state <= TEST_FILL_W;
when TEST_FILL_W =>
if sdram_req = sdram_ack then
sdram_a <= sdram_a + 1;
if sdram_a = "1111111111111111111111111" then
state <= TEST_CHECK;
else
state <= TEST_FILL;
end if;
end if;
when TEST_CHECK =>
sdram_req <= not sdram_req;
sdram_we <= '0';
state <= TEST_CHECK_W;
when TEST_CHECK_W =>
if sdram_req = sdram_ack then
sdram_a <= sdram_a + 1;
if sdram_q /= noise_bits then
state <= TEST_ERROR;
else
state <= TEST_CHECK;
end if;
end if;
when TEST_ERROR =>
null;
end case;
if reset = '1' then
state <= TEST_IDLE;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Sound test
-- -----------------------------------------------------------------------
process(sysclk)
begin
if rising_edge(sysclk) then
if ena_1khz = '1' then
if (mouse_left_button = '1') or (usart_cts = '0') then
sigma_l_reg <= not sigma_l_reg;
end if;
if (mouse_right_button = '1') or (reset_button_n = '0') then
sigma_r_reg <= not sigma_r_reg;
end if;
end if;
end if;
end process;
sigmaL <= sigma_l_reg;
sigmaR <= sigma_r_reg;
-- -----------------------------------------------------------------------
-- IEC test
-- -----------------------------------------------------------------------
process(sysclk)
begin
if rising_edge(sysclk) then
if ena_1khz = '1' then
case to_integer(iec_cnt) is
when 0 =>
iec_result(23) <= vga_id(0);
iec_result(22) <= vga_id(2);
iec_result(21) <= vga_id(1);
iec_result(20) <= vga_id(3);
iec_reg <= "1111";
when 1 =>
iec_result(3) <= vga_id(0);
iec_result(2) <= vga_id(2);
iec_result(1) <= vga_id(1);
iec_result(0) <= vga_id(3);
iec_reg <= "1110"; -- DAT
when 2 =>
iec_result(7) <= vga_id(0);
iec_result(6) <= vga_id(2);
iec_result(5) <= vga_id(1);
iec_result(4) <= vga_id(3);
iec_reg <= "1101"; -- CLK
when 3 =>
iec_result(11) <= vga_id(0);
iec_result(10) <= vga_id(2);
iec_result(9) <= vga_id(1);
iec_result(8) <= vga_id(3);
iec_reg <= "1011"; -- SRQ
when 4 =>
iec_result(15) <= vga_id(0);
iec_result(14) <= vga_id(2);
iec_result(13) <= vga_id(1);
iec_result(12) <= vga_id(3);
iec_reg <= "0111"; -- ATN
when 5 =>
iec_result(19) <= vga_id(0);
iec_result(18) <= vga_id(2);
iec_result(17) <= vga_id(1);
iec_result(16) <= vga_id(3);
iec_reg <= "0000";
when others =>
null;
end case;
iec_cnt <= iec_cnt + 1;
if iec_cnt = 5 then
iec_cnt <= (others => '0');
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Chameleon IO entity
-- -----------------------------------------------------------------------
chameleon_io_inst : entity work.chameleon_io
generic map (
enable_docking_station => true,
enable_docking_irq => true,
enable_vga_id_read => true,
enable_cdtv_remote => false,
enable_c64_joykeyb => true,
enable_c64_4player => true,
enable_raw_spi => false,
enable_iec_access => true
)
port map (
-- Clocks
clk => sysclk,
clk_mux => sysclk,
ena_1mhz => ena_1mhz,
reset => reset,
reset_ext => open,
-- Config
no_clock => no_clock,
docking_station => docking_station,
docking_version => docking_version,
vga_id => vga_id,
-- Chameleon FPGA pins
-- C64 Clocks
phi2_n => phi2_n,
dotclock_n => dotclock_n,
-- C64 cartridge control lines
io_ef_n => ioef_n,
rom_lh_n => romlh_n,
-- SPI bus
spi_miso => spi_miso,
-- CPLD multiplexer
mux_clk => mux_clk,
mux => mux,
mux_d => mux_d,
mux_q => mux_q,
-- LEDs
led_green => led_green,
led_red => led_red,
ir => ir,
-- PS/2 Keyboard
ps2_keyboard_clk_out => ps2_keyboard_clk_out,
ps2_keyboard_dat_out => ps2_keyboard_dat_out,
ps2_keyboard_clk_in => ps2_keyboard_clk_in,
ps2_keyboard_dat_in => ps2_keyboard_dat_in,
-- PS/2 Mouse
ps2_mouse_clk_out => ps2_mouse_clk_out,
ps2_mouse_dat_out => ps2_mouse_dat_out,
ps2_mouse_clk_in => ps2_mouse_clk_in,
ps2_mouse_dat_in => ps2_mouse_dat_in,
-- Buttons
button_reset_n => reset_button_n,
-- Joysticks
joystick1 => joystick1,
joystick2 => joystick2,
joystick3 => joystick3,
joystick4 => joystick4,
-- Keyboards
keys => docking_keys,
restore_key_n => docking_restore_n,
amiga_reset_n => docking_amiga_reset_n,
amiga_trigger => open,
amiga_scancode => docking_amiga_scancode,
-- IEC bus
iec_dat_out => iec_reg(0),
iec_clk_out => iec_reg(1),
iec_srq_out => iec_reg(2),
iec_atn_out => iec_reg(3),
iec_clk_in => open,
iec_dat_in => open,
iec_atn_in => open,
iec_srq_in => open,
-- MIDI (only available on Docking-station V2)
midi_txd => midi_txd,
midi_rxd => midi_rxd
);
-- -----------------------------------------------------------------------
-- LEDs
-- -----------------------------------------------------------------------
myGreenLed : entity work.chameleon_led
port map (
clk => sysclk,
clk_1khz => ena_1khz,
led_on => '0',
led_blink => '1',
led => led_red,
led_1hz => led_green
);
-- -----------------------------------------------------------------------
-- Keyboard controller
-- -----------------------------------------------------------------------
myKeyboard : entity work.io_ps2_keyboard
generic map (
ticksPerUsec => 100
)
port map (
clk => sysclk,
reset => reset,
ps2_clk_in => ps2_keyboard_clk_in,
ps2_dat_in => ps2_keyboard_dat_in,
ps2_clk_out => ps2_keyboard_clk_out,
ps2_dat_out => ps2_keyboard_dat_out,
-- Flash caps and num lock LEDs
caps_lock => led_green,
num_lock => led_red,
scroll_lock => '0',
trigger => keyboard_trigger,
scancode => keyboard_scancode
);
-- -----------------------------------------------------------------------
-- Mouse controller
-- -----------------------------------------------------------------------
myMouse : entity work.io_ps2_mouse
generic map (
ticksPerUsec => 100
)
port map (
clk => sysclk,
reset => reset,
ps2_clk_in => ps2_mouse_clk_in,
ps2_dat_in => ps2_mouse_dat_in,
ps2_clk_out => ps2_mouse_clk_out,
ps2_dat_out => ps2_mouse_dat_out,
mousePresent => mouse_present,
trigger => mouse_trigger,
leftButton => mouse_left_button,
middleButton => mouse_middle_button,
rightButton => mouse_right_button,
deltaX => mouse_delta_x,
deltaY => mouse_delta_y
);
-- -----------------------------------------------------------------------
-- VGA timing configured for 640x480
-- -----------------------------------------------------------------------
myVgaMaster : entity work.video_vga_master
generic map (
clkDivBits => 4
)
port map (
clk => sysclk,
-- 100 Mhz / (3+1) = 25 Mhz
clkDiv => X"3",
hSync => hSync,
vSync => vSync,
endOfPixel => end_of_pixel,
endOfLine => open,
endOfFrame => end_of_frame,
currentX => currentX,
currentY => currentY,
-- Setup 640x480@60hz needs ~25 Mhz
hSyncPol => '0',
vSyncPol => '0',
xSize => to_unsigned(800, 12),
ySize => to_unsigned(525, 12),
xSyncFr => to_unsigned(656, 12), -- Sync pulse 96
xSyncTo => to_unsigned(752, 12),
ySyncFr => to_unsigned(500, 12), -- Sync pulse 2
ySyncTo => to_unsigned(502, 12)
);
-- -----------------------------------------------------------------------
--
-- Reposition mouse cursor.
-- I like to move it, move it. You like to move it, move it.
-- We like to move it, move it. So just move it!
-- -----------------------------------------------------------------------
process(sysclk)
variable newX : signed(11 downto 0);
variable newY : signed(11 downto 0);
begin
if rising_edge(sysclk) then
--
-- Calculate new cursor coordinates
-- deltaY is subtracted as line count runs top to bottom on the screen.
newX := cursor_x + mouse_delta_x;
newY := cursor_y - mouse_delta_y;
--
-- Limit mouse cursor to screen
if newX > 640 then
newX := to_signed(640, 12);
end if;
if newX < 0 then
newX := to_signed(0, 12);
end if;
if newY > 480 then
newY := to_signed(480, 12);
end if;
if newY < 0 then
newY := to_signed(0, 12);
end if;
--
-- Update cursor location
if mouse_trigger = '1' then
cursor_x <= newX;
cursor_y <= newY;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Amiga scancode
-- -----------------------------------------------------------------------
process(sysclk) is
variable x : signed(11 downto 0);
variable y : signed(11 downto 0);
begin
x := signed(currentX);
y := signed(currentY);
if rising_edge(sysclk) then
video_amiga <= '0';
box(video_amiga, x, y, 144 + 9*16, 288, docking_amiga_reset_n);
for i in 0 to 7 loop
box(video_amiga, x, y, 144 + i*16, 288, docking_amiga_scancode(7-i));
end loop;
end if;
end process;
-- -----------------------------------------------------------------------
-- Midi ports on Docking-station V2
-- -----------------------------------------------------------------------
midi_blk : block
signal empty : std_logic;
signal uart_d : unsigned(7 downto 0) := (others => '0');
signal uart_d_trig : std_logic;
signal uart_q : unsigned(7 downto 0);
signal uart_q_trig : std_logic;
signal midi_data_reg : unsigned(63 downto 0) := (others => '0');
begin
midi_data <= midi_data_reg;
uart_inst : entity work.gen_uart
generic map (
bits => 8,
baud => 31250,
ticksPerUsec => 100
)
port map (
clk => sysclk,
d => uart_d,
d_trigger => uart_d_trig,
d_empty => empty,
q => uart_q,
q_trigger => uart_q_trig,
serial_rxd => midi_rxd,
serial_txd => midi_txd
);
process(sysclk)
begin
if rising_edge(sysclk) then
if uart_q_trig = '1' then
midi_data_reg <= midi_data_reg(55 downto 0) & uart_q;
end if;
end if;
end process;
process(sysclk)
begin
if rising_edge(sysclk) then
uart_d_trig <= '0';
if ena_1sec = '1' then
uart_d <= uart_d + 1;
uart_d_trig <= '1';
end if;
end if;
end process;
end block;
-- -----------------------------------------------------------------------
-- VGA colors
-- -----------------------------------------------------------------------
vga_colors_blk : block
signal vid_joystick_results : std_logic;
signal vid_keyboard_results : std_logic;
signal vid_midi_results : std_logic;
signal vid_mode : std_logic;
signal vid_version : std_logic;
begin
process(sysclk)
variable x : signed(11 downto 0);
variable y : signed(11 downto 0);
begin
x := signed(currentX);
y := signed(currentY);
if rising_edge(sysclk) then
vid_joystick_results <= '0';
drawtext(vid_joystick_results, x, y, 476, 288-5, "3 2 1 R L D U");
drawtext(vid_joystick_results, x, y, 416, 304-5, "PORT 1");
drawtext(vid_joystick_results, x, y, 416, 320-5, "PORT 2");
drawtext(vid_joystick_results, x, y, 416, 336-5, "PORT 3");
drawtext(vid_joystick_results, x, y, 416, 352-5, "PORT 4");
for i in 0 to 6 loop
box(vid_joystick_results, x, y, 480 + i*16, 304, joystick1(6-i));
box(vid_joystick_results, x, y, 480 + i*16, 320, joystick2(6-i));
box(vid_joystick_results, x, y, 480 + i*16, 336, joystick3(6-i));
box(vid_joystick_results, x, y, 480 + i*16, 352, joystick4(6-i));
end loop;
end if;
end process;
process(sysclk) is
variable x : signed(11 downto 0);
variable y : signed(11 downto 0);
begin
x := signed(currentX);
y := signed(currentY);
if rising_edge(sysclk) then
vid_keyboard_results <= '0';
for row in 0 to 7 loop
for col in 0 to 7 loop
box(vid_keyboard_results, x, y, 144 + col*16, 352 + row*16, docking_keys(row*8 + col));
end loop;
end loop;
box(vid_keyboard_results, x, y, 144 + 9*16, 352, docking_restore_n);
end if;
end process;
process(sysclk) is
variable x : signed(11 downto 0);
variable y : signed(11 downto 0);
begin
x := signed(currentX);
y := signed(currentY);
if rising_edge(sysclk) then
vid_midi_results <= '0';
if docking_version = '1' then
drawtext(vid_midi_results, x, y, 320, 400, "MIDI:");
drawunsigned(vid_midi_results, x, y, 320, 408, midi_data);
end if;
end if;
end process;
process(sysclk) is
variable x : signed(11 downto 0);
variable y : signed(11 downto 0);
begin
x := signed(currentX);
y := signed(currentY);
if rising_edge(sysclk) then
vid_mode <= '0';
if (docking_station = '1') and (docking_version = '0') then
drawtext(vid_mode, x, y, 320, 464, "DOCKINGSTATION V1");
elsif (docking_station = '1') and (docking_version = '1') then
drawtext(vid_mode, x, y, 320, 464, "DOCKINGSTATION V2");
elsif no_clock = '1' then
drawtext(vid_mode, x, y, 320, 464, "STANDALONE");
else
drawtext(vid_mode, x, y, 320, 464, "CARTRIDGE");
end if;
end if;
end process;
process(sysclk) is
variable x : signed(11 downto 0);
variable y : signed(11 downto 0);
begin
x := signed(currentX);
y := signed(currentY);
if rising_edge(sysclk) then
vid_version <= '0';
drawtext(vid_version, x, y, 560, 464, version_str);
end if;
end process;
process(sysclk)
variable x : signed(11 downto 0);
variable y : signed(11 downto 0);
begin
x := signed(currentX);
y := signed(currentY);
if rising_edge(sysclk) then
if end_of_pixel = '1' then
red <= (others => '0');
grn <= (others => '0');
blu <= (others => '0');
if currentY < 256 then
case currentX(11 downto 7) is
when "00001" =>
red <= currentX(6 downto 2);
when "00010" =>
grn <= currentX(6 downto 2);
when "00011" =>
blu <= currentX(6 downto 2);
when "00100" =>
red <= currentX(6 downto 2);
grn <= currentX(6 downto 2);
blu <= currentX(6 downto 2);
when others =>
null;
end case;
end if;
-- SDRAM check
if (currentY >= 256) and (currentY < 272) then
if (state = TEST_FILL) or (state = TEST_FILL_W) then
if currentX > sdram_a(24 downto 16) then
red <= (others => '1');
grn <= (others => '1');
blu <= (others => '1');
else
blu <= (others => '1');
end if;
end if;
if (state = TEST_CHECK) or (state = TEST_CHECK_W) then
if currentX > sdram_a(24 downto 16) then
red <= (others => '1');
grn <= (others => '1');
blu <= (others => '1');
else
grn <= (others => '1');
end if;
end if;
if (state = TEST_ERROR) then
if currentX > sdram_a(24 downto 16) then
red <= "00111";
else
red <= (others => '1');
end if;
end if;
end if;
-- Draw 3 push button tests
if (abs(x - 64) < 7) and (abs(y - 64) < 7) and (usart_cts = '0') then
blu <= (others => '1');
elsif (abs(x - 64) = 7) and (abs(y - 64) < 7) then
blu <= (others => '1');
elsif (abs(x - 64) < 7) and (abs(y - 64) = 7) then
blu <= (others => '1');
end if;
if (abs(x - 96) < 7) and (abs(y - 64) < 7) and (freeze_n = '0') then
blu <= (others => '1');
elsif (abs(x - 96) = 7) and (abs(y - 64) < 7) then
blu <= (others => '1');
elsif (abs(x - 96) < 7) and (abs(y - 64) = 7) then
blu <= (others => '1');
end if;
if (abs(x - 128) < 7) and (abs(y - 64) < 7) and (reset_button_n = '0') then
blu <= (others => '1');
elsif (abs(x - 128) = 7) and (abs(y - 64) < 7) then
blu <= (others => '1');
elsif (abs(x - 128) < 7) and (abs(y - 64) = 7) then
blu <= (others => '1');
end if;
-- Draw mouse button tests
if (abs(x - 64) < 7) and (abs(y - 128) < 7) and (mouse_left_button = '1') then
red <= (others => '1');
grn <= (others => '1');
elsif (abs(x - 64) = 7) and (abs(y - 128) < 7) then
red <= (others => '1');
grn <= (others => '1');
elsif (abs(x - 64) < 7) and (abs(y - 128) = 7) then
red <= (others => '1');
grn <= (others => '1');
end if;
if (abs(x - 96) < 7) and (abs(y - 128) < 7) and (mouse_middle_button = '1') then
red <= (others => '1');
grn <= (others => '1');
elsif (abs(x - 96) = 7) and (abs(y - 128) < 7) then
red <= (others => '1');
grn <= (others => '1');
elsif (abs(x - 96) < 7) and (abs(y - 128) = 7) then
red <= (others => '1');
grn <= (others => '1');
end if;
if (abs(x - 128) < 7) and (abs(y - 128) < 7) and (mouse_right_button = '1') then
red <= (others => '1');
grn <= (others => '1');
elsif (abs(x - 128) = 7) and (abs(y - 128) < 7) then
red <= (others => '1');
grn <= (others => '1');
elsif (abs(x - 128) < 7) and (abs(y - 128) = 7) then
red <= (others => '1');
grn <= (others => '1');
end if;
-- clock
if (abs(x - 64) < 7) and (abs(y - 192) < 7) and (no_clock = '0') then
grn <= (others => '1');
elsif (abs(x - 64) = 7) and (abs(y - 192) < 7) then
grn <= (others => '1');
elsif (abs(x - 64) < 7) and (abs(y - 192) = 7) then
grn <= (others => '1');
end if;
-- docking station
if (abs(x - 96) < 7) and (abs(y - 192) < 7) and (docking_station = '1') then
grn <= (others => '1');
elsif (abs(x - 96) = 7) and (abs(y - 192) < 7) then
grn <= (others => '1');
elsif (abs(x - 96) < 7) and (abs(y - 192) = 7) then
grn <= (others => '1');
end if;
-- IR tester
if (abs(x - 128) < 7) and (abs(y - 192) < 7) and (ir = '0') then
red <= (others => '1');
elsif (abs(x - 128) = 7) and (abs(y - 192) < 7) then
red <= (others => '1');
elsif (abs(x - 128) < 7) and (abs(y - 192) = 7) then
red <= (others => '1');
end if;
-- Draw IEC test pattern
for dy in 0 to 5 loop
for dx in 0 to 3 loop
if abs(x - (64 + (3-dx)*16)) < 5 and (abs(y - (320 + dy*16)) < 5) and (iec_result(dy*4+dx) = '1') then
red <= (others => '1');
grn <= (others => '1');
blu <= (others => '1');
elsif abs(x - (64 + (3-dx)*16)) = 5 and (abs(y - (320 + dy*16)) < 5) then
red <= (others => '1');
grn <= (others => '1');
blu <= (others => '1');
elsif abs(x - (64 + (3-dx)*16)) < 5 and (abs(y - (320 + dy*16)) = 5) then
red <= (others => '1');
grn <= (others => '1');
blu <= (others => '1');
end if;
end loop;
end loop;
--
-- Draw test results
if (vid_joystick_results
or vid_keyboard_results
or vid_midi_results
or video_amiga
or vid_mode
or vid_version) = '1' then
red <= (others => '1');
grn <= (others => '1');
blu <= (others => '1');
end if;
-- Draw mouse cursor
if mouse_present = '1' then
if (abs(x - cursor_x) < 5) and (abs(y - cursor_y) < 5) then
red <= (others => '1');
grn <= (others => '1');
blu <= (others => '0');
end if;
end if;
--
-- One pixel border around the screen
if (currentX = 0) or (currentX = 639) or (currentY =0) or (currentY = 479) then
red <= (others => '1');
grn <= (others => '1');
blu <= (others => '1');
end if;
--
-- Never draw pixels outside the visual area
if (currentX >= 640) or (currentY >= 480) then
red <= (others => '0');
grn <= (others => '0');
blu <= (others => '0');
end if;
end if;
end if;
end process;
end block;
end architecture;
| lgpl-2.1 | 28d70169c7ce59d73e981ffac36f6be5 | 0.539345 | 3.010435 | false | false | false | false |
EliasLuiz/TCC | Leon3/boards/terasic-de4/uniphy_266.vhd | 1 | 40,589 | -- megafunction wizard: %DDR2 SDRAM Controller with UniPHY v15.0%
-- GENERATION: XML
-- uniphy.vhd
-- Generated using ACDS version 15.0 145
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity uniphy is
port (
pll_ref_clk : in std_logic := '0'; -- pll_ref_clk.clk
global_reset_n : in std_logic := '0'; -- global_reset.reset_n
soft_reset_n : in std_logic := '0'; -- soft_reset.reset_n
afi_clk : out std_logic; -- afi_clk.clk
afi_half_clk : out std_logic; -- afi_half_clk.clk
afi_reset_n : out std_logic; -- afi_reset.reset_n
afi_reset_export_n : out std_logic; -- afi_reset_export.reset_n
mem_a : out std_logic_vector(13 downto 0); -- memory.mem_a
mem_ba : out std_logic_vector(2 downto 0); -- .mem_ba
mem_ck : out std_logic_vector(1 downto 0); -- .mem_ck
mem_ck_n : out std_logic_vector(1 downto 0); -- .mem_ck_n
mem_cke : out std_logic_vector(0 downto 0); -- .mem_cke
mem_cs_n : out std_logic_vector(0 downto 0); -- .mem_cs_n
mem_dm : out std_logic_vector(7 downto 0); -- .mem_dm
mem_ras_n : out std_logic_vector(0 downto 0); -- .mem_ras_n
mem_cas_n : out std_logic_vector(0 downto 0); -- .mem_cas_n
mem_we_n : out std_logic_vector(0 downto 0); -- .mem_we_n
mem_dq : inout std_logic_vector(63 downto 0) := (others => '0'); -- .mem_dq
mem_dqs : inout std_logic_vector(7 downto 0) := (others => '0'); -- .mem_dqs
mem_dqs_n : inout std_logic_vector(7 downto 0) := (others => '0'); -- .mem_dqs_n
mem_odt : out std_logic_vector(0 downto 0); -- .mem_odt
afi_addr : in std_logic_vector(13 downto 0) := (others => '0'); -- afi.afi_addr
afi_ba : in std_logic_vector(2 downto 0) := (others => '0'); -- .afi_ba
afi_cke : in std_logic_vector(0 downto 0) := (others => '0'); -- .afi_cke
afi_cs_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .afi_cs_n
afi_ras_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .afi_ras_n
afi_we_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .afi_we_n
afi_cas_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .afi_cas_n
afi_odt : in std_logic_vector(0 downto 0) := (others => '0'); -- .afi_odt
afi_dqs_burst : in std_logic_vector(7 downto 0) := (others => '0'); -- .afi_dqs_burst
afi_wdata_valid : in std_logic_vector(7 downto 0) := (others => '0'); -- .afi_wdata_valid
afi_wdata : in std_logic_vector(127 downto 0) := (others => '0'); -- .afi_wdata
afi_dm : in std_logic_vector(15 downto 0) := (others => '0'); -- .afi_dm
afi_rdata : out std_logic_vector(127 downto 0); -- .afi_rdata
afi_rdata_en : in std_logic_vector(0 downto 0) := (others => '0'); -- .afi_rdata_en
afi_rdata_en_full : in std_logic_vector(0 downto 0) := (others => '0'); -- .afi_rdata_en_full
afi_rdata_valid : out std_logic_vector(0 downto 0); -- .afi_rdata_valid
afi_mem_clk_disable : in std_logic_vector(1 downto 0) := (others => '0'); -- .afi_mem_clk_disable
afi_init_req : in std_logic := '0'; -- .afi_init_req
afi_cal_req : in std_logic := '0'; -- .afi_cal_req
afi_wlat : out std_logic_vector(5 downto 0); -- .afi_wlat
afi_rlat : out std_logic_vector(5 downto 0); -- .afi_rlat
afi_cal_success : out std_logic; -- .afi_cal_success
afi_cal_fail : out std_logic; -- .afi_cal_fail
oct_rdn : in std_logic := '0'; -- oct.rdn
oct_rup : in std_logic := '0' -- .rup
);
end entity uniphy;
architecture rtl of uniphy is
component uniphy_0002 is
port (
pll_ref_clk : in std_logic := 'X'; -- clk
global_reset_n : in std_logic := 'X'; -- reset_n
soft_reset_n : in std_logic := 'X'; -- reset_n
afi_clk : out std_logic; -- clk
afi_half_clk : out std_logic; -- clk
afi_reset_n : out std_logic; -- reset_n
afi_reset_export_n : out std_logic; -- reset_n
mem_a : out std_logic_vector(13 downto 0); -- mem_a
mem_ba : out std_logic_vector(2 downto 0); -- mem_ba
mem_ck : out std_logic_vector(1 downto 0); -- mem_ck
mem_ck_n : out std_logic_vector(1 downto 0); -- mem_ck_n
mem_cke : out std_logic_vector(0 downto 0); -- mem_cke
mem_cs_n : out std_logic_vector(0 downto 0); -- mem_cs_n
mem_dm : out std_logic_vector(7 downto 0); -- mem_dm
mem_ras_n : out std_logic_vector(0 downto 0); -- mem_ras_n
mem_cas_n : out std_logic_vector(0 downto 0); -- mem_cas_n
mem_we_n : out std_logic_vector(0 downto 0); -- mem_we_n
mem_dq : inout std_logic_vector(63 downto 0) := (others => 'X'); -- mem_dq
mem_dqs : inout std_logic_vector(7 downto 0) := (others => 'X'); -- mem_dqs
mem_dqs_n : inout std_logic_vector(7 downto 0) := (others => 'X'); -- mem_dqs_n
mem_odt : out std_logic_vector(0 downto 0); -- mem_odt
afi_addr : in std_logic_vector(13 downto 0) := (others => 'X'); -- afi_addr
afi_ba : in std_logic_vector(2 downto 0) := (others => 'X'); -- afi_ba
afi_cke : in std_logic_vector(0 downto 0) := (others => 'X'); -- afi_cke
afi_cs_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- afi_cs_n
afi_ras_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- afi_ras_n
afi_we_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- afi_we_n
afi_cas_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- afi_cas_n
afi_odt : in std_logic_vector(0 downto 0) := (others => 'X'); -- afi_odt
afi_dqs_burst : in std_logic_vector(7 downto 0) := (others => 'X'); -- afi_dqs_burst
afi_wdata_valid : in std_logic_vector(7 downto 0) := (others => 'X'); -- afi_wdata_valid
afi_wdata : in std_logic_vector(127 downto 0) := (others => 'X'); -- afi_wdata
afi_dm : in std_logic_vector(15 downto 0) := (others => 'X'); -- afi_dm
afi_rdata : out std_logic_vector(127 downto 0); -- afi_rdata
afi_rdata_en : in std_logic_vector(0 downto 0) := (others => 'X'); -- afi_rdata_en
afi_rdata_en_full : in std_logic_vector(0 downto 0) := (others => 'X'); -- afi_rdata_en_full
afi_rdata_valid : out std_logic_vector(0 downto 0); -- afi_rdata_valid
afi_mem_clk_disable : in std_logic_vector(1 downto 0) := (others => 'X'); -- afi_mem_clk_disable
afi_init_req : in std_logic := 'X'; -- afi_init_req
afi_cal_req : in std_logic := 'X'; -- afi_cal_req
afi_wlat : out std_logic_vector(5 downto 0); -- afi_wlat
afi_rlat : out std_logic_vector(5 downto 0); -- afi_rlat
afi_cal_success : out std_logic; -- afi_cal_success
afi_cal_fail : out std_logic; -- afi_cal_fail
oct_rdn : in std_logic := 'X'; -- rdn
oct_rup : in std_logic := 'X' -- rup
);
end component uniphy_0002;
begin
uniphy_inst : component uniphy_0002
port map (
pll_ref_clk => pll_ref_clk, -- pll_ref_clk.clk
global_reset_n => global_reset_n, -- global_reset.reset_n
soft_reset_n => soft_reset_n, -- soft_reset.reset_n
afi_clk => afi_clk, -- afi_clk.clk
afi_half_clk => afi_half_clk, -- afi_half_clk.clk
afi_reset_n => afi_reset_n, -- afi_reset.reset_n
afi_reset_export_n => afi_reset_export_n, -- afi_reset_export.reset_n
mem_a => mem_a, -- memory.mem_a
mem_ba => mem_ba, -- .mem_ba
mem_ck => mem_ck, -- .mem_ck
mem_ck_n => mem_ck_n, -- .mem_ck_n
mem_cke => mem_cke, -- .mem_cke
mem_cs_n => mem_cs_n, -- .mem_cs_n
mem_dm => mem_dm, -- .mem_dm
mem_ras_n => mem_ras_n, -- .mem_ras_n
mem_cas_n => mem_cas_n, -- .mem_cas_n
mem_we_n => mem_we_n, -- .mem_we_n
mem_dq => mem_dq, -- .mem_dq
mem_dqs => mem_dqs, -- .mem_dqs
mem_dqs_n => mem_dqs_n, -- .mem_dqs_n
mem_odt => mem_odt, -- .mem_odt
afi_addr => afi_addr, -- afi.afi_addr
afi_ba => afi_ba, -- .afi_ba
afi_cke => afi_cke, -- .afi_cke
afi_cs_n => afi_cs_n, -- .afi_cs_n
afi_ras_n => afi_ras_n, -- .afi_ras_n
afi_we_n => afi_we_n, -- .afi_we_n
afi_cas_n => afi_cas_n, -- .afi_cas_n
afi_odt => afi_odt, -- .afi_odt
afi_dqs_burst => afi_dqs_burst, -- .afi_dqs_burst
afi_wdata_valid => afi_wdata_valid, -- .afi_wdata_valid
afi_wdata => afi_wdata, -- .afi_wdata
afi_dm => afi_dm, -- .afi_dm
afi_rdata => afi_rdata, -- .afi_rdata
afi_rdata_en => afi_rdata_en, -- .afi_rdata_en
afi_rdata_en_full => afi_rdata_en_full, -- .afi_rdata_en_full
afi_rdata_valid => afi_rdata_valid, -- .afi_rdata_valid
afi_mem_clk_disable => afi_mem_clk_disable, -- .afi_mem_clk_disable
afi_init_req => afi_init_req, -- .afi_init_req
afi_cal_req => afi_cal_req, -- .afi_cal_req
afi_wlat => afi_wlat, -- .afi_wlat
afi_rlat => afi_rlat, -- .afi_rlat
afi_cal_success => afi_cal_success, -- .afi_cal_success
afi_cal_fail => afi_cal_fail, -- .afi_cal_fail
oct_rdn => oct_rdn, -- oct.rdn
oct_rup => oct_rup -- .rup
);
end architecture rtl; -- of uniphy
-- Retrieval info: <?xml version="1.0"?>
--<!--
-- Generated by Altera MegaWizard Launcher Utility version 1.0
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- ************************************************************
-- Copyright (C) 1991-2015 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
---->
-- Retrieval info: <instance entity-name="altera_mem_if_ddr2_emif" version="15.0" >
-- Retrieval info: <generic name="RATE" value="Full" />
-- Retrieval info: <generic name="MEM_CLK_FREQ" value="266.666666" />
-- Retrieval info: <generic name="USE_MEM_CLK_FREQ" value="false" />
-- Retrieval info: <generic name="FORCE_DQS_TRACKING" value="AUTO" />
-- Retrieval info: <generic name="FORCE_SHADOW_REGS" value="AUTO" />
-- Retrieval info: <generic name="MRS_MIRROR_PING_PONG_ATSO" value="false" />
-- Retrieval info: <generic name="MEM_VENDOR" value="Micron" />
-- Retrieval info: <generic name="MEM_FORMAT" value="UNBUFFERED" />
-- Retrieval info: <generic name="DISCRETE_FLY_BY" value="true" />
-- Retrieval info: <generic name="DEVICE_DEPTH" value="1" />
-- Retrieval info: <generic name="MEM_MIRROR_ADDRESSING" value="0" />
-- Retrieval info: <generic name="MEM_CLK_FREQ_MAX" value="400.0" />
-- Retrieval info: <generic name="MEM_ROW_ADDR_WIDTH" value="14" />
-- Retrieval info: <generic name="MEM_COL_ADDR_WIDTH" value="10" />
-- Retrieval info: <generic name="MEM_DQ_WIDTH" value="64" />
-- Retrieval info: <generic name="MEM_DQ_PER_DQS" value="8" />
-- Retrieval info: <generic name="MEM_BANKADDR_WIDTH" value="3" />
-- Retrieval info: <generic name="MEM_IF_DM_PINS_EN" value="true" />
-- Retrieval info: <generic name="MEM_IF_DQSN_EN" value="true" />
-- Retrieval info: <generic name="MEM_NUMBER_OF_DIMMS" value="1" />
-- Retrieval info: <generic name="MEM_NUMBER_OF_RANKS_PER_DIMM" value="1" />
-- Retrieval info: <generic name="MEM_NUMBER_OF_RANKS_PER_DEVICE" value="1" />
-- Retrieval info: <generic name="MEM_RANK_MULTIPLICATION_FACTOR" value="1" />
-- Retrieval info: <generic name="MEM_CK_WIDTH" value="2" />
-- Retrieval info: <generic name="MEM_CS_WIDTH" value="1" />
-- Retrieval info: <generic name="MEM_CLK_EN_WIDTH" value="1" />
-- Retrieval info: <generic name="ALTMEMPHY_COMPATIBLE_MODE" value="false" />
-- Retrieval info: <generic name="NEXTGEN" value="true" />
-- Retrieval info: <generic name="MEM_IF_BOARD_BASE_DELAY" value="10" />
-- Retrieval info: <generic name="MEM_IF_SIM_VALID_WINDOW" value="0" />
-- Retrieval info: <generic name="MEM_GUARANTEED_WRITE_INIT" value="false" />
-- Retrieval info: <generic name="MEM_VERBOSE" value="true" />
-- Retrieval info: <generic name="PINGPONGPHY_EN" value="false" />
-- Retrieval info: <generic name="DUPLICATE_AC" value="false" />
-- Retrieval info: <generic name="REFRESH_BURST_VALIDATION" value="false" />
-- Retrieval info: <generic name="AP_MODE_EN" value="0" />
-- Retrieval info: <generic name="AP_MODE" value="false" />
-- Retrieval info: <generic name="MEM_BL" value="4" />
-- Retrieval info: <generic name="MEM_BT" value="Sequential" />
-- Retrieval info: <generic name="MEM_ASR" value="Manual" />
-- Retrieval info: <generic name="MEM_SRT" value="2x refresh rate" />
-- Retrieval info: <generic name="MEM_PD" value="Fast exit" />
-- Retrieval info: <generic name="MEM_DRV_STR" value="Full" />
-- Retrieval info: <generic name="MEM_DLL_EN" value="true" />
-- Retrieval info: <generic name="MEM_RTT_NOM" value="50" />
-- Retrieval info: <generic name="MEM_ATCL" value="0" />
-- Retrieval info: <generic name="MEM_TCL" value="5" />
-- Retrieval info: <generic name="MEM_AUTO_LEVELING_MODE" value="true" />
-- Retrieval info: <generic name="MEM_USER_LEVELING_MODE" value="Leveling" />
-- Retrieval info: <generic name="MEM_INIT_EN" value="false" />
-- Retrieval info: <generic name="MEM_INIT_FILE" value="" />
-- Retrieval info: <generic name="DAT_DATA_WIDTH" value="32" />
-- Retrieval info: <generic name="TIMING_TIS" value="375" />
-- Retrieval info: <generic name="TIMING_TIH" value="500" />
-- Retrieval info: <generic name="TIMING_TDS" value="250" />
-- Retrieval info: <generic name="TIMING_TDH" value="300" />
-- Retrieval info: <generic name="TIMING_TDQSQ" value="200" />
-- Retrieval info: <generic name="TIMING_TQHS" value="300" />
-- Retrieval info: <generic name="TIMING_TDQSCK" value="350" />
-- Retrieval info: <generic name="TIMING_TDQSCKDS" value="450" />
-- Retrieval info: <generic name="TIMING_TDQSCKDM" value="900" />
-- Retrieval info: <generic name="TIMING_TDQSCKDL" value="1200" />
-- Retrieval info: <generic name="TIMING_TDQSS" value="0.25" />
-- Retrieval info: <generic name="TIMING_TDQSH" value="0.35" />
-- Retrieval info: <generic name="TIMING_TDSH" value="0.2" />
-- Retrieval info: <generic name="TIMING_TDSS" value="0.2" />
-- Retrieval info: <generic name="MEM_TINIT_US" value="200" />
-- Retrieval info: <generic name="MEM_TMRD_CK" value="5" />
-- Retrieval info: <generic name="MEM_TRAS_NS" value="40.0" />
-- Retrieval info: <generic name="MEM_TRCD_NS" value="15.0" />
-- Retrieval info: <generic name="MEM_TRP_NS" value="15.0" />
-- Retrieval info: <generic name="MEM_TREFI_US" value="7.8" />
-- Retrieval info: <generic name="MEM_TRFC_NS" value="127.5" />
-- Retrieval info: <generic name="CFG_TCCD_NS" value="2.5" />
-- Retrieval info: <generic name="MEM_TWR_NS" value="15.0" />
-- Retrieval info: <generic name="MEM_TWTR" value="3" />
-- Retrieval info: <generic name="MEM_TFAW_NS" value="37.5" />
-- Retrieval info: <generic name="MEM_TRRD_NS" value="7.5" />
-- Retrieval info: <generic name="MEM_TRTP_NS" value="7.5" />
-- Retrieval info: <generic name="SYS_INFO_DEVICE_FAMILY" value="Stratix IV" />
-- Retrieval info: <generic name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID" value="false" />
-- Retrieval info: <generic name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM" value="" />
-- Retrieval info: <generic name="DEVICE_FAMILY_PARAM" value="" />
-- Retrieval info: <generic name="SPEED_GRADE" value="2" />
-- Retrieval info: <generic name="IS_ES_DEVICE" value="false" />
-- Retrieval info: <generic name="DISABLE_CHILD_MESSAGING" value="false" />
-- Retrieval info: <generic name="HARD_EMIF" value="false" />
-- Retrieval info: <generic name="HHP_HPS" value="false" />
-- Retrieval info: <generic name="HHP_HPS_VERIFICATION" value="false" />
-- Retrieval info: <generic name="HHP_HPS_SIMULATION" value="false" />
-- Retrieval info: <generic name="HPS_PROTOCOL" value="DEFAULT" />
-- Retrieval info: <generic name="CUT_NEW_FAMILY_TIMING" value="true" />
-- Retrieval info: <generic name="POWER_OF_TWO_BUS" value="false" />
-- Retrieval info: <generic name="SOPC_COMPAT_RESET" value="false" />
-- Retrieval info: <generic name="AVL_MAX_SIZE" value="8" />
-- Retrieval info: <generic name="BYTE_ENABLE" value="true" />
-- Retrieval info: <generic name="ENABLE_CTRL_AVALON_INTERFACE" value="true" />
-- Retrieval info: <generic name="CTL_DEEP_POWERDN_EN" value="false" />
-- Retrieval info: <generic name="CTL_SELF_REFRESH_EN" value="false" />
-- Retrieval info: <generic name="AUTO_POWERDN_EN" value="false" />
-- Retrieval info: <generic name="AUTO_PD_CYCLES" value="0" />
-- Retrieval info: <generic name="CTL_USR_REFRESH_EN" value="false" />
-- Retrieval info: <generic name="CTL_AUTOPCH_EN" value="false" />
-- Retrieval info: <generic name="CTL_ZQCAL_EN" value="false" />
-- Retrieval info: <generic name="ADDR_ORDER" value="0" />
-- Retrieval info: <generic name="CTL_LOOK_AHEAD_DEPTH" value="4" />
-- Retrieval info: <generic name="CONTROLLER_LATENCY" value="5" />
-- Retrieval info: <generic name="CFG_REORDER_DATA" value="false" />
-- Retrieval info: <generic name="STARVE_LIMIT" value="10" />
-- Retrieval info: <generic name="CTL_CSR_ENABLED" value="false" />
-- Retrieval info: <generic name="CTL_CSR_CONNECTION" value="INTERNAL_JTAG" />
-- Retrieval info: <generic name="CTL_ECC_ENABLED" value="false" />
-- Retrieval info: <generic name="CTL_HRB_ENABLED" value="false" />
-- Retrieval info: <generic name="CTL_ECC_AUTO_CORRECTION_ENABLED" value="false" />
-- Retrieval info: <generic name="MULTICAST_EN" value="false" />
-- Retrieval info: <generic name="CTL_DYNAMIC_BANK_ALLOCATION" value="false" />
-- Retrieval info: <generic name="CTL_DYNAMIC_BANK_NUM" value="4" />
-- Retrieval info: <generic name="DEBUG_MODE" value="false" />
-- Retrieval info: <generic name="ENABLE_BURST_MERGE" value="false" />
-- Retrieval info: <generic name="CTL_ENABLE_BURST_INTERRUPT" value="true" />
-- Retrieval info: <generic name="CTL_ENABLE_BURST_TERMINATE" value="true" />
-- Retrieval info: <generic name="LOCAL_ID_WIDTH" value="8" />
-- Retrieval info: <generic name="WRBUFFER_ADDR_WIDTH" value="6" />
-- Retrieval info: <generic name="MAX_PENDING_WR_CMD" value="8" />
-- Retrieval info: <generic name="MAX_PENDING_RD_CMD" value="16" />
-- Retrieval info: <generic name="USE_MM_ADAPTOR" value="true" />
-- Retrieval info: <generic name="USE_AXI_ADAPTOR" value="false" />
-- Retrieval info: <generic name="HCX_COMPAT_MODE" value="false" />
-- Retrieval info: <generic name="CTL_CMD_QUEUE_DEPTH" value="8" />
-- Retrieval info: <generic name="CTL_CSR_READ_ONLY" value="1" />
-- Retrieval info: <generic name="CFG_DATA_REORDERING_TYPE" value="INTER_BANK" />
-- Retrieval info: <generic name="NUM_OF_PORTS" value="1" />
-- Retrieval info: <generic name="ENABLE_BONDING" value="false" />
-- Retrieval info: <generic name="ENABLE_USER_ECC" value="false" />
-- Retrieval info: <generic name="AVL_DATA_WIDTH_PORT" value="32,32,32,32,32,32" />
-- Retrieval info: <generic name="PRIORITY_PORT" value="1,1,1,1,1,1" />
-- Retrieval info: <generic name="WEIGHT_PORT" value="0,0,0,0,0,0" />
-- Retrieval info: <generic name="CPORT_TYPE_PORT" value="Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional" />
-- Retrieval info: <generic name="ENABLE_EMIT_BFM_MASTER" value="false" />
-- Retrieval info: <generic name="FORCE_SEQUENCER_TCL_DEBUG_MODE" value="false" />
-- Retrieval info: <generic name="ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT" value="false" />
-- Retrieval info: <generic name="REF_CLK_FREQ" value="50.0" />
-- Retrieval info: <generic name="REF_CLK_FREQ_PARAM_VALID" value="false" />
-- Retrieval info: <generic name="REF_CLK_FREQ_MIN_PARAM" value="0.0" />
-- Retrieval info: <generic name="REF_CLK_FREQ_MAX_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_DR_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_DR_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_DR_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_DR_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_DR_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_MEM_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_MEM_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_MEM_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_MEM_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_MEM_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_AFI_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_AFI_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_AFI_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_WRITE_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_WRITE_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_WRITE_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_WRITE_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_HALF_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_AFI_HALF_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_AFI_HALF_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_HALF_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_NIOS_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_NIOS_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_NIOS_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_NIOS_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_NIOS_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_CONFIG_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_CONFIG_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_CONFIG_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_CONFIG_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_P2C_READ_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_P2C_READ_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_P2C_READ_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_P2C_READ_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_HR_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_HR_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_HR_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_HR_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_HR_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_PHY_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_AFI_PHY_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_AFI_PHY_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_PHY_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_CLK_PARAM_VALID" value="false" />
-- Retrieval info: <generic name="ENABLE_EXTRA_REPORTING" value="false" />
-- Retrieval info: <generic name="NUM_EXTRA_REPORT_PATH" value="10" />
-- Retrieval info: <generic name="ENABLE_ISS_PROBES" value="false" />
-- Retrieval info: <generic name="CALIB_REG_WIDTH" value="8" />
-- Retrieval info: <generic name="USE_SEQUENCER_BFM" value="false" />
-- Retrieval info: <generic name="PLL_SHARING_MODE" value="None" />
-- Retrieval info: <generic name="NUM_PLL_SHARING_INTERFACES" value="1" />
-- Retrieval info: <generic name="EXPORT_AFI_HALF_CLK" value="false" />
-- Retrieval info: <generic name="ABSTRACT_REAL_COMPARE_TEST" value="false" />
-- Retrieval info: <generic name="INCLUDE_BOARD_DELAY_MODEL" value="false" />
-- Retrieval info: <generic name="INCLUDE_MULTIRANK_BOARD_DELAY_MODEL" value="false" />
-- Retrieval info: <generic name="USE_FAKE_PHY" value="false" />
-- Retrieval info: <generic name="FORCE_MAX_LATENCY_COUNT_WIDTH" value="0" />
-- Retrieval info: <generic name="ENABLE_NON_DESTRUCTIVE_CALIB" value="false" />
-- Retrieval info: <generic name="ENABLE_DELAY_CHAIN_WRITE" value="false" />
-- Retrieval info: <generic name="TRACKING_ERROR_TEST" value="false" />
-- Retrieval info: <generic name="TRACKING_WATCH_TEST" value="false" />
-- Retrieval info: <generic name="MARGIN_VARIATION_TEST" value="false" />
-- Retrieval info: <generic name="AC_ROM_USER_ADD_0" value="0_0000_0000_0000" />
-- Retrieval info: <generic name="AC_ROM_USER_ADD_1" value="0_0000_0000_1000" />
-- Retrieval info: <generic name="TREFI" value="35100" />
-- Retrieval info: <generic name="REFRESH_INTERVAL" value="15000" />
-- Retrieval info: <generic name="ENABLE_NON_DES_CAL_TEST" value="false" />
-- Retrieval info: <generic name="TRFC" value="350" />
-- Retrieval info: <generic name="ENABLE_NON_DES_CAL" value="false" />
-- Retrieval info: <generic name="EXTRA_SETTINGS" value="" />
-- Retrieval info: <generic name="MEM_DEVICE" value="MISSING_MODEL" />
-- Retrieval info: <generic name="FORCE_SYNTHESIS_LANGUAGE" value="" />
-- Retrieval info: <generic name="FORCED_NUM_WRITE_FR_CYCLE_SHIFTS" value="0" />
-- Retrieval info: <generic name="SEQUENCER_TYPE" value="NIOS" />
-- Retrieval info: <generic name="ADVERTIZE_SEQUENCER_SW_BUILD_FILES" value="false" />
-- Retrieval info: <generic name="FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT" value="false" />
-- Retrieval info: <generic name="PHY_ONLY" value="true" />
-- Retrieval info: <generic name="SEQ_MODE" value="0" />
-- Retrieval info: <generic name="ADVANCED_CK_PHASES" value="false" />
-- Retrieval info: <generic name="COMMAND_PHASE" value="0.0" />
-- Retrieval info: <generic name="MEM_CK_PHASE" value="0.0" />
-- Retrieval info: <generic name="P2C_READ_CLOCK_ADD_PHASE" value="0.0" />
-- Retrieval info: <generic name="C2P_WRITE_CLOCK_ADD_PHASE" value="0.0" />
-- Retrieval info: <generic name="ACV_PHY_CLK_ADD_FR_PHASE" value="0.0" />
-- Retrieval info: <generic name="PLL_LOCATION" value="Top_Bottom" />
-- Retrieval info: <generic name="SKIP_MEM_INIT" value="true" />
-- Retrieval info: <generic name="READ_DQ_DQS_CLOCK_SOURCE" value="INVERTED_DQS_BUS" />
-- Retrieval info: <generic name="DQ_INPUT_REG_USE_CLKN" value="false" />
-- Retrieval info: <generic name="DQS_DQSN_MODE" value="DIFFERENTIAL" />
-- Retrieval info: <generic name="AFI_DEBUG_INFO_WIDTH" value="32" />
-- Retrieval info: <generic name="CALIBRATION_MODE" value="Skip" />
-- Retrieval info: <generic name="NIOS_ROM_DATA_WIDTH" value="32" />
-- Retrieval info: <generic name="READ_FIFO_SIZE" value="8" />
-- Retrieval info: <generic name="PHY_CSR_ENABLED" value="false" />
-- Retrieval info: <generic name="PHY_CSR_CONNECTION" value="INTERNAL_JTAG" />
-- Retrieval info: <generic name="USER_DEBUG_LEVEL" value="0" />
-- Retrieval info: <generic name="TIMING_BOARD_DERATE_METHOD" value="AUTO" />
-- Retrieval info: <generic name="TIMING_BOARD_CK_CKN_SLEW_RATE" value="2.0" />
-- Retrieval info: <generic name="TIMING_BOARD_AC_SLEW_RATE" value="1.0" />
-- Retrieval info: <generic name="TIMING_BOARD_DQS_DQSN_SLEW_RATE" value="2.0" />
-- Retrieval info: <generic name="TIMING_BOARD_DQ_SLEW_RATE" value="1.0" />
-- Retrieval info: <generic name="TIMING_BOARD_TIS" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_TIH" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_TDS" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_TDH" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_ISI_METHOD" value="AUTO" />
-- Retrieval info: <generic name="TIMING_BOARD_AC_EYE_REDUCTION_SU" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_AC_EYE_REDUCTION_H" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_DQ_EYE_REDUCTION" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_READ_DQ_EYE_REDUCTION" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME" value="0.0" />
-- Retrieval info: <generic name="PACKAGE_DESKEW" value="false" />
-- Retrieval info: <generic name="AC_PACKAGE_DESKEW" value="false" />
-- Retrieval info: <generic name="TIMING_BOARD_MAX_CK_DELAY" value="0.6" />
-- Retrieval info: <generic name="TIMING_BOARD_MAX_DQS_DELAY" value="0.6" />
-- Retrieval info: <generic name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN" value="-0.01" />
-- Retrieval info: <generic name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX" value="0.01" />
-- Retrieval info: <generic name="TIMING_BOARD_SKEW_BETWEEN_DIMMS" value="0.05" />
-- Retrieval info: <generic name="TIMING_BOARD_SKEW_WITHIN_DQS" value="0.02" />
-- Retrieval info: <generic name="TIMING_BOARD_SKEW_BETWEEN_DQS" value="0.02" />
-- Retrieval info: <generic name="TIMING_BOARD_DQ_TO_DQS_SKEW" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_AC_SKEW" value="0.02" />
-- Retrieval info: <generic name="TIMING_BOARD_AC_TO_CK_SKEW" value="0.6" />
-- Retrieval info: <generic name="ENABLE_EXPORT_SEQ_DEBUG_BRIDGE" value="false" />
-- Retrieval info: <generic name="CORE_DEBUG_CONNECTION" value="EXPORT" />
-- Retrieval info: <generic name="ADD_EXTERNAL_SEQ_DEBUG_NIOS" value="false" />
-- Retrieval info: <generic name="ED_EXPORT_SEQ_DEBUG" value="false" />
-- Retrieval info: <generic name="ADD_EFFICIENCY_MONITOR" value="false" />
-- Retrieval info: <generic name="ENABLE_ABS_RAM_MEM_INIT" value="false" />
-- Retrieval info: <generic name="ABS_RAM_MEM_INIT_FILENAME" value="meminit" />
-- Retrieval info: <generic name="DLL_SHARING_MODE" value="None" />
-- Retrieval info: <generic name="NUM_DLL_SHARING_INTERFACES" value="1" />
-- Retrieval info: <generic name="OCT_SHARING_MODE" value="None" />
-- Retrieval info: <generic name="NUM_OCT_SHARING_INTERFACES" value="1" />
-- Retrieval info: <generic name="AUTO_DEVICE" value="Unknown" />
-- Retrieval info: <generic name="AUTO_DEVICE_SPEEDGRADE" value="Unknown" />
-- Retrieval info: </instance>
-- IPFS_FILES : uniphy.vho
-- RELATED_FILES: uniphy.vhd, uniphy_0002.v, uniphy_pll0.sv, uniphy_p0_clock_pair_generator.v, uniphy_p0_read_valid_selector.v, uniphy_p0_addr_cmd_datapath.v, uniphy_p0_reset.v, uniphy_p0_acv_ldc.v, uniphy_p0_memphy.sv, uniphy_p0_reset_sync.v, uniphy_p0_new_io_pads.v, uniphy_p0_fr_cycle_shifter.v, uniphy_p0_fr_cycle_extender.v, uniphy_p0_read_datapath.sv, uniphy_p0_write_datapath.v, uniphy_p0_simple_ddio_out.sv, uniphy_p0_phy_csr.sv, uniphy_p0_iss_probe.v, uniphy_p0_addr_cmd_pads.v, uniphy_p0_flop_mem.v, uniphy_p0.sv, uniphy_p0_altdqdqs.v, altdq_dqs2_ddio_3reg_stratixiv.sv, afi_mux_ddrx.v, uniphy_s0.v, altera_mem_if_sequencer_rst.sv, altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst.v, altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst_test_bench.v, sequencer_scc_mgr.sv, sequencer_scc_siii_wrapper.sv, sequencer_scc_siii_phase_decode.v, sequencer_scc_sv_wrapper.sv, sequencer_scc_sv_phase_decode.v, sequencer_scc_acv_wrapper.sv, sequencer_scc_acv_phase_decode.v, sequencer_scc_reg_file.v, sequencer_reg_file.sv, sequencer_phy_mgr.sv, sequencer_data_mgr.sv, rw_manager_ddr2.v, rw_manager_ac_ROM_reg.v, rw_manager_bitcheck.v, rw_manager_core.sv, rw_manager_data_broadcast.v, rw_manager_data_decoder.v, rw_manager_datamux.v, rw_manager_di_buffer.v, rw_manager_di_buffer_wrap.v, rw_manager_dm_decoder.v, rw_manager_generic.sv, rw_manager_inst_ROM_reg.v, rw_manager_jumplogic.v, rw_manager_lfsr72.v, rw_manager_lfsr36.v, rw_manager_lfsr12.v, rw_manager_pattern_fifo.v, rw_manager_ram.v, rw_manager_ram_csr.v, rw_manager_read_datapath.v, rw_manager_write_decoder.v, rw_manager_ac_ROM_no_ifdef_params.v, rw_manager_inst_ROM_no_ifdef_params.v, altera_mem_if_sequencer_mem_no_ifdef_params.sv, uniphy_s0_mm_interconnect_0.v, uniphy_s0_irq_mapper.sv, altera_merlin_master_translator.sv, altera_merlin_slave_translator.sv, altera_merlin_master_agent.sv, altera_merlin_slave_agent.sv, altera_merlin_burst_uncompressor.sv, altera_avalon_sc_fifo.v, uniphy_s0_mm_interconnect_0_router.sv, uniphy_s0_mm_interconnect_0_router_001.sv, uniphy_s0_mm_interconnect_0_router_002.sv, uniphy_s0_mm_interconnect_0_router_005.sv, uniphy_s0_mm_interconnect_0_cmd_demux.sv, uniphy_s0_mm_interconnect_0_cmd_demux_001.sv, altera_merlin_arbitrator.sv, uniphy_s0_mm_interconnect_0_cmd_mux.sv, uniphy_s0_mm_interconnect_0_cmd_mux_003.sv, uniphy_s0_mm_interconnect_0_rsp_demux_003.sv, uniphy_s0_mm_interconnect_0_rsp_mux.sv, uniphy_s0_mm_interconnect_0_rsp_mux_001.sv, uniphy_s0_mm_interconnect_0_avalon_st_adapter.v, uniphy_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv, altera_mem_if_oct_stratixiv.sv, altera_mem_if_dll_stratixiv.sv
| gpl-3.0 | d7ad5c4d0ce30eb892aa9235578a2219 | 0.58915 | 3.093438 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-terasic-de0-nano/sdctrl16.vhd | 2 | 40,241 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: sdctrl16
-- File: sdctrl16.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified by: Daniel Bengtsson & Richard Fång
-- Description: 16- and 32-bit SDRAM memory controller.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.memctrl.all;
entity sdctrl16 is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
pwron : integer := 0;
sdbits : integer := 16;
oepol : integer := 0;
pageburst : integer := 0;
mobile : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end;
architecture rtl of sdctrl16 is
constant WPROTEN : boolean := wprot = 1;
constant SDINVCLK : boolean := invclk = 1;
constant BUS16 : boolean := (sdbits = 16);
constant BUS32 : boolean := (sdbits = 32);
constant BUS64 : boolean := (sdbits = 64);
constant REVISION : integer := 1;
constant PM_PD : std_logic_vector(2 downto 0) := "001";
constant PM_SR : std_logic_vector(2 downto 0) := "010";
constant PM_DPD : std_logic_vector(2 downto 0) := "101";
constant std_rammask: Std_Logic_Vector(31 downto 20) :=
Conv_Std_Logic_Vector(hmask, 12);
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_SDCTRL, 0, REVISION, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
5 => ahb_iobar(ioaddr, iomask),
others => zero32);
type mcycletype is (midle, active, leadout);
type sdcycletype is (act1, act2, act3, act3_16, rd1, rd2, rd3, rd4, rd4_16, rd5, rd6, rd7, rd8,
wr1, wr1_16, wr2, wr3, wr4, wr5, sidle,
sref, pd, dpd);
type icycletype is (iidle, pre, ref, lmode, emode, finish);
-- sdram configuration register
type sdram_cfg_type is record
command : std_logic_vector(2 downto 0);
csize : std_logic_vector(1 downto 0);
bsize : std_logic_vector(2 downto 0);
casdel : std_ulogic; -- CAS to data delay: 2/3 clock cycles
trfc : std_logic_vector(2 downto 0);
trp : std_ulogic; -- precharge to activate: 2/3 clock cycles
refresh : std_logic_vector(14 downto 0);
renable : std_ulogic;
pageburst : std_ulogic;
mobileen : std_logic_vector(1 downto 0); -- Mobile SD support, Mobile SD enabled
ds : std_logic_vector(3 downto 0); -- ds(1:0) (ds(3:2) used to detect update)
tcsr : std_logic_vector(3 downto 0); -- tcrs(1:0) (tcrs(3:2) used to detect update)
pasr : std_logic_vector(5 downto 0); -- pasr(2:0) (pasr(5:3) used to detect update)
pmode : std_logic_vector(2 downto 0); -- Power-Saving mode
txsr : std_logic_vector(3 downto 0); -- Exit Self Refresh timing
cke : std_ulogic; -- Clock enable
end record;
-- local registers
type reg_type is record
hready : std_ulogic;
hsel : std_ulogic;
bdrive : std_ulogic;
nbdrive : std_ulogic;
burst : std_ulogic;
wprothit : std_ulogic;
hio : std_ulogic;
startsd : std_ulogic;
lhw : std_ulogic; --Lower halfword
mstate : mcycletype;
sdstate : sdcycletype;
cmstate : mcycletype;
istate : icycletype;
icnt : std_logic_vector(2 downto 0);
haddr : std_logic_vector(31 downto 0);
hrdata : std_logic_vector((sdbits-1)+((16/sdbits)*16) downto 0);
hwdata : std_logic_vector(31 downto 0);
hwrite : std_ulogic;
htrans : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
size : std_logic_vector(1 downto 0);
cfg : sdram_cfg_type;
trfc : std_logic_vector(3 downto 0);
refresh : std_logic_vector(14 downto 0);
sdcsn : std_logic_vector(1 downto 0);
sdwen : std_ulogic;
rasn : std_ulogic;
casn : std_ulogic;
dqm : std_logic_vector(7 downto 0);
address : std_logic_vector(16 downto 2); -- memory address
bsel : std_ulogic;
idlecnt : std_logic_vector(3 downto 0); -- Counter, 16 idle clock sycles before entering Power-Saving mode
sref_tmpcom : std_logic_vector(2 downto 0); -- Save SD command when exit sref
end record;
signal r, ri : reg_type;
signal rbdrive, ribdrive : std_logic_vector(31 downto 0);
attribute syn_preserve : boolean;
attribute syn_preserve of rbdrive : signal is true;
begin
ctrl : process(rst, ahbsi, r, sdi, rbdrive)
variable v : reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable dataout : std_logic_vector(31 downto 0); -- data from memory
variable regsd : std_logic_vector(31 downto 0); -- data from registers
variable dqm : std_logic_vector(7 downto 0);
variable raddr : std_logic_vector(12 downto 0);
variable adec : std_ulogic;
variable rams : std_logic_vector(1 downto 0);
variable ba : std_logic_vector(1 downto 0);
variable haddr : std_logic_vector(31 downto 0);
variable dout : std_logic_vector(31 downto 0);
variable hsize : std_logic_vector(1 downto 0);
variable hwrite : std_ulogic;
variable htrans : std_logic_vector(1 downto 0);
variable hready : std_ulogic;
variable vbdrive : std_logic_vector(31 downto 0);
variable bdrive : std_ulogic;
variable lline : std_logic_vector(2 downto 0);
variable lineburst : boolean;
variable haddr_tmp : std_logic_vector(31 downto 0);
variable arefresh : std_logic;
variable hwdata : std_logic_vector(31 downto 0);
begin
-- Variable default settings to avoid latches
v := r; startsd := '0'; v.hresp := HRESP_OKAY; vbdrive := rbdrive; arefresh := '0';
if BUS16 then
if (r.lhw = '1') then --muxes read data to correct part of the register.
v.hrdata(sdbits-1 downto 0) := sdi.data(sdbits-1 downto 0);
else
v.hrdata((sdbits*2)-1 downto sdbits) := sdi.data(sdbits-1 downto 0);
end if;
else
v.hrdata(sdbits-1 downto sdbits-32) := sdi.data(sdbits-1 downto sdbits-32);
v.hrdata(31 downto 0) := sdi.data(31 downto 0);
end if;
hwdata := ahbreadword(ahbsi.hwdata, r.haddr(4 downto 2)); v.hwdata := hwdata;
lline := not r.cfg.casdel & r.cfg.casdel & r.cfg.casdel;
if (pageburst = 0) or ((pageburst = 2) and r.cfg.pageburst = '0') then
lineburst := true;
else lineburst := false; end if;
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
v.size := ahbsi.hsize(1 downto 0); v.hwrite := ahbsi.hwrite;
v.htrans := ahbsi.htrans;
if ahbsi.htrans(1) = '1' then
v.hio := ahbsi.hmbsel(1);
v.hsel := '1'; v.hready := v.hio;
end if;
v.haddr := ahbsi.haddr;
-- addr must be masked since address range can be smaller than
-- total banksize. this can result in wrong chip select being
-- asserted
for i in 31 downto 20 loop
v.haddr(i) := ahbsi.haddr(i) and not std_rammask(i);
end loop;
end if;
if (r.hsel = '1') and (ahbsi.hready = '0') then
haddr := r.haddr; hsize := r.size;
htrans := r.htrans; hwrite := r.hwrite;
else
haddr := ahbsi.haddr; hsize := ahbsi.hsize(1 downto 0);
htrans := ahbsi.htrans; hwrite := ahbsi.hwrite;
-- addr must be masked since address range can be smaller than
-- total banksize. this can result in wrong chip select being
-- asserted
for i in 31 downto 20 loop
haddr(i) := ahbsi.haddr(i) and not std_rammask(i);
end loop;
end if;
if fast = 1 then haddr := r.haddr; end if;
if ahbsi.hready = '1' then v.hsel := ahbsi.hsel(hindex); end if;
-- main state
if BUS16 then
case r.size is
when "00" => --bytesize
case r.haddr(0) is
when '0' => dqm := "11111101";
when others => dqm := "11111110";
end case;
when others => dqm := "11111100"; --halfword, word
end case;
else
case r.size is
when "00" =>
case r.haddr(1 downto 0) is
when "00" => dqm := "11110111";
when "01" => dqm := "11111011";
when "10" => dqm := "11111101";
when others => dqm := "11111110";
end case;
when "01" =>
if r.haddr(1) = '0' then dqm := "11110011"; else dqm := "11111100"; end if;
when others => dqm := "11110000";
end case;
end if;
--
-- case r.size is
-- when "00" =>
-- case r.haddr(1 downto 0) is
-- when "00" => dqm := "11111101"; lhw := '0'; --lhv := r.haddr(1)
-- when "01" => dqm := "11111110"; lhw := '0';
-- when "10" => dqm := "11111101"; lhw := '1';
-- when others => dqm := "11111110"; lhw := '1';
-- end case;
-- when "01" =>
-- dqm := "11111100";
-- if r.haddr(1) = '0' then
-- lhw := '0';
-- else
-- lhw := '1';
-- end if;
-- when others => dqm := "11111100"; --remember when word: lhw first 0 then 1
-- end case;
--
if BUS64 and (r.bsel = '1') then dqm := dqm(3 downto 0) & "1111"; end if;
-- main FSM
case r.mstate is
when midle =>
if ((v.hsel and htrans(1) and not v.hio) = '1') then
if (r.sdstate = sidle) and (r.cfg.command = "000")
and (r.cmstate = midle) and (v.hio = '0')
then
if fast = 0 then startsd := '1'; else v.startsd := '1'; end if;
v.mstate := active;
elsif ((r.sdstate = sref) or (r.sdstate = pd) or (r.sdstate = dpd))
and (r.cfg.command = "000") and (r.cmstate = midle) and (v.hio = '0')
then
v.startsd := '1';
if r.sdstate = dpd then -- Error response when on Deep Power-Down mode
v.hresp := HRESP_ERROR;
else
v.mstate := active;
end if;
end if;
end if;
when others => null;
end case;
startsd := startsd or r.startsd;
-- generate row and column address size
if BUS16 then
case r.cfg.csize is
when "00" => raddr := haddr(21 downto 9);-- case to check for bursting over row limit, since 1 row is 512 byte.
when "01" => raddr := haddr(22 downto 10);
when "10" => raddr := haddr(23 downto 11);
when others =>
if r.cfg.bsize = "110" then raddr := haddr(25 downto 13); --tänk
else raddr := haddr(24 downto 12); end if;
end case;
else
case r.cfg.csize is
when "00" => raddr := haddr(22 downto 10);
when "01" => raddr := haddr(23 downto 11);
when "10" => raddr := haddr(24 downto 12);
when others =>
if r.cfg.bsize = "111" then raddr := haddr(26 downto 14);
else raddr := haddr(25 downto 13); end if;
end case;
end if;
-- generate bank address
-- if BUS16 then --011
-- ba := genmux(r.cfg.bsize, haddr(26 downto 19)) &
-- genmux(r.cfg.bsize, haddr(25 downto 18));
-- else
ba := genmux(r.cfg.bsize, haddr(28 downto 21)) &
genmux(r.cfg.bsize, haddr(27 downto 20));
-- end if;
-- generate chip select
if BUS64 then
adec := genmux(r.cfg.bsize, haddr(30 downto 23));
v.bsel := genmux(r.cfg.bsize, r.haddr(29 downto 22));
else
adec := genmux(r.cfg.bsize, haddr(29 downto 22)); v.bsel := '0';
end if;
-- elsif BUS32 then
-- adec := genmux(r.cfg.bsize, haddr(29 downto 22)); v.bsel := '0';
-- else
-- adec := genmux(r.cfg.bsize, haddr(27 downto 20)); v.bsel := '0';
-- end if;
rams := adec & not adec;
-- sdram access FSM
if r.trfc /= "0000" then v.trfc := r.trfc - 1; end if;
if r.idlecnt /= "0000" then v.idlecnt := r.idlecnt - 1; end if;
case r.sdstate is
when sidle =>
if (startsd = '1') and (r.cfg.command = "000") and (r.cmstate = midle) then
-- if BUS16 then
-- v.address(16 downto 2) := '0' & ba & raddr(11 downto 0); --since 1 bit lower row => tot adress field 14 bits
-- else
v.address(16 downto 2) := ba & raddr; -- ba(16-15) & raddr(14-2) (2+13= 15 bits)
-- end if;
v.sdcsn := not rams(1 downto 0); v.rasn := '0'; v.sdstate := act1;
v.startsd := '0';
elsif (r.idlecnt = "0000") and (r.cfg.command = "000")
and (r.cmstate = midle) and (r.cfg.mobileen(1) = '1') then
case r.cfg.pmode is
when PM_SR =>
v.cfg.cke := '0'; v.sdstate := sref;
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc; -- Control minimum duration of Self Refresh mode (= tRAS)
when PM_PD => v.cfg.cke := '0'; v.sdstate := pd;
when PM_DPD =>
v.cfg.cke := '0'; v.sdstate := dpd;
v.sdcsn := (others => '0'); v.sdwen := '0'; v.rasn := '1'; v.casn := '1';
when others =>
end case;
end if;
when act1 =>
v.rasn := '1'; v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc;
if r.cfg.casdel = '1' then v.sdstate := act2; else
v.sdstate := act3;
if not BUS16 then -- needs if, otherwise it might clock in incorrect write data to state act3_16
v.hready := r.hwrite and ahbsi.htrans(0) and ahbsi.htrans(1);
end if;
end if;
if WPROTEN then
v.wprothit := sdi.wprot;
if sdi.wprot = '1' then v.hresp := HRESP_ERROR; end if;
end if;
when act2 =>
v.sdstate := act3;
if not BUS16 then
v.hready := r.hwrite and ahbsi.htrans(0) and ahbsi.htrans(1);
end if;
if WPROTEN and (r.wprothit = '1') then
v.hresp := HRESP_ERROR; v.hready := '0';
end if;
when act3 =>
v.casn := '0';
if BUS16 then --HW adress needed to memory
v.address(14 downto 2) := r.haddr(12 downto 11) & '0' & r.haddr(10 downto 1); --only allowed to use tot adressbits - ba bits
-- v.address(13 downto 2) := r.haddr(11) & '0' & r.haddr(10 downto 1); --only allowed to use tot adressbits - ba bits
v.lhw := r.haddr(1); -- 14-2 = 12 colummn bits => 13 downto 2
else
v.address(14 downto 2) := r.haddr(13 downto 12) & '0' & r.haddr(11 downto 2);
end if;
v.dqm := dqm; v.burst := r.hready; -- ??
if r.hwrite = '1' then
if BUS16 then --16 bit
if r.size(1) = '1' then --word
v.hready := ahbsi.htrans(0) and ahbsi.htrans(1); --delayed this check 1 state to keep write data correct in act3_16
v.burst := ahbsi.htrans(0) and ahbsi.htrans(1);
v.sdstate := act3_16; -- goto state for second part of word transfer
-- v.lhw := '0'; --write MSB 16 bits to AMBA adress that ends with 00
else --halfword or byte
v.sdstate := act3_16; v.hready := '1';
end if;
else --32 bit or 64
v.sdstate := wr1;
if ahbsi.htrans = "11" or (r.hready = '0') then v.hready := '1'; end if;
end if;
v.sdwen := '0'; v.bdrive := '0'; --write
if WPROTEN and (r.wprothit = '1') then
v.hresp := HRESP_ERROR; v.hready := '1';
if BUS16 then v.sdstate := act3_16; else v.sdstate := wr1; end if;
v.sdwen := '1'; v.bdrive := '1'; v.casn := '1'; --skip write, remember hready high in next state
end if;
else v.sdstate := rd1; end if;
when act3_16 => --handle 16 bit and WORD write
v.address(14 downto 2) := r.haddr(12 downto 11) & '0' & r.haddr(10 downto 2) & '1';
-- v.address(13 downto 2) := r.haddr(11) & '0' & r.haddr(10 downto 2) & '1';
v.lhw := '1';
if (r.hready and r.burst) = '1' and not (WPROTEN and (r.wprothit = '1')) then
v.hready := '0'; --kolla på transfertyp nonseq om vi vill delaya nedankoll.
if( ahbsi.htrans = "11" and
not ((r.haddr(5 downto 2) = "1111") and (r.cfg.command = "100")) and
not ((r.haddr(9) xor ahbsi.haddr(9)) = '1' and r.cfg.csize = "00") ) then
v.sdstate := wr1_16;
end if;
elsif r.burst = '1' or (r.hready and not r.burst) = '1' then --terminate burst or single write
v.sdstate := wr2; v.bdrive := '1'; v.casn := '1'; v.sdwen := '1';
v.dqm := (others => '1');
else -- complete single write
v.hready := '1';
v.sdstate := act3_16; --gick till wr1 förut
end if;
when wr1_16 =>
v.address(14 downto 2) := r.haddr(12 downto 11) & '0' & r.haddr(10 downto 1);
-- v.address(13 downto 2) := r.haddr(11) & '0' & r.haddr(10 downto 1);
v.lhw := r.haddr(1);
v.sdstate := act3_16;
v.hready := '1';
when wr1 =>
v.address(14 downto 2) := r.haddr(13 downto 12) & '0' & r.haddr(11 downto 2);
if (((r.burst and r.hready) = '1') and (r.htrans = "11"))
and not (WPROTEN and (r.wprothit = '1'))
then
v.hready := ahbsi.htrans(0) and ahbsi.htrans(1) and r.hready;
if ((r.haddr(5 downto 2) = "1111") and (r.cfg.command = "100")) then -- exit on refresh
v.hready := '0';
end if;
else
v.sdstate := wr2; v.bdrive := '1'; v.casn := '1'; v.sdwen := '1';
v.dqm := (others => '1');
end if;
when wr2 =>
if (r.cfg.trp = '0') then v.rasn := '0'; v.sdwen := '0'; end if;
v.sdstate := wr3;
when wr3 =>
if (r.cfg.trp = '1') then
v.rasn := '0'; v.sdwen := '0'; v.sdstate := wr4;
else
v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1'; v.sdstate := sidle;
v.idlecnt := (others => '1');
end if;
when wr4 =>
v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1';
if (r.cfg.trp = '1') then v.sdstate := wr5;
else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
when wr5 =>
v.sdstate := sidle; v.idlecnt := (others => '1');
when rd1 => --first read applied to sdram
v.casn := '1'; v.sdstate := rd7; --nop
if not BUS16 then --starting adress cannot be XXXX...111 since we have word burst in this case. and lowest bit always 0.
if lineburst and (ahbsi.htrans = "11") then
if r.haddr(4 downto 2) = "111" then
v.address(9 downto 5) := r.address(9 downto 5) + 1; --adds only within 1KB limit.
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
end if;
when rd7 =>
v.casn := '1'; --nop
if BUS16 then
if r.cfg.casdel = '1' then --casdel3
v.sdstate := rd2;
if lineburst and (ahbsi.htrans = "11") then
if r.haddr(3 downto 1) = "110" then
v.address(10 downto 5) := r.address(10 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
else --casdel2
v.sdstate := rd3;
if ahbsi.htrans /= "11" then
if (r.trfc(3 downto 1) = "000") then v.rasn := '0'; v.sdwen := '0'; end if;
elsif lineburst then
if r.haddr(3 downto 1) = "110" then
v.address(10 downto 5) := r.address(10 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
end if;
else -- 32 bit or larger
if r.cfg.casdel = '1' then --casdel3
v.sdstate := rd2;
if lineburst and (ahbsi.htrans = "11") then
if r.haddr(4 downto 2) = "110" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
else --casdel2
v.sdstate := rd3;
if ahbsi.htrans /= "11" then
if (r.trfc(3 downto 1) = "000") then v.rasn := '0'; v.sdwen := '0'; end if; --precharge
elsif lineburst then
if r.haddr(4 downto 2) = "110" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
end if;
end if;
when rd2 =>
v.casn := '1'; v.sdstate := rd3;
if BUS16 then
if ahbsi.htrans /= "11" then
v.rasn := '0'; v.sdwen := '0'; v.dqm := (others => '1'); --precharge & DQM
--note that DQM always has 2 cycle delay before blocking data. So NP if we fetch second HW
end if;
else
if ahbsi.htrans /= "11" then v.rasn := '0'; v.sdwen := '0'; v.dqm := (others => '1'); --precharge & DQM
elsif lineburst then
if r.haddr(4 downto 2) = "101" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
end if;
when rd3 => --first read data from sdram output v.lhw := r.haddr(1);
v.casn := '1'; --if read before cas makes nop else if pre => no difference
if BUS16 then
--note if read is for halfwor or byte we dont want to read a second time but exit.
--if the read is a word we need to change LHW to one since the next read should be muxed in next cylcle.
-- if r.size(1) = '1' then --word v.hready := not r.size(1)
-- v.sdstate := rd4_16; v.hready := '0'; --hready low since just first part of a word
-- v.lhw := '1'; -- read low 16 next state
-- else --HW or byte
-- v.sdstate := rd4_16; v.hready := '1';
-- end if;
v.sdstate := rd4_16;
v.lhw := not r.lhw; --r.lhw is 0 for word, we should invert for next half of word.For HW or Byte v.lhw does not matter.
v.hready := not r.size(1); --if word transfer the r.size(1) is 1 and hready goes low.If HW or byte r.size(1)=0 => hready=1
if r.sdwen = '0' then
v.rasn := '1'; v.sdwen := '1'; v.sdcsn := "11"; v.dqm := (others => '1'); -- make DSEL (NOP)
elsif lineburst and ((ahbsi.htrans = "11") and (r.cfg.casdel = '1')) then --only enter if cl3
if r.haddr(3 downto 1) = "100" then
v.address(10 downto 5) := r.address(10 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
else --32 bit or larger
v.sdstate := rd4; v.hready := '1';
if r.sdwen = '0' then
v.rasn := '1'; v.sdwen := '1'; v.sdcsn := "11"; v.dqm := (others => '1'); -- make DSEL (NOP)
elsif lineburst and (ahbsi.htrans = "11") and (r.casn = '1') then
if r.haddr(4 downto 2) = ("10" & not r.cfg.casdel) then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
end if;
when rd4_16 => --enter as word (r.hready is still 0) else 1. If hready one next transfer sampled into v.
--v.hready := '1';
v.hready := not r.hready;-- if Byte or HW exit with hready low. If word flip bit, makes correct exit with hready low.
v.lhw := not r.lhw; --r.lhw is one the first time we enter (taking care of second part of word)
v.casn := '1';
--quit on: Single transfer CL 2/3 (prcharge if CL 2 and timer was not 0)
if (ahbsi.htrans /= "11" and (r.hready = '1')) or
((r.haddr(9) xor ahbsi.haddr(9)) = '1' and r.cfg.csize = "00" and r.hready = '1') or --probably dont have to check hready 1 since if 0 adresses equal.
((r.haddr(5 downto 2) = "1111") and (r.cfg.command = "100") and (r.hready = '1')) then --quit on: ST W/HW/BYTE OR
--v.hready := '0'; --if Byte or HW exit with hready low, if ST word exit with high.
v.dqm := (others => '1');
if r.sdcsn /= "11" then --not prechargeing
v.rasn := '0'; v.sdwen := '0'; v.sdstate := rd5; --precharge
else--exit
if r.cfg.trp = '1' then v.sdstate := rd6;
else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
end if;
elsif lineburst then --NOTE: r.casn = 1 makes sure its the first halfword of a word that is checked (hready low)
if r.cfg.casdel = '0' then
if (r.haddr(3 downto 1) = "100") and (r.casn = '1') then --lline = 011 if casdel =1, 100 if casdel= 0
v.address(10 downto 5) := r.address(10 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
else
if (r.haddr(3 downto 1) = "010") and (r.hready = '1') then --lline = 011 if casdel =1, 100 if casdel= 0
v.address(10 downto 5) := r.address(10 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
end if;
when rd4 =>
v.hready := '1'; v.casn := '1';
if (ahbsi.htrans /= "11") or (r.sdcsn = "11") or
((r.haddr(5 downto 2) = "1111") and (r.cfg.command = "100")) -- exit on refresh
then
v.hready := '0'; v.dqm := (others => '1');
if (r.sdcsn /= "11") then
v.rasn := '0'; v.sdwen := '0'; v.sdstate := rd5;
else
if r.cfg.trp = '1' then v.sdstate := rd6;
else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
end if;
elsif lineburst then
if (r.haddr(4 downto 2) = lline) and (r.casn = '1') then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
when rd5 =>
if r.cfg.trp = '1' then v.sdstate := rd6; else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1'; v.dqm := (others => '1');
v.casn := '1';
when rd6 =>
v.sdstate := sidle; v.idlecnt := (others => '1'); v.dqm := (others => '1');
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1';
when sref =>
if (startsd = '1' and (r.hio = '0'))
or (r.cfg.command /= "000") or r.cfg.pmode /= PM_SR then
if r.trfc = "0000" then -- Minimum duration (= tRAS)
v.cfg.cke := '1';
v.sdcsn := (others => '0'); v.rasn := '1'; v.casn := '1';
end if;
if r.cfg.cke = '1' then
if (r.idlecnt = "0000") then -- tXSR ns with NOP
v.sdstate := sidle;
v.idlecnt := (others => '1');
v.sref_tmpcom := r.cfg.command;
v.cfg.command := "100";
end if;
else
v.idlecnt := r.cfg.txsr;
end if;
end if;
when pd =>
if (startsd = '1' and (r.hio = '0'))
or (r.cfg.command /= "000") or r.cfg.pmode /= PM_PD then
v.cfg.cke := '1';
v.sdstate := sidle;
v.idlecnt := (others => '1');
end if;
when dpd =>
v.sdcsn := (others => '1'); v.sdwen := '1'; v.rasn := '1'; v.casn := '1';
v.cfg.renable := '0';
if (startsd = '1' and r.hio = '0') then
v.hready := '1'; -- ack all accesses with Error response
v.startsd := '0';
v.hresp := HRESP_ERROR;
elsif r.cfg.pmode /= PM_DPD then
v.cfg.cke := '1';
if r.cfg.cke = '1' then
v.sdstate := sidle;
v.idlecnt := (others => '1');
v.cfg.renable := '1';
end if;
end if;
when others =>
v.sdstate := sidle; v.idlecnt := (others => '1');
end case;
-- sdram commands
case r.cmstate is
when midle =>
if r.sdstate = sidle then
case r.cfg.command is
when "010" => -- precharge
v.sdcsn := (others => '0'); v.rasn := '0'; v.sdwen := '0';
v.address(12) := '1'; v.cmstate := active;
when "100" => -- auto-refresh
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.cmstate := active;
when "110" => -- Lodad Mode Reg
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active;
if lineburst then
v.address(16 downto 2) := "0000010001" & r.cfg.casdel & "0011";
else
v.address(16 downto 2) := "0000010001" & r.cfg.casdel & "0111";
end if;
when "111" => -- Load Ext-Mode Reg
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active;
v.address(16 downto 2) := "10000000" & r.cfg.ds(1 downto 0) & r.cfg.tcsr(1 downto 0)
& r.cfg.pasr(2 downto 0);
when others => null;
end case;
end if;
when active =>
v.sdcsn := (others => '1'); v.rasn := '1'; v.casn := '1';
v.sdwen := '1'; --v.cfg.command := "000";
v.cfg.command := r.sref_tmpcom; v.sref_tmpcom := "000";
v.cmstate := leadout; v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc;
when leadout =>
if r.trfc = "0000" then v.cmstate := midle; end if;
end case;
-- sdram init
case r.istate is
when iidle =>
v.cfg.cke := '1';
if r.cfg.renable = '1' and r.cfg.cke = '1' then
v.cfg.command := "010"; v.istate := pre;
end if;
when pre =>
if r.cfg.command = "000" then
v.cfg.command := "100"; v.istate := ref; v.icnt := "111";
end if;
when ref =>
if r.cfg.command = "000" then
v.cfg.command := "100"; v.icnt := r.icnt - 1;
if r.icnt = "000" then v.istate := lmode; v.cfg.command := "110"; end if;
end if;
when lmode =>
if r.cfg.command = "000" then
if r.cfg.mobileen = "11" then
v.cfg.command := "111"; v.istate := emode;
else
v.istate := finish;
end if;
end if;
when emode =>
if r.cfg.command = "000" then
v.istate := finish;
end if;
when others =>
if r.cfg.renable = '0' and r.sdstate /= dpd then
v.istate := iidle;
end if;
end case;
if (ahbsi.hready and ahbsi.hsel(hindex) ) = '1' then
if ahbsi.htrans(1) = '0' then v.hready := '1'; end if;
end if;
if (r.hsel and r.hio and not r.hready) = '1' then v.hready := '1'; end if;
-- second part of main fsm
case r.mstate is
when active =>
if v.hready = '1' then
v.mstate := midle;
end if;
when others => null;
end case;
-- sdram refresh counter
-- pragma translate_off
if not is_x(r.cfg.refresh) then
-- pragma translate_on
if (r.cfg.renable = '1') and (r.istate = finish) and r.sdstate /= sref then
v.refresh := r.refresh - 1;
if (v.refresh(14) and not r.refresh(14)) = '1' then
v.refresh := r.cfg.refresh;
v.cfg.command := "100";
arefresh := '1';
end if;
end if;
-- pragma translate_off
end if;
-- pragma translate_on
-- AHB register access
-- if writing to IO space config regs. Just mapping write data to all config values in config reg
if (r.hsel and r.hio and r.hwrite and r.htrans(1)) = '1' then
if r.haddr(3 downto 2) = "00" then
if pageburst = 2 then v.cfg.pageburst := hwdata(17); end if;
v.cfg.command := hwdata(20 downto 18);
v.cfg.csize := hwdata(22 downto 21);
v.cfg.bsize := hwdata(25 downto 23);
v.cfg.casdel := hwdata(26);
v.cfg.trfc := hwdata(29 downto 27);
v.cfg.trp := hwdata(30);
v.cfg.renable := hwdata(31);
v.cfg.refresh := hwdata(14 downto 0);
v.refresh := (others => '0');
elsif r.haddr(3 downto 2) = "01" then
if r.cfg.mobileen(1) = '1' and mobile /= 3 then v.cfg.mobileen(0) := hwdata(31); end if;
if r.cfg.pmode = "000" then
v.cfg.cke := hwdata(30);
end if;
if r.cfg.mobileen(1) = '1' then
v.cfg.txsr := hwdata(23 downto 20);
v.cfg.pmode := hwdata(18 downto 16);
v.cfg.ds(3 downto 2) := hwdata( 6 downto 5);
v.cfg.tcsr(3 downto 2) := hwdata( 4 downto 3);
v.cfg.pasr(5 downto 3) := hwdata( 2 downto 0);
end if;
end if;
end if;
-- Disable CS and DPD when Mobile SDR is Disabled
if r.cfg.mobileen(0) = '0' then v.cfg.pmode(2) := '0'; end if;
-- Update EMR when ds, tcsr or pasr change
if r.cfg.command = "000" and arefresh = '0' and r.cfg.mobileen(0) = '1' then
if r.cfg.ds(1 downto 0) /= r.cfg.ds(3 downto 2) then
v.cfg.command := "111"; v.cfg.ds(1 downto 0) := r.cfg.ds(3 downto 2);
end if;
if r.cfg.tcsr(1 downto 0) /= r.cfg.tcsr(3 downto 2) then
v.cfg.command := "111"; v.cfg.tcsr(1 downto 0) := r.cfg.tcsr(3 downto 2);
end if;
if r.cfg.pasr(2 downto 0) /= r.cfg.pasr(5 downto 3) then
v.cfg.command := "111"; v.cfg.pasr(2 downto 0) := r.cfg.pasr(5 downto 3);
end if;
end if;
regsd := (others => '0');
--reads out config registers (r/w does not matter) according to manual depending on address, notice generic determines data width.
if r.haddr(3 downto 2) = "00" then
regsd(31 downto 18) := r.cfg.renable & r.cfg.trp & r.cfg.trfc &
r.cfg.casdel & r.cfg.bsize & r.cfg.csize & r.cfg.command;
if not lineburst then regsd(17) := '1'; end if;
regsd(16) := r.cfg.mobileen(1);
if BUS64 then regsd(15) := '1'; end if;
regsd(14 downto 0) := r.cfg.refresh;
elsif r.haddr(3 downto 2) = "01" then
regsd(31) := r.cfg.mobileen(0);
regsd(30) := r.cfg.cke;
regsd(23 downto 0) := r.cfg.txsr & '0' & r.cfg.pmode & "000000000" &
r.cfg.ds(1 downto 0) & r.cfg.tcsr(1 downto 0) & r.cfg.pasr(2 downto 0);
end if;
if (r.hsel and r.hio) = '1' then dout := regsd;
else
if BUS64 and r.bsel = '1' then dout := r.hrdata(63 downto 32);
else dout := r.hrdata(31 downto 0); end if;
end if;
v.nbdrive := not v.bdrive;
if oepol = 1 then bdrive := r.nbdrive; vbdrive := (others => v.nbdrive);
else bdrive := r.bdrive; vbdrive := (others => v.bdrive);end if;
-- reset
if rst = '0' then
v.sdstate := sidle;
v.mstate := midle;
v.istate := iidle;
v.cmstate := midle;
v.hsel := '0';
v.cfg.command := "000";
v.cfg.csize := "10";
v.cfg.bsize := "000";
v.cfg.casdel := '1';
v.cfg.trfc := "111";
if pwron = 1 then v.cfg.renable := '1';
else v.cfg.renable := '0'; end if;
v.cfg.trp := '1';
v.dqm := (others => '1');
v.sdwen := '1';
v.rasn := '1';
v.casn := '1';
v.hready := '1';
v.bsel := '0';
v.startsd := '0';
if (pageburst = 2) then
v.cfg.pageburst := '0';
end if;
if mobile >= 2 then v.cfg.mobileen := "11";
elsif mobile = 1 then v.cfg.mobileen := "10";
else v.cfg.mobileen := "00"; end if;
v.cfg.txsr := (others => '1');
v.cfg.pmode := (others => '0');
v.cfg.ds := (others => '0');
v.cfg.tcsr := (others => '0');
v.cfg.pasr := (others => '0');
if mobile >= 2 then v.cfg.cke := '0';
else v.cfg.cke := '1'; end if;
v.sref_tmpcom := "000";
v.idlecnt := (others => '1');
end if;
ri <= v;
ribdrive <= vbdrive;
ahbso.hready <= r.hready;
ahbso.hresp <= r.hresp;
ahbso.hrdata <= ahbdrivedata(dout);
end process;
--sdo.sdcke <= (others => '1');
sdo.sdcke <= (others => r.cfg.cke);
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
-- Quick hack to get rid of undriven signal warnings. Check this for future
-- merge with main sdctrl.
drivehack : block
begin
sdo.qdrive <= '0';
sdo.nbdrive <= '0';
sdo.ce <= '0';
sdo.moben <= '0';
sdo.cal_rst <= '0';
sdo.oct <= '0';
sdo.xsdcsn <= (others => '1');
sdo.data(127 downto 16) <= (others => '0');
sdo.cb <= (others => '0');
sdo.ba <= (others => '0');
sdo.sdck <= (others => '0');
sdo.cal_en <= (others => '0');
sdo.cal_inc <= (others => '0');
sdo.cal_pll <= (others => '0');
sdo.odt <= (others => '0');
sdo.conf <= (others => '0');
sdo.vcbdrive <= (others => '0');
sdo.dqs_gate <= '0';
sdo.cbdqm <= (others => '0');
sdo.cbcal_en <= (others => '0');
sdo.cbcal_inc <= (others => '0');
sdo.read_pend <= (others => '0');
sdo.regwdata <= (others => '0');
sdo.regwrite <= (others => '0');
end block drivehack;
regs : process(clk, rst) begin
if rising_edge(clk) then
r <= ri; rbdrive <= ribdrive;
if rst = '0' then r.icnt <= (others => '0'); end if;
end if;
if (rst = '0') then
r.sdcsn <= (others => '1'); r.bdrive <= '1'; r.nbdrive <= '0';
if oepol = 0 then rbdrive <= (others => '1');
else rbdrive <= (others => '0'); end if;
end if;
end process;
rgen : if not SDINVCLK generate
sdo.address <= r.address;
sdo.bdrive <= r.nbdrive when oepol = 1 else r.bdrive;
sdo.vbdrive <= zero32 & rbdrive;
sdo.sdcsn <= r.sdcsn;
sdo.sdwen <= r.sdwen;
sdo.dqm <= "11111111" & r.dqm;
sdo.rasn <= r.rasn;
sdo.casn <= r.casn;
mux16_wrdata : if BUS16 generate --mux data depending on Low/High HW
sdo.data(15 downto 0) <= r.hwdata(15 downto 0) when r.lhw = '1' else r.hwdata(31 downto 16);
end generate;
wrdata : if not BUS16 generate
drivebus: for i in 0 to sdbits/64 generate
sdo.data(31+32*i downto 32*i) <= r.hwdata;
end generate;
end generate;
end generate;
ngen : if SDINVCLK generate
nregs : process(clk, rst) begin
if falling_edge(clk) then
sdo.address <= r.address;
if oepol = 1 then sdo.bdrive <= r.nbdrive;
else sdo.bdrive <= r.bdrive; end if;
sdo.vbdrive <= zero32 & rbdrive;
sdo.sdcsn <= r.sdcsn;
sdo.sdwen <= r.sdwen;
sdo.dqm <= "11111111" & r.dqm;
sdo.rasn <= r.rasn;
sdo.casn <= r.casn;
if BUS16 then --mux data depending on Low/High HW
if (r.lhw ='1') then
sdo.data(15 downto 0) <= r.hwdata(15 downto 0);
else
sdo.data(15 downto 0) <= r.hwdata(31 downto 16);
end if;
end if;
if not BUS16 then
for i in 0 to sdbits/64 loop
sdo.data(31+32*i downto 32*i) <= r.hwdata;
end loop;
end if;
end if;
if rst = '0' then sdo.sdcsn <= (others => '1'); end if;
end process;
end generate;
-- pragma translate_off
bootmsg : report_version
generic map ("sdctrl16" & tost(hindex) &
": PC133 SDRAM controller rev " & tost(REVISION));
-- pragma translate_on
end;
| gpl-3.0 | a1da51a4587a34feabda42467088cbf9 | 0.527997 | 3.285994 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-digilent-nexys4/config.vhd | 1 | 8,124 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := artix7;
constant CFG_MEMTECH : integer := artix7;
constant CFG_PADTECH : integer := artix7;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := artix7;
constant CFG_CLKMUL : integer := (10);
constant CFG_CLKDIV : integer := (20);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 1;
constant CFG_NWP : integer := (0);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 4;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 0*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 1 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 1;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 1;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000000#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDR2SP : integer := 0;
constant CFG_DDR2SP_INIT : integer := 0;
constant CFG_DDR2SP_FREQ : integer := 100;
constant CFG_DDR2SP_TRFC : integer := 130;
constant CFG_DDR2SP_DATAWIDTH : integer := 64;
constant CFG_DDR2SP_FTEN : integer := 0;
constant CFG_DDR2SP_FTWIDTH : integer := 0;
constant CFG_DDR2SP_COL : integer := 9;
constant CFG_DDR2SP_SIZE : integer := 8;
constant CFG_DDR2SP_DELAY0 : integer := 0;
constant CFG_DDR2SP_DELAY1 : integer := 0;
constant CFG_DDR2SP_DELAY2 : integer := 0;
constant CFG_DDR2SP_DELAY3 : integer := 0;
constant CFG_DDR2SP_DELAY4 : integer := 0;
constant CFG_DDR2SP_DELAY5 : integer := 0;
constant CFG_DDR2SP_DELAY6 : integer := 0;
constant CFG_DDR2SP_DELAY7 : integer := 0;
constant CFG_DDR2SP_NOSYNC : integer := 0;
-- Xilinx MIG
constant CFG_MIG_DDR2 : integer := 1;
constant CFG_MIG_RANKS : integer := (1);
constant CFG_MIG_COLBITS : integer := (10);
constant CFG_MIG_ROWBITS : integer := (13);
constant CFG_MIG_BANKBITS: integer := (2);
constant CFG_MIG_HMASK : integer := 16#F00#;
-- AHB ROM
constant CFG_AHBROMEN : integer := 1;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#100#;
constant CFG_ROMMASK : integer := 16#E00# + 16#100#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 4;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 1;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 0;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#0#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 0;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := 1;
constant CFG_SPIMCTRL_ASCALER : integer := 1;
constant CFG_SPIMCTRL_PWRUPCNT : integer := 0;
constant CFG_SPIMCTRL_OFFSET : integer := 16#0#;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 0;
constant CFG_SPICTRL_NUM : integer := 1;
constant CFG_SPICTRL_SLVS : integer := 1;
constant CFG_SPICTRL_FIFO : integer := 1;
constant CFG_SPICTRL_SLVREG : integer := 0;
constant CFG_SPICTRL_ODMODE : integer := 0;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 0;
constant CFG_SPICTRL_MAXWLEN : integer := 0;
constant CFG_SPICTRL_SYNCRAM : integer := 0;
constant CFG_SPICTRL_FT : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 1;
end;
| gpl-3.0 | d125dbf6ce2c4c10bb2e85756a034ba7 | 0.653496 | 3.567852 | false | false | false | false |
EliasLuiz/TCC | Teste/DefConstants.vhd | 1 | 7,206 | library ieee;
use ieee.math_real.all;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package Constants is
---------------------------FUNCTIONS---------------------------
function AddressBits(constant n : in integer) return integer;
function MaxValueBits(constant n : in integer) return integer;
function RoundToPowerOf2(constant n : in integer) return integer;
function Smaller(constant a, b : in std_logic_vector) return std_logic_vector;
function StdLogicToInteger(constant n : in std_logic_vector) return integer;
function IntegerToStdLogic(constant n, lenght : in integer) return std_logic_vector;
---------------------------------------------------------------
-----------------------------CONSTANTS-----------------------------
--Architecture bit quantity
--LEON3 = 32 bits
constant ArchitectureBitCount: integer;-- := 32;
constant ArchitectureBitCountAddress: integer;-- := ArchitectureBitCountAddress --5;
--Memory associativity
--Must be power of 2
constant MemoTableTAssociativity: integer;-- := 4;
constant MemoTableTAssociativityAddress: integer;-- := AddressBits(MemoTableTAssociativity) --2;
--Number of entries per way
--Must be greater than 1
constant MemoTableTWayLenght: integer;-- := 64;
constant MemoTableTWayAddressLenght: integer;-- := AddressBits(MemoTableTWayLenght) --6;
--Number of entries for all ways combined
constant MemoTableTLenght: integer;-- := MemoTableTWayLenght * MemoTableTAssociativity --256;
constant MemoTableTAddressLenght: integer;-- := AddressBits(MemoTableTLenght) --8;
--DTM storage parameters
constant InputContextLenght: integer;-- := 3;
constant OutputContextLenght: integer;-- := 3;
--Number of bits on the Tag field
constant MemoTableTTagWidth: integer;-- := ArchitectureBitCount - MemoTableTAddressLenght --24;
--Cache entry replacemento policy
--Possible values:
--"LRU" - Least Recently Used
--"LFU" - Least frequently used
--"PLR" - Pseudo-LRU
constant MemoTableTReplacement: string;-- := "LRU";
--Number of bits on an entry on the NPC + Tag memory
constant MemoTableTNPCTagEntryWidth: integer;-- := RoundToPowerOf2(
--ArchitectureBitCount
--+ MemoTableTTagWidth);
--Number of bits on an entry of the input context memory
constant MemoTableTInputEntryWidth: integer;-- := RoundToPowerOf2(
--ArchitectureBitCountAddress * InputContextLenght --Register identifiers
--+ ArchitectureBitCount * InputContextLenght); --Register values
--Number of bits on an entry of the input context memory
constant MemoTableTOutputEntryWidth: integer;-- := RoundToPowerOf2(
--ArchitectureBitCountAddress * OutputContextLenght --Register identifiers
--+ ArchitectureBitCount * OutputContextLenght);--Register values
--Number of bits on an entry on the LRU counter memory
constant MemoTableTLRUCounterEntryWidth: integer;-- := RoundToPowerOf2(
--AddressBits(MemoTableTAssociativity));
-------------------------------------------------------------------
end Constants;
package body Constants is
---------------------------FUNCTIONS---------------------------
--Parameters:
-- n: An integer to be represented in binary e.g. the maximum value of a counter.
--Return:
-- An integer defining the amount of bits needed to represent n in binary.
--Notes:
-- To be used to determine the lenght of address buses.
function AddressBits(constant n : in integer) return integer is
begin
return integer(ceil(log2(real(n))));
end AddressBits;
--Parameters:
-- n: The number of bits to represent the number in binary.
--Return:
-- An integer defining the maximum value possible with n bits.
function MaxValueBits(constant n : in integer) return integer is
begin
return integer(2**n - 1);
end MaxValueBits;
--Parameters:
-- n: An integer.
--Return:
-- An integer with value equal to the smaller power of 2 greater of equal than n.
function RoundToPowerOf2(constant n : in integer) return integer is
begin
return integer(2**ceil(log2(real(n))));
end RoundToPowerOf2;
--Parameters:
-- n: Two std_logic_vector.
--Return:
-- An std_logic_vector with the value of the parameter with smaller unsigned value.
function Smaller(constant a, b : in std_logic_vector) return std_logic_vector is
begin
if unsigned(a) < unsigned(b) then
return a;
else
return b;
end if;
end Smaller;
function StdLogicToInteger(constant n : in std_logic_vector) return integer is
begin
return to_integer(unsigned(n));
end StdLogicToInteger;
function IntegerToStdLogic(constant n, lenght : in integer) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(n, lenght));
end IntegerToStdLogic;
---------------------------------------------------------------
-----------------------------CONSTANTS-----------------------------
--Architecture bit quantity
--LEON3 = 32 bits
constant ArchitectureBitCount: integer := 32;
constant ArchitectureBitCountAddress: integer := AddressBits(ArchitectureBitCount);
--Memory associativity
--Must be power of 2
constant MemoTableTAssociativity: integer := 4;
constant MemoTableTAssociativityAddress: integer := AddressBits(MemoTableTAssociativity);
--Number of entries per way
--Must be greater than 1
constant MemoTableTWayLenght: integer := 64;
constant MemoTableTWayAddressLenght: integer := AddressBits(MemoTableTWayLenght);
--Number of entries for all ways combined
constant MemoTableTLenght: integer := MemoTableTWayLenght * MemoTableTAssociativity;
constant MemoTableTAddressLenght: integer := AddressBits(MemoTableTLenght);
--DTM storage parameters
constant InputContextLenght: integer := 3;
constant OutputContextLenght: integer := 3;
--Number of bits on the Tag field
constant MemoTableTTagWidth: integer := ArchitectureBitCount - MemoTableTAddressLenght;
--Cache entry replacemento policy
--Possible values:
--"LRU" - Least Recently Used
--"LFU" - Least frequently used
--"PLR" - Pseudo-LRU
constant MemoTableTReplacement: string := "LRU";
--Number of bits on an entry on the NPC + Tag memory
constant MemoTableTNPCTagEntryWidth: integer := RoundToPowerOf2(
ArchitectureBitCount
+ MemoTableTTagWidth);
--Number of bits on an entry of the input context memory
constant MemoTableTInputEntryWidth: integer := RoundToPowerOf2(
ArchitectureBitCountAddress * InputContextLenght --Register identifiers
+ ArchitectureBitCount * InputContextLenght); --Register values
--Number of bits on an entry of the input context memory
constant MemoTableTOutputEntryWidth: integer := RoundToPowerOf2(
ArchitectureBitCountAddress * OutputContextLenght --Register identifiers
+ ArchitectureBitCount * OutputContextLenght);--Register values
--Number of bits on an entry on the LRU counter memory
constant MemoTableTLRUCounterEntryWidth: integer := RoundToPowerOf2(
AddressBits(MemoTableTAssociativity));
-------------------------------------------------------------------
end package body; | gpl-3.0 | ee65e980ddf9780c2a74775911ca2b65 | 0.685817 | 3.965878 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/ddr/ahb2mig_7series_pkg.vhd | 1 | 32,550 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: ah2mig_7series_pkg
-- File: ah2mig_7series_pkg.vhd
-- Author: Fredrik Ringhage - Aeroflex Gaisler
-- Description: Components, types and functions for AHB2MIG 7-Series controller
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use grlib.config_types.all;
use grlib.config.all;
library gaisler;
use gaisler.all;
package ahb2mig_7series_pkg is
-------------------------------------------------------------------------------
-- AHB2MIG configuration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- AHB2MIG interface type declarations and constant
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- AHB2MIG Subprograms
-------------------------------------------------------------------------------
function nbrmaxmigcmds (
datawidth : integer)
return integer;
function nbrmigcmds (
hwrite : std_logic;
hsize : std_logic_vector;
htrans : std_logic_vector;
step : unsigned;
datawidth : integer)
return integer;
function nbrmigcmds16 (
hwrite : std_logic;
hsize : std_logic_vector;
htrans : std_logic_vector;
step : unsigned;
datawidth : integer)
return integer;
function reversebyte (
data : std_logic_vector)
return std_logic_vector;
function reversebytemig (
data : std_logic_vector)
return std_logic_vector;
function ahbselectdatanoreplicastep (
haddr : std_logic_vector(7 downto 2);
hsize : std_logic_vector(2 downto 0)
)
return unsigned;
-- Added in order to make it working for 16-bit memory (only with 32-bit bus)
function ahbselectdatanoreplicastep16 (
haddr : std_logic_vector(7 downto 2);
hsize : std_logic_vector(2 downto 0)
)
return unsigned;
function ahbselectdatanoreplicaoutput (
haddr : std_logic_vector(7 downto 0);
counter : unsigned(31 downto 0);
hsize : std_logic_vector(2 downto 0);
rdbuffer : unsigned;
wr_count : unsigned;
replica : boolean)
return std_logic_vector;
-- Added in order to make it working for 16-bit memory (only with 32-bit bus)
function ahbselectdatanoreplicaoutput16 (
haddr : std_logic_vector(7 downto 0);
counter : unsigned(31 downto 0);
hsize : std_logic_vector(2 downto 0);
rdbuffer : unsigned;
wr_count : unsigned;
replica : boolean)
return std_logic_vector;
function ahbselectdatanoreplicamask (
haddr : std_logic_vector(6 downto 0);
hsize : std_logic_vector(2 downto 0))
return std_logic_vector;
function ahbselectdatanoreplica (hdata : std_logic_vector(AHBDW-1 downto 0);
haddr : std_logic_vector(4 downto 0); hsize : std_logic_vector(2 downto 0))
return std_logic_vector;
function ahbdrivedatanoreplica (hdata : std_logic_vector) return std_logic_vector;
-------------------------------------------------------------------------------
-- AHB2MIG Components
-------------------------------------------------------------------------------
end;
package body ahb2mig_7series_pkg is
-- Number of Max MIG commands
function nbrmaxmigcmds(
datawidth : integer)
return integer is
variable ret : integer;
begin
case datawidth is
when 128 =>
ret:= 4;
when 64 =>
ret := 2;
when others =>
ret := 2;
end case;
return ret;
end function nbrmaxmigcmds;
-- Number of MIG commands
function nbrmigcmds(
hwrite : std_logic;
hsize : std_logic_vector;
htrans : std_logic_vector;
step : unsigned;
datawidth : integer)
return integer is
variable ret : integer;
begin
if (hwrite = '0') then
case datawidth is
when 128 =>
if (hsize = HSIZE_4WORD) then
ret:= 4;
elsif (hsize = HSIZE_DWORD) then
ret := 2;
elsif (hsize = HSIZE_WORD) then
ret := 1;
else
ret := 1;
end if;
when 64 =>
if (hsize = HSIZE_DWORD) then
ret := 2;
elsif (hsize = HSIZE_WORD) then
ret := 2;
else
ret := 1;
end if;
-- 32
when others =>
if (hsize = HSIZE_WORD) then
ret := 2;
else
ret := 1;
end if;
end case;
if (htrans /= HTRANS_SEQ) then
ret := 1;
end if;
else
ret := to_integer(shift_right(step,4)) + 1;
end if;
return ret;
end function nbrmigcmds;
function nbrmigcmds16(
hwrite : std_logic;
hsize : std_logic_vector;
htrans : std_logic_vector;
step : unsigned;
datawidth : integer)
return integer is
variable ret : integer;
begin
if (hwrite = '0') then
if (hsize = HSIZE_WORD) then
ret := 2;
else
ret := 1;
end if;
if (htrans /= HTRANS_SEQ) then
ret := 1;
end if;
else
ret := to_integer(shift_right(step,2)) + 1;
end if;
return ret;
end function nbrmigcmds16;
-- Reverses byte order.
function reversebyte(
data : std_logic_vector)
return std_logic_vector is
variable rdata: std_logic_vector(data'length-1 downto 0);
begin
for i in 0 to (data'length/8-1) loop
rdata(i*8+8-1 downto i*8) := data(data'length-i*8-1 downto data'length-i*8-8);
end loop;
return rdata;
end function reversebyte;
-- Reverses byte order.
function reversebytemig(
data : std_logic_vector)
return std_logic_vector is
variable rdata: std_logic_vector(data'length-1 downto 0);
begin
for i in 0 to (data'length/8-1) loop
rdata(i*8+8-1 downto i*8) := data(data'left-i*8 downto data'left-i*8-7);
end loop;
return rdata;
end function reversebytemig;
-- Takes in AHB data vector 'hdata' and returns valid data on the full
-- data vector output based on 'haddr' and 'hsize' inputs together with
-- GRLIB AHB bus width. The function works down to word granularity.
function ahbselectdatanoreplica (
hdata : std_logic_vector(AHBDW-1 downto 0);
haddr : std_logic_vector(4 downto 0);
hsize : std_logic_vector(2 downto 0))
return std_logic_vector is
variable ret : std_logic_vector(AHBDW-1 downto 0);
begin -- ahbselectdatanoreplica
ret := (others => '0');
case hsize is
when HSIZE_4WORD =>
ret(AHBDW-1 downto 0) := reversebytemig(hdata(AHBDW-1 downto 0));
when HSIZE_DWORD =>
if AHBDW = 128 then
case haddr(3) is
when '0' => ret(AHBDW/2-1 downto 0) := reversebytemig(hdata(AHBDW-1 downto AHBDW/2));
when others => ret(AHBDW/2-1 downto 0) := reversebytemig(hdata(AHBDW/2-1 downto 0));
end case;
elsif AHBDW = 64 then
ret(AHBDW-1 downto 0) := reversebytemig(hdata(AHBDW-1 downto 0));
end if;
when HSIZE_WORD =>
if AHBDW = 128 then
case haddr(3 downto 2) is
when "00" => ret(1*(AHBDW/4)-1 downto 0*(AHBDW/4)) := reversebytemig(hdata(4*(AHBDW/4)-1 downto 3*(AHBDW/4)));
when "01" => ret(1*(AHBDW/4)-1 downto 0*(AHBDW/4)) := reversebytemig(hdata(3*(AHBDW/4)-1 downto 2*(AHBDW/4)));
when "10" => ret(1*(AHBDW/4)-1 downto 0*(AHBDW/4)) := reversebytemig(hdata(2*(AHBDW/4)-1 downto 1*(AHBDW/4)));
when others => ret(1*(AHBDW/4)-1 downto 0*(AHBDW/4)) := reversebytemig(hdata(1*(AHBDW/4)-1 downto 0*(AHBDW/4)));
end case;
elsif AHBDW = 64 then
case haddr(2) is
when '0' => ret(AHBDW/2-1 downto 0) := reversebytemig(hdata(AHBDW-1 downto AHBDW/2));
when others => ret(AHBDW/2-1 downto 0) := reversebytemig(hdata(AHBDW/2-1 downto 0));
end case;
elsif AHBDW = 32 then
ret(AHBDW-1 downto 0) := reversebytemig(hdata(AHBDW-1 downto 0));
end if;
when HSIZE_HWORD =>
if AHBDW = 128 then
case haddr(3 downto 1) is
when "000" => ret(1*(AHBDW/8)-1 downto 0*(AHBDW/8)) := reversebytemig(hdata(8*(AHBDW/8)-1 downto 7*(AHBDW/8)));
when "001" => ret(2*(AHBDW/8)-1 downto 1*(AHBDW/8)) := reversebytemig(hdata(7*(AHBDW/8)-1 downto 6*(AHBDW/8)));
when "010" => ret(1*(AHBDW/8)-1 downto 0*(AHBDW/8)) := reversebytemig(hdata(6*(AHBDW/8)-1 downto 5*(AHBDW/8)));
when "011" => ret(2*(AHBDW/8)-1 downto 1*(AHBDW/8)) := reversebytemig(hdata(5*(AHBDW/8)-1 downto 4*(AHBDW/8)));
when "100" => ret(1*(AHBDW/8)-1 downto 0*(AHBDW/8)) := reversebytemig(hdata(4*(AHBDW/8)-1 downto 3*(AHBDW/8)));
when "101" => ret(2*(AHBDW/8)-1 downto 1*(AHBDW/8)) := reversebytemig(hdata(3*(AHBDW/8)-1 downto 2*(AHBDW/8)));
when "110" => ret(1*(AHBDW/8)-1 downto 0*(AHBDW/8)) := reversebytemig(hdata(2*(AHBDW/8)-1 downto 1*(AHBDW/8)));
when others => ret(2*(AHBDW/8)-1 downto 1*(AHBDW/8)) := reversebytemig(hdata(1*(AHBDW/8)-1 downto 0*(AHBDW/8)));
end case;
elsif AHBDW = 64 then
case haddr(2 downto 1) is
when "00" => ret(1*(AHBDW/4)-1 downto 0*(AHBDW/4)) := reversebytemig(hdata(4*(AHBDW/4)-1 downto 3*(AHBDW/4)));
when "01" => ret(2*(AHBDW/4)-1 downto 1*(AHBDW/4)) := reversebytemig(hdata(3*(AHBDW/4)-1 downto 2*(AHBDW/4)));
when "10" => ret(1*(AHBDW/4)-1 downto 0*(AHBDW/4)) := reversebytemig(hdata(2*(AHBDW/4)-1 downto 1*(AHBDW/4)));
when others => ret(2*(AHBDW/4)-1 downto 1*(AHBDW/4)) := reversebytemig(hdata(1*(AHBDW/4)-1 downto 0*(AHBDW/4)));
end case;
elsif AHBDW = 32 then
case haddr(1) is
when '0' => ret(AHBDW/2-1 downto 0) := reversebytemig(hdata(AHBDW-1 downto AHBDW/2));
when others => ret(AHBDW-1 downto AHBDW/2) := reversebytemig(hdata(AHBDW/2-1 downto 0));
end case;
end if;
-- HSIZE_BYTE
when others =>
if AHBDW = 128 then
case haddr(3 downto 0) is
when "0000" => ret( 1*(AHBDW/16)-1 downto 0*(AHBDW/16)) := hdata(16*(AHBDW/16)-1 downto 15*(AHBDW/16));
when "0001" => ret( 2*(AHBDW/16)-1 downto 1*(AHBDW/16)) := hdata(15*(AHBDW/16)-1 downto 14*(AHBDW/16));
when "0010" => ret( 3*(AHBDW/16)-1 downto 2*(AHBDW/16)) := hdata(14*(AHBDW/16)-1 downto 13*(AHBDW/16));
when "0011" => ret( 4*(AHBDW/16)-1 downto 3*(AHBDW/16)) := hdata(13*(AHBDW/16)-1 downto 12*(AHBDW/16));
when "0100" => ret( 1*(AHBDW/16)-1 downto 0*(AHBDW/16)) := hdata(12*(AHBDW/16)-1 downto 11*(AHBDW/16));
when "0101" => ret( 2*(AHBDW/16)-1 downto 1*(AHBDW/16)) := hdata(11*(AHBDW/16)-1 downto 10*(AHBDW/16));
when "0110" => ret( 3*(AHBDW/16)-1 downto 2*(AHBDW/16)) := hdata(10*(AHBDW/16)-1 downto 9*(AHBDW/16));
when "0111" => ret( 4*(AHBDW/16)-1 downto 3*(AHBDW/16)) := hdata( 9*(AHBDW/16)-1 downto 8*(AHBDW/16));
when "1000" => ret( 1*(AHBDW/16)-1 downto 0*(AHBDW/16)) := hdata( 8*(AHBDW/16)-1 downto 7*(AHBDW/16));
when "1001" => ret( 2*(AHBDW/16)-1 downto 1*(AHBDW/16)) := hdata( 7*(AHBDW/16)-1 downto 6*(AHBDW/16));
when "1010" => ret( 3*(AHBDW/16)-1 downto 2*(AHBDW/16)) := hdata( 6*(AHBDW/16)-1 downto 5*(AHBDW/16));
when "1011" => ret( 4*(AHBDW/16)-1 downto 3*(AHBDW/16)) := hdata( 5*(AHBDW/16)-1 downto 4*(AHBDW/16));
when "1100" => ret( 1*(AHBDW/16)-1 downto 0*(AHBDW/16)) := hdata( 4*(AHBDW/16)-1 downto 3*(AHBDW/16));
when "1101" => ret( 2*(AHBDW/16)-1 downto 1*(AHBDW/16)) := hdata( 3*(AHBDW/16)-1 downto 2*(AHBDW/16));
when "1110" => ret( 3*(AHBDW/16)-1 downto 2*(AHBDW/16)) := hdata( 2*(AHBDW/16)-1 downto 1*(AHBDW/16));
when others => ret( 4*(AHBDW/16)-1 downto 3*(AHBDW/16)) := hdata( 1*(AHBDW/16)-1 downto 0*(AHBDW/16));
end case;
elsif AHBDW = 64 then
case haddr(2 downto 0) is
when "000" => ret(1*(AHBDW/8)-1 downto 0*(AHBDW/8)) := hdata(8*(AHBDW/8)-1 downto 7*(AHBDW/8));
when "001" => ret(2*(AHBDW/8)-1 downto 1*(AHBDW/8)) := hdata(7*(AHBDW/8)-1 downto 6*(AHBDW/8));
when "010" => ret(3*(AHBDW/8)-1 downto 2*(AHBDW/8)) := hdata(6*(AHBDW/8)-1 downto 5*(AHBDW/8));
when "011" => ret(4*(AHBDW/8)-1 downto 3*(AHBDW/8)) := hdata(5*(AHBDW/8)-1 downto 4*(AHBDW/8));
when "100" => ret(1*(AHBDW/8)-1 downto 0*(AHBDW/8)) := hdata(4*(AHBDW/8)-1 downto 3*(AHBDW/8));
when "101" => ret(2*(AHBDW/8)-1 downto 1*(AHBDW/8)) := hdata(3*(AHBDW/8)-1 downto 2*(AHBDW/8));
when "110" => ret(3*(AHBDW/8)-1 downto 2*(AHBDW/8)) := hdata(2*(AHBDW/8)-1 downto 1*(AHBDW/8));
when others => ret(4*(AHBDW/8)-1 downto 3*(AHBDW/8)) := hdata(1*(AHBDW/8)-1 downto 0*(AHBDW/8));
end case;
elsif AHBDW = 32 then
case haddr(1 downto 0) is
when "00" => ret(1*(AHBDW/4)-1 downto 0*(AHBDW/4)) := hdata(4*(AHBDW/4)-1 downto 3*(AHBDW/4));
when "01" => ret(2*(AHBDW/4)-1 downto 1*(AHBDW/4)) := hdata(3*(AHBDW/4)-1 downto 2*(AHBDW/4));
when "10" => ret(3*(AHBDW/4)-1 downto 2*(AHBDW/4)) := hdata(2*(AHBDW/4)-1 downto 1*(AHBDW/4));
when others => ret(4*(AHBDW/4)-1 downto 3*(AHBDW/4)) := hdata(1*(AHBDW/4)-1 downto 0*(AHBDW/4));
end case;
end if;
end case;
return ret;
end ahbselectdatanoreplica;
function ahbselectdatanoreplicastep (
haddr : std_logic_vector(7 downto 2);
hsize : std_logic_vector(2 downto 0))
return unsigned is
variable ret : unsigned(31 downto 0);
begin -- ahbselectdatanoreplicastep
ret := (others => '0');
case AHBDW is
when 128 =>
if (hsize = HSIZE_4WORD) then
ret := resize(unsigned(haddr(5 downto 2)),ret'length);
elsif (hsize = HSIZE_DWORD) then
ret := resize(unsigned(haddr(5 downto 2)),ret'length);
else
ret := resize(unsigned(haddr(5 downto 2)),ret'length);
end if;
when 64 =>
if (hsize = HSIZE_DWORD) then
ret := resize(unsigned(haddr(5 downto 2)),ret'length);
else
ret := resize(unsigned(haddr(5 downto 2)),ret'length);
end if;
-- 32
when others =>
ret := resize(unsigned(haddr(5 downto 2)),ret'length);
end case;
return ret;
end ahbselectdatanoreplicastep;
function ahbselectdatanoreplicastep16 (
haddr : std_logic_vector(7 downto 2);
hsize : std_logic_vector(2 downto 0))
return unsigned is
variable ret : unsigned(31 downto 0);
begin -- ahbselectdatanoreplicastep
ret := resize(unsigned(haddr(3 downto 2)),ret'length);
return ret;
end ahbselectdatanoreplicastep16;
function ahbselectdatanoreplicamask (
haddr : std_logic_vector(6 downto 0);
hsize : std_logic_vector(2 downto 0))
return std_logic_vector is
variable ret : std_logic_vector(AHBDW/4-1 downto 0);
variable ret128 : std_logic_vector(128/4-1 downto 0);
begin -- ahbselectdatanoreplicamask
ret := (others => '0');
ret128 := (others => '0');
case hsize is
when HSIZE_4WORD =>
ret(AHBDW/8-1 downto 0) := (others => '1');
when HSIZE_DWORD =>
if AHBDW = 128 then
case haddr(3) is
when '0' => ret(AHBDW/8/2-1 downto 0) := (others => '1');
when others => ret(AHBDW/8/2-1 downto 0) := (others => '1');
end case;
else
ret(AHBDW/8-1 downto 0) := (others => '1');
end if;
when HSIZE_WORD =>
if AHBDW = 128 then
case haddr(3 downto 2) is
when "00" => ret(1*(AHBDW/8/4)-1 downto 0*(AHBDW/8/4)) := (others => '1');
when "01" => ret(1*(AHBDW/8/4)-1 downto 0*(AHBDW/8/4)) := (others => '1');
when "10" => ret(1*(AHBDW/8/4)-1 downto 0*(AHBDW/8/4)) := (others => '1');
when others => ret(1*(AHBDW/8/4)-1 downto 0*(AHBDW/8/4)) := (others => '1');
end case;
elsif AHBDW = 64 then
case haddr(2) is
when '0' => ret(AHBDW/8/2-1 downto 0) := (others => '1');
when others => ret(AHBDW/8/2-1 downto 0) := (others => '1');
end case;
elsif AHBDW = 32 then
ret(AHBDW/8-1 downto 0) := (others => '1');
end if;
when HSIZE_HWORD =>
if AHBDW = 128 then
case haddr(3 downto 1) is
when "000" => ret128(1*(128/8/8)-1 downto 0*(128/8/8)) := (others => '1');
when "001" => ret128(2*(128/8/8)-1 downto 1*(128/8/8)) := (others => '1');
when "010" => ret128(1*(128/8/8)-1 downto 0*(128/8/8)) := (others => '1');
when "011" => ret128(2*(128/8/8)-1 downto 1*(128/8/8)) := (others => '1');
when "100" => ret128(1*(128/8/8)-1 downto 0*(128/8/8)) := (others => '1');
when "101" => ret128(2*(128/8/8)-1 downto 1*(128/8/8)) := (others => '1');
when "110" => ret128(1*(128/8/8)-1 downto 0*(128/8/8)) := (others => '1');
when others => ret128(2*(128/8/8)-1 downto 1*(128/8/8)) := (others => '1');
end case;
ret := std_logic_vector(resize(unsigned(ret128),ret'length));
elsif AHBDW = 64 then
case haddr(2 downto 1) is
when "00" => ret(1*(AHBDW/8/4)-1 downto 0*(AHBDW/8/4)) := (others => '1');
when "01" => ret(2*(AHBDW/8/4)-1 downto 1*(AHBDW/8/4)) := (others => '1');
when "10" => ret(1*(AHBDW/8/4)-1 downto 0*(AHBDW/8/4)) := (others => '1');
when others => ret(2*(AHBDW/8/4)-1 downto 1*(AHBDW/8/4)) := (others => '1');
end case;
elsif AHBDW = 32 then
case haddr(1) is
when '0' => ret(AHBDW/8/2-1 downto 0) := (others => '1');
when others => ret(AHBDW/8-1 downto AHBDW/8/2) := (others => '1');
end case;
end if;
-- HSIZE_BYTE
when others =>
if AHBDW = 128 then
case haddr(3 downto 0) is
when "0000" => ret( 0) := '1';
when "0001" => ret( 1) := '1';
when "0010" => ret( 2) := '1';
when "0011" => ret( 3) := '1';
when "0100" => ret( 0) := '1';
when "0101" => ret( 1) := '1';
when "0110" => ret( 2) := '1';
when "0111" => ret( 3) := '1';
when "1000" => ret( 0) := '1';
when "1001" => ret( 1) := '1';
when "1010" => ret( 2) := '1';
when "1011" => ret( 3) := '1';
when "1100" => ret( 0) := '1';
when "1101" => ret( 1) := '1';
when "1110" => ret( 2) := '1';
when others => ret( 3) := '1';
end case;
elsif AHBDW = 64 then
case haddr(2 downto 0) is
when "000" => ret(0) := '1';
when "001" => ret(1) := '1';
when "010" => ret(2) := '1';
when "011" => ret(3) := '1';
when "100" => ret(0) := '1';
when "101" => ret(1) := '1';
when "110" => ret(2) := '1';
when others => ret(3) := '1';
end case;
elsif AHBDW = 32 then
case haddr(1 downto 0) is
when "00" => ret(0) := '1';
when "01" => ret(1) := '1';
when "10" => ret(2) := '1';
when others => ret(3) := '1';
end case;
end if;
end case;
return ret;
end ahbselectdatanoreplicamask;
function ahbselectdatanoreplicaoutput (
haddr : std_logic_vector(7 downto 0);
counter : unsigned(31 downto 0);
hsize : std_logic_vector(2 downto 0);
rdbuffer : unsigned;
wr_count : unsigned;
replica : boolean)
return std_logic_vector is
variable ret : std_logic_vector(AHBDW-1 downto 0);
variable retrep : std_logic_vector(AHBDW-1 downto 0);
variable rdbuffer_int : unsigned(AHBDW-1 downto 0);
variable hdata : std_logic_vector(AHBDW-1 downto 0);
variable offset : unsigned(31 downto 0);
variable steps : unsigned(31 downto 0);
variable stepsint : natural;
variable hstart_offset : unsigned(31 downto 0);
variable byteOffset : unsigned(31 downto 0);
variable rdbufferByte : unsigned(AHBDW-1 downto 0);
variable hdataByte : std_logic_vector(AHBDW-1 downto 0);
begin -- ahbselectdatanoreplicaoutput
ret := (others => '0');
--hstart_offset := (others => '0');
--synopsys synthesis_off
--Print("INFO: HADDR " & tost(haddr));
--Print("INFO: hsize " & tost(hsize));
--synopsys synthesis_on
--byteOffset := shift_left( resize(unsigned(haddr(5 downto 0)),byteOffset'length) ,3);
--rdbufferByte := resize(shift_right(rdbuffer,to_integer(byteOffset)),rdbufferByte'length);
--hdataByte := std_logic_vector(rdbufferByte(AHBDW-1 downto 0));
--Print("INFO: **> byteOffset " & tost(to_integer(byteOffset)));
--Print("INFO: **> hdataByte " & tost(hdataByte));
case hsize is
when HSIZE_4WORD =>
offset := resize((unsigned(haddr(5 downto 4))&"0000000"),offset'length);
steps := resize(unsigned(wr_count(wr_count'length-1 downto 0)&"0000000"),steps'length) + offset;
hstart_offset := (others => '0');
when HSIZE_DWORD =>
if AHBDW = 128 then
offset := resize((unsigned(haddr(5 downto 4))&"0000000"),offset'length);
steps := resize(unsigned(wr_count(wr_count'length-1 downto 0)&"000000"),steps'length) + offset;
hstart_offset := shift_left( resize(unsigned(haddr(3 downto 3)),hstart_offset'length) ,5);
elsif AHBDW = 64 then
offset := resize((unsigned(haddr(5 downto 3))&"000000"),offset'length);
steps := resize(unsigned(wr_count(wr_count'length-1 downto 0)&"000000"),steps'length) + offset;
hstart_offset := (others => '0');
end if;
when others =>
if AHBDW = 128 then
offset := resize((unsigned(haddr(5 downto 4))&"0000000"),offset'length);
steps := resize(unsigned(wr_count(wr_count'length-1 downto 0)&"00000"),steps'length) + offset;
hstart_offset := shift_left( resize(unsigned(haddr(3 downto 2)),hstart_offset'length) ,5);
elsif AHBDW = 64 then
offset := resize((unsigned(haddr(5 downto 3))&"000000"),offset'length);
steps := resize(unsigned(wr_count(wr_count'length-1 downto 0)&"00000"),steps'length) + offset;
hstart_offset := shift_left( resize(unsigned(haddr(2 downto 2)),hstart_offset'length) ,5);
elsif AHBDW = 32 then
offset := resize((unsigned(haddr(5 downto 2))&"00000"),offset'length);
steps := resize(unsigned(wr_count(wr_count'length-1 downto 0)&"00000"),steps'length) + offset;
hstart_offset := (others => '0');
end if;
end case;
--synopsys synthesis_off
--Print("INFO: wr_count " & tost(to_integer(wr_count)));
--Print("INFO: offset " & tost(to_integer(offset)));
--Print("INFO: steps " & tost(to_integer(steps)));
--Print("INFO: hstart_offset " & tost(to_integer(hstart_offset)));
--synopsys synthesis_on
stepsint := to_integer(steps) + to_integer(hstart_offset);
--synopsys synthesis_off
--Print("INFO: ------> stepsint" & tost(stepsint));
--synopsys synthesis_on
rdbuffer_int := resize(shift_right(rdbuffer,stepsint),rdbuffer_int'length);
hdata := std_logic_vector(rdbuffer_int(AHBDW-1 downto 0));
--synopsys synthesis_off
--Print("INFO: rdbuffer_int " & tost( std_logic_vector(rdbuffer(511 downto 0))));
--Print("INFO: rdbuffer_int " & tost( std_logic_vector(rdbuffer(1023 downto 512))));
--Print("INFO: hdata " & tost(hdata));
--synopsys synthesis_on
ret(AHBDW-1 downto 0) := reversebyte(hdata);
--synopsys synthesis_off
--Print("INFO: ret " & tost(ret));
--synopsys synthesis_on
case hsize is
when HSIZE_4WORD =>
offset := resize(unsigned(haddr) + unsigned(counter&"0000" - hstart_offset),offset'length);
when HSIZE_DWORD =>
offset := resize(unsigned(haddr) + unsigned(counter&"000" - hstart_offset),offset'length);
when others =>
offset := resize(unsigned(haddr) + unsigned(counter&"00" - hstart_offset),offset'length);
end case;
if (replica = true) then
case hsize is
when HSIZE_4WORD =>
retrep := ahbdrivedata(ret(AHBDW-1 downto 0));
when HSIZE_DWORD =>
if AHBDW = 128 then
if offset(3) = '0' then retrep := ahbdrivedata(ret(AHBDW-1 downto AHBDW/2));
else retrep := ahbdrivedata(ret(AHBDW/2-1 downto 0)); end if;
else
retrep := ahbdrivedata(ret(AHBDW-1 downto 0));
end if;
when HSIZE_WORD =>
if AHBDW = 128 then
case offset(3 downto 2) is
when "00" => retrep := ahbdrivedata(ret(4*(AHBDW/4)-1 downto 3*(AHBDW/4)));
when "01" => retrep := ahbdrivedata(ret(3*(AHBDW/4)-1 downto 2*(AHBDW/4)));
when "10" => retrep := ahbdrivedata(ret(2*(AHBDW/4)-1 downto 1*(AHBDW/4)));
when others => retrep := ahbdrivedata(ret(1*(AHBDW/4)-1 downto 0*(AHBDW/4)));
end case;
elsif AHBDW = 64 then
if offset(2) = '0' then retrep := ahbdrivedata(ret(AHBDW-1 downto AHBDW/2));
else retrep := ahbdrivedata(ret(AHBDW/2-1 downto 0)); end if;
if (wr_count > 0) then
retrep := ahbdrivedata(ret(AHBDW-1 downto AHBDW/2));
end if;
retrep := ahbdrivedata(ret(AHBDW-1 downto AHBDW/2));
else
retrep := ahbdrivedata(ret(AHBDW-1 downto 0));
end if;
when HSIZE_HWORD =>
if AHBDW = 128 then
case offset(3 downto 1) is
when "000" => retrep := ahbdrivedata(ret(8*(AHBDW/8)-1 downto 7*(AHBDW/8)));
when "001" => retrep := ahbdrivedata(ret(7*(AHBDW/8)-1 downto 6*(AHBDW/8)));
when "010" => retrep := ahbdrivedata(ret(6*(AHBDW/8)-1 downto 5*(AHBDW/8)));
when "011" => retrep := ahbdrivedata(ret(5*(AHBDW/8)-1 downto 4*(AHBDW/8)));
when "100" => retrep := ahbdrivedata(ret(4*(AHBDW/8)-1 downto 3*(AHBDW/8)));
when "101" => retrep := ahbdrivedata(ret(3*(AHBDW/8)-1 downto 2*(AHBDW/8)));
when "110" => retrep := ahbdrivedata(ret(2*(AHBDW/8)-1 downto 1*(AHBDW/8)));
when others => retrep := ahbdrivedata(ret(1*(AHBDW/8)-1 downto 0*(AHBDW/8)));
end case;
elsif AHBDW = 64 then
case offset(1) is
when '0' => retrep := ahbdrivedata(ret(4*(AHBDW/4)-1 downto 3*(AHBDW/4)));
when others => retrep := ahbdrivedata(ret(3*(AHBDW/4)-1 downto 2*(AHBDW/4)));
-- when "10" => retrep := ahbdrivedata(ret(2*(AHBDW/4)-1 downto 1*(AHBDW/4)));
-- when others => retrep := ahbdrivedata(ret(1*(AHBDW/4)-1 downto 0*(AHBDW/4)));
end case;
else
if offset(1) = '0' then retrep := ahbdrivedata(ret(AHBDW-1 downto AHBDW/2));
else retrep := ahbdrivedata(ret(AHBDW/2-1 downto 0)); end if;
end if;
-- HSIZE_BYTE
when others =>
if AHBDW = 128 then
case offset(2 downto 0) is
when "000" => retrep := ahbdrivedata(ret(16*(AHBDW/16)-1 downto 15*(AHBDW/16)));
when "001" => retrep := ahbdrivedata(ret(15*(AHBDW/16)-1 downto 14*(AHBDW/16)));
when "010" => retrep := ahbdrivedata(ret(14*(AHBDW/16)-1 downto 13*(AHBDW/16)));
when "011" => retrep := ahbdrivedata(ret(13*(AHBDW/16)-1 downto 12*(AHBDW/16)));
when "100" => retrep := ahbdrivedata(ret(12*(AHBDW/16)-1 downto 11*(AHBDW/16)));
when "101" => retrep := ahbdrivedata(ret(11*(AHBDW/16)-1 downto 10*(AHBDW/16)));
when "110" => retrep := ahbdrivedata(ret(10*(AHBDW/16)-1 downto 9*(AHBDW/16)));
when others => retrep := ahbdrivedata(ret( 9*(AHBDW/16)-1 downto 8*(AHBDW/16)));
end case;
elsif AHBDW = 64 then
case offset(1 downto 0) is
when "00" => retrep := ahbdrivedata(ret(8*(AHBDW/8)-1 downto 7*(AHBDW/8)));
when "01" => retrep := ahbdrivedata(ret(7*(AHBDW/8)-1 downto 6*(AHBDW/8)));
when "10" => retrep := ahbdrivedata(ret(6*(AHBDW/8)-1 downto 5*(AHBDW/8)));
when others => retrep := ahbdrivedata(ret(5*(AHBDW/8)-1 downto 4*(AHBDW/8)));
end case;
else
case offset(1 downto 0) is
when "00" => retrep := ahbdrivedata(ret(4*(AHBDW/4)-1 downto 3*(AHBDW/4)));
when "01" => retrep := ahbdrivedata(ret(3*(AHBDW/4)-1 downto 2*(AHBDW/4)));
when "10" => retrep := ahbdrivedata(ret(2*(AHBDW/4)-1 downto 1*(AHBDW/4)));
when others => retrep := ahbdrivedata(ret(1*(AHBDW/4)-1 downto 0*(AHBDW/4)));
end case;
end if;
end case;
--synopsys synthesis_off
-- Print("INFO: retrep " & tost(retrep));
--synopsys synthesis_on
--ret := ahbdrivedatamig(retrep);
ret :=retrep;
end if;
return ret;
end ahbselectdatanoreplicaoutput;
function ahbselectdatanoreplicaoutput16 (
haddr : std_logic_vector(7 downto 0);
counter : unsigned(31 downto 0);
hsize : std_logic_vector(2 downto 0);
rdbuffer : unsigned;
wr_count : unsigned;
replica : boolean)
return std_logic_vector is
variable ret : std_logic_vector(AHBDW-1 downto 0);
variable retrep : std_logic_vector(AHBDW-1 downto 0);
variable rdbuffer_int : unsigned(AHBDW-1 downto 0);
variable hdata : std_logic_vector(AHBDW-1 downto 0);
variable offset : unsigned(31 downto 0);
variable steps : unsigned(31 downto 0);
variable stepsint : natural;
variable hstart_offset : unsigned(31 downto 0);
variable byteOffset : unsigned(31 downto 0);
variable rdbufferByte : unsigned(AHBDW-1 downto 0);
variable hdataByte : std_logic_vector(AHBDW-1 downto 0);
begin -- ahbselectdatanoreplicaoutput16
ret := (others => '0');
offset := resize((unsigned(haddr(3 downto 2))&"00000"),offset'length);
steps := resize(unsigned(wr_count(wr_count'length-1 downto 0)&"00000"),steps'length) + offset;
hstart_offset := (others => '0');
stepsint := to_integer(steps) + to_integer(hstart_offset);
rdbuffer_int := resize(shift_right(rdbuffer,stepsint),rdbuffer_int'length);
hdata := std_logic_vector(rdbuffer_int(AHBDW-1 downto 0));
ret(AHBDW-1 downto 0) := reversebyte(hdata);
offset := resize(unsigned(haddr) + unsigned(counter&"00" - hstart_offset),offset'length);
return ret;
end ahbselectdatanoreplicaoutput16;
-- purpose: extends 'hdata' to suite AHB data width. If the input vector's
-- length exceeds AHBDW the low part is returned.
function ahbdrivedatanoreplica (
hdata : std_logic_vector)
return std_logic_vector is
variable data : std_logic_vector(AHBDW-1 downto 0);
begin -- ahbdrivedatanoreplica
if AHBDW < hdata'length then
data := hdata(AHBDW+hdata'low-1 downto hdata'low);
else
data := (others => '0');
data(hdata'length-1 downto 0) := hdata;
end if;
return data;
end ahbdrivedatanoreplica;
end;
| gpl-3.0 | e731775c313aa24c21569e999d0d3bdc | 0.561505 | 3.591526 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/leon3v3/libcache.vhd | 1 | 23,455 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: libcache
-- File: libcache.vhd
-- Author: Jiri Gaisler, Edvin Catovic, Gaisler Research
-- Description: Cache-related types and components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.libiu.all;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
package libcache is
constant TAG_HIGH : integer := 31;
constant CTAG_LRRPOS : integer := 9;
constant CTAG_LOCKPOS : integer := 8;
constant MAXSETS : integer := 4;
-- 3-way set permutations
-- s012 => set 0 - least recently used
-- set 2 - most recently used
constant s012 : std_logic_vector(2 downto 0) := "000";
constant s021 : std_logic_vector(2 downto 0) := "001";
constant s102 : std_logic_vector(2 downto 0) := "010";
constant s120 : std_logic_vector(2 downto 0) := "011";
constant s201 : std_logic_vector(2 downto 0) := "100";
constant s210 : std_logic_vector(2 downto 0) := "101";
-- 4-way set permutations
-- s0123 => set 0 - least recently used
-- set 3 - most recently used
-- bits assigned so bits 4:3 is LRU and 1:0 is MRU
-- middle bit is 0 for 01 02 03 12 13 23, 1 for 10 20 30 21 31 32
constant s0123 : std_logic_vector(4 downto 0) := "00011";
constant s0132 : std_logic_vector(4 downto 0) := "00010";
constant s0213 : std_logic_vector(4 downto 0) := "00111";
constant s0231 : std_logic_vector(4 downto 0) := "00001";
constant s0312 : std_logic_vector(4 downto 0) := "00110";
constant s0321 : std_logic_vector(4 downto 0) := "00101";
constant s1023 : std_logic_vector(4 downto 0) := "01011";
constant s1032 : std_logic_vector(4 downto 0) := "01010";
constant s1203 : std_logic_vector(4 downto 0) := "01111";
constant s1230 : std_logic_vector(4 downto 0) := "01000";
constant s1302 : std_logic_vector(4 downto 0) := "01110";
constant s1320 : std_logic_vector(4 downto 0) := "01100";
constant s2013 : std_logic_vector(4 downto 0) := "10011";
constant s2031 : std_logic_vector(4 downto 0) := "10001";
constant s2103 : std_logic_vector(4 downto 0) := "10111";
constant s2130 : std_logic_vector(4 downto 0) := "10000";
constant s2301 : std_logic_vector(4 downto 0) := "10101";
constant s2310 : std_logic_vector(4 downto 0) := "10100";
constant s3012 : std_logic_vector(4 downto 0) := "11010";
constant s3021 : std_logic_vector(4 downto 0) := "11001";
constant s3102 : std_logic_vector(4 downto 0) := "11110";
constant s3120 : std_logic_vector(4 downto 0) := "11000";
constant s3201 : std_logic_vector(4 downto 0) := "11101";
constant s3210 : std_logic_vector(4 downto 0) := "11100";
type lru_3set_table_vector_type is array(0 to 2) of std_logic_vector(2 downto 0);
type lru_3set_table_type is array (0 to 7) of lru_3set_table_vector_type;
constant lru_3set_table : lru_3set_table_type :=
( (s120, s021, s012), -- s012
(s210, s021, s012), -- s021
(s120, s021, s102), -- s102
(s120, s201, s102), -- s120
(s210, s201, s012), -- s201
(s210, s201, s102), -- s210
(s210, s201, s102), -- dummy
(s210, s201, s102) -- dummy
);
type lru_4set_table_vector_type is array(0 to 3) of std_logic_vector(4 downto 0);
type lru_4set_table_type is array(0 to 31) of lru_4set_table_vector_type;
constant lru_4set_table : lru_4set_table_type :=
( (s2310, s0231, s0312, s0213), -- "00000" (s0231/reset)
(s2310, s0231, s0312, s0213), -- "00001" s0231
(s1320, s0321, s0132, s0123), -- "00010" s0132
(s1230, s0231, s0132, s0123), -- "00011" s0123
(s3210, s0321, s0312, s0213), -- "00100" (s0321)
(s3210, s0321, s0312, s0213), -- "00101" s0321
(s3120, s0321, s0312, s0123), -- "00110" s0312
(s2130, s0231, s0132, s0213), -- "00111" s0213
(s1230, s2301, s1302, s1203), -- "01000" s1230
(s1230, s2301, s1302, s1203), -- "01001" (s1230)
(s1320, s0321, s1032, s1023), -- "01010" s1032
(s1230, s0231, s1032, s1023), -- "01011" s1023
(s1320, s3201, s1302, s1203), -- "01100" s1320
(s1320, s3201, s1302, s1203), -- "01101" (s1320)
(s1320, s3021, s1302, s1023), -- "01110" s1302
(s1230, s2031, s1032, s1203), -- "01111" s1203
(s2130, s2301, s1302, s2103), -- "10000" s2130
(s2310, s2031, s0312, s2013), -- "10001" s2031
(s2130, s2031, s0132, s2013), -- "10010" (s2013)
(s2130, s2031, s0132, s2013), -- "10011" s2013
(s2310, s2301, s3102, s2103), -- "10100" s2310
(s2310, s2301, s3012, s2013), -- "10101" s2301
(s2130, s2031, s1032, s2103), -- "10110" (s2103)
(s2130, s2031, s1032, s2103), -- "10111" s2103
(s3120, s3201, s3102, s1203), -- "11000" s3120
(s3210, s3021, s3012, s0213), -- "11001" s3021
(s3120, s3021, s3012, s0123), -- "11010" s3012
(s3120, s3021, s3012, s0123), -- "11011" (s3012)
(s3210, s3201, s3102, s2103), -- "11100" s3210
(s3210, s3201, s3012, s2013), -- "11101" s3201
(s3120, s3021, s3102, s1023), -- "11110" s3102
(s3120, s3021, s3102, s1023) -- "11111" (s3102)
);
type lru3_repl_table_single_type is array(0 to 2) of integer range 0 to 2;
type lru3_repl_table_type is array(0 to 7) of lru3_repl_table_single_type;
constant lru3_repl_table : lru3_repl_table_type :=
( (0, 1, 2), -- s012
(0, 2, 2), -- s021
(1, 1, 2), -- s102
(1, 1, 2), -- s120
(2, 2, 2), -- s201
(2, 2, 2), -- s210
(2, 2, 2), -- dummy
(2, 2, 2) -- dummy
);
type lru4_repl_table_single_type is array(0 to 3) of integer range 0 to 3;
type lru4_repl_table_type is array(0 to 31) of lru4_repl_table_single_type;
constant lru4_repl_table : lru4_repl_table_type :=
( (0, 2, 2, 3), -- (s0231/reset)
(0, 2, 2, 3), -- s0231
(0, 1, 3, 3), -- s0132
(0, 1, 2, 3), -- s0123
(0, 3, 3, 3), -- (s0321)
(0, 3, 3, 3), -- s0321
(0, 3, 3, 3), -- s0312
(0, 2, 2, 3), -- s0213
(1, 1, 2, 3), -- s1230
(1, 1, 2, 3), -- (s1230)
(1, 1, 3, 3), -- s1032
(1, 1, 2, 3), -- s1023
(1, 1, 3, 3), -- s1320
(1, 1, 3, 3), -- (s1320)
(1, 1, 3, 3), -- s1302
(1, 1, 2, 3), -- s1203
(2, 2, 2, 3), -- s2130
(2, 2, 2, 3), -- s2031
(2, 2, 2, 3), -- (s2013)
(2, 2, 2, 3), -- s2013
(2, 2, 2, 3), -- s2310
(2, 2, 2, 3), -- s2301
(2, 2, 2, 3), -- (s2103)
(2, 2, 2, 3), -- s2103
(3, 3, 3, 3), -- s3120
(3, 3, 3, 3), -- s3021
(3, 3, 3, 3), -- s3012
(3, 3, 3, 3), -- (s3012)
(3, 3, 3, 3), -- s3210
(3, 3, 3, 3), -- s3201
(3, 3, 3, 3), -- s3102
(3, 3, 3, 3) -- (s3102)
);
type ildram_in_type is record
enable : std_ulogic;
read : std_ulogic;
write : std_ulogic;
address : std_logic_vector(19 downto 0);
end record;
subtype ctxword is std_logic_vector(M_CTX_SZ-1 downto 0);
type ctxdatatype is array (0 to 3) of ctxword;
type icram_in_type is record
address : std_logic_vector(19 downto 0);
tag : cdatatype;
twrite : std_logic_vector(0 to 3);
tenable : std_ulogic;
flush : std_ulogic;
data : std_logic_vector(31 downto 0);
denable : std_ulogic;
dwrite : std_logic_vector(0 to 3);
ldramin : ildram_in_type;
ctx : std_logic_vector(M_CTX_SZ-1 downto 0);
end record;
type icram_out_type is record
tag : cdatatype;
data : cdatatype;
ctx : ctxdatatype;
end record;
type ldram_in_type is record
address : std_logic_vector(23 downto 2);
enable : std_ulogic;
read : std_ulogic;
write : std_ulogic;
end record;
type dcram_in_type is record
address : std_logic_vector(19 downto 0);
tag : cdatatype; --std_logic_vector(31 downto 0);
ptag : cdatatype; --std_logic_vector(31 downto 0);
twrite : std_logic_vector(0 to 3);
tpwrite : std_logic_vector(0 to 3);
tenable : std_logic_vector(0 to 3);
flush : std_logic_vector(0 to 3);
data : cdatatype;
denable : std_logic_vector(0 to 3);
dwrite : std_logic_vector(0 to 3);
senable : std_logic_vector(0 to 3);
swrite : std_logic_vector(0 to 3);
saddress : std_logic_vector(19 downto 0);
faddress : std_logic_vector(19 downto 0);
ldramin : ldram_in_type;
ctx : ctxdatatype;
snhit : std_logic_vector(0 to 3);
snhitaddr : std_logic_vector(19 downto 0);
flushall : std_ulogic;
end record;
type dcram_out_type is record
tag : cdatatype;
data : cdatatype;
stag : cdatatype;
ctx : ctxdatatype;
end record;
type cram_in_type is record
icramin : icram_in_type;
dcramin : dcram_in_type;
end record;
type cram_out_type is record
icramo : icram_out_type;
dcramo : dcram_out_type;
end record;
type memory_ic_in_type is record
address : std_logic_vector(31 downto 0); -- memory address
burst : std_ulogic; -- burst request
req : std_ulogic; -- memory cycle request
su : std_ulogic; -- supervisor address space
flush : std_ulogic; -- flush in progress
end record;
type memory_ic_out_type is record
data : std_logic_vector(31 downto 0); -- memory data
ready : std_ulogic; -- cycle ready
grant : std_ulogic; --
retry : std_ulogic; --
mexc : std_ulogic; -- memory exception
cache : std_ulogic; -- cacheable data
end record;
type memory_dc_in_type is record
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
asi : std_logic_vector(3 downto 0); -- ASI for load/store
size : std_logic_vector(1 downto 0);
burst : std_ulogic;
read : std_ulogic;
req : std_ulogic;
lock : std_ulogic;
cache : std_ulogic;
end record;
type memory_dc_out_type is record
data : std_logic_vector(31 downto 0); -- memory data
ready : std_ulogic; -- cycle ready
grant : std_ulogic;
retry : std_ulogic;
mexc : std_ulogic; -- memory exception
werr : std_ulogic; -- memory write error
cache : std_ulogic; -- cacheable data
ba : std_ulogic; -- bus active (used for snooping)
bg : std_ulogic; -- bus grant (used for snooping)
end record;
constant dir : integer := 3;
constant rnd : integer := 2;
constant lrr : integer := 1;
constant lru : integer := 0;
type cache_replalgbits_type is array (0 to 3) of integer;
constant creplalg_tbl : cache_replalgbits_type := (0, 1, 0, 0);
type lru_bits_type is array(1 to 4) of integer;
constant lru_table : lru_bits_type := (1,1,3,5);
component cachemem
generic (
tech : integer range 0 to NTECH := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 0;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 0;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 7 := 0;
ilram : integer range 0 to 2 := 0;
ilramsize : integer range 1 to 512 := 1;
dlram : integer range 0 to 2 := 0;
dlramsize : integer range 1 to 512 := 1;
mmuen : integer range 0 to 1 := 0;
testen : integer range 0 to 3 := 0
);
port (
clk : in std_ulogic;
crami : in cram_in_type;
cramo : out cram_out_type;
sclk : in std_ulogic;
testin: in std_logic_vector(TESTIN_WIDTH-1 downto 0)
);
end component;
component cmvalidbits is
generic (
abits : integer;
nways : integer range 1 to 4
);
port (
clk : in std_ulogic;
caddr : in std_logic_vector(abits-1 downto 0);
cenable : in std_logic_vector(0 to nways-1);
cwrite : in std_logic_vector(0 to nways-1);
cwdata : in std_logic_vector(0 to nways-1);
crdata : out std_logic_vector(0 to nways-1);
saddr : in std_logic_vector(abits-1 downto 0);
sclear : in std_logic_vector(0 to nways-1);
flush : in std_ulogic
);
end component;
-- mmu versions
component mmu_acache
generic (
hindex : integer range 0 to NAHBMST-1 := 0;
ilinesize : integer range 4 to 8 := 4;
cached : integer := 0;
clk2x : integer := 0;
scantest : integer := 0
);
port (
rst : in std_logic;
clk : in std_logic;
mcii : in memory_ic_in_type;
mcio : out memory_ic_out_type;
mcdi : in memory_dc_in_type;
mcdo : out memory_dc_out_type;
mcmmi : in memory_mm_in_type;
mcmmo : out memory_mm_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbso : in ahb_slv_out_vector;
hclken : in std_ulogic
);
end component;
component mmu_icache
generic (
fabtech : integer := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 0;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
lram : integer range 0 to 2 := 0;
lramsize : integer range 1 to 512 := 1;
lramstart : integer range 0 to 255 := 16#8e#;
mmuen : integer := 0
);
port (
rst : in std_logic;
clk : in std_logic;
ici : in icache_in_type;
ico : out icache_out_type;
dci : in dcache_in_type;
dco : in dcache_out_type;
mcii : out memory_ic_in_type;
mcio : in memory_ic_out_type;
icrami : out icram_in_type;
icramo : in icram_out_type;
fpuholdn : in std_logic;
mmudci : in mmudc_in_type;
mmuici : out mmuic_in_type;
mmuico : in mmuic_out_type
);
end component;
component mmu_dcache
generic (
dsu : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 0;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 7 := 0;
dlram : integer range 0 to 2 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
ilram : integer range 0 to 2 := 0;
ilramstart : integer range 0 to 255 := 16#8e#;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
memtech : integer range 0 to NTECH := 0;
cached : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
smp : integer := 0;
mmuen : integer := 0;
icen : integer range 0 to 1 := 0
);
port (
rst : in std_logic;
clk : in std_logic;
dci : in dcache_in_type;
dco : out dcache_out_type;
ico : in icache_out_type;
mcdi : out memory_dc_in_type;
mcdo : in memory_dc_out_type;
ahbsi : in ahb_slv_in_type;
dcrami : out dcram_in_type;
dcramo : in dcram_out_type;
fpuholdn : in std_logic;
mmudci : out mmudc_in_type;
mmudco : in mmudc_out_type;
sclk : in std_ulogic;
ahbso : in ahb_slv_out_vector
);
end component;
component mmu_cache
generic (
hindex : integer := 0;
fabtech : integer := 0;
memtech : integer := 0;
dsu : integer range 0 to 1 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 0;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 0;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 7 := 0;
ilram : integer range 0 to 2 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 2 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
cached : integer := 0;
clk2x : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
smp : integer := 0;
mmuen : integer range 0 to 1 := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ici : in icache_in_type;
ico : out icache_out_type;
dci : in dcache_in_type;
dco : out dcache_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
crami : out cram_in_type;
cramo : in cram_out_type;
fpuholdn : in std_ulogic;
hclk, sclk : in std_ulogic;
hclken : in std_ulogic
);
end component;
component clk2xqual
port (
rst : in std_ulogic;
clk : in std_ulogic;
clk2 : in std_ulogic;
clken : out std_ulogic);
end component;
component clk2xsync
generic (
hindex : integer := 0;
clk2x : integer := 1);
port (
rst : in std_ulogic;
hclk : in std_ulogic;
clk : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbi2 : out ahb_mst_in_type;
ahbo : in ahb_mst_out_type;
ahbo2 : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbsi2 : out ahb_slv_in_type;
mcii : in memory_ic_in_type;
mcdi : in memory_dc_in_type;
mcdo : in memory_dc_out_type;
mmreq : in std_ulogic;
mmgrant : in std_ulogic;
hclken : in std_ulogic
);
end component;
function cache_cfg(repl, sets, linesize, setsize, lock, snoop,
lram, lramsize, lramstart, mmuen : integer) return std_logic_vector;
end;
package body libcache is
function cache_cfg(repl, sets, linesize, setsize, lock, snoop,
lram, lramsize, lramstart, mmuen : integer)
return std_logic_vector is
variable cfg : std_logic_vector(31 downto 0);
begin
cfg := (others => '0');
cfg(31 downto 31) := conv_std_logic_vector(lock, 1);
if sets /= 1 then
cfg(30 downto 28) := conv_std_logic_vector(repl+1, 3);
end if;
if snoop /= 0 then cfg(27) := '1'; end if;
cfg(26 downto 24) := conv_std_logic_vector(sets-1, 3);
cfg(23 downto 20) := conv_std_logic_vector(log2(setsize), 4);
cfg(19 downto 19) := conv_std_logic_vector(lram, 1);
cfg(18 downto 16) := conv_std_logic_vector(log2(linesize), 3);
cfg(15 downto 12) := conv_std_logic_vector(log2(lramsize), 4);
cfg(11 downto 4) := conv_std_logic_vector(lramstart, 8);
cfg(3 downto 3) := conv_std_logic_vector(mmuen, 1);
return(cfg);
end;
end;
| gpl-3.0 | ff187b6edafcc8c6209706f0302734bf | 0.50501 | 3.463015 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/maps/clkmux.vhd | 1 | 4,013 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: clkmux
-- File: clkmux.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: Glitch-free clock multiplexer
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.gencomp.all;
use work.allclkgen.all;
entity clkmux is
generic(tech : integer := 0;
rsel : integer range 0 to 1 := 0); -- registered sel
port(
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic;
rst : in std_ulogic := '1'
);
end entity;
architecture rtl of clkmux is
signal seli, sel0, sel1, cg0, cg1 : std_ulogic;
begin
rs : if rsel = 1 generate
rsproc : process(i0)
begin
if rising_edge(i0) then seli <= sel; end if;
end process;
end generate;
cs : if rsel = 0 generate seli <= sel; end generate;
tec : if has_clkmux(tech) = 1 generate
xil : if is_unisim(tech) = 1 generate
buf : clkmux_unisim port map(sel => seli, I0 => i0, I1 => i1, O => o);
end generate;
rhl : if tech = rhlib18t generate
buf : clkmux_rhlib18t port map(sel => seli, I0 => i0, I1 => i1, O => o);
end generate;
ut13 : if tech = ut130 generate
x0 : clkmux_ut130hbd port map (i0 => i0, i1 => i1, sel => sel, o => o);
end generate;
n2x : if tech = easic45 generate
mux : clkmux_n2x port map (i0 => i0, i1 => i1, sel => sel, o => o);
end generate;
ut90n : if tech = ut90 generate
x0 : clkmux_ut90nhbd port map (i0 => i0, i1 => i1, sel => seli, o => o);
end generate;
saed : if tech = saed32 generate
x0 : clkmux_saed32 port map (i0 => i0, i1 => i1, sel => seli, o => o);
end generate;
rhs : if tech = rhs65 generate
x0 : clkmux_rhs65 port map (i0 => i0, i1 => i1, sel => seli, o => o);
end generate;
dar : if tech = dare generate
x0 : clkmux_dare port map (i0 => i0, i1 => i1, sel => seli, o => o);
end generate;
rhu : if tech = rhumc generate
x0 : clkmux_rhumc port map (i0 => i0, i1 => i1, sel => seli, o => o);
end generate;
noxil : if not((is_unisim(tech) = 1) or (tech = rhlib18t) or (tech = ut130) or
(tech = easic45) or (tech = ut90) or (tech = saed32) or (tech = rhs65) or (tech = dare) or (tech = rhumc)) generate
o <= i0 when seli = '0' else i1;
end generate;
end generate;
gen : if has_clkmux(tech) = 0 generate
p0 : process(i0, rst)
begin
if rst = '0' then
sel0 <= '1';
elsif falling_edge(i0) then
sel0 <= (not seli) and (not sel1);
end if;
end process;
p1 : process(i1, rst)
begin
if rst = '0' then
sel1 <= '0';
elsif falling_edge(i1) then
sel1 <= seli and (not sel0);
end if;
end process;
cg0 <= i0 and sel0;
cg1 <= i1 and sel1;
o <= cg0 or cg1;
end generate;
end architecture;
| gpl-3.0 | 0856c70a05bc06e93db21d5e8269cdc6 | 0.565163 | 3.450559 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-xilinx-ml605/config.vhd | 1 | 6,993 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex6;
constant CFG_MEMTECH : integer := virtex6;
constant CFG_PADTECH : integer := virtex6;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex6;
constant CFG_CLKMUL : integer := (2);
constant CFG_CLKDIV : integer := (2);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 4;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 4;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 1*2 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 4 + 64*0;
constant CFG_ATBSZ : integer := 4;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 1;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 16;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020789#;
constant CFG_ETH_ENL : integer := 16#000123#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- Xilinx MIG
constant CFG_MIG_DDR2 : integer := 1;
constant CFG_MIG_RANKS : integer := (1);
constant CFG_MIG_COLBITS : integer := (10);
constant CFG_MIG_ROWBITS : integer := (13);
constant CFG_MIG_BANKBITS: integer := (2);
constant CFG_MIG_HMASK : integer := 16#F00#;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 16;
constant CFG_GRETH_FT : integer := 0;
constant CFG_GRETH_EDCLFT : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (16);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- I2C master
constant CFG_I2C_ENABLE : integer := 1;
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 0;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 1;
-- AMBA System ACE Interface Controller
constant CFG_GRACECTRL : integer := 1;
-- PCIEXP interface
constant CFG_PCIEXP : integer := 0;
constant CFG_PCIE_TYPE : integer := 0;
constant CFG_PCIE_SIM_MAS : integer := 0;
constant CFG_PCIEXPVID : integer := 16#0#;
constant CFG_PCIEXPDID : integer := 16#0#;
constant CFG_NO_OF_LANES : integer := 1;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
-- Xilinx MIG controller ML605 specific option
constant CFG_MIG_CLK4 : integer := 16;
end;
| gpl-3.0 | c199314cdae66853af2b684ca5db0168 | 0.646933 | 3.578813 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/ddr/ahb2avl_async.vhd | 1 | 5,848 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahb2avl_async
-- File: ahb2avl_async.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Asynchronous AHB to Avalon-MM interface based on ddr2spa
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.ddrpkg.all;
use gaisler.ddrintpkg.all;
entity ahb2avl_async is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
burstlen : integer := 8;
nosync : integer := 0;
ahbbits : integer := ahbdw;
avldbits : integer := 32;
avlabits : integer := 20
);
port (
rst_ahb : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
rst_avl : in std_ulogic;
clk_avl : in std_ulogic;
avlsi : out ddravl_slv_in_type;
avlso : in ddravl_slv_out_type
);
end;
architecture struct of ahb2avl_async is
constant l2blen: integer := log2(burstlen)+log2(32);
constant l2ddrw: integer := log2(avldbits);
constant l2ahbw: integer := log2(ahbbits);
-- Write buffer dimensions
constant wbuf_rabits_s: integer := 1+l2blen-l2ddrw;
constant wbuf_rabits_r: integer := wbuf_rabits_s;
constant wbuf_rdbits: integer := avldbits;
constant wbuf_wabits: integer := 1+l2blen-5;
constant wbuf_wdbits: integer := ahbbits;
-- Read buffer dimensions
constant rbuf_rabits: integer := l2blen-l2ahbw;
constant rbuf_rdbits: integer := wbuf_wdbits;
constant rbuf_wabits: integer := l2blen-l2ddrw; -- log2((burstlen*32)/(2*ddrbits));
constant rbuf_wdbits: integer := avldbits;
signal request : ddr_request_type;
signal start_tog : std_ulogic;
signal response : ddr_response_type;
signal wbwaddr: std_logic_vector(wbuf_wabits-1 downto 0);
signal wbwdata: std_logic_vector(wbuf_wdbits-1 downto 0);
signal wbraddr: std_logic_vector(wbuf_rabits_s-1 downto 0);
signal wbrdata: std_logic_vector(wbuf_rdbits-1 downto 0);
signal rbwaddr: std_logic_vector(rbuf_wabits-1 downto 0);
signal rbwdata: std_logic_vector(rbuf_wdbits-1 downto 0);
signal rbraddr: std_logic_vector(rbuf_rabits-1 downto 0);
signal rbrdata: std_logic_vector(rbuf_rdbits-1 downto 0);
signal wbwrite,wbwritebig,rbwrite: std_ulogic;
signal gnd: std_logic_vector(3 downto 0);
signal vcc: std_ulogic;
begin
gnd <= (others => '0');
vcc <= '1';
fe0: ddr2spax_ahb
generic map (
hindex => hindex,
haddr => haddr,
hmask => hmask,
ioaddr => 0,
iomask => 0,
burstlen => burstlen,
nosync => nosync,
ahbbits => ahbbits,
devid => GAISLER_AHB2AVLA,
ddrbits => avldbits/2
)
port map (
rst => rst_ahb,
clk_ahb => clk_ahb,
ahbsi => ahbsi,
ahbso => ahbso,
request => request,
start_tog => start_tog,
response => response,
wbwaddr => wbwaddr,
wbwdata => wbwdata,
wbwrite => wbwrite,
wbwritebig => wbwritebig,
rbraddr => rbraddr,
rbrdata => rbrdata,
hwidth => gnd(0),
beid => gnd(3 downto 0)
);
be0: ahb2avl_async_be
generic map (
avldbits => avldbits,
avlabits => avlabits,
ahbbits => ahbbits,
burstlen => burstlen,
nosync => nosync
)
port map (
rst => rst_avl,
clk => clk_avl,
avlsi => avlsi,
avlso => avlso,
request => request,
start_tog => start_tog,
response => response,
wbraddr => wbraddr,
wbrdata => wbrdata,
rbwaddr => rbwaddr,
rbwdata => rbwdata,
rbwrite => rbwrite
);
wbuf: ddr2buf
generic map (tech => 0, wabits => wbuf_wabits, wdbits => wbuf_wdbits,
rabits => wbuf_rabits_r, rdbits => wbuf_rdbits,
sepclk => 1, wrfst => 0, testen => 0)
port map ( rclk => clk_avl, renable => vcc, raddress => wbraddr(wbuf_rabits_r-1 downto 0),
dataout => wbrdata, wclk => clk_ahb, write => wbwrite,
writebig => wbwritebig, waddress => wbwaddr, datain => wbwdata,
testin => ahbsi.testin);
rbuf: ddr2buf
generic map (tech => 0, wabits => rbuf_wabits, wdbits => rbuf_wdbits,
rabits => rbuf_rabits, rdbits => rbuf_rdbits,
sepclk => 1, wrfst => 0, testen => 0)
port map ( rclk => clk_ahb, renable => vcc, raddress => rbraddr,
dataout => rbrdata,
wclk => clk_avl, write => rbwrite,
writebig => '0', waddress => rbwaddr, datain => rbwdata,
testin => ahbsi.testin);
end;
| gpl-3.0 | bce4e415f10fbd8e76cc65aa4489acb1 | 0.592681 | 3.938047 | false | false | false | false |
pwsoft/fpga_examples | rtl/video/video_dither_rgb.vhd | 1 | 3,126 | -- -----------------------------------------------------------------------
--
-- Syntiac VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2009 by Peter Wendrich ([email protected])
-- http://www.syntiac.com
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
--
-- Video dither block. Converts high precision color signal to
-- lower precision by dithering. The dither input can for example
-- come from the current X and Y coordinates or a pseudo random source.
--
-- If bypass input is 1 the dither algorithm is disabled and the output
-- is equal to the input.
--
-- This component has a delay of one clock cycle.
--
-- uses entities:
-- * video_dither
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- -----------------------------------------------------------------------
entity video_dither_rgb is
generic (
dBitsR : integer := 8;
dBitsG : integer := 8;
dBitsB : integer := 8;
qBitsR : integer := 5;
qBitsG : integer := 6;
qBitsB : integer := 5;
ditherBits : integer := 4
);
port (
clk : in std_logic;
clkEna : in std_logic := '1';
bypass : in std_logic := '0';
dither : in unsigned(ditherBits-1 downto 0);
dR : in unsigned((dBitsR-1) downto 0);
dG : in unsigned((dBitsG-1) downto 0);
dB : in unsigned((dBitsB-1) downto 0);
qR : out unsigned((qBitsR-1) downto 0);
qG : out unsigned((qBitsG-1) downto 0);
qB : out unsigned((qBitsB-1) downto 0)
);
end entity;
-- -----------------------------------------------------------------------
architecture rtl of video_dither_rgb is
begin
myRed : entity work.video_dither
generic map (
ditherBits => ditherBits,
dBits => dBitsR,
qBits => qBitsR
)
port map (
clk => clk,
clkEna => clkEna,
bypass => bypass,
dither => dither,
d => dR,
q => qR
);
myGrn : entity work.video_dither
generic map (
ditherBits => ditherBits,
dBits => dBitsG,
qBits => qBitsG
)
port map (
clk => clk,
clkEna => clkEna,
bypass => bypass,
dither => dither,
d => dG,
q => qG
);
myBlu : entity work.video_dither
generic map (
ditherBits => ditherBits,
dBits => dBitsB,
qBits => qBitsB
)
port map (
clk => clk,
clkEna => clkEna,
bypass => bypass,
dither => dither,
d => dB,
q => qB
);
end architecture;
| lgpl-2.1 | 2fc921e00d85b0ed202cff47293a014e | 0.564619 | 3.580756 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/leon3v3/grfpwxsh.vhd | 1 | 9,971 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grfpwxsh
-- File: grfpwxsh.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: GRFPU/GRFPC wrapper and FP register file
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libleon3.all;
use gaisler.libfpu.all;
entity grfpwxsh is
generic (
tech : integer range 0 to NTECH := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
id : integer range 0 to 7 := 0;
scantest : integer := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi : in fpc_in_type;
cpo : out fpc_out_type;
fpui : out grfpu_in_type;
fpuo : in grfpu_out_type;
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0)
);
end;
architecture rtl of grfpwxsh is
signal rfi1, rfi2 : fp_rf_in_type;
signal rfo1, rfo2 : fp_rf_out_type;
component grfpwsh
generic (
tech : integer range 0 to NTECH := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
id : integer range 0 to 7 := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(31 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(31 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0);
start : out std_logic;
nonstd : out std_logic;
flop : out std_logic_vector(8 downto 0);
op1 : out std_logic_vector(63 downto 0);
op2 : out std_logic_vector(63 downto 0);
opid : out std_logic_vector(7 downto 0);
flush : out std_logic;
flushid : out std_logic_vector(5 downto 0);
rndmode : out std_logic_vector(1 downto 0);
req : out std_logic_vector(2 downto 0);
res : in std_logic_vector(63 downto 0);
exc : in std_logic_vector(5 downto 0);
allow : in std_logic_vector(2 downto 0);
rdy : in std_logic;
cc : in std_logic_vector(1 downto 0);
idout : in std_logic_vector(7 downto 0)
);
end component;
begin
x0 : grfpwsh generic map (tech, pclow, dsu, disas,
id)
port map (rst,
clk,
holdn,
cpi.flush ,
cpi.exack ,
cpi.a_rs1 ,
cpi.d.pc ,
cpi.d.inst ,
cpi.d.cnt ,
cpi.d.trap ,
cpi.d.annul ,
cpi.d.pv ,
cpi.a.pc ,
cpi.a.inst ,
cpi.a.cnt ,
cpi.a.trap ,
cpi.a.annul ,
cpi.a.pv ,
cpi.e.pc ,
cpi.e.inst ,
cpi.e.cnt ,
cpi.e.trap ,
cpi.e.annul ,
cpi.e.pv ,
cpi.m.pc ,
cpi.m.inst ,
cpi.m.cnt ,
cpi.m.trap ,
cpi.m.annul ,
cpi.m.pv ,
cpi.x.pc ,
cpi.x.inst ,
cpi.x.cnt ,
cpi.x.trap ,
cpi.x.annul ,
cpi.x.pv ,
cpi.lddata ,
cpi.dbg.enable ,
cpi.dbg.write ,
cpi.dbg.fsr ,
cpi.dbg.addr ,
cpi.dbg.data ,
cpo.data ,
cpo.exc ,
cpo.cc ,
cpo.ccv ,
cpo.ldlock ,
cpo.holdn ,
cpo.dbg.data ,
rfi1.rd1addr ,
rfi1.rd2addr ,
rfi1.wraddr ,
rfi1.wrdata ,
rfi1.ren1 ,
rfi1.ren2 ,
rfi1.wren ,
rfi2.rd1addr ,
rfi2.rd2addr ,
rfi2.wraddr ,
rfi2.wrdata ,
rfi2.ren1 ,
rfi2.ren2 ,
rfi2.wren ,
rfo1.data1 ,
rfo1.data2 ,
rfo2.data1 ,
rfo2.data2 ,
fpui.start ,
fpui.nonstd ,
fpui.flop ,
fpui.op1 ,
fpui.op2 ,
fpui.opid ,
fpui.flush ,
fpui.flushid ,
fpui.rndmode ,
fpui.req ,
fpuo.res ,
fpuo.exc ,
fpuo.allow ,
fpuo.rdy ,
fpuo.cc ,
fpuo.idout
);
rf1 : regfile_3p_l3 generic map (tech, 4, 32, 1, 16,
scantest
)
port map (clk, rfi1.wraddr, rfi1.wrdata, rfi1.wren, clk, rfi1.rd1addr,
rfi1.ren1, rfo1.data1, rfi1.rd2addr, rfi1.ren2, rfo1.data2,
testin
);
rf2 : regfile_3p_l3 generic map (tech, 4, 32, 1, 16,
scantest
)
port map (clk, rfi2.wraddr, rfi2.wrdata, rfi2.wren, clk, rfi2.rd1addr,
rfi2.ren1, rfo2.data1, rfi2.rd2addr, rfi2.ren2, rfo2.data2,
testin
);
end;
| gpl-3.0 | 46a40c1f47d282e6f58c00338b242f78 | 0.478788 | 3.5598 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-xilinx-xc3sd-1800/config.vhd | 1 | 7,936 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := spartan3;
constant CFG_MEMTECH : integer := spartan3;
constant CFG_PADTECH : integer := spartan3;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := spartan3;
constant CFG_CLKMUL : integer := (8);
constant CFG_CLKDIV : integer := (25);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 2;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 2;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 4 + 64*0;
constant CFG_ATBSZ : integer := 4;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 1;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#001234#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDR2SP : integer := 1;
constant CFG_DDR2SP_INIT : integer := 1;
constant CFG_DDR2SP_FREQ : integer := (125);
constant CFG_DDR2SP_TRFC : integer := (130);
constant CFG_DDR2SP_DATAWIDTH : integer := (32);
constant CFG_DDR2SP_FTEN : integer := 0;
constant CFG_DDR2SP_FTWIDTH : integer := 0;
constant CFG_DDR2SP_COL : integer := (10);
constant CFG_DDR2SP_SIZE : integer := (128);
constant CFG_DDR2SP_DELAY0 : integer := (0);
constant CFG_DDR2SP_DELAY1 : integer := (0);
constant CFG_DDR2SP_DELAY2 : integer := (0);
constant CFG_DDR2SP_DELAY3 : integer := (0);
constant CFG_DDR2SP_DELAY4 : integer := (0);
constant CFG_DDR2SP_DELAY5 : integer := (0);
constant CFG_DDR2SP_DELAY6 : integer := (0);
constant CFG_DDR2SP_DELAY7 : integer := (0);
constant CFG_DDR2SP_NOSYNC : integer := 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 16;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- SVGA controller
constant CFG_SVGA_ENABLE : integer := 0;
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 0;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#0#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 0;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := 1;
constant CFG_SPIMCTRL_ASCALER : integer := 1;
constant CFG_SPIMCTRL_PWRUPCNT : integer := 0;
constant CFG_SPIMCTRL_OFFSET : integer := 16#0#;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 0;
constant CFG_SPICTRL_NUM : integer := 1;
constant CFG_SPICTRL_SLVS : integer := 1;
constant CFG_SPICTRL_FIFO : integer := 1;
constant CFG_SPICTRL_SLVREG : integer := 0;
constant CFG_SPICTRL_ODMODE : integer := 0;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 0;
constant CFG_SPICTRL_MAXWLEN : integer := 0;
constant CFG_SPICTRL_SYNCRAM : integer := 0;
constant CFG_SPICTRL_FT : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-3.0 | 758359aae466d1c8e835d4da20e3193a | 0.652344 | 3.573165 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/testgrouppolito/pr/d2prc.vhd | 1 | 26,079 | ------------------------------------------------------------------------------
-- Copyright (c) 2014, Pascal Trotta - Testgroup (Politecnico di Torino)
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright notice, this
-- list of conditions and the following disclaimer in the documentation and/or other
-- materials provided with the distribution.
--
-- THIS SOURCE CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-- OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
-----------------------------------------------------------------------------
-- Entity: d2prc
-- File: d2prc.vhd
-- Author: Pascal Trotta (TestGroup research group - Politecnico di Torino)
-- Contacts: [email protected] www.testgroup.polito.it
-- Description: dprc dependable mode (see the DPR IP-core user manual for operations details).
-- Last revision: 08/10/2014
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.DMA2AHB_Package.all;
library testgrouppolito;
use testgrouppolito.dprc_pkg.all;
library techmap;
use techmap.gencomp.all;
entity d2prc is
generic (
technology : integer := virtex4; -- Target technology
fifo_depth : integer := 9; -- true FIFO depth = 2**fifo_depth
crc_block : integer := 10); -- Number of 32-bit words in a CRC-block
port (
rstn : in std_ulogic; -- Asynchronous Reset input (active low)
clkm : in std_ulogic; -- Clock input
clk100 : in std_ulogic; -- 100 MHz Clock input
dmai : out DMA_In_Type; -- dma signals input
dmao : in DMA_Out_Type; -- dma signals output
icapi : out icap_in_type; -- icap input signals
icapo : in icap_out_type; -- icap output signals
apbregi : in dprc_apbregin_type; -- values from apb registers (control, address, rm_reset)
apbcontrol : out dprc_apbcontrol_type; -- control signals for apb register
rm_reset : out std_logic_vector(31 downto 0)); -- Reconfigurable modules reset (1 bit for each different reconfigurable partition);
end d2prc;
architecture d2prc_rtl of d2prc is
type icap_state is (IDLE, START, READ_LENGTH, WAIT_AB, WRITE_ICAP, WRITE_ICAP_VERIFY, END_CONFIG, ABORT, ICAP_ERROR_LATENCY);
signal pstate, nstate : icap_state;
type ahb_state is (IDLE_AHB, START_AHB, GRANTED, CHECK_CRC, WAIT_WRITE_END, CHECK_LAST_CRC, BUS_CNTL_ERROR, FIFO_FULL, ICAP_ERROR, CRC_ERROR);
signal present_state, next_state : ahb_state;
-- fifo types
type ififo_type is record
wen : std_ulogic;
waddress : std_logic_vector(fifo_depth downto 0);
waddress_gray : std_logic_vector(fifo_depth downto 0);
idata : std_logic_vector(31 downto 0);
full : std_ulogic;
end record;
type ofifo_type is record
ren : std_ulogic;
raddress : std_logic_vector(fifo_depth downto 0);
raddress_gray : std_logic_vector(fifo_depth downto 0);
odata : std_logic_vector(31 downto 0);
empty : std_ulogic;
end record;
-- cdc control signals for async_dprc
type cdc_async is record
start : std_ulogic;
stop : std_ulogic;
icap_errn : std_ulogic;
icap_end : std_ulogic;
end record;
-- dummy fifo types
type icfifo_type is record
wen : std_ulogic;
waddress : std_logic_vector(4 downto 0);
waddress_gray : std_logic_vector(4 downto 0);
idata : std_logic_vector(0 downto 0);
full : std_ulogic;
end record;
type ocfifo_type is record
ren : std_ulogic;
raddress : std_logic_vector(4 downto 0);
raddress_gray : std_logic_vector(4 downto 0);
odata : std_logic_vector(0 downto 0);
empty : std_ulogic;
end record;
signal fifo_in, regfifo_in : ififo_type;
signal cfifoi, regcfifoi : icfifo_type;
signal fifo_out, regfifo_out : ofifo_type;
signal cfifoo, regcfifoo : ocfifo_type;
signal raddr_sync, waddr_sync : std_logic_vector(fifo_depth downto 0);
signal craddr_sync, cwaddr_sync : std_logic_vector(4 downto 0);
signal cdc_ahb, rcdc_ahb, cdc_icap, rcdc_icap : cdc_async;
type regs_ahb is record
c_grant : std_logic_vector(19 downto 0);
c_ready : std_logic_vector(19 downto 0);
c_latency : std_logic_vector(2 downto 0);
rm_reset : std_logic_vector(31 downto 0);
rst_persist : std_ulogic;
address : std_logic_vector(31 downto 0);
crc_signature : std_logic_vector(31 downto 0);
c_block : std_logic_vector(integer(ceil(log2(real(crc_block))))-1 downto 0); -- size the counter depending on the actual crc block size
end record;
type regs_icap is record
c_bitstream : std_logic_vector(19 downto 0);
c_latency : std_logic_vector(2 downto 0);
c_block : std_Logic_vector(integer(ceil(log2(real(crc_block))))-1 downto 0); -- size the counter depending on the actual crc block size
end record;
signal reg, regin : regs_ahb;
signal regicap, reginicap :regs_icap;
signal rstact : std_ulogic;
begin
-- fixed signals
dmai.Data <= (others => '0');
dmai.Beat <= HINCR;
dmai.Size <= HSIZE32;
dmai.Store <= '0'; --Only read transfer requests
dmai.Reset <= not(rstn);
dmai.Address <= reg.address;
rm_reset <= reg.rm_reset;
icapi.idata <= fifo_out.odata;
fifo_in.idata <= dmao.Data;
cfifoi.idata(0) <= cfifoi.wen;
-------------------------------
-- ahb bus clock domain
-------------------------------
ahbcomb: process(raddr_sync, craddr_sync, regfifo_in, regcfifoi, rcdc_ahb, cdc_ahb, reg, present_state, rstn, rstact, apbregi, dmao)
variable vfifo_in : ififo_type;
variable vcfifoi : icfifo_type;
variable vcdc_ahb : cdc_async;
variable regv : regs_ahb;
variable raddr_sync_decoded : std_logic_vector(fifo_depth downto 0);
variable craddr_sync_decoded : std_logic_vector(4 downto 0);
begin
apbcontrol.timer_clear <= '0';
apbcontrol.status_clr <= '0';
dmai.Request <= '0';
dmai.Burst <= '0';
dmai.Lock <= '0';
apbcontrol.status_value <= (others=>'0');
apbcontrol.status_en <= '0';
apbcontrol.control_clr <= '0';
apbcontrol.timer_en <= '0';
rstact <= '0';
vfifo_in.wen := '0';
vcfifoi.wen := '0';
regv := reg;
vcdc_ahb := rcdc_ahb;
vcdc_ahb.start := '0';
vcdc_ahb.stop := '0';
-- initialize fifo signals
vfifo_in.waddress := regfifo_in.waddress;
vfifo_in.full := '0';
vcfifoi.waddress := regcfifoi.waddress;
vcfifoi.full := '0';
-- fifos full generation
gray_decoder(raddr_sync,fifo_depth,raddr_sync_decoded);
if (vfifo_in.waddress(fifo_depth)=raddr_sync_decoded(fifo_depth) and (vfifo_in.waddress(fifo_depth-1 downto 0)-raddr_sync_decoded(fifo_depth-1 downto 0))>(2**fifo_depth-16)) then
vfifo_in.full := '1';
elsif (vfifo_in.waddress(fifo_depth)/= raddr_sync_decoded(fifo_depth) and (raddr_sync_decoded(fifo_depth-1 downto 0)-vfifo_in.waddress(fifo_depth-1 downto 0))<16) then
vfifo_in.full := '1';
end if;
gray_decoder(craddr_sync,4,craddr_sync_decoded);
if (vcfifoi.waddress(4)=craddr_sync_decoded(4) and (vcfifoi.waddress(3 downto 0)-craddr_sync_decoded(3 downto 0))>10) then
vcfifoi.full := '1';
elsif (vcfifoi.waddress(4)/= craddr_sync(4) and (craddr_sync_decoded(3 downto 0)-vcfifoi.waddress(3 downto 0))<10) then
vcfifoi.full := '1';
end if;
case present_state is
when IDLE_AHB =>
if (apbregi.control(19 downto 0)/=X"00000") then
next_state <= START_AHB;
apbcontrol.timer_clear <= '1'; -- clear timer register
apbcontrol.status_clr <= '1'; -- clear status register
regv.c_grant := apbregi.control(19 downto 0);
regv.c_ready := apbregi.control(19 downto 0);
regv.c_block := std_logic_vector(to_unsigned(crc_block-1,regv.c_block'length)); -- initialize counter
regv.address := apbregi.address;
vcdc_ahb.start := '1'; -- start icap write controller
regv.crc_signature := (others=>'1'); --reset crc_signature
else
next_state <= IDLE_AHB;
end if;
vfifo_in.waddress := (others=>'0');
vcfifoi.waddress := (others=>'0');
when START_AHB =>
if (dmao.Grant and dmao.Ready)='1' then
if (regv.c_block=0) then
next_state <= CHECK_CRC;
else
next_state <= GRANTED;
end if;
else
next_state <= START_AHB;
end if;
dmai.Request <= '1'; -- Request data
dmai.Burst <= '1'; -- Burst transfer
dmai.Lock <= '1'; -- Locked transfer
vcdc_ahb.start := '1'; -- start icap write controller
when GRANTED =>
if (regv.c_block=0) and (dmao.Ready='1') then
next_state <= CHECK_CRC;
dmai.Request <= '1'; -- Request data
dmai.Burst <= '1'; -- Burst transfer
dmai.Lock <= '1'; -- Locked transfer
elsif (regv.c_grant=0) then -- if the number of granted requests is equal to the bitstream words, request last crc
next_state <= CHECK_LAST_CRC;
elsif ((vfifo_in.full='1') or (vcfifoi.full='1')) then
next_state<=FIFO_FULL;
else
next_state <= GRANTED;
dmai.Request <= '1'; -- Request data
dmai.Burst <= '1'; -- Burst transfer
dmai.Lock <= '1'; -- Locked transfer
end if;
when CHECK_LAST_CRC =>
if (regv.c_ready=1) and (dmao.Ready='1') then -- if CRC word received, check CRC and start downloading another block
if (regv.crc_signature/=dmao.Data) then -- do not write signature in data FIFO
next_state <= CRC_ERROR;
vcdc_ahb.stop := '1';
else
next_state <= WAIT_WRITE_END;
vcfifoi.wen := '1'; -- validate block
end if;
else
next_state <= CHECK_LAST_CRC;
end if;
when CHECK_CRC =>
if (dmao.Ready='1') then -- if CRC word received, check CRC and start downloading another block
if (regv.crc_signature/=dmao.Data) then -- do not write signature in data FIFO
next_state <= CRC_ERROR;
vcdc_ahb.stop := '1';
else
if (regv.c_grant=0) then
next_state <= CHECK_LAST_CRC;
else
next_state <= GRANTED;
dmai.Request <= '1'; -- Request data
dmai.Burst <= '1'; -- Burst transfer
dmai.Lock <= '1'; -- Locked transfer
end if;
vcfifoi.wen := '1'; -- validate block
end if;
regv.c_block := std_logic_vector(to_unsigned(crc_block-1,regv.c_block'length)); -- re-initialize counter
else
next_state <= CHECK_CRC;
dmai.Request <= '1'; -- Request data
dmai.Burst <= '1'; -- Burst transfer
dmai.Lock <= '1'; -- Locked transfer
end if;
when FIFO_FULL =>
if (regv.c_block=0) and (dmao.Ready='1') then
next_state <= CHECK_CRC;
elsif ((regv.c_grant=regv.c_ready) and (vfifo_in.full='0') and (vcfifoi.full='0')) then
next_state <= GRANTED;
else
next_state <= FIFO_FULL;
end if;
when WAIT_WRITE_END =>
if (regv.c_block=0) and (dmao.Ready='1') then
next_state <= CHECK_CRC;
elsif (cdc_ahb.icap_end='1') then
next_state <= IDLE_AHB;
regv.rst_persist := '0';
apbcontrol.status_value(3 downto 0) <= "1111";
apbcontrol.status_en <= '1'; -- Write Status Register
apbcontrol.control_clr <= '1'; -- Clear Control Register
else
next_state <= WAIT_WRITE_END;
end if;
when CRC_ERROR =>
next_state <= IDLE_AHB;
apbcontrol.status_value(3 downto 0) <= "0001";
apbcontrol.status_en <= '1'; -- Write Status Register
apbcontrol.control_clr <= '1'; -- Clear Control Register
vfifo_in.waddress := (others=>'0');
vcfifoi.waddress := (others=>'0');
vcdc_ahb.stop := '1';
regv.rst_persist := '1';
when BUS_CNTL_ERROR =>
next_state <= IDLE_AHB;
apbcontrol.status_value(3 downto 0) <= "0100";
apbcontrol.status_en <= '1'; -- Write Status Register
apbcontrol.control_clr <= '1'; -- Clear Control Register
vfifo_in.waddress := (others=>'0');
vcfifoi.waddress := (others=>'0');
vcdc_ahb.stop := '1';
regv.rst_persist := '1';
when ICAP_ERROR =>
next_state <= IDLE_AHB;
apbcontrol.status_value(3 downto 0) <= "1000";
apbcontrol.status_en <= '1'; -- Write Status Register
apbcontrol.control_clr <= '1'; -- Clear Control Register
vfifo_in.waddress := (others=>'0');
vcfifoi.waddress := (others=>'0');
regv.rst_persist := '1';
end case;
-- CRC check and fifo write enables
if (dmao.Ready='1') then
if (present_state/=CHECK_CRC) or (present_state=CHECK_LAST_CRC and regv.c_ready>1) then
crc(dmao.Data,reg.crc_signature,regv.crc_signature);
vfifo_in.wen := '1';
end if;
end if;
if (present_state/=IDLE_AHB) then
apbcontrol.timer_en <= '1'; -- Enable timer
rstact <= '1';
if dmao.Ready='1' then
regv.c_ready:=regv.c_ready-1;
end if;
if dmao.Grant='1' then
regv.c_grant:=regv.c_grant-1;
regv.address:=regv.address+4;
end if;
end if;
if (present_state/=IDLE_AHB) and (present_state/=CHECK_CRC) and (dmao.Ready='1') then
regv.c_block := regv.c_block-1;
end if;
if (present_state/=IDLE_AHB) and (cdc_ahb.icap_errn='0') then
next_state <= ICAP_ERROR;
end if;
if (dmao.Fault or dmao.Retry)='1' then
next_state <= BUS_CNTL_ERROR;
vcdc_ahb.stop := '1';
end if;
-- write fifos
if vfifo_in.wen = '1' then
vfifo_in.waddress := vfifo_in.waddress +1;
end if;
if vcfifoi.wen = '1' then
vcfifoi.waddress := vcfifoi.waddress +1;
end if;
gray_encoder(vfifo_in.waddress,vfifo_in.waddress_gray);
gray_encoder(vcfifoi.waddress,vcfifoi.waddress_gray);
-- fifos write address to be latched and synchronized
fifo_in.waddress_gray <= vfifo_in.waddress_gray;
cfifoi.waddress_gray <= vcfifoi.waddress_gray;
fifo_in.waddress <= vfifo_in.waddress;
cfifoi.waddress <= vcfifoi.waddress;
fifo_in.wen <= vfifo_in.wen;
cfifoi.wen <= vcfifoi.wen;
-- update fifo full
fifo_in.full <= vfifo_in.full;
cfifoi.full <= vcfifoi.full;
-- reconfigurable modules synchrounous reset generation (active high)
for i in 0 to 31 loop
regv.rm_reset(i) := not(rstn) or (apbregi.rm_reset(i) and (rstact or regv.rst_persist));
end loop;
cdc_ahb.start <= vcdc_ahb.start;
cdc_ahb.stop <= vcdc_ahb.stop;
regin <= regv;
end process;
ahbreg: process(clkm,rstn)
begin
if rstn='0' then
regfifo_in.waddress <= (others =>'0');
regcfifoi.waddress <= (others =>'0');
regfifo_in.waddress_gray <= (others =>'0');
regcfifoi.waddress_gray <= (others =>'0');
rcdc_ahb.start <= '0';
rcdc_ahb.stop <= '0';
present_state <= IDLE_AHB;
reg.rm_reset <= (others=>'0');
reg.c_grant <= (others=>'0');
reg.c_ready <= (others=>'0');
reg.c_latency <= (others=>'0');
reg.address <= (others=>'0');
reg.crc_signature <= (others=>'1');
reg.c_block <= (others=>'0');
reg.rst_persist <= '0';
elsif rising_edge(clkm) then
regfifo_in <= fifo_in;
regcfifoi <= cfifoi;
rcdc_ahb <= cdc_ahb;
present_state <= next_state;
reg <= regin;
end if;
end process;
-------------------------------
-- synchronization registers
-------------------------------
-- input d is already registered in the source clock domain
syn_gen0: for i in 0 to fifo_depth generate -- data fifo addresses
syncreg_inst0: syncreg generic map (tech => technology, stages => 2)
port map(clk => clk100, d => regfifo_in.waddress_gray(i), q => waddr_sync(i));
syncreg_inst1: syncreg generic map (tech => technology, stages => 2)
port map(clk => clkm, d => regfifo_out.raddress_gray(i), q => raddr_sync(i));
end generate;
syn_gen01: for i in 0 to 4 generate -- dummy control fifo addresses
syncreg_inst01: syncreg generic map (tech => technology, stages => 2)
port map(clk => clk100, d => regcfifoi.waddress_gray(i), q => cwaddr_sync(i));
syncreg_inst11: syncreg generic map (tech => technology, stages => 2)
port map(clk => clkm, d => regcfifoo.raddress_gray(i), q => craddr_sync(i));
end generate;
-- CDC control signals
syncreg_inst2: syncreg generic map (tech => technology, stages => 2)
port map(clk => clkm, d => rcdc_icap.icap_errn, q => cdc_ahb.icap_errn);
syncreg_inst3: syncreg generic map (tech => technology, stages => 2)
port map(clk => clkm, d => rcdc_icap.icap_end, q => cdc_ahb.icap_end);
syncreg_inst4: syncreg generic map (tech => technology, stages => 2)
port map(clk => clk100, d => rcdc_ahb.start, q => cdc_icap.start);
syncreg_inst5: syncreg generic map (tech => technology, stages => 2)
port map(clk => clk100, d => rcdc_ahb.stop, q => cdc_icap.stop);
-------------------------------
-- icap clock domain
-------------------------------
icapcomb: process(waddr_sync, cwaddr_sync, regfifo_out, fifo_out, regcfifoo, cfifoo, cdc_icap, pstate, regicap, icapo)
variable vfifo_out : ofifo_type;
variable vcfifoo : ocfifo_type;
variable vcdc_icap : cdc_async;
variable vregicap : regs_icap;
begin
icapi.cen <= '1';
icapi.wen <= '1';
vcdc_icap.icap_end := '0';
vcdc_icap.icap_errn := '1';
vregicap := regicap;
-- initialize fifo signals
vfifo_out.raddress := regfifo_out.raddress;
vfifo_out.empty := '0';
vfifo_out.ren := '0';
vcfifoo.raddress := regcfifoo.raddress;
vcfifoo.empty := '0';
vcfifoo.ren := '0';
-- fifos empty generation
gray_encoder(vfifo_out.raddress,vfifo_out.raddress_gray);
if (vfifo_out.raddress_gray=waddr_sync) then
vfifo_out.empty := '1';
end if;
gray_encoder(vcfifoo.raddress,vcfifoo.raddress_gray);
if (vcfifoo.raddress_gray=cwaddr_sync) then
vcfifoo.empty := '1';
end if;
-- fsm
case pstate is
when IDLE =>
if (cdc_icap.start='1') then
nstate <= START;
else
nstate <= IDLE;
end if;
vregicap.c_block:=std_logic_vector(to_unsigned(crc_block-1,vregicap.c_block'length)); -- initialize counter
when START =>
if (cfifoo.empty='0') then -- read first word of the bitstream & first checked block
vfifo_out.ren := '1';
vcfifoo.ren := '1';
nstate <= READ_LENGTH;
else
nstate <= START;
end if;
icapi.wen <= '0';
when READ_LENGTH =>
if (vregicap.c_block=0) then
nstate <= WAIT_AB;
else
nstate <= WRITE_ICAP;
end if;
vregicap.c_bitstream := fifo_out.odata(19 downto 0);
vfifo_out.ren := '1';
icapi.wen <= '0';
when WAIT_AB =>
if (vregicap.c_bitstream=1) then
nstate <= ICAP_ERROR_LATENCY;
elsif (cfifoo.empty='0') then -- download another block
vfifo_out.ren := '1';
vcfifoo.ren := '1';
nstate <= WRITE_ICAP;
else
nstate <= WAIT_AB;
end if;
icapi.wen <= '0';
vregicap.c_block:=std_logic_vector(to_unsigned(crc_block-1,vregicap.c_block'length)); -- reinitialize counter
icapi.cen <= not(regfifo_out.ren); --1 cycle latency with respect to fifo_out.ren
when WRITE_ICAP =>
if (vregicap.c_bitstream=1) then
nstate <= ICAP_ERROR_LATENCY;
elsif (vregicap.c_block=0) then
nstate <= WAIT_AB; -- wait for another block
vfifo_out.ren := '1';
elsif (icapo.odata(7) = '1') then -- if the ICAP is correctly initialized, then monitor ICAP status
nstate <= WRITE_ICAP_VERIFY;
vfifo_out.ren := '1';
else
nstate <= WRITE_ICAP;
vfifo_out.ren := '1';
end if;
icapi.wen <= '0';
icapi.cen <= not(regfifo_out.ren); --1 cycle latency with respect to fifo_out.ren
when WRITE_ICAP_VERIFY =>
if (vregicap.c_bitstream=1) then
nstate <= ICAP_ERROR_LATENCY;
elsif (vregicap.c_block=0) then
nstate <= WAIT_AB; -- wait for another block
vfifo_out.ren := '1';
elsif (icapo.odata(7) = '0') then -- verify ICAP status for configuration errors
nstate <= ABORT;
vcdc_icap.icap_errn:='0'; -- signal icap error to the ahb clock domain
vfifo_out.ren := '1';
else
nstate <= WRITE_ICAP_VERIFY;
vfifo_out.ren := '1';
end if;
icapi.wen <= '0';
icapi.cen <= not(regfifo_out.ren); --1 cycle latency with respect to fifo_out.ren
when END_CONFIG =>
nstate <= IDLE;
vfifo_out.raddress := (others=>'0');
vcfifoo.raddress := (others=>'0');
vcdc_icap.icap_end := '1';
when ABORT =>
if (vregicap.c_latency=4) then
nstate <= IDLE;
vregicap.c_latency := (others=>'0');
else
nstate <= ABORT;
vregicap.c_latency := vregicap.c_latency+1;
end if;
icapi.cen <= '0'; -- continue abort sequence
vcdc_icap.icap_errn:='0'; -- signal icap error to the ahb clock domain
vfifo_out.raddress := (others=>'0'); -- reset fifo address
vcfifoo.raddress := (others=>'0');
when ICAP_ERROR_LATENCY =>
if (icapo.odata(7) = '0') then -- verify ICAP status for configuration errors
nstate <= ABORT;
vregicap.c_latency := (others=>'0');
vcdc_icap.icap_errn:='0'; -- signal icap error to the ahb clock domain
elsif (vregicap.c_latency=4) then
nstate <= END_CONFIG;
vregicap.c_latency := (others=>'0');
vcdc_icap.icap_end := '1';
else
nstate <= ICAP_ERROR_LATENCY;
vregicap.c_latency := vregicap.c_latency+1;
end if;
icapi.wen <= '0';
end case;
if (cdc_icap.stop='1') then
nstate <= ABORT;
vregicap.c_latency := (others=>'0');
vfifo_out.ren := '1';
end if;
-- read fifos
if vfifo_out.ren = '1' then
vfifo_out.raddress := vfifo_out.raddress +1;
end if;
if vcfifoo.ren = '1' then
vcfifoo.raddress := vcfifoo.raddress +1;
end if;
if vfifo_out.ren = '1' then
vregicap.c_bitstream := vregicap.c_bitstream -1; -- because fifo introduces 1-cycle latency on output data
vregicap.c_block := vregicap.c_block-1;
end if;
-- fifos read address to be latched and synchronized
fifo_out.raddress_gray <= vfifo_out.raddress_gray;
cfifoo.raddress_gray <= vcfifoo.raddress_gray;
fifo_out.raddress <= vfifo_out.raddress;
cfifoo.raddress <= vcfifoo.raddress;
-- update fifo empty
fifo_out.empty <= vfifo_out.empty;
cfifoo.empty <= vcfifoo.empty;
fifo_out.ren <= vfifo_out.ren;
cfifoo.ren <= vcfifoo.ren;
cdc_icap.icap_errn <= vcdc_icap.icap_errn;
cdc_icap.icap_end <= vcdc_icap.icap_end;
reginicap <= vregicap;
end process;
icapreg: process(clk100,rstn)
begin
if rstn='0' then
regfifo_out.raddress <= (others =>'0');
regfifo_out.raddress_gray <= (others =>'0');
regfifo_out.ren <= '0';
regcfifoo.raddress <= (others =>'0');
regcfifoo.raddress_gray <= (others =>'0');
regcfifoo.ren <= '0';
regicap.c_bitstream <= (others =>'0');
regicap.c_latency <= (others =>'0');
regicap.c_block <= (others=>'0');
rcdc_icap.start <= '0';
rcdc_icap.stop <= '0';
elsif rising_edge(clk100) then
regfifo_out.raddress <= fifo_out.raddress;
regfifo_out.raddress_gray <= fifo_out.raddress_gray;
regfifo_out.ren <= fifo_out.ren;
regcfifoo.raddress <= cfifoo.raddress;
regcfifoo.raddress_gray <= cfifoo.raddress_gray;
pstate <= nstate;
regicap <= reginicap;
rcdc_icap <= cdc_icap;
end if;
end process;
--Instantiate data buffer
ram0 : syncram_2p generic map ( tech => technology, abits => fifo_depth, dbits => 32, sepclk => 1) -- 2**fifo_depth 32-bit data RAM
port map (clk100, fifo_out.ren, fifo_out.raddress(fifo_depth-1 downto 0), fifo_out.odata, clkm, fifo_in.wen, fifo_in.waddress(fifo_depth-1 downto 0), fifo_in.idata);
end d2prc_rtl;
| gpl-3.0 | 04b014d8457261885f2d9288694292d2 | 0.588443 | 3.70493 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-digilent-xup/testbench.vhd | 1 | 8,925 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 10; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 18; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal sys_clk : std_logic := '0';
signal sysace_clk : std_logic := '0';
signal sys_rst_in : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal errorn : std_logic;
signal address : std_logic_vector(27 downto 0);
signal data : std_logic_vector(15 downto 0);
signal xdata : std_logic_vector(31 downto 0);
signal romsn : std_logic;
signal iosn : std_ulogic;
signal writen, read : std_ulogic;
signal oen : std_ulogic;
signal flash_rstn : std_logic;
signal ddr_clk : std_logic_vector(2 downto 0);
signal ddr_clkb : std_logic_vector(2 downto 0);
signal ddr_clk_fb : std_logic;
signal ddr_clk_fb_out : std_logic;
signal ddr_cke : std_logic_vector(1 downto 0);
signal ddr_csb : std_logic_vector(1 downto 0);
signal ddr_web : std_ulogic; -- ddr write enable
signal ddr_rasb : std_ulogic; -- ddr ras
signal ddr_casb : std_ulogic; -- ddr cas
signal ddr_dm : std_logic_vector (7 downto 0); -- ddr dm
signal ddr_dqs : std_logic_vector (7 downto 0); -- ddr dqs
signal ddr_ad : std_logic_vector (13 downto 0); -- ddr address
signal ddr_ba : std_logic_vector (1 downto 0); -- ddr bank address
signal ddr_dq : std_logic_vector (63 downto 0); -- ddr data
signal txd1 : std_logic; -- UART1 tx data
signal rxd1 : std_logic; -- UART1 rx data
signal gpio : std_logic_vector(31 downto 0); -- I/O port
signal flash_cex : std_logic;
signal etx_clk, erx_clk, erx_dv, erx_er, erx_col, erx_crs, etx_en, etx_er : std_logic:='0';
signal erxd, etxd: std_logic_vector(3 downto 0):=(others=>'0');
signal emdc, emdio, eresetn : std_logic;
signal etx_slew : std_logic_vector(1 downto 0);
signal leds : std_logic_vector(1 downto 0);
signal vid_clock : std_ulogic;
signal vid_blankn : std_ulogic;
signal vid_syncn : std_ulogic;
signal vid_hsync : std_ulogic;
signal vid_vsync : std_ulogic;
signal vid_r : std_logic_vector(7 downto 0);
signal vid_g : std_logic_vector(7 downto 0);
signal vid_b : std_logic_vector(7 downto 0);
signal ps2clk : std_logic_vector(1 downto 0);
signal ps2data : std_logic_vector(1 downto 0);
signal cf_mpa : std_logic_vector(6 downto 0);
signal cf_mpd : std_logic_vector(15 downto 0);
signal cf_mp_ce_z : std_ulogic;
signal cf_mp_oe_z : std_ulogic;
signal cf_mp_we_z : std_ulogic;
signal cf_mpirq : std_ulogic;
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
constant lresp : boolean := false;
signal dsuen : std_ulogic;
signal dsubre : std_ulogic;
signal dsuact : std_ulogic;
begin
-- clock and reset
sys_clk <= not sys_clk after ct * 1 ns;
sysace_clk <= not sysace_clk after 15 ns;
sys_rst_in <= '0', '1' after 200 ns;
rxd1 <= 'H'; errorn <= 'H'; dsuen <= '0'; dsubre <= 'H';
ddr_clk_fb <= ddr_clk_fb_out; rxd1 <= txd1;
cf_mpd <= (others => 'H'); cf_mpirq <= 'L';
cpu : entity work.leon3mp
generic map ( fabtech, memtech, padtech, ncpu, disas, dbguart, pclow )
port map ( sys_rst_in, sys_clk, sysace_clk, errorn, dsuen, dsubre, dsuact,
ddr_clk, ddr_clkb, ddr_clk_fb, ddr_clk_fb_out, ddr_cke, ddr_csb,
ddr_web, ddr_rasb, ddr_casb, ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
rxd1, txd1, leds(0), leds(1),
-- gpio,
emdio, etx_clk, erx_clk, erxd, erx_dv, erx_er, erx_col, erx_crs,
etxd, etx_en, etx_er, emdc, eresetn, etx_slew, ps2clk, ps2data,
vid_clock, vid_blankn, vid_syncn, vid_hsync, vid_vsync,
vid_r, vid_g, vid_b,
cf_mpa, cf_mpd, cf_mp_ce_z, cf_mp_oe_z, cf_mp_we_z, cf_mpirq
);
ddrmem : for i in 0 to 1 generate
-- u3 : mt46v16m16
-- generic map (index => 3, fname => sdramfile, bbits => 64)
-- PORT MAP(
-- Dq => ddr_dq(15 downto 0), Dqs => ddr_dqs(1 downto 0), Addr => ddr_ad(12 downto 0),
-- Ba => ddr_ba, Clk => ddr_clk(i), Clk_n => ddr_clkb(i), Cke => ddr_cke(i),
-- Cs_n => ddr_csb(i), Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
-- Dm => ddr_dm(1 downto 0));
-- u2 : mt46v16m16
-- generic map (index => 2, fname => sdramfile, bbits => 64)
-- PORT MAP(
-- Dq => ddr_dq(31 downto 16), Dqs => ddr_dqs(3 downto 2), Addr => ddr_ad(12 downto 0),
-- Ba => ddr_ba, Clk => ddr_clk(i), Clk_n => ddr_clkb(i), Cke => ddr_cke(i),
-- Cs_n => ddr_csb(i), Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
-- Dm => ddr_dm(3 downto 2));
-- u1 : mt46v16m16
-- generic map (index => 1, fname => sdramfile, bbits => 64)
-- PORT MAP(
-- Dq => ddr_dq(47 downto 32), Dqs => ddr_dqs(5 downto 4), Addr => ddr_ad(12 downto 0),
-- Ba => ddr_ba, Clk => ddr_clk(i), Clk_n => ddr_clkb(i), Cke => ddr_cke(i),
-- Cs_n => ddr_csb(i), Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
-- Dm => ddr_dm(5 downto 4));
-- u0 : mt46v16m16
-- generic map (index => 0, fname => sdramfile, bbits => 64)
-- PORT MAP(
-- Dq => ddr_dq(63 downto 48), Dqs => ddr_dqs(7 downto 6), Addr => ddr_ad(12 downto 0),
-- Ba => ddr_ba, Clk => ddr_clk(i), Clk_n => ddr_clkb(i), Cke => ddr_cke(i),
-- Cs_n => ddr_csb(i), Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
-- Dm => ddr_dm(7 downto 6));
ddr0 : ddrram
generic map(width => 64, abits => 14, colbits => 9, rowbits => 14,
implbanks => 1, fname => sdramfile, speedbin => 1, density => 1)
port map (ck => ddr_clk(i), cke => ddr_cke(i), csn => ddr_csb(i),
rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web,
dm => ddr_dm, ba => ddr_ba, a => ddr_ad, dq => ddr_dq,
dqs => ddr_dqs);
end generate;
prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile)
port map (address(romdepth-1 downto 0), data,
gnd, gnd, romsn, writen, oen);
iuerr : process
begin
wait for 5000 ns;
if to_x01(errorn) = '1' then wait on errorn; end if;
assert (to_x01(errorn) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
xdata <= "0000000000000000" & data;
test0 : grtestmod
port map ( sys_rst_in, sys_clk, errorn, address(20 downto 1), xdata,
iosn, oen, writen, open);
data <= buskeep(data), (others => 'H') after 250 ns;
ddr_dq <= buskeep(ddr_dq), (others => 'H') after 250 ns;
end ;
| gpl-3.0 | 60897eb6b0f4287acfd33fef90a22ba0 | 0.593501 | 3.157057 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/maps/memrwcol.vhd | 1 | 5,107 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: memrwcol
-- File: memrwcol.vhd
-- Author: Magnus Hjorth - Cobham Gaisler
-- Description: Sub-block for R/W collision management in syncram_2p/dp
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity memrwcol is
generic (
techwrfst : integer;
techrwcol : integer;
techrdhold : integer;
abits: integer;
dbits: integer;
sepclk: integer;
wrfst: integer
);
port (
clk1 : in std_ulogic;
clk2 : in std_ulogic;
uenable1 : in std_ulogic;
uwrite1 : in std_ulogic;
uaddress1: in std_logic_vector((abits-1) downto 0);
udatain1 : in std_logic_vector((dbits-1) downto 0);
udataout1: out std_logic_vector((dbits-1) downto 0);
uenable2 : in std_ulogic;
uwrite2 : in std_ulogic;
uaddress2: in std_logic_vector((abits-1) downto 0);
udatain2 : in std_logic_vector((dbits-1) downto 0);
udataout2: out std_logic_vector((dbits-1) downto 0);
menable1 : out std_ulogic;
menable2 : out std_ulogic;
mdataout1: in std_logic_vector((dbits-1) downto 0);
mdataout2: in std_logic_vector((dbits-1) downto 0);
testmode : in std_ulogic;
testdata : in std_logic_vector((dbits-1) downto 0)
);
end;
architecture rtl of memrwcol is
type memrwcol_regs is record
address : std_logic_vector((abits-1) downto 0);
mux : std_ulogic; -- Read gated prev cycle
wdata : std_logic_vector((dbits-1) downto 0);
wren : std_ulogic;
end record;
signal r1, r1i, r2, r2i: memrwcol_regs;
constant iwrfst : integer := (1-techwrfst) * wrfst;
begin
comb: process(uenable1,uwrite1,uaddress1,udatain1,mdataout1,
uenable2,uwrite2,uaddress2,udatain2,mdataout2,
r1,r2,testmode,testdata)
variable v1,v2: memrwcol_regs;
variable ven1,ven2: std_ulogic;
variable vout1,vout2: std_logic_vector((dbits-1) downto 0);
variable domux1,domux2: std_ulogic;
begin
v1.address := uaddress1;
v1.mux := '0';
v1.wdata := udatain1;
v1.wren := uenable1 and uwrite1;
v2.address := uaddress2;
v2.mux := '0';
v2.wdata := udatain2;
v2.wren := uenable2 and uwrite2;
ven1 := uenable1;
ven2 := uenable2;
vout1 := mdataout1;
vout2 := mdataout2;
domux1 := '0';
domux2 := '0';
if sepclk=0 and techrwcol=1 then
if uaddress1=uaddress2 then
if v1.wren='1' then
ven2 := '0';
v2.mux := '1';
end if;
if v2.wren='1' then
ven1 := '0';
v1.mux := '1';
end if;
end if;
domux1 := r1.mux;
domux2 := r2.mux;
elsif sepclk=0 and iwrfst=1 then
if r1.address=r2.address then
domux1 := r2.wren;
domux2 := r1.wren;
end if;
end if;
if (domux1='1' and wrfst=1) or testmode='1' then
vout1 := r2.wdata;
end if;
if (domux2='1' and wrfst=1) or testmode='1' then
vout2 := r1.wdata;
end if;
if (techrwcol=1 or iwrfst=1) and techrdhold=1 then
-- If technology provides read-hold characteristics but not
-- write-first behavior, make sure that works also in case
-- of collisions. This is done by holding all the
-- registers of the rw collision logic so the muxing stays active
-- with the same write data.
if (domux1='1' and uenable1='0') or (domux2='1' and uenable2='0') then
v1 := r1;
v2 := r2;
end if;
end if;
if testmode='1' then
v1.wdata := testdata;
v2.wdata := testdata;
end if;
r1i <= v1;
r2i <= v2;
menable1 <= ven1;
menable2 <= ven2;
udataout1 <= vout1;
udataout2 <= vout2;
end process;
regs1: process(clk1) is
begin
if rising_edge(clk1) then
r1 <= r1i;
end if;
end process;
regs2: process(clk2) is
begin
if rising_edge(clk2) then
r2 <= r2i;
end if;
end process;
end;
| gpl-3.0 | 3969c9b2ed280dff1bb449bc14acb98f | 0.594282 | 3.348852 | false | true | false | false |
hoglet67/CoPro6502 | src/CPU65C02/reg_sp.vhd | 1 | 5,305 | -- VHDL Entity r65c02_tc.reg_sp.symbol
--
-- Created:
-- by - eda.UNKNOWN (ENTW-7HPZ200)
-- at - 12:04:08 06.09.2018
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
entity reg_sp is
port(
adr_low_i : in std_logic_vector (7 downto 0);
clk_clk_i : in std_logic;
ld_low_i : in std_logic;
ld_sp_i : in std_logic;
rst_rst_n_i : in std_logic;
sel_sp_as_i : in std_logic;
sel_sp_in_i : in std_logic;
adr_sp_o : out std_logic_vector (15 downto 0)
);
-- Declarations
end reg_sp ;
-- (C) 2008 - 2018 Jens Gutschmidt
-- (email: [email protected])
--
-- Versions:
-- Revision 1.7 2013/07/21 11:11:00 jens
-- - Changing the title block and internal revision history
--
-- Revision 1.6 2009/01/04 10:20:47 eda
-- Changes for cosmetic issues only
--
-- Revision 1.5 2009/01/04 09:23:10 eda
-- - Delete unused nets and blocks (same as R6502_TC)
-- - Rename blocks
--
-- Revision 1.4 2009/01/03 16:53:02 eda
-- - Unused nets and blocks deleted
-- - Renamed blocks
--
-- Revision 1.3 2009/01/03 16:42:02 eda
-- - Unused nets and blocks deleted
-- - Renamed blocks
--
-- Revision 1.2 2008/12/31 19:31:24 eda
-- Production Release
--
--
--
-- VHDL Architecture r65c02_tc.reg_sp.struct
--
-- Created:
-- by - eda.UNKNOWN (ENTW-7HPZ200)
-- at - 12:04:08 06.09.2018
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5)
--
-- COPYRIGHT (C) 2008 - 2018 by Jens Gutschmidt
--
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
architecture struct of reg_sp is
-- Architecture declarations
-- Internal signal declarations
signal adr_sp_low_o_i : std_logic_vector(7 downto 0);
signal load_o_i : std_logic;
signal result_low1_o_i : std_logic_vector(7 downto 0);
signal result_low_o_i : std_logic_vector(7 downto 0);
signal sp_as_n_o_i : std_logic;
signal val_one : std_logic_vector(7 downto 0);
-- Implicit buffer signal declarations
signal adr_sp_o_internal : std_logic_vector (15 downto 0);
-- ModuleWare signal declarations(v1.12) for instance 'U_0' of 'adff'
signal mw_U_0reg_cval : std_logic_vector(7 downto 0);
begin
-- ModuleWare code(v1.12) for instance 'U_11' of 'addsub'
u_11combo_proc: process (adr_sp_low_o_i, val_one, sp_as_n_o_i)
variable temp_din0 : std_logic_vector(8 downto 0);
variable temp_din1 : std_logic_vector(8 downto 0);
variable temp_sum : unsigned(8 downto 0);
variable temp_carry : std_logic;
begin
temp_din0 := '0' & adr_sp_low_o_i;
temp_din1 := '0' & val_one;
temp_carry := '0';
if (sp_as_n_o_i = '1') then
temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry;
else
temp_sum := unsigned(temp_din0) - unsigned(temp_din1) - temp_carry;
end if;
result_low_o_i <= conv_std_logic_vector(temp_sum(7 downto 0),8);
end process u_11combo_proc;
-- ModuleWare code(v1.12) for instance 'U_0' of 'adff'
adr_sp_o_internal(7 DOWNTO 0) <= mw_U_0reg_cval;
u_0seq_proc: process (clk_clk_i, rst_rst_n_i)
begin
if (rst_rst_n_i = '0') then
mw_U_0reg_cval <= "00000000";
elsif (clk_clk_i'event and clk_clk_i='1') then
if (load_o_i = '1') then
mw_U_0reg_cval <= result_low1_o_i;
end if;
end if;
end process u_0seq_proc;
-- ModuleWare code(v1.12) for instance 'U_6' of 'and'
load_o_i <= ld_sp_i and ld_low_i;
-- ModuleWare code(v1.12) for instance 'U_3' of 'buff'
adr_sp_o_internal(15 DOWNTO 8) <= val_one;
-- ModuleWare code(v1.12) for instance 'U_4' of 'constval'
val_one <= "00000001";
-- ModuleWare code(v1.12) for instance 'U_2' of 'inv'
sp_as_n_o_i <= not(sel_sp_as_i);
-- ModuleWare code(v1.12) for instance 'U_8' of 'mux'
u_8combo_proc: process(result_low_o_i, adr_low_i, sel_sp_in_i)
begin
case sel_sp_in_i is
when '0' => result_low1_o_i <= result_low_o_i;
when '1' => result_low1_o_i <= adr_low_i;
when others => result_low1_o_i <= (others => 'X');
end case;
end process u_8combo_proc;
-- ModuleWare code(v1.12) for instance 'U_10' of 'tap'
adr_sp_low_o_i <= adr_sp_o_internal(7 downto 0);
-- Instance port mappings.
-- Implicit buffered output assignments
adr_sp_o <= adr_sp_o_internal;
end struct;
| gpl-3.0 | 8f14a9482b039ae1b5b79cc06730d472 | 0.609991 | 2.950501 | false | false | false | false |
freecores/cryptopan_core | rtl/cryptopan_unit.vhd | 1 | 6,111 | --
-- This file is part of the Crypto-PAn core.
--
-- Copyright (c) 2007 The University of Waikato, Hamilton, New Zealand.
-- Authors: Anthony Blake ([email protected])
--
-- All rights reserved.
--
-- This code has been developed by the University of Waikato WAND
-- research group. For further information please see http://www.wand.net.nz/
--
-- This source file is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This source is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with libtrace; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.cryptopan.all;
entity cryptopan_unit is
port (
clk : in std_logic;
reset : in std_logic;
ready : out std_logic;
key : in std_logic_vector(255 downto 0);
key_wren : in std_logic;
ip_in : in std_logic_vector(31 downto 0);
ip_wren : in std_logic;
ip_out : out std_logic_vector(31 downto 0);
ip_dv : out std_logic
);
end cryptopan_unit;
architecture rtl of cryptopan_unit is
component aes_encrypt_unit
port (
key_in : in std_logic_vector(127 downto 0);
key_wren : in std_logic;
ready : out std_logic;
data_in : in std_logic_vector(127 downto 0);
data_wren : in std_logic;
data_dv : out std_logic;
data_out : out std_logic_vector(127 downto 0);
clk : in std_logic;
reset : in std_logic);
end component;
signal aes_din, aes_dout : std_logic_vector(127 downto 0);
signal aes_din_wren, aes_dout_dv : std_logic;
signal ready_int : std_logic;
signal m_pad : std_logic_vector(127 downto 0);
signal ip_reg : std_logic_vector(31 downto 0);
signal read_ip_reg : std_logic_vector(31 downto 0);
type states is (INIT, INITWAIT, IDLE, BUSY);
signal state : states;
type read_states is (INIT, IDLE, BUSY);
signal read_state : read_states;
type output_states is (IDLE, BUSY);
signal output_state : output_states;
-- signal shift_counter : std_logic_vector(31 downto 0);
signal output_counter : std_logic_vector(4 downto 0);
signal first4bytes_pad : std_logic_vector(31 downto 0);
signal first4bytes_input : std_logic_vector(31 downto 0);
signal mask_onehot : std_logic_vector(31 downto 0);
signal mask_onehot_inv : std_logic_vector(31 downto 0);
signal ip_out_int : std_logic_vector(31 downto 0);
begin
mask_onehot_inv <= not mask_onehot;
with state select
ready <=
'1' when IDLE,
'0' when others;
first4bytes_pad <= m_pad(127 downto 96);
first4bytes_input <= (ip_reg and mask_onehot_inv) or (first4bytes_pad and mask_onehot);
LOAD_UNIT_LOGIC : process (clk, reset)
begin
if reset = '1' then
state <= INIT;
aes_din_wren <= '0';
aes_din <= (others => '0');
mask_onehot <= (others => '0');
ip_reg <= (others => '0');
elsif clk'event and clk = '1' then
mask_onehot <= (others => '1');
aes_din_wren <= '0';
if state = INIT and ready_int = '1' then
aes_din <= key(255 downto 128);
aes_din_wren <= '1';
state <= INITWAIT;
elsif state = INITWAIT and aes_dout_dv = '1' then
state <= IDLE;
elsif state = IDLE and ip_wren = '1' then
state <= BUSY;
ip_reg <= ip_in;
elsif state = BUSY then
if mask_onehot(0) = '1' then
aes_din_wren <= '1';
aes_din <= first4bytes_input & m_pad(95 downto 0);
else
state <= IDLE;
end if;
mask_onehot(31) <= '0';
for i in 30 downto 0 loop
mask_onehot(i) <= mask_onehot(i+1);
end loop;
end if;
end if;
end process LOAD_UNIT_LOGIC;
READ_UNIT_LOGIC : process (clk, reset)
begin
if reset = '1' then
m_pad <= (others => '0');
read_state <= INIT;
ip_out <= (others => '0');
ip_dv <= '0';
output_state <= IDLE;
read_ip_reg <= (others => '0');
output_counter <= (others => '1');
elsif clk'event and clk = '1' then
ip_dv <= '0';
if read_state = INIT then
if aes_dout_dv = '1' then
m_pad <= aes_dout;
read_state <= IDLE;
end if;
elsif read_state = IDLE then
if aes_dout_dv = '1' then
if output_counter = "11111" then
read_ip_reg <= ip_reg;
end if;
output_counter <= output_counter - 1;
ip_out_int <= ip_out_int(30 downto 0) & aes_dout(127);
end if;
if output_counter = "00000" then
output_state <= BUSY;
end if;
end if;
if output_state = BUSY then
output_state <= IDLE;
ip_dv <= '1';
ip_out <= ip_out_int xor read_ip_reg;
end if;
end if;
end process READ_UNIT_LOGIC;
-- OUTPUT_UNIT_LOGIC : process (clk, reset)
-- begin
-- if reset = '1' then
-- ip_out <= (others => '0');
-- ip_dv <= '0';
-- output_state <= IDLE;
-- elsif clk'event and clk = '1' then
-- end if;
-- end process OUTPUT_UNIT_LOGIC;
AES0 : aes_encrypt_unit
port map (
key_in => key(127 downto 0),
key_wren => key_wren,
ready => ready_int,
data_in => aes_din,
data_wren => aes_din_wren,
data_dv => aes_dout_dv,
data_out => aes_dout,
clk => clk,
reset => reset);
end rtl;
| gpl-2.0 | ec647bcd17ff9553688f6647d4c37e27 | 0.571756 | 3.383721 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-gr-pci-xc5v/lfclkgen.vhd | 1 | 3,356 | -------------------------------------------------------------------------------
-- Low-frequency clock generator for Virtex 4/5
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
library unisim;
use unisim.BUFG;
use unisim.DCM;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity lfclkgen is
generic (
dv_div : real;
fx_mul : integer;
fx_div : integer);
port (
resetin : in std_logic;
clkin : in std_logic;
clk : out std_logic;
resetout: out std_logic);
end;
architecture struct of lfclkgen is
-- attribute CLKIN_PERIOD : string;
-- attribute CLKIN_PERIOD of brm_dcm_fx: label is "20";
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFG port ( O : out std_logic; I : in std_logic); end component;
signal gnd, clk0, clk1, clk_fb0, clk_fb1, clk_dv, clk_div, clk_fx,clk_fxo, rst0, lock0 : std_logic;
signal rst1 : std_logic_vector(3 downto 0);
begin
process(clk_fxo, resetin)
begin
if resetin = '0' then rst1 <= "1111";
elsif rising_edge(clk_fxo) then rst1 <= rst1(2 downto 0) & not lock0; end if;
end process;
gnd <= '0';
rst0 <= not resetin;
bufg0 : BUFG port map (I => clk_dv, O => clk);
bufg1 : BUFG port map (I => clk0, O => clk_fb0);
bufg2 : BUFG port map (I => clk1, O => clk_fb1);
bufg3 : BUFG port map (I => clk_fx, O => clk_fxo);
brm_dcm_fx: DCM
generic map (CLKFX_MULTIPLY => fx_mul, CLKFX_DIVIDE => fx_div)
port map ( CLKIN => clkin, CLKFB => clk_fb0, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => rst0, CLK0 => clk0,
LOCKED => lock0, CLKFX => clk_fx);
brm_dcm_dv: DCM
generic map (CLKDV_DIVIDE => dv_div)
port map ( CLKIN => clk_fxo, CLKFB => clk_fb1, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => rst1(2), CLK0 => clk1,
LOCKED => resetout, CLKDV => clk_dv);
end;
| gpl-3.0 | 97650bb9aaf7c3fe97a46b24b93270af | 0.542312 | 3.438525 | false | false | false | false |
yishinli/emc2 | src/hal/drivers/mesa-hostmot2/firmware/src/d8o8.vhd | 1 | 16,530 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
--
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
-- http://www.mesanet.com
--
-- This program is is licensed under a disjunctive dual license giving you
-- the choice of one of the two following sets of free software/open source
-- licensing terms:
--
-- * GNU General Public License (GPL), version 2.0 or later
-- * 3-clause BSD License
--
--
-- The GNU GPL License:
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- The 3-clause BSD License:
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- * Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- * Neither the name of Mesa Electronics nor the names of its
-- contributors may be used to endorse or promote products
-- derived from this software without specific prior written
-- permission.
--
--
-- Disclaimer:
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
-- Small 8 bit Harvard Arch accumulator oriented processor ~150 slices:
-- 1 clk/inst, >120 MHz operation in Spartan3 >60 MHz in Spartan2
-- 8 bit data, 16 bit instruction width
-- 6 JMP instructions:
-- JMP, JMPNZ, JMPZ, JMPNC, JMPC, JSR
-- 9 basic memory reference instructions:
-- OR, XOR, AND, ADD, ADDC, SUB, SUBB, LDA, STA
-- 13 operate instructions, load immediate, rotate, index load/store:
-- LDI, RCL, RCR, LDYL, LDXL, STYL, STXL, LDYH, LDXH, STYL, STXH, RTT, TTR
-- 1K or 2K words instruction space
-- 4K words data space
-- 2 index registers for indirect memory access
-- 8 bit offset for indirect addressing (ADD sinetable(6) etc)
-- 11 bit direct memory addressing range
-- 12 bit indirect addressing range with 8 bit offset range
-- 2 levels of subroutine call/return
-- Starts at address 0 from reset
-- THE BAD NEWS: pipelined processor with no locks so --->
-- Instruction hazards:
-- 2 instructions following conditional jumps always executed
-- TTR must precede JSR by at least 2 instructions
-- RTT must precede JSR by at least 2 instructions
-- TTR must precede JMP@R by at least 2 instructions
-- Data hazards:
-- Stored data requires 3 instructions before fetch
-- Address hazards:
-- Fetches via index register require 2 instructions from ST(X,Y) or ADDI(X,Y)
-- to actual fetch (STA via index takes no extra delay)
-------------------------------------------------------------------------------
entity DumbAss8 is
generic(
width : integer := 8; -- data width
iwidth : integer := 16; -- instruction width
maddwidth : integer := 12; -- memory address width
paddwidth : integer := 10 -- program counter width
);
port (
clk : in std_logic;
reset : in std_logic;
iabus : out std_logic_vector(paddwidth-1 downto 0); -- program address bus
idbus : in std_logic_vector(iwidth-1 downto 0); -- program data bus
mradd : out std_logic_vector(maddwidth-1 downto 0); -- memory read address
mwadd : out std_logic_vector(maddwidth-1 downto 0); -- memory write address
mibus : in std_logic_vector(width-1 downto 0); -- memory data in bus
mobus : out std_logic_vector(width-1 downto 0); -- memory data out bus
mwrite: out std_logic; -- memory write signal
mread: out std_logic; -- memory read signal
carryflg : out std_logic -- carry flag
);
end DumbAss8;
architecture Behavioral of DumbAss8 is
constant carrymask : std_logic_vector := b"0_1111_1111"; -- mask to drop carry bit
constant ProcVersion : std_logic_vector (width downto 0) := conv_std_logic_vector(12,width);
-- basic op codes
-- Beware, certain bits are used to simpilfy decoding - dont change without knowing what you are doing...
constant opr : std_logic_vector (3 downto 0) := x"0";
constant jmp : std_logic_vector (3 downto 0) := x"1";
constant jmpnz : std_logic_vector (3 downto 0) := x"2";
constant jmpz : std_logic_vector (3 downto 0) := x"3";
constant jmpnc : std_logic_vector (3 downto 0) := x"4";
constant jmpc : std_logic_vector (3 downto 0) := x"5";
constant jsr : std_logic_vector (3 downto 0) := x"6";
constant lda : std_logic_vector (3 downto 0) := x"7";
constant lor : std_logic_vector (3 downto 0) := x"8";
constant lxor : std_logic_vector (3 downto 0) := x"9";
constant land : std_logic_vector (3 downto 0) := x"A";
constant sta : std_logic_vector (3 downto 0) := x"B";
constant add : std_logic_vector (3 downto 0) := x"C";
constant addc : std_logic_vector (3 downto 0) := x"D";
constant sub : std_logic_vector (3 downto 0) := x"E";
constant subc : std_logic_vector (3 downto 0) := x"F";
-- operate instructions
constant nop : std_logic_vector (3 downto 0) := x"0";
-- immediate load type
constant ldi : std_logic_vector (3 downto 0) := x"1";
-- accumulator operate type
constant rotcl : std_logic_vector (3 downto 0) := x"2";
constant rotcr : std_logic_vector (3 downto 0) := x"3";
-- index register load/store in address order
constant ldxl : std_logic_vector (3 downto 0) := x"4";
constant ldyl : std_logic_vector (3 downto 0) := x"5";
constant ldxh : std_logic_vector (3 downto 0) := x"6";
constant ldyh : std_logic_vector (3 downto 0) := x"7";
constant stxl : std_logic_vector (3 downto 0) := x"8";
constant styl : std_logic_vector (3 downto 0) := x"9";
constant stxh : std_logic_vector (3 downto 0) := x"A";
constant styh : std_logic_vector (3 downto 0) := x"B";
constant addix : std_logic_vector (3 downto 0) := x"C";
constant addiy : std_logic_vector (3 downto 0) := x"D";
-- return register save/restore
constant rtt : std_logic_vector (3 downto 0) := x"E";
constant ttr : std_logic_vector (3 downto 0) := x"F";
-- basic signals
signal accumcar : std_logic_vector (width downto 0) := ProcVersion; -- accumulator+carry
alias accum : std_logic_vector (width-1 downto 0) is accumcar(width-1 downto 0);
alias carrybit : std_logic is accumcar(width);
signal maskedcarry : std_logic;
signal pc : std_logic_vector (paddwidth -1 downto 0); -- program counter - 10 bits = 1k
signal mra : std_logic_vector (maddwidth -1 downto 0); -- memory read address - 11 bits = 2k
signal mwa : std_logic_vector (maddwidth -1 downto 0); -- memory write address - 11 bits = 2k
signal id1 : std_logic_vector (iwidth -1 downto 0); -- instruction pipeline 1
signal id2 : std_logic_vector (iwidth -1 downto 0); -- instruction pipeline 2
alias opcode0 : std_logic_vector (3 downto 0) is idbus (iwidth-1 downto iwidth-4); -- main opcode at pipe0
alias opcode2 : std_logic_vector (3 downto 0) is id2 (iwidth-1 downto iwidth-4); -- main opcode at pipe2
alias Arith : std_logic_vector (1 downto 0) is id2 (iwidth-1 downto iwidth-2);
alias WithCarry : std_logic is id2(iwidth-4); -- indicates add with carry or subtract with borrow
alias Minus is id2(iwidth-3); -- indicates subtract
alias opradd0 : std_logic_vector (maddwidth -1 downto 0) is idbus (maddwidth -1 downto 0); -- operand address at pipe0
alias opradd2 : std_logic_vector (maddwidth -1 downto 0) is id2 (maddwidth -1 downto 0); -- operand address at pipe2
alias ind0 : std_logic is idbus(iwidth -5);
alias ind2 : std_logic is id2(iwidth -5);
alias ireg0 : std_logic is idbus(iwidth -8);
alias ireg2 : std_logic is id2(iwidth -8);
alias offset0 : std_logic_vector (iwidth-9 downto 0) is idbus(iwidth-9 downto 0);
alias offset2 : std_logic_vector (iwidth-9 downto 0) is id2(iwidth-9 downto 0);
alias opropcode0 : std_logic_vector (3 downto 0) is idbus(iwidth-5 downto iwidth-8); -- operate opcode at pipe2 alias iopr2 : std_logic_vector (7 downto 0) is id2 (7 downto 0); -- immediate operand at pipe2
alias opropcode2 : std_logic_vector (3 downto 0) is id2(iwidth-5 downto iwidth-8); -- operate opcode at pipe2 alias iopr2 : std_logic_vector (7 downto 0) is id2 (7 downto 0); -- immediate operand at pipe2
alias iopr2 : std_logic_vector (7 downto 0) is id2 (7 downto 0); -- immediate operand at pipe2
signal oprr : std_logic_vector (width -1 downto 0); -- operand register
signal idx : std_logic_vector (maddwidth -1 downto 0);
signal idy : std_logic_vector (maddwidth -1 downto 0);
signal idn0 : std_logic_vector (maddwidth -1 downto 0);
signal idn2 : std_logic_vector (maddwidth -1 downto 0);
signal maddpipe1 : std_logic_vector (maddwidth -1 downto 0);
signal maddpipe2 : std_logic_vector (maddwidth -1 downto 0);
signal maddpipe3 : std_logic_vector (maddwidth -1 downto 0);
signal idr : std_logic_vector (paddwidth -1 downto 0);
signal idt : std_logic_vector (paddwidth -1 downto 0);
signal nextpc : std_logic_vector (paddwidth -1 downto 0);
signal pcplus1 : std_logic_vector (paddwidth -1 downto 0);
signal zero : std_logic;
function rotcleft(v : std_logic_vector ) return std_logic_vector is
variable result : std_logic_vector(width downto 0);
begin
result(width downto 1) := v(width-1 downto 0);
result(0) := v(width);
return result;
end rotcleft;
function rotcright(v : std_logic_vector ) return std_logic_vector is
variable result : std_logic_vector(width downto 0);
begin
result(width -1 downto 0) := v(width downto 1);
result(width) := v(0);
return result;
end rotcright;
begin -- the CPU
idproc : process (clk) -- instruction data pipeline
begin
if clk'event and clk = '1' then
id1 <= idbus;
id2 <= id1;
if reset = '1' then
id1 <= x"0000"; -- fill pipeline with 0 (nop)
end if;
end if; -- if clk
end process idproc;
nextpcproc : process (clk, reset, pc, zero, nextpc, id2,
ind0, ind2,idr, idbus, opcode0,
opcode2, carrybit) -- next pc calculation - jump decode
begin
pcplus1 <= pc + '1';
iabus <= nextpc; -- program memory address from combinatorial
if reset = '1' then -- nextpc since blockram has built in addr register
nextpc <= (others => '0');
else
if (opcode0 = jmp) or (opcode0 = jsr) then
if ind0 = '1' then -- indirect
nextpc <= idr;
else -- direct
nextpc <= idbus(paddwidth -1 downto 0);
end if;
elsif
((opcode2 = jmpnz) and (zero = '0')) or
((opcode2 = jmpz) and (zero = '1')) or
((opcode2 = jmpnc) and (carrybit = '0')) or
((opcode2 = jmpc) and (carrybit = '1')) then
if ind2 = '1' then -- indirect
nextpc <= idr;
else -- direct
nextpc <= id2(paddwidth -1 downto 0);
end if;
else
nextpc <= pcplus1;
end if; -- opcode = jmp
end if; -- no reset
if clk'event and clk = '1' then
pc <= nextpc;
end if;
end process nextpcproc;
mraproc : process (idbus, idx, idy, mra, ind0,
ireg0,
offset0, opcode0, opradd0, clk) -- memory read address generation
begin
mradd <= mra;
case ireg0 is
when '0' => idn0 <= idx;
when '1' => idn0 <= idy;
when others => null;
end case;
-- mux
if ((opcode0 /= opr) and (ind0 = '0')) then
mra <= opradd0;
else
mra <= idn0 + (x"0"&offset0);
end if;
if clk'event and clk = '1' then
maddpipe3 <= maddpipe2;
maddpipe2 <= maddpipe1;
maddpipe1 <= mra;
if (opcode0 = lda) or (opcode0 = lor) or (opcode0 = lxor) or (opcode0 = land)
or (opcode0 = add) or (opcode0 = addc) or (opcode0 = sub) or (opcode0 = subc) then
mread <= '1';
else
mread <= '0';
end if;
end if;
end process mraproc;
mwaproc : process (maddpipe3) -- memory write address generation
begin
mwadd <= maddpipe3;
end process mwaproc;
oprrproc : process (clk) -- memory operand register -- could remove to
begin -- reduce pipelining depth but would impact I/O read
if clk'event and clk = '1' then -- access time --> not good for larger systems
oprr <= mibus;
end if;
end process oprrproc;
accumproc : process (clk, accum, carrybit) -- accumulator instruction decode - operate
begin
carryflg <= carrybit;
if accum = x"00" then
zero <= '1';
else
zero <= '0';
end if;
maskedcarry <= carrybit and WithCarry;
if clk'event and clk = '1' then
case opcode2 is -- memory reference first
when land => accum <= accum and oprr;
when lor => accum <= accum or oprr;
when lxor => accum <= accum xor oprr;
when lda => accum <= oprr;
when opr => -- operate
case opropcode2 is
when ldi => accum <= iopr2; -- load immediate byte
when rotcl => accumcar <= rotcleft(accumcar); -- rotate left through carry
when rotcr => accumcar <= rotcright(accumcar); -- rotate right through carry
when ldxl => accum <= idx(width-1 downto 0);
when ldyl => accum <= idy(width-1 downto 0);
when stxl => idx(width-1 downto 0) <= accum;
when styl => idy(width-1 downto 0) <= accum;
when ldxh => accum((maddwidth-width)-1 downto 0) <= idx(maddwidth-1 downto width);
accum(width-1 downto maddwidth-width) <= (others => '0');
when ldyh => accum((maddwidth-width)-1 downto 0) <= idy(maddwidth-1 downto width);
accum(width-1 downto maddwidth-width) <= (others => '0');
when stxh => idx(maddwidth-1 downto width) <= accum((maddwidth-width)-1 downto 0);
when styh => idy(maddwidth-1 downto width) <= accum((maddwidth-width)-1 downto 0);
when rtt => idt <= idr;
when ttr => idr <= idt;
when addix => idx <= maddpipe2;
when addiy => idy <= maddpipe2;
when others => null;
end case;
when others => null;
end case;
if Arith = "11" then
if Minus = '0' then
accumcar <= '0'&accum + oprr + maskedcarry; -- add/addc
else
accumcar <= '0'&accum - oprr - maskedcarry; -- sub/subc
end if;
end if;
if (opcode0 = jsr) then -- save return address -- note priority over ttr!
idr <= pcplus1;
end if;
-- if opcode0 = opr then -- this can be done at pipe 0 at the cost of 6 or so slices
-- if opropcode0 = addix then
-- idx <= mra;
-- end if;
-- if opropcode0 = addiy then
-- idy <= mra;
-- end if;
-- end if;
end if; -- clk
end process accumproc;
staproc : process (clk, accum) -- sta decode -- not much to do but enable mwrite
begin
mobus <= accum;
if clk'event and clk = '1' then
if opcode2 = sta then
mwrite <= '1';
else
mwrite <= '0';
end if;
end if;
end process staproc;
end Behavioral;
| lgpl-2.1 | 89694064b6e594cd359c91ccaefb537f | 0.645251 | 3.304678 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/maps/techbuf.vhd | 1 | 5,015 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: genclkbuf
-- File: genclkbuf.vhd
-- Author: Jiri Gaisler, Marko Isomaki - Gaisler Research
-- Description: Hard buffers with tech wrapper
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
entity techbuf is
generic(
buftype : integer range 0 to 6 := 0;
tech : integer range 0 to NTECH := inferred);
port( i : in std_ulogic; o : out std_ulogic);
end entity;
architecture rtl of techbuf is
component clkbuf_fusion is generic( buftype : integer range 0 to 3 := 0);
port( i : in std_ulogic; o : out std_ulogic);
end component;
component clkbuf_apa3 is generic( buftype : integer range 0 to 3 := 0);
port( i : in std_ulogic; o : out std_ulogic);
end component;
component clkbuf_igloo2 is generic( buftype : integer range 0 to 5 := 0);
port( i : in std_ulogic; o : out std_ulogic);
end component;
component clkbuf_apa3e is generic( buftype : integer range 0 to 3 := 0);
port( i : in std_ulogic; o : out std_ulogic);
end component;
component clkbuf_apa3l is generic( buftype : integer range 0 to 3 := 0);
port( i : in std_ulogic; o : out std_ulogic);
end component;
component clkbuf_actel is generic( buftype : integer range 0 to 6 := 0);
port( i : in std_ulogic; o : out std_ulogic);
end component;
component clkbuf_xilinx is generic( buftype : integer range 0 to 3 := 0);
port( i : in std_ulogic; o : out std_ulogic);
end component;
component clkbuf_ut025crh is generic( buftype : integer range 0 to 3 := 0);
port( i : in std_ulogic; o : out std_ulogic);
end component;
component clkbuf_ut130hbd is generic( buftype : integer range 0 to 3 := 0);
port( i : in std_ulogic; o : out std_ulogic);
end component;
component clkbuf_nextreme is generic( buftype : integer range 0 to 3 := 0);
port( i : in std_ulogic; o : out std_ulogic);
end component;
component clkbuf_n2x is generic(buftype : integer range 0 to 3 := 0);
port( i : in std_ulogic; o : out std_ulogic);
end component;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
gen : if has_techbuf(tech) = 0 generate
o <= i;
end generate;
fus : if (tech = actfus) generate
fus0 : clkbuf_fusion generic map (buftype => buftype) port map(i => i, o => o);
end generate;
pa3 : if (tech = apa3) generate
pa30 : clkbuf_apa3 generic map (buftype => buftype) port map(i => i, o => o);
end generate;
pa3e : if (tech = apa3e) generate
pae30 : clkbuf_apa3e generic map (buftype => buftype) port map(i => i, o => o);
end generate;
igl2 : if (tech = igloo2) or (tech = rtg4) generate
igl20 : clkbuf_igloo2 generic map (buftype => buftype) port map(i => i, o => o);
end generate;
pa3l : if (tech = apa3l) generate
pa3l0 : clkbuf_apa3l generic map (buftype => buftype) port map(i => i, o => o);
end generate;
axc : if (tech = axcel) or (tech = axdsp) generate
axc0 : clkbuf_actel generic map (buftype => buftype) port map(i => i, o => o);
end generate;
xil : if (is_unisim(tech) = 1) generate
xil0 : clkbuf_xilinx generic map (buftype => buftype) port map(i => i, o => o);
end generate;
ut : if (tech = ut25) generate
ut0 : clkbuf_ut025crh generic map (buftype => buftype) port map(i => i, o => o);
end generate;
ut13 : if (tech = ut130) generate
ut0 : clkbuf_ut130hbd generic map (buftype => buftype) port map(i => i, o => o);
end generate;
ut09 : if (tech = ut90) generate
ut0 : clkand_ut90nhbd port map(i => i, en => vcc, o => o, tsten => gnd);
end generate;
easic: if tech = easic90 generate
eas : clkbuf_nextreme generic map (buftype => buftype) port map(i => i, o => o);
end generate easic;
n2x : if tech = easic45 generate
n2x0 : clkbuf_n2x generic map (buftype => buftype) port map(i => i, o => o);
end generate;
end architecture;
| gpl-3.0 | 61550cd6ad8af21aeddf7a5628953877 | 0.634895 | 3.472992 | false | false | false | false |
hoglet67/CoPro6502 | test/TestJens.vhd | 1 | 2,771 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY TestJens IS
END TestJens;
ARCHITECTURE behavior OF TestJens IS
-- Clock period definitions
constant clk_period : time := 100 ns;
signal clk : std_logic := '0';
signal cpu_RSTn : std_logic := '0';
signal cpu_addr : std_logic_vector(15 downto 0);
signal cpu_din : std_logic_vector(7 downto 0);
signal cpu_dout : std_logic_vector(7 downto 0);
signal cpu_R_W_n : std_logic;
type ram_type is array (65535 downto 0) of std_logic_vector (7 downto 0);
signal RAM : ram_type := (65535 downto 0 => X"00");
BEGIN
uut: entity work.r65c02_tc PORT MAP(
clk_clk_i => clk,
d_i => cpu_din,
irq_n_i => '1',
nmi_n_i => '1',
rdy_i => '1',
rst_rst_n_i => cpu_RSTn,
so_n_i => '1',
a_o => cpu_addr,
d_o => cpu_dout,
rd_o => open,
sync_o => open,
wr_n_o => cpu_R_W_n,
wr_o => open
);
-- CPU clock on rising edge, so for simplicity lets clock RAM on falling ende
process (clk)
begin
if falling_edge(clk) then
--if cpu_R_W_n = '0' then
-- RAM(to_integer(unsigned(cpu_addr))) <= cpu_dout;
--end if;
cpu_din <= RAM(to_integer(unsigned(cpu_addr)));
end if;
end process;
-- Clock process definitions
process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
process
begin
wait until falling_edge(clk);
cpu_RSTn <= '0';
for i in 0 to 9 loop
wait until falling_edge(clk);
end loop;
-- Initialize RAM with test program
RAM(16#0000#) <= x"4C";
RAM(16#0001#) <= x"FE";
RAM(16#0002#) <= x"10";
RAM(16#0003#) <= x"4C";
RAM(16#0004#) <= x"03";
RAM(16#0005#) <= x"00";
RAM(16#1000#) <= x"10";
RAM(16#1003#) <= x"4C";
RAM(16#1004#) <= x"03";
RAM(16#1005#) <= x"10";
RAM(16#10FE#) <= x"4C";
RAM(16#10FF#) <= x"03";
RAM(16#1100#) <= x"00";
RAM(16#FFFE#) <= x"00";
RAM(16#FFFF#) <= x"00";
wait until falling_edge(clk);
cpu_RSTn <= '1';
for i in 0 to 999 loop
wait until falling_edge(clk);
end loop;
assert false
report "simulation ended"
severity failure;
end process;
END;
| gpl-3.0 | 90df5e985c2e3a5a5bbd862224f1a130 | 0.501263 | 3.395833 | false | false | false | false |
hoglet67/CoPro6502 | client/6809/102c/tuberom_6809.vhd | 1 | 86,728 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tuberom_6809 is
port (
CLK : in std_logic;
ADDR : in std_logic_vector(10 downto 0);
DATA : out std_logic_vector(7 downto 0)
);
end;
architecture RTL of tuberom_6809 is
signal rom_addr : std_logic_vector(11 downto 0);
begin
p_addr : process(ADDR)
begin
rom_addr <= (others => '0');
rom_addr(10 downto 0) <= ADDR;
end process;
p_rom : process
begin
wait until rising_edge(CLK);
DATA <= (others => '0');
case rom_addr is
when x"000" => DATA <= x"F8";
when x"001" => DATA <= x"2C";
when x"002" => DATA <= x"F8";
when x"003" => DATA <= x"71";
when x"004" => DATA <= x"FF";
when x"005" => DATA <= x"E0";
when x"006" => DATA <= x"F8";
when x"007" => DATA <= x"EA";
when x"008" => DATA <= x"F8";
when x"009" => DATA <= x"FE";
when x"00A" => DATA <= x"FF";
when x"00B" => DATA <= x"EE";
when x"00C" => DATA <= x"F8";
when x"00D" => DATA <= x"F3";
when x"00E" => DATA <= x"FF";
when x"00F" => DATA <= x"E7";
when x"010" => DATA <= x"F8";
when x"011" => DATA <= x"F0";
when x"012" => DATA <= x"F8";
when x"013" => DATA <= x"E9";
when x"014" => DATA <= x"20";
when x"015" => DATA <= x"5B";
when x"016" => DATA <= x"0D";
when x"017" => DATA <= x"36";
when x"018" => DATA <= x"38";
when x"019" => DATA <= x"30";
when x"01A" => DATA <= x"39";
when x"01B" => DATA <= x"20";
when x"01C" => DATA <= x"54";
when x"01D" => DATA <= x"55";
when x"01E" => DATA <= x"42";
when x"01F" => DATA <= x"45";
when x"020" => DATA <= x"20";
when x"021" => DATA <= x"36";
when x"022" => DATA <= x"34";
when x"023" => DATA <= x"4B";
when x"024" => DATA <= x"20";
when x"025" => DATA <= x"31";
when x"026" => DATA <= x"2E";
when x"027" => DATA <= x"30";
when x"028" => DATA <= x"32";
when x"029" => DATA <= x"63";
when x"02A" => DATA <= x"0D";
when x"02B" => DATA <= x"00";
when x"02C" => DATA <= x"1A";
when x"02D" => DATA <= x"50";
when x"02E" => DATA <= x"10";
when x"02F" => DATA <= x"CE";
when x"030" => DATA <= x"F8";
when x"031" => DATA <= x"00";
when x"032" => DATA <= x"1F";
when x"033" => DATA <= x"41";
when x"034" => DATA <= x"EC";
when x"035" => DATA <= x"84";
when x"036" => DATA <= x"ED";
when x"037" => DATA <= x"81";
when x"038" => DATA <= x"8C";
when x"039" => DATA <= x"FE";
when x"03A" => DATA <= x"C0";
when x"03B" => DATA <= x"26";
when x"03C" => DATA <= x"03";
when x"03D" => DATA <= x"8E";
when x"03E" => DATA <= x"FE";
when x"03F" => DATA <= x"F0";
when x"040" => DATA <= x"8C";
when x"041" => DATA <= x"FF";
when x"042" => DATA <= x"8C";
when x"043" => DATA <= x"26";
when x"044" => DATA <= x"03";
when x"045" => DATA <= x"8E";
when x"046" => DATA <= x"FF";
when x"047" => DATA <= x"94";
when x"048" => DATA <= x"8C";
when x"049" => DATA <= x"00";
when x"04A" => DATA <= x"00";
when x"04B" => DATA <= x"26";
when x"04C" => DATA <= x"E7";
when x"04D" => DATA <= x"B6";
when x"04E" => DATA <= x"FE";
when x"04F" => DATA <= x"E0";
when x"050" => DATA <= x"1A";
when x"051" => DATA <= x"50";
when x"052" => DATA <= x"10";
when x"053" => DATA <= x"CE";
when x"054" => DATA <= x"FF";
when x"055" => DATA <= x"80";
when x"056" => DATA <= x"8D";
when x"057" => DATA <= x"69";
when x"058" => DATA <= x"BE";
when x"059" => DATA <= x"FF";
when x"05A" => DATA <= x"90";
when x"05B" => DATA <= x"BF";
when x"05C" => DATA <= x"FF";
when x"05D" => DATA <= x"8E";
when x"05E" => DATA <= x"1C";
when x"05F" => DATA <= x"00";
when x"060" => DATA <= x"8E";
when x"061" => DATA <= x"F8";
when x"062" => DATA <= x"16";
when x"063" => DATA <= x"BD";
when x"064" => DATA <= x"F9";
when x"065" => DATA <= x"35";
when x"066" => DATA <= x"BD";
when x"067" => DATA <= x"FF";
when x"068" => DATA <= x"E7";
when x"069" => DATA <= x"4F";
when x"06A" => DATA <= x"BD";
when x"06B" => DATA <= x"FF";
when x"06C" => DATA <= x"EE";
when x"06D" => DATA <= x"4F";
when x"06E" => DATA <= x"BD";
when x"06F" => DATA <= x"FA";
when x"070" => DATA <= x"43";
when x"071" => DATA <= x"10";
when x"072" => DATA <= x"CE";
when x"073" => DATA <= x"FF";
when x"074" => DATA <= x"80";
when x"075" => DATA <= x"8D";
when x"076" => DATA <= x"4A";
when x"077" => DATA <= x"10";
when x"078" => DATA <= x"FE";
when x"079" => DATA <= x"FF";
when x"07A" => DATA <= x"8A";
when x"07B" => DATA <= x"8E";
when x"07C" => DATA <= x"FF";
when x"07D" => DATA <= x"B9";
when x"07E" => DATA <= x"BF";
when x"07F" => DATA <= x"FF";
when x"080" => DATA <= x"90";
when x"081" => DATA <= x"1C";
when x"082" => DATA <= x"00";
when x"083" => DATA <= x"8E";
when x"084" => DATA <= x"F8";
when x"085" => DATA <= x"96";
when x"086" => DATA <= x"BD";
when x"087" => DATA <= x"F9";
when x"088" => DATA <= x"35";
when x"089" => DATA <= x"BD";
when x"08A" => DATA <= x"FF";
when x"08B" => DATA <= x"F1";
when x"08C" => DATA <= x"25";
when x"08D" => DATA <= x"14";
when x"08E" => DATA <= x"8E";
when x"08F" => DATA <= x"FF";
when x"090" => DATA <= x"00";
when x"091" => DATA <= x"BD";
when x"092" => DATA <= x"FF";
when x"093" => DATA <= x"F7";
when x"094" => DATA <= x"20";
when x"095" => DATA <= x"ED";
when x"096" => DATA <= x"36";
when x"097" => DATA <= x"38";
when x"098" => DATA <= x"30";
when x"099" => DATA <= x"39";
when x"09A" => DATA <= x"3E";
when x"09B" => DATA <= x"2A";
when x"09C" => DATA <= x"00";
when x"09D" => DATA <= x"FF";
when x"09E" => DATA <= x"00";
when x"09F" => DATA <= x"6F";
when x"0A0" => DATA <= x"20";
when x"0A1" => DATA <= x"FF";
when x"0A2" => DATA <= x"86";
when x"0A3" => DATA <= x"7E";
when x"0A4" => DATA <= x"BD";
when x"0A5" => DATA <= x"FF";
when x"0A6" => DATA <= x"F4";
when x"0A7" => DATA <= x"3F";
when x"0A8" => DATA <= x"11";
when x"0A9" => DATA <= x"45";
when x"0AA" => DATA <= x"73";
when x"0AB" => DATA <= x"63";
when x"0AC" => DATA <= x"61";
when x"0AD" => DATA <= x"70";
when x"0AE" => DATA <= x"65";
when x"0AF" => DATA <= x"00";
when x"0B0" => DATA <= x"10";
when x"0B1" => DATA <= x"FE";
when x"0B2" => DATA <= x"FF";
when x"0B3" => DATA <= x"8A";
when x"0B4" => DATA <= x"BD";
when x"0B5" => DATA <= x"FF";
when x"0B6" => DATA <= x"E7";
when x"0B7" => DATA <= x"A6";
when x"0B8" => DATA <= x"80";
when x"0B9" => DATA <= x"BD";
when x"0BA" => DATA <= x"F9";
when x"0BB" => DATA <= x"35";
when x"0BC" => DATA <= x"BD";
when x"0BD" => DATA <= x"FF";
when x"0BE" => DATA <= x"E7";
when x"0BF" => DATA <= x"20";
when x"0C0" => DATA <= x"C2";
when x"0C1" => DATA <= x"CC";
when x"0C2" => DATA <= x"00";
when x"0C3" => DATA <= x"00";
when x"0C4" => DATA <= x"FD";
when x"0C5" => DATA <= x"FF";
when x"0C6" => DATA <= x"88";
when x"0C7" => DATA <= x"CC";
when x"0C8" => DATA <= x"F8";
when x"0C9" => DATA <= x"00";
when x"0CA" => DATA <= x"FD";
when x"0CB" => DATA <= x"FF";
when x"0CC" => DATA <= x"8A";
when x"0CD" => DATA <= x"CC";
when x"0CE" => DATA <= x"F8";
when x"0CF" => DATA <= x"B0";
when x"0D0" => DATA <= x"FD";
when x"0D1" => DATA <= x"FF";
when x"0D2" => DATA <= x"FA";
when x"0D3" => DATA <= x"4D";
when x"0D4" => DATA <= x"2B";
when x"0D5" => DATA <= x"06";
when x"0D6" => DATA <= x"FC";
when x"0D7" => DATA <= x"FF";
when x"0D8" => DATA <= x"92";
when x"0D9" => DATA <= x"FD";
when x"0DA" => DATA <= x"FF";
when x"0DB" => DATA <= x"90";
when x"0DC" => DATA <= x"CC";
when x"0DD" => DATA <= x"FE";
when x"0DE" => DATA <= x"2E";
when x"0DF" => DATA <= x"FD";
when x"0E0" => DATA <= x"FE";
when x"0E1" => DATA <= x"FA";
when x"0E2" => DATA <= x"8E";
when x"0E3" => DATA <= x"FF";
when x"0E4" => DATA <= x"FA";
when x"0E5" => DATA <= x"10";
when x"0E6" => DATA <= x"8E";
when x"0E7" => DATA <= x"FF";
when x"0E8" => DATA <= x"80";
when x"0E9" => DATA <= x"39";
when x"0EA" => DATA <= x"BD";
when x"0EB" => DATA <= x"FF";
when x"0EC" => DATA <= x"E0";
when x"0ED" => DATA <= x"7E";
when x"0EE" => DATA <= x"FF";
when x"0EF" => DATA <= x"EE";
when x"0F0" => DATA <= x"BD";
when x"0F1" => DATA <= x"FF";
when x"0F2" => DATA <= x"E7";
when x"0F3" => DATA <= x"A6";
when x"0F4" => DATA <= x"80";
when x"0F5" => DATA <= x"81";
when x"0F6" => DATA <= x"04";
when x"0F7" => DATA <= x"27";
when x"0F8" => DATA <= x"F0";
when x"0F9" => DATA <= x"BD";
when x"0FA" => DATA <= x"FF";
when x"0FB" => DATA <= x"EE";
when x"0FC" => DATA <= x"20";
when x"0FD" => DATA <= x"F5";
when x"0FE" => DATA <= x"34";
when x"0FF" => DATA <= x"32";
when x"100" => DATA <= x"86";
when x"101" => DATA <= x"80";
when x"102" => DATA <= x"8E";
when x"103" => DATA <= x"FF";
when x"104" => DATA <= x"FF";
when x"105" => DATA <= x"1F";
when x"106" => DATA <= x"12";
when x"107" => DATA <= x"BD";
when x"108" => DATA <= x"FF";
when x"109" => DATA <= x"F4";
when x"10A" => DATA <= x"8C";
when x"10B" => DATA <= x"00";
when x"10C" => DATA <= x"00";
when x"10D" => DATA <= x"35";
when x"10E" => DATA <= x"B2";
when x"10F" => DATA <= x"1F";
when x"110" => DATA <= x"10";
when x"111" => DATA <= x"8D";
when x"112" => DATA <= x"04";
when x"113" => DATA <= x"1F";
when x"114" => DATA <= x"10";
when x"115" => DATA <= x"1F";
when x"116" => DATA <= x"98";
when x"117" => DATA <= x"34";
when x"118" => DATA <= x"02";
when x"119" => DATA <= x"44";
when x"11A" => DATA <= x"44";
when x"11B" => DATA <= x"44";
when x"11C" => DATA <= x"44";
when x"11D" => DATA <= x"8D";
when x"11E" => DATA <= x"02";
when x"11F" => DATA <= x"35";
when x"120" => DATA <= x"02";
when x"121" => DATA <= x"84";
when x"122" => DATA <= x"0F";
when x"123" => DATA <= x"81";
when x"124" => DATA <= x"0A";
when x"125" => DATA <= x"25";
when x"126" => DATA <= x"02";
when x"127" => DATA <= x"8B";
when x"128" => DATA <= x"07";
when x"129" => DATA <= x"8B";
when x"12A" => DATA <= x"30";
when x"12B" => DATA <= x"7E";
when x"12C" => DATA <= x"FF";
when x"12D" => DATA <= x"EE";
when x"12E" => DATA <= x"35";
when x"12F" => DATA <= x"10";
when x"130" => DATA <= x"8D";
when x"131" => DATA <= x"03";
when x"132" => DATA <= x"34";
when x"133" => DATA <= x"10";
when x"134" => DATA <= x"39";
when x"135" => DATA <= x"A6";
when x"136" => DATA <= x"80";
when x"137" => DATA <= x"27";
when x"138" => DATA <= x"FB";
when x"139" => DATA <= x"BD";
when x"13A" => DATA <= x"FF";
when x"13B" => DATA <= x"E3";
when x"13C" => DATA <= x"20";
when x"13D" => DATA <= x"F7";
when x"13E" => DATA <= x"10";
when x"13F" => DATA <= x"8E";
when x"140" => DATA <= x"00";
when x"141" => DATA <= x"00";
when x"142" => DATA <= x"A6";
when x"143" => DATA <= x"80";
when x"144" => DATA <= x"81";
when x"145" => DATA <= x"30";
when x"146" => DATA <= x"25";
when x"147" => DATA <= x"33";
when x"148" => DATA <= x"81";
when x"149" => DATA <= x"3A";
when x"14A" => DATA <= x"25";
when x"14B" => DATA <= x"0A";
when x"14C" => DATA <= x"84";
when x"14D" => DATA <= x"DF";
when x"14E" => DATA <= x"80";
when x"14F" => DATA <= x"07";
when x"150" => DATA <= x"25";
when x"151" => DATA <= x"29";
when x"152" => DATA <= x"81";
when x"153" => DATA <= x"40";
when x"154" => DATA <= x"24";
when x"155" => DATA <= x"25";
when x"156" => DATA <= x"84";
when x"157" => DATA <= x"0F";
when x"158" => DATA <= x"1E";
when x"159" => DATA <= x"02";
when x"15A" => DATA <= x"58";
when x"15B" => DATA <= x"49";
when x"15C" => DATA <= x"58";
when x"15D" => DATA <= x"49";
when x"15E" => DATA <= x"58";
when x"15F" => DATA <= x"49";
when x"160" => DATA <= x"58";
when x"161" => DATA <= x"49";
when x"162" => DATA <= x"1E";
when x"163" => DATA <= x"12";
when x"164" => DATA <= x"1E";
when x"165" => DATA <= x"01";
when x"166" => DATA <= x"1E";
when x"167" => DATA <= x"89";
when x"168" => DATA <= x"3A";
when x"169" => DATA <= x"1E";
when x"16A" => DATA <= x"12";
when x"16B" => DATA <= x"20";
when x"16C" => DATA <= x"D5";
when x"16D" => DATA <= x"A6";
when x"16E" => DATA <= x"80";
when x"16F" => DATA <= x"81";
when x"170" => DATA <= x"21";
when x"171" => DATA <= x"24";
when x"172" => DATA <= x"FA";
when x"173" => DATA <= x"30";
when x"174" => DATA <= x"1F";
when x"175" => DATA <= x"A6";
when x"176" => DATA <= x"80";
when x"177" => DATA <= x"81";
when x"178" => DATA <= x"20";
when x"179" => DATA <= x"27";
when x"17A" => DATA <= x"FA";
when x"17B" => DATA <= x"30";
when x"17C" => DATA <= x"1F";
when x"17D" => DATA <= x"81";
when x"17E" => DATA <= x"21";
when x"17F" => DATA <= x"39";
when x"180" => DATA <= x"34";
when x"181" => DATA <= x"7C";
when x"182" => DATA <= x"33";
when x"183" => DATA <= x"78";
when x"184" => DATA <= x"11";
when x"185" => DATA <= x"8C";
when x"186" => DATA <= x"F8";
when x"187" => DATA <= x"00";
when x"188" => DATA <= x"24";
when x"189" => DATA <= x"04";
when x"18A" => DATA <= x"10";
when x"18B" => DATA <= x"CE";
when x"18C" => DATA <= x"FF";
when x"18D" => DATA <= x"80";
when x"18E" => DATA <= x"34";
when x"18F" => DATA <= x"40";
when x"190" => DATA <= x"8D";
when x"191" => DATA <= x"13";
when x"192" => DATA <= x"35";
when x"193" => DATA <= x"40";
when x"194" => DATA <= x"32";
when x"195" => DATA <= x"48";
when x"196" => DATA <= x"35";
when x"197" => DATA <= x"FC";
when x"198" => DATA <= x"48";
when x"199" => DATA <= x"45";
when x"19A" => DATA <= x"4C";
when x"19B" => DATA <= x"50";
when x"19C" => DATA <= x"80";
when x"19D" => DATA <= x"47";
when x"19E" => DATA <= x"4F";
when x"19F" => DATA <= x"81";
when x"1A0" => DATA <= x"52";
when x"1A1" => DATA <= x"55";
when x"1A2" => DATA <= x"4E";
when x"1A3" => DATA <= x"82";
when x"1A4" => DATA <= x"00";
when x"1A5" => DATA <= x"8D";
when x"1A6" => DATA <= x"CE";
when x"1A7" => DATA <= x"A6";
when x"1A8" => DATA <= x"80";
when x"1A9" => DATA <= x"81";
when x"1AA" => DATA <= x"2A";
when x"1AB" => DATA <= x"27";
when x"1AC" => DATA <= x"F8";
when x"1AD" => DATA <= x"30";
when x"1AE" => DATA <= x"1F";
when x"1AF" => DATA <= x"34";
when x"1B0" => DATA <= x"10";
when x"1B1" => DATA <= x"8D";
when x"1B2" => DATA <= x"BA";
when x"1B3" => DATA <= x"BF";
when x"1B4" => DATA <= x"FF";
when x"1B5" => DATA <= x"86";
when x"1B6" => DATA <= x"10";
when x"1B7" => DATA <= x"8E";
when x"1B8" => DATA <= x"F9";
when x"1B9" => DATA <= x"98";
when x"1BA" => DATA <= x"AE";
when x"1BB" => DATA <= x"E4";
when x"1BC" => DATA <= x"A6";
when x"1BD" => DATA <= x"84";
when x"1BE" => DATA <= x"81";
when x"1BF" => DATA <= x"41";
when x"1C0" => DATA <= x"25";
when x"1C1" => DATA <= x"75";
when x"1C2" => DATA <= x"A6";
when x"1C3" => DATA <= x"80";
when x"1C4" => DATA <= x"84";
when x"1C5" => DATA <= x"DF";
when x"1C6" => DATA <= x"A1";
when x"1C7" => DATA <= x"A0";
when x"1C8" => DATA <= x"27";
when x"1C9" => DATA <= x"F8";
when x"1CA" => DATA <= x"A6";
when x"1CB" => DATA <= x"A2";
when x"1CC" => DATA <= x"2B";
when x"1CD" => DATA <= x"16";
when x"1CE" => DATA <= x"A6";
when x"1CF" => DATA <= x"1F";
when x"1D0" => DATA <= x"81";
when x"1D1" => DATA <= x"2E";
when x"1D2" => DATA <= x"27";
when x"1D3" => DATA <= x"0A";
when x"1D4" => DATA <= x"A6";
when x"1D5" => DATA <= x"A0";
when x"1D6" => DATA <= x"2A";
when x"1D7" => DATA <= x"FC";
when x"1D8" => DATA <= x"A6";
when x"1D9" => DATA <= x"A4";
when x"1DA" => DATA <= x"26";
when x"1DB" => DATA <= x"DE";
when x"1DC" => DATA <= x"20";
when x"1DD" => DATA <= x"59";
when x"1DE" => DATA <= x"A6";
when x"1DF" => DATA <= x"A0";
when x"1E0" => DATA <= x"2A";
when x"1E1" => DATA <= x"FC";
when x"1E2" => DATA <= x"20";
when x"1E3" => DATA <= x"06";
when x"1E4" => DATA <= x"E6";
when x"1E5" => DATA <= x"82";
when x"1E6" => DATA <= x"C1";
when x"1E7" => DATA <= x"21";
when x"1E8" => DATA <= x"24";
when x"1E9" => DATA <= x"4D";
when x"1EA" => DATA <= x"81";
when x"1EB" => DATA <= x"80";
when x"1EC" => DATA <= x"27";
when x"1ED" => DATA <= x"31";
when x"1EE" => DATA <= x"81";
when x"1EF" => DATA <= x"82";
when x"1F0" => DATA <= x"27";
when x"1F1" => DATA <= x"3C";
when x"1F2" => DATA <= x"8D";
when x"1F3" => DATA <= x"81";
when x"1F4" => DATA <= x"10";
when x"1F5" => DATA <= x"BE";
when x"1F6" => DATA <= x"FF";
when x"1F7" => DATA <= x"90";
when x"1F8" => DATA <= x"81";
when x"1F9" => DATA <= x"0D";
when x"1FA" => DATA <= x"27";
when x"1FB" => DATA <= x"18";
when x"1FC" => DATA <= x"81";
when x"1FD" => DATA <= x"3B";
when x"1FE" => DATA <= x"27";
when x"1FF" => DATA <= x"12";
when x"200" => DATA <= x"BD";
when x"201" => DATA <= x"FF";
when x"202" => DATA <= x"A1";
when x"203" => DATA <= x"24";
when x"204" => DATA <= x"32";
when x"205" => DATA <= x"BD";
when x"206" => DATA <= x"F9";
when x"207" => DATA <= x"75";
when x"208" => DATA <= x"81";
when x"209" => DATA <= x"3B";
when x"20A" => DATA <= x"27";
when x"20B" => DATA <= x"06";
when x"20C" => DATA <= x"81";
when x"20D" => DATA <= x"0D";
when x"20E" => DATA <= x"26";
when x"20F" => DATA <= x"27";
when x"210" => DATA <= x"30";
when x"211" => DATA <= x"1F";
when x"212" => DATA <= x"30";
when x"213" => DATA <= x"01";
when x"214" => DATA <= x"BF";
when x"215" => DATA <= x"FF";
when x"216" => DATA <= x"86";
when x"217" => DATA <= x"35";
when x"218" => DATA <= x"10";
when x"219" => DATA <= x"1F";
when x"21A" => DATA <= x"21";
when x"21B" => DATA <= x"1A";
when x"21C" => DATA <= x"01";
when x"21D" => DATA <= x"20";
when x"21E" => DATA <= x"2C";
when x"21F" => DATA <= x"BD";
when x"220" => DATA <= x"F9";
when x"221" => DATA <= x"75";
when x"222" => DATA <= x"25";
when x"223" => DATA <= x"04";
when x"224" => DATA <= x"81";
when x"225" => DATA <= x"2E";
when x"226" => DATA <= x"26";
when x"227" => DATA <= x"0F";
when x"228" => DATA <= x"8E";
when x"229" => DATA <= x"F8";
when x"22A" => DATA <= x"16";
when x"22B" => DATA <= x"BD";
when x"22C" => DATA <= x"F9";
when x"22D" => DATA <= x"35";
when x"22E" => DATA <= x"BD";
when x"22F" => DATA <= x"F9";
when x"230" => DATA <= x"75";
when x"231" => DATA <= x"BD";
when x"232" => DATA <= x"F9";
when x"233" => DATA <= x"6D";
when x"234" => DATA <= x"BF";
when x"235" => DATA <= x"FF";
when x"236" => DATA <= x"86";
when x"237" => DATA <= x"35";
when x"238" => DATA <= x"10";
when x"239" => DATA <= x"86";
when x"23A" => DATA <= x"02";
when x"23B" => DATA <= x"BD";
when x"23C" => DATA <= x"FC";
when x"23D" => DATA <= x"F5";
when x"23E" => DATA <= x"BD";
when x"23F" => DATA <= x"FC";
when x"240" => DATA <= x"B9";
when x"241" => DATA <= x"1A";
when x"242" => DATA <= x"01";
when x"243" => DATA <= x"BD";
when x"244" => DATA <= x"FA";
when x"245" => DATA <= x"CB";
when x"246" => DATA <= x"2A";
when x"247" => DATA <= x"53";
when x"248" => DATA <= x"BE";
when x"249" => DATA <= x"FF";
when x"24A" => DATA <= x"8E";
when x"24B" => DATA <= x"34";
when x"24C" => DATA <= x"01";
when x"24D" => DATA <= x"1F";
when x"24E" => DATA <= x"12";
when x"24F" => DATA <= x"E6";
when x"250" => DATA <= x"07";
when x"251" => DATA <= x"3A";
when x"252" => DATA <= x"CE";
when x"253" => DATA <= x"FA";
when x"254" => DATA <= x"AA";
when x"255" => DATA <= x"C6";
when x"256" => DATA <= x"04";
when x"257" => DATA <= x"A6";
when x"258" => DATA <= x"80";
when x"259" => DATA <= x"A1";
when x"25A" => DATA <= x"C2";
when x"25B" => DATA <= x"26";
when x"25C" => DATA <= x"3F";
when x"25D" => DATA <= x"5A";
when x"25E" => DATA <= x"26";
when x"25F" => DATA <= x"F7";
when x"260" => DATA <= x"A6";
when x"261" => DATA <= x"26";
when x"262" => DATA <= x"48";
when x"263" => DATA <= x"2A";
when x"264" => DATA <= x"45";
when x"265" => DATA <= x"84";
when x"266" => DATA <= x"1E";
when x"267" => DATA <= x"81";
when x"268" => DATA <= x"06";
when x"269" => DATA <= x"26";
when x"26A" => DATA <= x"3F";
when x"26B" => DATA <= x"30";
when x"26C" => DATA <= x"1C";
when x"26D" => DATA <= x"BF";
when x"26E" => DATA <= x"FF";
when x"26F" => DATA <= x"82";
when x"270" => DATA <= x"FE";
when x"271" => DATA <= x"FF";
when x"272" => DATA <= x"90";
when x"273" => DATA <= x"BE";
when x"274" => DATA <= x"FF";
when x"275" => DATA <= x"8A";
when x"276" => DATA <= x"35";
when x"277" => DATA <= x"02";
when x"278" => DATA <= x"34";
when x"279" => DATA <= x"50";
when x"27A" => DATA <= x"10";
when x"27B" => DATA <= x"8C";
when x"27C" => DATA <= x"80";
when x"27D" => DATA <= x"00";
when x"27E" => DATA <= x"25";
when x"27F" => DATA <= x"04";
when x"280" => DATA <= x"10";
when x"281" => DATA <= x"BF";
when x"282" => DATA <= x"FF";
when x"283" => DATA <= x"8A";
when x"284" => DATA <= x"10";
when x"285" => DATA <= x"BF";
when x"286" => DATA <= x"FF";
when x"287" => DATA <= x"92";
when x"288" => DATA <= x"BE";
when x"289" => DATA <= x"FF";
when x"28A" => DATA <= x"86";
when x"28B" => DATA <= x"EE";
when x"28C" => DATA <= x"66";
when x"28D" => DATA <= x"46";
when x"28E" => DATA <= x"86";
when x"28F" => DATA <= x"01";
when x"290" => DATA <= x"AD";
when x"291" => DATA <= x"A4";
when x"292" => DATA <= x"35";
when x"293" => DATA <= x"60";
when x"294" => DATA <= x"10";
when x"295" => DATA <= x"BF";
when x"296" => DATA <= x"FF";
when x"297" => DATA <= x"8A";
when x"298" => DATA <= x"FF";
when x"299" => DATA <= x"FF";
when x"29A" => DATA <= x"90";
when x"29B" => DATA <= x"39";
when x"29C" => DATA <= x"BE";
when x"29D" => DATA <= x"FF";
when x"29E" => DATA <= x"86";
when x"29F" => DATA <= x"EE";
when x"2A0" => DATA <= x"63";
when x"2A1" => DATA <= x"4F";
when x"2A2" => DATA <= x"35";
when x"2A3" => DATA <= x"01";
when x"2A4" => DATA <= x"6E";
when x"2A5" => DATA <= x"A4";
when x"2A6" => DATA <= x"29";
when x"2A7" => DATA <= x"43";
when x"2A8" => DATA <= x"28";
when x"2A9" => DATA <= x"00";
when x"2AA" => DATA <= x"35";
when x"2AB" => DATA <= x"01";
when x"2AC" => DATA <= x"10";
when x"2AD" => DATA <= x"24";
when x"2AE" => DATA <= x"05";
when x"2AF" => DATA <= x"09";
when x"2B0" => DATA <= x"BD";
when x"2B1" => DATA <= x"F8";
when x"2B2" => DATA <= x"CD";
when x"2B3" => DATA <= x"3F";
when x"2B4" => DATA <= x"F9";
when x"2B5" => DATA <= x"4E";
when x"2B6" => DATA <= x"6F";
when x"2B7" => DATA <= x"74";
when x"2B8" => DATA <= x"20";
when x"2B9" => DATA <= x"36";
when x"2BA" => DATA <= x"38";
when x"2BB" => DATA <= x"30";
when x"2BC" => DATA <= x"39";
when x"2BD" => DATA <= x"20";
when x"2BE" => DATA <= x"63";
when x"2BF" => DATA <= x"6F";
when x"2C0" => DATA <= x"64";
when x"2C1" => DATA <= x"65";
when x"2C2" => DATA <= x"00";
when x"2C3" => DATA <= x"4F";
when x"2C4" => DATA <= x"BD";
when x"2C5" => DATA <= x"FC";
when x"2C6" => DATA <= x"F5";
when x"2C7" => DATA <= x"8D";
when x"2C8" => DATA <= x"02";
when x"2C9" => DATA <= x"8B";
when x"2CA" => DATA <= x"80";
when x"2CB" => DATA <= x"B6";
when x"2CC" => DATA <= x"FE";
when x"2CD" => DATA <= x"E2";
when x"2CE" => DATA <= x"2A";
when x"2CF" => DATA <= x"FB";
when x"2D0" => DATA <= x"B6";
when x"2D1" => DATA <= x"FE";
when x"2D2" => DATA <= x"E3";
when x"2D3" => DATA <= x"39";
when x"2D4" => DATA <= x"34";
when x"2D5" => DATA <= x"06";
when x"2D6" => DATA <= x"4D";
when x"2D7" => DATA <= x"2B";
when x"2D8" => DATA <= x"23";
when x"2D9" => DATA <= x"86";
when x"2DA" => DATA <= x"04";
when x"2DB" => DATA <= x"BD";
when x"2DC" => DATA <= x"FC";
when x"2DD" => DATA <= x"F5";
when x"2DE" => DATA <= x"1F";
when x"2DF" => DATA <= x"10";
when x"2E0" => DATA <= x"BD";
when x"2E1" => DATA <= x"FC";
when x"2E2" => DATA <= x"F3";
when x"2E3" => DATA <= x"35";
when x"2E4" => DATA <= x"06";
when x"2E5" => DATA <= x"34";
when x"2E6" => DATA <= x"06";
when x"2E7" => DATA <= x"BD";
when x"2E8" => DATA <= x"FC";
when x"2E9" => DATA <= x"F5";
when x"2EA" => DATA <= x"8D";
when x"2EB" => DATA <= x"DF";
when x"2EC" => DATA <= x"1F";
when x"2ED" => DATA <= x"89";
when x"2EE" => DATA <= x"4F";
when x"2EF" => DATA <= x"1F";
when x"2F0" => DATA <= x"01";
when x"2F1" => DATA <= x"35";
when x"2F2" => DATA <= x"86";
when x"2F3" => DATA <= x"8E";
when x"2F4" => DATA <= x"F8";
when x"2F5" => DATA <= x"16";
when x"2F6" => DATA <= x"BF";
when x"2F7" => DATA <= x"FF";
when x"2F8" => DATA <= x"86";
when x"2F9" => DATA <= x"7E";
when x"2FA" => DATA <= x"FA";
when x"2FB" => DATA <= x"41";
when x"2FC" => DATA <= x"81";
when x"2FD" => DATA <= x"82";
when x"2FE" => DATA <= x"27";
when x"2FF" => DATA <= x"39";
when x"300" => DATA <= x"81";
when x"301" => DATA <= x"83";
when x"302" => DATA <= x"27";
when x"303" => DATA <= x"37";
when x"304" => DATA <= x"81";
when x"305" => DATA <= x"84";
when x"306" => DATA <= x"27";
when x"307" => DATA <= x"33";
when x"308" => DATA <= x"86";
when x"309" => DATA <= x"06";
when x"30A" => DATA <= x"BD";
when x"30B" => DATA <= x"FC";
when x"30C" => DATA <= x"F5";
when x"30D" => DATA <= x"1F";
when x"30E" => DATA <= x"10";
when x"30F" => DATA <= x"BD";
when x"310" => DATA <= x"FC";
when x"311" => DATA <= x"F3";
when x"312" => DATA <= x"BD";
when x"313" => DATA <= x"FC";
when x"314" => DATA <= x"F1";
when x"315" => DATA <= x"35";
when x"316" => DATA <= x"06";
when x"317" => DATA <= x"BD";
when x"318" => DATA <= x"FC";
when x"319" => DATA <= x"F5";
when x"31A" => DATA <= x"81";
when x"31B" => DATA <= x"9D";
when x"31C" => DATA <= x"27";
when x"31D" => DATA <= x"B5";
when x"31E" => DATA <= x"81";
when x"31F" => DATA <= x"8E";
when x"320" => DATA <= x"27";
when x"321" => DATA <= x"D1";
when x"322" => DATA <= x"34";
when x"323" => DATA <= x"06";
when x"324" => DATA <= x"8D";
when x"325" => DATA <= x"A5";
when x"326" => DATA <= x"8B";
when x"327" => DATA <= x"80";
when x"328" => DATA <= x"34";
when x"329" => DATA <= x"01";
when x"32A" => DATA <= x"8D";
when x"32B" => DATA <= x"9F";
when x"32C" => DATA <= x"1F";
when x"32D" => DATA <= x"89";
when x"32E" => DATA <= x"4F";
when x"32F" => DATA <= x"1F";
when x"330" => DATA <= x"02";
when x"331" => DATA <= x"8D";
when x"332" => DATA <= x"98";
when x"333" => DATA <= x"1E";
when x"334" => DATA <= x"89";
when x"335" => DATA <= x"1F";
when x"336" => DATA <= x"01";
when x"337" => DATA <= x"35";
when x"338" => DATA <= x"87";
when x"339" => DATA <= x"86";
when x"33A" => DATA <= x"85";
when x"33B" => DATA <= x"48";
when x"33C" => DATA <= x"8E";
when x"33D" => DATA <= x"FF";
when x"33E" => DATA <= x"82";
when x"33F" => DATA <= x"EC";
when x"340" => DATA <= x"86";
when x"341" => DATA <= x"1F";
when x"342" => DATA <= x"01";
when x"343" => DATA <= x"1F";
when x"344" => DATA <= x"89";
when x"345" => DATA <= x"4F";
when x"346" => DATA <= x"1F";
when x"347" => DATA <= x"02";
when x"348" => DATA <= x"35";
when x"349" => DATA <= x"86";
when x"34A" => DATA <= x"4D";
when x"34B" => DATA <= x"27";
when x"34C" => DATA <= x"5C";
when x"34D" => DATA <= x"34";
when x"34E" => DATA <= x"26";
when x"34F" => DATA <= x"34";
when x"350" => DATA <= x"10";
when x"351" => DATA <= x"1F";
when x"352" => DATA <= x"89";
when x"353" => DATA <= x"86";
when x"354" => DATA <= x"08";
when x"355" => DATA <= x"BD";
when x"356" => DATA <= x"FC";
when x"357" => DATA <= x"F5";
when x"358" => DATA <= x"BD";
when x"359" => DATA <= x"FC";
when x"35A" => DATA <= x"F3";
when x"35B" => DATA <= x"5D";
when x"35C" => DATA <= x"2A";
when x"35D" => DATA <= x"04";
when x"35E" => DATA <= x"A6";
when x"35F" => DATA <= x"84";
when x"360" => DATA <= x"20";
when x"361" => DATA <= x"0C";
when x"362" => DATA <= x"86";
when x"363" => DATA <= x"10";
when x"364" => DATA <= x"C1";
when x"365" => DATA <= x"15";
when x"366" => DATA <= x"24";
when x"367" => DATA <= x"06";
when x"368" => DATA <= x"8E";
when x"369" => DATA <= x"FB";
when x"36A" => DATA <= x"D8";
when x"36B" => DATA <= x"3A";
when x"36C" => DATA <= x"A6";
when x"36D" => DATA <= x"84";
when x"36E" => DATA <= x"35";
when x"36F" => DATA <= x"10";
when x"370" => DATA <= x"BD";
when x"371" => DATA <= x"FC";
when x"372" => DATA <= x"F5";
when x"373" => DATA <= x"1F";
when x"374" => DATA <= x"02";
when x"375" => DATA <= x"1E";
when x"376" => DATA <= x"89";
when x"377" => DATA <= x"4F";
when x"378" => DATA <= x"1E";
when x"379" => DATA <= x"02";
when x"37A" => DATA <= x"4A";
when x"37B" => DATA <= x"2B";
when x"37C" => DATA <= x"03";
when x"37D" => DATA <= x"BD";
when x"37E" => DATA <= x"FC";
when x"37F" => DATA <= x"C2";
when x"380" => DATA <= x"34";
when x"381" => DATA <= x"10";
when x"382" => DATA <= x"5D";
when x"383" => DATA <= x"2A";
when x"384" => DATA <= x"04";
when x"385" => DATA <= x"A6";
when x"386" => DATA <= x"01";
when x"387" => DATA <= x"20";
when x"388" => DATA <= x"0C";
when x"389" => DATA <= x"86";
when x"38A" => DATA <= x"10";
when x"38B" => DATA <= x"C1";
when x"38C" => DATA <= x"15";
when x"38D" => DATA <= x"24";
when x"38E" => DATA <= x"06";
when x"38F" => DATA <= x"8E";
when x"390" => DATA <= x"FB";
when x"391" => DATA <= x"EC";
when x"392" => DATA <= x"3A";
when x"393" => DATA <= x"A6";
when x"394" => DATA <= x"84";
when x"395" => DATA <= x"35";
when x"396" => DATA <= x"10";
when x"397" => DATA <= x"BD";
when x"398" => DATA <= x"FC";
when x"399" => DATA <= x"F5";
when x"39A" => DATA <= x"1F";
when x"39B" => DATA <= x"02";
when x"39C" => DATA <= x"1E";
when x"39D" => DATA <= x"89";
when x"39E" => DATA <= x"4F";
when x"39F" => DATA <= x"1E";
when x"3A0" => DATA <= x"02";
when x"3A1" => DATA <= x"4A";
when x"3A2" => DATA <= x"2B";
when x"3A3" => DATA <= x"03";
when x"3A4" => DATA <= x"BD";
when x"3A5" => DATA <= x"FC";
when x"3A6" => DATA <= x"D2";
when x"3A7" => DATA <= x"35";
when x"3A8" => DATA <= x"A6";
when x"3A9" => DATA <= x"86";
when x"3AA" => DATA <= x"0A";
when x"3AB" => DATA <= x"BD";
when x"3AC" => DATA <= x"FC";
when x"3AD" => DATA <= x"F5";
when x"3AE" => DATA <= x"30";
when x"3AF" => DATA <= x"02";
when x"3B0" => DATA <= x"10";
when x"3B1" => DATA <= x"8E";
when x"3B2" => DATA <= x"00";
when x"3B3" => DATA <= x"03";
when x"3B4" => DATA <= x"BD";
when x"3B5" => DATA <= x"FC";
when x"3B6" => DATA <= x"C2";
when x"3B7" => DATA <= x"30";
when x"3B8" => DATA <= x"1E";
when x"3B9" => DATA <= x"86";
when x"3BA" => DATA <= x"07";
when x"3BB" => DATA <= x"BD";
when x"3BC" => DATA <= x"FC";
when x"3BD" => DATA <= x"F5";
when x"3BE" => DATA <= x"4F";
when x"3BF" => DATA <= x"BD";
when x"3C0" => DATA <= x"FC";
when x"3C1" => DATA <= x"F5";
when x"3C2" => DATA <= x"BD";
when x"3C3" => DATA <= x"FA";
when x"3C4" => DATA <= x"CB";
when x"3C5" => DATA <= x"8B";
when x"3C6" => DATA <= x"80";
when x"3C7" => DATA <= x"25";
when x"3C8" => DATA <= x"0F";
when x"3C9" => DATA <= x"AE";
when x"3CA" => DATA <= x"84";
when x"3CB" => DATA <= x"BD";
when x"3CC" => DATA <= x"FA";
when x"3CD" => DATA <= x"CB";
when x"3CE" => DATA <= x"A7";
when x"3CF" => DATA <= x"80";
when x"3D0" => DATA <= x"31";
when x"3D1" => DATA <= x"21";
when x"3D2" => DATA <= x"81";
when x"3D3" => DATA <= x"0D";
when x"3D4" => DATA <= x"26";
when x"3D5" => DATA <= x"F5";
when x"3D6" => DATA <= x"31";
when x"3D7" => DATA <= x"3F";
when x"3D8" => DATA <= x"39";
when x"3D9" => DATA <= x"00";
when x"3DA" => DATA <= x"05";
when x"3DB" => DATA <= x"00";
when x"3DC" => DATA <= x"05";
when x"3DD" => DATA <= x"04";
when x"3DE" => DATA <= x"05";
when x"3DF" => DATA <= x"08";
when x"3E0" => DATA <= x"0E";
when x"3E1" => DATA <= x"04";
when x"3E2" => DATA <= x"01";
when x"3E3" => DATA <= x"01";
when x"3E4" => DATA <= x"05";
when x"3E5" => DATA <= x"00";
when x"3E6" => DATA <= x"10";
when x"3E7" => DATA <= x"20";
when x"3E8" => DATA <= x"10";
when x"3E9" => DATA <= x"0D";
when x"3EA" => DATA <= x"00";
when x"3EB" => DATA <= x"04";
when x"3EC" => DATA <= x"80";
when x"3ED" => DATA <= x"05";
when x"3EE" => DATA <= x"00";
when x"3EF" => DATA <= x"05";
when x"3F0" => DATA <= x"00";
when x"3F1" => DATA <= x"05";
when x"3F2" => DATA <= x"00";
when x"3F3" => DATA <= x"00";
when x"3F4" => DATA <= x"00";
when x"3F5" => DATA <= x"05";
when x"3F6" => DATA <= x"09";
when x"3F7" => DATA <= x"05";
when x"3F8" => DATA <= x"00";
when x"3F9" => DATA <= x"08";
when x"3FA" => DATA <= x"19";
when x"3FB" => DATA <= x"00";
when x"3FC" => DATA <= x"01";
when x"3FD" => DATA <= x"0D";
when x"3FE" => DATA <= x"80";
when x"3FF" => DATA <= x"04";
when x"400" => DATA <= x"80";
when x"401" => DATA <= x"34";
when x"402" => DATA <= x"26";
when x"403" => DATA <= x"86";
when x"404" => DATA <= x"0C";
when x"405" => DATA <= x"BD";
when x"406" => DATA <= x"FC";
when x"407" => DATA <= x"F5";
when x"408" => DATA <= x"BD";
when x"409" => DATA <= x"FC";
when x"40A" => DATA <= x"F1";
when x"40B" => DATA <= x"10";
when x"40C" => DATA <= x"8E";
when x"40D" => DATA <= x"00";
when x"40E" => DATA <= x"04";
when x"40F" => DATA <= x"BD";
when x"410" => DATA <= x"FC";
when x"411" => DATA <= x"C2";
when x"412" => DATA <= x"35";
when x"413" => DATA <= x"06";
when x"414" => DATA <= x"BD";
when x"415" => DATA <= x"FC";
when x"416" => DATA <= x"F5";
when x"417" => DATA <= x"BD";
when x"418" => DATA <= x"FA";
when x"419" => DATA <= x"CB";
when x"41A" => DATA <= x"34";
when x"41B" => DATA <= x"02";
when x"41C" => DATA <= x"10";
when x"41D" => DATA <= x"8E";
when x"41E" => DATA <= x"00";
when x"41F" => DATA <= x"04";
when x"420" => DATA <= x"BD";
when x"421" => DATA <= x"FC";
when x"422" => DATA <= x"D2";
when x"423" => DATA <= x"35";
when x"424" => DATA <= x"A2";
when x"425" => DATA <= x"34";
when x"426" => DATA <= x"04";
when x"427" => DATA <= x"86";
when x"428" => DATA <= x"0E";
when x"429" => DATA <= x"BD";
when x"42A" => DATA <= x"FC";
when x"42B" => DATA <= x"F5";
when x"42C" => DATA <= x"BD";
when x"42D" => DATA <= x"FC";
when x"42E" => DATA <= x"F1";
when x"42F" => DATA <= x"35";
when x"430" => DATA <= x"04";
when x"431" => DATA <= x"7E";
when x"432" => DATA <= x"FA";
when x"433" => DATA <= x"C7";
when x"434" => DATA <= x"34";
when x"435" => DATA <= x"06";
when x"436" => DATA <= x"86";
when x"437" => DATA <= x"10";
when x"438" => DATA <= x"BD";
when x"439" => DATA <= x"FC";
when x"43A" => DATA <= x"F5";
when x"43B" => DATA <= x"BD";
when x"43C" => DATA <= x"FC";
when x"43D" => DATA <= x"F1";
when x"43E" => DATA <= x"35";
when x"43F" => DATA <= x"06";
when x"440" => DATA <= x"34";
when x"441" => DATA <= x"06";
when x"442" => DATA <= x"BD";
when x"443" => DATA <= x"FC";
when x"444" => DATA <= x"F5";
when x"445" => DATA <= x"BD";
when x"446" => DATA <= x"FA";
when x"447" => DATA <= x"CB";
when x"448" => DATA <= x"35";
when x"449" => DATA <= x"86";
when x"44A" => DATA <= x"34";
when x"44B" => DATA <= x"06";
when x"44C" => DATA <= x"86";
when x"44D" => DATA <= x"12";
when x"44E" => DATA <= x"BD";
when x"44F" => DATA <= x"FC";
when x"450" => DATA <= x"F5";
when x"451" => DATA <= x"35";
when x"452" => DATA <= x"06";
when x"453" => DATA <= x"BD";
when x"454" => DATA <= x"FC";
when x"455" => DATA <= x"F5";
when x"456" => DATA <= x"4D";
when x"457" => DATA <= x"27";
when x"458" => DATA <= x"06";
when x"459" => DATA <= x"BD";
when x"45A" => DATA <= x"FC";
when x"45B" => DATA <= x"B9";
when x"45C" => DATA <= x"7E";
when x"45D" => DATA <= x"FA";
when x"45E" => DATA <= x"CB";
when x"45F" => DATA <= x"34";
when x"460" => DATA <= x"04";
when x"461" => DATA <= x"BD";
when x"462" => DATA <= x"FC";
when x"463" => DATA <= x"F1";
when x"464" => DATA <= x"BD";
when x"465" => DATA <= x"FA";
when x"466" => DATA <= x"CB";
when x"467" => DATA <= x"4F";
when x"468" => DATA <= x"35";
when x"469" => DATA <= x"84";
when x"46A" => DATA <= x"34";
when x"46B" => DATA <= x"32";
when x"46C" => DATA <= x"86";
when x"46D" => DATA <= x"14";
when x"46E" => DATA <= x"BD";
when x"46F" => DATA <= x"FC";
when x"470" => DATA <= x"F5";
when x"471" => DATA <= x"30";
when x"472" => DATA <= x"02";
when x"473" => DATA <= x"10";
when x"474" => DATA <= x"8E";
when x"475" => DATA <= x"00";
when x"476" => DATA <= x"10";
when x"477" => DATA <= x"BD";
when x"478" => DATA <= x"FC";
when x"479" => DATA <= x"C2";
when x"47A" => DATA <= x"30";
when x"47B" => DATA <= x"1E";
when x"47C" => DATA <= x"AE";
when x"47D" => DATA <= x"84";
when x"47E" => DATA <= x"BD";
when x"47F" => DATA <= x"FC";
when x"480" => DATA <= x"B9";
when x"481" => DATA <= x"35";
when x"482" => DATA <= x"02";
when x"483" => DATA <= x"BD";
when x"484" => DATA <= x"FC";
when x"485" => DATA <= x"F5";
when x"486" => DATA <= x"BD";
when x"487" => DATA <= x"FA";
when x"488" => DATA <= x"CB";
when x"489" => DATA <= x"35";
when x"48A" => DATA <= x"10";
when x"48B" => DATA <= x"34";
when x"48C" => DATA <= x"02";
when x"48D" => DATA <= x"30";
when x"48E" => DATA <= x"02";
when x"48F" => DATA <= x"10";
when x"490" => DATA <= x"8E";
when x"491" => DATA <= x"00";
when x"492" => DATA <= x"10";
when x"493" => DATA <= x"BD";
when x"494" => DATA <= x"FC";
when x"495" => DATA <= x"D2";
when x"496" => DATA <= x"30";
when x"497" => DATA <= x"1E";
when x"498" => DATA <= x"35";
when x"499" => DATA <= x"A2";
when x"49A" => DATA <= x"34";
when x"49B" => DATA <= x"22";
when x"49C" => DATA <= x"86";
when x"49D" => DATA <= x"16";
when x"49E" => DATA <= x"BD";
when x"49F" => DATA <= x"FC";
when x"4A0" => DATA <= x"F5";
when x"4A1" => DATA <= x"10";
when x"4A2" => DATA <= x"8E";
when x"4A3" => DATA <= x"00";
when x"4A4" => DATA <= x"0D";
when x"4A5" => DATA <= x"BD";
when x"4A6" => DATA <= x"FC";
when x"4A7" => DATA <= x"C2";
when x"4A8" => DATA <= x"35";
when x"4A9" => DATA <= x"02";
when x"4AA" => DATA <= x"BD";
when x"4AB" => DATA <= x"FC";
when x"4AC" => DATA <= x"F5";
when x"4AD" => DATA <= x"10";
when x"4AE" => DATA <= x"8E";
when x"4AF" => DATA <= x"00";
when x"4B0" => DATA <= x"0D";
when x"4B1" => DATA <= x"BD";
when x"4B2" => DATA <= x"FC";
when x"4B3" => DATA <= x"D2";
when x"4B4" => DATA <= x"35";
when x"4B5" => DATA <= x"20";
when x"4B6" => DATA <= x"7E";
when x"4B7" => DATA <= x"FA";
when x"4B8" => DATA <= x"C7";
when x"4B9" => DATA <= x"A6";
when x"4BA" => DATA <= x"80";
when x"4BB" => DATA <= x"8D";
when x"4BC" => DATA <= x"38";
when x"4BD" => DATA <= x"81";
when x"4BE" => DATA <= x"0D";
when x"4BF" => DATA <= x"26";
when x"4C0" => DATA <= x"F8";
when x"4C1" => DATA <= x"39";
when x"4C2" => DATA <= x"34";
when x"4C3" => DATA <= x"04";
when x"4C4" => DATA <= x"1F";
when x"4C5" => DATA <= x"20";
when x"4C6" => DATA <= x"3A";
when x"4C7" => DATA <= x"35";
when x"4C8" => DATA <= x"04";
when x"4C9" => DATA <= x"A6";
when x"4CA" => DATA <= x"82";
when x"4CB" => DATA <= x"8D";
when x"4CC" => DATA <= x"28";
when x"4CD" => DATA <= x"31";
when x"4CE" => DATA <= x"3F";
when x"4CF" => DATA <= x"26";
when x"4D0" => DATA <= x"F8";
when x"4D1" => DATA <= x"39";
when x"4D2" => DATA <= x"34";
when x"4D3" => DATA <= x"04";
when x"4D4" => DATA <= x"1F";
when x"4D5" => DATA <= x"20";
when x"4D6" => DATA <= x"3A";
when x"4D7" => DATA <= x"35";
when x"4D8" => DATA <= x"04";
when x"4D9" => DATA <= x"BD";
when x"4DA" => DATA <= x"FA";
when x"4DB" => DATA <= x"CB";
when x"4DC" => DATA <= x"A7";
when x"4DD" => DATA <= x"82";
when x"4DE" => DATA <= x"31";
when x"4DF" => DATA <= x"3F";
when x"4E0" => DATA <= x"26";
when x"4E1" => DATA <= x"F7";
when x"4E2" => DATA <= x"39";
when x"4E3" => DATA <= x"34";
when x"4E4" => DATA <= x"02";
when x"4E5" => DATA <= x"B6";
when x"4E6" => DATA <= x"FE";
when x"4E7" => DATA <= x"E0";
when x"4E8" => DATA <= x"48";
when x"4E9" => DATA <= x"2A";
when x"4EA" => DATA <= x"FA";
when x"4EB" => DATA <= x"35";
when x"4EC" => DATA <= x"02";
when x"4ED" => DATA <= x"B7";
when x"4EE" => DATA <= x"FE";
when x"4EF" => DATA <= x"E1";
when x"4F0" => DATA <= x"39";
when x"4F1" => DATA <= x"1F";
when x"4F2" => DATA <= x"20";
when x"4F3" => DATA <= x"1F";
when x"4F4" => DATA <= x"98";
when x"4F5" => DATA <= x"34";
when x"4F6" => DATA <= x"02";
when x"4F7" => DATA <= x"B6";
when x"4F8" => DATA <= x"FE";
when x"4F9" => DATA <= x"E2";
when x"4FA" => DATA <= x"48";
when x"4FB" => DATA <= x"2A";
when x"4FC" => DATA <= x"FA";
when x"4FD" => DATA <= x"35";
when x"4FE" => DATA <= x"02";
when x"4FF" => DATA <= x"B7";
when x"500" => DATA <= x"FE";
when x"501" => DATA <= x"E3";
when x"502" => DATA <= x"39";
when x"503" => DATA <= x"34";
when x"504" => DATA <= x"02";
when x"505" => DATA <= x"B6";
when x"506" => DATA <= x"FE";
when x"507" => DATA <= x"E6";
when x"508" => DATA <= x"2B";
when x"509" => DATA <= x"51";
when x"50A" => DATA <= x"B6";
when x"50B" => DATA <= x"FE";
when x"50C" => DATA <= x"E0";
when x"50D" => DATA <= x"2B";
when x"50E" => DATA <= x"06";
when x"50F" => DATA <= x"35";
when x"510" => DATA <= x"02";
when x"511" => DATA <= x"6E";
when x"512" => DATA <= x"9F";
when x"513" => DATA <= x"FF";
when x"514" => DATA <= x"B1";
when x"515" => DATA <= x"B6";
when x"516" => DATA <= x"FE";
when x"517" => DATA <= x"E1";
when x"518" => DATA <= x"2B";
when x"519" => DATA <= x"1B";
when x"51A" => DATA <= x"35";
when x"51B" => DATA <= x"02";
when x"51C" => DATA <= x"34";
when x"51D" => DATA <= x"76";
when x"51E" => DATA <= x"8D";
when x"51F" => DATA <= x"1C";
when x"520" => DATA <= x"1F";
when x"521" => DATA <= x"89";
when x"522" => DATA <= x"4F";
when x"523" => DATA <= x"1F";
when x"524" => DATA <= x"02";
when x"525" => DATA <= x"8D";
when x"526" => DATA <= x"15";
when x"527" => DATA <= x"1F";
when x"528" => DATA <= x"89";
when x"529" => DATA <= x"4F";
when x"52A" => DATA <= x"1F";
when x"52B" => DATA <= x"01";
when x"52C" => DATA <= x"8D";
when x"52D" => DATA <= x"0E";
when x"52E" => DATA <= x"AD";
when x"52F" => DATA <= x"9F";
when x"530" => DATA <= x"FF";
when x"531" => DATA <= x"FC";
when x"532" => DATA <= x"35";
when x"533" => DATA <= x"76";
when x"534" => DATA <= x"3B";
when x"535" => DATA <= x"48";
when x"536" => DATA <= x"B7";
when x"537" => DATA <= x"FF";
when x"538" => DATA <= x"80";
when x"539" => DATA <= x"35";
when x"53A" => DATA <= x"02";
when x"53B" => DATA <= x"3B";
when x"53C" => DATA <= x"B6";
when x"53D" => DATA <= x"FE";
when x"53E" => DATA <= x"E6";
when x"53F" => DATA <= x"2A";
when x"540" => DATA <= x"02";
when x"541" => DATA <= x"8D";
when x"542" => DATA <= x"12";
when x"543" => DATA <= x"B6";
when x"544" => DATA <= x"FE";
when x"545" => DATA <= x"E0";
when x"546" => DATA <= x"2A";
when x"547" => DATA <= x"F4";
when x"548" => DATA <= x"B6";
when x"549" => DATA <= x"FE";
when x"54A" => DATA <= x"E1";
when x"54B" => DATA <= x"39";
when x"54C" => DATA <= x"B6";
when x"54D" => DATA <= x"FE";
when x"54E" => DATA <= x"E6";
when x"54F" => DATA <= x"2A";
when x"550" => DATA <= x"FB";
when x"551" => DATA <= x"B6";
when x"552" => DATA <= x"FE";
when x"553" => DATA <= x"E7";
when x"554" => DATA <= x"39";
when x"555" => DATA <= x"1C";
when x"556" => DATA <= x"7F";
when x"557" => DATA <= x"34";
when x"558" => DATA <= x"01";
when x"559" => DATA <= x"34";
when x"55A" => DATA <= x"02";
when x"55B" => DATA <= x"35";
when x"55C" => DATA <= x"02";
when x"55D" => DATA <= x"34";
when x"55E" => DATA <= x"16";
when x"55F" => DATA <= x"B6";
when x"560" => DATA <= x"FE";
when x"561" => DATA <= x"E7";
when x"562" => DATA <= x"2A";
when x"563" => DATA <= x"22";
when x"564" => DATA <= x"10";
when x"565" => DATA <= x"CE";
when x"566" => DATA <= x"FF";
when x"567" => DATA <= x"80";
when x"568" => DATA <= x"8E";
when x"569" => DATA <= x"FF";
when x"56A" => DATA <= x"00";
when x"56B" => DATA <= x"BD";
when x"56C" => DATA <= x"FA";
when x"56D" => DATA <= x"CB";
when x"56E" => DATA <= x"86";
when x"56F" => DATA <= x"3F";
when x"570" => DATA <= x"A7";
when x"571" => DATA <= x"80";
when x"572" => DATA <= x"BD";
when x"573" => DATA <= x"FA";
when x"574" => DATA <= x"CB";
when x"575" => DATA <= x"A7";
when x"576" => DATA <= x"80";
when x"577" => DATA <= x"BD";
when x"578" => DATA <= x"FA";
when x"579" => DATA <= x"CB";
when x"57A" => DATA <= x"A7";
when x"57B" => DATA <= x"80";
when x"57C" => DATA <= x"26";
when x"57D" => DATA <= x"F9";
when x"57E" => DATA <= x"8E";
when x"57F" => DATA <= x"FF";
when x"580" => DATA <= x"01";
when x"581" => DATA <= x"34";
when x"582" => DATA <= x"10";
when x"583" => DATA <= x"7E";
when x"584" => DATA <= x"FF";
when x"585" => DATA <= x"BC";
when x"586" => DATA <= x"34";
when x"587" => DATA <= x"02";
when x"588" => DATA <= x"8D";
when x"589" => DATA <= x"C2";
when x"58A" => DATA <= x"35";
when x"58B" => DATA <= x"02";
when x"58C" => DATA <= x"81";
when x"58D" => DATA <= x"05";
when x"58E" => DATA <= x"26";
when x"58F" => DATA <= x"06";
when x"590" => DATA <= x"7F";
when x"591" => DATA <= x"FF";
when x"592" => DATA <= x"94";
when x"593" => DATA <= x"35";
when x"594" => DATA <= x"16";
when x"595" => DATA <= x"3B";
when x"596" => DATA <= x"34";
when x"597" => DATA <= x"02";
when x"598" => DATA <= x"8D";
when x"599" => DATA <= x"B2";
when x"59A" => DATA <= x"8D";
when x"59B" => DATA <= x"B0";
when x"59C" => DATA <= x"8D";
when x"59D" => DATA <= x"AE";
when x"59E" => DATA <= x"1E";
when x"59F" => DATA <= x"89";
when x"5A0" => DATA <= x"8D";
when x"5A1" => DATA <= x"AA";
when x"5A2" => DATA <= x"1E";
when x"5A3" => DATA <= x"89";
when x"5A4" => DATA <= x"1F";
when x"5A5" => DATA <= x"01";
when x"5A6" => DATA <= x"8D";
when x"5A7" => DATA <= x"A4";
when x"5A8" => DATA <= x"86";
when x"5A9" => DATA <= x"FF";
when x"5AA" => DATA <= x"B7";
when x"5AB" => DATA <= x"FF";
when x"5AC" => DATA <= x"94";
when x"5AD" => DATA <= x"1C";
when x"5AE" => DATA <= x"BF";
when x"5AF" => DATA <= x"A6";
when x"5B0" => DATA <= x"E0";
when x"5B1" => DATA <= x"27";
when x"5B2" => DATA <= x"66";
when x"5B3" => DATA <= x"81";
when x"5B4" => DATA <= x"02";
when x"5B5" => DATA <= x"25";
when x"5B6" => DATA <= x"55";
when x"5B7" => DATA <= x"27";
when x"5B8" => DATA <= x"43";
when x"5B9" => DATA <= x"81";
when x"5BA" => DATA <= x"04";
when x"5BB" => DATA <= x"25";
when x"5BC" => DATA <= x"2F";
when x"5BD" => DATA <= x"27";
when x"5BE" => DATA <= x"69";
when x"5BF" => DATA <= x"5F";
when x"5C0" => DATA <= x"81";
when x"5C1" => DATA <= x"07";
when x"5C2" => DATA <= x"25";
when x"5C3" => DATA <= x"11";
when x"5C4" => DATA <= x"26";
when x"5C5" => DATA <= x"65";
when x"5C6" => DATA <= x"B6";
when x"5C7" => DATA <= x"FE";
when x"5C8" => DATA <= x"E4";
when x"5C9" => DATA <= x"2A";
when x"5CA" => DATA <= x"FB";
when x"5CB" => DATA <= x"B6";
when x"5CC" => DATA <= x"FE";
when x"5CD" => DATA <= x"E5";
when x"5CE" => DATA <= x"A7";
when x"5CF" => DATA <= x"85";
when x"5D0" => DATA <= x"5C";
when x"5D1" => DATA <= x"26";
when x"5D2" => DATA <= x"F3";
when x"5D3" => DATA <= x"20";
when x"5D4" => DATA <= x"56";
when x"5D5" => DATA <= x"B6";
when x"5D6" => DATA <= x"FE";
when x"5D7" => DATA <= x"E4";
when x"5D8" => DATA <= x"2A";
when x"5D9" => DATA <= x"FB";
when x"5DA" => DATA <= x"A6";
when x"5DB" => DATA <= x"85";
when x"5DC" => DATA <= x"B7";
when x"5DD" => DATA <= x"FE";
when x"5DE" => DATA <= x"E5";
when x"5DF" => DATA <= x"5C";
when x"5E0" => DATA <= x"26";
when x"5E1" => DATA <= x"F3";
when x"5E2" => DATA <= x"B6";
when x"5E3" => DATA <= x"FE";
when x"5E4" => DATA <= x"E4";
when x"5E5" => DATA <= x"2A";
when x"5E6" => DATA <= x"FB";
when x"5E7" => DATA <= x"B7";
when x"5E8" => DATA <= x"FE";
when x"5E9" => DATA <= x"E5";
when x"5EA" => DATA <= x"20";
when x"5EB" => DATA <= x"3F";
when x"5EC" => DATA <= x"13";
when x"5ED" => DATA <= x"B6";
when x"5EE" => DATA <= x"FF";
when x"5EF" => DATA <= x"94";
when x"5F0" => DATA <= x"27";
when x"5F1" => DATA <= x"39";
when x"5F2" => DATA <= x"B6";
when x"5F3" => DATA <= x"FE";
when x"5F4" => DATA <= x"E5";
when x"5F5" => DATA <= x"F6";
when x"5F6" => DATA <= x"FE";
when x"5F7" => DATA <= x"E5";
when x"5F8" => DATA <= x"ED";
when x"5F9" => DATA <= x"81";
when x"5FA" => DATA <= x"20";
when x"5FB" => DATA <= x"F0";
when x"5FC" => DATA <= x"13";
when x"5FD" => DATA <= x"B6";
when x"5FE" => DATA <= x"FF";
when x"5FF" => DATA <= x"94";
when x"600" => DATA <= x"27";
when x"601" => DATA <= x"29";
when x"602" => DATA <= x"EC";
when x"603" => DATA <= x"81";
when x"604" => DATA <= x"B7";
when x"605" => DATA <= x"FE";
when x"606" => DATA <= x"E5";
when x"607" => DATA <= x"F7";
when x"608" => DATA <= x"FE";
when x"609" => DATA <= x"E5";
when x"60A" => DATA <= x"20";
when x"60B" => DATA <= x"F0";
when x"60C" => DATA <= x"13";
when x"60D" => DATA <= x"B6";
when x"60E" => DATA <= x"FF";
when x"60F" => DATA <= x"94";
when x"610" => DATA <= x"27";
when x"611" => DATA <= x"19";
when x"612" => DATA <= x"B6";
when x"613" => DATA <= x"FE";
when x"614" => DATA <= x"E5";
when x"615" => DATA <= x"A7";
when x"616" => DATA <= x"80";
when x"617" => DATA <= x"20";
when x"618" => DATA <= x"F3";
when x"619" => DATA <= x"13";
when x"61A" => DATA <= x"B6";
when x"61B" => DATA <= x"FF";
when x"61C" => DATA <= x"94";
when x"61D" => DATA <= x"27";
when x"61E" => DATA <= x"0C";
when x"61F" => DATA <= x"A6";
when x"620" => DATA <= x"80";
when x"621" => DATA <= x"B7";
when x"622" => DATA <= x"FE";
when x"623" => DATA <= x"E5";
when x"624" => DATA <= x"20";
when x"625" => DATA <= x"F3";
when x"626" => DATA <= x"20";
when x"627" => DATA <= x"03";
when x"628" => DATA <= x"BF";
when x"629" => DATA <= x"FF";
when x"62A" => DATA <= x"8E";
when x"62B" => DATA <= x"35";
when x"62C" => DATA <= x"16";
when x"62D" => DATA <= x"3B";
when x"62E" => DATA <= x"32";
when x"62F" => DATA <= x"6A";
when x"630" => DATA <= x"35";
when x"631" => DATA <= x"10";
when x"632" => DATA <= x"BF";
when x"633" => DATA <= x"FF";
when x"634" => DATA <= x"82";
when x"635" => DATA <= x"1C";
when x"636" => DATA <= x"00";
when x"637" => DATA <= x"6E";
when x"638" => DATA <= x"9F";
when x"639" => DATA <= x"FF";
when x"63A" => DATA <= x"FA";
when x"63B" => DATA <= x"FF";
when x"63C" => DATA <= x"FF";
when x"63D" => DATA <= x"FF";
when x"63E" => DATA <= x"FF";
when x"63F" => DATA <= x"FF";
when x"640" => DATA <= x"FF";
when x"641" => DATA <= x"FF";
when x"642" => DATA <= x"FF";
when x"643" => DATA <= x"FF";
when x"644" => DATA <= x"FF";
when x"645" => DATA <= x"FF";
when x"646" => DATA <= x"FF";
when x"647" => DATA <= x"FF";
when x"648" => DATA <= x"FF";
when x"649" => DATA <= x"FF";
when x"64A" => DATA <= x"FF";
when x"64B" => DATA <= x"FF";
when x"64C" => DATA <= x"FF";
when x"64D" => DATA <= x"FF";
when x"64E" => DATA <= x"FF";
when x"64F" => DATA <= x"FF";
when x"650" => DATA <= x"FF";
when x"651" => DATA <= x"FF";
when x"652" => DATA <= x"FF";
when x"653" => DATA <= x"FF";
when x"654" => DATA <= x"FF";
when x"655" => DATA <= x"FF";
when x"656" => DATA <= x"FF";
when x"657" => DATA <= x"FF";
when x"658" => DATA <= x"FF";
when x"659" => DATA <= x"FF";
when x"65A" => DATA <= x"FF";
when x"65B" => DATA <= x"FF";
when x"65C" => DATA <= x"FF";
when x"65D" => DATA <= x"FF";
when x"65E" => DATA <= x"FF";
when x"65F" => DATA <= x"FF";
when x"660" => DATA <= x"FF";
when x"661" => DATA <= x"FF";
when x"662" => DATA <= x"FF";
when x"663" => DATA <= x"FF";
when x"664" => DATA <= x"FF";
when x"665" => DATA <= x"FF";
when x"666" => DATA <= x"FF";
when x"667" => DATA <= x"FF";
when x"668" => DATA <= x"FF";
when x"669" => DATA <= x"FF";
when x"66A" => DATA <= x"FF";
when x"66B" => DATA <= x"FF";
when x"66C" => DATA <= x"FF";
when x"66D" => DATA <= x"FF";
when x"66E" => DATA <= x"FF";
when x"66F" => DATA <= x"FF";
when x"670" => DATA <= x"FF";
when x"671" => DATA <= x"FF";
when x"672" => DATA <= x"FF";
when x"673" => DATA <= x"FF";
when x"674" => DATA <= x"FF";
when x"675" => DATA <= x"FF";
when x"676" => DATA <= x"FF";
when x"677" => DATA <= x"FF";
when x"678" => DATA <= x"FF";
when x"679" => DATA <= x"FF";
when x"67A" => DATA <= x"FF";
when x"67B" => DATA <= x"FF";
when x"67C" => DATA <= x"FF";
when x"67D" => DATA <= x"FF";
when x"67E" => DATA <= x"FF";
when x"67F" => DATA <= x"FF";
when x"680" => DATA <= x"FF";
when x"681" => DATA <= x"FF";
when x"682" => DATA <= x"FF";
when x"683" => DATA <= x"FF";
when x"684" => DATA <= x"FF";
when x"685" => DATA <= x"FF";
when x"686" => DATA <= x"FF";
when x"687" => DATA <= x"FF";
when x"688" => DATA <= x"FF";
when x"689" => DATA <= x"FF";
when x"68A" => DATA <= x"FF";
when x"68B" => DATA <= x"FF";
when x"68C" => DATA <= x"FF";
when x"68D" => DATA <= x"FF";
when x"68E" => DATA <= x"FF";
when x"68F" => DATA <= x"FF";
when x"690" => DATA <= x"FF";
when x"691" => DATA <= x"FF";
when x"692" => DATA <= x"FF";
when x"693" => DATA <= x"FF";
when x"694" => DATA <= x"FF";
when x"695" => DATA <= x"FF";
when x"696" => DATA <= x"FF";
when x"697" => DATA <= x"FF";
when x"698" => DATA <= x"FF";
when x"699" => DATA <= x"FF";
when x"69A" => DATA <= x"FF";
when x"69B" => DATA <= x"FF";
when x"69C" => DATA <= x"FF";
when x"69D" => DATA <= x"FF";
when x"69E" => DATA <= x"FF";
when x"69F" => DATA <= x"FF";
when x"6A0" => DATA <= x"FF";
when x"6A1" => DATA <= x"FF";
when x"6A2" => DATA <= x"FF";
when x"6A3" => DATA <= x"FF";
when x"6A4" => DATA <= x"FF";
when x"6A5" => DATA <= x"FF";
when x"6A6" => DATA <= x"FF";
when x"6A7" => DATA <= x"FF";
when x"6A8" => DATA <= x"FF";
when x"6A9" => DATA <= x"FF";
when x"6AA" => DATA <= x"FF";
when x"6AB" => DATA <= x"FF";
when x"6AC" => DATA <= x"FF";
when x"6AD" => DATA <= x"FF";
when x"6AE" => DATA <= x"FF";
when x"6AF" => DATA <= x"FF";
when x"6B0" => DATA <= x"FF";
when x"6B1" => DATA <= x"FF";
when x"6B2" => DATA <= x"FF";
when x"6B3" => DATA <= x"FF";
when x"6B4" => DATA <= x"FF";
when x"6B5" => DATA <= x"FF";
when x"6B6" => DATA <= x"FF";
when x"6B7" => DATA <= x"FF";
when x"6B8" => DATA <= x"FF";
when x"6B9" => DATA <= x"FF";
when x"6BA" => DATA <= x"FF";
when x"6BB" => DATA <= x"FF";
when x"6BC" => DATA <= x"FF";
when x"6BD" => DATA <= x"FF";
when x"6BE" => DATA <= x"FF";
when x"6BF" => DATA <= x"FF";
when x"6C0" => DATA <= x"FF";
when x"6C1" => DATA <= x"FF";
when x"6C2" => DATA <= x"FF";
when x"6C3" => DATA <= x"FF";
when x"6C4" => DATA <= x"FF";
when x"6C5" => DATA <= x"FF";
when x"6C6" => DATA <= x"FF";
when x"6C7" => DATA <= x"FF";
when x"6C8" => DATA <= x"FF";
when x"6C9" => DATA <= x"FF";
when x"6CA" => DATA <= x"FF";
when x"6CB" => DATA <= x"FF";
when x"6CC" => DATA <= x"FF";
when x"6CD" => DATA <= x"FF";
when x"6CE" => DATA <= x"FF";
when x"6CF" => DATA <= x"FF";
when x"6D0" => DATA <= x"FF";
when x"6D1" => DATA <= x"FF";
when x"6D2" => DATA <= x"FF";
when x"6D3" => DATA <= x"FF";
when x"6D4" => DATA <= x"FF";
when x"6D5" => DATA <= x"FF";
when x"6D6" => DATA <= x"FF";
when x"6D7" => DATA <= x"FF";
when x"6D8" => DATA <= x"FF";
when x"6D9" => DATA <= x"FF";
when x"6DA" => DATA <= x"FF";
when x"6DB" => DATA <= x"FF";
when x"6DC" => DATA <= x"FF";
when x"6DD" => DATA <= x"FF";
when x"6DE" => DATA <= x"FF";
when x"6DF" => DATA <= x"FF";
when x"6E0" => DATA <= x"00";
when x"6E1" => DATA <= x"00";
when x"6E2" => DATA <= x"00";
when x"6E3" => DATA <= x"00";
when x"6E4" => DATA <= x"00";
when x"6E5" => DATA <= x"00";
when x"6E6" => DATA <= x"00";
when x"6E7" => DATA <= x"00";
when x"6E8" => DATA <= x"FF";
when x"6E9" => DATA <= x"FF";
when x"6EA" => DATA <= x"FF";
when x"6EB" => DATA <= x"FF";
when x"6EC" => DATA <= x"FF";
when x"6ED" => DATA <= x"FF";
when x"6EE" => DATA <= x"FF";
when x"6EF" => DATA <= x"FF";
when x"6F0" => DATA <= x"FE";
when x"6F1" => DATA <= x"2D";
when x"6F2" => DATA <= x"FE";
when x"6F3" => DATA <= x"2D";
when x"6F4" => DATA <= x"FE";
when x"6F5" => DATA <= x"2D";
when x"6F6" => DATA <= x"FD";
when x"6F7" => DATA <= x"03";
when x"6F8" => DATA <= x"FE";
when x"6F9" => DATA <= x"2D";
when x"6FA" => DATA <= x"FE";
when x"6FB" => DATA <= x"2E";
when x"6FC" => DATA <= x"FE";
when x"6FD" => DATA <= x"2D";
when x"6FE" => DATA <= x"F8";
when x"6FF" => DATA <= x"2C";
when x"700" => DATA <= x"00";
when x"701" => DATA <= x"00";
when x"702" => DATA <= x"00";
when x"703" => DATA <= x"00";
when x"704" => DATA <= x"00";
when x"705" => DATA <= x"00";
when x"706" => DATA <= x"00";
when x"707" => DATA <= x"00";
when x"708" => DATA <= x"00";
when x"709" => DATA <= x"00";
when x"70A" => DATA <= x"00";
when x"70B" => DATA <= x"00";
when x"70C" => DATA <= x"00";
when x"70D" => DATA <= x"00";
when x"70E" => DATA <= x"00";
when x"70F" => DATA <= x"00";
when x"710" => DATA <= x"00";
when x"711" => DATA <= x"00";
when x"712" => DATA <= x"00";
when x"713" => DATA <= x"00";
when x"714" => DATA <= x"00";
when x"715" => DATA <= x"00";
when x"716" => DATA <= x"00";
when x"717" => DATA <= x"00";
when x"718" => DATA <= x"00";
when x"719" => DATA <= x"00";
when x"71A" => DATA <= x"00";
when x"71B" => DATA <= x"00";
when x"71C" => DATA <= x"00";
when x"71D" => DATA <= x"00";
when x"71E" => DATA <= x"00";
when x"71F" => DATA <= x"00";
when x"720" => DATA <= x"00";
when x"721" => DATA <= x"00";
when x"722" => DATA <= x"00";
when x"723" => DATA <= x"00";
when x"724" => DATA <= x"00";
when x"725" => DATA <= x"00";
when x"726" => DATA <= x"00";
when x"727" => DATA <= x"00";
when x"728" => DATA <= x"00";
when x"729" => DATA <= x"00";
when x"72A" => DATA <= x"00";
when x"72B" => DATA <= x"00";
when x"72C" => DATA <= x"00";
when x"72D" => DATA <= x"00";
when x"72E" => DATA <= x"00";
when x"72F" => DATA <= x"00";
when x"730" => DATA <= x"00";
when x"731" => DATA <= x"00";
when x"732" => DATA <= x"00";
when x"733" => DATA <= x"00";
when x"734" => DATA <= x"00";
when x"735" => DATA <= x"00";
when x"736" => DATA <= x"00";
when x"737" => DATA <= x"00";
when x"738" => DATA <= x"00";
when x"739" => DATA <= x"00";
when x"73A" => DATA <= x"00";
when x"73B" => DATA <= x"00";
when x"73C" => DATA <= x"00";
when x"73D" => DATA <= x"00";
when x"73E" => DATA <= x"00";
when x"73F" => DATA <= x"00";
when x"740" => DATA <= x"00";
when x"741" => DATA <= x"00";
when x"742" => DATA <= x"00";
when x"743" => DATA <= x"00";
when x"744" => DATA <= x"00";
when x"745" => DATA <= x"00";
when x"746" => DATA <= x"00";
when x"747" => DATA <= x"00";
when x"748" => DATA <= x"00";
when x"749" => DATA <= x"00";
when x"74A" => DATA <= x"00";
when x"74B" => DATA <= x"00";
when x"74C" => DATA <= x"00";
when x"74D" => DATA <= x"00";
when x"74E" => DATA <= x"00";
when x"74F" => DATA <= x"00";
when x"750" => DATA <= x"00";
when x"751" => DATA <= x"00";
when x"752" => DATA <= x"00";
when x"753" => DATA <= x"00";
when x"754" => DATA <= x"00";
when x"755" => DATA <= x"00";
when x"756" => DATA <= x"00";
when x"757" => DATA <= x"00";
when x"758" => DATA <= x"00";
when x"759" => DATA <= x"00";
when x"75A" => DATA <= x"00";
when x"75B" => DATA <= x"00";
when x"75C" => DATA <= x"00";
when x"75D" => DATA <= x"00";
when x"75E" => DATA <= x"00";
when x"75F" => DATA <= x"00";
when x"760" => DATA <= x"00";
when x"761" => DATA <= x"00";
when x"762" => DATA <= x"00";
when x"763" => DATA <= x"00";
when x"764" => DATA <= x"00";
when x"765" => DATA <= x"00";
when x"766" => DATA <= x"00";
when x"767" => DATA <= x"00";
when x"768" => DATA <= x"00";
when x"769" => DATA <= x"00";
when x"76A" => DATA <= x"00";
when x"76B" => DATA <= x"00";
when x"76C" => DATA <= x"00";
when x"76D" => DATA <= x"00";
when x"76E" => DATA <= x"00";
when x"76F" => DATA <= x"00";
when x"770" => DATA <= x"00";
when x"771" => DATA <= x"00";
when x"772" => DATA <= x"00";
when x"773" => DATA <= x"00";
when x"774" => DATA <= x"00";
when x"775" => DATA <= x"00";
when x"776" => DATA <= x"00";
when x"777" => DATA <= x"00";
when x"778" => DATA <= x"00";
when x"779" => DATA <= x"00";
when x"77A" => DATA <= x"00";
when x"77B" => DATA <= x"00";
when x"77C" => DATA <= x"00";
when x"77D" => DATA <= x"00";
when x"77E" => DATA <= x"00";
when x"77F" => DATA <= x"00";
when x"780" => DATA <= x"00";
when x"781" => DATA <= x"00";
when x"782" => DATA <= x"F8";
when x"783" => DATA <= x"16";
when x"784" => DATA <= x"F8";
when x"785" => DATA <= x"B0";
when x"786" => DATA <= x"F8";
when x"787" => DATA <= x"16";
when x"788" => DATA <= x"00";
when x"789" => DATA <= x"00";
when x"78A" => DATA <= x"F8";
when x"78B" => DATA <= x"00";
when x"78C" => DATA <= x"00";
when x"78D" => DATA <= x"00";
when x"78E" => DATA <= x"00";
when x"78F" => DATA <= x"00";
when x"790" => DATA <= x"FF";
when x"791" => DATA <= x"B9";
when x"792" => DATA <= x"FF";
when x"793" => DATA <= x"B9";
when x"794" => DATA <= x"00";
when x"795" => DATA <= x"7E";
when x"796" => DATA <= x"FA";
when x"797" => DATA <= x"9B";
when x"798" => DATA <= x"7E";
when x"799" => DATA <= x"F8";
when x"79A" => DATA <= x"2C";
when x"79B" => DATA <= x"7E";
when x"79C" => DATA <= x"FA";
when x"79D" => DATA <= x"9B";
when x"79E" => DATA <= x"7E";
when x"79F" => DATA <= x"FA";
when x"7A0" => DATA <= x"9B";
when x"7A1" => DATA <= x"7E";
when x"7A2" => DATA <= x"F9";
when x"7A3" => DATA <= x"3E";
when x"7A4" => DATA <= x"7E";
when x"7A5" => DATA <= x"FA";
when x"7A6" => DATA <= x"9B";
when x"7A7" => DATA <= x"7E";
when x"7A8" => DATA <= x"F8";
when x"7A9" => DATA <= x"71";
when x"7AA" => DATA <= x"7E";
when x"7AB" => DATA <= x"F9";
when x"7AC" => DATA <= x"17";
when x"7AD" => DATA <= x"7E";
when x"7AE" => DATA <= x"F9";
when x"7AF" => DATA <= x"0F";
when x"7B0" => DATA <= x"7E";
when x"7B1" => DATA <= x"FE";
when x"7B2" => DATA <= x"2D";
when x"7B3" => DATA <= x"7E";
when x"7B4" => DATA <= x"F9";
when x"7B5" => DATA <= x"2E";
when x"7B6" => DATA <= x"7E";
when x"7B7" => DATA <= x"FA";
when x"7B8" => DATA <= x"9B";
when x"7B9" => DATA <= x"7E";
when x"7BA" => DATA <= x"F8";
when x"7BB" => DATA <= x"71";
when x"7BC" => DATA <= x"7E";
when x"7BD" => DATA <= x"FE";
when x"7BE" => DATA <= x"30";
when x"7BF" => DATA <= x"7E";
when x"7C0" => DATA <= x"F8";
when x"7C1" => DATA <= x"D3";
when x"7C2" => DATA <= x"7E";
when x"7C3" => DATA <= x"FA";
when x"7C4" => DATA <= x"9B";
when x"7C5" => DATA <= x"7E";
when x"7C6" => DATA <= x"F9";
when x"7C7" => DATA <= x"35";
when x"7C8" => DATA <= x"7E";
when x"7C9" => DATA <= x"FA";
when x"7CA" => DATA <= x"9B";
when x"7CB" => DATA <= x"7E";
when x"7CC" => DATA <= x"FA";
when x"7CD" => DATA <= x"9B";
when x"7CE" => DATA <= x"7E";
when x"7CF" => DATA <= x"FC";
when x"7D0" => DATA <= x"4A";
when x"7D1" => DATA <= x"7E";
when x"7D2" => DATA <= x"FC";
when x"7D3" => DATA <= x"9A";
when x"7D4" => DATA <= x"7E";
when x"7D5" => DATA <= x"FC";
when x"7D6" => DATA <= x"34";
when x"7D7" => DATA <= x"7E";
when x"7D8" => DATA <= x"FC";
when x"7D9" => DATA <= x"25";
when x"7DA" => DATA <= x"7E";
when x"7DB" => DATA <= x"FC";
when x"7DC" => DATA <= x"01";
when x"7DD" => DATA <= x"7E";
when x"7DE" => DATA <= x"FC";
when x"7DF" => DATA <= x"6A";
when x"7E0" => DATA <= x"7E";
when x"7E1" => DATA <= x"FA";
when x"7E2" => DATA <= x"C3";
when x"7E3" => DATA <= x"81";
when x"7E4" => DATA <= x"0D";
when x"7E5" => DATA <= x"26";
when x"7E6" => DATA <= x"07";
when x"7E7" => DATA <= x"86";
when x"7E8" => DATA <= x"0A";
when x"7E9" => DATA <= x"BD";
when x"7EA" => DATA <= x"FF";
when x"7EB" => DATA <= x"EE";
when x"7EC" => DATA <= x"86";
when x"7ED" => DATA <= x"0D";
when x"7EE" => DATA <= x"7E";
when x"7EF" => DATA <= x"FC";
when x"7F0" => DATA <= x"E3";
when x"7F1" => DATA <= x"7E";
when x"7F2" => DATA <= x"FB";
when x"7F3" => DATA <= x"4A";
when x"7F4" => DATA <= x"7E";
when x"7F5" => DATA <= x"FA";
when x"7F6" => DATA <= x"D4";
when x"7F7" => DATA <= x"7E";
when x"7F8" => DATA <= x"F9";
when x"7F9" => DATA <= x"80";
when x"7FA" => DATA <= x"F8";
when x"7FB" => DATA <= x"B0";
when x"7FC" => DATA <= x"FA";
when x"7FD" => DATA <= x"9B";
when x"7FE" => DATA <= x"F8";
when x"7FF" => DATA <= x"2C";
when others => DATA <= (others => '0');
end case;
end process;
end RTL;
| gpl-3.0 | d87fc0d2453a42d6ed7aa0052ae17b1d | 0.358731 | 2.974721 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/spi/spi2ahb.vhd | 1 | 2,987 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: spi2ahb
-- File: spi2ahb.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- Contact: [email protected]
-- Description: Simple SPI slave providing a bridge to AMBA AHB
-- See spi2ahbx.vhd and GRIP for documentation
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.conv_std_logic_vector;
library gaisler;
use gaisler.spi.all;
entity spi2ahb is
generic (
-- AHB Configuration
hindex : integer := 0;
--
ahbaddrh : integer := 0;
ahbaddrl : integer := 0;
ahbmaskh : integer := 0;
ahbmaskl : integer := 0;
--
oepol : integer range 0 to 1 := 0;
--
filter : integer range 2 to 512 := 2;
--
cpol : integer range 0 to 1 := 0;
cpha : integer range 0 to 1 := 0
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
-- SPI signals
spii : in spi_in_type;
spio : out spi_out_type
);
end entity spi2ahb;
architecture rtl of spi2ahb is
signal spi2ahbi : spi2ahb_in_type;
begin
bridge : spi2ahbx
generic map (
hindex => hindex,
oepol => oepol,
filter => filter,
cpol => cpol,
cpha => cpha)
port map (
rstn => rstn,
clk => clk,
ahbi => ahbi,
ahbo => ahbo,
spii => spii,
spio => spio,
spi2ahbi => spi2ahbi,
spi2ahbo => open);
spi2ahbi.en <= '1';
spi2ahbi.haddr <= conv_std_logic_vector(ahbaddrh, 16) &
conv_std_logic_vector(ahbaddrl, 16);
spi2ahbi.hmask <= conv_std_logic_vector(ahbmaskh, 16) &
conv_std_logic_vector(ahbmaskl, 16);
end architecture rtl;
| gpl-3.0 | cf6b62e54e0f83a25cbc7fd4adefe555 | 0.569133 | 3.889323 | false | false | false | false |
firecake/IRIS | FPGA/VHDL/ipcore_dir/Clk_Manager.vhd | 1 | 2,812 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.7
-- \ \ Application : xaw2vhdl
-- / / Filename : Clk_Manager.vhd
-- /___/ /\ Timestamp : 05/28/2015 11:45:02
-- \ \ / \
-- \___\/\___\
--
--Command: xaw2vhdl-st C:\IRIS\ipcore_dir\.\Clk_Manager.xaw C:\IRIS\ipcore_dir\.\Clk_Manager
--Design Name: Clk_Manager
--Device: xc3s200a-4vq100
--
-- Module Clk_Manager
-- Generated by Xilinx Architecture Wizard
-- Written for synthesis tool: XST
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity Clk_Manager is
port ( CLKIN_IN : in std_logic;
CLKIN_IBUFG_OUT : out std_logic;
CLK0_OUT : out std_logic;
LOCKED_OUT : out std_logic);
end Clk_Manager;
architecture BEHAVIORAL of Clk_Manager is
signal CLKFB_IN : std_logic;
signal CLKIN_IBUFG : std_logic;
signal CLK0_BUF : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
CLK0_OUT <= CLKFB_IN;
CLKIN_IBUFG_INST : IBUFG
port map (I=>CLKIN_IN,
O=>CLKIN_IBUFG);
CLK0_BUFG_INST : BUFG
port map (I=>CLK0_BUF,
O=>CLKFB_IN);
DCM_SP_INST : DCM_SP
generic map( CLK_FEEDBACK => "1X",
CLKDV_DIVIDE => 2.0,
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 4,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 25.000,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map (CLKFB=>CLKFB_IN,
CLKIN=>CLKIN_IBUFG,
DSSEN=>GND_BIT,
PSCLK=>GND_BIT,
PSEN=>GND_BIT,
PSINCDEC=>GND_BIT,
RST=>GND_BIT,
CLKDV=>open,
CLKFX=>open,
CLKFX180=>open,
CLK0=>CLK0_BUF,
CLK2X=>open,
CLK2X180=>open,
CLK90=>open,
CLK180=>open,
CLK270=>open,
LOCKED=>LOCKED_OUT,
PSDONE=>open,
STATUS=>open);
end BEHAVIORAL;
| gpl-3.0 | fa902e0420d92597fd5fc1d53fc7ca65 | 0.448791 | 3.831063 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/misc/ahbtrace_mb.vhd | 1 | 3,199 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbtrace_mb
-- File: ahbtrace_mb.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Jan Andersson - Aeroflex Gaisler
-- Description: AHB trace unit that can have registers on a separate bus
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.misc.all;
entity ahbtrace_mb is
generic (
hindex : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#E00#;
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 1;
bwidth : integer := 32;
ahbfilt : integer := 0;
scantest : integer range 0 to 1 := 0;
exttimer : integer range 0 to 1 := 0;
exten : integer range 0 to 1 := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type; -- Register interface
ahbso : out ahb_slv_out_type;
tahbmi : in ahb_mst_in_type; -- Trace
tahbsi : in ahb_slv_in_type;
timer : in std_logic_vector(30 downto 0) := (others => '0');
astat : out amba_stat_type;
resen : in std_ulogic := '0'
);
end;
architecture rtl of ahbtrace_mb is
signal tahbmiv : ahb_mst_in_vector_type(0 to 0);
signal tahbsiv : ahb_slv_in_vector_type(0 to 0);
begin
tahbmiv(0) <= tahbmi;
tahbsiv(0) <= tahbsi;
ahbt0 : ahbtrace_mmb
generic map (
hindex => hindex,
ioaddr => ioaddr,
iomask => iomask,
tech => tech,
irq => irq,
kbytes => kbytes,
bwidth => bwidth,
ahbfilt => ahbfilt,
ntrace => 1,
scantest => scantest,
exttimer => exttimer,
exten => exten)
port map(
rst => rst,
clk => clk,
ahbsi => ahbsi,
ahbso => ahbso,
tahbmiv => tahbmiv,
tahbsiv => tahbsiv,
timer => timer,
astat => astat,
resen => resen);
end;
| gpl-3.0 | d63116ecdb0fd7af62aae6f8b354ff87 | 0.568615 | 3.896468 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/maps/grpci2_phy_net.vhd | 1 | 41,186 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity grpci2_phy_net is
generic(
tech : integer := DEFMEMTECH;
oepol : integer := 0;
bypass : integer range 0 to 1 := 1;
netlist : integer := 0
);
port(
pciclk : in std_logic;
--pcii : in pci_in_type;
pcii_rst : in std_ulogic;
pcii_gnt : in std_ulogic;
pcii_idsel : in std_ulogic;
pcii_ad : in std_logic_vector(31 downto 0);
pcii_cbe : in std_logic_vector(3 downto 0);
pcii_frame : in std_ulogic;
pcii_irdy : in std_ulogic;
pcii_trdy : in std_ulogic;
pcii_devsel : in std_ulogic;
pcii_stop : in std_ulogic;
pcii_lock : in std_ulogic;
pcii_perr : in std_ulogic;
pcii_serr : in std_ulogic;
pcii_par : in std_ulogic;
pcii_host : in std_ulogic;
pcii_pci66 : in std_ulogic;
pcii_pme_status : in std_ulogic;
pcii_int : in std_logic_vector(3 downto 0);
--phyi : in grpci2_phy_in_type;
phyi_pcirstout : in std_logic;
phyi_pciasyncrst : in std_logic;
phyi_pcisoftrst : in std_logic_vector(2 downto 0);
phyi_pciinten : in std_logic_vector(3 downto 0);
phyi_m_request : in std_logic;
phyi_m_mabort : in std_logic;
phyi_pr_m_fstate : in std_logic_vector(1 downto 0); --pci_master_fifo_state_type;
--phyi_pr_m_cfifo : in pci_core_fifo_vector_type;
phyi_pr_m_cfifo_0_data : in std_logic_vector(31 downto 0);
phyi_pr_m_cfifo_0_last : in std_logic;
phyi_pr_m_cfifo_0_stlast : in std_logic;
phyi_pr_m_cfifo_0_hold : in std_logic;
phyi_pr_m_cfifo_0_valid : in std_logic;
phyi_pr_m_cfifo_0_err : in std_logic;
phyi_pr_m_cfifo_1_data : in std_logic_vector(31 downto 0);
phyi_pr_m_cfifo_1_last : in std_logic;
phyi_pr_m_cfifo_1_stlast : in std_logic;
phyi_pr_m_cfifo_1_hold : in std_logic;
phyi_pr_m_cfifo_1_valid : in std_logic;
phyi_pr_m_cfifo_1_err : in std_logic;
phyi_pr_m_cfifo_2_data : in std_logic_vector(31 downto 0);
phyi_pr_m_cfifo_2_last : in std_logic;
phyi_pr_m_cfifo_2_stlast : in std_logic;
phyi_pr_m_cfifo_2_hold : in std_logic;
phyi_pr_m_cfifo_2_valid : in std_logic;
phyi_pr_m_cfifo_2_err : in std_logic;
--phyi_pv_m_cfifo : in pci_core_fifo_vector_type;
phyi_pv_m_cfifo_0_data : in std_logic_vector(31 downto 0);
phyi_pv_m_cfifo_0_last : in std_logic;
phyi_pv_m_cfifo_0_stlast : in std_logic;
phyi_pv_m_cfifo_0_hold : in std_logic;
phyi_pv_m_cfifo_0_valid : in std_logic;
phyi_pv_m_cfifo_0_err : in std_logic;
phyi_pv_m_cfifo_1_data : in std_logic_vector(31 downto 0);
phyi_pv_m_cfifo_1_last : in std_logic;
phyi_pv_m_cfifo_1_stlast : in std_logic;
phyi_pv_m_cfifo_1_hold : in std_logic;
phyi_pv_m_cfifo_1_valid : in std_logic;
phyi_pv_m_cfifo_1_err : in std_logic;
phyi_pv_m_cfifo_2_data : in std_logic_vector(31 downto 0);
phyi_pv_m_cfifo_2_last : in std_logic;
phyi_pv_m_cfifo_2_stlast : in std_logic;
phyi_pv_m_cfifo_2_hold : in std_logic;
phyi_pv_m_cfifo_2_valid : in std_logic;
phyi_pv_m_cfifo_2_err : in std_logic;
phyi_pr_m_addr : in std_logic_vector(31 downto 0);
phyi_pr_m_cbe_data : in std_logic_vector(3 downto 0);
phyi_pr_m_cbe_cmd : in std_logic_vector(3 downto 0);
phyi_pr_m_first : in std_logic_vector(1 downto 0);
phyi_pv_m_term : in std_logic_vector(1 downto 0);
phyi_pr_m_ltimer : in std_logic_vector(7 downto 0);
phyi_pr_m_burst : in std_logic;
phyi_pr_m_abort : in std_logic_vector(0 downto 0);
phyi_pr_m_perren : in std_logic_vector(0 downto 0);
phyi_pr_m_done_fifo : in std_logic;
phyi_t_abort : in std_logic;
phyi_t_ready : in std_logic;
phyi_t_retry : in std_logic;
phyi_pr_t_state : in std_logic_vector(2 downto 0); --pci_target_state_type;
phyi_pv_t_state : in std_logic_vector(2 downto 0); --pci_target_state_type;
phyi_pr_t_fstate : in std_logic_vector(1 downto 0); --pci_target_fifo_state_type;
--phyi_pr_t_cfifo : in pci_core_fifo_vector_type;
phyi_pr_t_cfifo_0_data : in std_logic_vector(31 downto 0);
phyi_pr_t_cfifo_0_last : in std_logic;
phyi_pr_t_cfifo_0_stlast : in std_logic;
phyi_pr_t_cfifo_0_hold : in std_logic;
phyi_pr_t_cfifo_0_valid : in std_logic;
phyi_pr_t_cfifo_0_err : in std_logic;
phyi_pr_t_cfifo_1_data : in std_logic_vector(31 downto 0);
phyi_pr_t_cfifo_1_last : in std_logic;
phyi_pr_t_cfifo_1_stlast : in std_logic;
phyi_pr_t_cfifo_1_hold : in std_logic;
phyi_pr_t_cfifo_1_valid : in std_logic;
phyi_pr_t_cfifo_1_err : in std_logic;
phyi_pr_t_cfifo_2_data : in std_logic_vector(31 downto 0);
phyi_pr_t_cfifo_2_last : in std_logic;
phyi_pr_t_cfifo_2_stlast : in std_logic;
phyi_pr_t_cfifo_2_hold : in std_logic;
phyi_pr_t_cfifo_2_valid : in std_logic;
phyi_pr_t_cfifo_2_err : in std_logic;
phyi_pv_t_diswithout : in std_logic;
phyi_pr_t_stoped : in std_logic;
phyi_pr_t_lcount : in std_logic_vector(2 downto 0);
phyi_pr_t_first_word : in std_logic;
phyi_pr_t_cur_acc_0_read : in std_logic;
phyi_pv_t_hold_write : in std_logic;
phyi_pv_t_hold_reset : in std_logic;
phyi_pr_conf_comm_perren : in std_logic;
phyi_pr_conf_comm_serren : in std_logic;
--pcio : out pci_out_type;
pcio_aden : out std_ulogic;
pcio_vaden : out std_logic_vector(31 downto 0);
pcio_cbeen : out std_logic_vector(3 downto 0);
pcio_frameen : out std_ulogic;
pcio_irdyen : out std_ulogic;
pcio_trdyen : out std_ulogic;
pcio_devselen : out std_ulogic;
pcio_stopen : out std_ulogic;
pcio_ctrlen : out std_ulogic;
pcio_perren : out std_ulogic;
pcio_paren : out std_ulogic;
pcio_reqen : out std_ulogic;
pcio_locken : out std_ulogic;
pcio_serren : out std_ulogic;
pcio_inten : out std_ulogic;
pcio_vinten : out std_logic_vector(3 downto 0);
pcio_req : out std_ulogic;
pcio_ad : out std_logic_vector(31 downto 0);
pcio_cbe : out std_logic_vector(3 downto 0);
pcio_frame : out std_ulogic;
pcio_irdy : out std_ulogic;
pcio_trdy : out std_ulogic;
pcio_devsel : out std_ulogic;
pcio_stop : out std_ulogic;
pcio_perr : out std_ulogic;
pcio_serr : out std_ulogic;
pcio_par : out std_ulogic;
pcio_lock : out std_ulogic;
pcio_power_state : out std_logic_vector(1 downto 0);
pcio_pme_enable : out std_ulogic;
pcio_pme_clear : out std_ulogic;
pcio_int : out std_ulogic;
pcio_rst : out std_ulogic;
--phyo : out grpci2_phy_out_type
--phyo_pciv : out pci_in_type;
phyo_pciv_rst : out std_ulogic;
phyo_pciv_gnt : out std_ulogic;
phyo_pciv_idsel : out std_ulogic;
phyo_pciv_ad : out std_logic_vector(31 downto 0);
phyo_pciv_cbe : out std_logic_vector(3 downto 0);
phyo_pciv_frame : out std_ulogic;
phyo_pciv_irdy : out std_ulogic;
phyo_pciv_trdy : out std_ulogic;
phyo_pciv_devsel : out std_ulogic;
phyo_pciv_stop : out std_ulogic;
phyo_pciv_lock : out std_ulogic;
phyo_pciv_perr : out std_ulogic;
phyo_pciv_serr : out std_ulogic;
phyo_pciv_par : out std_ulogic;
phyo_pciv_host : out std_ulogic;
phyo_pciv_pci66 : out std_ulogic;
phyo_pciv_pme_status : out std_ulogic;
phyo_pciv_int : out std_logic_vector(3 downto 0);
phyo_pr_m_state : out std_logic_vector(2 downto 0); --pci_master_state_type;
phyo_pr_m_last : out std_logic_vector(1 downto 0);
phyo_pr_m_hold : out std_logic_vector(1 downto 0);
phyo_pr_m_term : out std_logic_vector(1 downto 0);
phyo_pr_t_hold : out std_logic_vector(0 downto 0);
phyo_pr_t_stop : out std_logic;
phyo_pr_t_abort : out std_logic;
phyo_pr_t_diswithout : out std_logic;
phyo_pr_t_addr_perr : out std_logic;
phyo_pcirsto : out std_logic_vector(0 downto 0);
--phyo_pr_po : out pci_reg_out_type;
phyo_pr_po_ad : out std_logic_vector(31 downto 0);
phyo_pr_po_aden : out std_logic_vector(31 downto 0);
phyo_pr_po_cbe : out std_logic_vector(3 downto 0);
phyo_pr_po_cbeen : out std_logic_vector(3 downto 0);
phyo_pr_po_frame : out std_logic;
phyo_pr_po_frameen : out std_logic;
phyo_pr_po_irdy : out std_logic;
phyo_pr_po_irdyen : out std_logic;
phyo_pr_po_trdy : out std_logic;
phyo_pr_po_trdyen : out std_logic;
phyo_pr_po_stop : out std_logic;
phyo_pr_po_stopen : out std_logic;
phyo_pr_po_devsel : out std_logic;
phyo_pr_po_devselen : out std_logic;
phyo_pr_po_par : out std_logic;
phyo_pr_po_paren : out std_logic;
phyo_pr_po_perr : out std_logic;
phyo_pr_po_perren : out std_logic;
phyo_pr_po_lock : out std_logic;
phyo_pr_po_locken : out std_logic;
phyo_pr_po_req : out std_logic;
phyo_pr_po_reqen : out std_logic;
phyo_pr_po_serren : out std_logic;
phyo_pr_po_inten : out std_logic;
phyo_pr_po_vinten : out std_logic_vector(3 downto 0);
--phyo_pio : out pci_in_type;
phyo_pio_rst : out std_ulogic;
phyo_pio_gnt : out std_ulogic;
phyo_pio_idsel : out std_ulogic;
phyo_pio_ad : out std_logic_vector(31 downto 0);
phyo_pio_cbe : out std_logic_vector(3 downto 0);
phyo_pio_frame : out std_ulogic;
phyo_pio_irdy : out std_ulogic;
phyo_pio_trdy : out std_ulogic;
phyo_pio_devsel : out std_ulogic;
phyo_pio_stop : out std_ulogic;
phyo_pio_lock : out std_ulogic;
phyo_pio_perr : out std_ulogic;
phyo_pio_serr : out std_ulogic;
phyo_pio_par : out std_ulogic;
phyo_pio_host : out std_ulogic;
phyo_pio_pci66 : out std_ulogic;
phyo_pio_pme_status : out std_ulogic;
phyo_pio_int : out std_logic_vector(3 downto 0);
--phyo_poo : out pci_reg_out_type;
phyo_poo_ad : out std_logic_vector(31 downto 0);
phyo_poo_aden : out std_logic_vector(31 downto 0);
phyo_poo_cbe : out std_logic_vector(3 downto 0);
phyo_poo_cbeen : out std_logic_vector(3 downto 0);
phyo_poo_frame : out std_logic;
phyo_poo_frameen : out std_logic;
phyo_poo_irdy : out std_logic;
phyo_poo_irdyen : out std_logic;
phyo_poo_trdy : out std_logic;
phyo_poo_trdyen : out std_logic;
phyo_poo_stop : out std_logic;
phyo_poo_stopen : out std_logic;
phyo_poo_devsel : out std_logic;
phyo_poo_devselen : out std_logic;
phyo_poo_par : out std_logic;
phyo_poo_paren : out std_logic;
phyo_poo_perr : out std_logic;
phyo_poo_perren : out std_logic;
phyo_poo_lock : out std_logic;
phyo_poo_locken : out std_logic;
phyo_poo_req : out std_logic;
phyo_poo_reqen : out std_logic;
phyo_poo_serren : out std_logic;
phyo_poo_inten : out std_logic;
phyo_poo_vinten : out std_logic_vector(3 downto 0)
);
end grpci2_phy_net;
architecture struct of grpci2_phy_net is
component grpci2_phy_rtax_bypass is
-- generic(
-- tech : integer := axcel;
-- oepol : integer := 1;
-- bypass : integer range 0 to 1 := 1;
-- netlist : integer := 1
-- scantest: integer := 0
-- );
port(
pciclk : in std_logic;
--pcii : in pci_in_type;
pcii_rst : in std_ulogic;
pcii_gnt : in std_ulogic;
pcii_idsel : in std_ulogic;
pcii_ad : in std_logic_vector(31 downto 0);
pcii_cbe : in std_logic_vector(3 downto 0);
pcii_frame : in std_ulogic;
pcii_irdy : in std_ulogic;
pcii_trdy : in std_ulogic;
pcii_devsel : in std_ulogic;
pcii_stop : in std_ulogic;
pcii_lock : in std_ulogic;
pcii_perr : in std_ulogic;
pcii_serr : in std_ulogic;
pcii_par : in std_ulogic;
pcii_host : in std_ulogic;
pcii_pci66 : in std_ulogic;
pcii_pme_status : in std_ulogic;
pcii_int : in std_logic_vector(3 downto 0);
--phyi : in grpci2_phy_in_type;
phyi_pcirstout : in std_logic;
phyi_pciasyncrst : in std_logic;
phyi_pcisoftrst : in std_logic_vector(2 downto 0);
phyi_pciinten : in std_logic_vector(3 downto 0);
phyi_m_request : in std_logic;
phyi_m_mabort : in std_logic;
phyi_pr_m_fstate : in std_logic_vector(1 downto 0); --pci_master_fifo_state_type;
--phyi_pr_m_cfifo : in pci_core_fifo_vector_type;
phyi_pr_m_cfifo_0_data : in std_logic_vector(31 downto 0);
phyi_pr_m_cfifo_0_last : in std_logic;
phyi_pr_m_cfifo_0_stlast : in std_logic;
phyi_pr_m_cfifo_0_hold : in std_logic;
phyi_pr_m_cfifo_0_valid : in std_logic;
phyi_pr_m_cfifo_0_err : in std_logic;
phyi_pr_m_cfifo_1_data : in std_logic_vector(31 downto 0);
phyi_pr_m_cfifo_1_last : in std_logic;
phyi_pr_m_cfifo_1_stlast : in std_logic;
phyi_pr_m_cfifo_1_hold : in std_logic;
phyi_pr_m_cfifo_1_valid : in std_logic;
phyi_pr_m_cfifo_1_err : in std_logic;
phyi_pr_m_cfifo_2_data : in std_logic_vector(31 downto 0);
phyi_pr_m_cfifo_2_last : in std_logic;
phyi_pr_m_cfifo_2_stlast : in std_logic;
phyi_pr_m_cfifo_2_hold : in std_logic;
phyi_pr_m_cfifo_2_valid : in std_logic;
phyi_pr_m_cfifo_2_err : in std_logic;
--phyi_pv_m_cfifo : in pci_core_fifo_vector_type;
phyi_pv_m_cfifo_0_data : in std_logic_vector(31 downto 0);
phyi_pv_m_cfifo_0_last : in std_logic;
phyi_pv_m_cfifo_0_stlast : in std_logic;
phyi_pv_m_cfifo_0_hold : in std_logic;
phyi_pv_m_cfifo_0_valid : in std_logic;
phyi_pv_m_cfifo_0_err : in std_logic;
phyi_pv_m_cfifo_1_data : in std_logic_vector(31 downto 0);
phyi_pv_m_cfifo_1_last : in std_logic;
phyi_pv_m_cfifo_1_stlast : in std_logic;
phyi_pv_m_cfifo_1_hold : in std_logic;
phyi_pv_m_cfifo_1_valid : in std_logic;
phyi_pv_m_cfifo_1_err : in std_logic;
phyi_pv_m_cfifo_2_data : in std_logic_vector(31 downto 0);
phyi_pv_m_cfifo_2_last : in std_logic;
phyi_pv_m_cfifo_2_stlast : in std_logic;
phyi_pv_m_cfifo_2_hold : in std_logic;
phyi_pv_m_cfifo_2_valid : in std_logic;
phyi_pv_m_cfifo_2_err : in std_logic;
phyi_pr_m_addr : in std_logic_vector(31 downto 0);
phyi_pr_m_cbe_data : in std_logic_vector(3 downto 0);
phyi_pr_m_cbe_cmd : in std_logic_vector(3 downto 0);
phyi_pr_m_first : in std_logic_vector(1 downto 0);
phyi_pv_m_term : in std_logic_vector(1 downto 0);
phyi_pr_m_ltimer : in std_logic_vector(7 downto 0);
phyi_pr_m_burst : in std_logic;
phyi_pr_m_abort : in std_logic_vector(0 downto 0);
phyi_pr_m_perren : in std_logic_vector(0 downto 0);
phyi_pr_m_done_fifo : in std_logic;
phyi_t_abort : in std_logic;
phyi_t_ready : in std_logic;
phyi_t_retry : in std_logic;
phyi_pr_t_state : in std_logic_vector(2 downto 0); --pci_target_state_type;
phyi_pv_t_state : in std_logic_vector(2 downto 0); --pci_target_state_type;
phyi_pr_t_fstate : in std_logic_vector(1 downto 0); --pci_target_fifo_state_type;
--phyi_pr_t_cfifo : in pci_core_fifo_vector_type;
phyi_pr_t_cfifo_0_data : in std_logic_vector(31 downto 0);
phyi_pr_t_cfifo_0_last : in std_logic;
phyi_pr_t_cfifo_0_stlast : in std_logic;
phyi_pr_t_cfifo_0_hold : in std_logic;
phyi_pr_t_cfifo_0_valid : in std_logic;
phyi_pr_t_cfifo_0_err : in std_logic;
phyi_pr_t_cfifo_1_data : in std_logic_vector(31 downto 0);
phyi_pr_t_cfifo_1_last : in std_logic;
phyi_pr_t_cfifo_1_stlast : in std_logic;
phyi_pr_t_cfifo_1_hold : in std_logic;
phyi_pr_t_cfifo_1_valid : in std_logic;
phyi_pr_t_cfifo_1_err : in std_logic;
phyi_pr_t_cfifo_2_data : in std_logic_vector(31 downto 0);
phyi_pr_t_cfifo_2_last : in std_logic;
phyi_pr_t_cfifo_2_stlast : in std_logic;
phyi_pr_t_cfifo_2_hold : in std_logic;
phyi_pr_t_cfifo_2_valid : in std_logic;
phyi_pr_t_cfifo_2_err : in std_logic;
phyi_pv_t_diswithout : in std_logic;
phyi_pr_t_stoped : in std_logic;
phyi_pr_t_lcount : in std_logic_vector(2 downto 0);
phyi_pr_t_first_word : in std_logic;
phyi_pr_t_cur_acc_0_read : in std_logic;
phyi_pv_t_hold_write : in std_logic;
phyi_pv_t_hold_reset : in std_logic;
phyi_pr_conf_comm_perren : in std_logic;
phyi_pr_conf_comm_serren : in std_logic;
--pcio : out pci_out_type;
pcio_aden : out std_ulogic;
pcio_vaden : out std_logic_vector(31 downto 0);
pcio_cbeen : out std_logic_vector(3 downto 0);
pcio_frameen : out std_ulogic;
pcio_irdyen : out std_ulogic;
pcio_trdyen : out std_ulogic;
pcio_devselen : out std_ulogic;
pcio_stopen : out std_ulogic;
pcio_ctrlen : out std_ulogic;
pcio_perren : out std_ulogic;
pcio_paren : out std_ulogic;
pcio_reqen : out std_ulogic;
pcio_locken : out std_ulogic;
pcio_serren : out std_ulogic;
pcio_inten : out std_ulogic;
pcio_vinten : out std_logic_vector(3 downto 0);
pcio_req : out std_ulogic;
pcio_ad : out std_logic_vector(31 downto 0);
pcio_cbe : out std_logic_vector(3 downto 0);
pcio_frame : out std_ulogic;
pcio_irdy : out std_ulogic;
pcio_trdy : out std_ulogic;
pcio_devsel : out std_ulogic;
pcio_stop : out std_ulogic;
pcio_perr : out std_ulogic;
pcio_serr : out std_ulogic;
pcio_par : out std_ulogic;
pcio_lock : out std_ulogic;
pcio_power_state : out std_logic_vector(1 downto 0);
pcio_pme_enable : out std_ulogic;
pcio_pme_clear : out std_ulogic;
pcio_int : out std_ulogic;
pcio_rst : out std_ulogic;
--phyo : out grpci2_phy_out_type
--phyo_pciv : out pci_in_type;
phyo_pciv_rst : out std_ulogic;
phyo_pciv_gnt : out std_ulogic;
phyo_pciv_idsel : out std_ulogic;
phyo_pciv_ad : out std_logic_vector(31 downto 0);
phyo_pciv_cbe : out std_logic_vector(3 downto 0);
phyo_pciv_frame : out std_ulogic;
phyo_pciv_irdy : out std_ulogic;
phyo_pciv_trdy : out std_ulogic;
phyo_pciv_devsel : out std_ulogic;
phyo_pciv_stop : out std_ulogic;
phyo_pciv_lock : out std_ulogic;
phyo_pciv_perr : out std_ulogic;
phyo_pciv_serr : out std_ulogic;
phyo_pciv_par : out std_ulogic;
phyo_pciv_host : out std_ulogic;
phyo_pciv_pci66 : out std_ulogic;
phyo_pciv_pme_status : out std_ulogic;
phyo_pciv_int : out std_logic_vector(3 downto 0);
phyo_pr_m_state : out std_logic_vector(2 downto 0); --pci_master_state_type;
phyo_pr_m_last : out std_logic_vector(1 downto 0);
phyo_pr_m_hold : out std_logic_vector(1 downto 0);
phyo_pr_m_term : out std_logic_vector(1 downto 0);
phyo_pr_t_hold : out std_logic_vector(0 downto 0);
phyo_pr_t_stop : out std_logic;
phyo_pr_t_abort : out std_logic;
phyo_pr_t_diswithout : out std_logic;
phyo_pr_t_addr_perr : out std_logic;
phyo_pcirsto : out std_logic_vector(0 downto 0);
--phyo_pr_po : out pci_reg_out_type;
phyo_pr_po_ad : out std_logic_vector(31 downto 0);
phyo_pr_po_aden : out std_logic_vector(31 downto 0);
phyo_pr_po_cbe : out std_logic_vector(3 downto 0);
phyo_pr_po_cbeen : out std_logic_vector(3 downto 0);
phyo_pr_po_frame : out std_logic;
phyo_pr_po_frameen : out std_logic;
phyo_pr_po_irdy : out std_logic;
phyo_pr_po_irdyen : out std_logic;
phyo_pr_po_trdy : out std_logic;
phyo_pr_po_trdyen : out std_logic;
phyo_pr_po_stop : out std_logic;
phyo_pr_po_stopen : out std_logic;
phyo_pr_po_devsel : out std_logic;
phyo_pr_po_devselen : out std_logic;
phyo_pr_po_par : out std_logic;
phyo_pr_po_paren : out std_logic;
phyo_pr_po_perr : out std_logic;
phyo_pr_po_perren : out std_logic;
phyo_pr_po_lock : out std_logic;
phyo_pr_po_locken : out std_logic;
phyo_pr_po_req : out std_logic;
phyo_pr_po_reqen : out std_logic;
phyo_pr_po_serren : out std_logic;
phyo_pr_po_inten : out std_logic;
phyo_pr_po_vinten : out std_logic_vector(3 downto 0);
--phyo_pio : out pci_in_type;
phyo_pio_rst : out std_ulogic;
phyo_pio_gnt : out std_ulogic;
phyo_pio_idsel : out std_ulogic;
phyo_pio_ad : out std_logic_vector(31 downto 0);
phyo_pio_cbe : out std_logic_vector(3 downto 0);
phyo_pio_frame : out std_ulogic;
phyo_pio_irdy : out std_ulogic;
phyo_pio_trdy : out std_ulogic;
phyo_pio_devsel : out std_ulogic;
phyo_pio_stop : out std_ulogic;
phyo_pio_lock : out std_ulogic;
phyo_pio_perr : out std_ulogic;
phyo_pio_serr : out std_ulogic;
phyo_pio_par : out std_ulogic;
phyo_pio_host : out std_ulogic;
phyo_pio_pci66 : out std_ulogic;
phyo_pio_pme_status : out std_ulogic;
phyo_pio_int : out std_logic_vector(3 downto 0);
--phyo_poo : out pci_reg_out_type;
phyo_poo_ad : out std_logic_vector(31 downto 0);
phyo_poo_aden : out std_logic_vector(31 downto 0);
phyo_poo_cbe : out std_logic_vector(3 downto 0);
phyo_poo_cbeen : out std_logic_vector(3 downto 0);
phyo_poo_frame : out std_logic;
phyo_poo_frameen : out std_logic;
phyo_poo_irdy : out std_logic;
phyo_poo_irdyen : out std_logic;
phyo_poo_trdy : out std_logic;
phyo_poo_trdyen : out std_logic;
phyo_poo_stop : out std_logic;
phyo_poo_stopen : out std_logic;
phyo_poo_devsel : out std_logic;
phyo_poo_devselen : out std_logic;
phyo_poo_par : out std_logic;
phyo_poo_paren : out std_logic;
phyo_poo_perr : out std_logic;
phyo_poo_perren : out std_logic;
phyo_poo_lock : out std_logic;
phyo_poo_locken : out std_logic;
phyo_poo_req : out std_logic;
phyo_poo_reqen : out std_logic;
phyo_poo_serren : out std_logic;
phyo_poo_inten : out std_logic;
phyo_poo_vinten : out std_logic_vector(3 downto 0)
);
end component;
begin
ax : if ((tech = axcel) or (tech = axdsp)) and (bypass = 1) generate
phy_bypass_rtax : grpci2_phy_rtax_bypass
port map(
pciclk => pciclk,
--pcii : in pci_in_type,
pcii_rst => pcii_rst,
pcii_gnt => pcii_gnt,
pcii_idsel => pcii_idsel,
pcii_ad => pcii_ad,
pcii_cbe => pcii_cbe,
pcii_frame => pcii_frame,
pcii_irdy => pcii_irdy,
pcii_trdy => pcii_trdy,
pcii_devsel => pcii_devsel,
pcii_stop => pcii_stop,
pcii_lock => pcii_lock,
pcii_perr => pcii_perr,
pcii_serr => pcii_serr,
pcii_par => pcii_par,
pcii_host => pcii_host,
pcii_pci66 => pcii_pci66,
pcii_pme_status => pcii_pme_status,
pcii_int => pcii_int,
--phyi : in grpci2_phy_in_type,
phyi_pcirstout => phyi_pcirstout,
phyi_pciasyncrst => phyi_pciasyncrst,
phyi_pcisoftrst => phyi_pcisoftrst,
phyi_pciinten => phyi_pciinten,
phyi_m_request => phyi_m_request,
phyi_m_mabort => phyi_m_mabort,
phyi_pr_m_fstate => phyi_pr_m_fstate,
phyi_pr_m_cfifo_0_data => phyi_pr_m_cfifo_0_data,
phyi_pr_m_cfifo_0_last => phyi_pr_m_cfifo_0_last,
phyi_pr_m_cfifo_0_stlast => phyi_pr_m_cfifo_0_stlast,
phyi_pr_m_cfifo_0_hold => phyi_pr_m_cfifo_0_hold,
phyi_pr_m_cfifo_0_valid => phyi_pr_m_cfifo_0_valid,
phyi_pr_m_cfifo_0_err => phyi_pr_m_cfifo_0_err,
phyi_pr_m_cfifo_1_data => phyi_pr_m_cfifo_1_data,
phyi_pr_m_cfifo_1_last => phyi_pr_m_cfifo_1_last,
phyi_pr_m_cfifo_1_stlast => phyi_pr_m_cfifo_1_stlast,
phyi_pr_m_cfifo_1_hold => phyi_pr_m_cfifo_1_hold,
phyi_pr_m_cfifo_1_valid => phyi_pr_m_cfifo_1_valid,
phyi_pr_m_cfifo_1_err => phyi_pr_m_cfifo_1_err,
phyi_pr_m_cfifo_2_data => phyi_pr_m_cfifo_2_data,
phyi_pr_m_cfifo_2_last => phyi_pr_m_cfifo_2_last,
phyi_pr_m_cfifo_2_stlast => phyi_pr_m_cfifo_2_stlast,
phyi_pr_m_cfifo_2_hold => phyi_pr_m_cfifo_2_hold,
phyi_pr_m_cfifo_2_valid => phyi_pr_m_cfifo_2_valid,
phyi_pr_m_cfifo_2_err => phyi_pr_m_cfifo_2_err,
phyi_pv_m_cfifo_0_data => phyi_pv_m_cfifo_0_data,
phyi_pv_m_cfifo_0_last => phyi_pv_m_cfifo_0_last,
phyi_pv_m_cfifo_0_stlast => phyi_pv_m_cfifo_0_stlast,
phyi_pv_m_cfifo_0_hold => phyi_pv_m_cfifo_0_hold,
phyi_pv_m_cfifo_0_valid => phyi_pv_m_cfifo_0_valid,
phyi_pv_m_cfifo_0_err => phyi_pv_m_cfifo_0_err,
phyi_pv_m_cfifo_1_data => phyi_pv_m_cfifo_1_data,
phyi_pv_m_cfifo_1_last => phyi_pv_m_cfifo_1_last,
phyi_pv_m_cfifo_1_stlast => phyi_pv_m_cfifo_1_stlast,
phyi_pv_m_cfifo_1_hold => phyi_pv_m_cfifo_1_hold,
phyi_pv_m_cfifo_1_valid => phyi_pv_m_cfifo_1_valid,
phyi_pv_m_cfifo_1_err => phyi_pv_m_cfifo_1_err,
phyi_pv_m_cfifo_2_data => phyi_pv_m_cfifo_2_data,
phyi_pv_m_cfifo_2_last => phyi_pv_m_cfifo_2_last,
phyi_pv_m_cfifo_2_stlast => phyi_pv_m_cfifo_2_stlast,
phyi_pv_m_cfifo_2_hold => phyi_pv_m_cfifo_2_hold,
phyi_pv_m_cfifo_2_valid => phyi_pv_m_cfifo_2_valid,
phyi_pv_m_cfifo_2_err => phyi_pv_m_cfifo_2_err,
phyi_pr_m_addr => phyi_pr_m_addr,
phyi_pr_m_cbe_data => phyi_pr_m_cbe_data,
phyi_pr_m_cbe_cmd => phyi_pr_m_cbe_cmd,
phyi_pr_m_first => phyi_pr_m_first,
phyi_pv_m_term => phyi_pv_m_term,
phyi_pr_m_ltimer => phyi_pr_m_ltimer,
phyi_pr_m_burst => phyi_pr_m_burst,
phyi_pr_m_abort => phyi_pr_m_abort,
phyi_pr_m_perren => phyi_pr_m_perren,
phyi_pr_m_done_fifo => phyi_pr_m_done_fifo,
phyi_t_abort => phyi_t_abort,
phyi_t_ready => phyi_t_ready,
phyi_t_retry => phyi_t_retry,
phyi_pr_t_state => phyi_pr_t_state,
phyi_pv_t_state => phyi_pv_t_state,
phyi_pr_t_fstate => phyi_pr_t_fstate,
phyi_pr_t_cfifo_0_data => phyi_pr_t_cfifo_0_data,
phyi_pr_t_cfifo_0_last => phyi_pr_t_cfifo_0_last,
phyi_pr_t_cfifo_0_stlast => phyi_pr_t_cfifo_0_stlast,
phyi_pr_t_cfifo_0_hold => phyi_pr_t_cfifo_0_hold,
phyi_pr_t_cfifo_0_valid => phyi_pr_t_cfifo_0_valid,
phyi_pr_t_cfifo_0_err => phyi_pr_t_cfifo_0_err,
phyi_pr_t_cfifo_1_data => phyi_pr_t_cfifo_1_data,
phyi_pr_t_cfifo_1_last => phyi_pr_t_cfifo_1_last,
phyi_pr_t_cfifo_1_stlast => phyi_pr_t_cfifo_1_stlast,
phyi_pr_t_cfifo_1_hold => phyi_pr_t_cfifo_1_hold,
phyi_pr_t_cfifo_1_valid => phyi_pr_t_cfifo_1_valid,
phyi_pr_t_cfifo_1_err => phyi_pr_t_cfifo_1_err,
phyi_pr_t_cfifo_2_data => phyi_pr_t_cfifo_2_data,
phyi_pr_t_cfifo_2_last => phyi_pr_t_cfifo_2_last,
phyi_pr_t_cfifo_2_stlast => phyi_pr_t_cfifo_2_stlast,
phyi_pr_t_cfifo_2_hold => phyi_pr_t_cfifo_2_hold,
phyi_pr_t_cfifo_2_valid => phyi_pr_t_cfifo_2_valid,
phyi_pr_t_cfifo_2_err => phyi_pr_t_cfifo_2_err,
phyi_pv_t_diswithout => phyi_pv_t_diswithout,
phyi_pr_t_stoped => phyi_pr_t_stoped,
phyi_pr_t_lcount => phyi_pr_t_lcount,
phyi_pr_t_first_word => phyi_pr_t_first_word,
phyi_pr_t_cur_acc_0_read => phyi_pr_t_cur_acc_0_read,
phyi_pv_t_hold_write => phyi_pv_t_hold_write,
phyi_pv_t_hold_reset => phyi_pv_t_hold_reset,
phyi_pr_conf_comm_perren => phyi_pr_conf_comm_perren,
phyi_pr_conf_comm_serren => phyi_pr_conf_comm_serren,
--pcio : out pci_out_type,
pcio_aden => pcio_aden,
pcio_vaden => pcio_vaden,
pcio_cbeen => pcio_cbeen,
pcio_frameen => pcio_frameen,
pcio_irdyen => pcio_irdyen,
pcio_trdyen => pcio_trdyen,
pcio_devselen => pcio_devselen,
pcio_stopen => pcio_stopen,
pcio_ctrlen => pcio_ctrlen,
pcio_perren => pcio_perren,
pcio_paren => pcio_paren,
pcio_reqen => pcio_reqen,
pcio_locken => pcio_locken,
pcio_serren => pcio_serren,
pcio_inten => pcio_inten,
pcio_vinten => pcio_vinten,
pcio_req => pcio_req,
pcio_ad => pcio_ad,
pcio_cbe => pcio_cbe,
pcio_frame => pcio_frame,
pcio_irdy => pcio_irdy,
pcio_trdy => pcio_trdy,
pcio_devsel => pcio_devsel,
pcio_stop => pcio_stop,
pcio_perr => pcio_perr,
pcio_serr => pcio_serr,
pcio_par => pcio_par,
pcio_lock => pcio_lock,
pcio_power_state => pcio_power_state,
pcio_pme_enable => pcio_pme_enable,
pcio_pme_clear => pcio_pme_clear,
pcio_int => pcio_int,
pcio_rst => pcio_rst,
--phyo : out grpci2_phy_out_type
phyo_pciv_rst => phyo_pciv_rst,
phyo_pciv_gnt => phyo_pciv_gnt,
phyo_pciv_idsel => phyo_pciv_idsel,
phyo_pciv_ad => phyo_pciv_ad,
phyo_pciv_cbe => phyo_pciv_cbe,
phyo_pciv_frame => phyo_pciv_frame,
phyo_pciv_irdy => phyo_pciv_irdy,
phyo_pciv_trdy => phyo_pciv_trdy,
phyo_pciv_devsel => phyo_pciv_devsel,
phyo_pciv_stop => phyo_pciv_stop,
phyo_pciv_lock => phyo_pciv_lock,
phyo_pciv_perr => phyo_pciv_perr,
phyo_pciv_serr => phyo_pciv_serr,
phyo_pciv_par => phyo_pciv_par,
phyo_pciv_host => phyo_pciv_host,
phyo_pciv_pci66 => phyo_pciv_pci66,
phyo_pciv_pme_status => phyo_pciv_pme_status,
phyo_pciv_int => phyo_pciv_int,
phyo_pr_m_state => phyo_pr_m_state,
phyo_pr_m_last => phyo_pr_m_last,
phyo_pr_m_hold => phyo_pr_m_hold,
phyo_pr_m_term => phyo_pr_m_term,
phyo_pr_t_hold => phyo_pr_t_hold,
phyo_pr_t_stop => phyo_pr_t_stop,
phyo_pr_t_abort => phyo_pr_t_abort,
phyo_pr_t_diswithout => phyo_pr_t_diswithout,
phyo_pr_t_addr_perr => phyo_pr_t_addr_perr,
phyo_pcirsto => phyo_pcirsto,
phyo_pr_po_ad => phyo_pr_po_ad,
phyo_pr_po_aden => phyo_pr_po_aden,
phyo_pr_po_cbe => phyo_pr_po_cbe,
phyo_pr_po_cbeen => phyo_pr_po_cbeen,
phyo_pr_po_frame => phyo_pr_po_frame,
phyo_pr_po_frameen => phyo_pr_po_frameen,
phyo_pr_po_irdy => phyo_pr_po_irdy,
phyo_pr_po_irdyen => phyo_pr_po_irdyen,
phyo_pr_po_trdy => phyo_pr_po_trdy,
phyo_pr_po_trdyen => phyo_pr_po_trdyen,
phyo_pr_po_stop => phyo_pr_po_stop,
phyo_pr_po_stopen => phyo_pr_po_stopen,
phyo_pr_po_devsel => phyo_pr_po_devsel,
phyo_pr_po_devselen => phyo_pr_po_devselen,
phyo_pr_po_par => phyo_pr_po_par,
phyo_pr_po_paren => phyo_pr_po_paren,
phyo_pr_po_perr => phyo_pr_po_perr,
phyo_pr_po_perren => phyo_pr_po_perren,
phyo_pr_po_lock => phyo_pr_po_lock,
phyo_pr_po_locken => phyo_pr_po_locken,
phyo_pr_po_req => phyo_pr_po_req,
phyo_pr_po_reqen => phyo_pr_po_reqen,
phyo_pr_po_serren => phyo_pr_po_serren,
phyo_pr_po_inten => phyo_pr_po_inten,
phyo_pr_po_vinten => phyo_pr_po_vinten,
phyo_pio_rst => phyo_pio_rst,
phyo_pio_gnt => phyo_pio_gnt,
phyo_pio_idsel => phyo_pio_idsel,
phyo_pio_ad => phyo_pio_ad,
phyo_pio_cbe => phyo_pio_cbe,
phyo_pio_frame => phyo_pio_frame,
phyo_pio_irdy => phyo_pio_irdy,
phyo_pio_trdy => phyo_pio_trdy,
phyo_pio_devsel => phyo_pio_devsel,
phyo_pio_stop => phyo_pio_stop,
phyo_pio_lock => phyo_pio_lock,
phyo_pio_perr => phyo_pio_perr,
phyo_pio_serr => phyo_pio_serr,
phyo_pio_par => phyo_pio_par,
phyo_pio_host => phyo_pio_host,
phyo_pio_pci66 => phyo_pio_pci66,
phyo_pio_pme_status => phyo_pio_pme_status,
phyo_pio_int => phyo_pio_int,
phyo_poo_ad => phyo_poo_ad,
phyo_poo_aden => phyo_poo_aden,
phyo_poo_cbe => phyo_poo_cbe,
phyo_poo_cbeen => phyo_poo_cbeen,
phyo_poo_frame => phyo_poo_frame,
phyo_poo_frameen => phyo_poo_frameen,
phyo_poo_irdy => phyo_poo_irdy,
phyo_poo_irdyen => phyo_poo_irdyen,
phyo_poo_trdy => phyo_poo_trdy,
phyo_poo_trdyen => phyo_poo_trdyen,
phyo_poo_stop => phyo_poo_stop,
phyo_poo_stopen => phyo_poo_stopen,
phyo_poo_devsel => phyo_poo_devsel,
phyo_poo_devselen => phyo_poo_devselen,
phyo_poo_par => phyo_poo_par,
phyo_poo_paren => phyo_poo_paren,
phyo_poo_perr => phyo_poo_perr,
phyo_poo_perren => phyo_poo_perren,
phyo_poo_lock => phyo_poo_lock,
phyo_poo_locken => phyo_poo_locken,
phyo_poo_req => phyo_poo_req,
phyo_poo_reqen => phyo_poo_reqen,
phyo_poo_serren => phyo_poo_serren,
phyo_poo_inten => phyo_poo_inten,
phyo_poo_vinten => phyo_poo_vinten
);
end generate;
-- pragma translate_off
nonet : if not (((tech = axcel) or (tech = axdsp)) and
(bypass = 1))
generate
err : process
begin
assert False report "ERROR : No pci_arb netlist available for this configuration!"
severity Failure;
wait;
end process;
end generate;
-- pragma translate_on
end struct;
| gpl-3.0 | bcbfe407de8257d0fa2d1f8b0af2ea0c | 0.503861 | 3.229768 | false | false | false | false |
freecores/cryptopan_core | tb/aes_encrypt_unit_tb.vhd | 1 | 3,768 | --
-- This file is part of the Crypto-PAn core (www.opencores.org).
--
-- Copyright (c) 2007 The University of Waikato, Hamilton, New Zealand.
-- Authors: Anthony Blake ([email protected])
--
-- All rights reserved.
--
-- This code has been developed by the University of Waikato WAND
-- research group. For further information please see http://www.wand.net.nz/
--
-- This source file is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This source is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with libtrace; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--
library ieee;
use ieee.std_logic_1164.all;
entity aes_encrypt_unit_tb is
end aes_encrypt_unit_tb;
architecture tb of aes_encrypt_unit_tb is
component aes_encrypt_unit
port (
key_in : in std_logic_vector(127 downto 0);
key_wren : in std_logic;
ready : out std_logic;
data_in : in std_logic_vector(127 downto 0);
data_wren : in std_logic;
data_dv : out std_logic;
data_out : out std_logic_vector(127 downto 0);
clk : in std_logic;
reset : in std_logic);
end component;
signal clk : std_logic;
signal reset : std_logic;
signal key_in : std_logic_vector(127 downto 0);
signal key_wren : std_logic;
signal ready : std_logic;
signal data_in : std_logic_vector(127 downto 0);
signal data_wren : std_logic;
signal data_dv : std_logic;
signal data_out : std_logic_vector(127 downto 0);
begin
CLKGEN: process
begin
clk <= '1';
wait for 5 ns;
clk <= '0';
wait for 5 ns;
end process CLKGEN;
CRYPT0: aes_encrypt_unit
port map (
key_in => key_in,
key_wren => key_wren,
ready => ready,
data_in => data_in,
data_wren => data_wren,
data_dv => data_dv,
data_out => data_out,
clk => clk,
reset => reset);
TESTBENCH: process
begin
reset <= '1';
data_in <= (others => '0');
key_in <= (others => '0');
data_wren <= '0';
key_wren <= '0';
wait for 50 ns;
reset <= '0';
wait for 20 ns;
key_in <= X"2b7e151628aed2a6abf7158809cf4f3c";
key_wren <= '1';
wait for 10 ns;
key_wren <= '0';
wait until ready='1';
wait for 40 ns;
data_in <= X"3243f6a8885a308d313198a2e0370734";
data_wren <= '1';
wait for 10 ns;
data_in <= X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA";
wait for 10 ns;
data_in <= X"BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB";
wait for 10 ns;
data_in <= X"CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC";
wait for 10 ns;
data_in <= X"DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD";
wait for 10 ns;
data_in <= X"3243f6a8885a308d313198a2e0370734";
wait for 10 ns;
data_in <= X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA";
wait for 10 ns;
data_in <= X"BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB";
wait for 10 ns;
data_in <= X"CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC";
wait for 10 ns;
data_in <= X"DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD";
wait for 10 ns;
data_in <= X"3243f6a8885a308d313198a2e0370734";
wait for 10 ns;
data_wren <= '0';
data_in <= (others => '0');
wait until data_dv='1';
wait;
end process TESTBENCH;
end tb;
| gpl-2.0 | 3e1d10491537c74f2de502ce35102710 | 0.632431 | 3.444241 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-asic/core_clock_mux.vhd | 1 | 2,836 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: core_clock_mux
-- File: core_clock_mux.vhd
-- Author: Fredrik Ringhage - Aeroflex Gaisler AB
-- Description: Clock muxes for LEONx ASIC
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.clkmux;
use techmap.gencomp.has_clkmux;
entity core_clock_mux is
generic(
tech : integer;
scantest : integer range 0 to 1 := 0
);
port(
clksel : in std_logic_vector(1 downto 0);
testen : in std_logic;
clkin : in std_logic;
clk1x : in std_logic;
clk2x : in std_logic;
clk4x : in std_logic;
clkout : out std_ulogic
);
end entity;
architecture rtl of core_clock_mux is
signal sel1x,sel2x,sel4x : std_logic;
signal lclkm1o,lclkm2o : std_logic;
signal selbypass,seltest : std_logic;
begin
-- Select testclk or not
seltest <= '1' when (testen = '1' and scantest = 1) else '0';
-- Bypass PLL
selbypass <= '1' when (clksel = "00" or seltest = '1') else '0';
-- Select PLL clock if not test or bypassed
sel1x <= '1' when (clksel(1 downto 0) = "01" and selbypass = '0' and seltest = '0') else '0';
sel2x <= '1' when (clksel(1 downto 0) = "10" and selbypass = '0' and seltest = '0') else '0';
sel4x <= '1' when (clksel(1 downto 0) = "11" and selbypass = '0' and seltest = '0') else '0';
-- Select output clock from PLL (or bypass PLL)
lpllclkm1 : clkmux generic map (tech => tech) port map (clkin ,clk1x,sel1x,lclkm1o);
lpllclkm2 : clkmux generic map (tech => tech) port map (lclkm1o,clk2x,sel2x,lclkm2o);
lpllclkm4 : clkmux generic map (tech => tech) port map (lclkm2o,clk4x,sel4x,clkout );
end architecture;
| gpl-3.0 | 30c7cb931aa4d5389e31a305427692f8 | 0.612482 | 3.571788 | false | true | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-gr-xc3s-1500/config.vhd | 1 | 9,241 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := spartan3;
constant CFG_MEMTECH : integer := spartan3;
constant CFG_PADTECH : integer := spartan3;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := spartan3;
constant CFG_CLKMUL : integer := (4);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (4);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 4;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- USB DSU
constant CFG_GRUSB_DCL : integer := 0;
constant CFG_GRUSB_DCL_UIFACE : integer := 1;
constant CFG_GRUSB_DCL_DW : integer := 8;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000008#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 1 + 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 0;
constant CFG_AHBSTATN : integer := 1;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 16;
-- CAN 2.0 interface
constant CFG_CAN : integer := 0;
constant CFG_CAN_NUM : integer := 1;
constant CFG_CANIO : integer := 16#0#;
constant CFG_CANIRQ : integer := 0;
constant CFG_CANSEPIRQ: integer := 0;
constant CFG_CAN_SYNCRST : integer := 0;
constant CFG_CANFT : integer := 0;
-- GR USB 2.0 Device Controller
constant CFG_GRUSBDC : integer := 0;
constant CFG_GRUSBDC_AIFACE : integer := 0;
constant CFG_GRUSBDC_UIFACE : integer := 1;
constant CFG_GRUSBDC_DW : integer := 8;
constant CFG_GRUSBDC_NEPI : integer := 1;
constant CFG_GRUSBDC_NEPO : integer := 1;
constant CFG_GRUSBDC_I0 : integer := 1024;
constant CFG_GRUSBDC_I1 : integer := 1024;
constant CFG_GRUSBDC_I2 : integer := 1024;
constant CFG_GRUSBDC_I3 : integer := 1024;
constant CFG_GRUSBDC_I4 : integer := 1024;
constant CFG_GRUSBDC_I5 : integer := 1024;
constant CFG_GRUSBDC_I6 : integer := 1024;
constant CFG_GRUSBDC_I7 : integer := 1024;
constant CFG_GRUSBDC_I8 : integer := 1024;
constant CFG_GRUSBDC_I9 : integer := 1024;
constant CFG_GRUSBDC_I10 : integer := 1024;
constant CFG_GRUSBDC_I11 : integer := 1024;
constant CFG_GRUSBDC_I12 : integer := 1024;
constant CFG_GRUSBDC_I13 : integer := 1024;
constant CFG_GRUSBDC_I14 : integer := 1024;
constant CFG_GRUSBDC_I15 : integer := 1024;
constant CFG_GRUSBDC_O0 : integer := 1024;
constant CFG_GRUSBDC_O1 : integer := 1024;
constant CFG_GRUSBDC_O2 : integer := 1024;
constant CFG_GRUSBDC_O3 : integer := 1024;
constant CFG_GRUSBDC_O4 : integer := 1024;
constant CFG_GRUSBDC_O5 : integer := 1024;
constant CFG_GRUSBDC_O6 : integer := 1024;
constant CFG_GRUSBDC_O7 : integer := 1024;
constant CFG_GRUSBDC_O8 : integer := 1024;
constant CFG_GRUSBDC_O9 : integer := 1024;
constant CFG_GRUSBDC_O10 : integer := 1024;
constant CFG_GRUSBDC_O11 : integer := 1024;
constant CFG_GRUSBDC_O12 : integer := 1024;
constant CFG_GRUSBDC_O13 : integer := 1024;
constant CFG_GRUSBDC_O14 : integer := 1024;
constant CFG_GRUSBDC_O15 : integer := 1024;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- UART 2
constant CFG_UART2_ENABLE : integer := 0;
constant CFG_UART2_FIFO : integer := 1;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- Spacewire interface
constant CFG_SPW_EN : integer := 0;
constant CFG_SPW_NUM : integer := 1;
constant CFG_SPW_AHBFIFO : integer := 4;
constant CFG_SPW_RXFIFO : integer := 16;
constant CFG_SPW_RMAP : integer := 0;
constant CFG_SPW_RMAPBUF : integer := 4;
constant CFG_SPW_RMAPCRC : integer := 0;
constant CFG_SPW_NETLIST : integer := 0;
constant CFG_SPW_FT : integer := 0;
constant CFG_SPW_GRSPW : integer := 2;
constant CFG_SPW_RXUNAL : integer := 0;
constant CFG_SPW_DMACHAN : integer := 1;
constant CFG_SPW_PORTS : integer := 1;
constant CFG_SPW_INPUT : integer := 2;
constant CFG_SPW_OUTPUT : integer := 0;
constant CFG_SPW_RTSAME : integer := 0;
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 1;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 1;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-3.0 | a2c52fbae0d048fef75fd12a2cb7124b | 0.654907 | 3.570711 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/gencomp/netcomp.vhd | 1 | 72,126 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: netcomp
-- File: netcomp.vhd
-- Author: Jiri Gaisler - Aeroflex Gaisler
-- Description: Declaration of netlists components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use work.gencomp.all;
package netcomp is
---------------------------------------------------------------------------
-- netlists ---------------------------------------------------------------
---------------------------------------------------------------------------
component grusbhc_net is
generic (
tech : integer := 0;
nports : integer range 1 to 15 := 1;
ehcgen : integer range 0 to 1 := 1;
uhcgen : integer range 0 to 1 := 1;
n_cc : integer range 1 to 15 := 1;
n_pcc : integer range 1 to 15 := 1;
prr : integer range 0 to 1 := 0;
portroute1 : integer := 0;
portroute2 : integer := 0;
endian_conv : integer range 0 to 1 := 1;
be_regs : integer range 0 to 1 := 0;
be_desc : integer range 0 to 1 := 0;
uhcblo : integer range 0 to 255 := 2;
bwrd : integer range 1 to 256 := 16;
utm_type : integer range 0 to 2 := 2;
vbusconf : integer := 3;
ramtest : integer range 0 to 1 := 0;
urst_time : integer := 250;
oepol : integer range 0 to 1 := 0;
scantest : integer range 0 to 1 := 0;
isfpga : integer range 0 to 1 := 1;
memsel : integer := 0;
syncprst : integer range 0 to 1 := 0;
sysfreq : integer := 65000;
pcidev : integer range 0 to 1 := 0;
debug : integer := 0;
debug_abits : integer := 12);
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel : in std_ulogic;
ehc_apbsi_penable : in std_ulogic;
ehc_apbsi_paddr : in std_logic_vector(31 downto 0);
ehc_apbsi_pwrite : in std_ulogic;
ehc_apbsi_pwdata : in std_logic_vector(31 downto 0);
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata : out std_logic_vector(31 downto 0);
ehc_apbso_pirq : out std_ulogic;
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant : in std_logic_vector(n_cc*uhcgen downto 0);
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel : in std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbsi_haddr : in std_logic_vector(31 downto 0);
uhc_ahbsi_hwrite : in std_ulogic;
uhc_ahbsi_htrans : in std_logic_vector(1 downto 0);
uhc_ahbsi_hsize : in std_logic_vector(2 downto 0);
uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0);
uhc_ahbsi_hready : in std_ulogic;
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq : out std_ulogic;
ehc_ahbmo_hlock : out std_ulogic;
ehc_ahbmo_htrans : out std_logic_vector(1 downto 0);
ehc_ahbmo_haddr : out std_logic_vector(31 downto 0);
ehc_ahbmo_hwrite : out std_ulogic;
ehc_ahbmo_hsize : out std_logic_vector(2 downto 0);
ehc_ahbmo_hburst : out std_logic_vector(2 downto 0);
ehc_ahbmo_hprot : out std_logic_vector(3 downto 0);
ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0);
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_hlock : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_htrans : out std_logic_vector((n_cc*2)*uhcgen downto 1*uhcgen);
uhc_ahbmo_haddr : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hwrite : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_hsize : out std_logic_vector((n_cc*3)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hburst : out std_logic_vector((n_cc*3)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hprot : out std_logic_vector((n_cc*4)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hwdata : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbso_hresp : out std_logic_vector((n_cc*2)*uhcgen downto 1*uhcgen);
uhc_ahbso_hrdata : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
uhc_ahbso_hsplit : out std_logic_vector((n_cc*16)*uhcgen downto 1*uhcgen);
uhc_ahbso_hirq : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
-- grusb_out_type_vector unwrapped
xcvrsel : out std_logic_vector(((nports*2)-1) downto 0);
termsel : out std_logic_vector((nports-1) downto 0);
opmode : out std_logic_vector(((nports*2)-1) downto 0);
txvalid : out std_logic_vector((nports-1) downto 0);
drvvbus : out std_logic_vector((nports-1) downto 0);
dataho : out std_logic_vector(((nports*8)-1) downto 0);
validho : out std_logic_vector((nports-1) downto 0);
stp : out std_logic_vector((nports-1) downto 0);
datao : out std_logic_vector(((nports*8)-1) downto 0);
utm_rst : out std_logic_vector((nports-1) downto 0);
dctrlo : out std_logic_vector((nports-1) downto 0);
suspendm : out std_ulogic;
dbus16_8 : out std_ulogic;
dppulldown : out std_ulogic;
dmpulldown : out std_ulogic;
idpullup : out std_ulogic;
dischrgvbus : out std_ulogic;
chrgvbus : out std_ulogic;
txbitstuffenable : out std_ulogic;
txbitstuffenableh : out std_ulogic;
fslsserialmode : out std_ulogic;
txenablen : out std_ulogic;
txdat : out std_ulogic;
txse0 : out std_ulogic;
-- grusb_in_type_vector unwrapped
linestate : in std_logic_vector(((nports*2)-1) downto 0);
txready : in std_logic_vector((nports-1) downto 0);
rxvalid : in std_logic_vector((nports-1) downto 0);
rxactive : in std_logic_vector((nports-1) downto 0);
rxerror : in std_logic_vector((nports-1) downto 0);
vbusvalid : in std_logic_vector((nports-1) downto 0);
datahi : in std_logic_vector(((nports*8)-1) downto 0);
validhi : in std_logic_vector((nports-1) downto 0);
hostdisc : in std_logic_vector((nports-1) downto 0);
nxt : in std_logic_vector((nports-1) downto 0);
dir : in std_logic_vector((nports-1) downto 0);
datai : in std_logic_vector(((nports*8)-1) downto 0);
urstdrive : in std_logic_vector((nports-1) downto 0);
-- EHC transaction buffer signals
mbc20_tb_addr : out std_logic_vector(8 downto 0);
mbc20_tb_data : out std_logic_vector(31 downto 0);
mbc20_tb_en : out std_ulogic;
mbc20_tb_wel : out std_ulogic;
mbc20_tb_weh : out std_ulogic;
tb_mbc20_data : in std_logic_vector(31 downto 0);
pe20_tb_addr : out std_logic_vector(8 downto 0);
pe20_tb_data : out std_logic_vector(31 downto 0);
pe20_tb_en : out std_ulogic;
pe20_tb_wel : out std_ulogic;
pe20_tb_weh : out std_ulogic;
tb_pe20_data : in std_logic_vector(31 downto 0);
-- EHC packet buffer signals
mbc20_pb_addr : out std_logic_vector(8 downto 0);
mbc20_pb_data : out std_logic_vector(31 downto 0);
mbc20_pb_en : out std_ulogic;
mbc20_pb_we : out std_ulogic;
pb_mbc20_data : in std_logic_vector(31 downto 0);
sie20_pb_addr : out std_logic_vector(8 downto 0);
sie20_pb_data : out std_logic_vector(31 downto 0);
sie20_pb_en : out std_ulogic;
sie20_pb_we : out std_ulogic;
pb_sie20_data : in std_logic_vector(31 downto 0);
-- UHC packet buffer signals
sie11_pb_addr : out std_logic_vector((n_cc*9)*uhcgen downto 1*uhcgen);
sie11_pb_data : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
sie11_pb_en : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
sie11_pb_we : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
pb_sie11_data : in std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
mbc11_pb_addr : out std_logic_vector((n_cc*9)*uhcgen downto 1*uhcgen);
mbc11_pb_data : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
mbc11_pb_en : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
mbc11_pb_we : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
pb_mbc11_data : in std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
bufsel : out std_ulogic;
-- scan signals
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic;
-- debug signals
debug_raddr : out std_logic_vector(15 downto 0);
debug_waddr : out std_logic_vector(15 downto 0);
debug_wdata : out std_logic_vector(31 downto 0);
debug_we : out std_ulogic;
debug_rdata : in std_logic_vector(31 downto 0));
end component;
component grspwc_net
generic(
tech : integer := 0;
sysfreq : integer := 40000;
usegen : integer range 0 to 1 := 1;
nsync : integer range 1 to 2 := 1;
rmap : integer range 0 to 2 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 32 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
scantest : integer range 0 to 1 := 0;
nodeaddr : integer range 0 to 255 := 254;
destkey : integer range 0 to 255 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
d : in std_logic_vector(1 downto 0);
nd : in std_logic_vector(9 downto 0);
dconnect : in std_logic_vector(3 downto 0);
--spw out
do : out std_logic_vector(1 downto 0);
so : out std_logic_vector(1 downto 0);
rxrsto : out std_ulogic;
--time iface
tickin : in std_ulogic;
tickout : out std_ulogic;
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
dcrstval : in std_logic_vector(9 downto 0);
timerrstval : in std_logic_vector(11 downto 0);
--rmapen
rmapen : in std_ulogic;
rmapnodeaddr : in std_logic_vector(7 downto 0);
--clk bufs
rxclki : in std_logic_vector(1 downto 0);
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(4 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(4 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(4 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(4 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--nchar fifo
ncrenable : out std_ulogic;
ncraddress : out std_logic_vector(5 downto 0);
ncwrite : out std_ulogic;
ncwdata : out std_logic_vector(8 downto 0);
ncwaddress : out std_logic_vector(5 downto 0);
ncrdata : in std_logic_vector(8 downto 0);
--rmap buf
rmrenable : out std_ulogic;
rmraddress : out std_logic_vector(7 downto 0);
rmwrite : out std_ulogic;
rmwdata : out std_logic_vector(7 downto 0);
rmwaddress : out std_logic_vector(7 downto 0);
rmrdata : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testclk : in std_ulogic := '0';
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0'
);
end component;
component grspwc2_net is
generic(
rmap : integer range 0 to 2 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 32 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
scantest : integer range 0 to 1 := 0;
ports : integer range 1 to 2 := 1;
dmachan : integer range 1 to 4 := 1;
tech : integer;
input_type : integer range 0 to 4 := 0;
output_type : integer range 0 to 2 := 0;
rxtx_sameclk : integer range 0 to 1 := 0;
nodeaddr : integer range 0 to 255 := 254;
destkey : integer range 0 to 255 := 0;
interruptdist : integer range 0 to 32 := 0;
intscalerbits : integer range 0 to 31 := 0;
intisrtimerbits : integer range 0 to 31 := 0;
intiatimerbits : integer range 0 to 31 := 0;
intctimerbits : integer range 0 to 31 := 0;
tickinasync : integer range 0 to 1 := 0;
pnp : integer range 0 to 2 := 0;
pnpvendid : integer range 0 to 16#FFFF# := 0;
pnpprodid : integer range 0 to 16#FFFF# := 0;
pnpmajorver : integer range 0 to 16#FF# := 0;
pnpminorver : integer range 0 to 16#FF# := 0;
pnppatch : integer range 0 to 16#FF# := 0;
num_txdesc : integer range 64 to 512 := 64;
num_rxdesc : integer range 128 to 1024 := 128
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxclk : in std_logic_vector(1 downto 0);
txclk : in std_ulogic;
txclkn : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
d : in std_logic_vector(3 downto 0);
dv : in std_logic_vector(3 downto 0);
dconnect : in std_logic_vector(3 downto 0);
--spw out
do : out std_logic_vector(3 downto 0);
so : out std_logic_vector(3 downto 0);
--time iface
tickin : in std_logic;
tickinraw : in std_logic;
timein : in std_logic_vector(7 downto 0);
tickindone : out std_logic;
tickout : out std_logic;
tickoutraw : out std_logic;
timeout : out std_logic_vector(7 downto 0);
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
dcrstval : in std_logic_vector(9 downto 0);
timerrstval : in std_logic_vector(11 downto 0);
--rmapen
rmapen : in std_ulogic;
rmapnodeaddr : in std_logic_vector(7 downto 0);
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(5 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(5 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(5 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(5 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--nchar fifo
ncrenable : out std_ulogic;
ncraddress : out std_logic_vector(5 downto 0);
ncwrite : out std_ulogic;
ncwdata : out std_logic_vector(9 downto 0);
ncwaddress : out std_logic_vector(5 downto 0);
ncrdata : in std_logic_vector(9 downto 0);
--rmap buf
rmrenable : out std_ulogic;
rmraddress : out std_logic_vector(7 downto 0);
rmwrite : out std_ulogic;
rmwdata : out std_logic_vector(7 downto 0);
rmwaddress : out std_logic_vector(7 downto 0);
rmrdata : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testclk : in std_ulogic;
testrst : in std_logic;
testen : in std_logic;
rxdav : out std_logic;
rxdataout : out std_logic_vector(8 downto 0);
loopback : out std_logic;
-- interrupt dist. default values
intpreload : in std_logic_vector(30 downto 0);
inttreload : in std_logic_vector(30 downto 0);
intiareload : in std_logic_vector(30 downto 0);
intcreload : in std_logic_vector(30 downto 0);
irqtxdefault : in std_logic_vector(4 downto 0);
--SpW PnP enable
pnpen : in std_ulogic;
pnpuvendid : in std_logic_vector(15 downto 0);
pnpuprodid : in std_logic_vector(15 downto 0);
pnpusn : in std_logic_vector(31 downto 0)
);
end component;
component grlfpw_net
generic (tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 1;
disas : integer range 0 to 2 := 0;
pipe : integer range 0 to 2 := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(31 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(31 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0)
);
end component;
component grfpw_net
generic (tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 2 := 1;
disas : integer range 0 to 2 := 0;
pipe : integer range 0 to 2 := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(31 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(31 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0)
);
end component;
component leon3_net
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 63 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0;
pwd : integer range 0 to 2 := 2;
svt : integer range 0 to 1 := 1;
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0;
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
cached : integer := 0;
clk2x : integer := 1;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0;
rex : integer range 0 to 1 := 0;
altwin : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic; -- free-running clock
gclk2 : in std_ulogic; -- gated 2x clock
gfclk2 : in std_ulogic; -- gated 2x FPU clock
clk2 : in std_ulogic; -- free-running 2x clock
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
-- ahbso : in ahb_slv_out_vector;
irqi_irl : in std_logic_vector(3 downto 0);
irqi_resume : in std_ulogic;
irqi_rstrun : in std_ulogic;
irqi_rstvec : in std_logic_vector(31 downto 12);
irqi_index : in std_logic_vector(3 downto 0);
irqi_pwdsetaddr : in std_ulogic;
irqi_pwdnewaddr : in std_logic_vector(31 downto 2);
irqi_forceerr : in std_ulogic;
irqo_intack : out std_ulogic;
irqo_irl : out std_logic_vector(3 downto 0);
irqo_pwd : out std_ulogic;
irqo_fpen : out std_ulogic;
irqo_err : out std_ulogic;
dbgi_dsuen : in std_ulogic; -- DSU enable
dbgi_denable : in std_ulogic; -- diagnostic register access enablee
dbgi_dbreak : in std_ulogic; -- debug break-in
dbgi_step : in std_ulogic; -- single step
dbgi_halt : in std_ulogic; -- halt processor
dbgi_reset : in std_ulogic; -- reset processor
dbgi_dwrite : in std_ulogic; -- read/write
dbgi_daddr : in std_logic_vector(23 downto 2); -- diagnostic address
dbgi_ddata : in std_logic_vector(31 downto 0); -- diagnostic data
dbgi_btrapa : in std_ulogic; -- break on IU trap
dbgi_btrape : in std_ulogic; -- break on IU trap
dbgi_berror : in std_ulogic; -- break on IU error mode
dbgi_bwatch : in std_ulogic; -- break on IU watchpoint
dbgi_bsoft : in std_ulogic; -- break on software breakpoint (TA 1)
dbgi_tenable : in std_ulogic;
dbgi_timer : in std_logic_vector(30 downto 0);
dbgo_data : out std_logic_vector(31 downto 0);
dbgo_crdy : out std_ulogic;
dbgo_dsu : out std_ulogic;
dbgo_dsumode : out std_ulogic;
dbgo_error : out std_ulogic;
dbgo_halt : out std_ulogic;
dbgo_pwd : out std_ulogic;
dbgo_idle : out std_ulogic;
dbgo_ipend : out std_ulogic;
dbgo_icnt : out std_ulogic;
dbgo_fcnt : out std_ulogic;
dbgo_optype : out std_logic_vector(5 downto 0); -- instruction type
dbgo_bpmiss : out std_ulogic; -- branch predict miss
dbgo_istat_cmiss : out std_ulogic;
dbgo_istat_tmiss : out std_ulogic;
dbgo_istat_chold : out std_ulogic;
dbgo_istat_mhold : out std_ulogic;
dbgo_dstat_cmiss : out std_ulogic;
dbgo_dstat_tmiss : out std_ulogic;
dbgo_dstat_chold : out std_ulogic;
dbgo_dstat_mhold : out std_ulogic;
dbgo_wbhold : out std_ulogic; -- write buffer hold
dbgo_su : out std_ulogic;
-- fpui : out grfpu_in_type;
-- fpuo : in grfpu_out_type;
clken : in std_ulogic
);
end component;
component ssrctrl_net
generic (
tech: Integer := 0;
bus16: Integer := 1);
port (
rst: in Std_Logic;
clk: in Std_Logic;
n_ahbsi_hsel: in Std_Logic_Vector(0 to 15);
n_ahbsi_haddr: in Std_Logic_Vector(31 downto 0);
n_ahbsi_hwrite: in Std_Logic;
n_ahbsi_htrans: in Std_Logic_Vector(1 downto 0);
n_ahbsi_hsize: in Std_Logic_Vector(2 downto 0);
n_ahbsi_hburst: in Std_Logic_Vector(2 downto 0);
n_ahbsi_hwdata: in Std_Logic_Vector(31 downto 0);
n_ahbsi_hprot: in Std_Logic_Vector(3 downto 0);
n_ahbsi_hready: in Std_Logic;
n_ahbsi_hmaster: in Std_Logic_Vector(3 downto 0);
n_ahbsi_hmastlock:in Std_Logic;
n_ahbsi_hmbsel: in Std_Logic_Vector(0 to 3);
n_ahbsi_hirq: in Std_Logic_Vector(31 downto 0);
n_ahbso_hready: out Std_Logic;
n_ahbso_hresp: out Std_Logic_Vector(1 downto 0);
n_ahbso_hrdata: out Std_Logic_Vector(31 downto 0);
n_ahbso_hsplit: out Std_Logic_Vector(15 downto 0);
n_ahbso_hirq: out Std_Logic_Vector(31 downto 0);
n_apbi_psel: in Std_Logic_Vector(0 to 15);
n_apbi_penable: in Std_Logic;
n_apbi_paddr: in Std_Logic_Vector(31 downto 0);
n_apbi_pwrite: in Std_Logic;
n_apbi_pwdata: in Std_Logic_Vector(31 downto 0);
n_apbi_pirq: in Std_Logic_Vector(31 downto 0);
n_apbo_prdata: out Std_Logic_Vector(31 downto 0);
n_apbo_pirq: out Std_Logic_Vector(31 downto 0);
n_sri_data: in Std_Logic_Vector(31 downto 0);
n_sri_brdyn: in Std_Logic;
n_sri_bexcn: in Std_Logic;
n_sri_writen: in Std_Logic;
n_sri_wrn: in Std_Logic_Vector(3 downto 0);
n_sri_bwidth: in Std_Logic_Vector(1 downto 0);
n_sri_sd: in Std_Logic_Vector(63 downto 0);
n_sri_cb: in Std_Logic_Vector(7 downto 0);
n_sri_scb: in Std_Logic_Vector(7 downto 0);
n_sri_edac: in Std_Logic;
n_sro_address: out Std_Logic_Vector(31 downto 0);
n_sro_data: out Std_Logic_Vector(31 downto 0);
n_sro_sddata: out Std_Logic_Vector(63 downto 0);
n_sro_ramsn: out Std_Logic_Vector(7 downto 0);
n_sro_ramoen: out Std_Logic_Vector(7 downto 0);
n_sro_ramn: out Std_Logic;
n_sro_romn: out Std_Logic;
n_sro_mben: out Std_Logic_Vector(3 downto 0);
n_sro_iosn: out Std_Logic;
n_sro_romsn: out Std_Logic_Vector(7 downto 0);
n_sro_oen: out Std_Logic;
n_sro_writen: out Std_Logic;
n_sro_wrn: out Std_Logic_Vector(3 downto 0);
n_sro_bdrive: out Std_Logic_Vector(3 downto 0);
n_sro_vbdrive: out Std_Logic_Vector(31 downto 0);
n_sro_svbdrive: out Std_Logic_Vector(63 downto 0);
n_sro_read: out Std_Logic;
n_sro_sa: out Std_Logic_Vector(14 downto 0);
n_sro_cb: out Std_Logic_Vector(7 downto 0);
n_sro_scb: out Std_Logic_Vector(7 downto 0);
n_sro_vcdrive: out Std_Logic_Vector(7 downto 0);
n_sro_svcdrive: out Std_Logic_Vector(7 downto 0);
n_sro_ce: out Std_Logic);
end component;
component ftsrctrl_net
generic (
hindex : integer := 0;
romaddr : integer := 0;
rommask : integer := 16#ff0#;
ramaddr : integer := 16#400#;
rammask : integer := 16#ff0#;
ioaddr : integer := 16#200#;
iomask : integer := 16#ff0#;
ramws : integer := 0;
romws : integer := 2;
iows : integer := 2;
rmw : integer := 0;
srbanks : integer range 1 to 8 := 1;
banksz : integer range 0 to 15 := 15;
rombanks : integer range 1 to 8 := 1;
rombanksz : integer range 0 to 15 := 15;
rombankszdef : integer range 0 to 15 := 15;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
edacen : integer range 0 to 1 := 1;
errcnt : integer range 0 to 1 := 0;
cntbits : integer range 1 to 8 := 1;
wsreg : integer := 0;
oepol : integer := 0;
prom8en : integer := 0;
netlist : integer := 0;
tech : integer := 0
);
port (
rst: in Std_ULogic;
clk: in Std_ULogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
sri_data: in Std_Logic_Vector(31 downto 0); -- Data bus address
sri_brdyn: in Std_Logic;
sri_bexcn: in Std_Logic;
sri_writen: in Std_Logic;
sri_wrn: in Std_Logic_Vector(3 downto 0);
sri_bwidth: in Std_Logic_Vector(1 downto 0);
sri_sd: in Std_Logic_Vector(63 downto 0);
sri_cb: in Std_Logic_Vector(15 downto 0);
sri_scb: in Std_Logic_Vector(15 downto 0);
sri_edac: in Std_Logic;
sro_address: out Std_Logic_Vector(31 downto 0);
sro_data: out Std_Logic_Vector(31 downto 0);
sro_sddata: out Std_Logic_Vector(63 downto 0);
sro_ramsn: out Std_Logic_Vector(7 downto 0);
sro_ramoen: out Std_Logic_Vector(7 downto 0);
sro_ramn: out Std_ULogic;
sro_romn: out Std_ULogic;
sro_mben: out Std_Logic_Vector(3 downto 0);
sro_iosn: out Std_Logic;
sro_romsn: out Std_Logic_Vector(7 downto 0);
sro_oen: out Std_Logic;
sro_writen: out Std_Logic;
sro_wrn: out Std_Logic_Vector(3 downto 0);
sro_bdrive: out Std_Logic_Vector(3 downto 0);
sro_vbdrive: out Std_Logic_Vector(31 downto 0); --vector bus drive
sro_svbdrive: out Std_Logic_Vector(63 downto 0); --vector bus drive sdram
sro_read: out Std_Logic;
sro_sa: out Std_Logic_Vector(14 downto 0);
sro_cb: out Std_Logic_Vector(15 downto 0);
sro_scb: out Std_Logic_Vector(15 downto 0);
sro_vcdrive: out Std_Logic_Vector(15 downto 0); --vector bus drive cb
sro_svcdrive: out Std_Logic_Vector(15 downto 0); --vector bus drive cb sdram
sro_ce: out Std_ULogic;
sdo_sdcke: out Std_Logic_Vector( 1 downto 0); -- clk en
sdo_sdcsn: out Std_Logic_Vector( 1 downto 0); -- chip sel
sdo_sdwen: out Std_ULogic; -- write en
sdo_rasn: out Std_ULogic; -- row addr stb
sdo_casn: out Std_ULogic; -- col addr stb
sdo_dqm: out Std_Logic_Vector(15 downto 0); -- data i/o mask
sdo_bdrive: out Std_ULogic; -- bus drive
sdo_qdrive: out Std_ULogic; -- bus drive
sdo_vbdrive: out Std_Logic_Vector(31 downto 0); -- vector bus drive
sdo_address: out Std_Logic_Vector(16 downto 2); -- address out
sdo_data: out Std_Logic_Vector(127 downto 0); -- data out
sdo_cb: out Std_Logic_Vector(15 downto 0);
sdo_ce: out Std_ULogic;
sdo_ba: out Std_Logic_Vector(2 downto 0)); -- bank address
end component;
component grlfpw4_net
generic (tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 1;
disas : integer range 0 to 2 := 0;
pipe : integer range 0 to 2 := 0;
wrt : integer range 0 to 2 := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(63 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(63 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0)
);
end component;
component grfpw4_net
generic (tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 2 := 1;
disas : integer range 0 to 2 := 0;
pipe : integer range 0 to 2 := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
fpuclk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(63 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(63 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0)
);
end component;
component spictrl_net
generic (
tech : integer range 0 to NTECH := 0;
fdepth : integer range 1 to 7 := 1;
slvselen : integer range 0 to 1 := 0;
slvselsz : integer range 1 to 32 := 1;
oepol : integer range 0 to 1 := 0;
odmode : integer range 0 to 1 := 0;
automode : integer range 0 to 1 := 0;
acntbits : integer range 1 to 32 := 32;
aslvsel : integer range 0 to 1 := 0;
twen : integer range 0 to 1 := 1;
maxwlen : integer range 0 to 15 := 0;
automask0 : integer := 0;
automask1 : integer := 0;
automask2 : integer := 0;
automask3 : integer := 0);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
apbi_psel : in std_ulogic;
apbi_penable : in std_ulogic;
apbi_paddr : in std_logic_vector(31 downto 0);
apbi_pwrite : in std_ulogic;
apbi_pwdata : in std_logic_vector(31 downto 0);
apbi_testen : in std_ulogic;
apbi_testrst : in std_ulogic;
apbi_scanen : in std_ulogic;
apbi_testoen : in std_ulogic;
apbo_prdata : out std_logic_vector(31 downto 0);
apbo_pirq : out std_ulogic;
spii_miso : in std_ulogic;
spii_mosi : in std_ulogic;
spii_sck : in std_ulogic;
spii_spisel : in std_ulogic;
spii_astart : in std_ulogic;
spii_cstart : in std_ulogic;
spio_miso : out std_ulogic;
spio_misooen : out std_ulogic;
spio_mosi : out std_ulogic;
spio_mosioen : out std_ulogic;
spio_sck : out std_ulogic;
spio_sckoen : out std_ulogic;
spio_enable : out std_ulogic;
spio_astart : out std_ulogic;
spio_aready : out std_ulogic;
slvsel : out std_logic_vector((slvselsz-1) downto 0));
end component;
component leon4_net
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 31 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
cached : integer := 0;
scantest : integer := 0
);
port (
clk : in std_ulogic;
gclk : in std_ulogic;
hclken : in std_ulogic;
rstn : in std_ulogic;
ahbix : in ahb_mst_in_type;
ahbox : out ahb_mst_out_type;
ahbsix : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi_irl : in std_logic_vector(3 downto 0);
irqi_resume : in std_ulogic;
irqi_rstrun : in std_ulogic;
irqi_rstvec : in std_logic_vector(31 downto 12);
irqi_index : in std_logic_vector(3 downto 0);
irqi_pwdsetaddr : in std_ulogic;
irqi_pwdnewaddr : in std_logic_vector(31 downto 2);
irqi_forceerr : in std_ulogic;
irqo_intack : out std_ulogic;
irqo_irl : out std_logic_vector(3 downto 0);
irqo_pwd : out std_ulogic;
irqo_fpen : out std_ulogic;
irqo_err : out std_ulogic;
dbgi_dsuen: in std_ulogic; -- DSU enable
dbgi_denable: in std_ulogic; -- diagnostic register access enable
dbgi_dbreak: in std_ulogic; -- debug break-in
dbgi_step: in std_ulogic; -- single step
dbgi_halt: in std_ulogic; -- halt processor
dbgi_reset: in std_ulogic; -- reset processor
dbgi_dwrite: in std_ulogic; -- read/write
dbgi_daddr: in std_logic_vector(23 downto 2); -- diagnostic address
dbgi_ddata: in std_logic_vector(31 downto 0); -- diagnostic data
dbgi_btrapa: in std_ulogic; -- break on IU trap
dbgi_btrape: in std_ulogic; -- break on IU trap
dbgi_berror: in std_ulogic; -- break on IU error mode
dbgi_bwatch: in std_ulogic; -- break on IU watchpoint
dbgi_bsoft: in std_ulogic; -- break on software breakpoint (TA 1)
dbgi_tenable: in std_ulogic;
dbgi_timer: in std_logic_vector(63 downto 0);
dbgo_data: out std_logic_vector(31 downto 0);
dbgo_crdy: out std_ulogic;
dbgo_dsu: out std_ulogic;
dbgo_dsumode: out std_ulogic;
dbgo_error: out std_ulogic;
dbgo_halt: out std_ulogic;
dbgo_pwd: out std_ulogic;
dbgo_idle: out std_ulogic;
dbgo_ipend: out std_ulogic;
dbgo_icnt: out std_ulogic;
dbgo_fcnt : out std_ulogic;
dbgo_optype : out std_logic_vector(5 downto 0); -- instruction type
dbgo_bpmiss : out std_ulogic; -- branch predict miss
dbgo_istat_cmiss: out std_ulogic;
dbgo_istat_tmiss: out std_ulogic;
dbgo_istat_chold: out std_ulogic;
dbgo_istat_mhold: out std_ulogic;
dbgo_dstat_cmiss: out std_ulogic;
dbgo_dstat_tmiss: out std_ulogic;
dbgo_dstat_chold: out std_ulogic;
dbgo_dstat_mhold: out std_ulogic;
dbgo_wbhold : out std_ulogic; -- write buffer hold
dbgo_su : out std_ulogic;
dbgo_ducnt : out std_ulogic);
end component;
component grpci2_phy_net is
generic(
tech : integer := DEFMEMTECH;
oepol : integer := 0;
bypass : integer range 0 to 1 := 1;
netlist : integer := 0
);
port(
pciclk : in std_logic;
pcii_rst : in std_ulogic;
pcii_gnt : in std_ulogic;
pcii_idsel : in std_ulogic;
pcii_ad : in std_logic_vector(31 downto 0);
pcii_cbe : in std_logic_vector(3 downto 0);
pcii_frame : in std_ulogic;
pcii_irdy : in std_ulogic;
pcii_trdy : in std_ulogic;
pcii_devsel : in std_ulogic;
pcii_stop : in std_ulogic;
pcii_lock : in std_ulogic;
pcii_perr : in std_ulogic;
pcii_serr : in std_ulogic;
pcii_par : in std_ulogic;
pcii_host : in std_ulogic;
pcii_pci66 : in std_ulogic;
pcii_pme_status : in std_ulogic;
pcii_int : in std_logic_vector(3 downto 0);
phyi_pcirstout : in std_logic;
phyi_pciasyncrst : in std_logic;
phyi_pcisoftrst : in std_logic_vector(2 downto 0);
phyi_pciinten : in std_logic_vector(3 downto 0);
phyi_m_request : in std_logic;
phyi_m_mabort : in std_logic;
phyi_pr_m_fstate : in std_logic_vector(1 downto 0);
phyi_pr_m_cfifo_0_data : in std_logic_vector(31 downto 0);
phyi_pr_m_cfifo_0_last : in std_logic;
phyi_pr_m_cfifo_0_stlast : in std_logic;
phyi_pr_m_cfifo_0_hold : in std_logic;
phyi_pr_m_cfifo_0_valid : in std_logic;
phyi_pr_m_cfifo_0_err : in std_logic;
phyi_pr_m_cfifo_1_data : in std_logic_vector(31 downto 0);
phyi_pr_m_cfifo_1_last : in std_logic;
phyi_pr_m_cfifo_1_stlast : in std_logic;
phyi_pr_m_cfifo_1_hold : in std_logic;
phyi_pr_m_cfifo_1_valid : in std_logic;
phyi_pr_m_cfifo_1_err : in std_logic;
phyi_pr_m_cfifo_2_data : in std_logic_vector(31 downto 0);
phyi_pr_m_cfifo_2_last : in std_logic;
phyi_pr_m_cfifo_2_stlast : in std_logic;
phyi_pr_m_cfifo_2_hold : in std_logic;
phyi_pr_m_cfifo_2_valid : in std_logic;
phyi_pr_m_cfifo_2_err : in std_logic;
phyi_pv_m_cfifo_0_data : in std_logic_vector(31 downto 0);
phyi_pv_m_cfifo_0_last : in std_logic;
phyi_pv_m_cfifo_0_stlast : in std_logic;
phyi_pv_m_cfifo_0_hold : in std_logic;
phyi_pv_m_cfifo_0_valid : in std_logic;
phyi_pv_m_cfifo_0_err : in std_logic;
phyi_pv_m_cfifo_1_data : in std_logic_vector(31 downto 0);
phyi_pv_m_cfifo_1_last : in std_logic;
phyi_pv_m_cfifo_1_stlast : in std_logic;
phyi_pv_m_cfifo_1_hold : in std_logic;
phyi_pv_m_cfifo_1_valid : in std_logic;
phyi_pv_m_cfifo_1_err : in std_logic;
phyi_pv_m_cfifo_2_data : in std_logic_vector(31 downto 0);
phyi_pv_m_cfifo_2_last : in std_logic;
phyi_pv_m_cfifo_2_stlast : in std_logic;
phyi_pv_m_cfifo_2_hold : in std_logic;
phyi_pv_m_cfifo_2_valid : in std_logic;
phyi_pv_m_cfifo_2_err : in std_logic;
phyi_pr_m_addr : in std_logic_vector(31 downto 0);
phyi_pr_m_cbe_data : in std_logic_vector(3 downto 0);
phyi_pr_m_cbe_cmd : in std_logic_vector(3 downto 0);
phyi_pr_m_first : in std_logic_vector(1 downto 0);
phyi_pv_m_term : in std_logic_vector(1 downto 0);
phyi_pr_m_ltimer : in std_logic_vector(7 downto 0);
phyi_pr_m_burst : in std_logic;
phyi_pr_m_abort : in std_logic_vector(0 downto 0);
phyi_pr_m_perren : in std_logic_vector(0 downto 0);
phyi_pr_m_done_fifo : in std_logic;
phyi_t_abort : in std_logic;
phyi_t_ready : in std_logic;
phyi_t_retry : in std_logic;
phyi_pr_t_state : in std_logic_vector(2 downto 0);
phyi_pv_t_state : in std_logic_vector(2 downto 0);
phyi_pr_t_fstate : in std_logic_vector(1 downto 0);
phyi_pr_t_cfifo_0_data : in std_logic_vector(31 downto 0);
phyi_pr_t_cfifo_0_last : in std_logic;
phyi_pr_t_cfifo_0_stlast : in std_logic;
phyi_pr_t_cfifo_0_hold : in std_logic;
phyi_pr_t_cfifo_0_valid : in std_logic;
phyi_pr_t_cfifo_0_err : in std_logic;
phyi_pr_t_cfifo_1_data : in std_logic_vector(31 downto 0);
phyi_pr_t_cfifo_1_last : in std_logic;
phyi_pr_t_cfifo_1_stlast : in std_logic;
phyi_pr_t_cfifo_1_hold : in std_logic;
phyi_pr_t_cfifo_1_valid : in std_logic;
phyi_pr_t_cfifo_1_err : in std_logic;
phyi_pr_t_cfifo_2_data : in std_logic_vector(31 downto 0);
phyi_pr_t_cfifo_2_last : in std_logic;
phyi_pr_t_cfifo_2_stlast : in std_logic;
phyi_pr_t_cfifo_2_hold : in std_logic;
phyi_pr_t_cfifo_2_valid : in std_logic;
phyi_pr_t_cfifo_2_err : in std_logic;
phyi_pv_t_diswithout : in std_logic;
phyi_pr_t_stoped : in std_logic;
phyi_pr_t_lcount : in std_logic_vector(2 downto 0);
phyi_pr_t_first_word : in std_logic;
phyi_pr_t_cur_acc_0_read : in std_logic;
phyi_pv_t_hold_write : in std_logic;
phyi_pv_t_hold_reset : in std_logic;
phyi_pr_conf_comm_perren : in std_logic;
phyi_pr_conf_comm_serren : in std_logic;
pcio_aden : out std_ulogic;
pcio_vaden : out std_logic_vector(31 downto 0);
pcio_cbeen : out std_logic_vector(3 downto 0);
pcio_frameen : out std_ulogic;
pcio_irdyen : out std_ulogic;
pcio_trdyen : out std_ulogic;
pcio_devselen : out std_ulogic;
pcio_stopen : out std_ulogic;
pcio_ctrlen : out std_ulogic;
pcio_perren : out std_ulogic;
pcio_paren : out std_ulogic;
pcio_reqen : out std_ulogic;
pcio_locken : out std_ulogic;
pcio_serren : out std_ulogic;
pcio_inten : out std_ulogic;
pcio_vinten : out std_logic_vector(3 downto 0);
pcio_req : out std_ulogic;
pcio_ad : out std_logic_vector(31 downto 0);
pcio_cbe : out std_logic_vector(3 downto 0);
pcio_frame : out std_ulogic;
pcio_irdy : out std_ulogic;
pcio_trdy : out std_ulogic;
pcio_devsel : out std_ulogic;
pcio_stop : out std_ulogic;
pcio_perr : out std_ulogic;
pcio_serr : out std_ulogic;
pcio_par : out std_ulogic;
pcio_lock : out std_ulogic;
pcio_power_state : out std_logic_vector(1 downto 0);
pcio_pme_enable : out std_ulogic;
pcio_pme_clear : out std_ulogic;
pcio_int : out std_ulogic;
pcio_rst : out std_ulogic;
phyo_pciv_rst : out std_ulogic;
phyo_pciv_gnt : out std_ulogic;
phyo_pciv_idsel : out std_ulogic;
phyo_pciv_ad : out std_logic_vector(31 downto 0);
phyo_pciv_cbe : out std_logic_vector(3 downto 0);
phyo_pciv_frame : out std_ulogic;
phyo_pciv_irdy : out std_ulogic;
phyo_pciv_trdy : out std_ulogic;
phyo_pciv_devsel : out std_ulogic;
phyo_pciv_stop : out std_ulogic;
phyo_pciv_lock : out std_ulogic;
phyo_pciv_perr : out std_ulogic;
phyo_pciv_serr : out std_ulogic;
phyo_pciv_par : out std_ulogic;
phyo_pciv_host : out std_ulogic;
phyo_pciv_pci66 : out std_ulogic;
phyo_pciv_pme_status : out std_ulogic;
phyo_pciv_int : out std_logic_vector(3 downto 0);
phyo_pr_m_state : out std_logic_vector(2 downto 0);
phyo_pr_m_last : out std_logic_vector(1 downto 0);
phyo_pr_m_hold : out std_logic_vector(1 downto 0);
phyo_pr_m_term : out std_logic_vector(1 downto 0);
phyo_pr_t_hold : out std_logic_vector(0 downto 0);
phyo_pr_t_stop : out std_logic;
phyo_pr_t_abort : out std_logic;
phyo_pr_t_diswithout : out std_logic;
phyo_pr_t_addr_perr : out std_logic;
phyo_pcirsto : out std_logic_vector(0 downto 0);
phyo_pr_po_ad : out std_logic_vector(31 downto 0);
phyo_pr_po_aden : out std_logic_vector(31 downto 0);
phyo_pr_po_cbe : out std_logic_vector(3 downto 0);
phyo_pr_po_cbeen : out std_logic_vector(3 downto 0);
phyo_pr_po_frame : out std_logic;
phyo_pr_po_frameen : out std_logic;
phyo_pr_po_irdy : out std_logic;
phyo_pr_po_irdyen : out std_logic;
phyo_pr_po_trdy : out std_logic;
phyo_pr_po_trdyen : out std_logic;
phyo_pr_po_stop : out std_logic;
phyo_pr_po_stopen : out std_logic;
phyo_pr_po_devsel : out std_logic;
phyo_pr_po_devselen : out std_logic;
phyo_pr_po_par : out std_logic;
phyo_pr_po_paren : out std_logic;
phyo_pr_po_perr : out std_logic;
phyo_pr_po_perren : out std_logic;
phyo_pr_po_lock : out std_logic;
phyo_pr_po_locken : out std_logic;
phyo_pr_po_req : out std_logic;
phyo_pr_po_reqen : out std_logic;
phyo_pr_po_serren : out std_logic;
phyo_pr_po_inten : out std_logic;
phyo_pr_po_vinten : out std_logic_vector(3 downto 0);
phyo_pio_rst : out std_ulogic;
phyo_pio_gnt : out std_ulogic;
phyo_pio_idsel : out std_ulogic;
phyo_pio_ad : out std_logic_vector(31 downto 0);
phyo_pio_cbe : out std_logic_vector(3 downto 0);
phyo_pio_frame : out std_ulogic;
phyo_pio_irdy : out std_ulogic;
phyo_pio_trdy : out std_ulogic;
phyo_pio_devsel : out std_ulogic;
phyo_pio_stop : out std_ulogic;
phyo_pio_lock : out std_ulogic;
phyo_pio_perr : out std_ulogic;
phyo_pio_serr : out std_ulogic;
phyo_pio_par : out std_ulogic;
phyo_pio_host : out std_ulogic;
phyo_pio_pci66 : out std_ulogic;
phyo_pio_pme_status : out std_ulogic;
phyo_pio_int : out std_logic_vector(3 downto 0);
phyo_poo_ad : out std_logic_vector(31 downto 0);
phyo_poo_aden : out std_logic_vector(31 downto 0);
phyo_poo_cbe : out std_logic_vector(3 downto 0);
phyo_poo_cbeen : out std_logic_vector(3 downto 0);
phyo_poo_frame : out std_logic;
phyo_poo_frameen : out std_logic;
phyo_poo_irdy : out std_logic;
phyo_poo_irdyen : out std_logic;
phyo_poo_trdy : out std_logic;
phyo_poo_trdyen : out std_logic;
phyo_poo_stop : out std_logic;
phyo_poo_stopen : out std_logic;
phyo_poo_devsel : out std_logic;
phyo_poo_devselen : out std_logic;
phyo_poo_par : out std_logic;
phyo_poo_paren : out std_logic;
phyo_poo_perr : out std_logic;
phyo_poo_perren : out std_logic;
phyo_poo_lock : out std_logic;
phyo_poo_locken : out std_logic;
phyo_poo_req : out std_logic;
phyo_poo_reqen : out std_logic;
phyo_poo_serren : out std_logic;
phyo_poo_inten : out std_logic;
phyo_poo_vinten : out std_logic_vector(3 downto 0)
);
end component;
component gr1553b_net
generic (
tech : integer range 0 to NTECH := DEFFABTECH;
bc_enable: integer range 0 to 1 := 1;
rt_enable: integer range 0 to 1 := 1;
bm_enable: integer range 0 to 1 := 1;
bc_timer: integer range 0 to 2 := 1;
bc_rtbusmask: integer range 0 to 1 := 1;
extra_regkeys: integer range 0 to 1 := 0;
syncrst: integer range 0 to 2 := 1;
ahbendian: integer := 0;
bm_filters: integer range 0 to 1 := 1;
codecfreq: integer := 20;
sameclk: integer range 0 to 1 := 0;
codecver: integer range 0 to 2 := 0
);
port (
clk: in std_logic;
rst: in std_logic;
codec_clk: in std_logic;
codec_rst: in std_logic;
-- AHB interface
mi_hgrant : in std_logic; -- bus grant
mi_hready : in std_ulogic; -- transfer done
mi_hresp : in std_logic_vector(1 downto 0); -- response type
mi_hrdata : in std_logic_vector(31 downto 0); -- read data bus
mo_hbusreq : out std_ulogic; -- bus request
mo_htrans : out std_logic_vector(1 downto 0); -- transfer type
mo_haddr : out std_logic_vector(31 downto 0); -- address bus (byte)
mo_hwrite : out std_ulogic; -- read/write
mo_hsize : out std_logic_vector(2 downto 0); -- transfer size
mo_hburst : out std_logic_vector(2 downto 0); -- burst type
mo_hwdata : out std_logic_vector(31 downto 0); -- write data bus
-- APB interface
si_psel : in std_logic; -- slave select
si_penable : in std_ulogic; -- strobe
si_paddr : in std_logic_vector(7 downto 0); -- address bus (byte addr)
si_pwrite : in std_ulogic; -- write
si_pwdata : in std_logic_vector(31 downto 0); -- write data bus
so_prdata : out std_logic_vector(31 downto 0); -- read data bus
so_pirq : out std_logic; -- interrupt bus
-- Aux signals
bcsync : in std_logic;
rtsync : out std_logic;
busreset : out std_logic;
rtaddr : in std_logic_vector(4 downto 0);
rtaddrp : in std_logic;
-- 1553 transceiver interface
busainen : out std_logic;
busainp : in std_logic;
busainn : in std_logic;
busaouten : out std_logic;
busaoutp : out std_logic;
busaoutn : out std_logic;
busbinen : out std_logic;
busbinp : in std_logic;
busbinn : in std_logic;
busbouten : out std_logic;
busboutp : out std_logic;
busboutn : out std_logic
);
end component;
end;
| gpl-3.0 | 74192851376e9a23cc1d36f88b776b14 | 0.532915 | 3.380325 | false | false | false | false |
hoglet67/CoPro6502 | src/CPU65C02/regbank_axy.vhd | 1 | 6,968 | -- VHDL Entity r65c02_tc.regbank_axy.symbol
--
-- Created:
-- by - eda.UNKNOWN (ENTW-7HPZ200)
-- at - 20:45:48 27.08.2018
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
entity regbank_axy is
port(
clk_clk_i : in std_logic;
d_regs_in_i : in std_logic_vector (7 downto 0);
load_regs_i : in std_logic;
rst_rst_n_i : in std_logic;
sel_rb_in_i : in std_logic_vector (1 downto 0);
sel_rb_out_i : in std_logic_vector (1 downto 0);
sel_reg_i : in std_logic_vector (1 downto 0);
d_regs_out_o : out std_logic_vector (7 downto 0);
q_a_o : out std_logic_vector (7 downto 0);
q_x_o : out std_logic_vector (7 downto 0);
q_y_o : out std_logic_vector (7 downto 0)
);
-- Declarations
end regbank_axy ;
-- (C) 2008 - 2018 Jens Gutschmidt
-- (email: [email protected])
--
-- Versions:
-- Revision 1.7 2013/07/21 11:11:00 jens
-- - Changing the title block and internal revision history
--
-- Revision 1.6 2009/01/04 10:20:47 eda
-- Changes for cosmetic issues only
--
-- Revision 1.5 2009/01/04 09:23:10 eda
-- - Delete unused nets and blocks (same as R6502_TC)
-- - Rename blocks
--
-- Revision 1.4 2009/01/03 16:53:02 eda
-- - Unused nets and blocks deleted
-- - Renamed blocks
--
-- Revision 1.3 2009/01/03 16:42:02 eda
-- - Unused nets and blocks deleted
-- - Renamed blocks
--
-- Revision 1.2 2008/12/31 19:31:24 eda
-- Production Release
--
--
--
-- VHDL Architecture r65c02_tc.regbank_axy.struct
--
-- Created:
-- by - eda.UNKNOWN (ENTW-7HPZ200)
-- at - 12:04:48 06.09.2018
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5)
--
-- COPYRIGHT (C) 2008 - 2018 by Jens Gutschmidt
--
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
architecture struct of regbank_axy is
-- Architecture declarations
-- Internal signal declarations
signal ld : std_logic_vector(2 downto 0);
signal load1_o_i : std_logic;
signal load2_o_i : std_logic;
signal load_o_i : std_logic;
signal q_mux_o_i : std_logic_vector(7 downto 0);
signal val_zero : std_logic_vector(7 downto 0);
-- Implicit buffer signal declarations
signal q_a_o_internal : std_logic_vector (7 downto 0);
signal q_x_o_internal : std_logic_vector (7 downto 0);
signal q_y_o_internal : std_logic_vector (7 downto 0);
-- ModuleWare signal declarations(v1.12) for instance 'U_0' of 'adff'
signal mw_U_0reg_cval : std_logic_vector(7 downto 0);
-- ModuleWare signal declarations(v1.12) for instance 'U_4' of 'adff'
signal mw_U_4reg_cval : std_logic_vector(7 downto 0);
-- ModuleWare signal declarations(v1.12) for instance 'U_5' of 'adff'
signal mw_U_5reg_cval : std_logic_vector(7 downto 0);
begin
-- ModuleWare code(v1.12) for instance 'U_0' of 'adff'
q_a_o_internal <= mw_U_0reg_cval;
u_0seq_proc: process (clk_clk_i, rst_rst_n_i)
begin
if (rst_rst_n_i = '0') then
mw_U_0reg_cval <= "00000000";
elsif (clk_clk_i'event and clk_clk_i='1') then
if (load_o_i = '1') then
mw_U_0reg_cval <= q_mux_o_i;
end if;
end if;
end process u_0seq_proc;
-- ModuleWare code(v1.12) for instance 'U_4' of 'adff'
q_x_o_internal <= mw_U_4reg_cval;
u_4seq_proc: process (clk_clk_i, rst_rst_n_i)
begin
if (rst_rst_n_i = '0') then
mw_U_4reg_cval <= "00000000";
elsif (clk_clk_i'event and clk_clk_i='1') then
if (load1_o_i = '1') then
mw_U_4reg_cval <= q_mux_o_i;
end if;
end if;
end process u_4seq_proc;
-- ModuleWare code(v1.12) for instance 'U_5' of 'adff'
q_y_o_internal <= mw_U_5reg_cval;
u_5seq_proc: process (clk_clk_i, rst_rst_n_i)
begin
if (rst_rst_n_i = '0') then
mw_U_5reg_cval <= "00000000";
elsif (clk_clk_i'event and clk_clk_i='1') then
if (load2_o_i = '1') then
mw_U_5reg_cval <= q_mux_o_i;
end if;
end if;
end process u_5seq_proc;
-- ModuleWare code(v1.12) for instance 'U_6' of 'and'
load_o_i <= load_regs_i and ld(0);
-- ModuleWare code(v1.12) for instance 'U_7' of 'and'
load1_o_i <= load_regs_i and ld(1);
-- ModuleWare code(v1.12) for instance 'U_8' of 'and'
load2_o_i <= load_regs_i and ld(2);
-- ModuleWare code(v1.12) for instance 'U_11' of 'constval'
val_zero <= "00000000";
-- ModuleWare code(v1.12) for instance 'U_1' of 'decoder1'
u_1combo_proc: process (sel_reg_i)
begin
ld <= (others => '0');
case sel_reg_i is
when "00" => ld(0) <= '1';
when "01" => ld(1) <= '1';
when "10" => ld(2) <= '1';
when others => ld <= (others => '0');
end case;
end process u_1combo_proc;
-- ModuleWare code(v1.12) for instance 'U_2' of 'mux'
u_2combo_proc: process(q_a_o_internal, q_x_o_internal, q_y_o_internal,
val_zero, sel_rb_out_i)
begin
case sel_rb_out_i is
when "00" => d_regs_out_o <= q_a_o_internal;
when "01" => d_regs_out_o <= q_x_o_internal;
when "10" => d_regs_out_o <= q_y_o_internal;
when "11" => d_regs_out_o <= val_zero;
when others => d_regs_out_o <= (others => 'X');
end case;
end process u_2combo_proc;
-- ModuleWare code(v1.12) for instance 'U_3' of 'mux'
u_3combo_proc: process(q_a_o_internal, q_y_o_internal, q_x_o_internal,
d_regs_in_i, sel_rb_in_i)
begin
case sel_rb_in_i is
when "00" => q_mux_o_i <= q_a_o_internal;
when "01" => q_mux_o_i <= q_y_o_internal;
when "10" => q_mux_o_i <= q_x_o_internal;
when "11" => q_mux_o_i <= d_regs_in_i;
when others => q_mux_o_i <= (others => 'X');
end case;
end process u_3combo_proc;
-- Instance port mappings.
-- Implicit buffered output assignments
q_a_o <= q_a_o_internal;
q_x_o <= q_x_o_internal;
q_y_o <= q_y_o_internal;
end struct;
| gpl-3.0 | 539bda3abe67c8d0b8ec944c7dd3b756 | 0.580941 | 2.897297 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/leon3/leon3.vhd | 1 | 42,363 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: leon3
-- File: leon3.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: LEON3 types and components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
package leon3 is
constant LEON3_VERSION : integer := 3;
type l3_irq_in_type is record
irl : std_logic_vector(3 downto 0);
resume : std_ulogic;
rstrun : std_ulogic;
rstvec : std_logic_vector(31 downto 12);
index : std_logic_vector(3 downto 0);
pwdsetaddr : std_ulogic;
pwdnewaddr : std_logic_vector(31 downto 2);
forceerr : std_ulogic;
end record;
type l3_irq_out_type is record
intack : std_ulogic;
irl : std_logic_vector(3 downto 0);
pwd : std_ulogic;
fpen : std_ulogic;
err : std_ulogic;
end record;
type l3_debug_in_type is record
dsuen : std_ulogic; -- DSU enable
denable : std_ulogic; -- diagnostic register access enable
dbreak : std_ulogic; -- debug break-in
step : std_ulogic; -- single step
halt : std_ulogic; -- halt processor
reset : std_ulogic; -- reset processor
dwrite : std_ulogic; -- read/write
daddr : std_logic_vector(23 downto 2); -- diagnostic address
ddata : std_logic_vector(31 downto 0); -- diagnostic data
btrapa : std_ulogic; -- break on IU trap
btrape : std_ulogic; -- break on IU trap
berror : std_ulogic; -- break on IU error mode
bwatch : std_ulogic; -- break on IU watchpoint
bsoft : std_ulogic; -- break on software breakpoint (TA 1)
tenable : std_ulogic;
timer : std_logic_vector(30 downto 0); --
end record;
constant dbgi_none : l3_debug_in_type := ('0', '0', '0', '0', '0',
'0', '0', (others => '0'), (others => '0'), '0', '0', '0', '0', '0', '0', (others => '0'));
constant l3_dbgi_none : l3_debug_in_type := dbgi_none;
type l3_cstat_type is record
cmiss : std_ulogic; -- cache miss
tmiss : std_ulogic; -- TLB miss
chold : std_ulogic; -- cache hold
mhold : std_ulogic; -- cache mmu hold
end record;
constant cstat_none : l3_cstat_type := ('0', '0', '0', '0');
type l3_debug_out_type is record
data : std_logic_vector(31 downto 0);
crdy : std_ulogic;
dsu : std_ulogic;
dsumode : std_ulogic;
error : std_ulogic;
halt : std_ulogic;
pwd : std_ulogic;
idle : std_ulogic;
ipend : std_ulogic;
icnt : std_ulogic;
fcnt : std_ulogic;
optype : std_logic_vector(5 downto 0); -- instruction type
bpmiss : std_ulogic; -- branch predict miss
istat : l3_cstat_type;
dstat : l3_cstat_type;
wbhold : std_ulogic; -- write buffer hold
su : std_ulogic; -- supervisor state
end record;
type l3_debug_in_vector is array (natural range <>) of l3_debug_in_type;
type l3_debug_out_vector is array (natural range <>) of l3_debug_out_type;
constant dbgo_none : l3_debug_out_type := (X"00000000", '0', '0', '0', '0',
'0', '0', '0', '0', '0', '0', "000000", '0', cstat_none, cstat_none, '0', '0');
constant l3_dbgo_none : l3_debug_out_type := dbgo_none;
type tracebuf_in_type is record
addr : std_logic_vector(11 downto 0);
data : std_logic_vector(255 downto 0);
enable : std_logic;
write : std_logic_vector(7 downto 0);
end record;
type tracebuf_out_type is record
data : std_logic_vector(255 downto 0);
end record;
type tracebuf_2p_in_type is record
renable : std_logic;
raddr : std_logic_vector(11 downto 0);
write : std_logic_vector(7 downto 0);
waddr : std_logic_vector(11 downto 0);
data : std_logic_vector(255 downto 0);
end record;
type tracebuf_2p_out_type is record
data : std_logic_vector(255 downto 0);
end record;
component tbufmem
generic ( tech : integer := 0; tbuf : integer := 0; dwidth : integer := 32; testen: integer := 0);
port (
clk : in std_ulogic;
di : in tracebuf_in_type;
do : out tracebuf_out_type;
testin: in std_logic_vector(TESTIN_WIDTH-1 downto 0)
);
end component;
component tbufmem_2p is
generic (
tech : integer := 0;
tbuf : integer := 0; -- trace buf size in kB (0 - no trace buffer)
dwidth : integer := 64; -- AHB data width
testen : integer := 0
);
port (
clk : in std_ulogic;
di : in tracebuf_2p_in_type;
do : out tracebuf_2p_out_type;
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0)
);
end component;
constant tracebuf_out_type_none : tracebuf_out_type :=
(data => (others => '0'));
constant tracebuf_in_type_none : tracebuf_in_type := (
addr => (others => '0'),
data => (others => '0'),
enable => '0',
write => (others => '0')
);
constant tracebuf_2p_out_type_none : tracebuf_2p_out_type :=
(data => (others => '0'));
constant tracebuf_2p_in_type_none : tracebuf_2p_in_type := (
renable => '0',
raddr => (others => '0'),
write => (others => '0'),
waddr => (others => '0'),
data => (others => '0')
);
component leon3s
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 7 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart: integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart: integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0;
pwd : integer range 0 to 2 := 2;
svt : integer range 0 to 1 := 1;
rstaddr : integer := 16#00000#;
smp : integer range 0 to 15 := 0;
cached : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0;
rex : integer range 0 to 1 := 0;
altwin : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type
);
end component;
component leon3cg
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 7 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart: integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart: integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0;
pwd : integer range 0 to 2 := 2;
svt : integer range 0 to 1 := 1;
rstaddr : integer := 16#00000#;
smp : integer range 0 to 15 := 0;
cached : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0;
rex : integer range 0 to 1 := 0;
altwin : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
gclk : in std_ulogic
);
end component;
component leon3ft
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 7 := 0;
ilram : integer range 0 to 2 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart: integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 2 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart: integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0;
pwd : integer range 0 to 2 := 2;
svt : integer range 0 to 1 := 1;
rstaddr : integer := 16#00000#;
smp : integer range 0 to 15 := 0; -- support SMP systems
iuft : integer range 0 to 6 := 0;
fpft : integer range 0 to 6 := 0;
cmft : integer range 0 to 1 := 0;
iuinj : integer := 0;
ceinj : integer range 0 to 3 := 0;
cached : integer := 0; -- cacheability table
netlist : integer := 0; -- use netlist
scantest : integer := 0; -- enable scan test support
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0;
rex : integer range 0 to 1 := 0;
altwin : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
gclk : in std_ulogic
);
end component;
type grfpu_in_type is record
start : std_logic;
nonstd : std_logic;
flop : std_logic_vector(8 downto 0);
op1 : std_logic_vector(63 downto 0);
op2 : std_logic_vector(63 downto 0);
opid : std_logic_vector(7 downto 0);
flush : std_logic;
flushid : std_logic_vector(5 downto 0);
rndmode : std_logic_vector(1 downto 0);
req : std_logic_vector(2 downto 0);
end record;
constant grfpu_in_none : grfpu_in_type :=
('0', '0', (others => '0'), (others => '0'), (others => '0'),
(others => '0'), '0', (others => '0'), (others => '0'),
(others => '0'));
type grfpu_out_type is record
res : std_logic_vector(63 downto 0);
exc : std_logic_vector(5 downto 0);
allow : std_logic_vector(2 downto 0);
rdy : std_logic;
cc : std_logic_vector(1 downto 0);
idout : std_logic_vector(7 downto 0);
end record;
constant grfpu_out_none : grfpu_out_type :=
((others => '0'), (others => '0'), (others => '0'),
'0', (others => '0'), (others => '0'));
type grfpu_out_vector_type is array (integer range 0 to 7) of grfpu_out_type;
type grfpu_in_vector_type is array (integer range 0 to 7) of grfpu_in_type;
component grfpushwx
generic (mul : integer := 0;
nshare : integer range 0 to 8 := 0;
tech : integer;
arb : integer range 0 to 2 := 1);
port(
clk : in std_logic;
reset : in std_logic;
fpvi : in grfpu_in_vector_type;
fpvo : out grfpu_out_vector_type
);
end component;
component leon3sh
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 63 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 7 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
cached : integer := 0; -- cacheability table
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0;
rex : integer range 0 to 1 := 0;
altwin : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
fpui : out grfpu_in_type;
fpuo : in grfpu_out_type
);
end component;
component leon3s2x
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 7 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
cached : integer := 0; -- cacheability table
clk2x : integer := 1;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0;
rex : integer range 0 to 1 := 0;
altwin : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
gclk2 : in std_ulogic;
clk2 : in std_ulogic; -- snoop clock
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
clken : in std_ulogic
);
end component;
component leon3ft2x
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 63 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 7 := 0;
ilram : integer range 0 to 2 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 2 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
iuft : integer range 0 to 6 := 0;
fpft : integer range 0 to 6 := 0;
cmft : integer range 0 to 1 := 0;
iuinj : integer := 0;
ceinj : integer range 0 to 3 := 0;
cached : integer := 0;
clk2x : integer := 1;
netlist : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0;
rex : integer range 0 to 1 := 0;
altwin : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic; -- free-running clock
gclk2 : in std_ulogic; -- gated 2x clock
gfclk2 : in std_ulogic; -- gated 2x FPU clock
clk2 : in std_ulogic; -- free-running 2x clock
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
fpui : out grfpu_in_type;
fpuo : in grfpu_out_type;
clken : in std_ulogic
);
end component;
type dsu_in_type is record
enable : std_ulogic;
break : std_ulogic;
end record;
subtype dsu_astat_type is amba_stat_type;
constant dsu_astat_none : dsu_astat_type := amba_stat_none;
type dsu_out_type is record
active : std_ulogic;
tstop : std_ulogic;
pwd : std_logic_vector(15 downto 0);
astat : dsu_astat_type;
end record;
constant dsu_out_none : dsu_out_type :=
(active => '0', tstop => '0', pwd => (others => '0'),
astat => dsu_astat_none);
component dsu3
generic (
hindex : integer := 0;
haddr : integer := 16#900#;
hmask : integer := 16#f00#;
ncpu : integer := 1;
tbits : integer := 30; -- timer bits (instruction trace time tag)
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 0;
testen : integer := 0;
bwidth : integer := 32;
ahbpf : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
dbgi : in l3_debug_out_vector(0 to NCPU-1);
dbgo : out l3_debug_in_vector(0 to NCPU-1);
dsui : in dsu_in_type;
dsuo : out dsu_out_type
);
end component;
component dsu3_2x
generic (
hindex : integer := 0;
haddr : integer := 16#900#;
hmask : integer := 16#f00#;
ncpu : integer := 1;
tbits : integer := 30; -- timer bits (instruction trace time tag)
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 0;
testen : integer := 0;
bwidth : integer := 32;
ahbpf : integer := 0
);
port (
rst : in std_ulogic;
hclk : in std_ulogic;
cpuclk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
dbgi : in l3_debug_out_vector(0 to NCPU-1);
dbgo : out l3_debug_in_vector(0 to NCPU-1);
dsui : in dsu_in_type;
dsuo : out dsu_out_type;
hclken : in std_ulogic
);
end component;
component dsu3x
generic (
hindex : integer := 0;
haddr : integer := 16#900#;
hmask : integer := 16#f00#;
ncpu : integer := 1;
tbits : integer := 30; -- timer bits (instruction trace time tag)
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 0;
clk2x : integer range 0 to 1 := 0;
testen : integer := 0;
bwidth : integer := 32;
ahbpf : integer := 0
);
port (
rst : in std_ulogic;
hclk : in std_ulogic;
cpuclk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
tahbsi : in ahb_slv_in_type;
dbgi : in l3_debug_out_vector(0 to NCPU-1);
dbgo : out l3_debug_in_vector(0 to NCPU-1);
dsui : in dsu_in_type;
dsuo : out dsu_out_type;
hclken : in std_ulogic
);
end component;
component dsu3_mb
generic (
hindex : integer := 0;
haddr : integer := 16#900#;
hmask : integer := 16#f00#;
ncpu : integer := 1;
tbits : integer := 30; -- timer bits (instruction trace time tag)
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 0;
testen : integer := 0;
bwidth : integer := 32;
ahbpf : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
tahbsi : in ahb_slv_in_type;
dbgi : in l3_debug_out_vector(0 to NCPU-1);
dbgo : out l3_debug_in_vector(0 to NCPU-1);
dsui : in dsu_in_type;
dsuo : out dsu_out_type
);
end component;
type l3stat_src_array is array (15 downto 0) of std_logic_vector(3 downto 0);
type l3stat_in_type is record
event : std_logic_vector(15 downto 0);
esource : l3stat_src_array;
sel : std_logic_vector(15 downto 0);
req : std_logic_vector(15 downto 0);
latcnt : std_ulogic;
timer : std_logic_vector(31 downto 0);
end record;
constant l3stat_in_none : l3stat_in_type :=
(event => (others => '0'),
esource => (others => (others => '0')),
sel => (others => '0'),
req => (others => '0'),
latcnt => '0',
timer => (others => '0'));
component l3stat
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ncnt : integer range 1 to 64 := 2;
ncpu : integer := 1;
nmax : integer := 0;
lahben : integer := 0;
dsuen : integer := 0;
nextev : integer range 0 to 16 := 0;
apb2en : integer := 0;
pindex2 : integer := 0;
paddr2 : integer := 0;
pmask2 : integer := 16#fff#;
astaten : integer := 0;
selreq : integer := 0;
clatch : integer := 0;
forcer0 : integer range 0 to 1 := 0
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbsi : in ahb_slv_in_type;
dbgo : in l3_debug_out_vector(0 to NCPU-1);
dsuo : in dsu_out_type := dsu_out_none;
stati : in l3stat_in_type := l3stat_in_none;
apb2i : in apb_slv_in_type := apb_slv_in_none;
apb2o : out apb_slv_out_type;
astat : in amba_stat_type := amba_stat_none);
end component;
type irq_in_vector is array (Natural range <> ) of l3_irq_in_type;
type irq_out_vector is array (Natural range <> ) of l3_irq_out_type;
component irqmp
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ncpu : integer := 1;
eirq : integer := 0;
irqmap : integer := 0;
bootreg : integer := 1
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
irqi : in irq_out_vector(0 to ncpu-1);
irqo : out irq_in_vector(0 to ncpu-1)
);
end component;
component irqmp2x
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ncpu : integer := 1;
eirq : integer := 0;
clkfact : integer := 2;
irqmap : integer := 0
);
port (
rst : in std_ulogic;
hclk : in std_ulogic;
cpuclk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
irqi : in irq_out_vector(0 to ncpu-1);
irqo : out irq_in_vector(0 to ncpu-1);
hclken : in std_ulogic
);
end component;
component irqamp
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ncpu : integer := 1;
eirq : integer := 0;
nctrl : integer range 1 to 16 := 1;
tstamp : integer range 0 to 16 := 0;
wdogen : integer range 0 to 1 := 0;
nwdog : integer range 1 to 16 := 1;
dynrstaddr : integer range 0 to 0 := 0;
rstaddr : integer range 0 to 16#fffff# := 0;
extrun : integer range 0 to 1 := 0;
irqmap : integer := 0;
exttimer : integer range 0 to 1 := 0;
bootreg : integer range 0 to 1 := 1
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
irqi : in irq_out_vector(0 to ncpu-1);
irqo : out irq_in_vector(0 to ncpu-1);
wdog : in std_logic_vector(nwdog-1 downto 0) := (others => '0');
cpurun : in std_logic_vector(ncpu-1 downto 0) := (others => '0');
timer : in std_logic_vector(31 downto 0) := (others => '0');
rstmap : in std_logic_vector((64*5)-1 downto 0) := (others => '0')
);
end component;
component irqamp2x
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ncpu : integer := 1;
eirq : integer := 0;
nctrl : integer range 1 to 16 := 1;
tstamp : integer range 0 to 16 := 0;
wdogen : integer range 0 to 1 := 0;
nwdog : integer range 1 to 16 := 1;
dynrstaddr : integer range 0 to 0 := 0;
rstaddr : integer range 0 to 16#fffff# := 0;
extrun : integer range 0 to 1 := 0;
clkfact : integer := 2;
irqmap : integer := 0;
exttimer : integer range 0 to 1 := 0;
bootreg : integer range 0 to 1 := 1
);
port (
rst : in std_ulogic;
hclk : in std_ulogic;
cpuclk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
irqi : in irq_out_vector(0 to ncpu-1);
irqo : out irq_in_vector(0 to ncpu-1);
wdog : in std_logic_vector(nwdog-1 downto 0) := (others => '0');
cpurun : in std_logic_vector(ncpu-1 downto 0) := (others => '0');
hclken : in std_ulogic;
timer : in std_logic_vector(31 downto 0) := (others => '0');
rstmap : in std_logic_vector((64*5)-1 downto 0) := (others => '0')
);
end component;
component leon3ftsh
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 63 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 7 := 0;
ilram : integer range 0 to 2 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 2 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
iuft : integer range 0 to 6 := 0;
fpft : integer range 0 to 6 := 0;
cmft : integer range 0 to 1 := 0;
iuinj : integer := 0;
ceinj : integer range 0 to 3 := 0;
cached : integer := 0;
netlist : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0;
altwin : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic; -- free-running clock
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
gclk : in std_ulogic; -- gated clock
fpui : out grfpu_in_type;
fpuo : in grfpu_out_type
);
end component;
component leon3x
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 63 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 7 := 0;
ilram : integer range 0 to 2 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 2 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
iuft : integer range 0 to 6 := 0;
fpft : integer range 0 to 6 := 0;
cmft : integer range 0 to 1 := 0;
iuinj : integer := 0;
ceinj : integer range 0 to 3 := 0;
cached : integer := 0;
clk2x : integer := 1;
netlist : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0;
rex : integer := 0;
altwin : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic; -- free-running clock
gclk2 : in std_ulogic; -- gated 2x clock
gfclk2 : in std_ulogic; -- gated 2x FPU clock
clk2 : in std_ulogic; -- free-running 2x clock
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
fpui : out grfpu_in_type;
fpuo : in grfpu_out_type;
clken : in std_ulogic
);
end component;
-- disassembly dummy module
component cpu_disasx
port (
clk : in std_ulogic;
rstn : in std_ulogic;
dummy : out std_ulogic;
inst : in std_logic_vector(31 downto 0);
pc : in std_logic_vector(31 downto 2);
result : in std_logic_vector(31 downto 0);
index : in std_logic_vector(3 downto 0);
wreg : in std_ulogic;
annul : in std_ulogic;
holdn : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic;
disas : in std_ulogic);
end component;
end;
| gpl-3.0 | dbb08301acf435799d503c38aec69f80 | 0.523004 | 3.420233 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-arrow-bemicro-sdk/leon3mp.vhd | 1 | 27,537 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2011 - 2012 Jan Andersson, Aeroflex Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.net.all;
use gaisler.jtag.all;
--pragma translate_off
use gaisler.sim.all;
--pragma translate_on
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
freq : integer := 50000 -- frequency of main clock (used for PLLs)
);
port (
cpu_rst_n : in std_ulogic;
clk_fpga_50m : in std_ulogic;
-- DDR SDRAM
ram_a : out std_logic_vector (13 downto 0); -- ddr address
ram_ck_p : out std_logic;
ram_ck_n : out std_logic;
ram_cke : out std_logic;
ram_cs_n : out std_logic;
ram_ws_n : out std_ulogic; -- ddr write enable
ram_ras_n : out std_ulogic; -- ddr ras
ram_cas_n : out std_ulogic; -- ddr cas
ram_dm : out std_logic_vector(1 downto 0); -- ram_udm & ram_ldm
ram_dqs : inout std_logic_vector (1 downto 0); -- ram_udqs & ram_lqds
ram_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ram_d : inout std_logic_vector (15 downto 0); -- ddr data
-- Ethernet PHY
txd : out std_logic_vector(3 downto 0);
rxd : in std_logic_vector(3 downto 0);
tx_clk : in std_logic;
rx_clk : in std_logic;
tx_en : out std_logic;
rx_dv : in std_logic;
eth_crs : in std_logic;
rx_er : in std_logic;
eth_col : in std_logic;
mdio : inout std_logic;
mdc : out std_logic;
eth_reset_n : out std_logic;
-- Temperature sensor
temp_sc : inout std_logic;
temp_cs_n : out std_logic;
temp_sio : inout std_logic;
-- LEDs
f_led : inout std_logic_vector(7 downto 0);
-- User push-button
pbsw_n : in std_logic;
-- Reconfig SW1 and SW2
reconfig_sw : in std_logic_vector(2 downto 1);
-- SD card interface
sd_dat0 : inout std_logic;
sd_dat1 : inout std_logic;
sd_dat2 : inout std_logic;
sd_dat3 : inout std_logic;
sd_cmd : inout std_logic;
sd_clk : inout std_logic;
-- EPCS
epcs_data : in std_ulogic;
epcs_dclk : out std_ulogic;
epcs_csn : out std_ulogic;
epcs_asdi : out std_ulogic
-- Expansion connector on card edge (set as reserved in design's QSF)
--reset_exp_n : out std_logic;
--exp_present : in std_logic;
--p : inout std_logic_vector(64 downto 1)
);
end;
architecture rtl of leon3mp is
constant maxahbm : integer := NCPU+CFG_AHB_JTAG+CFG_GRETH;
constant maxahbs : integer := 6
--pragma translate_off
+1 -- one more in simulation (AHBREP)
--pragma translate_on
;
signal vcc, gnd : std_logic_vector(7 downto 0);
signal clkm, clkml : std_ulogic;
signal lclk, resetn : std_ulogic;
signal clklock, lock : std_ulogic;
signal rstn, rawrstn : std_ulogic;
signal ddr_clkv : std_logic_vector(2 downto 0);
signal ddr_clkbv : std_logic_vector(2 downto 0);
signal ddr_ckev : std_logic_vector(1 downto 0);
signal ddr_csbv : std_logic_vector(1 downto 0);
signal tck : std_ulogic;
signal tckn : std_ulogic;
signal tms : std_ulogic;
signal tdi : std_ulogic;
signal tdo : std_ulogic;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u0i : uart_in_type;
signal u0o : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal spii : spi_in_type;
signal spio : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal spii2 : spi_in_type;
signal spio2 : spi_out_type;
signal slvsel2 : std_logic_vector(0 downto 0);
signal spmi : spimctrl_in_type;
signal spmo : spimctrl_out_type;
signal ethi : eth_in_type;
signal etho : eth_out_type;
constant IOAEN : integer := 1;
constant BOARD_FREQ : integer := 50000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
signal dsu_breakn : std_ulogic;
attribute syn_keep : boolean;
attribute syn_keep of clkm : signal is true;
attribute syn_keep of clkml : signal is true;
begin
vcc <= (others => '1'); gnd <= (others => '0');
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
cgi.pllctrl <= "00"; cgi.pllrst <= not rawrstn; cgi.pllref <= '0';
clklock <= cgo.clklock and lock;
clk_pad : clkpad generic map (tech => padtech)
port map (clk_fpga_50m, lclk);
clkgen0 : clkgen -- clock generator using toplevel generic 'freq'
generic map (
tech => CFG_CLKTECH,
clk_mul => CFG_CLKMUL,
clk_div => CFG_CLKDIV,
sdramen => 0,
freq => freq)
port map (
clkin => lclk,
pciclkin => gnd(0),
clk => clkm,
clkn => open,
clk2x => open,
sdclk => open,
pciclk => open,
cgi => cgi,
cgo => cgo);
reset_pad : inpad generic map (tech => padtech) port map (cpu_rst_n, resetn);
rst0 : rstgen -- reset generator
port map (
rstin => resetn,
clk => clkm,
clklock => clklock,
rstout => rstn,
rstoutraw => rawrstn);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (
defmast => CFG_DEFMST,
split => CFG_SPLIT,
rrobin => CFG_RROBIN,
ioaddr => CFG_AHBIO,
ioen => IOAEN,
nahbm => maxahbm,
nahbs => maxahbs)
port map (
rst => rstn,
clk => clkm,
msti => ahbmi,
msto => ahbmo,
slvi => ahbsi,
slvo => ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (
hindex => i,
fabtech => fabtech,
memtech => memtech,
nwindows => CFG_NWIN,
dsu => CFG_DSU,
fpu => CFG_FPU,
v8 => CFG_V8,
cp => 0,
mac => CFG_MAC,
pclow => pclow,
notag => CFG_NOTAG,
nwp => CFG_NWP,
icen => CFG_ICEN,
irepl => CFG_IREPL,
isets => CFG_ISETS,
ilinesize => CFG_ILINE,
isetsize => CFG_ISETSZ,
isetlock => CFG_ILOCK,
dcen => CFG_DCEN,
drepl => CFG_DREPL,
dsets => CFG_DSETS,
dlinesize => CFG_DLINE,
dsetsize => CFG_DSETSZ,
dsetlock => CFG_DLOCK,
dsnoop => CFG_DSNOOP,
ilram => CFG_ILRAMEN,
ilramsize => CFG_ILRAMSZ,
ilramstart => CFG_ILRAMADDR,
dlram => CFG_DLRAMEN,
dlramsize => CFG_DLRAMSZ,
dlramstart => CFG_DLRAMADDR,
mmuen => CFG_MMUEN,
itlbnum => CFG_ITLBNUM,
dtlbnum => CFG_DTLBNUM,
tlb_type => CFG_TLB_TYPE,
tlb_rep => CFG_TLB_REP,
lddel => CFG_LDDEL,
disas => disas,
tbuf => CFG_ITBSZ,
pwd => CFG_PWD,
svt => CFG_SVT,
rstaddr => CFG_RSTADDR,
smp => NCPU-1,
cached => CFG_DFIXED,
scantest => CFG_SCAN,
mmupgsz => CFG_MMU_PAGE,
bp => CFG_BP,
npasi => CFG_NP_ASI,
pwrpsr => CFG_WRPSR)
port map (
clk => clkm,
rstn => rstn,
ahbi => ahbmi,
ahbo => ahbmo(i),
ahbsi => ahbsi,
ahbso => ahbso,
irqi => irqi(i),
irqo => irqo(i),
dbgi => dbgi(i),
dbgo => dbgo(i));
end generate;
errorn_pad : toutpad generic map (tech => padtech) port map (f_led(6), gnd(0), dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (
hindex => 2,
haddr => 16#900#,
hmask => 16#F00#,
ncpu => NCPU,
tbits => 30,
tech => memtech,
irq => 0,
kbytes => CFG_ATBSZ)
port map (
rst => rstn,
clk => clkm,
ahbmi => ahbmi,
ahbsi => ahbsi,
ahbso => ahbso(2),
dbgi => dbgo,
dbgo => dbgi,
dsui => dsui,
dsuo => dsuo);
dsui.enable <= '1';
dsui.break <= not dsu_breakn; -- Switch polarity
dsubre_pad : inpad generic map (tech => padtech) port map (pbsw_n, dsu_breakn);
dsuact_pad : toutpad generic map (tech => padtech) port map (f_led(7), gnd(0), dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(
rst => rstn,
clk => clkm,
tck => tck,
tms => tms,
tdi => tdi,
tdo => tdo,
ahbi => ahbmi,
ahbo => ahbmo(NCPU+CFG_AHB_UART),
tapo_tck => open,
tapo_tdi => open,
tapo_inst => open,
tapo_rst => open,
tapo_capt => open,
tapo_shft => open,
tapo_upd => open,
tapi_tdo => gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
-- DDR memory controller
ddrsp0 : if (CFG_DDRSP /= 0) generate
ddrc0 : ddrspa
generic map (
fabtech => fabtech,
memtech => memtech,
hindex => 0,
haddr => 16#400#,
hmask => 16#F00#,
ioaddr => 1,
pwron => CFG_DDRSP_INIT,
MHz => BOARD_FREQ/1000,
rskew => CFG_DDRSP_RSKEW,
clkmul => CFG_DDRSP_FREQ/5,
clkdiv => 10,
ahbfreq => CPU_FREQ/1000,
col => CFG_DDRSP_COL,
Mbyte => CFG_DDRSP_SIZE,
ddrbits => 16,
regoutput => 1,
mobile => 0)
port map (
rst_ddr => rawrstn,
rst_ahb => rstn,
clk_ddr => lclk,
clk_ahb => clkm,
lock => lock,
clkddro => clkml,
clkddri => clkml,
ahbsi => ahbsi,
ahbso => ahbso(0),
ddr_clk => ddr_clkv,
ddr_clkb => ddr_clkbv,
ddr_clk_fb_out => open,
ddr_clk_fb => gnd(0),
ddr_cke => ddr_ckev,
ddr_csb => ddr_csbv,
ddr_web => ram_ws_n,
ddr_rasb => ram_ras_n,
ddr_casb => ram_cas_n,
ddr_dm => ram_dm,
ddr_dqs => ram_dqs,
ddr_ad => ram_a,
ddr_ba => ram_ba,
ddr_dq => ram_d);
end generate;
ram_ck_p <= ddr_clkv(0);
ram_ck_n <= ddr_clkbv(0);
ram_cke <= ddr_ckev(0);
ram_cs_n <= ddr_csbv(0);
ddrsp1 : if (CFG_DDRSP = 0) generate
ahbso(0) <= ahbs_none;
lock <= '1';
ddr_clkv <= (others => '0');
ddr_clkbv <= (others => '0');
ddr_ckev <= (others => '1');
ddr_csbv <= (others => '1');
end generate;
-- SPI Memory Controller
spimc: if CFG_SPIMCTRL /= 0 and CFG_AHBROMEN = 0 generate
spimctrl0 : spimctrl
generic map (
hindex => 4,
hirq => 9,
faddr => 16#000#,
fmask => 16#f00#,
ioaddr => 16#002#,
iomask => 16#fff#,
spliten => CFG_SPLIT,
oepol => 0,
sdcard => CFG_SPIMCTRL_SDCARD,
readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => CFG_SPIMCTRL_DUALOUTPUT,
scaler => CFG_SPIMCTRL_SCALER,
altscaler => CFG_SPIMCTRL_ASCALER,
pwrupcnt => CFG_SPIMCTRL_PWRUPCNT,
offset => CFG_SPIMCTRL_OFFSET)
port map (
rstn => rstn,
clk => clkm,
ahbsi => ahbsi,
ahbso => ahbso(4),
spii => spmi,
spio => spmo);
end generate;
epcs_miso_pad : inpad generic map (tech => padtech)
port map (epcs_data, spmi.miso);
epcs_mosi_pad : outpad generic map (tech => padtech)
port map (epcs_asdi, spmo.mosi);
epcs_sck_pad : outpad generic map (tech => padtech)
port map (epcs_dclk, spmo.sck);
epcs_slvsel0_pad : outpad generic map (tech => padtech)
port map (epcs_csn, spmo.csn);
nospimc : if CFG_SPIMCTRL /= 1 or CFG_AHBROMEN /= 0 generate
spmo <= spimctrl_out_none;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
-- AHB/APB bridge
apb0 : apbctrl
generic map (
hindex => 1,
haddr => CFG_APBADDR,
nslaves => 7)
port map (
rst => rstn,
clk => clkm,
ahbi => ahbsi,
ahbo => ahbso(1),
apbi => apbi,
apbo => apbo);
-- 8-bit UART, not connected off-chip, use in loopback with GRMON
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (
pindex => 1,
paddr => 1,
pirq => 2,
console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (
rst => rstn,
clk => clkm,
apbi => apbi,
apbo => apbo(1),
uarti => u0i,
uarto => u0o);
end generate;
u0i.rxd <= '0'; u0i.ctsn <= '0'; u0i.extclk <= '0';
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
-- Interrupt controller
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (
pindex => 2,
paddr => 2,
ncpu => NCPU)
port map (
rst => rstn,
clk => clkm,
apbi => apbi,
apbo => apbo(2),
irqi => irqo,
irqo => irqi);
end generate;
noirqctrl : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
-- Timer unit
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer
generic map (
pindex => 3,
paddr => 3,
pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ,
sbits => CFG_GPT_SW,
ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (
rst => rstn,
clk => clkm,
apbi => apbi,
apbo => apbo(3),
gpti => gpti,
gpto => open);
end generate;
gpti <= gpti_dhalt_drive(dsuo.tstop);
notim : if CFG_GPT_ENABLE = 0 generate
apbo(3) <= apb_none;
end generate;
-- GPIO unit
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate
grgpio0: grgpio
generic map(
pindex => 0,
paddr => 0,
imask => CFG_GRGPIO_IMASK,
nbits => CFG_GRGPIO_WIDTH)
port map(
rst => rstn,
clk => clkm,
apbi => apbi,
apbo => apbo(0),
gpioi => gpioi,
gpioo => gpioo);
end generate;
gpio_pads : iopadvv generic map (tech => padtech, width => 6)
port map (f_led(5 downto 0), gpioo.dout(5 downto 0),
gpioo.oen(5 downto 0), gpioi.din(5 downto 0));
gpioi.din(31 downto 6) <= (others => '0');
nogpio : if CFG_GRGPIO_ENABLE = 0 generate
apbo(0) <= apb_none;
end generate;
-- SPI controller connected to temperature sensor
spic: if CFG_SPICTRL_ENABLE /= 0 generate
spi1 : spictrl
generic map (
pindex => 4,
paddr => 4,
pmask => 16#fff#,
pirq => 9,
fdepth => CFG_SPICTRL_FIFO,
slvselen => CFG_SPICTRL_SLVREG,
slvselsz => CFG_SPICTRL_SLVS,
odmode => CFG_SPICTRL_ODMODE,
automode => CFG_SPICTRL_AM,
aslvsel => CFG_SPICTRL_ASEL,
twen => 1,
maxwlen => CFG_SPICTRL_MAXWLEN,
netlist => 0,
syncram => CFG_SPICTRL_SYNCRAM,
ft => CFG_SPICTRL_FT)
port map (
rstn => rstn,
clk => clkm,
apbi => apbi,
apbo => apbo(4),
spii => spii,
spio => spio,
slvsel => slvsel);
end generate spic;
-- MISO signal not used
spii.miso <= '0';
mosi_pad : iopad generic map (tech => padtech)
port map (temp_sio, spio.mosi, spio.mosioen, spii.mosi);
sck_pad : iopad generic map (tech => padtech)
port map (temp_sc, spio.sck, spio.sckoen, spii.sck);
slvsel_pad : outpad generic map (tech => padtech)
port map (temp_cs_n, slvsel(0));
spii.spisel <= '1'; -- Master only
nospic : if CFG_SPICTRL_ENABLE = 0 generate
apbo(4) <= apb_none;
spio.misooen <= '1';
spio.mosioen <= '1';
spio.sckoen <= '1';
slvsel <= (others => '1');
end generate;
-- SPI controller connected to SD card slot
spic2: if CFG_SPICTRL_ENABLE /= 0 and CFG_SPICTRL_NUM > 1 generate
spi1 : spictrl
generic map (
pindex => 5,
paddr => 5,
pmask => 16#fff#,
pirq => 11,
fdepth => CFG_SPICTRL_FIFO,
slvselen => 1,
slvselsz => 1,
odmode => CFG_SPICTRL_ODMODE,
automode => CFG_SPICTRL_AM,
aslvsel => CFG_SPICTRL_ASEL,
twen => 0,
maxwlen => CFG_SPICTRL_MAXWLEN,
netlist => 0,
syncram => CFG_SPICTRL_SYNCRAM,
ft => CFG_SPICTRL_FT)
port map (
rstn => rstn,
clk => clkm,
apbi => apbi,
apbo => apbo(5),
spii => spii2,
spio => spio2,
slvsel => slvsel2);
miso_pad : iopad generic map (tech => padtech)
port map (sd_dat0, spio2.miso, spio2.misooen, spii2.miso);
mosi_pad : iopad generic map (tech => padtech)
port map (sd_cmd, spio2.mosi, spio2.mosioen, spii2.mosi);
sck_pad : iopad generic map (tech => padtech)
port map (sd_clk, spio2.sck, spio2.sckoen, spii2.sck);
slvsel_pad : outpad generic map (tech => padtech)
port map (sd_dat3, slvsel2(0));
spii2.spisel <= '1'; -- Master only
end generate;
nospic2 : if CFG_SPICTRL_ENABLE = 0 or CFG_SPICTRL_NUM < 2 generate
apbo(5) <= apb_none;
spio2.misooen <= '1';
spio2.mosioen <= '1';
spio2.sckoen <= '1';
slvsel2(0) <= '0';
end generate;
-- sd_dat1 and sd_dat2 are unused
unuseddat1_pad : iopad generic map (tech => padtech)
port map (sd_dat1, gnd(0), vcc(1), open);
unuseddat2_pad : iopad generic map (tech => padtech)
port map (sd_dat2, gnd(0), vcc(1), open);
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH /= 0 generate -- Gaisler Ethernet MAC
e1 : grethm
generic map(
hindex => CFG_NCPU+CFG_AHB_JTAG,
pindex => 6,
paddr => 6,
pirq => 10,
memtech => memtech,
mdcscaler => CPU_FREQ/(4*1000)-1,
enable_mdio => 1,
fifosize => CFG_ETH_FIFO,
nsync => 1,
edcl => CFG_DSU_ETH,
edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM,
macaddrl => CFG_ETH_ENL,
phyrstadr => 1,
ipaddrh => CFG_ETH_IPM,
ipaddrl => CFG_ETH_IPL,
giga => CFG_GRETH1G)
port map(
rst => rstn,
clk => clkm,
ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_JTAG),
apbi => apbi,
apbo => apbo(6),
ethi => ethi,
etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (mdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (tx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (rx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (rxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (rx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (rx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (eth_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (eth_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (txd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (tx_en, etho.tx_en);
emdc_pad : outpad generic map (tech => padtech)
port map (mdc, etho.mdc);
erst_pad : outpad generic map (tech => padtech)
port map (eth_reset_n, rawrstn);
end generate;
noeth : if CFG_GRETH = 0 generate
apbo(6) <= apb_none;
ethi <= eth_in_none;
etho <= eth_out_none;
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (
hindex => 3,
haddr => CFG_AHBRODDR,
pipe => CFG_AHBROPIP)
port map (
rst => rstn,
clk => clkm,
ahbsi => ahbsi,
ahbso => ahbso(3));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(3) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram
generic map (
hindex => 5,
haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH,
kbytes => CFG_AHBRSZ,
pipe => CFG_AHBRPIPE)
port map (
rst => rstn,
clk => clkm,
ahbsi => ahbsi,
ahbso => ahbso(5));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(5) <= ahbs_none; end generate;
-----------------------------------------------------------------------
-- AHB Report Module for simulation ----------------------------------
-----------------------------------------------------------------------
--pragma translate_off
test0 : ahbrep generic map (hindex => 6, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(6));
--pragma translate_on
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
driveahbm : for i in maxahbm to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
driveahbs : for i in maxahbs to NAHBSLV-1 generate
ahbso(i) <= ahbs_none;
end generate;
driveapb : for i in 7 to NAPBSLV-1 generate
apbo(i) <= apb_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 BeMicro SDK Design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-3.0 | ccf226680967ce5db87ff2cdbf4d2007 | 0.477503 | 3.95249 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-digilent-basys3/config.vhd | 1 | 5,903 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := artix7;
constant CFG_MEMTECH : integer := artix7;
constant CFG_PADTECH : integer := artix7;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := artix7;
constant CFG_CLKMUL : integer := (9);
constant CFG_CLKDIV : integer := (10);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (0);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 2;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 2;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 0*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 1 + 64*0;
constant CFG_ATBSZ : integer := 1;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 1;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 0 + 0 + 0;
constant CFG_ETH_BUF : integer := 1;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000009#;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 1;
constant CFG_AHBRSZ : integer := 128;
constant CFG_AHBRADDR : integer := 16#400#;
constant CFG_AHBRPIPE : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 1;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 1;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#0B#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 0;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := (2);
constant CFG_SPIMCTRL_ASCALER : integer := (2);
constant CFG_SPIMCTRL_PWRUPCNT : integer := (0);
constant CFG_SPIMCTRL_OFFSET : integer := 16#0#;
-- GRLIB debugging
constant CFG_DUART : integer := 1;
end;
| gpl-3.0 | acb75e90115ac4fe6a56e1100047ee2d | 0.644418 | 3.655108 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/ddr/ddr1spax_ddr.vhd | 1 | 40,538 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr1spax_ddr
-- File: ddr1spax_ddr.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Merged 16/32/64-bit DDR/mobile-DDR backend
-- Based on ddrsp*a and ddr2spax_ddr
--------------------------------------------------------------------------------
-- Added features from the original ddrspa:
-- * Separated AHB,DDR parts of controller like for DDR2SPA
-- * 64/32/16 bit interfaces in the same entity
-- * Checkbit support for use with ft_ddr2spax_ahb front-end.
-- * Extended timing fields plus tRAS setting to meet DDR400 timing.
-- * Configurable burst length
-- * Support for PHY:s with read data valid signaling and extra latency
-- Incompatibility/differences to the original ddrspa:
-- * The mobile DDR had an undocumented feature that tRFC was extended with 8
-- cycles if the TRP bit was set. This is replaced by the extended
-- timing fields.
-- * ddrsp16a used a separate read-clock supplied only from the Spartan PHY.
-- * Reads/writes are made as multiple length-2 burst commands.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
library gaisler;
use gaisler.ddrpkg.all;
use gaisler.ddrintpkg.all;
entity ddr1spax_ddr is
generic (
ddrbits : integer := 32;
burstlen : integer := 8;
MHz : integer := 100;
col : integer := 9;
Mbyte : integer := 8;
pwron : integer := 0;
oepol : integer := 0;
mobile : integer := 0;
confapi : integer := 0;
conf0 : integer := 0;
conf1 : integer := 0;
nosync : integer := 0;
ddr_syncrst: integer range 0 to 1 := 0;
chkbits : integer := 0;
hasdqvalid : integer := 0;
readdly : integer := 0;
regoutput : integer := 1;
ddr400 : integer := 1;
rstdel : integer := 200;
phyptctrl : integer := 0;
scantest : integer := 0
);
port (
ddr_rst : in std_ulogic;
clk_ddr : in std_ulogic;
request : in ddr_request_type;
start_tog: in std_logic;
response : out ddr_response_type;
sdi : in ddrctrl_in_type;
sdo : out ddrctrl_out_type;
wbraddr : out std_logic_vector(log2((16*burstlen)/ddrbits) downto 0);
wbrdata : in std_logic_vector(2*(ddrbits+chkbits)-1 downto 0);
rbwaddr : out std_logic_vector(log2((16*burstlen)/ddrbits)-1 downto 0);
rbwdata : out std_logic_vector(2*(ddrbits+chkbits)-1 downto 0);
rbwrite : out std_logic;
reqsel : in std_ulogic;
frequest : in ddr_request_type;
response2: out ddr_response_type;
testen : in std_ulogic;
testrst : in std_ulogic;
testoen : in std_ulogic
);
end ddr1spax_ddr;
architecture rtl of ddr1spax_ddr is
constant l2blen: integer := log2(burstlen)+log2(32);
constant l2ddrw: integer := log2(ddrbits*2);
constant l2ddr_burstlen: integer := l2blen-l2ddrw;
-- constant oepols: std_logic := tosl(oepol);
-- Write buffer dimensions
-- Write buffer is addressable down to 32-bit level on write (AHB) side.
constant wbuf_rabits: integer := 1+l2blen-l2ddrw; -- log2((burstlen*32)/(2*ddrbits));
constant wbuf_rdbits: integer := 2*ddrbits;
-- Read buffer dimensions
constant rbuf_wabits: integer := l2blen-l2ddrw; -- log2((burstlen*32)/(2*ddrbits));
constant rbuf_wdbits: integer := 2*(ddrbits+chkbits);
type ddrstate is (dsidle,dsact1,dsact2,dsact3,dswr1,dswr2,dswr3,dswr4,dswr5,dswr6,
dsrd1,dsrd2,dsrd3,dsrd4,dsreg1,dsreg2,dscmd1,dscmd2,dspdown1,dspdown2,dsref1,
dssrr1,dssrr2);
type ddrinitstate is (disrstdel,disidle,disrun,disfinished);
type sdram_cfg_type is record
command : std_logic_vector(2 downto 0);
csize : std_logic_vector(1 downto 0);
bsize : std_logic_vector(2 downto 0);
trcd : std_ulogic; -- tCD : 2/3 clock cycles
trfc : std_logic_vector(4 downto 0);
trp : std_logic_vector(1 downto 0); -- precharge to activate: 2/3 clock cycles
refresh : std_logic_vector(11 downto 0);
renable : std_ulogic;
dllrst : std_ulogic;
refon : std_ulogic;
cke : std_ulogic;
pasr : std_logic_vector(5 downto 0); -- pasr(2:0) (pasr(5:3) used to detect update)
tcsr : std_logic_vector(3 downto 0); -- tcrs(1:0) (tcrs(3:2) used to detect update)
ds : std_logic_vector(5 downto 0); -- ds(1:0) (ds(3:2) used to detect update)
pmode : std_logic_vector(2 downto 0); -- Power-Saving mode
mobileen : std_logic; -- Mobile SD support, Mobile SD enabled
txsr : std_logic_vector(5 downto 0); -- Exit Self Refresh timing
txp : std_logic_vector(1 downto 0); -- Exit Power-Down timing
tcke : std_logic; -- Clock enable timing
cl : std_logic; -- CAS latency 2/3 (0/1)
conf : std_logic_vector(63 downto 0); -- PHY control
tras : std_logic_vector(1 downto 0); -- tRAS minimum (6-9 cycles)
twr : std_logic; -- tWR write recovery, 2/3 cycles
end record;
type ddr_reg_type is record
s : ddrstate;
initstate : ddrinitstate;
cfg : sdram_cfg_type;
resp,resp2 : ddr_response_type;
req1,req2 : ddr_request_type;
start1,start2 : std_logic;
start3 : std_logic;
ramaddr : std_logic_vector(rbuf_wabits-1 downto 0);
readpipe : std_logic_vector(4+readdly downto 0);
initpos : std_logic_vector(2 downto 0);
cmdctr : std_logic_vector(7 downto 0);
readdone : std_logic;
refctr : std_logic_vector(17 downto 0);
refpend : std_logic;
idlectr : std_logic_vector(3 downto 0);
pdowns : std_logic_vector(1 downto 0);
sdo_casn : std_logic;
sdo_rasn : std_logic;
sdo_wen : std_logic;
sdo_csn : std_logic_vector(1 downto 0);
sdo_ba : std_logic_vector(1 downto 0);
sdo_address : std_logic_vector(14 downto 0);
sdo_data : std_logic_vector(2*ddrbits-1 downto 0);
sdo_dqm : std_logic_vector(ddrbits/4-1 downto 0);
sdo_cb : std_logic_vector(2*chkbits downto 0);
sdo_ck : std_logic_vector(2 downto 0);
sdo_bdrive : std_logic;
sdo_qdrive : std_logic;
end record;
signal dr,ndr: ddr_reg_type;
constant onev: std_logic_vector(15 downto 0) := x"FFFF";
constant zerov: std_logic_vector(15 downto 0) := x"0000";
signal arst : std_ulogic;
begin
arst <= testrst when (scantest/=0 and ddr_syncrst=0) and testen='1' else ddr_rst;
ddrcomb: process(ddr_rst,sdi,request,frequest,start_tog,dr,wbrdata,testen,testoen,reqsel)
variable dv: ddr_reg_type;
variable o: ddrctrl_out_type;
variable rbw: std_logic;
variable rbwd: std_logic_vector(2*(ddrbits+chkbits)-1 downto 0);
variable vstart, vstartd, vdone, incdone: std_logic;
variable vrctr: std_logic_vector(3 downto 0);
variable vreq,vreqf: ddr_request_type;
variable regsd1 : std_logic_vector(31 downto 0);
variable regsd2 : std_logic_vector(31 downto 0);
variable regsd3 : std_logic_vector(31 downto 0);
variable lastreadcmd: std_logic;
variable lastwrite : std_logic;
variable vmaskfirst, vmasklast: std_logic_vector(ddrbits/4-1 downto 0);
variable ea: std_logic_vector(3 downto 2);
variable inc_sdoaddr, inc_ramaddr: std_logic;
variable datavalid: std_logic;
variable vcsf: std_logic_vector(1 downto 0);
variable vrowf: std_logic_vector(14 downto 0);
variable vbankf: std_logic_vector(1 downto 0);
variable vcol,vcoladdr: std_logic_vector(14 downto 1);
variable seqin,seqout: std_logic_vector(3 downto 0);
variable regrdata: std_logic_vector(2*ddrbits-1 downto 0);
variable regad: std_logic_vector(2 downto 0);
variable wrdreg1,wrdreg2,wrdreg3: std_logic_vector(31 downto 0);
variable reqselv: std_logic_vector(3 downto 0);
begin
---------------------------------------------------------------------------
-- Init vars
---------------------------------------------------------------------------
dv := dr;
o := ddrctrl_out_none;
o.bdrive := '1'; o.qdrive := '1';
vdone := dr.resp.done_tog or dr.resp2.done_tog;
vrctr := dr.resp.rctr_gray or dr.resp2.rctr_gray;
incdone := '0';
lastreadcmd := '0';
lastwrite := '0';
reqselv := reqsel & reqsel & reqsel & reqsel;
-- Config registers
regsd1 := (others => '0');
regsd1(31 downto 15) := dr.cfg.refon & dr.cfg.trp(0) & dr.cfg.trfc(2 downto 0) &
dr.cfg.trcd & dr.cfg.bsize & dr.cfg.csize & dr.cfg.command &
dr.cfg.dllrst & dr.cfg.renable & dr.cfg.cke;
regsd1(11 downto 0) := dr.cfg.refresh;
regsd2 := (others => '0');
regsd2(8 downto 0) := conv_std_logic_vector(MHz, 9);
regsd2(14 downto 12) := conv_std_logic_vector(log2(ddrbits/8),3);
if mobile/=0 then regsd2(15):='1'; end if;-- Mobile DDR support
regsd2(19 downto 16) := conv_std_logic_vector(confapi, 4);
regsd3 := (others => '0');
regsd3(31) := dr.cfg.mobileen; -- Mobile DDR enable
regsd3(30) := dr.cfg.cl;
regsd3(24 downto 19) := dr.cfg.tcke & dr.cfg.txsr(3 downto 0) & dr.cfg.txp(0);
regsd3(18 downto 16) := dr.cfg.pmode;
regsd3( 7 downto 0) := dr.cfg.ds(2 downto 0) & dr.cfg.tcsr(1 downto 0)
& dr.cfg.pasr(2 downto 0);
-- Extended timing fields for DDR400
if ddr400 /= 0 then
regsd2(20) := '1'; -- Ext. fields available
regsd3(29 downto 28) := dr.cfg.tras;
regsd3(27 downto 26) := dr.cfg.txsr(5 downto 4);
regsd3(25) := dr.cfg.txp(1);
regsd3(11) := dr.cfg.twr;
regsd3(10) := dr.cfg.trp(1);
regsd3(9 downto 8) := dr.cfg.trfc(4 downto 3);
end if;
-- Data path
rbw := '0';
rbwd := (others => '0');
rbwd(ddrbits-1 downto 0) := sdi.data(ddrbits-1 downto 0);
rbwd(2*ddrbits+chkbits-1 downto ddrbits+chkbits) :=
sdi.data(2*ddrbits-1 downto ddrbits);
if chkbits > 0 then
rbwd(ddrbits+chkbits-1 downto ddrbits) := sdi.cb(chkbits-1 downto 0);
rbwd(2*(ddrbits+chkbits)-1 downto 2*ddrbits+chkbits) :=
sdi.cb(2*chkbits-1 downto chkbits);
end if;
dv.sdo_data(ddrbits-1 downto 0) := wbrdata(ddrbits-1 downto 0);
dv.sdo_data(2*ddrbits-1 downto ddrbits) :=
wbrdata(2*ddrbits+chkbits-1 downto ddrbits+chkbits);
dv.sdo_cb(chkbits) := '0'; -- dummy bit just to ensure length>0
if chkbits > 0 then
dv.sdo_cb(chkbits-1 downto 0) := wbrdata(ddrbits+chkbits-1 downto ddrbits);
dv.sdo_cb(2*chkbits-1 downto chkbits) :=
wbrdata(2*(ddrbits+chkbits)-1 downto 2*ddrbits+chkbits);
end if;
---------------------------------------------------------------------------
-- Request handling logic
---------------------------------------------------------------------------
-- Sync request inputs
dv.req1 := request;
dv.req2 := dr.req1;
dv.start1 := start_tog;
dv.start2 := dr.start1;
dv.start3 := dr.start2;
vstart := dr.start2;
vstartd := dr.start3;
vreq := dr.req2;
vreqf := dr.req1;
if nosync/=0 then
vstart:=start_tog;
vstartd:=start_tog;
vreq:=request;
vreqf:=request;
end if;
if nosync > 1 then
vreqf := frequest;
end if;
-- Address muxing
vcsf(0) := genmux(dr.cfg.bsize, vreqf.startaddr(30 downto 23));
vcsf(1) := not vcsf(0);
vbankf := genmux(dr.cfg.bsize, vreqf.startaddr(29 downto 22)) &
genmux(dr.cfg.bsize, vreqf.startaddr(28 downto 21));
case dr.cfg.csize is
when "00" => vrowf := vreqf.startaddr(19+l2ddrw downto 5+l2ddrw);
when "01" => vrowf := vreqf.startaddr(20+l2ddrw downto 6+l2ddrw);
when "10" => vrowf := vreqf.startaddr(21+l2ddrw downto 7+l2ddrw);
when others => vrowf := vreqf.startaddr(22+l2ddrw downto 8+l2ddrw);
end case;
vcol := vreq.startaddr(l2ddrw+10 downto l2ddrw-3);
-- vcoladdr==vcol when dr.ramaddr==lsb of vcol
vcoladdr := vcol(14 downto rbuf_wabits+1) & dr.ramaddr;
-- Generate data mask
-- Mask for 32-bit and larger bursts and single access
vmaskfirst := (others => '0');
vmasklast := (others => '0');
ea := vreq.endaddr(3 downto 2);
if vreq.hsize(1 downto 0)="11" then ea(2):='1'; end if;
if vreq.hsize(2)='1' then ea(3 downto 2):="11"; end if;
case ddrbits is
when 64 =>
-- 64-bit DDR width
case vreq.startaddr(3 downto 2) is
when "11" => vmaskfirst := "1111111111110000";
when "10" => vmaskfirst := "1111111100000000";
when "01" => vmaskfirst := "1111000000000000";
when others => vmaskfirst := "0000000000000000";
end case;
case ea(3 downto 2) is
when "11" => vmasklast := "0000000000000000";
when "10" => vmasklast := "0000000000001111";
when "01" => vmasklast := "0000000011111111";
when others => vmasklast := "0000111111111111";
end case;
if vreq.hsize(2 downto 1)="00" then
if vreq.startaddr(1)='1' then
vmaskfirst := vmaskfirst or "1100110011001100";
else
vmaskfirst := vmaskfirst or "0011001100110011";
end if;
end if;
if vreq.hsize="000" then
if vreq.startaddr(0)='1' then
vmaskfirst := vmaskfirst or "1010101010101010";
else
vmaskfirst := vmaskfirst or "0101010101010101";
end if;
end if;
when 32 =>
-- 32-bit DDR width
case vreq.startaddr(2) is
when '1' => vmaskfirst := "11110000";
when others => vmaskfirst := "00000000";
end case;
case ea(2) is
when '1' => vmasklast := "00000000";
when others => vmasklast := "00001111";
end case;
if vreq.hsize(2 downto 1)="00" then
if vreq.startaddr(1)='1' then
vmaskfirst := vmaskfirst or "11001100";
else
vmaskfirst := vmaskfirst or "00110011";
end if;
end if;
if vreq.hsize="000" then
if vreq.startaddr(0)='1' then
vmaskfirst := vmaskfirst or "10101010";
else
vmaskfirst := vmaskfirst or "01010101";
end if;
end if;
when others =>
-- 16-bit DDR width
if vreq.hsize(2 downto 1)="00" then
if vreq.startaddr(1)='1' then
vmaskfirst := vmaskfirst or "1100";
else
vmaskfirst := vmaskfirst or "0011";
end if;
end if;
if vreq.hsize="000" then
if vreq.startaddr(0)='1' then
vmaskfirst := vmaskfirst or "1010";
else
vmaskfirst := vmaskfirst or "0101";
end if;
end if;
end case;
-- Register read/write data muxing
regrdata := (others => '0');
case ddrbits is
when 64 =>
regad := vreq.startaddr(4 downto 2);
regrdata := regsd1 & regsd2 & regsd3 & x"00000000";
if confapi /= 0 and regad(2)='1' then
regrdata(95 downto 32) := dr.cfg.conf(31 downto 0) & dr.cfg.conf(63 downto 32);
end if;
wrdreg1 := wbrdata(128+chkbits-1 downto 96+chkbits);
wrdreg2 := wbrdata(96+chkbits-1 downto 64+chkbits);
wrdreg3 := wbrdata(63 downto 32);
when 32 =>
regad := dr.ramaddr(1 downto 0) & vreq.startaddr(2);
if regad(1)='0' then
regrdata := regsd1 & regsd2;
if confapi /= 0 and regad(2)='1' then
regrdata := regsd1 & dr.cfg.conf(31 downto 0);
end if;
else
regrdata := regsd3 & regsd2;
if confapi /= 0 and regad(2)='1' then
regrdata := dr.cfg.conf(63 downto 0);
end if;
end if;
wrdreg1 := wbrdata(64+chkbits-1 downto 32+chkbits);
wrdreg2 := wbrdata(31 downto 0);
wrdreg3 := wbrdata(64+chkbits-1 downto 32+chkbits);
when others =>
regad := dr.ramaddr(2 downto 0);
case regad is
when "000"|"100" => regrdata := regsd1;
when "001" => regrdata := regsd2;
when "010" => regrdata := regsd3;
when "101" =>
if confapi /= 0 then
regrdata := dr.cfg.conf(31 downto 0);
else
regrdata := regsd2;
end if;
when "110" =>
if confapi /= 0 then
regrdata := dr.cfg.conf(63 downto 32);
else
regrdata := regsd3;
end if;
when others => regrdata := regsd3;
end case;
wrdreg1 := wbrdata(31+chkbits downto 16+chkbits) & wbrdata(15 downto 0);
wrdreg2 := wbrdata(31+chkbits downto 16+chkbits) & wbrdata(15 downto 0);
wrdreg3 := wbrdata(31+chkbits downto 16+chkbits) & wbrdata(15 downto 0);
end case;
---------------------------------------------------------------------------
-- Main DDR-SDRAM access FSM
---------------------------------------------------------------------------
dv.sdo_ck := "111";
dv.sdo_rasn := '1';
dv.sdo_casn := '1';
dv.sdo_wen := '1';
dv.sdo_dqm := (others => '1');
dv.sdo_bdrive := '1';
dv.sdo_qdrive := '1';
inc_sdoaddr := '0';
inc_ramaddr := '0';
dv.readpipe := dr.readpipe(3+readdly downto 0) & '0';
datavalid := '0';
if hasdqvalid/=0 then
datavalid := sdi.datavalid;
if dr.s/=dsrd1 and dr.s/=dsrd2 and dr.s/=dsrd3 and dr.s/=dsrd4 and dr.s/=dssrr2 then
datavalid := '0';
end if;
end if;
if hasdqvalid=0 then
if dr.cfg.cl='0' then
datavalid := dr.readpipe(3+readdly);
else
datavalid := dr.readpipe(4+readdly);
end if;
end if;
if datavalid='1' and dr.s/=dsidle then
inc_ramaddr := '1';
rbw := '1';
vrctr(l2ddr_burstlen-1 downto 0) :=
nextgray(vrctr(l2ddr_burstlen-1 downto 0));
if dr.ramaddr=onev(dr.ramaddr'length-1 downto 0) then
dv.readdone := '1';
incdone:='1';
vrctr := "0000";
end if;
end if;
if dr.sdo_address((l2blen-l2ddrw) downto 1)=onev((l2blen-l2ddrw) downto 1) then
lastreadcmd := '1';
end if;
if dr.ramaddr=vreq.endaddr((l2blen-3)-1 downto (l2ddrw-3)) then
lastwrite := '1';
end if;
-- Update EMR when ds, tcsr or pasr change
if dr.cfg.command="000" and
( dr.cfg.ds(2 downto 0) /= dr.cfg.ds(5 downto 3) or
dr.cfg.tcsr(1 downto 0) /= dr.cfg.tcsr(3 downto 2) or
dr.cfg.pasr(2 downto 0) /= dr.cfg.pasr(5 downto 3) ) then
dv.cfg.command := "111";
end if;
-- Auto-refresh counter
dv.refctr := std_logic_vector(unsigned(dr.refctr)+1);
if (dr.refctr(11 downto 0)=dr.cfg.refresh and dr.cfg.refon='1') then
dv.refpend := '1';
dv.refctr := (others => '0');
end if;
if dr.initstate/=disrstdel and (dr.cfg.refon='0' or dr.cfg.pmode(1)='1') then
dv.refpend := '0';
dv.refctr := (others => '0');
end if;
dv.idlectr := "0000";
dv.pdowns(0) := '0';
if not (dr.cmdctr=(dr.cmdctr'range => '0')) and dr.pdowns(0)='0' then
dv.cmdctr := std_logic_vector(unsigned(dr.cmdctr)-1);
end if;
case dr.s is
when dsidle =>
vrctr := "0000";
dv.sdo_ck := "111";
if dr.cfg.pmode /= "000" then
dv.idlectr := std_logic_vector(unsigned(dr.idlectr)+1);
end if;
dv.sdo_csn := "11";
if dr.refpend='1' then
dv.sdo_csn := "00";
dv.sdo_rasn := '0';
dv.sdo_casn := '0';
dv.s := dsref1;
dv.refpend := '0';
elsif vstart /= vdone and dr.cfg.renable='0' then
-- Transfer
dv.sdo_csn := vcsf;
dv.sdo_address := vrowf;
dv.sdo_ba := vbankf;
dv.sdo_rasn := '0' or vreqf.hio;
dv.s := dsact1;
elsif dr.cfg.command /= "000" then
dv.s := dscmd1;
elsif dr.idlectr="1111" then
dv.s := dspdown1;
end if;
when dsact1 =>
dv.ramaddr := vcol(rbuf_wabits downto 1);
if ddr400 /= 0 then
dv.cmdctr(2 downto 0) := "1" & dr.cfg.tras; -- t(RAS)-2t(CK) = TRAS+6-2 = TRAS+4
else
dv.cmdctr(2 downto 0) := "10" & dr.cfg.trcd;
end if;
dv.readdone := '0';
if dr.cfg.trcd='1' then
dv.s := dsact2;
else
dv.s := dsact3;
end if;
if vreq.hio='1' then
dv.s := dsreg1;
end if;
when dsact2 =>
dv.s := dsact3;
when dsact3 =>
dv.sdo_casn := '0';
dv.sdo_wen := not vreq.hwrite;
dv.sdo_qdrive := not vreq.hwrite;
-- dv.sdo_address := vcol(12 downto 10) & '0' & vcol(9 downto 1) & '0';
-- Since part of column is stored in ramaddr in dsact1, use that to
-- reduce fanout on vreq.startaddr
dv.sdo_address := vcoladdr(13 downto 10) & '0' & vcoladdr(9 downto 1) & '0';
if vreq.hwrite='1' then
dv.s := dswr1;
else
dv.s := dsrd1;
dv.readpipe(0) := '1';
end if;
when dswr1 =>
-- NOP,NOP,[WR]: issue either WR+D or NOP+D
dv.sdo_bdrive := '0';
dv.sdo_qdrive := '0';
inc_sdoaddr := '1';
inc_ramaddr := '1';
if lastwrite='1' then
dv.sdo_dqm := vmaskfirst or vmasklast;
dv.s := dswr3;
else
dv.sdo_casn := '0';
dv.sdo_wen := '0';
dv.sdo_dqm := vmaskfirst;
dv.s := dswr2;
end if;
when dswr2 =>
dv.sdo_dqm := (others => '0');
dv.sdo_bdrive := '0';
dv.sdo_qdrive := '0';
inc_sdoaddr := '1';
inc_ramaddr := '1';
if lastwrite='0' then
dv.sdo_casn := '0';
dv.sdo_wen := '0';
else
dv.s := dswr3;
dv.sdo_dqm := vmasklast;
end if;
when dswr3 =>
-- ...,WR+D,WR+D,[NOP+D]: issue NOP
dv.sdo_qdrive := '0';
dv.sdo_dqm := (others => '1');
dv.s := dswr4;
incdone := '1';
when dswr4 =>
-- Issue more NOP:s to meet tWR
dv.idlectr := std_logic_vector(unsigned(dr.idlectr)+1);
if dr.idlectr(0)=dr.cfg.twr then
dv.s := dswr5;
end if;
when dswr5 =>
-- Issue NOP:s until tRAS met.
if dr.cmdctr(2 downto 0)="000" then
dv.sdo_rasn := '0';
dv.sdo_wen := '0';
dv.s := dswr6;
end if;
when dswr6 =>
-- PRE: issue one or two NOP:s depending on trp setting
if dr.idlectr(1 downto 0)=dr.cfg.trp then
dv.s := dsidle;
else
dv.idlectr := std_logic_vector(unsigned(dr.idlectr)+1);
end if;
when dsrd1 =>
inc_sdoaddr := '1';
if lastreadcmd='0' then
dv.sdo_casn := '0';
dv.readpipe(0):='1';
elsif dr.cmdctr(2 downto 0)="000" then
dv.sdo_rasn := '0';
dv.sdo_wen := '0';
dv.s := dsrd3;
else
dv.s := dsrd2;
end if;
when dsrd2 =>
if dr.cmdctr(2 downto 0)="000" then
dv.sdo_rasn := '0';
dv.sdo_wen := '0';
dv.s := dsrd3;
end if;
when dsrd3 =>
if dr.idlectr(1 downto 0)=dr.cfg.trp then
if dv.readdone='1' then
dv.s := dsidle;
else
dv.s := dsrd4;
end if;
else
dv.idlectr := std_logic_vector(unsigned(dr.idlectr)+1);
end if;
when dsrd4 =>
if dv.readdone='1' then
dv.s := dsidle;
end if;
when dsreg1 =>
rbw := '1';
rbwd(2*ddrbits+chkbits-1 downto ddrbits+chkbits) := regrdata(2*ddrbits-1 downto ddrbits);
rbwd(ddrbits-1 downto 0) := regrdata(ddrbits-1 downto 0);
if vreq.hwrite='1' then
dv.s := dsreg2;
elsif regad="100" and dr.cfg.mobileen='1' then
dv.sdo_address := (others => '0');
dv.sdo_ba := "01";
dv.sdo_csn := "10";
dv.sdo_rasn := '0';
dv.sdo_casn := '0';
dv.sdo_wen := '0';
dv.s := dssrr1;
dv.cmdctr(0) := '1';
null;
else
incdone := '1';
dv.s := dsidle;
end if;
when dsreg2 =>
case regad is
when "000" =>
dv.cfg.refon := wrdreg1(31);
dv.cfg.trp(0) := wrdreg1(30);
dv.cfg.trfc(2 downto 0) := wrdreg1(29 downto 27);
dv.cfg.trcd := wrdreg1(26);
dv.cfg.bsize := wrdreg1(25 downto 23);
dv.cfg.csize := wrdreg1(22 downto 21);
dv.cfg.command := wrdreg1(20 downto 18);
dv.cfg.dllrst := wrdreg1(17);
dv.cfg.renable := wrdreg1(16);
dv.cfg.cke := wrdreg1(15);
dv.cfg.refresh := wrdreg1(11 downto 0);
when "010" =>
dv.cfg.mobileen := wrdreg3(31);
dv.cfg.cl := wrdreg3(30);
dv.cfg.tcke := wrdreg3(24);
dv.cfg.txsr(3 downto 0) := wrdreg3(23 downto 20);
dv.cfg.txp(0) := wrdreg3(19);
dv.cfg.pmode := wrdreg3(18 downto 16);
dv.cfg.ds (5 downto 3) := wrdreg3(7 downto 5);
dv.cfg.tcsr(3 downto 2) := wrdreg3(4 downto 3);
dv.cfg.pasr(5 downto 3) := wrdreg3(2 downto 0);
-- Extended DDR400 fields
dv.cfg.tras := wrdreg3(29 downto 28);
dv.cfg.txsr(5 downto 4) := wrdreg3(27 downto 26);
dv.cfg.txp(1) := wrdreg3(25);
dv.cfg.twr := wrdreg3(11);
dv.cfg.trp(1) := wrdreg3(10);
dv.cfg.trfc(4 downto 3) := wrdreg3(9 downto 8);
when "101" =>
if confapi /= 0 then
dv.cfg.conf(31 downto 0) := wrdreg2;
end if;
when "110" =>
if confapi /= 0 then
dv.cfg.conf(63 downto 32) := wrdreg3;
end if;
when others =>
null;
end case;
incdone := '1';
dv.s := dsidle;
when dscmd1 =>
dv.sdo_csn := (others => '0');
dv.sdo_address(10) := '1';
dv.cfg.command := "000";
dv.s := dscmd2;
case dr.cfg.command is
when "010" => -- PRECHARGE ALL
dv.sdo_rasn := '0';
dv.sdo_wen := '0';
dv.cmdctr(1 downto 0) := "11";
when "100" => -- AUTO-REFRESH
dv.sdo_rasn := '0';
dv.sdo_casn := '0';
dv.cmdctr(4 downto 0) := dr.cfg.trfc;
when "110" => -- MODE REGISTER
dv.sdo_rasn := '0';
dv.sdo_casn := '0';
dv.sdo_wen := '0';
dv.sdo_ba := "00";
dv.sdo_address := "00000000" & "01" & dr.cfg.cl & "0001";
if dr.cfg.mobileen='0' then
dv.sdo_address(8) := dr.cfg.dllrst;
end if;
if dr.cfg.dllrst='1' then
dv.cmdctr := std_logic_vector(to_unsigned(200,dr.cmdctr'length));
end if;
when "111" => -- EXT. MODE REGISTER
dv.sdo_rasn := '0';
dv.sdo_casn := '0';
dv.sdo_wen := '0';
if dr.cfg.mobileen='1' then
dv.sdo_ba := "10";
dv.sdo_address := "0000000" & dr.cfg.ds(5 downto 3) & dr.cfg.tcsr(3 downto 2)
& dr.cfg.pasr(5 downto 3);
else
dv.sdo_ba := "01";
dv.sdo_address := "000000000000000"; -- bit0=0 -> DLL enable
end if;
dv.cfg.pasr(2 downto 0) := dr.cfg.pasr(5 downto 3);
dv.cfg.ds(2 downto 0) := dr.cfg.ds(5 downto 3);
dv.cfg.tcsr(1 downto 0) := dr.cfg.tcsr(3 downto 2);
when others => null;
end case;
when dscmd2 =>
if dr.cmdctr=(dr.cmdctr'range => '0') then
dv.s := dsidle;
end if;
when dspdown1 =>
dv.sdo_csn := "00";
if dr.cfg.pmode(0)='1' or dr.cfg.pmode(1)='1' then
dv.cfg.cke := '0';
end if;
if dr.cfg.pmode(1)='1' then
dv.sdo_rasn := '0';
dv.sdo_casn := '0';
end if;
if dr.cfg.pmode(2)='1' and dr.cfg.pmode(0)='1' then
dv.sdo_wen := '0';
end if;
if dr.cfg.pmode(0)='1' then
dv.cmdctr(1 downto 0) := dr.cfg.txp;
end if;
if dr.cfg.pmode(1)='1' then
if dr.cfg.mobileen='1' then
dv.cmdctr(5 downto 0) := dr.cfg.txsr;
else
dv.cmdctr(7 downto 0) := std_logic_vector(to_unsigned(200,8));
end if;
end if;
dv.pdowns(1) := '0';
dv.s := dspdown2;
when dspdown2 =>
dv.pdowns(0) := '1';
if dr.pdowns(0)='0' and dr.cmdctr=(dr.cmdctr'range => '0') then
dv.pdowns(1):='1';
end if;
if dr.cfg.pmode(2)='1' and dr.cfg.pmode(0)='0' then
dv.sdo_ck := "000";
end if;
if dr.cfg.pmode(1)='1' then
dv.refpend := '1';
end if;
if (dr.refpend='1' and dr.cfg.pmode(1)='0') or vstart /= vdone then
if (dr.pdowns(0) or not dr.cfg.tcke)='1' then
dv.cfg.cke := '1';
if dr.pdowns(1)='1' then
dv.s := dsidle;
else
dv.s := dscmd2;
dv.pdowns(0) := '0';
end if;
end if;
end if;
when dsref1 =>
dv.s := dscmd2;
dv.cmdctr(4 downto 0) := dr.cfg.trfc;
when dssrr1 =>
if dr.cmdctr(0)='0' then
dv.sdo_casn := '0';
dv.readpipe(0):='1';
dv.s := dssrr2;
end if;
when dssrr2 =>
if datavalid='1' then
incdone := '1';
dv.s := dsidle;
end if;
end case;
if inc_sdoaddr='1' then
dv.sdo_address(l2blen-l2ddrw downto 1) :=
std_logic_vector(unsigned(dr.sdo_address(l2blen-l2ddrw downto 1))+1);
end if;
if inc_ramaddr='1' then
dv.ramaddr := std_logic_vector(unsigned(dr.ramaddr)+1);
end if;
-- Update the done flags
dv.resp.done_tog := (dr.resp.done_tog xor incdone) and (not reqsel);
dv.resp.rctr_gray := vrctr and (not reqselv);
dv.resp2.done_tog := (dr.resp2.done_tog xor incdone) and reqsel;
dv.resp2.rctr_gray := vrctr and reqselv;
---------------------------------------------------------------------------
-- DDR Init Sequence FSM
---------------------------------------------------------------------------
-- Command sequence lookup table
seqin := dr.cfg.mobileen & dr.initpos;
case seqin is
-- Mobile DDR
when "1100" => seqout := "0010"; -- PRECHARGE ALL
when "1011" => seqout := "0100"; -- AUTO REFRESH #1
when "1010" => seqout := "0100"; -- AUTO REFRESH #2
when "1001" => seqout := "0110"; -- MODE REG
when "1000" => seqout := "0111"; -- EXT MODE REG
-- Normal DDR
when "0110" => seqout := "0010"; -- PRECHARGE ALL
when "0101" => seqout := "0111"; -- EXT MODE REG En DLL
when "0100" => seqout := "1110"; -- MODE REG Rst DLL
when "0011" => seqout := "0010"; -- PRECHARGE ALL
when "0010" => seqout := "0100"; -- AUTO REFRESH #1
when "0001" => seqout := "0100"; -- AUTO REFRESH #2
when "0000" => seqout := "0110"; -- MODE REG NoRst DLL
when others => seqout := "0000";
end case;
case dr.initstate is
when disrstdel =>
if dr.refctr=std_logic_vector(to_unsigned(MHz*rstdel,dr.refctr'length)) then
dv.initstate := disidle;
if pwron=0 then dv.cfg.renable:='0'; end if;
end if;
-- Bypass reset delay by writing anything to regsd2
if vstartd='1' and (vreq.hio='1' and vreq.hwrite='1' and vreq.endaddr(4 downto 2)="001") then
dv.initstate := disidle;
if pwron=0 then dv.cfg.renable:='0'; end if;
end if;
when disidle =>
if dr.cfg.renable='1' then
dv.cfg.cke := '1';
if dr.cfg.cke='1' then
dv.initpos := "111";
dv.initstate := disrun;
end if;
end if;
when disrun =>
if dr.cfg.command="000" then
dv.cfg.dllrst := seqout(3);
dv.cfg.command := seqout(2 downto 0);
dv.initpos := std_logic_vector(unsigned(dr.initpos)-1);
if dr.initpos="000" then
dv.initstate := disfinished;
end if;
end if;
when disfinished =>
if dr.cfg.command="000" then
dv.cfg.renable := '0';
dv.cfg.refon := '1';
dv.initstate := disidle;
end if;
end case;
---------------------------------------------------------------------------
-- Reset
---------------------------------------------------------------------------
if ddr_rst='0' then
dv.s := dsidle;
dv.cmdctr := (others => '0');
dv.refctr := (others => '0');
dv.resp := ddr_response_none;
dv.resp2 := ddr_response_none;
dv.initstate := disrstdel;
dv.refpend := '0';
-- Reset cfg record
dv.cfg.command := "000";
dv.cfg.csize := conv_std_logic_vector(col-9, 2);
dv.cfg.bsize := conv_std_logic_vector(log2(Mbyte/8), 3);
dv.cfg.refon := '0';
dv.cfg.refresh := conv_std_logic_vector(7800*MHz/1000, 12);
dv.cfg.dllrst := '0';
dv.cfg.pasr := (others => '0');
dv.cfg.tcsr := (others => '0');
dv.cfg.ds := (others => '0');
dv.cfg.pmode := (others => '0');
dv.cfg.txsr := conv_std_logic_vector(120*MHz/1000, 6);
dv.cfg.txp := "01";
dv.cfg.cl := '0'; -- CL = 3/2 -- ****
dv.cfg.tcke := '1';
if MHz > 100 then
dv.cfg.trcd := '1';
else dv.cfg.trcd := '0';
end if;
if MHz > 100 then
dv.cfg.trp := "01";
else dv.cfg.trp := "00";
end if;
dv.cfg.renable := '1'; -- Updated in disrstdel state
if mobile >= 2 then
dv.cfg.mobileen := '1'; -- Default: Mobile DDR
else dv.cfg.mobileen := '0';
end if;
if mobile >= 2 then
dv.cfg.trfc := conv_std_logic_vector(98*MHz/1000-2, 5);
else dv.cfg.trfc := conv_std_logic_vector(75*MHz/1000-2, 5);
end if;
if ddr_syncrst /= 0 then
dv.sdo_ck := "000";
if mobile >= 2 then
dv.cfg.cke := '1';
else dv.cfg.cke := '0';
end if;
end if;
if confapi /= 0 then
dv.cfg.conf(31 downto 0) := conv_std_logic_vector(conf0, 32); --x"0000A0A0";
dv.cfg.conf(63 downto 32) := conv_std_logic_vector(conf1, 32); --x"00060606";
else
dv.cfg.conf := (others => '0');
end if;
if MHz > 175 then
dv.cfg.tras := "10";
elsif MHz > 150 then
dv.cfg.tras := "01";
else
dv.cfg.tras := "00";
end if;
if MHz > 133 then
dv.cfg.twr := '1';
else
dv.cfg.twr := '0';
end if;
dv.sdo_csn := "11";
dv.sdo_dqm := (others => '1');
dv.sdo_wen := '1';
dv.sdo_rasn := '1';
dv.sdo_casn := '1';
-- Extra reset for X-sensitive techs
dv.ramaddr := (others => '0');
end if;
---------------------------------------------------------------------------
-- Static logic/forced regs, etc
---------------------------------------------------------------------------
-- Force mobile disable/enabled
if mobile=0 then dv.cfg.mobileen := '0'; end if;
if mobile=3 then dv.cfg.mobileen := '1'; end if;
if mobile=0 then
dv.cfg.pasr := (others => '0');
dv.cfg.tcsr := (others => '0');
dv.cfg.ds := (others => '0');
dv.cfg.pmode := (others => '0');
dv.cfg.txp := "00";
dv.cfg.txsr := (others => '0');
dv.cfg.tcke := '0';
end if;
if ddr400=0 then
dv.cfg.tras := "00";
dv.cfg.txsr(5 downto 4) := "00";
dv.cfg.txp(1) := '0';
dv.cfg.trp(1) := '0';
dv.cfg.trfc(4 downto 3) := "00";
dv.cfg.twr := '0';
end if;
-- Assign sdo
o.bdrive := '1'; o.qdrive := '1'; --Temp.
o.sdck := dr.sdo_ck;
if ddr_syncrst/=0 and phyptctrl/=0 then
o.sdck := o.sdck and (o.sdck'range => ddr_rst);
end if;
if regoutput /= 0 then
o.casn := dr.sdo_casn;
o.rasn := dr.sdo_rasn;
o.sdwen := dr.sdo_wen;
o.sdcsn := dr.sdo_csn;
o.ba := '0' & dr.sdo_ba;
o.address := dr.sdo_address;
o.sdcke := (others => dr.cfg.cke);
if ddr_syncrst /= 0 and phyptctrl /= 0 then
if ddr_rst='0' then
if mobile >= 2 then o.sdcke := (others => '1');
else o.sdcke := (others => '0');
end if;
end if;
end if;
o.data(2*ddrbits-1 downto 0) := dr.sdo_data;
o.dqm(ddrbits/4-1 downto 0) := dr.sdo_dqm;
if chkbits > 0 then
o.cb(2*chkbits-1 downto 0) := dr.sdo_cb(2*chkbits-1 downto 0);
end if;
o.bdrive := dr.sdo_bdrive;
o.qdrive := dr.sdo_qdrive;
else
o.casn := dv.sdo_casn;
o.rasn := dv.sdo_rasn;
o.sdwen := dv.sdo_wen;
o.sdcsn := dv.sdo_csn;
o.ba := '0' & dv.sdo_ba;
o.address := dv.sdo_address;
o.sdcke := (others => dv.cfg.cke);
o.data(2*ddrbits-1 downto 0) := dv.sdo_data;
o.dqm(ddrbits/4-1 downto 0) := dv.sdo_dqm;
if chkbits > 0 then
o.cb(2*chkbits-1 downto 0) := dv.sdo_cb(2*chkbits-1 downto 0);
end if;
o.bdrive := dv.sdo_bdrive;
o.qdrive := dv.sdo_qdrive;
end if;
for x in 7 downto 0 loop
o.cbdqm(x) := o.dqm(2*x);
end loop;
-- Diag access
if vreq.maskcb='1' then
o.cbdqm := (others => '1');
end if;
if vreq.maskdata='1' then
o.dqm := (others => '1');
end if;
if scantest/=0 and phyptctrl/=0 then
if testen='1' then
o.bdrive := testoen;
o.qdrive := testoen;
end if;
end if;
---------------------------------------------------------------------------
-- Drive outputs
---------------------------------------------------------------------------
ndr <= dv;
sdo <= o;
response <= dr.resp;
response2 <= dr.resp2;
rbwrite <= rbw;
rbwaddr <= dr.ramaddr;
rbwdata <= rbwd;
wbraddr <= vdone & dv.ramaddr;
end process;
ddrregs: process(clk_ddr,arst)
begin
if rising_edge(clk_ddr) then
dr <= ndr;
end if;
if ddr_syncrst=0 and arst='0' then
dr.sdo_ck <= "000";
if mobile >= 2 then
dr.cfg.cke <= '1';
else dr.cfg.cke <= '0';
end if;
end if;
end process;
end;
| gpl-3.0 | 2d7440fc06f6f1ec4782a95534b6d8cd | 0.508905 | 3.521063 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/altera_mf/memory_altera_mf.vhd | 1 | 11,616 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: mem_altera_gen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Memory generators for Altera altsynram
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library altera_mf;
use altera_mf.altsyncram;
-- pragma translate_on
entity altera_syncram_dp is
generic (
abits : integer := 4; dbits : integer := 32
);
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic);
end;
architecture behav of altera_syncram_dp is
component altsyncram
generic (
width_a : natural;
width_b : natural := 1;
widthad_a : natural;
widthad_b : natural := 1);
port(
address_a : in std_logic_vector(widthad_a-1 downto 0);
address_b : in std_logic_vector(widthad_b-1 downto 0);
clock0 : in std_logic;
clock1 : in std_logic;
data_a : in std_logic_vector(width_a-1 downto 0);
data_b : in std_logic_vector(width_b-1 downto 0);
q_a : out std_logic_vector(width_a-1 downto 0);
q_b : out std_logic_vector(width_b-1 downto 0);
rden_b : in std_logic;
wren_a : in std_logic;
wren_b : in std_logic
);
end component;
begin
u0 : altsyncram
generic map (
WIDTH_A => dbits, WIDTHAD_A => abits,
WIDTH_B => dbits, WIDTHAD_B => abits)
port map (
address_a => address1, address_b => address2, clock0 => clk1,
clock1 => clk2, data_a => datain1, data_b => datain2,
q_a => dataout1, q_b => dataout2, rden_b => enable2,
wren_a => write1, wren_b => write2);
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
entity altera_syncram is
generic ( abits : integer := 9; dbits : integer := 32);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (dbits -1 downto 0);
dataout : out std_logic_vector (dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end;
architecture behav of altera_syncram is
component altera_syncram_dp
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end component;
signal agnd : std_logic_vector(abits-1 downto 0);
signal dgnd : std_logic_vector(dbits-1 downto 0);
begin
agnd <= (others => '0'); dgnd <= (others => '0');
u0: altera_syncram_dp
generic map (abits, dbits)
port map (
clk1 => clk, address1 => address, datain1 => datain,
dataout1 => dataout, enable1 => enable, write1 => write,
clk2 => clk, address2 => agnd, datain2 => dgnd,
dataout2 => open, enable2 => agnd(0), write2 => agnd(0));
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library altera_mf;
use altera_mf.altsyncram;
-- pragma translate_on
entity altera_syncram128bw is
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (127 downto 0);
dataout : out std_logic_vector (127 downto 0);
enable : in std_logic_vector (15 downto 0);
write : in std_logic_vector (15 downto 0)
);
end;
architecture behav of altera_syncram128bw is
component altsyncram
generic (
width_a : natural;
width_b : natural := 1;
widthad_a : natural;
widthad_b : natural := 1;
byte_size : integer := 0;
width_byteena_a : integer := 1
);
port(
address_a : in std_logic_vector(widthad_a-1 downto 0);
clock0 : in std_logic;
clock1 : in std_logic;
data_a : in std_logic_vector(width_a-1 downto 0);
q_a : out std_logic_vector(width_a-1 downto 0);
wren_a : in std_logic;
byteena_a : in std_logic_vector( (width_byteena_a - 1) downto 0) := (others => '1')
);
end component;
signal agnd : std_logic_vector(abits-1 downto 0);
signal dgnd : std_logic_vector(127 downto 0);
signal write1 : std_logic;
signal enablex : std_logic_vector (15 downto 0);
begin
agnd <= (others => '0'); dgnd <= (others => '0');
write1 <= orv(write and enable);
enablex <= write when write1 = '1' else enable;
u0 : altsyncram
generic map (
WIDTH_A => 128, WIDTHAD_A => abits,
WIDTH_B => 128, WIDTHAD_B => abits, byte_size => 8,
width_byteena_a => 16 )
port map (
address_a => address, clock0 => clk, clock1 => clk,
data_a => datain, q_a => dataout, wren_a => write1,
byteena_a => enablex );
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library altera_mf;
use altera_mf.altsyncram;
-- pragma translate_on
entity altera_syncram256bw is
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (255 downto 0);
dataout : out std_logic_vector (255 downto 0);
enable : in std_logic_vector (31 downto 0);
write : in std_logic_vector (31 downto 0)
);
end;
architecture behav of altera_syncram256bw is
component altsyncram
generic (
width_a : natural;
width_b : natural := 1;
widthad_a : natural;
widthad_b : natural := 1;
byte_size : integer := 0;
width_byteena_a : integer := 1
);
port(
address_a : in std_logic_vector(widthad_a-1 downto 0);
clock0 : in std_logic;
clock1 : in std_logic;
data_a : in std_logic_vector(width_a-1 downto 0);
q_a : out std_logic_vector(width_a-1 downto 0);
wren_a : in std_logic;
byteena_a : in std_logic_vector( (width_byteena_a - 1) downto 0) := (others => '1')
);
end component;
signal agnd : std_logic_vector(abits-1 downto 0);
signal dgnd : std_logic_vector(255 downto 0);
signal write1 : std_logic;
signal enablex : std_logic_vector (31 downto 0);
begin
agnd <= (others => '0'); dgnd <= (others => '0');
write1 <= orv(write and enable);
enablex <= write when write1 = '1' else enable;
u0 : altsyncram
generic map (
WIDTH_A => 256, WIDTHAD_A => abits,
WIDTH_B => 256, WIDTHAD_B => abits, byte_size => 8,
width_byteena_a => 32 )
port map (
address_a => address, clock0 => clk, clock1 => clk,
data_a => datain, q_a => dataout, wren_a => write1,
byteena_a => enablex );
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library altera_mf;
use altera_mf.dcfifo;
-- pragma translate_on
entity altera_fifo_dp is
generic (
tech : integer := 0;
abits : integer := 4;
dbits : integer := 32
);
port (
rdclk : in std_logic;
rdreq : in std_logic;
rdfull : out std_logic;
rdempty : out std_logic;
rdusedw : out std_logic_vector(abits-1 downto 0);
q : out std_logic_vector(dbits-1 downto 0);
wrclk : in std_logic;
wrreq : in std_logic;
wrfull : out std_logic;
wrempty : out std_logic;
wrusedw : out std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
aclr : in std_logic := '0');
end;
architecture behav of altera_fifo_dp is
component dcfifo
generic (
lpm_width : natural;
lpm_widthu : natural;
lpm_numwords : natural;
lpm_showahead : string := "OFF";
lpm_hint : string := "USE_EAB=ON";
overflow_checking : string := "ON";
underflow_checking : string := "ON";
delay_rdusedw : natural := 1;
delay_wrusedw : natural := 1;
rdsync_delaypipe : natural := 0;
wrsync_delaypipe : natural := 0;
use_eab : string := "ON";
add_ram_output_register : string := "OFF";
add_width : natural := 1;
clocks_are_synchronized : string := "FALSE";
ram_block_type : string := "AUTO";
add_usedw_msb_bit : string := "OFF";
write_aclr_synch : string := "OFF";
lpm_type : string := "dcfifo";
intended_device_family : string := "NON_STRATIX" );
port (
data : in std_logic_vector(lpm_width-1 downto 0);
rdclk : in std_logic;
wrclk : in std_logic;
wrreq : in std_logic;
rdreq : in std_logic;
aclr : in std_logic := '0';
rdfull : out std_logic;
wrfull : out std_logic;
wrempty : out std_logic;
rdempty : out std_logic;
q : out std_logic_vector(lpm_width-1 downto 0);
rdusedw : out std_logic_vector(lpm_widthu-1 downto 0);
wrusedw : out std_logic_vector(lpm_widthu-1 downto 0) );
end component;
begin
u0 : dcfifo
generic map (
intended_device_family => "STRATIX IV",
lpm_numwords => 2**abits,
lpm_showahead => "OFF",
lpm_type => "dcfifo",
lpm_width => dbits,
lpm_widthu => abits,
overflow_checking => "ON",
rdsync_delaypipe => 4,
underflow_checking => "ON",
use_eab => "ON",
wrsync_delaypipe => 4
)
port map (
rdclk => rdclk,
rdreq => rdreq,
rdfull => rdfull,
rdempty => rdempty,
rdusedw => rdusedw,
q => q,
wrclk => wrclk,
wrreq => wrreq,
wrfull => wrfull,
wrempty => wrempty,
wrusedw => wrusedw,
data => data,
aclr => aclr
);
end;
| gpl-3.0 | 628963551ec5cb6732c30a8ad0406edf | 0.586088 | 3.439739 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/leon3v3/tbufmem_2p.vhd | 1 | 4,849 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: tbufmem_2p
-- File: tbufmem_2p.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Andrea Gianarro - Aeroflex Gaisler AB
-- Description: 256-bit trace buffer memory (CPU/AHB), two ports
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.leon3.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.stdlib.all;
entity tbufmem_2p is
generic (
tech : integer := 0;
tbuf : integer := 0; -- trace buf size in kB (0 - no trace buffer)
dwidth : integer := 32; -- AHB data width
testen : integer := 0
);
port (
clk : in std_ulogic;
di : in tracebuf_2p_in_type;
do : out tracebuf_2p_out_type;
testin: in std_logic_vector(TESTIN_WIDTH-1 downto 0)
);
end;
architecture rtl of tbufmem_2p is
constant ADDRBITS : integer := 10 + log2(tbuf) - 4;
begin
mem32 : for i in 0 to 3 generate -- basic 128 buffer
ram0 : syncram_2p
generic map (
tech => tech,
abits => addrbits,
dbits => 32,
wrfst => 1,
testen => testen,
custombits => memtest_vlen
)
port map (
rclk => clk,
renable => di.renable,
raddress => di.raddr(addrbits-1 downto 0),
dataout => do.data(((i*32)+31) downto (i*32)),
wclk => clk,
write => di.write(i),
waddress => di.waddr(addrbits-1 downto 0),
datain => di.data(((i*32)+31) downto (i*32)),
testin => testin
);
end generate;
mem64 : if dwidth > 32 generate -- extra data buffer for 64-bit bus
ram0 : syncram_2p
generic map (
tech => tech,
abits => addrbits,
dbits => 32,
wrfst => 1,
testen => testen,
custombits => memtest_vlen
)
port map (
rclk => clk,
renable => di.renable,
raddress => di.raddr(addrbits-1 downto 0),
dataout => do.data((128+31) downto 128),
wclk => clk,
write => di.write(7),
waddress => di.waddr(addrbits-1 downto 0),
datain => di.data((128+31) downto 128),
testin => testin
);
end generate;
mem128 : if dwidth > 64 generate -- extra data buffer for 128-bit bus
memwd: for i in 0 to 1 generate
ram0 : syncram_2p
generic map (
tech => tech,
abits => addrbits,
dbits => 32,
wrfst => 1,
testen => testen,
custombits => memtest_vlen
)
port map (
rclk => clk,
renable => di.renable,
raddress => di.raddr(addrbits-1 downto 0),
dataout => do.data((128+63+i*32) downto (128+32+i*32)),
wclk => clk,
write => di.write(5+i),
waddress => di.waddr(addrbits-1 downto 0),
datain => di.data((128+63+i*32) downto (128+32+i*32)),
testin => testin
);
end generate;
end generate;
nomem64 : if dwidth < 64 generate -- no extra data buffer for 64-bit bus
do.data((128+31) downto 128) <= (others => '0');
end generate;
nomem128 : if dwidth < 128 generate -- no extra data buffer for 128-bit bus
do.data((128+95) downto (128+32)) <= (others => '0');
end generate;
do.data(255 downto 224) <= (others => '0');
end;
| gpl-3.0 | 41deafc0b190055fcd24192e471e4a1c | 0.509383 | 4.140905 | false | true | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-altera-de2-ep2c35/clkgen_de2.vhd | 1 | 3,590 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library altera_mf;
-- pragma translate_off
use altera_mf.altpll;
-- pragma translate_on
entity clkgen_de2 is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic
);
end;
architecture rtl of clkgen_de2 is
component altpll
generic (
intended_device_family : string := "Stratix" ;
operation_mode : string := "NORMAL" ;
compensate_clock : string := "CLK0" ;
inclk0_input_frequency : positive;
width_clock : positive := 6;
clk0_multiply_by : positive := 1;
clk0_divide_by : positive := 1;
clk1_multiply_by : positive := 1;
clk1_divide_by : positive := 1;
clk2_multiply_by : positive := 1;
clk2_divide_by : positive := 1
);
port (
inclk : in std_logic_vector(1 downto 0);
clk : out std_logic_vector(width_clock-1 downto 0);
locked : out std_logic
);
end component;
signal clkout : std_logic_vector (5 downto 0);
signal inclk : std_logic_vector (1 downto 0);
constant clk_period : integer := 1000000000/clk_freq;
constant CLK_MUL2X : integer := clk_mul * 2;
begin
inclk <= '0' & inclk0;
c0 <= clkout(0); c0_2x <= clkout(1);
sden : if sdramen = 1 generate
altpll0 : altpll
generic map (
intended_device_family => "Cyclone II",
operation_mode => "ZERO_DELAY_BUFFER",
compensate_clock => "CLK2",
inclk0_input_frequency => clk_period,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => 5, clk1_divide_by => 10,
clk2_multiply_by => clk_mul, clk2_divide_by => clk_div)
port map (inclk => inclk, clk => clkout, locked => locked);
e0 <= clkout(2);
end generate;
nosd : if sdramen = 0 generate
altpll0 : altpll
generic map (
intended_device_family => "Cyclone II",
operation_mode => "NORMAL",
inclk0_input_frequency => clk_period,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => 5, clk1_divide_by => 10)
port map (inclk => inclk, clk => clkout, locked => locked);
e0 <= '0';
end generate;
end;
| gpl-3.0 | d8e4ee75692a8f05a4941f94bf29eb9a | 0.595543 | 3.674514 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-gr-pci-xc5v/config.vhd | 1 | 12,920 |
-----------------------------------------------------------------------------
-- LEON4 Demonstration design test bench configuration
-- Copyright (C) 2010 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex5;
constant CFG_MEMTECH : integer := virtex5;
constant CFG_PADTECH : integer := virtex5;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex5;
constant CFG_CLKMUL : integer := (7);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON processor core
constant CFG_LEON : integer := 3;
constant CFG_NCPU : integer := (2);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 4;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 4;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_BWMASK : integer := 16#0#;
constant CFG_CACHEBW : integer := 128;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 16;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_AHBWP : integer := 2;
constant CFG_LEONFT_EN : integer := 0 + 0*8;
constant CFG_LEON_NETLIST : integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- L2 Cache
constant CFG_L2_EN : integer := 0;
constant CFG_L2_SIZE : integer := 16;
constant CFG_L2_WAYS : integer := 2;
constant CFG_L2_HPROT : integer := 0;
constant CFG_L2_PEN : integer := 1;
constant CFG_L2_WT : integer := 0;
constant CFG_L2_RAN : integer := 0;
constant CFG_L2_SHARE : integer := 1;
constant CFG_L2_LSZ : integer := 32;
constant CFG_L2_MAP : integer := 16#00F0#;
constant CFG_L2_MTRR : integer := (0);
constant CFG_L2_EDAC : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- USB DSU
constant CFG_GRUSB_DCL : integer := 0;
constant CFG_GRUSB_DCL_UIFACE : integer := 1;
constant CFG_GRUSB_DCL_DW : integer := 8;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#0200ee#;
constant CFG_ETH_ENL : integer := 16#000007#;
-- PROM/SRAM controller
constant CFG_SRCTRL : integer := 1;
constant CFG_SRCTRL_PROMWS : integer := (5);
constant CFG_SRCTRL_RAMWS : integer := (0);
constant CFG_SRCTRL_IOWS : integer := (0);
constant CFG_SRCTRL_RMW : integer := 0;
constant CFG_SRCTRL_8BIT : integer := 0;
constant CFG_SRCTRL_SRBANKS : integer := 1;
constant CFG_SRCTRL_BANKSZ : integer := 0;
constant CFG_SRCTRL_ROMASEL : integer := (24);
-- SDRAM controller
constant CFG_SDCTRL : integer := 1;
constant CFG_SDCTRL_INVCLK : integer := 0;
constant CFG_SDCTRL_SD64 : integer := 1;
constant CFG_SDCTRL_PAGE : integer := 0 + 0;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 0;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- FTMCTRL memory controller
constant CFG_MCTRLFT : integer := 0;
constant CFG_MCTRLFT_RAM8BIT : integer := 0;
constant CFG_MCTRLFT_RAM16BIT : integer := 0;
constant CFG_MCTRLFT_5CS : integer := 0;
constant CFG_MCTRLFT_SDEN : integer := 0;
constant CFG_MCTRLFT_SEPBUS : integer := 0;
constant CFG_MCTRLFT_INVCLK : integer := 0;
constant CFG_MCTRLFT_SD64 : integer := 0;
constant CFG_MCTRLFT_EDAC : integer := 0 + 0 + 0;
constant CFG_MCTRLFT_PAGE : integer := 0 + 0;
constant CFG_MCTRLFT_ROMASEL : integer := 0;
constant CFG_MCTRLFT_WFB : integer := 0;
constant CFG_MCTRLFT_NET : integer := 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 4;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 16;
-- CAN 2.0 interface
constant CFG_CAN : integer := 0;
constant CFG_CAN_NUM : integer := (1);
constant CFG_CANIO : integer := 16#C00#;
constant CFG_CANIRQ : integer := (13);
constant CFG_CANSEPIRQ: integer := 0;
constant CFG_CAN_SYNCRST : integer := 0;
constant CFG_CANFT : integer := 0;
-- Spacewire interface
constant CFG_SPW_EN : integer := 0;
constant CFG_SPW_NUM : integer := (1);
constant CFG_SPW_AHBFIFO : integer := 16;
constant CFG_SPW_RXFIFO : integer := 16;
constant CFG_SPW_RMAP : integer := 0;
constant CFG_SPW_RMAPBUF : integer := 4;
constant CFG_SPW_RMAPCRC : integer := 0;
constant CFG_SPW_NETLIST : integer := 0;
constant CFG_SPW_FT : integer := 0;
constant CFG_SPW_GRSPW : integer := 2;
constant CFG_SPW_RXUNAL : integer := 0;
constant CFG_SPW_DMACHAN : integer := (1);
constant CFG_SPW_PORTS : integer := (1);
constant CFG_SPW_INPUT : integer := 3;
constant CFG_SPW_OUTPUT : integer := 0;
constant CFG_SPW_RTSAME : integer := 0;
-- GRPCI2 interface
constant CFG_GRPCI2_MASTER : integer := 1;
constant CFG_GRPCI2_TARGET : integer := 1;
constant CFG_GRPCI2_DMA : integer := 0;
constant CFG_GRPCI2_VID : integer := 16#1AC8#;
constant CFG_GRPCI2_DID : integer := 16#0054#;
constant CFG_GRPCI2_CLASS : integer := 16#000000#;
constant CFG_GRPCI2_RID : integer := 16#00#;
constant CFG_GRPCI2_CAP : integer := 16#40#;
constant CFG_GRPCI2_NCAP : integer := 16#00#;
constant CFG_GRPCI2_BAR0 : integer := (26);
constant CFG_GRPCI2_BAR1 : integer := (0);
constant CFG_GRPCI2_BAR2 : integer := (0);
constant CFG_GRPCI2_BAR3 : integer := (0);
constant CFG_GRPCI2_BAR4 : integer := (0);
constant CFG_GRPCI2_BAR5 : integer := (0);
constant CFG_GRPCI2_FDEPTH : integer := 3;
constant CFG_GRPCI2_FCOUNT : integer := 2;
constant CFG_GRPCI2_ENDIAN : integer := 0;
constant CFG_GRPCI2_DEVINT : integer := 0;
constant CFG_GRPCI2_DEVINTMSK : integer := 16#0#;
constant CFG_GRPCI2_HOSTINT : integer := 0;
constant CFG_GRPCI2_HOSTINTMSK: integer := 16#0#;
constant CFG_GRPCI2_TRACE : integer := 0;
constant CFG_GRPCI2_TRACEAPB : integer := 0;
constant CFG_GRPCI2_BYPASS : integer := 0;
constant CFG_GRPCI2_EXTCFG : integer := (0);
-- PCI arbiter
constant CFG_PCI_ARB : integer := 0;
constant CFG_PCI_ARBAPB : integer := 0;
constant CFG_PCI_ARB_NGNT : integer := (4);
-- USB Host Controller
constant CFG_GRUSBHC : integer := 0;
constant CFG_GRUSBHC_NPORTS : integer := (1);
constant CFG_GRUSBHC_EHC : integer := 0;
constant CFG_GRUSBHC_UHC : integer := 0;
constant CFG_GRUSBHC_NCC : integer := 1;
constant CFG_GRUSBHC_NPCC : integer := (1);
constant CFG_GRUSBHC_PRR : integer := 0;
constant CFG_GRUSBHC_PR1 : integer := 0*2**26 + 0*2**22 + 0*2**18 + 0*2**14 + 0*2**10 + 0*2**6 + 0*2**2 + (1/4);
constant CFG_GRUSBHC_PR2 : integer := 0*2**26 + 0*2**22 + 0*2**18 + 0*2**14 + 0*2**10 + 0*2**6 + 0*2**2 + (1 mod 4);
constant CFG_GRUSBHC_ENDIAN : integer := 1;
constant CFG_GRUSBHC_BEREGS : integer := 0;
constant CFG_GRUSBHC_BEDESC : integer := 0;
constant CFG_GRUSBHC_BLO : integer := 3;
constant CFG_GRUSBHC_BWRD : integer := (16);
constant CFG_GRUSBHC_UTM : integer := 2;
constant CFG_GRUSBHC_VBUSCONF : integer := 3;
-- GR USB 2.0 Device Controller
constant CFG_GRUSBDC : integer := 0;
constant CFG_GRUSBDC_AIFACE : integer := 0;
constant CFG_GRUSBDC_UIFACE : integer := 1;
constant CFG_GRUSBDC_DW : integer := 8;
constant CFG_GRUSBDC_NEPI : integer := (1);
constant CFG_GRUSBDC_NEPO : integer := (1);
constant CFG_GRUSBDC_I0 : integer := (1024);
constant CFG_GRUSBDC_I1 : integer := (1024);
constant CFG_GRUSBDC_I2 : integer := (1024);
constant CFG_GRUSBDC_I3 : integer := (1024);
constant CFG_GRUSBDC_I4 : integer := (1024);
constant CFG_GRUSBDC_I5 : integer := (1024);
constant CFG_GRUSBDC_I6 : integer := (1024);
constant CFG_GRUSBDC_I7 : integer := (1024);
constant CFG_GRUSBDC_I8 : integer := (1024);
constant CFG_GRUSBDC_I9 : integer := (1024);
constant CFG_GRUSBDC_I10 : integer := (1024);
constant CFG_GRUSBDC_I11 : integer := (1024);
constant CFG_GRUSBDC_I12 : integer := (1024);
constant CFG_GRUSBDC_I13 : integer := (1024);
constant CFG_GRUSBDC_I14 : integer := (1024);
constant CFG_GRUSBDC_I15 : integer := (1024);
constant CFG_GRUSBDC_O0 : integer := (1024);
constant CFG_GRUSBDC_O1 : integer := (1024);
constant CFG_GRUSBDC_O2 : integer := (1024);
constant CFG_GRUSBDC_O3 : integer := (1024);
constant CFG_GRUSBDC_O4 : integer := (1024);
constant CFG_GRUSBDC_O5 : integer := (1024);
constant CFG_GRUSBDC_O6 : integer := (1024);
constant CFG_GRUSBDC_O7 : integer := (1024);
constant CFG_GRUSBDC_O8 : integer := (1024);
constant CFG_GRUSBDC_O9 : integer := (1024);
constant CFG_GRUSBDC_O10 : integer := (1024);
constant CFG_GRUSBDC_O11 : integer := (1024);
constant CFG_GRUSBDC_O12 : integer := (1024);
constant CFG_GRUSBDC_O13 : integer := (1024);
constant CFG_GRUSBDC_O14 : integer := (1024);
constant CFG_GRUSBDC_O15 : integer := (1024);
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- UART 2
constant CFG_UART2_ENABLE : integer := 1;
constant CFG_UART2_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (16);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#fe#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- MIL-STD-1553 controllers
constant CFG_GR1553B_ENABLE : integer := 0;
constant CFG_GR1553B_RTEN : integer := 0;
constant CFG_GR1553B_BCEN : integer := 0;
constant CFG_GR1553B_BMEN : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-3.0 | 7cebd58442d86d919dab20c42daf2960 | 0.652477 | 3.426147 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/srmmu/mmutlb.vhd | 1 | 21,812 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mmutlb
-- File: mmutlb.vhd
-- Author: Konrad Eisele, Jiri Gaisler, Gaisler Research
-- Description: MMU TLB logic
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
use gaisler.libmmu.all;
entity mmutlb is
generic (
tech : integer range 0 to NTECH := 0;
entries : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 1;
mmupgsz : integer range 0 to 5 := 0;
scantest : integer := 0;
ramcbits: integer := 1
);
port (
rst : in std_logic;
clk : in std_logic;
tlbi : in mmutlb_in_type;
tlbo : out mmutlb_out_type;
two : in mmutw_out_type;
twi : out mmutw_in_type;
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0)
);
end mmutlb;
architecture rtl of mmutlb is
constant M_TLB_FASTWRITE : integer range 0 to 3 :=
conv_integer(conv_std_logic_vector(tlb_type,2) and conv_std_logic_vector(2,2)); -- fast writebuffer
constant entries_log : integer := log2(entries);
constant entries_max : std_logic_vector(entries_log-1 downto 0) :=
conv_std_logic_vector(entries-1, entries_log);
type states is (idle, match, walk, pack, flush, sync, diag, dofault);
type tlb_rtype is record
s2_tlbstate : states;
s2_entry : std_logic_vector(entries_log-1 downto 0);
s2_hm : std_logic;
s2_needsync : std_logic;
s2_data : std_logic_vector(31 downto 0);
s2_isid : mmu_idcache;
s2_su : std_logic;
s2_read : std_logic;
s2_flush : std_logic;
s2_ctx : std_logic_vector(M_CTX_SZ-1 downto 0);
walk_use : std_logic;
walk_transdata : mmuidc_data_out_type;
walk_fault : mmutlbfault_out_type;
nrep : std_logic_vector(entries_log-1 downto 0);
tpos : std_logic_vector(entries_log-1 downto 0);
touch : std_logic;
sync_isw : std_logic;
tlbmiss : std_logic;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant ASYNC_RESET : boolean := GRLIB_CONFIG_ARRAY(grlib_async_reset_enable) = 1;
constant RRES : tlb_rtype := (
s2_tlbstate => idle,
s2_entry => (others => '0'),
s2_hm => '0',
s2_needsync => '0',
s2_data => (others => '0'),
s2_isid => id_icache,
s2_su => '0',
s2_read => '0',
s2_flush => '0',
s2_ctx => (others => '0'),
walk_use => '0',
walk_transdata => mmuidco_zero,
walk_fault => mmutlbfault_out_zero,
nrep => (others => '0'),
tpos => (others => '0'),
touch => '0',
sync_isw => '0',
tlbmiss => '0');
signal c,r : tlb_rtype;
-- tlb cams
component mmutlbcam
generic (
tlb_type : integer range 0 to 3 := 1;
mmupgsz : integer range 0 to 5 := 0
);
port (
rst : in std_logic;
clk : in std_logic;
tlbcami : in mmutlbcam_in_type;
tlbcamo : out mmutlbcam_out_type
);
end component;
signal tlbcami : mmutlbcami_a (entries-1 downto 0);
signal tlbcamo : mmutlbcamo_a (entries-1 downto 0);
-- least recently used
component mmulru
generic (
entries : integer := 8
);
port (
clk : in std_logic;
rst : in std_logic;
lrui : in mmulru_in_type;
lruo : out mmulru_out_type
);
end component;
signal lrui : mmulru_in_type;
signal lruo : mmulru_out_type;
-- data-ram syncram signals
signal dr1_addr : std_logic_vector(entries_log-1 downto 0);
signal dr1_datain : std_logic_vector(29 downto 0);
signal dr1_dataout : std_logic_vector(29 downto 0);
signal dr1_enable : std_logic;
signal dr1_write : std_logic;
begin
p0: process (rst, r, tlbi, two, tlbcamo, dr1_dataout, lruo)
variable v : tlb_rtype;
variable finish, selstate : std_logic;
variable cam_hitaddr : std_logic_vector(entries_log-1 downto 0);
variable cam_hit_all : std_logic;
variable mtag,ftag : tlbcam_tfp;
-- tlb cam input
variable tlbcam_trans_op : std_logic;
variable tlbcam_write_op : std_logic_vector(entries-1 downto 0);
variable tlbcam_flush_op : std_logic;
-- tw inputs
variable twi_walk_op_ur : std_logic;
variable twi_data : std_logic_vector(31 downto 0);
variable twi_areq_ur : std_logic;
variable twi_aaddr : std_logic_vector(31 downto 0);
variable twi_adata : std_logic_vector(31 downto 0);
variable two_error : std_logic;
-- lru inputs
variable lrui_touch : std_logic;
variable lrui_touchmin : std_logic;
variable lrui_pos : std_logic_vector(entries_log-1 downto 0);
-- syncram inputs
variable dr1write : std_logic;
-- hit tlbcam's output
variable ACC : std_logic_vector(2 downto 0);
variable PTE : std_logic_vector(31 downto 0);
variable LVL : std_logic_vector(1 downto 0);
variable CAC : std_logic;
variable NEEDSYNC : std_logic;
-- wb hit tlbcam's output
variable wb_i_entry : integer range 0 to entries-1;
variable wb_ACC : std_logic_vector(2 downto 0);
variable wb_PTE : std_logic_vector(31 downto 0);
variable wb_LVL : std_logic_vector(1 downto 0);
variable wb_CAC : std_logic;
variable wb_fault_pro, wb_fault_pri : std_logic;
variable wb_WBNEEDSYNC : std_logic;
variable twACC : std_logic_vector(2 downto 0);
variable tWLVL : std_logic_vector(1 downto 0);
variable twPTE : std_logic_vector(31 downto 0);
variable twNEEDSYNC : std_logic;
variable tlbcam_tagin : tlbcam_tfp;
variable tlbcam_tagwrite : tlbcam_reg;
variable store : std_logic;
variable reppos : std_logic_vector(entries_log-1 downto 0);
variable i_entry : integer range 0 to entries-1;
variable i_reppos : integer range 0 to entries-1;
variable fault_pro, fault_pri : std_logic;
variable fault_mexc, fault_trans, fault_inv, fault_access : std_logic;
variable transdata : mmuidc_data_out_type;
variable fault : mmutlbfault_out_type;
variable savewalk : std_logic;
variable tlbo_s1finished : std_logic;
variable wb_transdata : mmuidc_data_out_type;
variable cam_addr : std_logic_vector(31 downto 0);
begin
v := r; v.tlbmiss := '0';
cam_addr := tlbi.transdata.data;
wb_i_entry := 0;
wb_ACC := (others => '0');
wb_PTE := (others => '0');
wb_LVL := (others => '0');
wb_CAC := '0';
wb_fault_pro := '0';
wb_fault_pri := '0';
wb_WBNEEDSYNC := '0';
if (M_TLB_FASTWRITE /= 0) and (tlbi.trans_op = '0') then
cam_addr := tlbi.transdata.wb_data;
end if;
wb_transdata.finish := '0';
wb_transdata.data := (others => '0');
wb_transdata.cache := '0';
wb_transdata.accexc := '0';
finish := '0';
selstate := '0';
cam_hitaddr := (others => '0');
cam_hit_all := '0';
mtag.TYP := (others => '0');
mtag.I1 := (others => '0');
mtag.I2 := (others => '0');
mtag.I3 := (others => '0');
mtag.CTX := (others => '0');
mtag.M := '0';
ftag.TYP := (others => '0');
ftag.I1 := (others => '0');
ftag.I2 := (others => '0');
ftag.I3 := (others => '0');
ftag.CTX := (others => '0');
ftag.M := '0';
tlbcam_trans_op := '0';
tlbcam_write_op := (others => '0');
tlbcam_flush_op := '0';
twi_walk_op_ur := '0';
twi_data := (others => '0');
twi_areq_ur := '0';
twi_aaddr := (others => '0');
twi_adata := (others => '0');
two_error := '0';
lrui_touch:= '0';
lrui_touchmin:= '0';
lrui_pos := (others => '0');
dr1write := '0';
ACC := (others => '0');
PTE := (others => '0');
LVL := (others => '0');
CAC := '0';
NEEDSYNC := '0';
twACC := (others => '0');
tWLVL := (others => '0');
twPTE := (others => '0');
twNEEDSYNC := '0';
tlbcam_tagin.TYP := (others => '0');
tlbcam_tagin.I1 := (others => '0');
tlbcam_tagin.I2 := (others => '0');
tlbcam_tagin.I3 := (others => '0');
tlbcam_tagin.CTX := (others => '0');
tlbcam_tagin.M := '0';
tlbcam_tagwrite.ET := (others => '0');
tlbcam_tagwrite.ACC := (others => '0');
tlbcam_tagwrite.M := '0';
tlbcam_tagwrite.R := '0';
tlbcam_tagwrite.SU := '0';
tlbcam_tagwrite.VALID := '0';
tlbcam_tagwrite.LVL := (others => '0');
tlbcam_tagwrite.I1 := (others => '0');
tlbcam_tagwrite.I2 := (others => '0');
tlbcam_tagwrite.I3 := (others => '0');
tlbcam_tagwrite.CTX := (others => '0');
tlbcam_tagwrite.PPN := (others => '0');
tlbcam_tagwrite.C := '0';
store := '0';
reppos := (others => '0');
fault_pro := '0';
fault_pri := '0';
fault_mexc := '0';
fault_trans := '0';
fault_inv := '0';
fault_access := '0';
transdata.finish := '0';
transdata.data := (others => '0');
transdata.cache := '0';
transdata.accexc := '0';
fault.fault_pro := '0';
fault.fault_pri := '0';
fault.fault_access := '0';
fault.fault_mexc := '0';
fault.fault_trans := '0';
fault.fault_inv := '0';
fault.fault_lvl := (others => '0');
fault.fault_su := '0';
fault.fault_read := '0';
fault.fault_isid := id_dcache;
fault.fault_addr := (others => '0');
savewalk := '0';
tlbo_s1finished := '0';
tlbcam_trans_op := '0'; tlbcam_write_op := (others => '0'); tlbcam_flush_op := '0';
lrui_touch := '0'; lrui_touchmin := '0'; lrui_pos := (others => '0');
dr1write := '0';
fault_pro := '0'; fault_pri := '0'; fault_mexc := '0'; fault_trans := '0'; fault_inv := '0'; fault_access := '0';
twi_walk_op_ur := '0'; twi_areq_ur := '0'; twi_aaddr := dr1_dataout&"00";
finish := '0';
store := '0'; savewalk := '0'; tlbo_s1finished := '0';
selstate := '0';
cam_hitaddr := (others => '0');
cam_hit_all := '0';
NEEDSYNC := '0';
for i in entries-1 downto 0 loop
NEEDSYNC := NEEDSYNC or tlbcamo(i).NEEDSYNC;
if (tlbcamo(i).hit) = '1' then
cam_hitaddr(entries_log-1 downto 0) := cam_hitaddr(entries_log-1 downto 0) or conv_std_logic_vector(i, entries_log);
cam_hit_all := '1';
end if;
end loop;
-- tlbcam write operation
tlbcam_tagwrite := TLB_CreateCamWrite( two.data, r.s2_read, two.lvl, r.s2_ctx, r.s2_data);
-- replacement position
reppos := (others => '0');
if tlb_rep = 0 then
reppos := lruo.pos(entries_log-1 downto 0);
v.touch := '0';
elsif tlb_rep = 1 then
reppos := r.nrep;
end if;
i_reppos := conv_integer(reppos);
-- tw
two_error := two.fault_mexc or two.fault_trans or two.fault_inv;
twACC := two.data(PTE_ACC_U downto PTE_ACC_D);
twLVL := two.lvl;
twPTE := two.data;
twNEEDSYNC := (not two.data(PTE_R)) or ((not r.s2_read) and (not two.data(PTE_M))); -- tw : writeback on next flush
case r.s2_tlbstate is
when idle =>
if (tlbi.s2valid) = '1' then
if r.s2_flush = '1' then
v.s2_tlbstate := pack;
else
v.walk_fault.fault_pri := '0';
v.walk_fault.fault_pro := '0';
v.walk_fault.fault_access := '0';
v.walk_fault.fault_trans := '0';
v.walk_fault.fault_inv := '0';
v.walk_fault.fault_mexc := '0';
if (r.s2_hm and not tlbi.mmctrl1.tlbdis ) = '1' then
if r.s2_needsync = '1' then
v.s2_tlbstate := sync;
else
finish := '1';
end if;
if tlb_rep = 0 then
v.tpos := r.s2_entry; v.touch := '1'; -- touch lru
end if;
else
v.s2_entry := reppos;
v.s2_tlbstate := walk; v.tlbmiss := '1';
if tlb_rep = 0 then
lrui_touchmin := '1'; -- lru element consumed
end if;
end if;
end if;
end if;
when walk =>
if (two.finish = '1') then
if ( two_error ) = '0' then
tlbcam_write_op := decode(r.s2_entry);
dr1write := '1';
TLB_CheckFault( twACC, r.s2_isid, r.s2_su, r.s2_read, v.walk_fault.fault_pro, v.walk_fault.fault_pri );
end if;
TLB_MergeData( mmupgsz, tlbi.mmctrl1, two.lvl , two.data, r.s2_data, v.walk_transdata.data );
v.walk_transdata.cache := two.data(PTE_C);
v.walk_fault.fault_lvl := two.fault_lvl;
v.walk_fault.fault_access := '0';
v.walk_fault.fault_mexc := two.fault_mexc;
v.walk_fault.fault_trans := two.fault_trans;
v.walk_fault.fault_inv := two.fault_inv;
v.walk_use := '1';
if ( twNEEDSYNC = '0' or two_error = '1') then
v.s2_tlbstate := pack;
else
v.s2_tlbstate := sync;
v.sync_isw := '1';
end if;
if tlb_rep = 1 then
if (r.nrep = entries_max) then v.nrep := (others => '0');
else v.nrep := r.nrep + 1;
end if;
end if;
else
twi_walk_op_ur := '1';
end if;
when pack =>
v.s2_flush := '0';
v.walk_use := '0';
finish := '1';
v.s2_tlbstate := idle;
when sync =>
tlbcam_trans_op := '1';
if ( v.sync_isw = '1') then
-- pte address is currently written to syncram, wait one cycle before issuing twi_areq_ur
v.sync_isw := '0';
else
if (two.finish = '1') then
v.s2_tlbstate := pack;
v.walk_fault.fault_mexc := two.fault_mexc;
if (two.fault_mexc) = '1' then
v.walk_use := '1';
end if;
else
twi_areq_ur := '1';
end if;
end if;
when others =>
v .s2_tlbstate := idle;
end case;
if selstate = '1' then
if tlbi.trans_op = '1' then
elsif tlbi.flush_op = '1' then
end if;
end if;
i_entry := conv_integer(r.s2_entry);
ACC := tlbcamo(i_entry).pteout(PTE_ACC_U downto PTE_ACC_D);
PTE := tlbcamo(i_entry).pteout;
LVL := tlbcamo(i_entry).LVL;
CAC := tlbcamo(i_entry).pteout(PTE_C);
transdata.cache := CAC;
TLB_CheckFault( ACC, r.s2_isid, r.s2_su, r.s2_read, fault_pro, fault_pri );
fault.fault_pro := '0';
fault.fault_pri := '0';
fault.fault_access := '0';
fault.fault_mexc := '0';
fault.fault_trans := '0';
fault.fault_inv := '0';
if finish = '1' and (r.s2_flush = '0') then --protect flush path
fault.fault_pro := fault_pro;
fault.fault_pri := fault_pri;
fault.fault_access := fault_access;
fault.fault_mexc := fault_mexc;
fault.fault_trans := fault_trans;
fault.fault_inv := fault_inv;
end if;
if (M_TLB_FASTWRITE /= 0) then
wb_i_entry := conv_integer(cam_hitaddr(entries_log-1 downto 0));
wb_ACC := tlbcamo(wb_i_entry).pteout(PTE_ACC_U downto PTE_ACC_D);
wb_PTE := tlbcamo(wb_i_entry).pteout;
wb_LVL := tlbcamo(wb_i_entry).LVL;
wb_CAC := tlbcamo(wb_i_entry).pteout(PTE_C);
wb_WBNEEDSYNC := tlbcamo(wb_i_entry).WBNEEDSYNC;
wb_transdata.cache := wb_CAC;
TLB_MergeData( mmupgsz, tlbi.mmctrl1, wb_LVL, wb_PTE, tlbi.transdata.data, wb_transdata.data );
TLB_CheckFault( wb_ACC, tlbi.transdata.isid, tlbi.transdata.su, tlbi.transdata.read, wb_fault_pro, wb_fault_pri );
wb_transdata.accexc := wb_fault_pro or wb_fault_pri or wb_WBNEEDSYNC or (not cam_hit_all);
end if;
--# merge data
TLB_MergeData( mmupgsz, tlbi.mmctrl1, LVL, PTE, r.s2_data, transdata.data );
--# reset
if (not ASYNC_RESET) and (not RESET_ALL) and (rst = '0') then
v.s2_flush := '0';
v.s2_tlbstate := idle;
if tlb_rep = 1 then
v.nrep := (others => '0');
end if;
if tlb_rep = 0 then
v.touch := '0';
end if;
v.sync_isw := '0';
end if;
if (finish = '1') or (tlbi.s2valid = '0') then
tlbo_s1finished := '1';
v.s2_hm := cam_hit_all;
v.s2_entry := cam_hitaddr(entries_log-1 downto 0);
v.s2_needsync := NEEDSYNC;
v.s2_data := tlbi.transdata.data;
v.s2_read := tlbi.transdata.read;
v.s2_su := tlbi.transdata.su;
v.s2_isid := tlbi.transdata.isid;
v.s2_flush := tlbi.flush_op;
v.s2_ctx := tlbi.mmctrl1.ctx;
end if;
-- translation operation tag
mtag := TLB_CreateCamTrans( cam_addr, tlbi.transdata.read, tlbi.mmctrl1.ctx );
tlbcam_tagin := mtag;
-- flush/(probe) operation tag
ftag := TLB_CreateCamFlush( r.s2_data, tlbi.mmctrl1.ctx );
if (r.s2_flush = '1') then
tlbcam_tagin := ftag;
end if;
if r.walk_use = '1' then
transdata := r.walk_transdata;
fault := r.walk_fault;
end if;
fault.fault_read := r.s2_read;
fault.fault_su := r.s2_su;
fault.fault_isid := r.s2_isid;
fault.fault_addr := r.s2_data;
transdata.finish := finish;
transdata.accexc := '0';
twi_adata := PTE;
--# drive signals
tlbo.wbtransdata <= wb_transdata;
tlbo.transdata <= transdata;
tlbo.fault <= fault;
tlbo.nexttrans <= store;
tlbo.s1finished <= tlbo_s1finished;
twi.walk_op_ur <= twi_walk_op_ur;
twi.data <= r.s2_data;
twi.areq_ur <= twi_areq_ur;
twi.adata <= twi_adata;
twi.aaddr <= twi_aaddr;
twi.tlbmiss <= r.tlbmiss;
if tlb_rep = 0 then
lrui.flush <= r.s2_flush;
lrui.touch <= r.touch;
lrui.touchmin <= lrui_touchmin;
lrui.pos <= (others => '0');
lrui.pos(entries_log-1 downto 0) <= r.tpos;
lrui.mmctrl1 <= tlbi.mmctrl1;
end if;
dr1_addr <= r.s2_entry;
dr1_datain <= two.addr(31 downto 2);
dr1_enable <= '1';
dr1_write <= dr1write;
for i in entries-1 downto 0 loop
tlbcami(i).mmctrl <= tlbi.mmctrl1;
tlbcami(i).tagin <= tlbcam_tagin;
tlbcami(i).trans_op <= tlbi.trans_op; --tlbcam_trans_op;
tlbcami(i).wb_op <= tlbi.wb_op; --tlbcam_trans_op;
tlbcami(i).flush_op <= r.s2_flush;
tlbcami(i).mmuen <= tlbi.mmctrl1.e;
tlbcami(i).tagwrite <= tlbcam_tagwrite;
tlbcami(i).write_op <= tlbcam_write_op(i);
tlbcami(i).mset <= '0';
end loop; -- i
c <= v;
end process p0;
syncrregs : if not ASYNC_RESET generate
p1: process (clk)
begin
if rising_edge(clk) then
r <= c;
if RESET_ALL and (rst = '0') then
r <= RRES;
end if;
end if;
end process p1;
end generate;
asyncrregs : if ASYNC_RESET generate
p1: process (clk, rst)
begin
if rst = '0' then
r <= RRES;
elsif rising_edge(clk) then
r <= c;
end if;
end process p1;
end generate;
-- tag-cam tlb entries
tlbcam0: for i in entries-1 downto 0 generate
tag0 : mmutlbcam
generic map ( tlb_type, mmupgsz )
port map (rst, clk, tlbcami(i), tlbcamo(i));
end generate tlbcam0;
-- data-ram syncram
dataram : syncram
generic map ( tech => tech, dbits => 30, abits => entries_log, testen => scantest, custombits => ramcbits)
port map ( clk, dr1_addr, dr1_datain, dr1_dataout, dr1_enable, dr1_write,
testin
);
-- lru
lru0: if tlb_rep = 0 generate
lru : mmulru
generic map ( entries => entries)
port map ( clk, rst, lrui, lruo );
end generate lru0;
end rtl;
| gpl-3.0 | d6998e268cab40e9d563f58d8d712f01 | 0.530121 | 3.336188 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/maps/ringosc.vhd | 1 | 2,533 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ringosc
-- File: ringosc.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Ring-oscillator with tech mapping
------------------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity ringosc is
generic (tech : integer := 0);
port (
roen : in Std_ULogic;
roout : out Std_ULogic);
end ;
architecture rtl of ringosc is
component ringosc_rhumc
port (
roen : in Std_ULogic;
roout : out Std_ULogic);
end component;
component ringosc_ut130hbd
port (
roen : in Std_ULogic;
roout : out Std_ULogic);
end component;
component ringosc_rhs65
port (
roen : in Std_ULogic;
roout : out Std_ULogic);
end component;
begin
dr : if tech = rhumc generate
drx : ringosc_rhumc port map (roen, roout);
end generate;
ut130r : if tech = ut130 generate
ut130rx : ringosc_ut130hbd port map (roen, roout);
end generate;
rhs65r : if tech = rhs65 generate
rhs65rx : ringosc_rhs65 port map (roen, roout);
end generate;
-- pragma translate_off
gen : if tech /= rhumc and tech /= ut130 and tech /= rhs65 generate
signal tmp : std_ulogic := '0';
begin
tmp <= not tmp after 1 ns when roen = '1' else '0';
roout <= tmp;
end generate;
-- pragma translate_on
end architecture rtl;
| gpl-3.0 | 25b4271eb5f6e6c40b54aaa6a29a8422 | 0.605606 | 4.065811 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/altera_mf/tap_altera_mf.vhd | 1 | 4,982 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: tap_altera
-- File: tap_altera_gen.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: Altera TAP controllers wrappers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library altera_mf;
use altera_mf.altera_mf_components.all;
use altera_mf.sld_virtual_jtag;
-- pragma translate_on
entity altera_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_inst : out std_logic_vector(7 downto 0);
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of altera_tap is
signal ir0 : std_logic_vector(7 downto 0);
component sld_virtual_jtag
generic (
--lpm_hint : string := "UNUSED";
--lpm_type : string := "sld_virtual_jtag";
sld_auto_instance_index : string := "NO";
sld_instance_index : natural := 0;
sld_ir_width : natural := 1
--sld_sim_action : string := "UNUSED"
--sld_sim_n_scan : natural := 0;
--sld_sim_total_length : natural := 0
);
port(
ir_in : out std_logic_vector(sld_ir_width-1 downto 0);
ir_out : in std_logic_vector(sld_ir_width-1 downto 0);
jtag_state_cdr : out std_logic;
jtag_state_cir : out std_logic;
jtag_state_e1dr : out std_logic;
jtag_state_e1ir : out std_logic;
jtag_state_e2dr : out std_logic;
jtag_state_e2ir : out std_logic;
jtag_state_pdr : out std_logic;
jtag_state_pir : out std_logic;
jtag_state_rti : out std_logic;
jtag_state_sdr : out std_logic;
jtag_state_sdrs : out std_logic;
jtag_state_sir : out std_logic;
jtag_state_sirs : out std_logic;
jtag_state_tlr : out std_logic;
jtag_state_udr : out std_logic;
jtag_state_uir : out std_logic;
tck : out std_logic;
tdi : out std_logic;
tdo : in std_logic;
tms : out std_logic;
virtual_state_cdr : out std_logic;
virtual_state_cir : out std_logic;
virtual_state_e1dr : out std_logic;
virtual_state_e2dr : out std_logic;
virtual_state_pdr : out std_logic;
virtual_state_sdr : out std_logic;
virtual_state_udr : out std_logic;
virtual_state_uir : out std_logic
);
end component;
begin
tapo_rst <= '0';
tapo_xsel1 <= '0'; tapo_xsel2 <= '0';
u0 : sld_virtual_jtag
generic map (sld_ir_width => 8,
sld_auto_instance_index => "NO",
sld_instance_index => 0)
port map (ir_in => tapo_inst,
ir_out => ir0,
jtag_state_cdr => open,
jtag_state_cir => open,
jtag_state_e1dr => open,
jtag_state_e1ir => open,
jtag_state_e2dr => open,
jtag_state_e2ir => open,
jtag_state_pdr => open,
jtag_state_pir => open,
jtag_state_rti => open,
jtag_state_sdr => open,
jtag_state_sdrs => open,
jtag_state_sir => open,
jtag_state_sirs => open,
jtag_state_tlr => open,
jtag_state_udr => open,
jtag_state_uir => open,
tck => tapo_tck,
tdi => tapo_tdi,
tdo => tapi_tdo1,
tms => open,
virtual_state_cdr => tapo_capt,
virtual_state_cir => open,
virtual_state_e1dr => open,
virtual_state_e2dr => open,
virtual_state_pdr => open,
virtual_state_sdr => tapo_shft,
virtual_state_udr => tapo_upd,
virtual_state_uir => open);
end;
| gpl-3.0 | 138c9a4ccb1a48f358548ff6ed011927 | 0.55841 | 3.319121 | false | false | false | false |
hoglet67/CoPro6502 | src/T80/DebugSystemXR.vhd | 1 | 4,171 | -- Z80, Monitor ROM, external SRAM interface and two 16450 UARTs
-- that can be synthesized and used with
-- the NoICE debugger that can be found at
-- http://www.noicedebugger.com/
library IEEE;
use IEEE.std_logic_1164.all;
entity DebugSystemXR is
port(
Reset_n : in std_logic;
Clk : in std_logic;
NMI_n : in std_logic;
OE_n : out std_logic;
WE_n : out std_logic;
RAMCS_n : out std_logic;
ROMCS_n : out std_logic;
PGM_n : out std_logic;
A : out std_logic_vector(16 downto 0);
D : inout std_logic_vector(7 downto 0);
RXD0 : in std_logic;
CTS0 : in std_logic;
DSR0 : in std_logic;
RI0 : in std_logic;
DCD0 : in std_logic;
RXD1 : in std_logic;
CTS1 : in std_logic;
DSR1 : in std_logic;
RI1 : in std_logic;
DCD1 : in std_logic;
TXD0 : out std_logic;
RTS0 : out std_logic;
DTR0 : out std_logic;
TXD1 : out std_logic;
RTS1 : out std_logic;
DTR1 : out std_logic
);
end entity DebugSystemXR;
architecture struct of DebugSystemXR is
signal M1_n : std_logic;
signal MREQ_n : std_logic;
signal IORQ_n : std_logic;
signal RD_n : std_logic;
signal WR_n : std_logic;
signal RFSH_n : std_logic;
signal HALT_n : std_logic;
signal WAIT_n : std_logic;
signal INT_n : std_logic;
signal RESET_s : std_logic;
signal BUSRQ_n : std_logic;
signal BUSAK_n : std_logic;
signal A_i : std_logic_vector(15 downto 0);
signal D_i : std_logic_vector(7 downto 0);
signal ROM_D : std_logic_vector(7 downto 0);
signal UART0_D : std_logic_vector(7 downto 0);
signal UART1_D : std_logic_vector(7 downto 0);
signal CPU_D : std_logic_vector(7 downto 0);
signal Mirror : std_logic;
signal IOWR_n : std_logic;
signal RAMCS_n_i : std_logic;
signal UART0CS_n : std_logic;
signal UART1CS_n : std_logic;
signal BaudOut0 : std_logic;
signal BaudOut1 : std_logic;
begin
Wait_n <= '1';
BusRq_n <= '1';
INT_n <= '1';
OE_n <= RD_n;
WE_n <= WR_n;
RAMCS_n <= RAMCS_n_i;
ROMCS_n <= '1';
PGM_n <= '1';
A(14 downto 0) <= A_i(14 downto 0);
A(16 downto 15) <= "00";
D <= D_i when WR_n = '0' else "ZZZZZZZZ";
process (Reset_n, Clk)
begin
if Reset_n = '0' then
Reset_s <= '0';
Mirror <= '0';
elsif Clk'event and Clk = '1' then
Reset_s <= '1';
if IORQ_n = '0' and A_i(7 downto 4) = "1111" then
Mirror <= D_i(0);
end if;
end if;
end process;
IOWR_n <= WR_n or IORQ_n;
RAMCS_n_i <= (not Mirror and not A_i(15)) or MREQ_n;
UART0CS_n <= '0' when IORQ_n = '0' and A_i(7 downto 3) = "00000" else '1';
UART1CS_n <= '0' when IORQ_n = '0' and A_i(7 downto 3) = "10000" else '1';
CPU_D <=
D when RAMCS_n_i = '0' else
UART0_D when UART0CS_n = '0' else
UART1_D when UART1CS_n = '0' else
ROM_D;
u0 : entity work.T80s
generic map(Mode => 1, T2Write => 1, IOWait => 0)
port map(
RESET_n => RESET_s,
CLK_n => Clk,
WAIT_n => WAIT_n,
INT_n => INT_n,
NMI_n => NMI_n,
BUSRQ_n => BUSRQ_n,
M1_n => M1_n,
MREQ_n => MREQ_n,
IORQ_n => IORQ_n,
RD_n => RD_n,
WR_n => WR_n,
RFSH_n => RFSH_n,
HALT_n => HALT_n,
BUSAK_n => BUSAK_n,
A => A_i,
DI => CPU_D,
DO => D_i);
u1 : entity work.MonZ80
port map(
Clk => Clk,
A => A_i(10 downto 0),
D => ROM_D);
u3 : entity work.T16450
port map(
MR_n => Reset_s,
XIn => Clk,
RClk => BaudOut0,
CS_n => UART0CS_n,
Rd_n => RD_n,
Wr_n => IOWR_n,
A => A_i(2 downto 0),
D_In => D_i,
D_Out => UART0_D,
SIn => RXD0,
CTS_n => CTS0,
DSR_n => DSR0,
RI_n => RI0,
DCD_n => DCD0,
SOut => TXD0,
RTS_n => RTS0,
DTR_n => DTR0,
OUT1_n => open,
OUT2_n => open,
BaudOut => BaudOut0,
Intr => open);
u4 : entity work.T16450
port map(
MR_n => Reset_s,
XIn => Clk,
RClk => BaudOut1,
CS_n => UART1CS_n,
Rd_n => RD_n,
Wr_n => IOWR_n,
A => A_i(2 downto 0),
D_In => D_i,
D_Out => UART1_D,
SIn => RXD1,
CTS_n => CTS1,
DSR_n => DSR1,
RI_n => RI1,
DCD_n => DCD1,
SOut => TXD1,
RTS_n => RTS1,
DTR_n => DTR1,
OUT1_n => open,
OUT2_n => open,
BaudOut => BaudOut1,
Intr => open);
end;
| gpl-3.0 | 6f43ccb86eeb0fa353db5f82322e8d9d | 0.558619 | 2.229289 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-digilent-nexys4/testbench.vhd | 1 | 6,675 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
use work.debug.all;
use work.config.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 10 -- system clock period
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sdramfile : string := "ram.srec"; -- sdram contents
constant lresp : boolean := false;
constant ct : integer := clkperiod/2;
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal rstn : std_logic;
signal error : std_logic;
-- PROM flash
signal address : std_logic_vector(26 downto 0):=(others =>'0');
signal data : std_logic_vector(31 downto 0);
signal RamCE : std_logic;
signal oen : std_ulogic;
signal writen : std_ulogic;
-- Debug support unit
signal dsubre : std_ulogic;
-- AHB Uart
signal dsurx : std_ulogic;
signal dsutx : std_ulogic;
-- APB Uart
signal urxd : std_ulogic;
signal utxd : std_ulogic;
-- Ethernet signals
signal erx_er : std_ulogic;
signal erx_crs : std_ulogic;
signal etxdt : std_logic_vector(1 downto 0);
-- SVGA signals
signal vid_hsync : std_ulogic;
signal vid_vsync : std_ulogic;
signal vid_r : std_logic_vector(3 downto 0);
signal vid_g : std_logic_vector(3 downto 0);
signal vid_b : std_logic_vector(3 downto 0);
-- Select signal for SPI flash
signal spi_sel_n : std_logic;
signal spi_clk : std_logic;
signal spi_mosi : std_logic;
-- Output signals for LEDs
signal led : std_logic_vector(15 downto 0);
signal brdyn : std_ulogic;
signal sw : std_logic_vector(15 downto 0):= (others =>'0');
signal btn : std_logic_vector(4 downto 0):= (others =>'0');
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
rst <= '1', '0' after 100 ns;
rstn <= not rst;
dsubre <= '0';
urxd <= 'H';
spi_sel_n <= 'H';
spi_clk <= 'L';
d3 : entity work.leon3mp
generic map (fabtech, memtech, padtech, clktech, disas, dbguart, pclow)
port map (
clk => clk,
btnCpuResetn => rstn,
-- PROM
address => address(22 downto 0),
data => data(31 downto 16),
RamOE => oen,
RamWE => writen,
RamCE => RamCE,
-- AHB Uart
RsRx => dsurx,
RsTx => dsutx,
-- PHY
PhyCrs => erx_crs,
PhyRxd => etxdt,
PhyRxEr => erx_er,
-- Output signals for LEDs
led => led,
sw => sw,
btn => btn
);
sram0 : sram
generic map (index => 4, abits => 24, fname => sdramfile)
port map (address(23 downto 0), data(31 downto 24), RamCE, writen, oen);
sram1 : sram
generic map (index => 5, abits => 24, fname => sdramfile)
port map (address(23 downto 0), data(23 downto 16), RamCE, writen, oen);
-- Ethernet model diasbled
erx_crs <= '0'; etxdt<= (others =>'0'); erx_er<= '0';
spimem0: if CFG_SPIMCTRL = 1 generate
s0 : spi_flash generic map (ftype => 4, debug => 0, fname => promfile,
readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => 0)
port map (spi_clk, spi_mosi, data(24), spi_sel_n);
end generate spimem0;
led(3) <= 'L'; -- ERROR pull-down
error <= not led(3);
iuerr : process
begin
wait for 5 us;
assert (to_X01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure;
end process;
data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#ef#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
--
-- txc(dsutx, 16#80#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end;
| gpl-3.0 | 068da3dcecef11a6235cb23a7c00b258 | 0.561498 | 3.582931 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-avnet-3s1500/testbench.vhd | 1 | 12,544 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
use work.debug.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 16; -- system clock period
comboard : integer := 1 -- Comms. adapter board attached
);
port (
pci_rst : out std_logic;
pci_clk : in std_logic;
pci_gnt : in std_logic;
pci_idsel : in std_logic;
pci_lock : inout std_logic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_logic;
pci_irdy : inout std_logic;
pci_trdy : inout std_logic;
pci_devsel : inout std_logic;
pci_stop : inout std_logic;
pci_perr : inout std_logic;
pci_par : inout std_logic;
pci_req : inout std_logic;
pci_serr : inout std_logic;
pci_host : in std_logic;
pci_66 : in std_logic
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
component leon3mp
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
mezz : integer := CFG_ADS_DAU_MEZZ
);
port (
clk_66mhz : in std_logic;
clk_socket : in std_logic;
leds : out std_logic_vector(7 downto 0);
switches : in std_logic_vector(5 downto 0);
sram_a : out std_logic_vector(24 downto 0);
sram_ben_l : out std_logic_vector(0 to 3);
sram_cs_l : out std_logic_vector(1 downto 0);
sram_oe_l : out std_logic;
sram_we_l : out std_logic;
sram_dq : inout std_logic_vector(31 downto 0);
flash_cs_l : out std_logic;
flash_rst_l : out std_logic;
iosn : out std_logic;
sdclk : out std_logic;
rasn : out std_logic;
casn : out std_logic;
sdcke : out std_logic;
sdcsn : out std_logic;
tx : out std_logic;
rx : in std_logic;
can_txd : out std_logic;
can_rxd : in std_logic;
phy_txck : in std_logic;
phy_rxck : in std_logic;
phy_rxd : in std_logic_vector(3 downto 0);
phy_rxdv : in std_logic;
phy_rxer : in std_logic;
phy_col : in std_logic;
phy_crs : in std_logic;
phy_txd : out std_logic_vector(3 downto 0);
phy_txen : out std_logic;
phy_txer : out std_logic;
phy_mdc : out std_logic;
phy_mdio : inout std_logic; -- ethernet PHY interface
phy_reset_l : inout std_logic;
video_clk : in std_logic;
comp_sync : out std_logic;
blank : out std_logic;
video_out : out std_logic_vector(23 downto 0);
msclk : inout std_logic;
msdata : inout std_logic;
kbclk : inout std_logic;
kbdata : inout std_logic;
disp_seg1 : out std_logic_vector(7 downto 0);
disp_seg2 : out std_logic_vector(7 downto 0);
pci_clk : in std_logic;
pci_gnt : in std_logic;
pci_idsel : in std_logic;
pci_lock : inout std_logic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_logic;
pci_irdy : inout std_logic;
pci_trdy : inout std_logic;
pci_devsel : inout std_logic;
pci_stop : inout std_logic;
pci_perr : inout std_logic;
pci_par : inout std_logic;
pci_req : inout std_logic;
pci_serr : inout std_logic;
pci_host : in std_logic;
pci_66 : in std_logic
);
end component;
signal clk : std_logic := '0';
constant ct : integer := clkperiod/2;
signal gnd : std_logic := '0';
signal vcc : std_logic := '1';
signal sdcke : std_logic;
signal sdcsn : std_logic;
signal sdwen : std_logic; -- write en
signal sdrasn : std_logic; -- row addr stb
signal sdcasn : std_logic; -- col addr stb
signal sddqm : std_logic_vector ( 7 downto 0); -- data i/o mask
signal sdclk : std_logic;
signal plllock : std_logic;
signal tx, rx : std_logic;
signal dsutx, dsurx : std_logic;
signal leds : std_logic_vector(7 downto 0);
signal switches : std_logic_vector(5 downto 0);
constant lresp : boolean := false;
signal sram_oe_l, sram_we_l : std_logic;
signal sram_cs_l : std_logic_vector(1 downto 0);
signal sram_ben_l : std_logic_vector(0 to 3);
signal sram_dq : std_logic_vector(31 downto 0);
signal flash_cs_l, flash_rst_l : std_logic;
signal iosn : std_logic;
signal phy_txck : std_logic;
signal phy_rxck : std_logic;
signal phy_rxd : std_logic_vector(3 downto 0);
signal phy_rxdt : std_logic_vector(7 downto 0);
signal phy_rxdv : std_logic;
signal phy_rxer : std_logic;
signal phy_col : std_logic;
signal phy_crs : std_logic;
signal phy_txd : std_logic_vector(3 downto 0);
signal phy_txdt : std_logic_vector(7 downto 0);
signal phy_txen : std_logic;
signal phy_txer : std_logic;
signal phy_mdc : std_logic;
signal phy_mdio : std_logic;
signal phy_reset_l : std_logic;
signal phy_gtx_clk : std_logic := '0';
signal video_clk : std_logic := '0';
signal comp_sync : std_logic;
signal blank : std_logic;
signal video_out : std_logic_vector(23 downto 0);
signal msclk : std_logic;
signal msdata : std_logic;
signal kbclk : std_logic;
signal kbdata : std_logic;
signal dsurst : std_logic;
signal disp_seg1 : std_logic_vector(7 downto 0);
signal disp_seg2 : std_logic_vector(7 downto 0);
signal baddr : std_logic_vector(27 downto 0) := (others => '0');
signal can_txd : std_logic;
signal can_rxd : std_logic;
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
switches(0) <= '1'; -- DSUEN
switches(4) <= not dsurst; -- reset
switches(5) <= '0'; -- DSUBRE
dsutx <= tx; rx <= dsurx;
pci_rst <= phy_reset_l;
phy_reset_l <= 'H';
video_clk <= not video_clk after 20 ns;
can_rxd <= can_txd;
sddqm(3) <= sram_ben_l(0); sddqm(2) <= sram_ben_l(1);
sddqm(1) <= sram_ben_l(2); sddqm(0) <= sram_ben_l(3);
cpu : leon3mp
generic map (fabtech, memtech, padtech, clktech,
disas, dbguart, pclow )
port map (clk, sdclk, leds, switches, baddr(24 downto 0),
sram_ben_l, sram_cs_l, sram_oe_l, sram_we_l, sram_dq,
flash_cs_l, flash_rst_l, iosn, sdclk, sdrasn, sdcasn, sdcke, sdcsn,
tx, rx, can_txd, can_rxd, phy_txck, phy_rxck, phy_rxd, phy_rxdv,
phy_rxer, phy_col, phy_crs, phy_txd, phy_txen, phy_txer, phy_mdc,
phy_mdio, phy_reset_l,
video_clk, comp_sync, blank, video_out,
msclk, msdata, kbclk, kbdata, disp_seg1, disp_seg2,
pci_clk, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr, pci_par,
pci_req, pci_serr, pci_host, pci_66);
-- One 32-bit SRAM bank on main board
sram0 : for i in 0 to 1 generate
sr0 : sram16 generic map (index => i*2, abits => 18, fname => sramfile)
port map (baddr(17 downto 0), sram_dq(31-i*16 downto 16-i*16),
sram_ben_l(i*2), sram_ben_l(i*2+1), sram_cs_l(0), sram_we_l, sram_oe_l);
end generate;
phy_mdio <= 'H';
phy_rxd <= phy_rxdt(3 downto 0);
phy_txdt <= "0000" & phy_txd;
p0: phy
generic map(base1000_t_fd => 0, base1000_t_hd => 0)
port map(dsurst, phy_mdio, phy_txck, phy_rxck, phy_rxdt, phy_rxdv,
phy_rxer, phy_col, phy_crs, phy_txdt, phy_txen, phy_txer, phy_mdc, phy_gtx_clk);
-- optional communications adapter
comms : if (comboard = 1) generate
-- 32-bit flash prom
flash0 : for i in 0 to 1 generate
sr0 : sram16 generic map (index => i*2, abits => 18, fname => promfile)
port map (baddr(19 downto 2), sram_dq(31-i*16 downto 16-i*16),
flash_cs_l, flash_cs_l, flash_cs_l, sram_we_l, sram_oe_l);
end generate;
-- second SRAM bank
sram1 : for i in 0 to 1 generate
sr0 : sram16 generic map (index => i*2, abits => 18, fname => sramfile)
port map (baddr(19 downto 2), sram_dq(31-i*16 downto 16-i*16),
sram_ben_l(i*2), sram_ben_l(i*2+1), sram_cs_l(1), sram_we_l, sram_oe_l);
end generate;
sdwen <= sram_we_l;
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sram_dq(31 downto 16), Addr => baddr(14 downto 2),
Ba => baddr(16 downto 15), Clk => sdclk, Cke => sdcke,
Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sram_dq(15 downto 0), Addr => baddr(14 downto 2),
Ba => baddr(16 downto 15), Clk => sdclk, Cke => sdcke,
Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
end generate;
test0 : grtestmod
port map ( dsurst, clk, leds(0), baddr(21 downto 2), sram_dq,
iosn, sram_oe_l, sram_we_l, open);
leds(0) <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2000 ns;
if to_x01(leds(0)) = '0' then wait on leds; end if;
assert (to_x01(leds(0)) = '0')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
sram_dq <= buskeep(sram_dq), (others => 'H') after 250 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_logic; signal dsutx : out std_logic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#ef#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
| gpl-3.0 | 4140d9fb7a8ebba52d595c1122d59f0f | 0.597258 | 3.052068 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-nuhorizons-3s1500/config.vhd | 1 | 6,371 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := spartan3;
constant CFG_MEMTECH : integer := spartan3;
constant CFG_PADTECH : integer := spartan3;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := spartan3;
constant CFG_CLKMUL : integer := (4);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 1;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 1;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 8;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#00f3#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#00002B#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 1;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- CAN 2.0 interface
constant CFG_CAN : integer := 1;
constant CFG_CANIO : integer := 16#C00#;
constant CFG_CANIRQ : integer := (13);
constant CFG_CANLOOP : integer := 0;
constant CFG_CAN_SYNCRST : integer := 0;
constant CFG_CANFT : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- UART 2
constant CFG_UART2_ENABLE : integer := 0;
constant CFG_UART2_FIFO : integer := 1;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#fffe#;
constant CFG_GRGPIO_WIDTH : integer := (16);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-3.0 | 012e2f9a36eb8f7e867ab93c68c82c54 | 0.643541 | 3.597403 | false | false | false | false |
yishinli/emc2 | src/hal/drivers/m5i20/hostmot5_src/pwmrefh.vhd | 1 | 3,662 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity pwmrefh is
Port (
clk: in STD_LOGIC;
hclk: in STD_LOGIC;
refcount: out STD_LOGIC_VECTOR (9 downto 0);
irqgen: out STD_LOGIC;
ibus: in STD_LOGIC_VECTOR (15 downto 0);
obus: out STD_LOGIC_VECTOR (15 downto 0);
irqdivload: in STD_LOGIC;
irqdivread: in STD_LOGIC;
phaseload: in STD_LOGIC;
phaseread: in STD_LOGIC
);
end pwmrefh;
architecture behavioral of pwmrefh is
signal count: STD_LOGIC_VECTOR (9 downto 0);
signal irqdivisor: STD_LOGIC_VECTOR (7 downto 0);
signal preirqdivisor: STD_LOGIC_VECTOR (7 downto 0);
signal irqcounter: STD_LOGIC_VECTOR (7 downto 0);
signal phaseacc: STD_LOGIC_VECTOR (16 downto 0);
alias phasemsb: std_logic is phaseacc(16);
signal oldphasemsb: STD_LOGIC;
signal phaselatch: STD_LOGIC_VECTOR (15 downto 0);
signal prephaselatch: STD_LOGIC_VECTOR (15 downto 0);
signal irqdivloadreq: STD_LOGIC;
signal oldirqdivloadreq: STD_LOGIC;
signal olderirqdivloadreq: STD_LOGIC;
signal phaselatchloadreq: STD_LOGIC;
signal oldphaselatchloadreq: STD_LOGIC;
signal olderphaselatchloadreq: STD_LOGIC;
signal irqgenreq: STD_LOGIC;
signal oldirqgenreq: STD_LOGIC;
signal olderirqgenreq: STD_LOGIC;
signal irqgenint: STD_LOGIC;
begin
apwmref: process (clk,
irqdivload,
count,
irqcounter,
irqdivisor,
ibus,
irqdivread,
phaseread)
begin
if hclk'event and hclk = '1' then -- 100 Mhz high speed clock
if oldirqdivloadreq = '1' and olderirqdivloadreq = '1' then -- these are for crossing 33 Mhz/100 MHz
irqdivisor <= preirqdivisor; -- clock domains
irqcounter <= preirqdivisor;
end if;
if oldphaselatchloadreq = '1' and olderphaselatchloadreq = '1' then
phaselatch <= prephaselatch;
end if;
oldirqdivloadreq <= irqdivloadreq;
oldphaselatchloadreq <= phaselatchloadreq;
olderirqdivloadreq <= oldirqdivloadreq;
olderphaselatchloadreq <= oldphaselatchloadreq;
phaseacc <= phaseacc + phaselatch;
oldphasemsb <= phasemsb;
if oldphasemsb /= phasemsb then
count <= count + 1;
if count = 0 then
irqcounter <= irqcounter -1;
if irqcounter = 0 then
irqgenreq <= '1';
irqcounter <= irqdivisor;
end if; -- irqcounter = 0
end if; -- count = 0
end if; -- old /= new
end if; -- hclk
if clk'event and clk = '1' then -- 33 Mhz local clock
if olderirqgenreq = '0' and oldirqgenreq = '1' then -- just one 33 mhz clk wide
irqgenint <= '1';
else
irqgenint <='0';
end if;
olderirqgenreq <= oldirqgenreq;
oldirqgenreq <= irqgenreq;
if irqdivload = '1' then
preirqdivisor <= ibus(7 downto 0);
irqdivloadreq <= '1';
end if;
if phaseload = '1' then
prephaselatch <= ibus;
phaselatchloadreq <= '1';
end if;
end if; -- clk
if olderirqdivloadreq = '1' then -- asyncronous request clear
irqdivloadreq <= '0';
end if;
if olderphaselatchloadreq = '1' then -- asyncronous request clear
phaselatchloadreq <= '0';
end if;
if olderirqgenreq = '1' then -- asyncronous request clear
irqgenreq <= '0';
end if;
if irqdivread = '1' and phaseread = '0' then
obus(7 downto 0) <= irqdivisor;
obus(15 downto 8) <= x"00";
elsif phaseread = '1' and irqdivread = '0' then
obus <= phaselatch;
else
obus <= "ZZZZZZZZZZZZZZZZ";
end if;
refcount <= count;
irqgen <= irqgenint;
end process;
end behavioral;
| lgpl-2.1 | 4f82f1966f4b2c865a297f844274f4c3 | 0.644457 | 3.082492 | false | false | false | false |
hoglet67/CoPro6502 | src/DCM/dcm_32_80.vhd | 1 | 2,185 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity dcm_32_80 is
port (CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic);
end dcm_32_80;
architecture BEHAVIORAL of dcm_32_80 is
signal CLKFX_BUF : std_logic;
signal CLK2X_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKFX_BUFG_INST : BUFG
port map (I => CLKFX_BUF, O => CLK0_OUT);
CLK2X_BUFG_INST : BUFG
port map (I => CLK2X_BUF, O => CLK2X_OUT);
DCM_INST : DCM
generic map(CLK_FEEDBACK => "NONE",
CLKDV_DIVIDE => 4.0, -- 80.00 = 32.000 * 10/4
CLKFX_MULTIPLY => 10,
CLKFX_DIVIDE => 4,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => 31.25,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => true,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => false)
port map (CLKFB => GND_BIT,
CLKIN => CLKIN_IN,
DSSEN => GND_BIT,
PSCLK => GND_BIT,
PSEN => GND_BIT,
PSINCDEC => GND_BIT,
RST => GND_BIT,
CLKDV => open,
CLKFX => CLKFX_BUF,
CLKFX180 => open,
CLK0 => open,
CLK2X => CLK2X_BUF,
CLK2X180 => open,
CLK90 => open,
CLK180 => open,
CLK270 => open,
LOCKED => open,
PSDONE => open,
STATUS => open);
end BEHAVIORAL;
| gpl-3.0 | 2ac733f11a407b57f786881e6530acb5 | 0.413272 | 4.084112 | false | false | false | false |
pwsoft/fpga_examples | rtl/chameleon/chameleon_c64_joykeyb.vhd | 1 | 9,207 | -- -----------------------------------------------------------------------
--
-- Turbo Chameleon
--
-- Multi purpose FPGA expansion for the Commodore 64 computer
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2017 by Peter Wendrich ([email protected])
-- http://www.syntiac.com
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
--
-- Keyboard/joystick readout in cartridge mode
--
-- -----------------------------------------------------------------------
-- clk - system clock
-- ena_1mhz - Enable must be '1' one clk cycle each 1 Mhz.
-- no_clock - High when there is no phi-2 clock, the joystick and keyboard
-- information will be unavailable.
-- reset - system reset
--
-- ba - Status of the BA line on the cartridge port
-- req - Toggles to perform a C64 access
-- ack - Acknoledge of the C64 access, becomes equal to req when complete.
-- we - Low performs read access, high performs write access
-- a - Address for C64 access
-- d - Data input from the C64 cartridge port
-- q - Data output for write accesses
--
-- joystick* - Joystick outputs (fire2, fire1, right, left, down, up) low active
-- keys - State of the keyboard (low is pressed)
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
-- -----------------------------------------------------------------------
entity chameleon_c64_joykeyb is
generic (
enable_4player : boolean
);
port (
clk : in std_logic;
ena_1mhz : in std_logic;
no_clock : in std_logic;
reset : in std_logic;
-- To C64 cartridge logic
ba : in std_logic;
req : out std_logic;
ack : in std_logic;
we : out std_logic;
a : out unsigned(15 downto 0);
d : in unsigned(7 downto 0);
q : out unsigned(7 downto 0);
joystick1 : out unsigned(6 downto 0);
joystick2 : out unsigned(6 downto 0);
joystick3 : out unsigned(6 downto 0);
joystick4 : out unsigned(6 downto 0);
-- 0 = col0, row0
-- 1 = col1, row0
-- 8 = col0, row1
-- 63 = col7, row7
keys : out unsigned(63 downto 0)
);
end entity;
-- -----------------------------------------------------------------------
architecture rtl of chameleon_c64_joykeyb is
type state_t is (
INIT_RESET, INIT_DISABLE_VIC, INIT_DISABLE_MOB,
INIT_CIA1_A, INIT_CIA1_B, INIT_CIA2_B, --INIT_CIA2_A, ,
SET_COL, READ_ROW, STORE_ROW, SET_NOCOL,
READ_JOY_EXTRA1, READ_JOY_EXTRA2, READ_JOY_EXTRA3,
READ_JOY1, STORE_JOY1, STORE_JOY2,
READ_JOY34, STORE_JOY34);
signal state : state_t := INIT_RESET;
signal req_reg : std_logic := '0';
signal joy34_flag : std_logic := '0';
signal cnt : unsigned(3 downto 0) := (others => '0');
signal pot_flag : std_logic := '0';
signal potcnt : unsigned(9 downto 0) := (others => '0');
signal col : integer range 0 to 7 := 0;
signal joystick1_reg : unsigned(joystick1'range) := (others => '1');
signal joystick2_reg : unsigned(joystick2'range) := (others => '1');
signal joystick3_reg : unsigned(joystick3'range) := (others => '1');
signal joystick4_reg : unsigned(joystick4'range) := (others => '1');
signal keys_reg : unsigned(63 downto 0) := (others => '1');
begin
joystick1 <= joystick1_reg;
joystick2 <= joystick2_reg;
joystick3 <= joystick3_reg;
joystick4 <= joystick4_reg;
keys <= keys_reg;
req <= req_reg;
process(clk)
begin
if rising_edge(clk) then
if ena_1mhz = '1' then
cnt <= cnt - 1;
if cnt = 0 then
cnt <= (others => '0');
end if;
end if;
if (req_reg = ack) and (ba = '1') and (cnt = 0) then
we <= '-';
a <= (others => '-');
q <= (others => '-');
case state is
when INIT_RESET =>
if (reset = '0') and (ba = '1') then
state <= INIT_DISABLE_VIC;
end if;
when INIT_DISABLE_VIC =>
-- Turn off VIC-II raster DMA, so we don't have to deal with BA.
we <= '1';
a <= X"D011";
q <= X"00";
req_reg <= not req_reg;
state <= INIT_DISABLE_MOB;
when INIT_DISABLE_MOB =>
-- Turn off VIC-II sprite DMA, so we don't have to deal with BA.
we <= '1';
a <= X"D015";
q <= X"00";
req_reg <= not req_reg;
state <= INIT_CIA1_A;
when INIT_CIA1_A =>
-- Set keyboard columns port (joy2) to output
we <= '1';
a <= X"DC02";
q <= X"FF";
req_reg <= not req_reg;
state <= INIT_CIA1_B;
when INIT_CIA1_B =>
-- Set keyboard rows port (joy1) to input
we <= '1';
a <= X"DC03";
q <= X"00";
req_reg <= not req_reg;
state <= SET_COL;
if enable_4player then
state <= INIT_CIA2_B;
end if;
when INIT_CIA2_B =>
-- Set CIA2 port B for 4 player adapter
-- Bit7 output and others input.
we <= '1';
a <= X"DD03";
q <= X"80";
req_reg <= not req_reg;
state <= SET_COL;
when SET_COL =>
we <= '1';
a <= X"DC00";
q <= to_unsigned(255 - 2**col, 8);
req_reg <= not req_reg;
cnt <= (others => '1');
state <= READ_ROW;
when READ_ROW =>
we <= '0';
a <= X"DC01";
req_reg <= not req_reg;
state <= STORE_ROW;
when STORE_ROW =>
keys_reg(0 + col) <= d(0);
keys_reg(8 + col) <= d(1);
keys_reg(16 + col) <= d(2);
keys_reg(24 + col) <= d(3);
keys_reg(32 + col) <= d(4);
keys_reg(40 + col) <= d(5);
keys_reg(48 + col) <= d(6);
keys_reg(56 + col) <= d(7);
if col /= 7 then
col <= col + 1;
state <= SET_COL;
else
col <= 0;
state <= SET_NOCOL;
end if;
when SET_NOCOL =>
we <= '1';
a <= X"DC00";
if pot_flag = '0' then
q <= X"BF"; -- paddle port 1
else
q <= X"7F"; -- paddle port 2
end if;
req_reg <= not req_reg;
cnt <= (others => '1');
potcnt <= potcnt + 1;
if potcnt(9) = '1' then
potcnt <= "0000000000";
pot_flag <= not pot_flag;
state <= READ_JOY_EXTRA1;
else
state <= SET_NOCOL; -- wait
end if;
when READ_JOY_EXTRA1 =>
we <= '0';
a <= X"D419"; -- POTX
req_reg <= not req_reg;
state <= READ_JOY_EXTRA2;
when READ_JOY_EXTRA2 =>
we <= '0';
a <= X"D41A"; -- POTY
req_reg <= not req_reg;
if pot_flag = '0' then
joystick1_reg(5) <= d(7); -- paddle port 1
else
joystick2_reg(5) <= d(7); -- paddle port 2
end if;
state <= READ_JOY_EXTRA3;
when READ_JOY_EXTRA3 =>
we <= '1';
a <= X"DC00";
q <= X"FF";
req_reg <= not req_reg;
if pot_flag = '0' then
joystick1_reg(6) <= d(7); -- paddle port 1
else
joystick2_reg(6) <= d(7); -- paddle port 2
end if;
state <= READ_JOY1;
when READ_JOY1 =>
-- read joystick port 1
we <= '0';
a <= X"DC01";
req_reg <= not req_reg;
state <= STORE_JOY1;
when STORE_JOY1 =>
-- read joystick port 2
we <= '0';
a <= X"DC00";
req_reg <= not req_reg;
joystick1_reg(4 downto 0) <= d(4 downto 0);
state <= STORE_JOY2;
when STORE_JOY2 =>
joystick2_reg(4 downto 0) <= d(4 downto 0);
state <= SET_COL;
if enable_4player then
state <= READ_JOY34;
end if;
when READ_JOY34 =>
-- read user port for joystick 3 or 4
we <= '0';
a <= X"DD01";
req_reg <= not req_reg;
state <= STORE_JOY34;
when STORE_JOY34 =>
joystick3_reg(4) <= d(5);
joystick4_reg(4) <= d(4);
if joy34_flag = '0' then
joystick4_reg(3 downto 0) <= d(3 downto 0);
else
joystick3_reg(3 downto 0) <= d(3 downto 0);
end if;
-- select the other joystick (3 or 4) on the userport
we <= '1';
a <= X"DD01";
q <= joy34_flag & "0000000";
joy34_flag <= not joy34_flag;
req_reg <= not req_reg;
state <= SET_COL;
end case;
end if;
if reset = '1' then
state <= INIT_RESET;
end if;
if no_clock = '1' then
joystick1_reg <= (others => '1');
joystick2_reg <= (others => '1');
joystick3_reg <= (others => '1');
joystick4_reg <= (others => '1');
keys_reg <= (others => '1');
end if;
if not enable_4player then
joystick3_reg <= (others => '1');
joystick4_reg <= (others => '1');
end if;
-- No second and third button on 4 player adapter
joystick3_reg(6 downto 5) <= "11";
joystick4_reg(6 downto 5) <= "11";
end if;
end process;
end architecture;
| lgpl-2.1 | 05c03bb81517026f71d2bd50d09be266 | 0.527859 | 3 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-altera-c5ekit/pllsim.vhd | 1 | 1,486 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee;
use ieee.std_logic_1164.all;
entity syspll1 is
port (
refclk : in std_logic := 'X'; -- clk
rst : in std_logic := 'X'; -- reset
outclk_0 : out std_logic; -- clk
locked : out std_logic -- export
);
end;
architecture sim of syspll1 is
begin
p: process
variable vclk: std_logic := '0';
begin
outclk_0 <= vclk;
wait for 5.555 ns;
vclk := not vclk;
end process;
locked <= '0', '1' after 1 us;
end;
| gpl-3.0 | 0e00f2332321f03cbfa78e431d328b13 | 0.632571 | 3.85974 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/can/can_oc.vhd | 1 | 5,737 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: can_oc
-- File: can_oc.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB interface for the OpenCores CAN MAC
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.can.all;
entity can_oc is
generic (
slvndx : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#FF0#;
irq : integer := 0;
memtech : integer := DEFMEMTECH;
syncrst : integer := 0;
ft : integer := 0);
port (
resetn : in std_logic;
clk : in std_logic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
can_rxi : in std_logic;
can_txo : out std_logic
);
end;
architecture rtl of can_oc is
constant ncores : integer := 1;
constant sepirq : integer := 0;
constant REVISION : amba_version_type := ncores-1;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_CANAHB, 0, REVISION, irq),
4 => ahb_iobar(ioaddr, iomask), others => zero32);
type ahbregs is record
hsel : std_ulogic;
hwrite : std_ulogic;
hwrite2 : std_ulogic;
htrans : std_logic_vector(1 downto 0);
haddr : std_logic_vector(10 downto 0);
hwdata : std_logic_vector(7 downto 0);
herr : std_ulogic;
hready : std_ulogic;
ws : std_logic_vector(1 downto 0);
irqi : std_logic_vector(ncores-1 downto 0);
irqo : std_logic_vector(ncores-1 downto 0);
end record;
subtype cdata is std_logic_vector(7 downto 0);
type cdataarr is array (0 to 7) of cdata;
signal data_out : cdataarr;
signal reset : std_logic;
signal irqo : std_logic_vector(ncores-1 downto 0);
signal vcc, gnd : std_ulogic;
signal r, rin : ahbregs;
attribute sync_set_reset : string;
attribute sync_set_reset of reset : signal is "true";
begin
gnd <= '0'; vcc <= '1'; reset <= not resetn;
comb : process(ahbsi, r, resetn, data_out, irqo)
variable v : ahbregs;
variable hresp : std_logic_vector(1 downto 0);
variable dataout : std_logic_vector(7 downto 0);
variable irqvec : std_logic_vector(NAHBIRQ-1 downto 0);
variable hwdata : std_logic_vector(31 downto 0);
begin
v := r;
hwdata := ahbreadword(ahbsi.hwdata, r.haddr(4 downto 2));
if (r.hsel = '1' ) and (r.ws /= "11") then v.ws := r.ws + 1; end if;
if ahbsi.hready = '1' then
v.hsel := ahbsi.hsel(slvndx);
v.haddr := ahbsi.haddr(10 downto 0);
v.htrans := ahbsi.htrans;
v.hwrite := ahbsi.hwrite;
v.herr := orv(ahbsi.hsize) and ahbsi.hwrite;
v.ws := "00";
end if;
v.hready := (r.hsel and r.ws(1) and not r.ws(0)) or not resetn
or (ahbsi.hready and not ahbsi.htrans(1)) or not v.hsel;
v.hwrite2 := r.hwrite and r.hsel and r.htrans(1) and r.ws(1)
and not r.ws(0) and not r.herr;
if (r.herr and r.ws(1)) = '1' then hresp := HRESP_ERROR;
else hresp := HRESP_OKAY; end if;
case r.haddr(1 downto 0) is
when "00" => v.hwdata := hwdata(31 downto 24);
when "01" => v.hwdata := hwdata(23 downto 16);
when "10" => v.hwdata := hwdata(15 downto 8);
when others => v.hwdata := hwdata(7 downto 0);
end case;
dataout := data_out(0);
-- Interrupt goes to low when appeard and is normal high
-- but the irq controller from leon is active high and the interrupt should appear only
-- for 1 Clk cycle,
v.irqi := irqo; v.irqo:= (r.irqi and not irqo);
irqvec := (others => '0');
if sepirq = 1 then irqvec(ncores-1+irq downto irq) := r.irqo;
else irqvec(irq) := orv(r.irqo); end if;
ahbso.hirq <= irqvec;
ahbso.hrdata <= ahbdrivedata(dataout);
ahbso.hresp <= hresp; rin <= v;
end process;
reg : process(clk)
begin if clk'event and clk = '1' then r <= rin; end if; end process;
cmod : can_mod generic map (memtech, syncrst, ft)
port map (reset, clk, r.hsel, r.hwrite2, r.haddr(7 downto 0), r.hwdata,
data_out(0), irqo(0), can_rxi, can_txo, ahbsi.testen);
ahbso.hconfig <= hconfig;
ahbso.hindex <= slvndx;
ahbso.hsplit <= (others => '0');
ahbso.hready <= r.hready;
-- pragma translate_off
bootmsg : report_version
generic map (
"can_oc" & tost(slvndx) &
": SJA1000 Compatible CAN MAC, revision " & tost(REVISION) &
", irq " & tost(irq));
-- pragma translate_on
end;
| gpl-3.0 | 3e80d03700cd5911cbdd658dc0f5e2f7 | 0.595607 | 3.541358 | false | false | false | false |
yishinli/emc2 | src/hal/drivers/m5i20/hostmot5_src/gmodereg.vhd | 1 | 2,223 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity globalmodereg is
port (
clk: in STD_LOGIC;
ibus: in STD_LOGIC_VECTOR (15 downto 0);
obus: out STD_LOGIC_VECTOR (15 downto 0);
reset: in STD_LOGIC;
loadglobalmode: in STD_LOGIC;
readglobalmode: in STD_LOGIC;
ctrena: out STD_LOGIC;
pwmena: out STD_LOGIC;
clearpwmena: in STD_LOGIC;
loi: out STD_LOGIC;
som: out STD_LOGIC;
sot: out STD_LOGIC;
miout: out STD_LOGIC;
miin: in STD_LOGIC;
irqmask: out STD_LOGIC;
irqstatus: in STD_LOGIC
);
end globalmodereg;
architecture behavioral of globalmodereg is
signal ctrenareg: STD_LOGIC;
signal pwmenareg: STD_LOGIC;
signal loireg: STD_LOGIC;
signal somreg: STD_LOGIC;
signal sotreg: STD_LOGIC;
signal mioutreg: STD_LOGIC;
signal irqmaskreg: STD_LOGIC;
begin
aglobalmodereg: process(
clk,
ibus,
loadglobalmode,
reset,
readglobalmode,
ctrenareg,
pwmenareg,
clearpwmena,
loireg,
somreg,
sotreg,
mioutreg,
miin
)
begin
if clk'event and clk = '1' then
if reset = '1' then
ctrenareg <= '0';
pwmenareg <= '0';
loireg <= '0';
somreg <= '0';
sotreg <= '0';
mioutreg <= '1';
irqmaskreg <= '0';
elsif loadglobalmode = '1' then
ctrenareg <= ibus(0);
pwmenareg <= ibus(1);
loireg <= ibus(2);
somreg <= ibus(3);
mioutreg <= not ibus(4);
irqmaskreg <= ibus(5);
sotreg <= ibus(7);
end if;
if mioutreg = '1' then
mioutreg <= '0';
end if;
end if;
if clearpwmena = '1' then
pwmenareg <= '0';
end if;
if readglobalmode = '1' then
obus(0) <= ctrenareg;
obus(1) <= pwmenareg;
obus(2) <= loireg;
obus(3) <= somreg;
obus(4) <= miin;
obus(5) <= irqmaskreg;
obus(6) <= irqstatus;
obus(7) <= sotreg;
obus(15 downto 8) <= "ZZZZZZZZ";
else
obus <= "ZZZZZZZZZZZZZZZZ";
end if;
ctrena <= ctrenareg;
pwmena <= pwmenareg;
loi <= loireg;
miout <= mioutreg or reset;
som <= somreg;
irqmask <= irqmaskreg;
sot <= sotreg;
end process;
end behavioral;
| lgpl-2.1 | 873abdcd327a69bfde5a9b4bc8b4e96b | 0.568151 | 2.785714 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-terasic-de0-nano/testbench.vhd | 1 | 6,567 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2012 Aeroflex Gaisler
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
use work.debug.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library grlib;
use grlib.stdlib.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
romdepth : integer := 22 -- rom address depth (flash 4 MB)
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec";
constant sdramfile : string := "ram.srec";
signal clock_50 : std_logic := '0';
signal led : std_logic_vector(7 downto 0);
signal key : std_logic_vector(1 downto 0);
signal sw : std_logic_vector(3 downto 0);
signal dram_ba : std_logic_vector(1 downto 0);
signal dram_dqm : std_logic_vector(1 downto 0);
signal dram_ras_n : std_ulogic;
signal dram_cas_n : std_ulogic;
signal dram_cke : std_ulogic;
signal dram_clk : std_ulogic;
signal dram_we_n : std_ulogic;
signal dram_cs_n : std_ulogic;
signal dram_dq : std_logic_vector(15 downto 0);
signal dram_addr : std_logic_vector(12 downto 0);
signal epcs_data0 : std_logic;
signal epcs_dclk : std_logic;
signal epcs_ncso : std_logic;
signal epcs_asdo : std_logic;
signal i2c_sclk : std_logic;
signal i2c_sdat : std_logic;
signal g_sensor_cs_n : std_ulogic;
signal g_sensor_int : std_ulogic;
signal adc_cs_n : std_ulogic;
signal adc_saddr : std_ulogic;
signal adc_sclk : std_ulogic;
signal adc_sdat : std_ulogic;
signal gpio_2 : std_logic_vector(12 downto 0);
signal gpio_2_in : std_logic_vector(2 downto 0);
signal gpio_1_in : std_logic_vector(1 downto 0);
signal gpio_1 : std_logic_vector(33 downto 0);
signal gpio_0_in : std_logic_vector(1 downto 0);
signal gpio_0 : std_logic_vector(33 downto 0);
begin
clock_50 <= not clock_50 after 10 ns; --50 MHz clk
key(0) <= '0', '1' after 300 ns;
key(1) <= '1'; -- DSU break, disabled
sw <= (others => 'H');
gpio_0 <= (others => 'H');
gpio_0_in <= (others => 'H');
gpio_1 <= (others => 'H');
gpio_1_in <= (others => 'H');
gpio_2 <= (others => 'H');
gpio_2_in <= (others => 'H');
led(5 downto 0) <= (others => 'H');
d3 : entity work.leon3mp
generic map ( fabtech, memtech, padtech, clktech, disas, dbguart, pclow )
port map (
clock_50 => clock_50,
led => led,
key => key,
sw => sw,
dram_ba => dram_ba,
dram_dqm => dram_dqm,
dram_ras_n => dram_ras_n,
dram_cas_n => dram_cas_n,
dram_cke => dram_cke,
dram_clk => dram_clk,
dram_we_n => dram_we_n,
dram_cs_n => dram_cs_n,
dram_dq => dram_dq,
dram_addr => dram_addr,
epcs_data0 => epcs_data0,
epcs_dclk => epcs_dclk,
epcs_ncso => epcs_ncso,
epcs_asdo => epcs_asdo,
i2c_sclk => i2c_sclk,
i2c_sdat => i2c_sdat,
g_sensor_cs_n => g_sensor_cs_n,
g_sensor_int => g_sensor_int,
adc_cs_n => adc_cs_n,
adc_saddr => adc_saddr,
adc_sclk => adc_sclk,
adc_sdat => adc_sdat,
gpio_2 => gpio_2,
gpio_2_in => gpio_2_in,
gpio_1_in => gpio_1_in,
gpio_1 => gpio_1,
gpio_0_in => gpio_0_in,
gpio_0 => gpio_0);
sd1 : if (CFG_SDCTRL /= 0) generate
u1: entity work.mt48lc16m16a2 generic map (addr_bits => 13, col_bits => 8, index => 1024, fname => sdramfile)
PORT MAP(
Dq => dram_dq, Addr => dram_addr, Ba => dram_ba, Clk => dram_clk,
Cke => dram_cke, Cs_n => dram_cs_n, Ras_n => dram_ras_n,
Cas_n => dram_cas_n, We_n => dram_we_n, Dqm => dram_dqm);
end generate;
dram_dq <= buskeep(dram_dq) after 5 ns;
spif : if CFG_SPIMCTRL /= 0 generate
spi0: spi_flash
generic map (
ftype => 4,
debug => 0,
fname => promfile,
readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => CFG_SPIMCTRL_DUALOUTPUT,
memoffset => CFG_SPIMCTRL_OFFSET)
port map (
sck => epcs_dclk,
di => epcs_asdo,
do => epcs_data0,
csn => epcs_ncso,
sd_cmd_timeout => open,
sd_data_timeout => open);
end generate;
iuerr : process
begin
wait for 2500 ns;
if to_x01(led(6)) = '1' then wait on led(6); end if;
assert (to_x01(led(6)) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
end ;
| gpl-3.0 | d134f7e01a91a18fd8e58113f69e86b9 | 0.539668 | 3.532544 | false | false | false | false |
ggaray/nicsim-vhd | clkgen.vhd | 1 | 2,858 | -- NICSim-vhd: A VHDL-based modelling and simulation of NIC's buffers
-- Copyright (C) 2013 Godofredo R. Garay <godofredo.garay (-at-) gmail.com>
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
entity clkgen is
port (
pciclk : out bit;
nicclk : out bit;
ethclk : out bit
);
end clkgen;
architecture V1 of clkgen is
--------------- Line speed configuration ---------------
--constant ethclk_period : time := 0.1 us; --Ethernet
--constant ethclk_period : time := 0.01 us; -- Fast Ethernet
constant ethclk_period : time := 0.001 us; -- Gigabit Ethernet
--constant ethclk_period : time := 0.0001 us; -- 10 Gigabit Ethernet
--constant ethclk_period : time := 0.00001 us; -- 100 Gigabit Ethernet
--------------- I/O-bus speed configuration ---------------
--constant pciclk_period : time := 0.03030303 us; -- PCI 33
--constant pciclk_period : time := 0.015151515 us; -- PCI-X 66
constant pciclk_period : time := 0.007518797 us; -- PCI-X 133
--constant pciclk_period : time := 0.003759398 us; -- PCI-X 266
--constant pciclk_period : time := 0.001876173 us; -- PCI-X 533
--constant freq : integer := 33; -- PCI Clock in MHz
--constant clk_period : time := 1/freq; -- Clock Period in microseconds
--constant eth_freq : time := 10; -- Ethernet Clock in MHz
constant pcitpw : time := pciclk_period/2; --Pulse width (0 and 1) of the PCI Clock
constant nicclk_period : time := pciclk_period/100; -- NIC Clock Period (this clock 100 times faster than IO-bus clock)
constant nictpw : time := nicclk_period/2; -- Pulse width (0 and 1) of the Memory Clock
constant ethtpw : time := ethclk_period/2; -- Pulse width (0 and 1) of the Ethernet Clock
begin
pci_clock_generator: process
begin
pciclk <= '0', '1' after pcitpw;
wait for pciclk_period;
end process pci_clock_generator;
nic_clock_generator: process
begin
nicclk <= '1', '0' after nictpw;
wait for nicclk_period;
end process nic_clock_generator;
eth_clock_generator: process
begin
ethclk <= '1', '0' after ethtpw;
wait for ethclk_period;
end process eth_clock_generator;
end V1;
| gpl-3.0 | c3a55372e8f6f3ae0050802a8edc815b | 0.646256 | 3.186176 | false | false | false | false |
pwsoft/fpga_examples | rtl/chameleon/chameleon_phi_clock_a.vhd | 1 | 5,546 | -- -----------------------------------------------------------------------
--
-- VGA-64
--
-- Multi purpose FPGA expansion for the Commodore 64 computer
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2018 by Peter Wendrich ([email protected])
-- http://www.syntiac.com/chameleon.html
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
--
-- C64 Phi2-clock regeneration and divider
--
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
-- -----------------------------------------------------------------------
architecture rtl of chameleon_phi_clock is
constant guardBits : integer := 4; -- Extra bits to reduce rounding errors in calculations
signal phi2_n_reg : unsigned(11 downto 0) := (others => '0');
signal phiSync : std_logic := '0';
signal locCnt : unsigned(7 downto 0) := (others => '0');
signal fracCnt : unsigned(guardBits-1 downto 0) := (others => '0');
signal c64Cnt : unsigned(7 downto 0) := (others => '0');
signal slvCnt : unsigned(7 downto 0) := (others => '0');
signal avgDelta : signed(8 downto 0) := (others => '0');
signal avgLen : unsigned((7+guardBits) downto 0) := (others => '0');
signal localPreHalf : std_logic := '0';
signal localHalf : std_logic := '0';
signal localPreEnd : std_logic := '0';
signal localEnd : std_logic := '0';
signal localPhi : std_logic := '0';
signal localPost1 : std_logic := '0';
signal localPost2 : std_logic := '0';
signal localPost3 : std_logic := '0';
signal localPost4 : std_logic := '0';
begin
-- Average phi length
phiLength <= avgLen((7+guardBits) downto guardBits);
-- Local generated phi
phiLocal <= localPhi;
-- Cycle counter (add 1 to max-counter for each Mhz system clock)
-- For 100Mhz the cycle-counter runs to about 97 (NTSC) or 102 (PAL)
phiCnt <= locCnt;
phiPreHalf <= localPreHalf;
phiHalf <= localHalf;
phiPreEnd <= localPreEnd;
phiEnd <= localEnd;
phiPost1 <= localPost1;
phiPost2 <= localPost2;
phiPost3 <= localPost3;
phiPost4 <= localPost4;
-- Input clock synchronizer
process(clk) is
begin
if rising_edge(clk) then
phiSync <= '0';
phi2_n_reg <= phi2_n_reg(phi2_n_reg'high-1 downto 0) & phi2_n;
-- Detect falling edge of phi2 (is rising edge here as phi2_n input is inverted).
if phi2_n_reg = "000000000001" then
phiSync <= '1';
end if;
end if;
end process;
-- Determine cycle length
process(clk) is
begin
if rising_edge(clk) then
no_clock <= '0';
docking_station <= '0';
avgDelta <= (others => '0');
avgLen <= unsigned(signed(avgLen) + avgDelta);
if (not c64Cnt) /= 0 then
c64Cnt <= c64Cnt + 1;
else
-- No Sync? Use internal speed.
-- Values for avgLen are determined experimentally using the testbench to measure actually speed.
-- Higher numbers slow down clock. Lower numbers speed clock up. Try a few times until optimum is reached
-- for particular system clock (100 Mhz at time of writing). Clocks can be accurate to atleast 3 digits with 4 guard bits.
-- PAL mode 0.985248 Mhz
avgLen <= to_unsigned(1703, 8+guardBits);
if mode = '1' then
-- NTSC mode 1.022727 Mhz
avgLen <= to_unsigned(1643, 8+guardBits);
end if;
if phi2_n_reg(11 downto 4) = "11111111" then
docking_station <= '1';
end if;
no_clock <= '1';
end if;
if phiSync = '1' then
avgDelta <= signed("0" & c64Cnt) - signed("0" & avgLen((7+guardBits) downto guardBits));
c64Cnt <= (others => '0');
end if;
end if;
end process;
process(clk) is
begin
if rising_edge(clk) then
localPost1 <= localHalf or localEnd;
localPost2 <= localPost1;
localPost3 <= localPost2;
localPost4 <= localPost3;
end if;
end process;
process(clk) is
variable newFrac : unsigned(fracCnt'high+1 downto fracCnt'low);
begin
if rising_edge(clk) then
localPreHalf <= '0';
localHalf <= localPreHalf;
localPreEnd <= '0';
localEnd <= localPreEnd;
locCnt <= locCnt + 1;
if slvCnt >= avgLen((7+guardBits) downto guardBits) then
slvCnt <= (others => '0');
else
slvCnt <= slvCnt + 1;
end if;
if (slvCnt + phase_shift) = avgLen((7+guardBits) downto (1+guardBits)) then
localPreHalf <= '1';
end if;
if (slvCnt + phase_shift) = avgLen((7+guardBits) downto guardBits)
and localPhi = '1' then
localPreEnd <= '1';
end if;
if localHalf = '1' then
localPhi <= '1';
end if;
if localEnd = '1' then
-- Add fractional part to clock counter to have higher precision
newFrac := ("0" & fracCnt) + ("0" & (not avgLen(guardBits-1 downto 0)));
fracCnt <= newFrac(fracCnt'range);
localPhi <= '0';
locCnt <= (others => '0');
slvCnt <= c64Cnt + ("0000000" & newFrac(newFrac'high));
end if;
end if;
end process;
end architecture;
| lgpl-2.1 | a3c9b93e2c572ab695e2efe7cb49c2d8 | 0.617382 | 3.297265 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-xilinx-ml50x/leon3mp.vhd | 1 | 46,866 | -----------------------------------------------------------------------------
-- LEON Demonstration design
-- Copyright (C) 2004 - 2015 Cobham Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.i2c.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.l2cache.all;
use gaisler.subsys.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
use work.ml50x.all;
use work.pcie.all;
-- pragma translate_off
library unisim;
use unisim.ODDR;
use unisim.IBUFDS;
-- pragma translate_on
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
transtech : integer := CFG_TRANSTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
sys_rst_in : in std_ulogic;
clk_100 : in std_ulogic; -- 100 MHz main clock
clk_200_p : in std_ulogic; -- 200 MHz
clk_200_n : in std_ulogic; -- 200 MHz
clk_33 : in std_ulogic; -- 33 MHz
sram_flash_addr : out std_logic_vector(23 downto 0);
sram_flash_data : inout std_logic_vector(31 downto 0);
sram_cen : out std_logic;
sram_bw : out std_logic_vector (0 to 3);
sram_oen : out std_ulogic;
sram_flash_we_n : out std_ulogic;
flash_ce : out std_logic;
flash_oen : out std_logic;
flash_adv_n : out std_logic;
sram_clk : out std_ulogic;
sram_clk_fb : in std_ulogic;
sram_mode : out std_ulogic;
sram_adv_ld_n : out std_ulogic;
--pragma translate_off
iosn : out std_ulogic;
--pragma translate_on
ddr_clk : out std_logic_vector(1 downto 0);
ddr_clkb : out std_logic_vector(1 downto 0);
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_odt : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (7 downto 0); -- ddr dm
ddr_dqsp : inout std_logic_vector (7 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (7 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+CFG_DDR2SP downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (63 downto 0); -- ddr data
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
txd2 : out std_ulogic; -- UART2 tx data
rxd2 : in std_ulogic; -- UART2 rx data
gpio : inout std_logic_vector(12 downto 0); -- I/O port
led : out std_logic_vector(12 downto 0);
bus_error : out std_logic_vector(1 downto 0);
phy_gtx_clk : out std_logic;
phy_mii_data : inout std_logic; -- ethernet PHY interface
phy_tx_clk : in std_ulogic;
phy_rx_clk : in std_ulogic;
phy_rx_data : in std_logic_vector(7 downto 0);
phy_dv : in std_ulogic;
phy_rx_er : in std_ulogic;
phy_col : in std_ulogic;
phy_crs : in std_ulogic;
phy_tx_data : out std_logic_vector(7 downto 0);
phy_tx_en : out std_ulogic;
phy_tx_er : out std_ulogic;
phy_mii_clk : out std_ulogic;
phy_rst_n : out std_ulogic;
phy_int : in std_ulogic;
sgmii_rx_n : in std_ulogic;
sgmii_rx_p : in std_ulogic;
sgmii_tx_n : out std_ulogic;
sgmii_tx_p : out std_ulogic;
sgmiiclk_qo_n : in std_ulogic;
sgmiiclk_qo_p : in std_ulogic;
ps2_keyb_clk : inout std_logic;
ps2_keyb_data : inout std_logic;
ps2_mouse_clk : inout std_logic;
ps2_mouse_data : inout std_logic;
usb_csn : out std_logic;
usb_rstn : out std_logic;
iic_scl_main : inout std_ulogic;
iic_sda_main : inout std_ulogic;
iic_scl_video : inout std_logic;
iic_sda_video : inout std_logic;
tft_lcd_data : out std_logic_vector(11 downto 0);
tft_lcd_clk_p : out std_ulogic;
tft_lcd_clk_n : out std_ulogic;
tft_lcd_hsync : out std_ulogic;
tft_lcd_vsync : out std_ulogic;
tft_lcd_de : out std_ulogic;
tft_lcd_reset_b : out std_ulogic;
sysace_mpa : out std_logic_vector(6 downto 0);
sysace_mpce : out std_ulogic;
sysace_mpirq : in std_ulogic;
sysace_mpoe : out std_ulogic;
sysace_mpwe : out std_ulogic;
sysace_d : inout std_logic_vector(15 downto 0);
pci_exp_txp : out std_logic_vector(CFG_NO_OF_LANES-1 downto 0);
pci_exp_txn : out std_logic_vector(CFG_NO_OF_LANES-1 downto 0);
pci_exp_rxp : in std_logic_vector(CFG_NO_OF_LANES-1 downto 0);
pci_exp_rxn : in std_logic_vector(CFG_NO_OF_LANES-1 downto 0);
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_reset_n : in std_logic
);
end;
architecture rtl of leon3mp is
component ODDR
generic
( DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
-- INIT : bit := '0';
SRTYPE : string := "SYNC");
port
(
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
component svga2ch7301c
generic (
tech : integer := 0;
idf : integer := 0;
dynamic : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
clksel : in std_logic_vector(1 downto 0);
vgao : in apbvga_out_type;
vgaclk_fb : in std_ulogic;
clk25_fb : in std_ulogic;
clk40_fb : in std_ulogic;
clk65_fb : in std_ulogic;
vgaclk : out std_ulogic;
clk25 : out std_ulogic;
clk40 : out std_ulogic;
clk65 : out std_ulogic;
dclk_p : out std_ulogic;
dclk_n : out std_ulogic;
locked : out std_ulogic;
data : out std_logic_vector(11 downto 0);
hsync : out std_ulogic;
vsync : out std_ulogic;
de : out std_ulogic
);
end component;
component IBUFDS
generic ( CAPACITANCE : string := "DONT_CARE";
DIFF_TERM : boolean := FALSE; IBUF_DELAY_VALUE : string := "0";
IFD_DELAY_VALUE : string := "AUTO"; IOSTANDARD : string := "DEFAULT");
port ( O : out std_ulogic; I : in std_ulogic; IB : in std_ulogic);
end component;
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := NCPU+CFG_AHB_UART
+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE+CFG_PCIEXP;
signal ddr_clk_fb : std_logic;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdctrl_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal ddr2_ahbsi : ahb_slv_in_type;
signal ddr2_ahbso : ahb_slv_out_type;
signal clkm, rstn, rstraw, srclkl : std_ulogic;
signal clk_200 : std_ulogic;
signal clk25, clk40, clk65 : std_ulogic;
signal sgmii_refclk, sgmii_rst : std_ulogic;
signal cgi, cgi2 : clkgen_in_type;
signal cgo, cgo2 : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal sysi : leon_dsu_stat_base_in_type;
signal syso : leon_dsu_stat_base_out_type;
signal perf : l3stat_in_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal mdio_reset, mdio_o, mdio_oe, mdio_i, mdc, mdint : std_logic;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal clklock, lock, lclk, clkml, rst, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal ddrclk, ddrrst : std_ulogic;
signal egtx_clk_fb : std_ulogic;
signal egtx_clk, legtx_clk, l2egtx_clk : std_ulogic;
signal kbdi : ps2_in_type;
signal kbdo : ps2_out_type;
signal moui : ps2_in_type;
signal mouo : ps2_out_type;
signal vgao : apbvga_out_type;
signal lcd_datal : std_logic_vector(11 downto 0);
signal lcd_hsyncl, lcd_vsyncl, lcd_del, lcd_reset_bl : std_ulogic;
signal clk_sel : std_logic_vector(1 downto 0);
signal vgalock : std_ulogic;
signal clkvga, clkvga_p, clkvga_n : std_ulogic;
signal i2ci, dvi_i2ci : i2c_in_type;
signal i2co, dvi_i2co : i2c_out_type;
constant BOARD_FREQ_200 : integer := 200000; -- input frequency in KHz
constant BOARD_FREQ : integer := 100000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant I2C_FILTER : integer := (CPU_FREQ*5+50000)/100000+1;
constant IOAEN : integer := CFG_DDR2SP + CFG_GRACECTRL;
signal stati : ahbstat_in_type;
signal ssrclkfb : std_ulogic;
-- Used for connecting input/output signals to the DDR3 controller
signal migi : mig_app_in_type;
signal migo : mig_app_out_type;
signal phy_init_done : std_ulogic;
signal clk0_tb, rst0_tb, rst0_tbn : std_ulogic;
signal sysmoni : grsysmon_in_type;
signal sysmono : grsysmon_out_type;
signal clkace : std_ulogic;
signal acei : gracectrl_in_type;
signal aceo : gracectrl_out_type;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of clkml : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute syn_keep of clkm : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute syn_keep of egtx_clk : signal is true;
attribute syn_preserve of egtx_clk : signal is true;
attribute syn_keep of clkvga : signal is true;
attribute syn_preserve of clkvga : signal is true;
attribute syn_keep of clk25 : signal is true;
attribute syn_preserve of clk25 : signal is true;
attribute syn_keep of clk40 : signal is true;
attribute syn_preserve of clk40 : signal is true;
attribute syn_keep of clk65 : signal is true;
attribute syn_preserve of clk65 : signal is true;
attribute syn_keep of clk_200 : signal is true;
attribute syn_preserve of clk_200 : signal is true;
attribute syn_preserve of phy_init_done : signal is true;
attribute keep : boolean;
attribute keep of lock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
attribute keep of egtx_clk : signal is true;
attribute keep of clkvga : signal is true;
attribute keep of clk25 : signal is true;
attribute keep of clk40 : signal is true;
attribute keep of clk65 : signal is true;
attribute keep of clk_200 : signal is true;
attribute keep of phy_init_done : signal is true;
attribute syn_noprune : boolean;
attribute syn_noprune of clk_33_pad : label is true;
begin
usb_csn <= '1';
usb_rstn <= rstn;
rst0_tbn <= not rst0_tb;
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; cgi.pllref <= ssrclkfb;
ssrref_pad : clkpad generic map (tech => padtech)
port map (sram_clk_fb, ssrclkfb);
clk_pad : clkpad generic map (tech => padtech, arch => 2)
port map (clk_100, lclk);
clk200_pad : clkpad_ds generic map (tech => padtech, level => lvds, voltage => x25v)
port map (clk_200_p, clk_200_n, clk_200);
srclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (sram_clk, srclkl);
clk_33_pad : clkpad generic map (tech => padtech)
port map (clk_33, clkace);
clkgen0 : clkgen -- system clock generator
generic map (CFG_FABTECH, CFG_CLKMUL, CFG_CLKDIV, 1, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd(0), clkm, open, open, srclkl, open, cgi, cgo);
gclk : if CFG_GRETH1G /= 0 generate
clkgen1 : clkgen -- Ethernet 1G PHY clock generator
generic map (CFG_FABTECH, 5, 4, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd(0), egtx_clk, open, open, open, open, cgi2, cgo2);
cgi2.pllctrl <= "00"; cgi2.pllrst <= rstraw; --cgi2.pllref <= egtx_clk_fb;
x0 : ODDR port map ( Q => phy_gtx_clk, C => egtx_clk, CE => vcc(0),
D1 => gnd(0), D2 => vcc(0), R => gnd(0), S => gnd(0));
end generate;
nogclk : if CFG_GRETH1G = 0 generate
cgo2.clklock <= '1'; phy_gtx_clk <= '0';
end generate;
resetn_pad : inpad generic map (tech => padtech) port map (sys_rst_in, rst);
rst0 : rstgen -- reset generator
port map (rst, clkm, clklock, rstn, rstraw);
clklock <= lock and cgo.clklock and cgo2.clklock and vgalock;
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, devid => CFG_BOARD_SELECTION,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON processor and DSU -----------------------------------------
----------------------------------------------------------------------
leon : leon_dsu_stat_base
generic map (
leon => CFG_LEON, ncpu => ncpu, fabtech => fabtech, memtech => memtech,
nwindows => CFG_NWIN, dsu => CFG_DSU, fpu => CFG_FPU, v8 => CFG_V8, cp => 0,
mac => CFG_MAC, pclow => pclow, notag => 0, nwp => CFG_NWP, icen => CFG_ICEN,
irepl => CFG_IREPL, isets => CFG_ISETS, ilinesize => CFG_ILINE,
isetsize => CFG_ISETSZ, isetlock => CFG_ILOCK, dcen => CFG_DCEN,
drepl => CFG_DREPL, dsets => CFG_DSETS, dlinesize => CFG_DLINE,
dsetsize => CFG_DSETSZ, dsetlock => CFG_DLOCK, dsnoop => CFG_DSNOOP,
ilram => CFG_ILRAMEN, ilramsize => CFG_ILRAMSZ, ilramstart => CFG_ILRAMADDR,
dlram => CFG_DLRAMEN, dlramsize => CFG_DLRAMSZ, dlramstart => CFG_DLRAMADDR,
mmuen => CFG_MMUEN, itlbnum => CFG_ITLBNUM, dtlbnum => CFG_DTLBNUM,
tlb_type => CFG_TLB_TYPE, tlb_rep => CFG_TLB_REP, lddel => CFG_LDDEL,
disas => disas, tbuf => CFG_ITBSZ, pwd => CFG_PWD, svt => CFG_SVT,
rstaddr => CFG_RSTADDR, smp => ncpu-1, cached => CFG_DFIXED,
wbmask => CFG_BWMASK, busw => CFG_CACHEBW, netlist => CFG_LEON_NETLIST,
ft => CFG_LEONFT_EN, npasi => CFG_NP_ASI, pwrpsr => CFG_WRPSR,
rex => CFG_REX, altwin => CFG_ALTWIN, grfpush => CFG_GRFPUSH,
dsu_hindex => 2, dsu_haddr => 16#D00#, dsu_hmask => 16#F00#, atbsz => CFG_ATBSZ,
stat => CFG_STAT_ENABLE, stat_pindex => 13, stat_paddr => 16#100#,
stat_pmask => 16#ffc#, stat_ncnt => CFG_STAT_CNT, stat_nmax => CFG_STAT_NMAX)
port map (
rstn => rstn, ahbclk => clkm, cpuclk => clkm, hclken => vcc(0),
leon_ahbmi => ahbmi, leon_ahbmo => ahbmo(CFG_NCPU-1 downto 0),
leon_ahbsi => ahbsi, leon_ahbso => ahbso,
irqi => irqi, irqo => irqo,
stat_apbi => apbi, stat_apbo => apbo(14), stat_ahbsi => ahbsi,
stati => perf,
dsu_ahbsi => ahbsi, dsu_ahbso => ahbso(2),
dsu_tahbmi => ahbmi, dsu_tahbsi => ahbsi,
sysi => sysi, syso => syso);
sysi.dsu_enable <= '1';
bus_error(0) <= syso.proc_errorn;
bus_error(1) <= rstn;
led(4) <= syso.dsu_active;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(NCPU));
-- dsurx_pad : inpad generic map (tech => padtech) port map (rxd1, dui.rxd);
-- dsutx_pad : outpad generic map (tech => padtech) port map (txd1, duo.txd);
dui.rxd <= rxd1 when gpioo.val(0) = '1' else '1';
end generate;
txd1 <= duo.txd when gpioo.val(0) = '1' else u1o.txd;
txd2 <= '0'; -- Second UART is unused
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
memi.brdyn <= '1'; memi.bexcn <= '1';
mctrl0 : if CFG_MCTRL_LEON2 = 1 generate
mctrl0 : mctrl generic map (hindex => 3, pindex => 0,
ramaddr => 16#400# + (CFG_DDR2SP+CFG_MIG_DDR2)*16#800#, rammask => 16#FE0#,
paddr => 0, srbanks => 1, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN,
invclk => CFG_MCTRL_INVCLK, sepbus => CFG_MCTRL_SEPBUS)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(3), apbi, apbo(0), wpo, open);
end generate;
flash_adv_n_pad : outpad generic map (tech => padtech)
port map (flash_adv_n, gnd(0));
sram_adv_ld_n_pad : outpad generic map (tech => padtech)
port map (sram_adv_ld_n, gnd(0));
sram_mode_pad : outpad generic map (tech => padtech)
port map (sram_mode, gnd(0));
addr_pad : outpadv generic map (width => 24, tech => padtech)
port map (sram_flash_addr, memo.address(24 downto 1));
rams_pad : outpad generic map ( tech => padtech)
port map (sram_cen, memo.ramsn(0));
roms_pad : outpad generic map (tech => padtech)
port map (flash_ce, memo.romsn(0));
ramoen_pad : outpad generic map (tech => padtech)
port map (sram_oen, memo.ramoen(0));
flash_oen_pad : outpad generic map (tech => padtech)
port map (flash_oen, memo.oen);
--pragma translate_off
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
--pragma translate_on
rwen_pad : outpadv generic map (width => 2, tech => padtech)
port map (sram_bw(0 to 1), memo.wrn(3 downto 2));
rwen_pad2 : outpadv generic map (width => 2, tech => padtech)
port map (sram_bw(2 to 3), memo.wrn(1 downto 0));
wri_pad : outpad generic map (tech => padtech)
port map (sram_flash_we_n, memo.writen);
data_pads : iopadvv generic map (tech => padtech, width => 16)
port map (sram_flash_data(15 downto 0), memo.data(31 downto 16),
memo.vbdrive(31 downto 16), memi.data(31 downto 16));
data_pads2 : iopadvv generic map (tech => padtech, width => 16)
port map (sram_flash_data(31 downto 16), memo.data(15 downto 0),
memo.vbdrive(15 downto 0), memi.data(15 downto 0));
-----------------------------------------------------------------------------
-- L2 cache, optionally covering DDR2 SDRAM memory controller
-----------------------------------------------------------------------------
l2cen : if CFG_L2_EN /= 0 generate
l2cblock : block
signal mem_ahbsi : ahb_slv_in_type;
signal mem_ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal mem_ahbmi : ahb_mst_in_type;
signal mem_ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal l2c_stato : std_logic_vector(10 downto 0);
begin
l2c0 : l2c generic map (
hslvidx => 0, hmstidx => 0, cen => CFG_L2_PEN,
haddr => 16#400#, hmask => 16#c00#, ioaddr => 16#FF0#,
cached => CFG_L2_MAP, repl => CFG_L2_RAN, ways => CFG_L2_WAYS,
linesize => CFG_L2_LSZ, waysize => CFG_L2_SIZE,
memtech => memtech, bbuswidth => AHBDW,
bioaddr => 16#FFE#, biomask => 16#fff#,
sbus => 0, mbus => 1, arch => CFG_L2_SHARE,
ft => CFG_L2_EDAC)
port map(rst => rstn, clk => clkm, ahbsi => ahbsi, ahbso => ahbso(0),
ahbmi => mem_ahbmi, ahbmo => mem_ahbmo(0), ahbsov => mem_ahbso,
sto => l2c_stato);
memahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => 16#FFE#,
ioen => 1, nahbm => 1, nahbs => 2)
port map (rstn, clkm, mem_ahbmi, mem_ahbmo, mem_ahbsi, mem_ahbso);
mem_ahbso(0) <= ddr2_ahbso;
ddr2_ahbsi <= mem_ahbsi;
perf.event(15 downto 7) <= (others => '0');
perf.esource(15 downto 7) <= (others => (others => '0'));
perf.event(6) <= l2c_stato(10); -- Data uncorrectable error
perf.event(5) <= l2c_stato(9); -- Data correctable error
perf.event(4) <= l2c_stato(8); -- Tag uncorrectable error
perf.event(3) <= l2c_stato(7); -- Tag correctable error
perf.event(2) <= l2c_stato(2); -- Bus access
perf.event(1) <= l2c_stato(1); -- Miss
perf.event(0) <= l2c_stato(0); -- Hit
perf.esource(6 downto 3) <= (others => (others => '0'));
perf.esource(2 downto 0) <= (others => l2c_stato(6 downto 3));
perf.req <= (others => '0');
perf.sel <= (others => '0');
perf.latcnt <= '0';
--perf.timer <= dbgi(0).timer(31 downto 0);
end block l2cblock;
end generate l2cen;
nol2c : if CFG_L2_EN = 0 generate
ahbso(0) <= ddr2_ahbso;
ddr2_ahbsi <= ahbsi;
perf <= l3stat_in_none;
end generate;
-----------------------------------------------------------------------------
-- DDR2 SDRAM memory controllers
-----------------------------------------------------------------------------
migsp0 : if (CFG_MIG_DDR2 = 1) generate
ahb2mig0 : entity work.ahb2mig_ml50x
generic map ( hindex => 0, haddr => 16#400#, hmask => MIGHMASK,
MHz => 400, Mbyte => 512, nosync => 0) --boolean'pos(CFG_MIG_CLK4=12)) --CFG_CLKDIV/12)
port map (
rst_ahb => rstn, rst_ddr => rst0_tbn, clk_ahb => clkm, clk_ddr => clk0_tb,
ahbsi => ddr2_ahbsi, ahbso => ddr2_ahbso, migi => migi, migo => migo);
migv5 : mig_36_1
generic map (
CKE_WIDTH => CKE_WIDTH, CS_NUM => CS_NUM, CS_WIDTH => CS_WIDTH, CS_BITS => CS_BITS,
COL_WIDTH => COL_WIDTH, ROW_WIDTH => ROW_WIDTH,
NOCLK200 => true, SIM_ONLY => 1)
port map(
ddr2_dq => ddr_dq(DQ_WIDTH-1 downto 0),
ddr2_a => ddr_ad(ROW_WIDTH-1 downto 0),
ddr2_ba => ddr_ba(1 downto 0), ddr2_ras_n => ddr_rasb,
ddr2_cas_n => ddr_casb, ddr2_we_n => ddr_web,
ddr2_cs_n => ddr_csb(CS_NUM-1 downto 0), ddr2_odt => ddr_odt(0 downto 0),
ddr2_cke => ddr_cke(CKE_WIDTH-1 downto 0),
ddr2_dm => ddr_dm(DM_WIDTH-1 downto 0),
sys_clk => clk_200, idly_clk_200 => clk_200, sys_rst_n => rstraw,
phy_init_done => phy_init_done,
rst0_tb => rst0_tb, clk0_tb => clk0_tb,
app_wdf_afull => migo.app_wdf_afull,
app_af_afull => migo.app_af_afull,
rd_data_valid => migo.app_rd_data_valid,
app_wdf_wren => migi.app_wdf_wren,
app_af_wren => migi.app_en, app_af_addr => migi.app_addr,
app_af_cmd => migi.app_cmd,
rd_data_fifo_out => migo.app_rd_data, app_wdf_data => migi.app_wdf_data,
app_wdf_mask_data => migi.app_wdf_mask,
ddr2_dqs => ddr_dqsp(DQS_WIDTH-1 downto 0),
ddr2_dqs_n => ddr_dqsn(DQS_WIDTH-1 downto 0),
ddr2_ck => ddr_clk((CLK_WIDTH-1) downto 0),
ddr2_ck_n => ddr_clkb((CLK_WIDTH-1) downto 0)
);
lock <= phy_init_done;
led(5) <= phy_init_done;
ddr_ad(13) <= '0';
ddr_odt(1) <= '0';
ddr_csb(1) <= '0';
end generate;
ddrsp0 : if (CFG_DDR2SP /= 0) and (CFG_MIG_DDR2 = 0) generate
ddrc0 : ddr2spa generic map ( fabtech => fabtech, memtech => memtech,
hindex => 0, haddr => 16#400#, hmask => 16#C00#, ioaddr => 1,
pwron => CFG_DDR2SP_INIT, MHz => BOARD_FREQ_200/1000, TRFC => CFG_DDR2SP_TRFC,
clkmul => CFG_DDR2SP_FREQ/10, clkdiv => 20, ahbfreq => CPU_FREQ/1000,
col => CFG_DDR2SP_COL, Mbyte => CFG_DDR2SP_SIZE, ddrbits => 64,
ddelayb0 => CFG_DDR2SP_DELAY0, ddelayb1 => CFG_DDR2SP_DELAY1,
ddelayb2 => CFG_DDR2SP_DELAY2, ddelayb3 => CFG_DDR2SP_DELAY3,
ddelayb4 => CFG_DDR2SP_DELAY4, ddelayb5 => CFG_DDR2SP_DELAY5,
ddelayb6 => CFG_DDR2SP_DELAY6, ddelayb7 => CFG_DDR2SP_DELAY7,
numidelctrl => 1, norefclk => 0, odten => 3, nclk => 2,
eightbanks => 1)
port map ( rst, rstn, clk_200, clkm, clk_200, lock, clkml, clkml, ddr2_ahbsi, ddr2_ahbso,
ddr_clk, ddr_clkb, ddr_clk_fb, ddr_clk_fb, ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqsp, ddr_dqsn, ddr_ad, ddr_ba, ddr_dq, ddr_odt);
led(5) <= '0';
end generate;
noddr : if (CFG_DDR2SP = 0) and (CFG_MIG_DDR2 = 0) generate lock <= '1'; led(5) <= '0'; end generate;
----------------------------------------------------------------------
--- System ACE I/F Controller ---------------------------------------
----------------------------------------------------------------------
grace: if CFG_GRACECTRL = 1 generate
grace0 : gracectrl generic map (hindex => 4, hirq => 3,
haddr => 16#002#, hmask => 16#fff#, split => CFG_SPLIT)
port map (rstn, clkm, clkace, ahbsi, ahbso(4), acei, aceo);
end generate;
nograce: if CFG_GRACECTRL /= 1 generate
aceo <= gracectrl_none;
end generate;
sysace_mpa_pads : outpadv generic map (width => 7, tech => padtech)
port map (sysace_mpa, aceo.addr);
sysace_mpce_pad : outpad generic map (tech => padtech)
port map (sysace_mpce, aceo.cen);
sysace_d_pads : iopadv generic map (tech => padtech, width => 16)
port map (sysace_d, aceo.do, aceo.doen, acei.di);
sysace_mpoe_pad : outpad generic map (tech => padtech)
port map (sysace_mpoe, aceo.oen);
sysace_mpwe_pad : outpad generic map (tech => padtech)
port map (sysace_mpwe, aceo.wen);
sysace_mpirq_pad : inpad generic map (tech => padtech)
port map (sysace_mpirq, acei.irq);
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0'; u1i.ctsn <= '0';
u1i.rxd <= rxd1 when gpioo.val(0) = '0' else '1';
end generate;
led(0) <= gpioo.val(0); led(1) <= not rxd1;
led(2) <= not duo.txd when gpioo.val(0) = '1' else not u1o.txd;
led (12 downto 6) <= (others => '0');
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
gpti <= gpti_dhalt_drive(syso.dsu_tstop);
led(3) <= gpto.wdog;
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
kbd : if CFG_KBD_ENABLE /= 0 generate
ps21 : apbps2 generic map(pindex => 4, paddr => 4, pirq => 4)
port map(rstn, clkm, apbi, apbo(4), moui, mouo);
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
end generate;
nokbd : if CFG_KBD_ENABLE = 0 generate apbo(5) <= apb_none; kbdo <= ps2o_none; end generate;
kbdclk_pad : iopad generic map (tech => padtech)
port map (ps2_keyb_clk,kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
kbdata_pad : iopad generic map (tech => padtech)
port map (ps2_keyb_data, kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
mouclk_pad : iopad generic map (tech => padtech)
port map (ps2_mouse_clk, mouo.ps2_clk_o, mouo.ps2_clk_oe, moui.ps2_clk_i);
mouata_pad : iopad generic map (tech => padtech)
port map (ps2_mouse_data, mouo.ps2_data_o, mouo.ps2_data_oe, moui.ps2_data_i);
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, clkvga, apbi, apbo(6), vgao);
clk_sel <= "00";
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(
memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
clk0 => 40000, clk1 => 40000, clk2 => 25000, clk3 => 15385, burstlen => 6,
ahbaccsz => CFG_AHBDW)
port map(rstn, clkm, clkvga, apbi, apbo(6), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), clk_sel);
end generate;
vgadvi : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) /= 0 generate
dvi0 : svga2ch7301c generic map (tech => fabtech, idf => 2)
port map (lclk, rstraw, clk_sel, vgao, clkvga, clk25, clk40, clk65,
clkvga, clk25, clk40, clk65, clkvga_p, clkvga_n,
vgalock, lcd_datal, lcd_hsyncl, lcd_vsyncl, lcd_del);
i2cdvi : i2cmst
generic map (pindex => 9, paddr => 9, pmask => 16#FFF#,
pirq => 6, filter => I2C_FILTER)
port map (rstn, clkm, apbi, apbo(9), dvi_i2ci, dvi_i2co);
end generate;
novga : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) = 0 generate
apbo(6) <= apb_none; vgalock <= '1';
lcd_datal <= (others => '0'); clkvga_p <= '0'; clkvga_n <= '0';
lcd_hsyncl <= '0'; lcd_vsyncl <= '0'; lcd_del <= '0';
dvi_i2co.scloen <= '1'; dvi_i2co.sdaoen <= '1';
end generate;
tft_lcd_data_pad : outpadv generic map (width => 12, tech => padtech)
port map (tft_lcd_data, lcd_datal);
tft_lcd_clkp_pad : outpad generic map (tech => padtech)
port map (tft_lcd_clk_p, clkvga_p);
tft_lcd_clkn_pad : outpad generic map (tech => padtech)
port map (tft_lcd_clk_n, clkvga_n);
tft_lcd_hsync_pad : outpad generic map (tech => padtech)
port map (tft_lcd_hsync, lcd_hsyncl);
tft_lcd_vsync_pad : outpad generic map (tech => padtech)
port map (tft_lcd_vsync, lcd_vsyncl);
tft_lcd_de_pad : outpad generic map (tech => padtech)
port map (tft_lcd_de, lcd_del);
tft_lcd_reset_pad : outpad generic map (tech => padtech)
port map (tft_lcd_reset_b, rstn);
dvi_i2c_scl_pad : iopad generic map (tech => padtech)
port map (iic_scl_video, dvi_i2co.scl, dvi_i2co.scloen, dvi_i2ci.scl);
dvi_i2c_sda_pad : iopad generic map (tech => padtech)
port map (iic_sda_video, dvi_i2co.sda, dvi_i2co.sdaoen, dvi_i2ci.sda);
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 8, paddr => 8, imask => 16#00F0#, nbits => 13)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(8),
gpioi => gpioi, gpioo => gpioo);
gpio_pads : iopadvv generic map (tech => padtech, width => 13)
port map (gpio, gpioo.dout(12 downto 0), gpioo.oen(12 downto 0),
gpioi.din(12 downto 0));
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
stati <= ahbstat_in_none;
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 1,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master
i2c0 : i2cmst
generic map (pindex => 12, paddr => 12, pmask => 16#FFF#,
pirq => 11, filter => I2C_FILTER)
port map (rstn, clkm, apbi, apbo(12), i2ci, i2co);
i2c_scl_pad : iopad generic map (tech => padtech)
port map (iic_scl_main, i2co.scl, i2co.scloen, i2ci.scl);
i2c_sda_pad : iopad generic map (tech => padtech)
port map (iic_sda_main, i2co.sda, i2co.sdaoen, i2ci.sda);
end generate i2cm;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth1 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
gmii_eth: if CFG_GRETH_SGMII = 0 generate
e1 : grethm
generic map(
hindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 11, paddr => 11, pirq => 7, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 7,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G,
enable_mdint => 1
)
port map(
rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
apbi => apbi, apbo => apbo(11), ethi => ethi, etho => etho
);
emdio_pad : iopad generic map (tech => padtech)
port map (phy_mii_data, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (phy_tx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (phy_rx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 8)
port map (phy_rx_data, ethi.rxd(7 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (phy_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (phy_rx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (phy_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (phy_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 8)
port map (phy_tx_data, etho.txd(7 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( phy_tx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (phy_tx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (phy_mii_clk, etho.mdc);
erst_pad : outpad generic map (tech => padtech)
port map (phy_rst_n, rstn);
emdintn_pad : inpad generic map (tech => padtech)
port map (phy_int, ethi.mdint);
ethi.gtx_clk <= egtx_clk;
end generate;
sgmii_eth: if CFG_GRETH_SGMII /= 0 generate
sgmii_rst <= not rst;
refclk_bufds : IBUFDS
port map (
I => sgmiiclk_qo_p,
IB => sgmiiclk_qo_n,
O => sgmii_refclk
);
e1 : greths
generic map(
hindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 11, paddr => 11, pirq => 7,
fabtech => fabtech,
memtech => memtech,
transtech => transtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 7,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G,
enable_mdint => 1
)
port map(
rst => rstn,
clk => clkm,
ahbmi => ahbmi,
ahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
apbi => apbi,
apbo => apbo(11),
-- High-speed Serial Interface
clk_125 => sgmii_refclk,
rst_125 => sgmii_rst,
eth_rx_p => sgmii_rx_p,
eth_rx_n => sgmii_rx_n,
eth_tx_p => sgmii_tx_p,
eth_tx_n => sgmii_tx_n,
-- MDIO interface
reset => mdio_reset,
mdio_o => mdio_o,
mdio_oe => mdio_oe,
mdio_i => mdio_i,
mdc => mdc,
mdint => mdint,
-- Control signals
phyrstaddr => "00000",
edcladdr => "0000",
edclsepahb => '0',
edcldisable => '0'
);
emdio_pad : iopad generic map (tech => padtech)
port map (phy_mii_data, mdio_o, mdio_oe, mdio_i);
emdc_pad : outpad generic map (tech => padtech)
port map (phy_mii_clk, mdc);
erst_pad : outpad generic map (tech => padtech)
port map (phy_rst_n, mdio_reset);
emdintn_pad : inpad generic map (tech => padtech)
port map (phy_int, mdint);
end generate;
end generate;
-----------------PCI-EXPRESS-Master-Target------------------------------------------
pcie_mt : if CFG_PCIE_TYPE = 1 generate -- master/target without fifo
EP: pcie_master_target_virtex
generic map (
fabtech => fabtech,
hmstndx => NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
hslvndx => 6,
abits => 21,
device_id => CFG_PCIEXPDID, -- PCIE device ID
vendor_id => CFG_PCIEXPVID, -- PCIE vendor ID
pcie_bar_mask => 16#FFE#,
nsync => 2, -- 1 or 2 sync regs between clocks
haddr => 16#a00#,
hmask => 16#fff#,
pindex => 10,
paddr => 10,
pmask => 16#fff#,
Master => CFG_PCIE_SIM_MAS,
lane_width => CFG_NO_OF_LANES
)
port map(
rst => rstn,
clk => clkm,
-- System Interface
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
sys_reset_n => sys_reset_n,
-- PCI Express Fabric Interface
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
ahbso => ahbso(6),
ahbsi => ahbsi,
apbi => apbi,
apbo => apbo(10),
ahbmi => ahbmi,
ahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE)
);
end generate;
pcie_mf : if CFG_PCIE_TYPE = 3 generate -- master with fifo and DMA
dma:pciedma
generic map (fabtech => fabtech, memtech => memtech, dmstndx =>(NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
dapbndx => 13, dapbaddr => 13,dapbirq => 13, blength => 12, abits => 21,
device_id => CFG_PCIEXPDID, vendor_id => CFG_PCIEXPVID, pcie_bar_mask => 16#FFE#,
slvndx => 6, apbndx => 10, apbaddr => 10, haddr => 16#A00#,hmask=> 16#FFF#,
nsync => 2,lane_width => CFG_NO_OF_LANES)
port map(
rst => rstn,
clk => clkm,
-- System Interface
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
sys_reset_n => sys_reset_n,
-- PCI Express Fabric Interface
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
dapbo => apbo(13),
dahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
apbi => apbi,
apbo => apbo(10),
ahbmi => ahbmi,
ahbsi => ahbsi,
ahbso => ahbso(6)
);
end generate;
----------------------------------------------------------------------
pcie_mf_no_dma: if CFG_PCIE_TYPE = 2 generate -- master with fifo
EP:pcie_master_fifo_virtex
generic map (fabtech => fabtech, memtech => memtech,
hslvndx => 6, abits => 21, device_id => CFG_PCIEXPDID, vendor_id => CFG_PCIEXPVID,
pcie_bar_mask => 16#FFE#, pindex => 10, paddr => 10,
haddr => 16#A00#, hmask => 16#FFF#, nsync => 2, lane_width => CFG_NO_OF_LANES)
port map(
rst => rstn,
clk => clkm,
-- System Interface
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
sys_reset_n => sys_reset_n,
-- PCI Express Fabric Interface
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
ahbso => ahbso(6),
ahbsi => ahbsi,
apbi => apbi,
apbo => apbo(10)
);
end generate;
-----------------------------------------------------------------------
--- SYSTEM MONITOR ---------------------------------------------------
-----------------------------------------------------------------------
grsmon: if CFG_GRSYSMON = 1 generate
sysm0 : grsysmon generic map (tech => fabtech, hindex => 5,
hirq => 10, caddr => 16#003#, cmask => 16#fff#,
saddr => 16#004#, smask => 16#ffe#, split => CFG_SPLIT,
extconvst => 0, wrdalign => 1, INIT_40 => X"0000",
INIT_41 => X"0000", INIT_42 => X"0800", INIT_43 => X"0000",
INIT_44 => X"0000", INIT_45 => X"0000", INIT_46 => X"0000",
INIT_47 => X"0000", INIT_48 => X"0000", INIT_49 => X"0000",
INIT_4A => X"0000", INIT_4B => X"0000", INIT_4C => X"0000",
INIT_4D => X"0000", INIT_4E => X"0000", INIT_4F => X"0000",
INIT_50 => X"0000", INIT_51 => X"0000", INIT_52 => X"0000",
INIT_53 => X"0000", INIT_54 => X"0000", INIT_55 => X"0000",
INIT_56 => X"0000", INIT_57 => X"0000",
SIM_MONITOR_FILE => "sysmon.txt")
port map (rstn, clkm, ahbsi, ahbso(5), sysmoni, sysmono);
sysmoni <= grsysmon_in_gnd;
end generate grsmon;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- AHB DEBUG --------------------------------------------------------
-----------------------------------------------------------------------
-- dma0 : ahbdma
-- generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG,
-- pindex => 13, paddr => 13, dbuf => 6)
-- port map (rstn, clkm, apbi, apbo(13), ahbmi,
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG));
-- at0 : ahbtrace
-- generic map ( hindex => 7, ioaddr => 16#200#, iomask => 16#E00#,
-- tech => memtech, irq => 0, kbytes => 8)
-- port map ( rstn, clkm, ahbmi, ahbsi, ahbso(7));
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (NCPU+CFG_AHB_UART+CFG_ETH+CFG_AHB_ETH+CFG_AHB_JTAG+CFG_PCIEXP) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => system_table(CFG_BOARD_SELECTION),
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-3.0 | 0031302e3d4a3d30e8e2b7ff0b4609f1 | 0.547049 | 3.45085 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/unisim/buffer_unisim.vhd | 1 | 2,803 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: clkbuf_xilinx
-- File: clkbuf_xilinx.vhd
-- Author: Marko Isomaki, Jiri GAisler - Gaisler Research
-- Description: Clock buffer generator for Xilinx devices
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BUFGMUX;
use unisim.BUFG;
-- pragma translate_on
entity clkbuf_xilinx is
generic(
buftype : integer range 0 to 3 := 0);
port(
i : in std_ulogic;
o : out std_ulogic
);
end entity;
architecture rtl of clkbuf_xilinx is
component BUFGMUX port (O : out std_logic; I0, I1, S : in std_logic); end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
signal gnd : std_ulogic;
signal x : std_ulogic;
attribute syn_noclockbuf : boolean;
attribute syn_noclockbuf of x : signal is true;
begin
gnd <= '0';
buf0 : if (buftype = 0) or (buftype > 2) generate
x <= i; o <= x;
end generate;
buf1 : if buftype = 1 generate
buf : bufgmux port map(S => gnd, I0 => i, I1 => gnd, O => o);
end generate;
buf2 : if (buftype = 2) generate
buf : bufg port map(I => i, O => o);
end generate;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BUFGMUX;
-- pragma translate_on
entity clkmux_xilinx is
port(
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic
);
end entity;
architecture rtl of clkmux_xilinx is
component BUFGMUX port (O : out std_logic; I0, I1, S : in std_logic); end component;
begin
buf : bufgmux port map(S => sel, I0 => i0, I1 => i1, O => o);
end architecture;
| gpl-3.0 | c7da2df8e3efdcc05a65bef71ce80bac | 0.62112 | 3.747326 | false | false | false | false |
ARC-Lab-UF/UAA | src/add_flt_stratix5_latency.vhd | 1 | 255,975 | -- megafunction wizard: %ALTFP_ADD_SUB%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altfp_add_sub
-- ============================================================
-- File Name: add_flt_stratix5_latency.vhd
-- Megafunction Name(s):
-- altfp_add_sub
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
--altfp_add_sub CBX_AUTO_BLACKBOX="ALL" DENORMAL_SUPPORT="NO" DEVICE_FAMILY="Stratix V" DIRECTION="ADD" OPTIMIZE="SPEED" PIPELINE=7 REDUCED_FUNCTIONALITY="NO" WIDTH_EXP=8 WIDTH_MAN=23 clk_en clock dataa datab result
--VERSION_BEGIN 13.1 cbx_altbarrel_shift 2013:10:23:18:05:48:SJ cbx_altfp_add_sub 2013:10:23:18:05:48:SJ cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_cycloneii 2013:10:23:18:05:48:SJ cbx_lpm_add_sub 2013:10:23:18:05:48:SJ cbx_lpm_compare 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ cbx_stratix 2013:10:23:18:05:48:SJ cbx_stratixii 2013:10:23:18:05:48:SJ VERSION_END
--altbarrel_shift CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix V" PIPELINE=1 SHIFTDIR="LEFT" WIDTH=26 WIDTHDIST=5 aclr clk_en clock data distance result
--VERSION_BEGIN 13.1 cbx_altbarrel_shift 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--synthesis_resources = reg 27
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_latency_altbarrel_shift_nud IS
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (25 DOWNTO 0);
distance : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (25 DOWNTO 0)
);
END add_flt_stratix5_latency_altbarrel_shift_nud;
ARCHITECTURE RTL OF add_flt_stratix5_latency_altbarrel_shift_nud IS
SIGNAL dir_pipe : STD_LOGIC_VECTOR(0 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL sbit_piper1d : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w681w682w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w677w678w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w702w703w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w698w699w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w724w725w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w720w721w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w746w747w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w742w743w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w768w769w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w764w765w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w673w674w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w694w695w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w716w717w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w738w739w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w760w761w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range668w681w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range668w677w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range689w702w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range689w698w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range711w724w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range711w720w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range733w746w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range733w742w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range755w768w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range755w764w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_dir_w_range665w680w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_dir_w_range687w701w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_dir_w_range708w723w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_dir_w_range730w745w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_dir_w_range752w767w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range668w673w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range689w694w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range711w716w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range733w738w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range755w760w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range668w681w682w683w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range689w702w703w704w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range711w724w725w726w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range733w746w747w748w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range755w768w769w770w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w684w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w705w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w727w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w749w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w771w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL dir_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL direction_w : STD_LOGIC;
SIGNAL pad_w : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sbit_w : STD_LOGIC_VECTOR (155 DOWNTO 0);
SIGNAL sel_w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL smux_w : STD_LOGIC_VECTOR (129 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w676w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w679w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w697w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w700w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w719w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w722w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w741w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w744w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w763w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w766w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_dir_w_range665w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_dir_w_range687w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_dir_w_range708w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_dir_w_range730w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_dir_w_range752w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sbit_w_range728w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sbit_w_range750w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sbit_w_range663w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sbit_w_range686w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sbit_w_range706w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sel_w_range668w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sel_w_range689w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sel_w_range711w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sel_w_range733w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sel_w_range755w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_smux_w_range759w : STD_LOGIC_VECTOR (25 DOWNTO 0);
BEGIN
loop0 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w681w682w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range668w681w(0) AND wire_lbarrel_shift_w679w(i);
END GENERATE loop0;
loop1 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w677w678w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range668w677w(0) AND wire_lbarrel_shift_w676w(i);
END GENERATE loop1;
loop2 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w702w703w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range689w702w(0) AND wire_lbarrel_shift_w700w(i);
END GENERATE loop2;
loop3 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w698w699w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range689w698w(0) AND wire_lbarrel_shift_w697w(i);
END GENERATE loop3;
loop4 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w724w725w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range711w724w(0) AND wire_lbarrel_shift_w722w(i);
END GENERATE loop4;
loop5 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w720w721w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range711w720w(0) AND wire_lbarrel_shift_w719w(i);
END GENERATE loop5;
loop6 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w746w747w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range733w746w(0) AND wire_lbarrel_shift_w744w(i);
END GENERATE loop6;
loop7 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w742w743w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range733w742w(0) AND wire_lbarrel_shift_w741w(i);
END GENERATE loop7;
loop8 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w768w769w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range755w768w(0) AND wire_lbarrel_shift_w766w(i);
END GENERATE loop8;
loop9 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w764w765w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range755w764w(0) AND wire_lbarrel_shift_w763w(i);
END GENERATE loop9;
loop10 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w673w674w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range668w673w(0) AND wire_lbarrel_shift_w_sbit_w_range663w(i);
END GENERATE loop10;
loop11 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w694w695w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range689w694w(0) AND wire_lbarrel_shift_w_sbit_w_range686w(i);
END GENERATE loop11;
loop12 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w716w717w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range711w716w(0) AND wire_lbarrel_shift_w_sbit_w_range706w(i);
END GENERATE loop12;
loop13 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w738w739w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range733w738w(0) AND wire_lbarrel_shift_w_sbit_w_range728w(i);
END GENERATE loop13;
loop14 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w760w761w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range755w760w(0) AND wire_lbarrel_shift_w_sbit_w_range750w(i);
END GENERATE loop14;
wire_lbarrel_shift_w_lg_w_sel_w_range668w681w(0) <= wire_lbarrel_shift_w_sel_w_range668w(0) AND wire_lbarrel_shift_w_lg_w_dir_w_range665w680w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range668w677w(0) <= wire_lbarrel_shift_w_sel_w_range668w(0) AND wire_lbarrel_shift_w_dir_w_range665w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range689w702w(0) <= wire_lbarrel_shift_w_sel_w_range689w(0) AND wire_lbarrel_shift_w_lg_w_dir_w_range687w701w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range689w698w(0) <= wire_lbarrel_shift_w_sel_w_range689w(0) AND wire_lbarrel_shift_w_dir_w_range687w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range711w724w(0) <= wire_lbarrel_shift_w_sel_w_range711w(0) AND wire_lbarrel_shift_w_lg_w_dir_w_range708w723w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range711w720w(0) <= wire_lbarrel_shift_w_sel_w_range711w(0) AND wire_lbarrel_shift_w_dir_w_range708w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range733w746w(0) <= wire_lbarrel_shift_w_sel_w_range733w(0) AND wire_lbarrel_shift_w_lg_w_dir_w_range730w745w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range733w742w(0) <= wire_lbarrel_shift_w_sel_w_range733w(0) AND wire_lbarrel_shift_w_dir_w_range730w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range755w768w(0) <= wire_lbarrel_shift_w_sel_w_range755w(0) AND wire_lbarrel_shift_w_lg_w_dir_w_range752w767w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range755w764w(0) <= wire_lbarrel_shift_w_sel_w_range755w(0) AND wire_lbarrel_shift_w_dir_w_range752w(0);
wire_lbarrel_shift_w_lg_w_dir_w_range665w680w(0) <= NOT wire_lbarrel_shift_w_dir_w_range665w(0);
wire_lbarrel_shift_w_lg_w_dir_w_range687w701w(0) <= NOT wire_lbarrel_shift_w_dir_w_range687w(0);
wire_lbarrel_shift_w_lg_w_dir_w_range708w723w(0) <= NOT wire_lbarrel_shift_w_dir_w_range708w(0);
wire_lbarrel_shift_w_lg_w_dir_w_range730w745w(0) <= NOT wire_lbarrel_shift_w_dir_w_range730w(0);
wire_lbarrel_shift_w_lg_w_dir_w_range752w767w(0) <= NOT wire_lbarrel_shift_w_dir_w_range752w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range668w673w(0) <= NOT wire_lbarrel_shift_w_sel_w_range668w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range689w694w(0) <= NOT wire_lbarrel_shift_w_sel_w_range689w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range711w716w(0) <= NOT wire_lbarrel_shift_w_sel_w_range711w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range733w738w(0) <= NOT wire_lbarrel_shift_w_sel_w_range733w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range755w760w(0) <= NOT wire_lbarrel_shift_w_sel_w_range755w(0);
loop15 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range668w681w682w683w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w681w682w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w677w678w(i);
END GENERATE loop15;
loop16 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range689w702w703w704w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w702w703w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w698w699w(i);
END GENERATE loop16;
loop17 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range711w724w725w726w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w724w725w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w720w721w(i);
END GENERATE loop17;
loop18 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range733w746w747w748w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w746w747w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w742w743w(i);
END GENERATE loop18;
loop19 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range755w768w769w770w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w768w769w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w764w765w(i);
END GENERATE loop19;
loop20 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w684w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range668w681w682w683w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w673w674w(i);
END GENERATE loop20;
loop21 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w705w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range689w702w703w704w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w694w695w(i);
END GENERATE loop21;
loop22 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w727w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range711w724w725w726w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w716w717w(i);
END GENERATE loop22;
loop23 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w749w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range733w746w747w748w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w738w739w(i);
END GENERATE loop23;
loop24 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w771w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range755w768w769w770w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w760w761w(i);
END GENERATE loop24;
dir_w <= ( dir_pipe(0) & dir_w(3 DOWNTO 0) & direction_w);
direction_w <= '0';
pad_w <= (OTHERS => '0');
result <= sbit_w(155 DOWNTO 130);
sbit_w <= ( sbit_piper1d & smux_w(103 DOWNTO 0) & data);
sel_w <= ( distance(4 DOWNTO 0));
smux_w <= ( wire_lbarrel_shift_w771w & wire_lbarrel_shift_w749w & wire_lbarrel_shift_w727w & wire_lbarrel_shift_w705w & wire_lbarrel_shift_w684w);
wire_lbarrel_shift_w676w <= ( pad_w(0) & sbit_w(25 DOWNTO 1));
wire_lbarrel_shift_w679w <= ( sbit_w(24 DOWNTO 0) & pad_w(0));
wire_lbarrel_shift_w697w <= ( pad_w(1 DOWNTO 0) & sbit_w(51 DOWNTO 28));
wire_lbarrel_shift_w700w <= ( sbit_w(49 DOWNTO 26) & pad_w(1 DOWNTO 0));
wire_lbarrel_shift_w719w <= ( pad_w(3 DOWNTO 0) & sbit_w(77 DOWNTO 56));
wire_lbarrel_shift_w722w <= ( sbit_w(73 DOWNTO 52) & pad_w(3 DOWNTO 0));
wire_lbarrel_shift_w741w <= ( pad_w(7 DOWNTO 0) & sbit_w(103 DOWNTO 86));
wire_lbarrel_shift_w744w <= ( sbit_w(95 DOWNTO 78) & pad_w(7 DOWNTO 0));
wire_lbarrel_shift_w763w <= ( pad_w(15 DOWNTO 0) & sbit_w(129 DOWNTO 120));
wire_lbarrel_shift_w766w <= ( sbit_w(113 DOWNTO 104) & pad_w(15 DOWNTO 0));
wire_lbarrel_shift_w_dir_w_range665w(0) <= dir_w(0);
wire_lbarrel_shift_w_dir_w_range687w(0) <= dir_w(1);
wire_lbarrel_shift_w_dir_w_range708w(0) <= dir_w(2);
wire_lbarrel_shift_w_dir_w_range730w(0) <= dir_w(3);
wire_lbarrel_shift_w_dir_w_range752w(0) <= dir_w(4);
wire_lbarrel_shift_w_sbit_w_range728w <= sbit_w(103 DOWNTO 78);
wire_lbarrel_shift_w_sbit_w_range750w <= sbit_w(129 DOWNTO 104);
wire_lbarrel_shift_w_sbit_w_range663w <= sbit_w(25 DOWNTO 0);
wire_lbarrel_shift_w_sbit_w_range686w <= sbit_w(51 DOWNTO 26);
wire_lbarrel_shift_w_sbit_w_range706w <= sbit_w(77 DOWNTO 52);
wire_lbarrel_shift_w_sel_w_range668w(0) <= sel_w(0);
wire_lbarrel_shift_w_sel_w_range689w(0) <= sel_w(1);
wire_lbarrel_shift_w_sel_w_range711w(0) <= sel_w(2);
wire_lbarrel_shift_w_sel_w_range733w(0) <= sel_w(3);
wire_lbarrel_shift_w_sel_w_range755w(0) <= sel_w(4);
wire_lbarrel_shift_w_smux_w_range759w <= smux_w(129 DOWNTO 104);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN dir_pipe <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN dir_pipe(0) <= ( dir_w(4));
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sbit_piper1d <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sbit_piper1d <= wire_lbarrel_shift_w_smux_w_range759w;
END IF;
END IF;
END PROCESS;
END RTL; --add_flt_stratix5_latency_altbarrel_shift_nud
--altbarrel_shift CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix V" SHIFTDIR="RIGHT" WIDTH=26 WIDTHDIST=5 data distance result
--VERSION_BEGIN 13.1 cbx_altbarrel_shift 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_latency_altbarrel_shift_cfb IS
PORT
(
data : IN STD_LOGIC_VECTOR (25 DOWNTO 0);
distance : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (25 DOWNTO 0)
);
END add_flt_stratix5_latency_altbarrel_shift_cfb;
ARCHITECTURE RTL OF add_flt_stratix5_latency_altbarrel_shift_cfb IS
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range782w795w796w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range782w791w792w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range803w816w817w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range803w812w813w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range825w838w839w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range825w834w835w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range847w860w861w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range847w856w857w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range869w882w883w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range869w878w879w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range782w787w788w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range803w808w809w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range825w830w831w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range847w852w853w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range869w874w875w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range782w795w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range782w791w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range803w816w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range803w812w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range825w838w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range825w834w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range847w860w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range847w856w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range869w882w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range869w878w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_dir_w_range779w794w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_dir_w_range801w815w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_dir_w_range822w837w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_dir_w_range844w859w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_dir_w_range866w881w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range782w787w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range803w808w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range825w830w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range847w852w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range869w874w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range782w795w796w797w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range803w816w817w818w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range825w838w839w840w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range847w860w861w862w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range869w882w883w884w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w798w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w819w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w841w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w863w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w885w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL dir_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL direction_w : STD_LOGIC;
SIGNAL pad_w : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sbit_w : STD_LOGIC_VECTOR (155 DOWNTO 0);
SIGNAL sel_w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL smux_w : STD_LOGIC_VECTOR (129 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w790w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w793w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w811w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w814w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w833w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w836w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w855w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w858w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w877w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w880w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_dir_w_range779w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_dir_w_range801w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_dir_w_range822w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_dir_w_range844w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_dir_w_range866w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sbit_w_range842w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sbit_w_range864w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sbit_w_range777w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sbit_w_range800w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sbit_w_range820w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sel_w_range782w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sel_w_range803w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sel_w_range825w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sel_w_range847w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sel_w_range869w : STD_LOGIC_VECTOR (0 DOWNTO 0);
BEGIN
loop25 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range782w795w796w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range782w795w(0) AND wire_rbarrel_shift_w793w(i);
END GENERATE loop25;
loop26 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range782w791w792w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range782w791w(0) AND wire_rbarrel_shift_w790w(i);
END GENERATE loop26;
loop27 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range803w816w817w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range803w816w(0) AND wire_rbarrel_shift_w814w(i);
END GENERATE loop27;
loop28 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range803w812w813w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range803w812w(0) AND wire_rbarrel_shift_w811w(i);
END GENERATE loop28;
loop29 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range825w838w839w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range825w838w(0) AND wire_rbarrel_shift_w836w(i);
END GENERATE loop29;
loop30 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range825w834w835w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range825w834w(0) AND wire_rbarrel_shift_w833w(i);
END GENERATE loop30;
loop31 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range847w860w861w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range847w860w(0) AND wire_rbarrel_shift_w858w(i);
END GENERATE loop31;
loop32 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range847w856w857w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range847w856w(0) AND wire_rbarrel_shift_w855w(i);
END GENERATE loop32;
loop33 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range869w882w883w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range869w882w(0) AND wire_rbarrel_shift_w880w(i);
END GENERATE loop33;
loop34 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range869w878w879w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range869w878w(0) AND wire_rbarrel_shift_w877w(i);
END GENERATE loop34;
loop35 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range782w787w788w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range782w787w(0) AND wire_rbarrel_shift_w_sbit_w_range777w(i);
END GENERATE loop35;
loop36 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range803w808w809w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range803w808w(0) AND wire_rbarrel_shift_w_sbit_w_range800w(i);
END GENERATE loop36;
loop37 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range825w830w831w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range825w830w(0) AND wire_rbarrel_shift_w_sbit_w_range820w(i);
END GENERATE loop37;
loop38 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range847w852w853w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range847w852w(0) AND wire_rbarrel_shift_w_sbit_w_range842w(i);
END GENERATE loop38;
loop39 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range869w874w875w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range869w874w(0) AND wire_rbarrel_shift_w_sbit_w_range864w(i);
END GENERATE loop39;
wire_rbarrel_shift_w_lg_w_sel_w_range782w795w(0) <= wire_rbarrel_shift_w_sel_w_range782w(0) AND wire_rbarrel_shift_w_lg_w_dir_w_range779w794w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range782w791w(0) <= wire_rbarrel_shift_w_sel_w_range782w(0) AND wire_rbarrel_shift_w_dir_w_range779w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range803w816w(0) <= wire_rbarrel_shift_w_sel_w_range803w(0) AND wire_rbarrel_shift_w_lg_w_dir_w_range801w815w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range803w812w(0) <= wire_rbarrel_shift_w_sel_w_range803w(0) AND wire_rbarrel_shift_w_dir_w_range801w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range825w838w(0) <= wire_rbarrel_shift_w_sel_w_range825w(0) AND wire_rbarrel_shift_w_lg_w_dir_w_range822w837w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range825w834w(0) <= wire_rbarrel_shift_w_sel_w_range825w(0) AND wire_rbarrel_shift_w_dir_w_range822w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range847w860w(0) <= wire_rbarrel_shift_w_sel_w_range847w(0) AND wire_rbarrel_shift_w_lg_w_dir_w_range844w859w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range847w856w(0) <= wire_rbarrel_shift_w_sel_w_range847w(0) AND wire_rbarrel_shift_w_dir_w_range844w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range869w882w(0) <= wire_rbarrel_shift_w_sel_w_range869w(0) AND wire_rbarrel_shift_w_lg_w_dir_w_range866w881w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range869w878w(0) <= wire_rbarrel_shift_w_sel_w_range869w(0) AND wire_rbarrel_shift_w_dir_w_range866w(0);
wire_rbarrel_shift_w_lg_w_dir_w_range779w794w(0) <= NOT wire_rbarrel_shift_w_dir_w_range779w(0);
wire_rbarrel_shift_w_lg_w_dir_w_range801w815w(0) <= NOT wire_rbarrel_shift_w_dir_w_range801w(0);
wire_rbarrel_shift_w_lg_w_dir_w_range822w837w(0) <= NOT wire_rbarrel_shift_w_dir_w_range822w(0);
wire_rbarrel_shift_w_lg_w_dir_w_range844w859w(0) <= NOT wire_rbarrel_shift_w_dir_w_range844w(0);
wire_rbarrel_shift_w_lg_w_dir_w_range866w881w(0) <= NOT wire_rbarrel_shift_w_dir_w_range866w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range782w787w(0) <= NOT wire_rbarrel_shift_w_sel_w_range782w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range803w808w(0) <= NOT wire_rbarrel_shift_w_sel_w_range803w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range825w830w(0) <= NOT wire_rbarrel_shift_w_sel_w_range825w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range847w852w(0) <= NOT wire_rbarrel_shift_w_sel_w_range847w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range869w874w(0) <= NOT wire_rbarrel_shift_w_sel_w_range869w(0);
loop40 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range782w795w796w797w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range782w795w796w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range782w791w792w(i);
END GENERATE loop40;
loop41 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range803w816w817w818w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range803w816w817w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range803w812w813w(i);
END GENERATE loop41;
loop42 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range825w838w839w840w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range825w838w839w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range825w834w835w(i);
END GENERATE loop42;
loop43 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range847w860w861w862w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range847w860w861w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range847w856w857w(i);
END GENERATE loop43;
loop44 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range869w882w883w884w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range869w882w883w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range869w878w879w(i);
END GENERATE loop44;
loop45 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w798w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range782w795w796w797w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range782w787w788w(i);
END GENERATE loop45;
loop46 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w819w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range803w816w817w818w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range803w808w809w(i);
END GENERATE loop46;
loop47 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w841w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range825w838w839w840w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range825w830w831w(i);
END GENERATE loop47;
loop48 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w863w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range847w860w861w862w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range847w852w853w(i);
END GENERATE loop48;
loop49 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w885w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range869w882w883w884w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range869w874w875w(i);
END GENERATE loop49;
dir_w <= ( dir_w(4 DOWNTO 0) & direction_w);
direction_w <= '1';
pad_w <= (OTHERS => '0');
result <= sbit_w(155 DOWNTO 130);
sbit_w <= ( smux_w(129 DOWNTO 0) & data);
sel_w <= ( distance(4 DOWNTO 0));
smux_w <= ( wire_rbarrel_shift_w885w & wire_rbarrel_shift_w863w & wire_rbarrel_shift_w841w & wire_rbarrel_shift_w819w & wire_rbarrel_shift_w798w);
wire_rbarrel_shift_w790w <= ( pad_w(0) & sbit_w(25 DOWNTO 1));
wire_rbarrel_shift_w793w <= ( sbit_w(24 DOWNTO 0) & pad_w(0));
wire_rbarrel_shift_w811w <= ( pad_w(1 DOWNTO 0) & sbit_w(51 DOWNTO 28));
wire_rbarrel_shift_w814w <= ( sbit_w(49 DOWNTO 26) & pad_w(1 DOWNTO 0));
wire_rbarrel_shift_w833w <= ( pad_w(3 DOWNTO 0) & sbit_w(77 DOWNTO 56));
wire_rbarrel_shift_w836w <= ( sbit_w(73 DOWNTO 52) & pad_w(3 DOWNTO 0));
wire_rbarrel_shift_w855w <= ( pad_w(7 DOWNTO 0) & sbit_w(103 DOWNTO 86));
wire_rbarrel_shift_w858w <= ( sbit_w(95 DOWNTO 78) & pad_w(7 DOWNTO 0));
wire_rbarrel_shift_w877w <= ( pad_w(15 DOWNTO 0) & sbit_w(129 DOWNTO 120));
wire_rbarrel_shift_w880w <= ( sbit_w(113 DOWNTO 104) & pad_w(15 DOWNTO 0));
wire_rbarrel_shift_w_dir_w_range779w(0) <= dir_w(0);
wire_rbarrel_shift_w_dir_w_range801w(0) <= dir_w(1);
wire_rbarrel_shift_w_dir_w_range822w(0) <= dir_w(2);
wire_rbarrel_shift_w_dir_w_range844w(0) <= dir_w(3);
wire_rbarrel_shift_w_dir_w_range866w(0) <= dir_w(4);
wire_rbarrel_shift_w_sbit_w_range842w <= sbit_w(103 DOWNTO 78);
wire_rbarrel_shift_w_sbit_w_range864w <= sbit_w(129 DOWNTO 104);
wire_rbarrel_shift_w_sbit_w_range777w <= sbit_w(25 DOWNTO 0);
wire_rbarrel_shift_w_sbit_w_range800w <= sbit_w(51 DOWNTO 26);
wire_rbarrel_shift_w_sbit_w_range820w <= sbit_w(77 DOWNTO 52);
wire_rbarrel_shift_w_sel_w_range782w(0) <= sel_w(0);
wire_rbarrel_shift_w_sel_w_range803w(0) <= sel_w(1);
wire_rbarrel_shift_w_sel_w_range825w(0) <= sel_w(2);
wire_rbarrel_shift_w_sel_w_range847w(0) <= sel_w(3);
wire_rbarrel_shift_w_sel_w_range869w(0) <= sel_w(4);
END RTL; --add_flt_stratix5_latency_altbarrel_shift_cfb
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" WIDTH=32 WIDTHAD=5 data q
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=16 WIDTHAD=4 data q
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=8 WIDTHAD=3 data q zero
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=4 WIDTHAD=2 data q zero
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=2 WIDTHAD=1 data q zero
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_latency_altpriority_encoder_3e8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END add_flt_stratix5_latency_altpriority_encoder_3e8;
ARCHITECTURE RTL OF add_flt_stratix5_latency_altpriority_encoder_3e8 IS
BEGIN
q(0) <= ( data(1));
zero <= (NOT (data(0) OR data(1)));
END RTL; --add_flt_stratix5_latency_altpriority_encoder_3e8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_latency_altpriority_encoder_6e8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END add_flt_stratix5_latency_altpriority_encoder_6e8;
ARCHITECTURE RTL OF add_flt_stratix5_latency_altpriority_encoder_6e8 IS
SIGNAL wire_altpriority_encoder13_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder13_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder14_w_lg_w_lg_zero920w921w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder14_w_lg_zero922w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder14_w_lg_zero920w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder14_w_lg_w_lg_zero922w923w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder14_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder14_zero : STD_LOGIC;
COMPONENT add_flt_stratix5_latency_altpriority_encoder_3e8
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder14_w_lg_zero920w & wire_altpriority_encoder14_w_lg_w_lg_zero922w923w);
zero <= (wire_altpriority_encoder13_zero AND wire_altpriority_encoder14_zero);
altpriority_encoder13 : add_flt_stratix5_latency_altpriority_encoder_3e8
PORT MAP (
data => data(1 DOWNTO 0),
q => wire_altpriority_encoder13_q,
zero => wire_altpriority_encoder13_zero
);
wire_altpriority_encoder14_w_lg_w_lg_zero920w921w(0) <= wire_altpriority_encoder14_w_lg_zero920w(0) AND wire_altpriority_encoder14_q(0);
wire_altpriority_encoder14_w_lg_zero922w(0) <= wire_altpriority_encoder14_zero AND wire_altpriority_encoder13_q(0);
wire_altpriority_encoder14_w_lg_zero920w(0) <= NOT wire_altpriority_encoder14_zero;
wire_altpriority_encoder14_w_lg_w_lg_zero922w923w(0) <= wire_altpriority_encoder14_w_lg_zero922w(0) OR wire_altpriority_encoder14_w_lg_w_lg_zero920w921w(0);
altpriority_encoder14 : add_flt_stratix5_latency_altpriority_encoder_3e8
PORT MAP (
data => data(3 DOWNTO 2),
q => wire_altpriority_encoder14_q,
zero => wire_altpriority_encoder14_zero
);
END RTL; --add_flt_stratix5_latency_altpriority_encoder_6e8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_latency_altpriority_encoder_be8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END add_flt_stratix5_latency_altpriority_encoder_be8;
ARCHITECTURE RTL OF add_flt_stratix5_latency_altpriority_encoder_be8 IS
SIGNAL wire_altpriority_encoder11_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder11_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder12_w_lg_w_lg_zero910w911w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder12_w_lg_zero912w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder12_w_lg_zero910w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder12_w_lg_w_lg_zero912w913w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder12_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder12_zero : STD_LOGIC;
COMPONENT add_flt_stratix5_latency_altpriority_encoder_6e8
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder12_w_lg_zero910w & wire_altpriority_encoder12_w_lg_w_lg_zero912w913w);
zero <= (wire_altpriority_encoder11_zero AND wire_altpriority_encoder12_zero);
altpriority_encoder11 : add_flt_stratix5_latency_altpriority_encoder_6e8
PORT MAP (
data => data(3 DOWNTO 0),
q => wire_altpriority_encoder11_q,
zero => wire_altpriority_encoder11_zero
);
loop50 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder12_w_lg_w_lg_zero910w911w(i) <= wire_altpriority_encoder12_w_lg_zero910w(0) AND wire_altpriority_encoder12_q(i);
END GENERATE loop50;
loop51 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder12_w_lg_zero912w(i) <= wire_altpriority_encoder12_zero AND wire_altpriority_encoder11_q(i);
END GENERATE loop51;
wire_altpriority_encoder12_w_lg_zero910w(0) <= NOT wire_altpriority_encoder12_zero;
loop52 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder12_w_lg_w_lg_zero912w913w(i) <= wire_altpriority_encoder12_w_lg_zero912w(i) OR wire_altpriority_encoder12_w_lg_w_lg_zero910w911w(i);
END GENERATE loop52;
altpriority_encoder12 : add_flt_stratix5_latency_altpriority_encoder_6e8
PORT MAP (
data => data(7 DOWNTO 4),
q => wire_altpriority_encoder12_q,
zero => wire_altpriority_encoder12_zero
);
END RTL; --add_flt_stratix5_latency_altpriority_encoder_be8
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=8 WIDTHAD=3 data q
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=4 WIDTHAD=2 data q
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=2 WIDTHAD=1 data q
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_latency_altpriority_encoder_3v7 IS
PORT
(
data : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END add_flt_stratix5_latency_altpriority_encoder_3v7;
ARCHITECTURE RTL OF add_flt_stratix5_latency_altpriority_encoder_3v7 IS
BEGIN
q(0) <= ( data(1));
END RTL; --add_flt_stratix5_latency_altpriority_encoder_3v7
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_latency_altpriority_encoder_6v7 IS
PORT
(
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END add_flt_stratix5_latency_altpriority_encoder_6v7;
ARCHITECTURE RTL OF add_flt_stratix5_latency_altpriority_encoder_6v7 IS
SIGNAL wire_altpriority_encoder17_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_w_lg_w_lg_zero945w946w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_w_lg_zero947w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_w_lg_zero945w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_w_lg_w_lg_zero947w948w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_zero : STD_LOGIC;
COMPONENT add_flt_stratix5_latency_altpriority_encoder_3v7
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT;
COMPONENT add_flt_stratix5_latency_altpriority_encoder_3e8
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder18_w_lg_zero945w & wire_altpriority_encoder18_w_lg_w_lg_zero947w948w);
altpriority_encoder17 : add_flt_stratix5_latency_altpriority_encoder_3v7
PORT MAP (
data => data(1 DOWNTO 0),
q => wire_altpriority_encoder17_q
);
wire_altpriority_encoder18_w_lg_w_lg_zero945w946w(0) <= wire_altpriority_encoder18_w_lg_zero945w(0) AND wire_altpriority_encoder18_q(0);
wire_altpriority_encoder18_w_lg_zero947w(0) <= wire_altpriority_encoder18_zero AND wire_altpriority_encoder17_q(0);
wire_altpriority_encoder18_w_lg_zero945w(0) <= NOT wire_altpriority_encoder18_zero;
wire_altpriority_encoder18_w_lg_w_lg_zero947w948w(0) <= wire_altpriority_encoder18_w_lg_zero947w(0) OR wire_altpriority_encoder18_w_lg_w_lg_zero945w946w(0);
altpriority_encoder18 : add_flt_stratix5_latency_altpriority_encoder_3e8
PORT MAP (
data => data(3 DOWNTO 2),
q => wire_altpriority_encoder18_q,
zero => wire_altpriority_encoder18_zero
);
END RTL; --add_flt_stratix5_latency_altpriority_encoder_6v7
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_latency_altpriority_encoder_bv7 IS
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
);
END add_flt_stratix5_latency_altpriority_encoder_bv7;
ARCHITECTURE RTL OF add_flt_stratix5_latency_altpriority_encoder_bv7 IS
SIGNAL wire_altpriority_encoder15_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_w_lg_w_lg_zero936w937w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_w_lg_zero938w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_w_lg_zero936w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_w_lg_w_lg_zero938w939w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_zero : STD_LOGIC;
COMPONENT add_flt_stratix5_latency_altpriority_encoder_6v7
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END COMPONENT;
COMPONENT add_flt_stratix5_latency_altpriority_encoder_6e8
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder16_w_lg_zero936w & wire_altpriority_encoder16_w_lg_w_lg_zero938w939w);
altpriority_encoder15 : add_flt_stratix5_latency_altpriority_encoder_6v7
PORT MAP (
data => data(3 DOWNTO 0),
q => wire_altpriority_encoder15_q
);
loop53 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder16_w_lg_w_lg_zero936w937w(i) <= wire_altpriority_encoder16_w_lg_zero936w(0) AND wire_altpriority_encoder16_q(i);
END GENERATE loop53;
loop54 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder16_w_lg_zero938w(i) <= wire_altpriority_encoder16_zero AND wire_altpriority_encoder15_q(i);
END GENERATE loop54;
wire_altpriority_encoder16_w_lg_zero936w(0) <= NOT wire_altpriority_encoder16_zero;
loop55 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder16_w_lg_w_lg_zero938w939w(i) <= wire_altpriority_encoder16_w_lg_zero938w(i) OR wire_altpriority_encoder16_w_lg_w_lg_zero936w937w(i);
END GENERATE loop55;
altpriority_encoder16 : add_flt_stratix5_latency_altpriority_encoder_6e8
PORT MAP (
data => data(7 DOWNTO 4),
q => wire_altpriority_encoder16_q,
zero => wire_altpriority_encoder16_zero
);
END RTL; --add_flt_stratix5_latency_altpriority_encoder_bv7
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_latency_altpriority_encoder_r08 IS
PORT
(
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END add_flt_stratix5_latency_altpriority_encoder_r08;
ARCHITECTURE RTL OF add_flt_stratix5_latency_altpriority_encoder_r08 IS
SIGNAL wire_altpriority_encoder10_w_lg_w_lg_zero901w902w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder10_w_lg_zero903w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder10_w_lg_zero901w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder10_w_lg_w_lg_zero903w904w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder10_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder10_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder9_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
COMPONENT add_flt_stratix5_latency_altpriority_encoder_be8
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT add_flt_stratix5_latency_altpriority_encoder_bv7
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder10_w_lg_zero901w & wire_altpriority_encoder10_w_lg_w_lg_zero903w904w);
loop56 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder10_w_lg_w_lg_zero901w902w(i) <= wire_altpriority_encoder10_w_lg_zero901w(0) AND wire_altpriority_encoder10_q(i);
END GENERATE loop56;
loop57 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder10_w_lg_zero903w(i) <= wire_altpriority_encoder10_zero AND wire_altpriority_encoder9_q(i);
END GENERATE loop57;
wire_altpriority_encoder10_w_lg_zero901w(0) <= NOT wire_altpriority_encoder10_zero;
loop58 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder10_w_lg_w_lg_zero903w904w(i) <= wire_altpriority_encoder10_w_lg_zero903w(i) OR wire_altpriority_encoder10_w_lg_w_lg_zero901w902w(i);
END GENERATE loop58;
altpriority_encoder10 : add_flt_stratix5_latency_altpriority_encoder_be8
PORT MAP (
data => data(15 DOWNTO 8),
q => wire_altpriority_encoder10_q,
zero => wire_altpriority_encoder10_zero
);
altpriority_encoder9 : add_flt_stratix5_latency_altpriority_encoder_bv7
PORT MAP (
data => data(7 DOWNTO 0),
q => wire_altpriority_encoder9_q
);
END RTL; --add_flt_stratix5_latency_altpriority_encoder_r08
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=16 WIDTHAD=4 data q zero
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_latency_altpriority_encoder_rf8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
zero : OUT STD_LOGIC
);
END add_flt_stratix5_latency_altpriority_encoder_rf8;
ARCHITECTURE RTL OF add_flt_stratix5_latency_altpriority_encoder_rf8 IS
SIGNAL wire_altpriority_encoder19_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder19_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder20_w_lg_w_lg_zero957w958w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder20_w_lg_zero959w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder20_w_lg_zero957w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder20_w_lg_w_lg_zero959w960w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder20_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder20_zero : STD_LOGIC;
COMPONENT add_flt_stratix5_latency_altpriority_encoder_be8
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder20_w_lg_zero957w & wire_altpriority_encoder20_w_lg_w_lg_zero959w960w);
zero <= (wire_altpriority_encoder19_zero AND wire_altpriority_encoder20_zero);
altpriority_encoder19 : add_flt_stratix5_latency_altpriority_encoder_be8
PORT MAP (
data => data(7 DOWNTO 0),
q => wire_altpriority_encoder19_q,
zero => wire_altpriority_encoder19_zero
);
loop59 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder20_w_lg_w_lg_zero957w958w(i) <= wire_altpriority_encoder20_w_lg_zero957w(0) AND wire_altpriority_encoder20_q(i);
END GENERATE loop59;
loop60 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder20_w_lg_zero959w(i) <= wire_altpriority_encoder20_zero AND wire_altpriority_encoder19_q(i);
END GENERATE loop60;
wire_altpriority_encoder20_w_lg_zero957w(0) <= NOT wire_altpriority_encoder20_zero;
loop61 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder20_w_lg_w_lg_zero959w960w(i) <= wire_altpriority_encoder20_w_lg_zero959w(i) OR wire_altpriority_encoder20_w_lg_w_lg_zero957w958w(i);
END GENERATE loop61;
altpriority_encoder20 : add_flt_stratix5_latency_altpriority_encoder_be8
PORT MAP (
data => data(15 DOWNTO 8),
q => wire_altpriority_encoder20_q,
zero => wire_altpriority_encoder20_zero
);
END RTL; --add_flt_stratix5_latency_altpriority_encoder_rf8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_latency_altpriority_encoder_qb6 IS
PORT
(
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END add_flt_stratix5_latency_altpriority_encoder_qb6;
ARCHITECTURE RTL OF add_flt_stratix5_latency_altpriority_encoder_qb6 IS
SIGNAL wire_altpriority_encoder7_q : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_w_lg_w_lg_zero892w893w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_w_lg_zero894w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_w_lg_zero892w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_w_lg_w_lg_zero894w895w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_q : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_zero : STD_LOGIC;
COMPONENT add_flt_stratix5_latency_altpriority_encoder_r08
PORT
(
data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
COMPONENT add_flt_stratix5_latency_altpriority_encoder_rf8
PORT
(
data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder8_w_lg_zero892w & wire_altpriority_encoder8_w_lg_w_lg_zero894w895w);
altpriority_encoder7 : add_flt_stratix5_latency_altpriority_encoder_r08
PORT MAP (
data => data(15 DOWNTO 0),
q => wire_altpriority_encoder7_q
);
loop62 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder8_w_lg_w_lg_zero892w893w(i) <= wire_altpriority_encoder8_w_lg_zero892w(0) AND wire_altpriority_encoder8_q(i);
END GENERATE loop62;
loop63 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder8_w_lg_zero894w(i) <= wire_altpriority_encoder8_zero AND wire_altpriority_encoder7_q(i);
END GENERATE loop63;
wire_altpriority_encoder8_w_lg_zero892w(0) <= NOT wire_altpriority_encoder8_zero;
loop64 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder8_w_lg_w_lg_zero894w895w(i) <= wire_altpriority_encoder8_w_lg_zero894w(i) OR wire_altpriority_encoder8_w_lg_w_lg_zero892w893w(i);
END GENERATE loop64;
altpriority_encoder8 : add_flt_stratix5_latency_altpriority_encoder_rf8
PORT MAP (
data => data(31 DOWNTO 16),
q => wire_altpriority_encoder8_q,
zero => wire_altpriority_encoder8_zero
);
END RTL; --add_flt_stratix5_latency_altpriority_encoder_qb6
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=32 WIDTHAD=5 data q
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=16 WIDTHAD=4 data q zero
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=8 WIDTHAD=3 data q zero
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=4 WIDTHAD=2 data q zero
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=2 WIDTHAD=1 data q zero
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_latency_altpriority_encoder_nh8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END add_flt_stratix5_latency_altpriority_encoder_nh8;
ARCHITECTURE RTL OF add_flt_stratix5_latency_altpriority_encoder_nh8 IS
SIGNAL wire_altpriority_encoder27_w_lg_w_data_range1004w1006w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_w_data_range1004w : STD_LOGIC_VECTOR (0 DOWNTO 0);
BEGIN
wire_altpriority_encoder27_w_lg_w_data_range1004w1006w(0) <= NOT wire_altpriority_encoder27_w_data_range1004w(0);
q <= ( wire_altpriority_encoder27_w_lg_w_data_range1004w1006w);
zero <= (NOT (data(0) OR data(1)));
wire_altpriority_encoder27_w_data_range1004w(0) <= data(0);
END RTL; --add_flt_stratix5_latency_altpriority_encoder_nh8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_latency_altpriority_encoder_qh8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END add_flt_stratix5_latency_altpriority_encoder_qh8;
ARCHITECTURE RTL OF add_flt_stratix5_latency_altpriority_encoder_qh8 IS
SIGNAL wire_altpriority_encoder27_w_lg_w_lg_zero996w997w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_w_lg_zero998w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_w_lg_zero996w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_w_lg_w_lg_zero998w999w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder28_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder28_zero : STD_LOGIC;
COMPONENT add_flt_stratix5_latency_altpriority_encoder_nh8
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder27_zero & wire_altpriority_encoder27_w_lg_w_lg_zero998w999w);
zero <= (wire_altpriority_encoder27_zero AND wire_altpriority_encoder28_zero);
wire_altpriority_encoder27_w_lg_w_lg_zero996w997w(0) <= wire_altpriority_encoder27_w_lg_zero996w(0) AND wire_altpriority_encoder27_q(0);
wire_altpriority_encoder27_w_lg_zero998w(0) <= wire_altpriority_encoder27_zero AND wire_altpriority_encoder28_q(0);
wire_altpriority_encoder27_w_lg_zero996w(0) <= NOT wire_altpriority_encoder27_zero;
wire_altpriority_encoder27_w_lg_w_lg_zero998w999w(0) <= wire_altpriority_encoder27_w_lg_zero998w(0) OR wire_altpriority_encoder27_w_lg_w_lg_zero996w997w(0);
altpriority_encoder27 : add_flt_stratix5_latency_altpriority_encoder_nh8
PORT MAP (
data => data(1 DOWNTO 0),
q => wire_altpriority_encoder27_q,
zero => wire_altpriority_encoder27_zero
);
altpriority_encoder28 : add_flt_stratix5_latency_altpriority_encoder_nh8
PORT MAP (
data => data(3 DOWNTO 2),
q => wire_altpriority_encoder28_q,
zero => wire_altpriority_encoder28_zero
);
END RTL; --add_flt_stratix5_latency_altpriority_encoder_qh8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_latency_altpriority_encoder_vh8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END add_flt_stratix5_latency_altpriority_encoder_vh8;
ARCHITECTURE RTL OF add_flt_stratix5_latency_altpriority_encoder_vh8 IS
SIGNAL wire_altpriority_encoder25_w_lg_w_lg_zero986w987w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder25_w_lg_zero988w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder25_w_lg_zero986w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder25_w_lg_w_lg_zero988w989w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder25_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder25_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder26_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder26_zero : STD_LOGIC;
COMPONENT add_flt_stratix5_latency_altpriority_encoder_qh8
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder25_zero & wire_altpriority_encoder25_w_lg_w_lg_zero988w989w);
zero <= (wire_altpriority_encoder25_zero AND wire_altpriority_encoder26_zero);
loop65 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder25_w_lg_w_lg_zero986w987w(i) <= wire_altpriority_encoder25_w_lg_zero986w(0) AND wire_altpriority_encoder25_q(i);
END GENERATE loop65;
loop66 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder25_w_lg_zero988w(i) <= wire_altpriority_encoder25_zero AND wire_altpriority_encoder26_q(i);
END GENERATE loop66;
wire_altpriority_encoder25_w_lg_zero986w(0) <= NOT wire_altpriority_encoder25_zero;
loop67 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder25_w_lg_w_lg_zero988w989w(i) <= wire_altpriority_encoder25_w_lg_zero988w(i) OR wire_altpriority_encoder25_w_lg_w_lg_zero986w987w(i);
END GENERATE loop67;
altpriority_encoder25 : add_flt_stratix5_latency_altpriority_encoder_qh8
PORT MAP (
data => data(3 DOWNTO 0),
q => wire_altpriority_encoder25_q,
zero => wire_altpriority_encoder25_zero
);
altpriority_encoder26 : add_flt_stratix5_latency_altpriority_encoder_qh8
PORT MAP (
data => data(7 DOWNTO 4),
q => wire_altpriority_encoder26_q,
zero => wire_altpriority_encoder26_zero
);
END RTL; --add_flt_stratix5_latency_altpriority_encoder_vh8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_latency_altpriority_encoder_fj8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
zero : OUT STD_LOGIC
);
END add_flt_stratix5_latency_altpriority_encoder_fj8;
ARCHITECTURE RTL OF add_flt_stratix5_latency_altpriority_encoder_fj8 IS
SIGNAL wire_altpriority_encoder23_w_lg_w_lg_zero976w977w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder23_w_lg_zero978w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder23_w_lg_zero976w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder23_w_lg_w_lg_zero978w979w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder23_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder23_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder24_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder24_zero : STD_LOGIC;
COMPONENT add_flt_stratix5_latency_altpriority_encoder_vh8
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder23_zero & wire_altpriority_encoder23_w_lg_w_lg_zero978w979w);
zero <= (wire_altpriority_encoder23_zero AND wire_altpriority_encoder24_zero);
loop68 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder23_w_lg_w_lg_zero976w977w(i) <= wire_altpriority_encoder23_w_lg_zero976w(0) AND wire_altpriority_encoder23_q(i);
END GENERATE loop68;
loop69 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder23_w_lg_zero978w(i) <= wire_altpriority_encoder23_zero AND wire_altpriority_encoder24_q(i);
END GENERATE loop69;
wire_altpriority_encoder23_w_lg_zero976w(0) <= NOT wire_altpriority_encoder23_zero;
loop70 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder23_w_lg_w_lg_zero978w979w(i) <= wire_altpriority_encoder23_w_lg_zero978w(i) OR wire_altpriority_encoder23_w_lg_w_lg_zero976w977w(i);
END GENERATE loop70;
altpriority_encoder23 : add_flt_stratix5_latency_altpriority_encoder_vh8
PORT MAP (
data => data(7 DOWNTO 0),
q => wire_altpriority_encoder23_q,
zero => wire_altpriority_encoder23_zero
);
altpriority_encoder24 : add_flt_stratix5_latency_altpriority_encoder_vh8
PORT MAP (
data => data(15 DOWNTO 8),
q => wire_altpriority_encoder24_q,
zero => wire_altpriority_encoder24_zero
);
END RTL; --add_flt_stratix5_latency_altpriority_encoder_fj8
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=16 WIDTHAD=4 data q
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=8 WIDTHAD=3 data q
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=4 WIDTHAD=2 data q
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=2 WIDTHAD=1 data q
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_latency_altpriority_encoder_n28 IS
PORT
(
data : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END add_flt_stratix5_latency_altpriority_encoder_n28;
ARCHITECTURE RTL OF add_flt_stratix5_latency_altpriority_encoder_n28 IS
SIGNAL wire_altpriority_encoder34_w_lg_w_data_range1038w1040w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder34_w_data_range1038w : STD_LOGIC_VECTOR (0 DOWNTO 0);
BEGIN
wire_altpriority_encoder34_w_lg_w_data_range1038w1040w(0) <= NOT wire_altpriority_encoder34_w_data_range1038w(0);
q <= ( wire_altpriority_encoder34_w_lg_w_data_range1038w1040w);
wire_altpriority_encoder34_w_data_range1038w(0) <= data(0);
END RTL; --add_flt_stratix5_latency_altpriority_encoder_n28
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_latency_altpriority_encoder_q28 IS
PORT
(
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END add_flt_stratix5_latency_altpriority_encoder_q28;
ARCHITECTURE RTL OF add_flt_stratix5_latency_altpriority_encoder_q28 IS
SIGNAL wire_altpriority_encoder33_w_lg_w_lg_zero1031w1032w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder33_w_lg_zero1033w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder33_w_lg_zero1031w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder33_w_lg_w_lg_zero1033w1034w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder33_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder33_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder34_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT add_flt_stratix5_latency_altpriority_encoder_nh8
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT add_flt_stratix5_latency_altpriority_encoder_n28
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder33_zero & wire_altpriority_encoder33_w_lg_w_lg_zero1033w1034w);
wire_altpriority_encoder33_w_lg_w_lg_zero1031w1032w(0) <= wire_altpriority_encoder33_w_lg_zero1031w(0) AND wire_altpriority_encoder33_q(0);
wire_altpriority_encoder33_w_lg_zero1033w(0) <= wire_altpriority_encoder33_zero AND wire_altpriority_encoder34_q(0);
wire_altpriority_encoder33_w_lg_zero1031w(0) <= NOT wire_altpriority_encoder33_zero;
wire_altpriority_encoder33_w_lg_w_lg_zero1033w1034w(0) <= wire_altpriority_encoder33_w_lg_zero1033w(0) OR wire_altpriority_encoder33_w_lg_w_lg_zero1031w1032w(0);
altpriority_encoder33 : add_flt_stratix5_latency_altpriority_encoder_nh8
PORT MAP (
data => data(1 DOWNTO 0),
q => wire_altpriority_encoder33_q,
zero => wire_altpriority_encoder33_zero
);
altpriority_encoder34 : add_flt_stratix5_latency_altpriority_encoder_n28
PORT MAP (
data => data(3 DOWNTO 2),
q => wire_altpriority_encoder34_q
);
END RTL; --add_flt_stratix5_latency_altpriority_encoder_q28
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_latency_altpriority_encoder_v28 IS
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
);
END add_flt_stratix5_latency_altpriority_encoder_v28;
ARCHITECTURE RTL OF add_flt_stratix5_latency_altpriority_encoder_v28 IS
SIGNAL wire_altpriority_encoder31_w_lg_w_lg_zero1022w1023w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder31_w_lg_zero1024w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder31_w_lg_zero1022w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder31_w_lg_w_lg_zero1024w1025w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder31_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder31_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder32_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
COMPONENT add_flt_stratix5_latency_altpriority_encoder_qh8
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT add_flt_stratix5_latency_altpriority_encoder_q28
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder31_zero & wire_altpriority_encoder31_w_lg_w_lg_zero1024w1025w);
loop71 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder31_w_lg_w_lg_zero1022w1023w(i) <= wire_altpriority_encoder31_w_lg_zero1022w(0) AND wire_altpriority_encoder31_q(i);
END GENERATE loop71;
loop72 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder31_w_lg_zero1024w(i) <= wire_altpriority_encoder31_zero AND wire_altpriority_encoder32_q(i);
END GENERATE loop72;
wire_altpriority_encoder31_w_lg_zero1022w(0) <= NOT wire_altpriority_encoder31_zero;
loop73 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder31_w_lg_w_lg_zero1024w1025w(i) <= wire_altpriority_encoder31_w_lg_zero1024w(i) OR wire_altpriority_encoder31_w_lg_w_lg_zero1022w1023w(i);
END GENERATE loop73;
altpriority_encoder31 : add_flt_stratix5_latency_altpriority_encoder_qh8
PORT MAP (
data => data(3 DOWNTO 0),
q => wire_altpriority_encoder31_q,
zero => wire_altpriority_encoder31_zero
);
altpriority_encoder32 : add_flt_stratix5_latency_altpriority_encoder_q28
PORT MAP (
data => data(7 DOWNTO 4),
q => wire_altpriority_encoder32_q
);
END RTL; --add_flt_stratix5_latency_altpriority_encoder_v28
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_latency_altpriority_encoder_f48 IS
PORT
(
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END add_flt_stratix5_latency_altpriority_encoder_f48;
ARCHITECTURE RTL OF add_flt_stratix5_latency_altpriority_encoder_f48 IS
SIGNAL wire_altpriority_encoder29_w_lg_w_lg_zero1013w1014w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder29_w_lg_zero1015w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder29_w_lg_zero1013w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder29_w_lg_w_lg_zero1015w1016w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder29_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder29_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder30_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
COMPONENT add_flt_stratix5_latency_altpriority_encoder_vh8
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT add_flt_stratix5_latency_altpriority_encoder_v28
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder29_zero & wire_altpriority_encoder29_w_lg_w_lg_zero1015w1016w);
loop74 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder29_w_lg_w_lg_zero1013w1014w(i) <= wire_altpriority_encoder29_w_lg_zero1013w(0) AND wire_altpriority_encoder29_q(i);
END GENERATE loop74;
loop75 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder29_w_lg_zero1015w(i) <= wire_altpriority_encoder29_zero AND wire_altpriority_encoder30_q(i);
END GENERATE loop75;
wire_altpriority_encoder29_w_lg_zero1013w(0) <= NOT wire_altpriority_encoder29_zero;
loop76 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder29_w_lg_w_lg_zero1015w1016w(i) <= wire_altpriority_encoder29_w_lg_zero1015w(i) OR wire_altpriority_encoder29_w_lg_w_lg_zero1013w1014w(i);
END GENERATE loop76;
altpriority_encoder29 : add_flt_stratix5_latency_altpriority_encoder_vh8
PORT MAP (
data => data(7 DOWNTO 0),
q => wire_altpriority_encoder29_q,
zero => wire_altpriority_encoder29_zero
);
altpriority_encoder30 : add_flt_stratix5_latency_altpriority_encoder_v28
PORT MAP (
data => data(15 DOWNTO 8),
q => wire_altpriority_encoder30_q
);
END RTL; --add_flt_stratix5_latency_altpriority_encoder_f48
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_latency_altpriority_encoder_e48 IS
PORT
(
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END add_flt_stratix5_latency_altpriority_encoder_e48;
ARCHITECTURE RTL OF add_flt_stratix5_latency_altpriority_encoder_e48 IS
SIGNAL wire_altpriority_encoder21_w_lg_w_lg_zero967w968w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_w_lg_zero969w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_w_lg_zero967w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_w_lg_w_lg_zero969w970w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_q : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder22_q : STD_LOGIC_VECTOR (3 DOWNTO 0);
COMPONENT add_flt_stratix5_latency_altpriority_encoder_fj8
PORT
(
data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT add_flt_stratix5_latency_altpriority_encoder_f48
PORT
(
data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder21_zero & wire_altpriority_encoder21_w_lg_w_lg_zero969w970w);
loop77 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder21_w_lg_w_lg_zero967w968w(i) <= wire_altpriority_encoder21_w_lg_zero967w(0) AND wire_altpriority_encoder21_q(i);
END GENERATE loop77;
loop78 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder21_w_lg_zero969w(i) <= wire_altpriority_encoder21_zero AND wire_altpriority_encoder22_q(i);
END GENERATE loop78;
wire_altpriority_encoder21_w_lg_zero967w(0) <= NOT wire_altpriority_encoder21_zero;
loop79 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder21_w_lg_w_lg_zero969w970w(i) <= wire_altpriority_encoder21_w_lg_zero969w(i) OR wire_altpriority_encoder21_w_lg_w_lg_zero967w968w(i);
END GENERATE loop79;
altpriority_encoder21 : add_flt_stratix5_latency_altpriority_encoder_fj8
PORT MAP (
data => data(15 DOWNTO 0),
q => wire_altpriority_encoder21_q,
zero => wire_altpriority_encoder21_zero
);
altpriority_encoder22 : add_flt_stratix5_latency_altpriority_encoder_f48
PORT MAP (
data => data(31 DOWNTO 16),
q => wire_altpriority_encoder22_q
);
END RTL; --add_flt_stratix5_latency_altpriority_encoder_e48
LIBRARY lpm;
USE lpm.all;
--synthesis_resources = lpm_add_sub 14 lpm_compare 1 reg 282
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_latency_altfp_add_sub_5jj IS
PORT
(
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END add_flt_stratix5_latency_altfp_add_sub_5jj;
ARCHITECTURE RTL OF add_flt_stratix5_latency_altfp_add_sub_5jj IS
SIGNAL wire_lbarrel_shift_result : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_data : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_result : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_leading_zeroes_cnt_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL wire_leading_zeroes_cnt_q : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_trailing_zeros_cnt_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL wire_trailing_zeros_cnt_q : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL both_inputs_are_infinite_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL data_exp_dffe1 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL dataa_man_dffe1 : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL dataa_sign_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL datab_man_dffe1 : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL datab_sign_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL denormal_res_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL denormal_res_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL exp_adj_dffe21 : STD_LOGIC_VECTOR(1 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_out_dffe5 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe2 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe21 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe3 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe4 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_res_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_res_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_add_sub_res_mag_dffe21 : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_add_sub_res_sign_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_dffe31 : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_leading_zeros_dffe31 : STD_LOGIC_VECTOR(4 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_out_dffe5 : STD_LOGIC_VECTOR(22 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_res_dffe4 : STD_LOGIC_VECTOR(22 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_res_is_not_zero_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_res_is_not_zero_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_res_is_not_zero_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL need_complement_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL round_bit_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL round_bit_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL round_bit_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL rounded_res_infinity_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_out_dffe5 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_res_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_res_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL zero_man_sign_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL zero_man_sign_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_add_sub1_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_add_sub2_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_add_sub3_result : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_add_sub4_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_add_sub5_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_add_sub6_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_man_2comp_res_lower_w_lg_w_lg_cout367w368w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_2comp_res_lower_w_lg_cout366w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_2comp_res_lower_w_lg_cout367w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_2comp_res_lower_w_lg_w_lg_w_lg_cout367w368w369w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_2comp_res_lower_cout : STD_LOGIC;
SIGNAL wire_man_2comp_res_lower_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_gnd : STD_LOGIC;
SIGNAL wire_man_2comp_res_upper0_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_vcc : STD_LOGIC;
SIGNAL wire_man_2comp_res_upper1_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_lower_w_lg_w_lg_cout354w355w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_lower_w_lg_cout353w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_lower_w_lg_cout354w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_add_sub_lower_w_lg_w_lg_w_lg_cout354w355w356w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_lower_cout : STD_LOGIC;
SIGNAL wire_man_add_sub_lower_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_upper0_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_upper1_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_lower_w_lg_w_lg_cout580w581w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_lower_w_lg_cout579w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_lower_w_lg_cout580w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_lower_w_lg_w_lg_w_lg_cout580w581w582w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_lower_cout : STD_LOGIC;
SIGNAL wire_man_res_rounding_add_sub_lower_result : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_upper1_result : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_trailing_zeros_limit_comparator_agb : STD_LOGIC;
SIGNAL wire_w248w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w267w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w397w407w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_force_zero_w634w635w636w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_force_zero_w634w635w645w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_denormal_result_w558w559w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w324w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w331w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w317w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_amb_mux_w275w278w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_amb_mux_w275w276w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_infinity_w629w639w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_infinity_w629w648w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_infinity_w629w654w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_nan_w630w642w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_nan_w630w651w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w243w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w234w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_dataa_infinite_dffe11_wo246w247w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w262w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w253w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_datab_infinite_dffe11_wo265w266w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_datab_infinite_dffe15_wo337w338w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_man_res_not_zero_dffe26_wo503w504w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w292w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_w397w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w383w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_w412w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_man_add_sub_w_range372w375w378w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL wire_w587w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_zero_w634w637w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_zero_w634w646w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_dffe15_wo330w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_dffe15_wo323w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_dffe15_wo314w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_w279w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_w273w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_force_infinity_w640w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_force_infinity_w649w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_force_nan_w643w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_force_nan_w652w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_need_complement_dffe22_wo376w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range17w23w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range27w33w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range37w43w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range47w53w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range57w63w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range67w73w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range77w83w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range20w25w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range30w35w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range40w45w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range50w55w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range60w65w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range70w75w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range80w85w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_a_all_one_w_range84w220w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_b_all_one_w_range86w226w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_diff_abs_exceed_max_w_range289w293w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range540w542w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range543w544w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range545w546w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range547w548w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range549w550w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range551w552w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range553w554w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range555w561w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range601w604w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range605w607w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range608w610w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range611w613w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range614w616w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range617w619w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range620w622w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w391w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w384w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w414w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_w_range372w379w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_rounding_add_sub_w_range585w589w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_zero_w634w635w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_add_sub_dffe25_wo491w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_add_sub_w2342w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_denormal_result_w558w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_dffe15_wo316w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_w275w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_force_infinity_w629w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_force_nan_w630w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_force_zero_w628w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_dataa_denormal_dffe11_wo233w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_dataa_infinite_dffe11_wo246w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_dataa_zero_dffe11_wo245w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_datab_denormal_dffe11_wo252w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_datab_infinite_dffe11_wo265w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_datab_infinite_dffe15_wo337w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_datab_zero_dffe11_wo264w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_man_res_is_not_zero_dffe4_wo627w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_man_res_not_zero_dffe26_wo503w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_need_complement_dffe22_wo373w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_sticky_bit_dffe1_wo343w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_adjustment2_add_sub_w_range511w560w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_diff_abs_exceed_max_w_range289w291w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_a_not_zero_w_range215w219w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range387w390w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_w_range372w375w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_b_not_zero_w_range218w225w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_rounding_add_sub_w_range585w586w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_force_zero_w634w637w638w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_force_zero_w634w646w647w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_infinity_w640w641w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_infinity_w649w650w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_force_zero_w634w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_sticky_bit_dffe27_wo402w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range141w142w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range147w148w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range153w154w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range159w160w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range165w166w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range171w172w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range177w178w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range183w184w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range189w190w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range195w196w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range87w88w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range201w202w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range207w208w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range213w214w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range17w18w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range27w28w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range37w38w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range47w48w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range57w58w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range67w68w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range93w94w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range77w78w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range99w100w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range105w106w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range111w112w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range117w118w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range123w124w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range129w130w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range135w136w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range144w145w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range150w151w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range156w157w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range162w163w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range168w169w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range174w175w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range180w181w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range186w187w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range192w193w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range198w199w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range90w91w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range204w205w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range210w211w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range216w217w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range20w21w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range30w31w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range40w41w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range50w51w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range60w61w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range70w71w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range96w97w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range80w81w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range102w103w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range108w109w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range114w115w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range120w121w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range126w127w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range132w133w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range138w139w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_diff_abs_exceed_max_w_range282w285w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_diff_abs_exceed_max_w_range286w288w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range516w519w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range520w522w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range523w525w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range526w528w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range529w531w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range532w534w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range535w537w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range538w539w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range417w420w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range448w450w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range451w453w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range454w456w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range457w459w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range460w462w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range463w465w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range466w468w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range469w471w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range472w474w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range475w477w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range421w423w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range478w480w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range481w483w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range484w486w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range487w489w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range424w426w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range427w429w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range430w432w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range433w435w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range436w438w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range439w441w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range442w444w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range445w447w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL aclr : STD_LOGIC;
SIGNAL add_sub_dffe25_wi : STD_LOGIC;
SIGNAL add_sub_dffe25_wo : STD_LOGIC;
SIGNAL add_sub_w2 : STD_LOGIC;
SIGNAL adder_upper_w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe12_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe12_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe13_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe13_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe14_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe14_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe15_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe15_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe12_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe12_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe13_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe13_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe14_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe14_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe15_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe15_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe15_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL aligned_dataa_sign_dffe12_wi : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe12_wo : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe13_wi : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe13_wo : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe14_wi : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe14_wo : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe15_wi : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe15_wo : STD_LOGIC;
SIGNAL aligned_dataa_sign_w : STD_LOGIC;
SIGNAL aligned_datab_exp_dffe12_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe12_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe13_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe13_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe14_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe14_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe15_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe15_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_man_dffe12_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe12_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe13_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe13_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe14_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe14_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe15_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL aligned_datab_man_dffe15_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe15_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL aligned_datab_sign_dffe12_wi : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe12_wo : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe13_wi : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe13_wo : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe14_wi : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe14_wo : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe15_wi : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe15_wo : STD_LOGIC;
SIGNAL aligned_datab_sign_w : STD_LOGIC;
SIGNAL borrow_w : STD_LOGIC;
SIGNAL both_inputs_are_infinite_dffe1_wi : STD_LOGIC;
SIGNAL both_inputs_are_infinite_dffe1_wo : STD_LOGIC;
SIGNAL both_inputs_are_infinite_dffe25_wi : STD_LOGIC;
SIGNAL both_inputs_are_infinite_dffe25_wo : STD_LOGIC;
SIGNAL data_exp_dffe1_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL data_exp_dffe1_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL dataa_dffe11_wi : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL dataa_dffe11_wo : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL dataa_man_dffe1_wi : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL dataa_man_dffe1_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL dataa_sign_dffe1_wi : STD_LOGIC;
SIGNAL dataa_sign_dffe1_wo : STD_LOGIC;
SIGNAL dataa_sign_dffe25_wi : STD_LOGIC;
SIGNAL dataa_sign_dffe25_wo : STD_LOGIC;
SIGNAL datab_dffe11_wi : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL datab_dffe11_wo : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL datab_man_dffe1_wi : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL datab_man_dffe1_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL datab_sign_dffe1_wi : STD_LOGIC;
SIGNAL datab_sign_dffe1_wo : STD_LOGIC;
SIGNAL denormal_flag_w : STD_LOGIC;
SIGNAL denormal_res_dffe32_wi : STD_LOGIC;
SIGNAL denormal_res_dffe32_wo : STD_LOGIC;
SIGNAL denormal_res_dffe33_wi : STD_LOGIC;
SIGNAL denormal_res_dffe33_wo : STD_LOGIC;
SIGNAL denormal_res_dffe3_wi : STD_LOGIC;
SIGNAL denormal_res_dffe3_wo : STD_LOGIC;
SIGNAL denormal_res_dffe41_wi : STD_LOGIC;
SIGNAL denormal_res_dffe41_wo : STD_LOGIC;
SIGNAL denormal_res_dffe42_wi : STD_LOGIC;
SIGNAL denormal_res_dffe42_wo : STD_LOGIC;
SIGNAL denormal_res_dffe4_wi : STD_LOGIC;
SIGNAL denormal_res_dffe4_wo : STD_LOGIC;
SIGNAL denormal_result_w : STD_LOGIC;
SIGNAL exp_a_all_one_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_a_not_zero_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_adj_0pads : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL exp_adj_dffe21_wi : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adj_dffe21_wo : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adj_dffe23_wi : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adj_dffe23_wo : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adj_dffe26_wi : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adj_dffe26_wo : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adjust_by_add1 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adjust_by_add2 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adjustment2_add_sub_dataa_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adjustment2_add_sub_datab_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adjustment2_add_sub_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adjustment_add_sub_dataa_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adjustment_add_sub_datab_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adjustment_add_sub_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_all_ones_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_all_zeros_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_amb_mux_dffe13_wi : STD_LOGIC;
SIGNAL exp_amb_mux_dffe13_wo : STD_LOGIC;
SIGNAL exp_amb_mux_dffe14_wi : STD_LOGIC;
SIGNAL exp_amb_mux_dffe14_wo : STD_LOGIC;
SIGNAL exp_amb_mux_dffe15_wi : STD_LOGIC;
SIGNAL exp_amb_mux_dffe15_wo : STD_LOGIC;
SIGNAL exp_amb_mux_w : STD_LOGIC;
SIGNAL exp_amb_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_b_all_one_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_b_not_zero_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_bma_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_diff_abs_exceed_max_w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL exp_diff_abs_max_w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL exp_diff_abs_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_intermediate_res_dffe41_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_intermediate_res_dffe41_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_intermediate_res_dffe42_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_intermediate_res_dffe42_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_intermediate_res_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_out_dffe5_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_out_dffe5_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe21_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe21_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe22_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe22_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe23_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe23_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe25_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe25_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe26_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe26_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe27_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe27_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe2_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe2_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe32_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe32_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe33_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe33_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe3_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe3_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe4_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe4_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_max_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_not_zero_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_res_rounding_adder_dataa_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_res_rounding_adder_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_rounded_res_infinity_w : STD_LOGIC;
SIGNAL exp_rounded_res_max_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_rounded_res_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_rounding_adjustment_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_value : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL force_infinity_w : STD_LOGIC;
SIGNAL force_nan_w : STD_LOGIC;
SIGNAL force_zero_w : STD_LOGIC;
SIGNAL guard_bit_dffe3_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe1_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe1_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe21_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe21_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe22_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe22_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe23_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe23_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe25_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe25_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe26_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe26_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe27_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe27_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe2_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe2_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe31_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe31_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe32_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe32_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe33_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe33_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe3_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe3_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe41_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe41_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe42_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe42_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe4_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe4_wo : STD_LOGIC;
SIGNAL infinite_res_dff32_wi : STD_LOGIC;
SIGNAL infinite_res_dff32_wo : STD_LOGIC;
SIGNAL infinite_res_dff33_wi : STD_LOGIC;
SIGNAL infinite_res_dff33_wo : STD_LOGIC;
SIGNAL infinite_res_dffe3_wi : STD_LOGIC;
SIGNAL infinite_res_dffe3_wo : STD_LOGIC;
SIGNAL infinite_res_dffe41_wi : STD_LOGIC;
SIGNAL infinite_res_dffe41_wo : STD_LOGIC;
SIGNAL infinite_res_dffe42_wi : STD_LOGIC;
SIGNAL infinite_res_dffe42_wo : STD_LOGIC;
SIGNAL infinite_res_dffe4_wi : STD_LOGIC;
SIGNAL infinite_res_dffe4_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe21_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe21_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe22_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe22_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe23_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe23_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe26_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe26_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe27_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe27_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe2_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe2_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe31_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe31_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe32_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe32_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe33_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe33_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe3_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe3_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe41_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe41_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe42_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe42_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe4_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe4_wo : STD_LOGIC;
SIGNAL input_dataa_denormal_dffe11_wi : STD_LOGIC;
SIGNAL input_dataa_denormal_dffe11_wo : STD_LOGIC;
SIGNAL input_dataa_denormal_w : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe11_wi : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe11_wo : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe12_wi : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe12_wo : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe13_wi : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe13_wo : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe14_wi : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe14_wo : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe15_wi : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe15_wo : STD_LOGIC;
SIGNAL input_dataa_infinite_w : STD_LOGIC;
SIGNAL input_dataa_nan_dffe11_wi : STD_LOGIC;
SIGNAL input_dataa_nan_dffe11_wo : STD_LOGIC;
SIGNAL input_dataa_nan_dffe12_wi : STD_LOGIC;
SIGNAL input_dataa_nan_dffe12_wo : STD_LOGIC;
SIGNAL input_dataa_nan_w : STD_LOGIC;
SIGNAL input_dataa_zero_dffe11_wi : STD_LOGIC;
SIGNAL input_dataa_zero_dffe11_wo : STD_LOGIC;
SIGNAL input_dataa_zero_w : STD_LOGIC;
SIGNAL input_datab_denormal_dffe11_wi : STD_LOGIC;
SIGNAL input_datab_denormal_dffe11_wo : STD_LOGIC;
SIGNAL input_datab_denormal_w : STD_LOGIC;
SIGNAL input_datab_infinite_dffe11_wi : STD_LOGIC;
SIGNAL input_datab_infinite_dffe11_wo : STD_LOGIC;
SIGNAL input_datab_infinite_dffe12_wi : STD_LOGIC;
SIGNAL input_datab_infinite_dffe12_wo : STD_LOGIC;
SIGNAL input_datab_infinite_dffe13_wi : STD_LOGIC;
SIGNAL input_datab_infinite_dffe13_wo : STD_LOGIC;
SIGNAL input_datab_infinite_dffe14_wi : STD_LOGIC;
SIGNAL input_datab_infinite_dffe14_wo : STD_LOGIC;
SIGNAL input_datab_infinite_dffe15_wi : STD_LOGIC;
SIGNAL input_datab_infinite_dffe15_wo : STD_LOGIC;
SIGNAL input_datab_infinite_w : STD_LOGIC;
SIGNAL input_datab_nan_dffe11_wi : STD_LOGIC;
SIGNAL input_datab_nan_dffe11_wo : STD_LOGIC;
SIGNAL input_datab_nan_dffe12_wi : STD_LOGIC;
SIGNAL input_datab_nan_dffe12_wo : STD_LOGIC;
SIGNAL input_datab_nan_w : STD_LOGIC;
SIGNAL input_datab_zero_dffe11_wi : STD_LOGIC;
SIGNAL input_datab_zero_dffe11_wo : STD_LOGIC;
SIGNAL input_datab_zero_w : STD_LOGIC;
SIGNAL input_is_infinite_dffe1_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe1_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe21_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe21_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe22_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe22_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe23_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe23_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe25_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe25_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe26_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe26_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe27_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe27_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe2_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe2_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe31_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe31_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe32_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe32_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe33_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe33_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe3_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe3_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe41_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe41_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe42_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe42_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe4_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe4_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe13_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe13_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe14_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe14_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe15_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe15_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe1_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe1_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe21_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe21_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe22_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe22_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe23_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe23_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe25_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe25_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe26_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe26_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe27_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe27_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe2_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe2_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe31_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe31_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe32_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe32_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe33_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe33_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe3_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe3_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe41_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe41_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe42_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe42_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe4_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe4_wo : STD_LOGIC;
SIGNAL man_2comp_res_dataa_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_2comp_res_datab_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_2comp_res_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_a_not_zero_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_add_sub_dataa_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_add_sub_datab_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe21_wi : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe21_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe23_wi : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe23_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe26_wi : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe26_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe27_wi : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe27_wo : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_add_sub_res_mag_w2 : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_add_sub_res_sign_dffe21_wo : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe23_wi : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe23_wo : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe26_wi : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe26_wo : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe27_wi : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe27_wo : STD_LOGIC;
SIGNAL man_add_sub_res_sign_w2 : STD_LOGIC;
SIGNAL man_add_sub_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_all_zeros_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_b_not_zero_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_dffe31_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_intermediate_res_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_leading_zeros_cnt_w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL man_leading_zeros_dffe31_wi : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL man_leading_zeros_dffe31_wo : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL man_nan_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_out_dffe5_wi : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_out_dffe5_wo : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_res_dffe4_wi : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_res_dffe4_wo : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_res_is_not_zero_dffe31_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe31_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe32_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe32_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe33_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe33_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe3_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe3_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe41_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe41_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe42_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe42_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe4_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe4_wo : STD_LOGIC;
SIGNAL man_res_mag_w2 : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_res_not_zero_dffe23_wi : STD_LOGIC;
SIGNAL man_res_not_zero_dffe23_wo : STD_LOGIC;
SIGNAL man_res_not_zero_dffe26_wi : STD_LOGIC;
SIGNAL man_res_not_zero_dffe26_wo : STD_LOGIC;
SIGNAL man_res_not_zero_w2 : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL man_res_rounding_add_sub_datab_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_res_rounding_add_sub_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_res_w3 : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL man_rounded_res_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_rounding_add_value_w : STD_LOGIC;
SIGNAL man_smaller_dffe13_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL man_smaller_dffe13_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL man_smaller_w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL need_complement_dffe22_wi : STD_LOGIC;
SIGNAL need_complement_dffe22_wo : STD_LOGIC;
SIGNAL need_complement_dffe2_wi : STD_LOGIC;
SIGNAL need_complement_dffe2_wo : STD_LOGIC;
SIGNAL pos_sign_bit_ext : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL priority_encoder_1pads_w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL round_bit_dffe21_wi : STD_LOGIC;
SIGNAL round_bit_dffe21_wo : STD_LOGIC;
SIGNAL round_bit_dffe23_wi : STD_LOGIC;
SIGNAL round_bit_dffe23_wo : STD_LOGIC;
SIGNAL round_bit_dffe26_wi : STD_LOGIC;
SIGNAL round_bit_dffe26_wo : STD_LOGIC;
SIGNAL round_bit_dffe31_wi : STD_LOGIC;
SIGNAL round_bit_dffe31_wo : STD_LOGIC;
SIGNAL round_bit_dffe32_wi : STD_LOGIC;
SIGNAL round_bit_dffe32_wo : STD_LOGIC;
SIGNAL round_bit_dffe33_wi : STD_LOGIC;
SIGNAL round_bit_dffe33_wo : STD_LOGIC;
SIGNAL round_bit_dffe3_wi : STD_LOGIC;
SIGNAL round_bit_dffe3_wo : STD_LOGIC;
SIGNAL round_bit_w : STD_LOGIC;
SIGNAL rounded_res_infinity_dffe4_wi : STD_LOGIC;
SIGNAL rounded_res_infinity_dffe4_wo : STD_LOGIC;
SIGNAL rshift_distance_dffe13_wi : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_dffe13_wo : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_dffe14_wi : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_dffe14_wo : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_dffe15_wi : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_dffe15_wo : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sign_dffe31_wi : STD_LOGIC;
SIGNAL sign_dffe31_wo : STD_LOGIC;
SIGNAL sign_dffe32_wi : STD_LOGIC;
SIGNAL sign_dffe32_wo : STD_LOGIC;
SIGNAL sign_dffe33_wi : STD_LOGIC;
SIGNAL sign_dffe33_wo : STD_LOGIC;
SIGNAL sign_out_dffe5_wi : STD_LOGIC;
SIGNAL sign_out_dffe5_wo : STD_LOGIC;
SIGNAL sign_res_dffe3_wi : STD_LOGIC;
SIGNAL sign_res_dffe3_wo : STD_LOGIC;
SIGNAL sign_res_dffe41_wi : STD_LOGIC;
SIGNAL sign_res_dffe41_wo : STD_LOGIC;
SIGNAL sign_res_dffe42_wi : STD_LOGIC;
SIGNAL sign_res_dffe42_wo : STD_LOGIC;
SIGNAL sign_res_dffe4_wi : STD_LOGIC;
SIGNAL sign_res_dffe4_wo : STD_LOGIC;
SIGNAL sticky_bit_cnt_dataa_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sticky_bit_cnt_datab_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sticky_bit_cnt_res_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sticky_bit_dffe1_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe1_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe21_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe21_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe22_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe22_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe23_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe23_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe25_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe25_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe26_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe26_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe27_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe27_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe2_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe2_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe31_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe31_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe32_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe32_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe33_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe33_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe3_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe3_wo : STD_LOGIC;
SIGNAL sticky_bit_w : STD_LOGIC;
SIGNAL trailing_zeros_limit_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL zero_man_sign_dffe21_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe21_wo : STD_LOGIC;
SIGNAL zero_man_sign_dffe22_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe22_wo : STD_LOGIC;
SIGNAL zero_man_sign_dffe23_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe23_wo : STD_LOGIC;
SIGNAL zero_man_sign_dffe26_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe26_wo : STD_LOGIC;
SIGNAL zero_man_sign_dffe27_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe27_wo : STD_LOGIC;
SIGNAL zero_man_sign_dffe2_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe2_wo : STD_LOGIC;
SIGNAL wire_w_aligned_dataa_exp_dffe15_wo_range315w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_aligned_datab_exp_dffe15_wo_range313w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_dataa_range141w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range147w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range153w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range159w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range165w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range171w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range177w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range183w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range189w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range195w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range87w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range201w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range207w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range213w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range17w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range27w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range37w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range47w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range57w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range67w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range93w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range77w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range99w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range105w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range111w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range117w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range123w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range129w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range135w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_dffe11_wo_range242w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_dataa_dffe11_wo_range232w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_datab_range144w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range150w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range156w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range162w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range168w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range174w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range180w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range186w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range192w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range198w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range90w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range204w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range210w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range216w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range20w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range30w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range40w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range50w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range60w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range70w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range96w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range80w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range102w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range108w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range114w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range120w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range126w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range132w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range138w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_dffe11_wo_range261w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_datab_dffe11_wo_range251w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range7w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range24w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range34w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range44w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range54w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range64w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range74w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range84w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range2w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range19w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range29w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range39w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range49w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range59w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range69w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range518w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range521w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range524w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range527w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range530w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range533w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range557w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range536w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range511w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_amb_w_range274w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range9w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range26w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range36w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range46w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range56w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range66w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range76w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range86w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range5w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range22w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range32w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range42w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range52w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range62w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range72w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_bma_w_range272w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_exceed_max_w_range282w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_exceed_max_w_range286w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_exceed_max_w_range289w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_w_range290w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_w_range284w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_w_range287w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range540w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range543w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range545w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range547w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range549w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range551w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range553w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range555w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range516w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range520w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range523w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range526w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range529w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range532w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range535w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range538w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range601w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range605w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range608w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range611w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range614w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range617w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range620w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range603w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range606w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range609w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range612w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range615w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range618w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range621w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range12w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range143w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range149w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range155w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range161w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range167w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range173w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range179w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range185w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range191w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range197w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range89w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range203w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range209w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range215w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range95w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range101w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range107w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range113w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range119w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range125w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range131w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range137w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range443w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range446w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range449w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range452w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range455w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range458w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range461w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range464w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range467w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range470w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range473w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range476w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range479w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range482w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range485w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range488w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range419w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range422w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range425w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range428w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range431w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range434w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range437w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range440w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe27_wo_range396w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe27_wo_range411w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe27_wo_range387w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe27_wo_range413w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe27_wo_range381w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_w_range372w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range15w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range146w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range152w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range158w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range164w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range170w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range176w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range182w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range188w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range194w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range200w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range92w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range206w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range212w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range218w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range98w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range104w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range110w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range116w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range122w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range128w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range134w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range140w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range417w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range448w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range451w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range454w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range457w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range460w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range463w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range466w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range469w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range472w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range475w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range421w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range478w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range481w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range484w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range487w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range424w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range427w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range430w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range433w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range436w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range439w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range442w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range445w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_rounding_add_sub_w_range584w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_man_res_rounding_add_sub_w_range588w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_man_res_rounding_add_sub_w_range585w : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT add_flt_stratix5_latency_altbarrel_shift_nud
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
distance : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR(25 DOWNTO 0)
);
END COMPONENT;
COMPONENT add_flt_stratix5_latency_altbarrel_shift_cfb
PORT
(
data : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
distance : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR(25 DOWNTO 0)
);
END COMPONENT;
COMPONENT add_flt_stratix5_latency_altpriority_encoder_qb6
PORT
(
data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT;
COMPONENT add_flt_stratix5_latency_altpriority_encoder_e48
PORT
(
data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT;
COMPONENT lpm_add_sub
GENERIC
(
LPM_DIRECTION : STRING := "DEFAULT";
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "SIGNED";
LPM_WIDTH : NATURAL;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_add_sub"
);
PORT
(
aclr : IN STD_LOGIC := '0';
add_sub : IN STD_LOGIC := '1';
cin : IN STD_LOGIC := 'Z';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
cout : OUT STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
overflow : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT lpm_compare
GENERIC
(
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "UNSIGNED";
LPM_WIDTH : NATURAL;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_compare"
);
PORT
(
aclr : IN STD_LOGIC := '0';
aeb : OUT STD_LOGIC;
agb : OUT STD_LOGIC;
ageb : OUT STD_LOGIC;
alb : OUT STD_LOGIC;
aleb : OUT STD_LOGIC;
aneb : OUT STD_LOGIC;
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
BEGIN
wire_gnd <= '0';
wire_vcc <= '1';
wire_w248w(0) <= wire_w_lg_w_lg_input_dataa_infinite_dffe11_wo246w247w(0) AND wire_w_lg_input_dataa_zero_dffe11_wo245w(0);
wire_w267w(0) <= wire_w_lg_w_lg_input_datab_infinite_dffe11_wo265w266w(0) AND wire_w_lg_input_datab_zero_dffe11_wo264w(0);
wire_w_lg_w397w407w(0) <= wire_w397w(0) AND sticky_bit_dffe27_wo;
loop80 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_w_lg_force_zero_w634w635w636w(i) <= wire_w_lg_w_lg_force_zero_w634w635w(0) AND exp_res_dffe4_wo(i);
END GENERATE loop80;
loop81 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_w_lg_force_zero_w634w635w645w(i) <= wire_w_lg_w_lg_force_zero_w634w635w(0) AND man_res_dffe4_wo(i);
END GENERATE loop81;
loop82 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_denormal_result_w558w559w(i) <= wire_w_lg_denormal_result_w558w(0) AND wire_w_exp_adjustment2_add_sub_w_range557w(i);
END GENERATE loop82;
loop83 : FOR i IN 0 TO 25 GENERATE
wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w324w(i) <= wire_w_lg_exp_amb_mux_dffe15_wo316w(0) AND aligned_dataa_man_dffe15_w(i);
END GENERATE loop83;
loop84 : FOR i IN 0 TO 25 GENERATE
wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w331w(i) <= wire_w_lg_exp_amb_mux_dffe15_wo316w(0) AND wire_rbarrel_shift_result(i);
END GENERATE loop84;
loop85 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w317w(i) <= wire_w_lg_exp_amb_mux_dffe15_wo316w(0) AND wire_w_aligned_dataa_exp_dffe15_wo_range315w(i);
END GENERATE loop85;
loop86 : FOR i IN 0 TO 23 GENERATE
wire_w_lg_w_lg_exp_amb_mux_w275w278w(i) <= wire_w_lg_exp_amb_mux_w275w(0) AND aligned_datab_man_dffe12_wo(i);
END GENERATE loop86;
loop87 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_exp_amb_mux_w275w276w(i) <= wire_w_lg_exp_amb_mux_w275w(0) AND wire_w_exp_amb_w_range274w(i);
END GENERATE loop87;
loop88 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_force_infinity_w629w639w(i) <= wire_w_lg_force_infinity_w629w(0) AND wire_w_lg_w_lg_w_lg_force_zero_w634w637w638w(i);
END GENERATE loop88;
loop89 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_force_infinity_w629w648w(i) <= wire_w_lg_force_infinity_w629w(0) AND wire_w_lg_w_lg_w_lg_force_zero_w634w646w647w(i);
END GENERATE loop89;
wire_w_lg_w_lg_force_infinity_w629w654w(0) <= wire_w_lg_force_infinity_w629w(0) AND sign_res_dffe4_wo;
loop90 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_force_nan_w630w642w(i) <= wire_w_lg_force_nan_w630w(0) AND wire_w_lg_w_lg_force_infinity_w640w641w(i);
END GENERATE loop90;
loop91 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_force_nan_w630w651w(i) <= wire_w_lg_force_nan_w630w(0) AND wire_w_lg_w_lg_force_infinity_w649w650w(i);
END GENERATE loop91;
loop92 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w243w(i) <= wire_w_lg_input_dataa_denormal_dffe11_wo233w(0) AND wire_w_dataa_dffe11_wo_range242w(i);
END GENERATE loop92;
loop93 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w234w(i) <= wire_w_lg_input_dataa_denormal_dffe11_wo233w(0) AND wire_w_dataa_dffe11_wo_range232w(i);
END GENERATE loop93;
wire_w_lg_w_lg_input_dataa_infinite_dffe11_wo246w247w(0) <= wire_w_lg_input_dataa_infinite_dffe11_wo246w(0) AND wire_w_lg_input_dataa_denormal_dffe11_wo233w(0);
loop94 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w262w(i) <= wire_w_lg_input_datab_denormal_dffe11_wo252w(0) AND wire_w_datab_dffe11_wo_range261w(i);
END GENERATE loop94;
loop95 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w253w(i) <= wire_w_lg_input_datab_denormal_dffe11_wo252w(0) AND wire_w_datab_dffe11_wo_range251w(i);
END GENERATE loop95;
wire_w_lg_w_lg_input_datab_infinite_dffe11_wo265w266w(0) <= wire_w_lg_input_datab_infinite_dffe11_wo265w(0) AND wire_w_lg_input_datab_denormal_dffe11_wo252w(0);
wire_w_lg_w_lg_input_datab_infinite_dffe15_wo337w338w(0) <= wire_w_lg_input_datab_infinite_dffe15_wo337w(0) AND aligned_dataa_sign_dffe15_wo;
wire_w_lg_w_lg_man_res_not_zero_dffe26_wo503w504w(0) <= wire_w_lg_man_res_not_zero_dffe26_wo503w(0) AND zero_man_sign_dffe26_wo;
loop96 : FOR i IN 0 TO 4 GENERATE
wire_w292w(i) <= wire_w_lg_w_exp_diff_abs_exceed_max_w_range289w291w(0) AND wire_w_exp_diff_abs_w_range290w(i);
END GENERATE loop96;
wire_w397w(0) <= wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) AND wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range387w390w(0);
loop97 : FOR i IN 0 TO 1 GENERATE
wire_w383w(i) <= wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) AND exp_adjust_by_add1(i);
END GENERATE loop97;
loop98 : FOR i IN 0 TO 25 GENERATE
wire_w412w(i) <= wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) AND wire_w_man_add_sub_res_mag_dffe27_wo_range411w(i);
END GENERATE loop98;
loop99 : FOR i IN 0 TO 27 GENERATE
wire_w_lg_w_lg_w_man_add_sub_w_range372w375w378w(i) <= wire_w_lg_w_man_add_sub_w_range372w375w(0) AND man_add_sub_w(i);
END GENERATE loop99;
loop100 : FOR i IN 0 TO 22 GENERATE
wire_w587w(i) <= wire_w_lg_w_man_res_rounding_add_sub_w_range585w586w(0) AND wire_w_man_res_rounding_add_sub_w_range584w(i);
END GENERATE loop100;
loop101 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_force_zero_w634w637w(i) <= wire_w_lg_force_zero_w634w(0) AND exp_all_zeros_w(i);
END GENERATE loop101;
loop102 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_force_zero_w634w646w(i) <= wire_w_lg_force_zero_w634w(0) AND man_all_zeros_w(i);
END GENERATE loop102;
loop103 : FOR i IN 0 TO 25 GENERATE
wire_w_lg_exp_amb_mux_dffe15_wo330w(i) <= exp_amb_mux_dffe15_wo AND aligned_datab_man_dffe15_w(i);
END GENERATE loop103;
loop104 : FOR i IN 0 TO 25 GENERATE
wire_w_lg_exp_amb_mux_dffe15_wo323w(i) <= exp_amb_mux_dffe15_wo AND wire_rbarrel_shift_result(i);
END GENERATE loop104;
loop105 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_exp_amb_mux_dffe15_wo314w(i) <= exp_amb_mux_dffe15_wo AND wire_w_aligned_datab_exp_dffe15_wo_range313w(i);
END GENERATE loop105;
loop106 : FOR i IN 0 TO 23 GENERATE
wire_w_lg_exp_amb_mux_w279w(i) <= exp_amb_mux_w AND aligned_dataa_man_dffe12_wo(i);
END GENERATE loop106;
loop107 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_exp_amb_mux_w273w(i) <= exp_amb_mux_w AND wire_w_exp_bma_w_range272w(i);
END GENERATE loop107;
loop108 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_force_infinity_w640w(i) <= force_infinity_w AND exp_all_ones_w(i);
END GENERATE loop108;
loop109 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_force_infinity_w649w(i) <= force_infinity_w AND man_all_zeros_w(i);
END GENERATE loop109;
loop110 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_force_nan_w643w(i) <= force_nan_w AND exp_all_ones_w(i);
END GENERATE loop110;
loop111 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_force_nan_w652w(i) <= force_nan_w AND man_nan_w(i);
END GENERATE loop111;
wire_w_lg_need_complement_dffe22_wo376w(0) <= need_complement_dffe22_wo AND wire_w_lg_w_man_add_sub_w_range372w375w(0);
wire_w_lg_w_dataa_range17w23w(0) <= wire_w_dataa_range17w(0) AND wire_w_exp_a_all_one_w_range7w(0);
wire_w_lg_w_dataa_range27w33w(0) <= wire_w_dataa_range27w(0) AND wire_w_exp_a_all_one_w_range24w(0);
wire_w_lg_w_dataa_range37w43w(0) <= wire_w_dataa_range37w(0) AND wire_w_exp_a_all_one_w_range34w(0);
wire_w_lg_w_dataa_range47w53w(0) <= wire_w_dataa_range47w(0) AND wire_w_exp_a_all_one_w_range44w(0);
wire_w_lg_w_dataa_range57w63w(0) <= wire_w_dataa_range57w(0) AND wire_w_exp_a_all_one_w_range54w(0);
wire_w_lg_w_dataa_range67w73w(0) <= wire_w_dataa_range67w(0) AND wire_w_exp_a_all_one_w_range64w(0);
wire_w_lg_w_dataa_range77w83w(0) <= wire_w_dataa_range77w(0) AND wire_w_exp_a_all_one_w_range74w(0);
wire_w_lg_w_datab_range20w25w(0) <= wire_w_datab_range20w(0) AND wire_w_exp_b_all_one_w_range9w(0);
wire_w_lg_w_datab_range30w35w(0) <= wire_w_datab_range30w(0) AND wire_w_exp_b_all_one_w_range26w(0);
wire_w_lg_w_datab_range40w45w(0) <= wire_w_datab_range40w(0) AND wire_w_exp_b_all_one_w_range36w(0);
wire_w_lg_w_datab_range50w55w(0) <= wire_w_datab_range50w(0) AND wire_w_exp_b_all_one_w_range46w(0);
wire_w_lg_w_datab_range60w65w(0) <= wire_w_datab_range60w(0) AND wire_w_exp_b_all_one_w_range56w(0);
wire_w_lg_w_datab_range70w75w(0) <= wire_w_datab_range70w(0) AND wire_w_exp_b_all_one_w_range66w(0);
wire_w_lg_w_datab_range80w85w(0) <= wire_w_datab_range80w(0) AND wire_w_exp_b_all_one_w_range76w(0);
wire_w_lg_w_exp_a_all_one_w_range84w220w(0) <= wire_w_exp_a_all_one_w_range84w(0) AND wire_w_lg_w_man_a_not_zero_w_range215w219w(0);
wire_w_lg_w_exp_b_all_one_w_range86w226w(0) <= wire_w_exp_b_all_one_w_range86w(0) AND wire_w_lg_w_man_b_not_zero_w_range218w225w(0);
loop112 : FOR i IN 0 TO 4 GENERATE
wire_w_lg_w_exp_diff_abs_exceed_max_w_range289w293w(i) <= wire_w_exp_diff_abs_exceed_max_w_range289w(0) AND exp_diff_abs_max_w(i);
END GENERATE loop112;
wire_w_lg_w_exp_res_max_w_range540w542w(0) <= wire_w_exp_res_max_w_range540w(0) AND wire_w_exp_adjustment2_add_sub_w_range518w(0);
wire_w_lg_w_exp_res_max_w_range543w544w(0) <= wire_w_exp_res_max_w_range543w(0) AND wire_w_exp_adjustment2_add_sub_w_range521w(0);
wire_w_lg_w_exp_res_max_w_range545w546w(0) <= wire_w_exp_res_max_w_range545w(0) AND wire_w_exp_adjustment2_add_sub_w_range524w(0);
wire_w_lg_w_exp_res_max_w_range547w548w(0) <= wire_w_exp_res_max_w_range547w(0) AND wire_w_exp_adjustment2_add_sub_w_range527w(0);
wire_w_lg_w_exp_res_max_w_range549w550w(0) <= wire_w_exp_res_max_w_range549w(0) AND wire_w_exp_adjustment2_add_sub_w_range530w(0);
wire_w_lg_w_exp_res_max_w_range551w552w(0) <= wire_w_exp_res_max_w_range551w(0) AND wire_w_exp_adjustment2_add_sub_w_range533w(0);
wire_w_lg_w_exp_res_max_w_range553w554w(0) <= wire_w_exp_res_max_w_range553w(0) AND wire_w_exp_adjustment2_add_sub_w_range536w(0);
wire_w_lg_w_exp_res_max_w_range555w561w(0) <= wire_w_exp_res_max_w_range555w(0) AND wire_w_lg_w_exp_adjustment2_add_sub_w_range511w560w(0);
wire_w_lg_w_exp_rounded_res_max_w_range601w604w(0) <= wire_w_exp_rounded_res_max_w_range601w(0) AND wire_w_exp_rounded_res_w_range603w(0);
wire_w_lg_w_exp_rounded_res_max_w_range605w607w(0) <= wire_w_exp_rounded_res_max_w_range605w(0) AND wire_w_exp_rounded_res_w_range606w(0);
wire_w_lg_w_exp_rounded_res_max_w_range608w610w(0) <= wire_w_exp_rounded_res_max_w_range608w(0) AND wire_w_exp_rounded_res_w_range609w(0);
wire_w_lg_w_exp_rounded_res_max_w_range611w613w(0) <= wire_w_exp_rounded_res_max_w_range611w(0) AND wire_w_exp_rounded_res_w_range612w(0);
wire_w_lg_w_exp_rounded_res_max_w_range614w616w(0) <= wire_w_exp_rounded_res_max_w_range614w(0) AND wire_w_exp_rounded_res_w_range615w(0);
wire_w_lg_w_exp_rounded_res_max_w_range617w619w(0) <= wire_w_exp_rounded_res_max_w_range617w(0) AND wire_w_exp_rounded_res_w_range618w(0);
wire_w_lg_w_exp_rounded_res_max_w_range620w622w(0) <= wire_w_exp_rounded_res_max_w_range620w(0) AND wire_w_exp_rounded_res_w_range621w(0);
wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w391w(0) <= wire_w_man_add_sub_res_mag_dffe27_wo_range381w(0) AND wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range387w390w(0);
loop113 : FOR i IN 0 TO 1 GENERATE
wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w384w(i) <= wire_w_man_add_sub_res_mag_dffe27_wo_range381w(0) AND exp_adjust_by_add2(i);
END GENERATE loop113;
loop114 : FOR i IN 0 TO 25 GENERATE
wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w414w(i) <= wire_w_man_add_sub_res_mag_dffe27_wo_range381w(0) AND wire_w_man_add_sub_res_mag_dffe27_wo_range413w(i);
END GENERATE loop114;
loop115 : FOR i IN 0 TO 27 GENERATE
wire_w_lg_w_man_add_sub_w_range372w379w(i) <= wire_w_man_add_sub_w_range372w(0) AND man_2comp_res_w(i);
END GENERATE loop115;
loop116 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_man_res_rounding_add_sub_w_range585w589w(i) <= wire_w_man_res_rounding_add_sub_w_range585w(0) AND wire_w_man_res_rounding_add_sub_w_range588w(i);
END GENERATE loop116;
wire_w_lg_w_lg_force_zero_w634w635w(0) <= NOT wire_w_lg_force_zero_w634w(0);
wire_w_lg_add_sub_dffe25_wo491w(0) <= NOT add_sub_dffe25_wo;
wire_w_lg_add_sub_w2342w(0) <= NOT add_sub_w2;
wire_w_lg_denormal_result_w558w(0) <= NOT denormal_result_w;
wire_w_lg_exp_amb_mux_dffe15_wo316w(0) <= NOT exp_amb_mux_dffe15_wo;
wire_w_lg_exp_amb_mux_w275w(0) <= NOT exp_amb_mux_w;
wire_w_lg_force_infinity_w629w(0) <= NOT force_infinity_w;
wire_w_lg_force_nan_w630w(0) <= NOT force_nan_w;
wire_w_lg_force_zero_w628w(0) <= NOT force_zero_w;
wire_w_lg_input_dataa_denormal_dffe11_wo233w(0) <= NOT input_dataa_denormal_dffe11_wo;
wire_w_lg_input_dataa_infinite_dffe11_wo246w(0) <= NOT input_dataa_infinite_dffe11_wo;
wire_w_lg_input_dataa_zero_dffe11_wo245w(0) <= NOT input_dataa_zero_dffe11_wo;
wire_w_lg_input_datab_denormal_dffe11_wo252w(0) <= NOT input_datab_denormal_dffe11_wo;
wire_w_lg_input_datab_infinite_dffe11_wo265w(0) <= NOT input_datab_infinite_dffe11_wo;
wire_w_lg_input_datab_infinite_dffe15_wo337w(0) <= NOT input_datab_infinite_dffe15_wo;
wire_w_lg_input_datab_zero_dffe11_wo264w(0) <= NOT input_datab_zero_dffe11_wo;
wire_w_lg_man_res_is_not_zero_dffe4_wo627w(0) <= NOT man_res_is_not_zero_dffe4_wo;
wire_w_lg_man_res_not_zero_dffe26_wo503w(0) <= NOT man_res_not_zero_dffe26_wo;
wire_w_lg_need_complement_dffe22_wo373w(0) <= NOT need_complement_dffe22_wo;
wire_w_lg_sticky_bit_dffe1_wo343w(0) <= NOT sticky_bit_dffe1_wo;
wire_w_lg_w_exp_adjustment2_add_sub_w_range511w560w(0) <= NOT wire_w_exp_adjustment2_add_sub_w_range511w(0);
wire_w_lg_w_exp_diff_abs_exceed_max_w_range289w291w(0) <= NOT wire_w_exp_diff_abs_exceed_max_w_range289w(0);
wire_w_lg_w_man_a_not_zero_w_range215w219w(0) <= NOT wire_w_man_a_not_zero_w_range215w(0);
wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range387w390w(0) <= NOT wire_w_man_add_sub_res_mag_dffe27_wo_range387w(0);
wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) <= NOT wire_w_man_add_sub_res_mag_dffe27_wo_range381w(0);
wire_w_lg_w_man_add_sub_w_range372w375w(0) <= NOT wire_w_man_add_sub_w_range372w(0);
wire_w_lg_w_man_b_not_zero_w_range218w225w(0) <= NOT wire_w_man_b_not_zero_w_range218w(0);
wire_w_lg_w_man_res_rounding_add_sub_w_range585w586w(0) <= NOT wire_w_man_res_rounding_add_sub_w_range585w(0);
loop117 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_w_lg_force_zero_w634w637w638w(i) <= wire_w_lg_w_lg_force_zero_w634w637w(i) OR wire_w_lg_w_lg_w_lg_force_zero_w634w635w636w(i);
END GENERATE loop117;
loop118 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_w_lg_force_zero_w634w646w647w(i) <= wire_w_lg_w_lg_force_zero_w634w646w(i) OR wire_w_lg_w_lg_w_lg_force_zero_w634w635w645w(i);
END GENERATE loop118;
loop119 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_force_infinity_w640w641w(i) <= wire_w_lg_force_infinity_w640w(i) OR wire_w_lg_w_lg_force_infinity_w629w639w(i);
END GENERATE loop119;
loop120 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_force_infinity_w649w650w(i) <= wire_w_lg_force_infinity_w649w(i) OR wire_w_lg_w_lg_force_infinity_w629w648w(i);
END GENERATE loop120;
wire_w_lg_force_zero_w634w(0) <= force_zero_w OR denormal_flag_w;
wire_w_lg_sticky_bit_dffe27_wo402w(0) <= sticky_bit_dffe27_wo OR wire_w_man_add_sub_res_mag_dffe27_wo_range396w(0);
wire_w_lg_w_dataa_range141w142w(0) <= wire_w_dataa_range141w(0) OR wire_w_man_a_not_zero_w_range137w(0);
wire_w_lg_w_dataa_range147w148w(0) <= wire_w_dataa_range147w(0) OR wire_w_man_a_not_zero_w_range143w(0);
wire_w_lg_w_dataa_range153w154w(0) <= wire_w_dataa_range153w(0) OR wire_w_man_a_not_zero_w_range149w(0);
wire_w_lg_w_dataa_range159w160w(0) <= wire_w_dataa_range159w(0) OR wire_w_man_a_not_zero_w_range155w(0);
wire_w_lg_w_dataa_range165w166w(0) <= wire_w_dataa_range165w(0) OR wire_w_man_a_not_zero_w_range161w(0);
wire_w_lg_w_dataa_range171w172w(0) <= wire_w_dataa_range171w(0) OR wire_w_man_a_not_zero_w_range167w(0);
wire_w_lg_w_dataa_range177w178w(0) <= wire_w_dataa_range177w(0) OR wire_w_man_a_not_zero_w_range173w(0);
wire_w_lg_w_dataa_range183w184w(0) <= wire_w_dataa_range183w(0) OR wire_w_man_a_not_zero_w_range179w(0);
wire_w_lg_w_dataa_range189w190w(0) <= wire_w_dataa_range189w(0) OR wire_w_man_a_not_zero_w_range185w(0);
wire_w_lg_w_dataa_range195w196w(0) <= wire_w_dataa_range195w(0) OR wire_w_man_a_not_zero_w_range191w(0);
wire_w_lg_w_dataa_range87w88w(0) <= wire_w_dataa_range87w(0) OR wire_w_man_a_not_zero_w_range12w(0);
wire_w_lg_w_dataa_range201w202w(0) <= wire_w_dataa_range201w(0) OR wire_w_man_a_not_zero_w_range197w(0);
wire_w_lg_w_dataa_range207w208w(0) <= wire_w_dataa_range207w(0) OR wire_w_man_a_not_zero_w_range203w(0);
wire_w_lg_w_dataa_range213w214w(0) <= wire_w_dataa_range213w(0) OR wire_w_man_a_not_zero_w_range209w(0);
wire_w_lg_w_dataa_range17w18w(0) <= wire_w_dataa_range17w(0) OR wire_w_exp_a_not_zero_w_range2w(0);
wire_w_lg_w_dataa_range27w28w(0) <= wire_w_dataa_range27w(0) OR wire_w_exp_a_not_zero_w_range19w(0);
wire_w_lg_w_dataa_range37w38w(0) <= wire_w_dataa_range37w(0) OR wire_w_exp_a_not_zero_w_range29w(0);
wire_w_lg_w_dataa_range47w48w(0) <= wire_w_dataa_range47w(0) OR wire_w_exp_a_not_zero_w_range39w(0);
wire_w_lg_w_dataa_range57w58w(0) <= wire_w_dataa_range57w(0) OR wire_w_exp_a_not_zero_w_range49w(0);
wire_w_lg_w_dataa_range67w68w(0) <= wire_w_dataa_range67w(0) OR wire_w_exp_a_not_zero_w_range59w(0);
wire_w_lg_w_dataa_range93w94w(0) <= wire_w_dataa_range93w(0) OR wire_w_man_a_not_zero_w_range89w(0);
wire_w_lg_w_dataa_range77w78w(0) <= wire_w_dataa_range77w(0) OR wire_w_exp_a_not_zero_w_range69w(0);
wire_w_lg_w_dataa_range99w100w(0) <= wire_w_dataa_range99w(0) OR wire_w_man_a_not_zero_w_range95w(0);
wire_w_lg_w_dataa_range105w106w(0) <= wire_w_dataa_range105w(0) OR wire_w_man_a_not_zero_w_range101w(0);
wire_w_lg_w_dataa_range111w112w(0) <= wire_w_dataa_range111w(0) OR wire_w_man_a_not_zero_w_range107w(0);
wire_w_lg_w_dataa_range117w118w(0) <= wire_w_dataa_range117w(0) OR wire_w_man_a_not_zero_w_range113w(0);
wire_w_lg_w_dataa_range123w124w(0) <= wire_w_dataa_range123w(0) OR wire_w_man_a_not_zero_w_range119w(0);
wire_w_lg_w_dataa_range129w130w(0) <= wire_w_dataa_range129w(0) OR wire_w_man_a_not_zero_w_range125w(0);
wire_w_lg_w_dataa_range135w136w(0) <= wire_w_dataa_range135w(0) OR wire_w_man_a_not_zero_w_range131w(0);
wire_w_lg_w_datab_range144w145w(0) <= wire_w_datab_range144w(0) OR wire_w_man_b_not_zero_w_range140w(0);
wire_w_lg_w_datab_range150w151w(0) <= wire_w_datab_range150w(0) OR wire_w_man_b_not_zero_w_range146w(0);
wire_w_lg_w_datab_range156w157w(0) <= wire_w_datab_range156w(0) OR wire_w_man_b_not_zero_w_range152w(0);
wire_w_lg_w_datab_range162w163w(0) <= wire_w_datab_range162w(0) OR wire_w_man_b_not_zero_w_range158w(0);
wire_w_lg_w_datab_range168w169w(0) <= wire_w_datab_range168w(0) OR wire_w_man_b_not_zero_w_range164w(0);
wire_w_lg_w_datab_range174w175w(0) <= wire_w_datab_range174w(0) OR wire_w_man_b_not_zero_w_range170w(0);
wire_w_lg_w_datab_range180w181w(0) <= wire_w_datab_range180w(0) OR wire_w_man_b_not_zero_w_range176w(0);
wire_w_lg_w_datab_range186w187w(0) <= wire_w_datab_range186w(0) OR wire_w_man_b_not_zero_w_range182w(0);
wire_w_lg_w_datab_range192w193w(0) <= wire_w_datab_range192w(0) OR wire_w_man_b_not_zero_w_range188w(0);
wire_w_lg_w_datab_range198w199w(0) <= wire_w_datab_range198w(0) OR wire_w_man_b_not_zero_w_range194w(0);
wire_w_lg_w_datab_range90w91w(0) <= wire_w_datab_range90w(0) OR wire_w_man_b_not_zero_w_range15w(0);
wire_w_lg_w_datab_range204w205w(0) <= wire_w_datab_range204w(0) OR wire_w_man_b_not_zero_w_range200w(0);
wire_w_lg_w_datab_range210w211w(0) <= wire_w_datab_range210w(0) OR wire_w_man_b_not_zero_w_range206w(0);
wire_w_lg_w_datab_range216w217w(0) <= wire_w_datab_range216w(0) OR wire_w_man_b_not_zero_w_range212w(0);
wire_w_lg_w_datab_range20w21w(0) <= wire_w_datab_range20w(0) OR wire_w_exp_b_not_zero_w_range5w(0);
wire_w_lg_w_datab_range30w31w(0) <= wire_w_datab_range30w(0) OR wire_w_exp_b_not_zero_w_range22w(0);
wire_w_lg_w_datab_range40w41w(0) <= wire_w_datab_range40w(0) OR wire_w_exp_b_not_zero_w_range32w(0);
wire_w_lg_w_datab_range50w51w(0) <= wire_w_datab_range50w(0) OR wire_w_exp_b_not_zero_w_range42w(0);
wire_w_lg_w_datab_range60w61w(0) <= wire_w_datab_range60w(0) OR wire_w_exp_b_not_zero_w_range52w(0);
wire_w_lg_w_datab_range70w71w(0) <= wire_w_datab_range70w(0) OR wire_w_exp_b_not_zero_w_range62w(0);
wire_w_lg_w_datab_range96w97w(0) <= wire_w_datab_range96w(0) OR wire_w_man_b_not_zero_w_range92w(0);
wire_w_lg_w_datab_range80w81w(0) <= wire_w_datab_range80w(0) OR wire_w_exp_b_not_zero_w_range72w(0);
wire_w_lg_w_datab_range102w103w(0) <= wire_w_datab_range102w(0) OR wire_w_man_b_not_zero_w_range98w(0);
wire_w_lg_w_datab_range108w109w(0) <= wire_w_datab_range108w(0) OR wire_w_man_b_not_zero_w_range104w(0);
wire_w_lg_w_datab_range114w115w(0) <= wire_w_datab_range114w(0) OR wire_w_man_b_not_zero_w_range110w(0);
wire_w_lg_w_datab_range120w121w(0) <= wire_w_datab_range120w(0) OR wire_w_man_b_not_zero_w_range116w(0);
wire_w_lg_w_datab_range126w127w(0) <= wire_w_datab_range126w(0) OR wire_w_man_b_not_zero_w_range122w(0);
wire_w_lg_w_datab_range132w133w(0) <= wire_w_datab_range132w(0) OR wire_w_man_b_not_zero_w_range128w(0);
wire_w_lg_w_datab_range138w139w(0) <= wire_w_datab_range138w(0) OR wire_w_man_b_not_zero_w_range134w(0);
wire_w_lg_w_exp_diff_abs_exceed_max_w_range282w285w(0) <= wire_w_exp_diff_abs_exceed_max_w_range282w(0) OR wire_w_exp_diff_abs_w_range284w(0);
wire_w_lg_w_exp_diff_abs_exceed_max_w_range286w288w(0) <= wire_w_exp_diff_abs_exceed_max_w_range286w(0) OR wire_w_exp_diff_abs_w_range287w(0);
wire_w_lg_w_exp_res_not_zero_w_range516w519w(0) <= wire_w_exp_res_not_zero_w_range516w(0) OR wire_w_exp_adjustment2_add_sub_w_range518w(0);
wire_w_lg_w_exp_res_not_zero_w_range520w522w(0) <= wire_w_exp_res_not_zero_w_range520w(0) OR wire_w_exp_adjustment2_add_sub_w_range521w(0);
wire_w_lg_w_exp_res_not_zero_w_range523w525w(0) <= wire_w_exp_res_not_zero_w_range523w(0) OR wire_w_exp_adjustment2_add_sub_w_range524w(0);
wire_w_lg_w_exp_res_not_zero_w_range526w528w(0) <= wire_w_exp_res_not_zero_w_range526w(0) OR wire_w_exp_adjustment2_add_sub_w_range527w(0);
wire_w_lg_w_exp_res_not_zero_w_range529w531w(0) <= wire_w_exp_res_not_zero_w_range529w(0) OR wire_w_exp_adjustment2_add_sub_w_range530w(0);
wire_w_lg_w_exp_res_not_zero_w_range532w534w(0) <= wire_w_exp_res_not_zero_w_range532w(0) OR wire_w_exp_adjustment2_add_sub_w_range533w(0);
wire_w_lg_w_exp_res_not_zero_w_range535w537w(0) <= wire_w_exp_res_not_zero_w_range535w(0) OR wire_w_exp_adjustment2_add_sub_w_range536w(0);
wire_w_lg_w_exp_res_not_zero_w_range538w539w(0) <= wire_w_exp_res_not_zero_w_range538w(0) OR wire_w_exp_adjustment2_add_sub_w_range511w(0);
wire_w_lg_w_man_res_not_zero_w2_range417w420w(0) <= wire_w_man_res_not_zero_w2_range417w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range419w(0);
wire_w_lg_w_man_res_not_zero_w2_range448w450w(0) <= wire_w_man_res_not_zero_w2_range448w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range449w(0);
wire_w_lg_w_man_res_not_zero_w2_range451w453w(0) <= wire_w_man_res_not_zero_w2_range451w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range452w(0);
wire_w_lg_w_man_res_not_zero_w2_range454w456w(0) <= wire_w_man_res_not_zero_w2_range454w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range455w(0);
wire_w_lg_w_man_res_not_zero_w2_range457w459w(0) <= wire_w_man_res_not_zero_w2_range457w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range458w(0);
wire_w_lg_w_man_res_not_zero_w2_range460w462w(0) <= wire_w_man_res_not_zero_w2_range460w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range461w(0);
wire_w_lg_w_man_res_not_zero_w2_range463w465w(0) <= wire_w_man_res_not_zero_w2_range463w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range464w(0);
wire_w_lg_w_man_res_not_zero_w2_range466w468w(0) <= wire_w_man_res_not_zero_w2_range466w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range467w(0);
wire_w_lg_w_man_res_not_zero_w2_range469w471w(0) <= wire_w_man_res_not_zero_w2_range469w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range470w(0);
wire_w_lg_w_man_res_not_zero_w2_range472w474w(0) <= wire_w_man_res_not_zero_w2_range472w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range473w(0);
wire_w_lg_w_man_res_not_zero_w2_range475w477w(0) <= wire_w_man_res_not_zero_w2_range475w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range476w(0);
wire_w_lg_w_man_res_not_zero_w2_range421w423w(0) <= wire_w_man_res_not_zero_w2_range421w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range422w(0);
wire_w_lg_w_man_res_not_zero_w2_range478w480w(0) <= wire_w_man_res_not_zero_w2_range478w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range479w(0);
wire_w_lg_w_man_res_not_zero_w2_range481w483w(0) <= wire_w_man_res_not_zero_w2_range481w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range482w(0);
wire_w_lg_w_man_res_not_zero_w2_range484w486w(0) <= wire_w_man_res_not_zero_w2_range484w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range485w(0);
wire_w_lg_w_man_res_not_zero_w2_range487w489w(0) <= wire_w_man_res_not_zero_w2_range487w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range488w(0);
wire_w_lg_w_man_res_not_zero_w2_range424w426w(0) <= wire_w_man_res_not_zero_w2_range424w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range425w(0);
wire_w_lg_w_man_res_not_zero_w2_range427w429w(0) <= wire_w_man_res_not_zero_w2_range427w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range428w(0);
wire_w_lg_w_man_res_not_zero_w2_range430w432w(0) <= wire_w_man_res_not_zero_w2_range430w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range431w(0);
wire_w_lg_w_man_res_not_zero_w2_range433w435w(0) <= wire_w_man_res_not_zero_w2_range433w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range434w(0);
wire_w_lg_w_man_res_not_zero_w2_range436w438w(0) <= wire_w_man_res_not_zero_w2_range436w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range437w(0);
wire_w_lg_w_man_res_not_zero_w2_range439w441w(0) <= wire_w_man_res_not_zero_w2_range439w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range440w(0);
wire_w_lg_w_man_res_not_zero_w2_range442w444w(0) <= wire_w_man_res_not_zero_w2_range442w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range443w(0);
wire_w_lg_w_man_res_not_zero_w2_range445w447w(0) <= wire_w_man_res_not_zero_w2_range445w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range446w(0);
aclr <= '0';
add_sub_dffe25_wi <= add_sub_w2;
add_sub_dffe25_wo <= add_sub_dffe25_wi;
add_sub_w2 <= (NOT (dataa_sign_dffe1_wo XOR datab_sign_dffe1_wo));
adder_upper_w <= man_intermediate_res_w(25 DOWNTO 13);
aligned_dataa_exp_dffe12_wi <= aligned_dataa_exp_w;
aligned_dataa_exp_dffe12_wo <= aligned_dataa_exp_dffe12_wi;
aligned_dataa_exp_dffe13_wi <= aligned_dataa_exp_dffe12_wo;
aligned_dataa_exp_dffe13_wo <= aligned_dataa_exp_dffe13_wi;
aligned_dataa_exp_dffe14_wi <= aligned_dataa_exp_dffe13_wo;
aligned_dataa_exp_dffe14_wo <= aligned_dataa_exp_dffe14_wi;
aligned_dataa_exp_dffe15_wi <= aligned_dataa_exp_dffe14_wo;
aligned_dataa_exp_dffe15_wo <= aligned_dataa_exp_dffe15_wi;
aligned_dataa_exp_w <= ( "0" & wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w234w);
aligned_dataa_man_dffe12_wi <= aligned_dataa_man_w(25 DOWNTO 2);
aligned_dataa_man_dffe12_wo <= aligned_dataa_man_dffe12_wi;
aligned_dataa_man_dffe13_wi <= aligned_dataa_man_dffe12_wo;
aligned_dataa_man_dffe13_wo <= aligned_dataa_man_dffe13_wi;
aligned_dataa_man_dffe14_wi <= aligned_dataa_man_dffe13_wo;
aligned_dataa_man_dffe14_wo <= aligned_dataa_man_dffe14_wi;
aligned_dataa_man_dffe15_w <= ( aligned_dataa_man_dffe15_wo & "00");
aligned_dataa_man_dffe15_wi <= aligned_dataa_man_dffe14_wo;
aligned_dataa_man_dffe15_wo <= aligned_dataa_man_dffe15_wi;
aligned_dataa_man_w <= ( wire_w248w & wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w243w & "00");
aligned_dataa_sign_dffe12_wi <= aligned_dataa_sign_w;
aligned_dataa_sign_dffe12_wo <= aligned_dataa_sign_dffe12_wi;
aligned_dataa_sign_dffe13_wi <= aligned_dataa_sign_dffe12_wo;
aligned_dataa_sign_dffe13_wo <= aligned_dataa_sign_dffe13_wi;
aligned_dataa_sign_dffe14_wi <= aligned_dataa_sign_dffe13_wo;
aligned_dataa_sign_dffe14_wo <= aligned_dataa_sign_dffe14_wi;
aligned_dataa_sign_dffe15_wi <= aligned_dataa_sign_dffe14_wo;
aligned_dataa_sign_dffe15_wo <= aligned_dataa_sign_dffe15_wi;
aligned_dataa_sign_w <= dataa_dffe11_wo(31);
aligned_datab_exp_dffe12_wi <= aligned_datab_exp_w;
aligned_datab_exp_dffe12_wo <= aligned_datab_exp_dffe12_wi;
aligned_datab_exp_dffe13_wi <= aligned_datab_exp_dffe12_wo;
aligned_datab_exp_dffe13_wo <= aligned_datab_exp_dffe13_wi;
aligned_datab_exp_dffe14_wi <= aligned_datab_exp_dffe13_wo;
aligned_datab_exp_dffe14_wo <= aligned_datab_exp_dffe14_wi;
aligned_datab_exp_dffe15_wi <= aligned_datab_exp_dffe14_wo;
aligned_datab_exp_dffe15_wo <= aligned_datab_exp_dffe15_wi;
aligned_datab_exp_w <= ( "0" & wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w253w);
aligned_datab_man_dffe12_wi <= aligned_datab_man_w(25 DOWNTO 2);
aligned_datab_man_dffe12_wo <= aligned_datab_man_dffe12_wi;
aligned_datab_man_dffe13_wi <= aligned_datab_man_dffe12_wo;
aligned_datab_man_dffe13_wo <= aligned_datab_man_dffe13_wi;
aligned_datab_man_dffe14_wi <= aligned_datab_man_dffe13_wo;
aligned_datab_man_dffe14_wo <= aligned_datab_man_dffe14_wi;
aligned_datab_man_dffe15_w <= ( aligned_datab_man_dffe15_wo & "00");
aligned_datab_man_dffe15_wi <= aligned_datab_man_dffe14_wo;
aligned_datab_man_dffe15_wo <= aligned_datab_man_dffe15_wi;
aligned_datab_man_w <= ( wire_w267w & wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w262w & "00");
aligned_datab_sign_dffe12_wi <= aligned_datab_sign_w;
aligned_datab_sign_dffe12_wo <= aligned_datab_sign_dffe12_wi;
aligned_datab_sign_dffe13_wi <= aligned_datab_sign_dffe12_wo;
aligned_datab_sign_dffe13_wo <= aligned_datab_sign_dffe13_wi;
aligned_datab_sign_dffe14_wi <= aligned_datab_sign_dffe13_wo;
aligned_datab_sign_dffe14_wo <= aligned_datab_sign_dffe14_wi;
aligned_datab_sign_dffe15_wi <= aligned_datab_sign_dffe14_wo;
aligned_datab_sign_dffe15_wo <= aligned_datab_sign_dffe15_wi;
aligned_datab_sign_w <= datab_dffe11_wo(31);
borrow_w <= (wire_w_lg_sticky_bit_dffe1_wo343w(0) AND wire_w_lg_add_sub_w2342w(0));
both_inputs_are_infinite_dffe1_wi <= (input_dataa_infinite_dffe15_wo AND input_datab_infinite_dffe15_wo);
both_inputs_are_infinite_dffe1_wo <= both_inputs_are_infinite_dffe1;
both_inputs_are_infinite_dffe25_wi <= both_inputs_are_infinite_dffe1_wo;
both_inputs_are_infinite_dffe25_wo <= both_inputs_are_infinite_dffe25_wi;
data_exp_dffe1_wi <= (wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w317w OR wire_w_lg_exp_amb_mux_dffe15_wo314w);
data_exp_dffe1_wo <= data_exp_dffe1;
dataa_dffe11_wi <= dataa;
dataa_dffe11_wo <= dataa_dffe11_wi;
dataa_man_dffe1_wi <= (wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w324w OR wire_w_lg_exp_amb_mux_dffe15_wo323w);
dataa_man_dffe1_wo <= dataa_man_dffe1;
dataa_sign_dffe1_wi <= aligned_dataa_sign_dffe15_wo;
dataa_sign_dffe1_wo <= dataa_sign_dffe1;
dataa_sign_dffe25_wi <= dataa_sign_dffe1_wo;
dataa_sign_dffe25_wo <= dataa_sign_dffe25_wi;
datab_dffe11_wi <= datab;
datab_dffe11_wo <= datab_dffe11_wi;
datab_man_dffe1_wi <= (wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w331w OR wire_w_lg_exp_amb_mux_dffe15_wo330w);
datab_man_dffe1_wo <= datab_man_dffe1;
datab_sign_dffe1_wi <= aligned_datab_sign_dffe15_wo;
datab_sign_dffe1_wo <= datab_sign_dffe1;
denormal_flag_w <= (((wire_w_lg_force_nan_w630w(0) AND wire_w_lg_force_infinity_w629w(0)) AND wire_w_lg_force_zero_w628w(0)) AND denormal_res_dffe4_wo);
denormal_res_dffe32_wi <= denormal_result_w;
denormal_res_dffe32_wo <= denormal_res_dffe32_wi;
denormal_res_dffe33_wi <= denormal_res_dffe32_wo;
denormal_res_dffe33_wo <= denormal_res_dffe33_wi;
denormal_res_dffe3_wi <= denormal_res_dffe33_wo;
denormal_res_dffe3_wo <= denormal_res_dffe3;
denormal_res_dffe41_wi <= denormal_res_dffe42_wo;
denormal_res_dffe41_wo <= denormal_res_dffe41_wi;
denormal_res_dffe42_wi <= denormal_res_dffe3_wo;
denormal_res_dffe42_wo <= denormal_res_dffe42_wi;
denormal_res_dffe4_wi <= denormal_res_dffe41_wo;
denormal_res_dffe4_wo <= denormal_res_dffe4;
denormal_result_w <= ((NOT exp_res_not_zero_w(8)) OR exp_adjustment2_add_sub_w(8));
exp_a_all_one_w <= ( wire_w_lg_w_dataa_range77w83w & wire_w_lg_w_dataa_range67w73w & wire_w_lg_w_dataa_range57w63w & wire_w_lg_w_dataa_range47w53w & wire_w_lg_w_dataa_range37w43w & wire_w_lg_w_dataa_range27w33w & wire_w_lg_w_dataa_range17w23w & dataa(23));
exp_a_not_zero_w <= ( wire_w_lg_w_dataa_range77w78w & wire_w_lg_w_dataa_range67w68w & wire_w_lg_w_dataa_range57w58w & wire_w_lg_w_dataa_range47w48w & wire_w_lg_w_dataa_range37w38w & wire_w_lg_w_dataa_range27w28w & wire_w_lg_w_dataa_range17w18w & dataa(23));
exp_adj_0pads <= (OTHERS => '0');
exp_adj_dffe21_wi <= (wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w384w OR wire_w383w);
exp_adj_dffe21_wo <= exp_adj_dffe21;
exp_adj_dffe23_wi <= exp_adj_dffe21_wo;
exp_adj_dffe23_wo <= exp_adj_dffe23_wi;
exp_adj_dffe26_wi <= exp_adj_dffe23_wo;
exp_adj_dffe26_wo <= exp_adj_dffe26_wi;
exp_adjust_by_add1 <= "01";
exp_adjust_by_add2 <= "10";
exp_adjustment2_add_sub_dataa_w <= exp_value;
exp_adjustment2_add_sub_datab_w <= exp_adjustment_add_sub_w;
exp_adjustment2_add_sub_w <= wire_add_sub5_result;
exp_adjustment_add_sub_dataa_w <= ( priority_encoder_1pads_w & wire_leading_zeroes_cnt_q);
exp_adjustment_add_sub_datab_w <= ( exp_adj_0pads & exp_adj_dffe26_wo);
exp_adjustment_add_sub_w <= wire_add_sub4_result;
exp_all_ones_w <= (OTHERS => '1');
exp_all_zeros_w <= (OTHERS => '0');
exp_amb_mux_dffe13_wi <= exp_amb_mux_w;
exp_amb_mux_dffe13_wo <= exp_amb_mux_dffe13_wi;
exp_amb_mux_dffe14_wi <= exp_amb_mux_dffe13_wo;
exp_amb_mux_dffe14_wo <= exp_amb_mux_dffe14_wi;
exp_amb_mux_dffe15_wi <= exp_amb_mux_dffe14_wo;
exp_amb_mux_dffe15_wo <= exp_amb_mux_dffe15_wi;
exp_amb_mux_w <= exp_amb_w(8);
exp_amb_w <= wire_add_sub1_result;
exp_b_all_one_w <= ( wire_w_lg_w_datab_range80w85w & wire_w_lg_w_datab_range70w75w & wire_w_lg_w_datab_range60w65w & wire_w_lg_w_datab_range50w55w & wire_w_lg_w_datab_range40w45w & wire_w_lg_w_datab_range30w35w & wire_w_lg_w_datab_range20w25w & datab(23));
exp_b_not_zero_w <= ( wire_w_lg_w_datab_range80w81w & wire_w_lg_w_datab_range70w71w & wire_w_lg_w_datab_range60w61w & wire_w_lg_w_datab_range50w51w & wire_w_lg_w_datab_range40w41w & wire_w_lg_w_datab_range30w31w & wire_w_lg_w_datab_range20w21w & datab(23));
exp_bma_w <= wire_add_sub2_result;
exp_diff_abs_exceed_max_w <= ( wire_w_lg_w_exp_diff_abs_exceed_max_w_range286w288w & wire_w_lg_w_exp_diff_abs_exceed_max_w_range282w285w & exp_diff_abs_w(5));
exp_diff_abs_max_w <= (OTHERS => '1');
exp_diff_abs_w <= (wire_w_lg_w_lg_exp_amb_mux_w275w276w OR wire_w_lg_exp_amb_mux_w273w);
exp_intermediate_res_dffe41_wi <= exp_intermediate_res_dffe42_wo;
exp_intermediate_res_dffe41_wo <= exp_intermediate_res_dffe41_wi;
exp_intermediate_res_dffe42_wi <= exp_intermediate_res_w;
exp_intermediate_res_dffe42_wo <= exp_intermediate_res_dffe42_wi;
exp_intermediate_res_w <= exp_res_dffe3_wo;
exp_out_dffe5_wi <= (wire_w_lg_force_nan_w643w OR wire_w_lg_w_lg_force_nan_w630w642w);
exp_out_dffe5_wo <= exp_out_dffe5;
exp_res_dffe21_wi <= exp_res_dffe27_wo;
exp_res_dffe21_wo <= exp_res_dffe21;
exp_res_dffe22_wi <= exp_res_dffe2_wo;
exp_res_dffe22_wo <= exp_res_dffe22_wi;
exp_res_dffe23_wi <= exp_res_dffe21_wo;
exp_res_dffe23_wo <= exp_res_dffe23_wi;
exp_res_dffe25_wi <= data_exp_dffe1_wo;
exp_res_dffe25_wo <= exp_res_dffe25_wi;
exp_res_dffe26_wi <= exp_res_dffe23_wo;
exp_res_dffe26_wo <= exp_res_dffe26_wi;
exp_res_dffe27_wi <= exp_res_dffe22_wo;
exp_res_dffe27_wo <= exp_res_dffe27_wi;
exp_res_dffe2_wi <= exp_res_dffe25_wo;
exp_res_dffe2_wo <= exp_res_dffe2;
exp_res_dffe32_wi <= wire_w_lg_w_lg_denormal_result_w558w559w;
exp_res_dffe32_wo <= exp_res_dffe32_wi;
exp_res_dffe33_wi <= exp_res_dffe32_wo;
exp_res_dffe33_wo <= exp_res_dffe33_wi;
exp_res_dffe3_wi <= exp_res_dffe33_wo;
exp_res_dffe3_wo <= exp_res_dffe3;
exp_res_dffe4_wi <= exp_rounded_res_w;
exp_res_dffe4_wo <= exp_res_dffe4;
exp_res_max_w <= ( wire_w_lg_w_exp_res_max_w_range553w554w & wire_w_lg_w_exp_res_max_w_range551w552w & wire_w_lg_w_exp_res_max_w_range549w550w & wire_w_lg_w_exp_res_max_w_range547w548w & wire_w_lg_w_exp_res_max_w_range545w546w & wire_w_lg_w_exp_res_max_w_range543w544w & wire_w_lg_w_exp_res_max_w_range540w542w & exp_adjustment2_add_sub_w(0));
exp_res_not_zero_w <= ( wire_w_lg_w_exp_res_not_zero_w_range538w539w & wire_w_lg_w_exp_res_not_zero_w_range535w537w & wire_w_lg_w_exp_res_not_zero_w_range532w534w & wire_w_lg_w_exp_res_not_zero_w_range529w531w & wire_w_lg_w_exp_res_not_zero_w_range526w528w & wire_w_lg_w_exp_res_not_zero_w_range523w525w & wire_w_lg_w_exp_res_not_zero_w_range520w522w & wire_w_lg_w_exp_res_not_zero_w_range516w519w & exp_adjustment2_add_sub_w(0));
exp_res_rounding_adder_dataa_w <= ( "0" & exp_intermediate_res_dffe41_wo);
exp_res_rounding_adder_w <= wire_add_sub6_result;
exp_rounded_res_infinity_w <= exp_rounded_res_max_w(7);
exp_rounded_res_max_w <= ( wire_w_lg_w_exp_rounded_res_max_w_range620w622w & wire_w_lg_w_exp_rounded_res_max_w_range617w619w & wire_w_lg_w_exp_rounded_res_max_w_range614w616w & wire_w_lg_w_exp_rounded_res_max_w_range611w613w & wire_w_lg_w_exp_rounded_res_max_w_range608w610w & wire_w_lg_w_exp_rounded_res_max_w_range605w607w & wire_w_lg_w_exp_rounded_res_max_w_range601w604w & exp_rounded_res_w(0));
exp_rounded_res_w <= exp_res_rounding_adder_w(7 DOWNTO 0);
exp_rounding_adjustment_w <= ( "00000000" & man_res_rounding_add_sub_w(24));
exp_value <= ( "0" & exp_res_dffe26_wo);
force_infinity_w <= ((input_is_infinite_dffe4_wo OR rounded_res_infinity_dffe4_wo) OR infinite_res_dffe4_wo);
force_nan_w <= (infinity_magnitude_sub_dffe4_wo OR input_is_nan_dffe4_wo);
force_zero_w <= wire_w_lg_man_res_is_not_zero_dffe4_wo627w(0);
guard_bit_dffe3_wo <= man_res_w3(0);
infinite_output_sign_dffe1_wi <= (wire_w_lg_w_lg_input_datab_infinite_dffe15_wo337w338w(0) OR (input_datab_infinite_dffe15_wo AND aligned_datab_sign_dffe15_wo));
infinite_output_sign_dffe1_wo <= infinite_output_sign_dffe1;
infinite_output_sign_dffe21_wi <= infinite_output_sign_dffe27_wo;
infinite_output_sign_dffe21_wo <= infinite_output_sign_dffe21;
infinite_output_sign_dffe22_wi <= infinite_output_sign_dffe2_wo;
infinite_output_sign_dffe22_wo <= infinite_output_sign_dffe22_wi;
infinite_output_sign_dffe23_wi <= infinite_output_sign_dffe21_wo;
infinite_output_sign_dffe23_wo <= infinite_output_sign_dffe23_wi;
infinite_output_sign_dffe25_wi <= infinite_output_sign_dffe1_wo;
infinite_output_sign_dffe25_wo <= infinite_output_sign_dffe25_wi;
infinite_output_sign_dffe26_wi <= infinite_output_sign_dffe23_wo;
infinite_output_sign_dffe26_wo <= infinite_output_sign_dffe26_wi;
infinite_output_sign_dffe27_wi <= infinite_output_sign_dffe22_wo;
infinite_output_sign_dffe27_wo <= infinite_output_sign_dffe27_wi;
infinite_output_sign_dffe2_wi <= infinite_output_sign_dffe25_wo;
infinite_output_sign_dffe2_wo <= infinite_output_sign_dffe2;
infinite_output_sign_dffe31_wi <= infinite_output_sign_dffe26_wo;
infinite_output_sign_dffe31_wo <= infinite_output_sign_dffe31;
infinite_output_sign_dffe32_wi <= infinite_output_sign_dffe31_wo;
infinite_output_sign_dffe32_wo <= infinite_output_sign_dffe32_wi;
infinite_output_sign_dffe33_wi <= infinite_output_sign_dffe32_wo;
infinite_output_sign_dffe33_wo <= infinite_output_sign_dffe33_wi;
infinite_output_sign_dffe3_wi <= infinite_output_sign_dffe33_wo;
infinite_output_sign_dffe3_wo <= infinite_output_sign_dffe3;
infinite_output_sign_dffe41_wi <= infinite_output_sign_dffe42_wo;
infinite_output_sign_dffe41_wo <= infinite_output_sign_dffe41_wi;
infinite_output_sign_dffe42_wi <= infinite_output_sign_dffe3_wo;
infinite_output_sign_dffe42_wo <= infinite_output_sign_dffe42_wi;
infinite_output_sign_dffe4_wi <= infinite_output_sign_dffe41_wo;
infinite_output_sign_dffe4_wo <= infinite_output_sign_dffe4;
infinite_res_dff32_wi <= wire_w_lg_w_exp_res_max_w_range555w561w(0);
infinite_res_dff32_wo <= infinite_res_dff32_wi;
infinite_res_dff33_wi <= infinite_res_dff32_wo;
infinite_res_dff33_wo <= infinite_res_dff33_wi;
infinite_res_dffe3_wi <= infinite_res_dff33_wo;
infinite_res_dffe3_wo <= infinite_res_dffe3;
infinite_res_dffe41_wi <= infinite_res_dffe42_wo;
infinite_res_dffe41_wo <= infinite_res_dffe41_wi;
infinite_res_dffe42_wi <= infinite_res_dffe3_wo;
infinite_res_dffe42_wo <= infinite_res_dffe42_wi;
infinite_res_dffe4_wi <= infinite_res_dffe41_wo;
infinite_res_dffe4_wo <= infinite_res_dffe4;
infinity_magnitude_sub_dffe21_wi <= infinity_magnitude_sub_dffe27_wo;
infinity_magnitude_sub_dffe21_wo <= infinity_magnitude_sub_dffe21;
infinity_magnitude_sub_dffe22_wi <= infinity_magnitude_sub_dffe2_wo;
infinity_magnitude_sub_dffe22_wo <= infinity_magnitude_sub_dffe22_wi;
infinity_magnitude_sub_dffe23_wi <= infinity_magnitude_sub_dffe21_wo;
infinity_magnitude_sub_dffe23_wo <= infinity_magnitude_sub_dffe23_wi;
infinity_magnitude_sub_dffe26_wi <= infinity_magnitude_sub_dffe23_wo;
infinity_magnitude_sub_dffe26_wo <= infinity_magnitude_sub_dffe26_wi;
infinity_magnitude_sub_dffe27_wi <= infinity_magnitude_sub_dffe22_wo;
infinity_magnitude_sub_dffe27_wo <= infinity_magnitude_sub_dffe27_wi;
infinity_magnitude_sub_dffe2_wi <= (wire_w_lg_add_sub_dffe25_wo491w(0) AND both_inputs_are_infinite_dffe25_wo);
infinity_magnitude_sub_dffe2_wo <= infinity_magnitude_sub_dffe2;
infinity_magnitude_sub_dffe31_wi <= infinity_magnitude_sub_dffe26_wo;
infinity_magnitude_sub_dffe31_wo <= infinity_magnitude_sub_dffe31;
infinity_magnitude_sub_dffe32_wi <= infinity_magnitude_sub_dffe31_wo;
infinity_magnitude_sub_dffe32_wo <= infinity_magnitude_sub_dffe32_wi;
infinity_magnitude_sub_dffe33_wi <= infinity_magnitude_sub_dffe32_wo;
infinity_magnitude_sub_dffe33_wo <= infinity_magnitude_sub_dffe33_wi;
infinity_magnitude_sub_dffe3_wi <= infinity_magnitude_sub_dffe33_wo;
infinity_magnitude_sub_dffe3_wo <= infinity_magnitude_sub_dffe3;
infinity_magnitude_sub_dffe41_wi <= infinity_magnitude_sub_dffe42_wo;
infinity_magnitude_sub_dffe41_wo <= infinity_magnitude_sub_dffe41_wi;
infinity_magnitude_sub_dffe42_wi <= infinity_magnitude_sub_dffe3_wo;
infinity_magnitude_sub_dffe42_wo <= infinity_magnitude_sub_dffe42_wi;
infinity_magnitude_sub_dffe4_wi <= infinity_magnitude_sub_dffe41_wo;
infinity_magnitude_sub_dffe4_wo <= infinity_magnitude_sub_dffe4;
input_dataa_denormal_dffe11_wi <= input_dataa_denormal_w;
input_dataa_denormal_dffe11_wo <= input_dataa_denormal_dffe11_wi;
input_dataa_denormal_w <= ((NOT exp_a_not_zero_w(7)) AND man_a_not_zero_w(22));
input_dataa_infinite_dffe11_wi <= input_dataa_infinite_w;
input_dataa_infinite_dffe11_wo <= input_dataa_infinite_dffe11_wi;
input_dataa_infinite_dffe12_wi <= input_dataa_infinite_dffe11_wo;
input_dataa_infinite_dffe12_wo <= input_dataa_infinite_dffe12_wi;
input_dataa_infinite_dffe13_wi <= input_dataa_infinite_dffe12_wo;
input_dataa_infinite_dffe13_wo <= input_dataa_infinite_dffe13_wi;
input_dataa_infinite_dffe14_wi <= input_dataa_infinite_dffe13_wo;
input_dataa_infinite_dffe14_wo <= input_dataa_infinite_dffe14_wi;
input_dataa_infinite_dffe15_wi <= input_dataa_infinite_dffe14_wo;
input_dataa_infinite_dffe15_wo <= input_dataa_infinite_dffe15_wi;
input_dataa_infinite_w <= wire_w_lg_w_exp_a_all_one_w_range84w220w(0);
input_dataa_nan_dffe11_wi <= input_dataa_nan_w;
input_dataa_nan_dffe11_wo <= input_dataa_nan_dffe11_wi;
input_dataa_nan_dffe12_wi <= input_dataa_nan_dffe11_wo;
input_dataa_nan_dffe12_wo <= input_dataa_nan_dffe12_wi;
input_dataa_nan_w <= (exp_a_all_one_w(7) AND man_a_not_zero_w(22));
input_dataa_zero_dffe11_wi <= input_dataa_zero_w;
input_dataa_zero_dffe11_wo <= input_dataa_zero_dffe11_wi;
input_dataa_zero_w <= ((NOT exp_a_not_zero_w(7)) AND wire_w_lg_w_man_a_not_zero_w_range215w219w(0));
input_datab_denormal_dffe11_wi <= input_datab_denormal_w;
input_datab_denormal_dffe11_wo <= input_datab_denormal_dffe11_wi;
input_datab_denormal_w <= ((NOT exp_b_not_zero_w(7)) AND man_b_not_zero_w(22));
input_datab_infinite_dffe11_wi <= input_datab_infinite_w;
input_datab_infinite_dffe11_wo <= input_datab_infinite_dffe11_wi;
input_datab_infinite_dffe12_wi <= input_datab_infinite_dffe11_wo;
input_datab_infinite_dffe12_wo <= input_datab_infinite_dffe12_wi;
input_datab_infinite_dffe13_wi <= input_datab_infinite_dffe12_wo;
input_datab_infinite_dffe13_wo <= input_datab_infinite_dffe13_wi;
input_datab_infinite_dffe14_wi <= input_datab_infinite_dffe13_wo;
input_datab_infinite_dffe14_wo <= input_datab_infinite_dffe14_wi;
input_datab_infinite_dffe15_wi <= input_datab_infinite_dffe14_wo;
input_datab_infinite_dffe15_wo <= input_datab_infinite_dffe15_wi;
input_datab_infinite_w <= wire_w_lg_w_exp_b_all_one_w_range86w226w(0);
input_datab_nan_dffe11_wi <= input_datab_nan_w;
input_datab_nan_dffe11_wo <= input_datab_nan_dffe11_wi;
input_datab_nan_dffe12_wi <= input_datab_nan_dffe11_wo;
input_datab_nan_dffe12_wo <= input_datab_nan_dffe12_wi;
input_datab_nan_w <= (exp_b_all_one_w(7) AND man_b_not_zero_w(22));
input_datab_zero_dffe11_wi <= input_datab_zero_w;
input_datab_zero_dffe11_wo <= input_datab_zero_dffe11_wi;
input_datab_zero_w <= ((NOT exp_b_not_zero_w(7)) AND wire_w_lg_w_man_b_not_zero_w_range218w225w(0));
input_is_infinite_dffe1_wi <= (input_dataa_infinite_dffe15_wo OR input_datab_infinite_dffe15_wo);
input_is_infinite_dffe1_wo <= input_is_infinite_dffe1;
input_is_infinite_dffe21_wi <= input_is_infinite_dffe27_wo;
input_is_infinite_dffe21_wo <= input_is_infinite_dffe21;
input_is_infinite_dffe22_wi <= input_is_infinite_dffe2_wo;
input_is_infinite_dffe22_wo <= input_is_infinite_dffe22_wi;
input_is_infinite_dffe23_wi <= input_is_infinite_dffe21_wo;
input_is_infinite_dffe23_wo <= input_is_infinite_dffe23_wi;
input_is_infinite_dffe25_wi <= input_is_infinite_dffe1_wo;
input_is_infinite_dffe25_wo <= input_is_infinite_dffe25_wi;
input_is_infinite_dffe26_wi <= input_is_infinite_dffe23_wo;
input_is_infinite_dffe26_wo <= input_is_infinite_dffe26_wi;
input_is_infinite_dffe27_wi <= input_is_infinite_dffe22_wo;
input_is_infinite_dffe27_wo <= input_is_infinite_dffe27_wi;
input_is_infinite_dffe2_wi <= input_is_infinite_dffe25_wo;
input_is_infinite_dffe2_wo <= input_is_infinite_dffe2;
input_is_infinite_dffe31_wi <= input_is_infinite_dffe26_wo;
input_is_infinite_dffe31_wo <= input_is_infinite_dffe31;
input_is_infinite_dffe32_wi <= input_is_infinite_dffe31_wo;
input_is_infinite_dffe32_wo <= input_is_infinite_dffe32_wi;
input_is_infinite_dffe33_wi <= input_is_infinite_dffe32_wo;
input_is_infinite_dffe33_wo <= input_is_infinite_dffe33_wi;
input_is_infinite_dffe3_wi <= input_is_infinite_dffe33_wo;
input_is_infinite_dffe3_wo <= input_is_infinite_dffe3;
input_is_infinite_dffe41_wi <= input_is_infinite_dffe42_wo;
input_is_infinite_dffe41_wo <= input_is_infinite_dffe41_wi;
input_is_infinite_dffe42_wi <= input_is_infinite_dffe3_wo;
input_is_infinite_dffe42_wo <= input_is_infinite_dffe42_wi;
input_is_infinite_dffe4_wi <= input_is_infinite_dffe41_wo;
input_is_infinite_dffe4_wo <= input_is_infinite_dffe4;
input_is_nan_dffe13_wi <= (input_dataa_nan_dffe12_wo OR input_datab_nan_dffe12_wo);
input_is_nan_dffe13_wo <= input_is_nan_dffe13_wi;
input_is_nan_dffe14_wi <= input_is_nan_dffe13_wo;
input_is_nan_dffe14_wo <= input_is_nan_dffe14_wi;
input_is_nan_dffe15_wi <= input_is_nan_dffe14_wo;
input_is_nan_dffe15_wo <= input_is_nan_dffe15_wi;
input_is_nan_dffe1_wi <= input_is_nan_dffe15_wo;
input_is_nan_dffe1_wo <= input_is_nan_dffe1;
input_is_nan_dffe21_wi <= input_is_nan_dffe27_wo;
input_is_nan_dffe21_wo <= input_is_nan_dffe21;
input_is_nan_dffe22_wi <= input_is_nan_dffe2_wo;
input_is_nan_dffe22_wo <= input_is_nan_dffe22_wi;
input_is_nan_dffe23_wi <= input_is_nan_dffe21_wo;
input_is_nan_dffe23_wo <= input_is_nan_dffe23_wi;
input_is_nan_dffe25_wi <= input_is_nan_dffe1_wo;
input_is_nan_dffe25_wo <= input_is_nan_dffe25_wi;
input_is_nan_dffe26_wi <= input_is_nan_dffe23_wo;
input_is_nan_dffe26_wo <= input_is_nan_dffe26_wi;
input_is_nan_dffe27_wi <= input_is_nan_dffe22_wo;
input_is_nan_dffe27_wo <= input_is_nan_dffe27_wi;
input_is_nan_dffe2_wi <= input_is_nan_dffe25_wo;
input_is_nan_dffe2_wo <= input_is_nan_dffe2;
input_is_nan_dffe31_wi <= input_is_nan_dffe26_wo;
input_is_nan_dffe31_wo <= input_is_nan_dffe31;
input_is_nan_dffe32_wi <= input_is_nan_dffe31_wo;
input_is_nan_dffe32_wo <= input_is_nan_dffe32_wi;
input_is_nan_dffe33_wi <= input_is_nan_dffe32_wo;
input_is_nan_dffe33_wo <= input_is_nan_dffe33_wi;
input_is_nan_dffe3_wi <= input_is_nan_dffe33_wo;
input_is_nan_dffe3_wo <= input_is_nan_dffe3;
input_is_nan_dffe41_wi <= input_is_nan_dffe42_wo;
input_is_nan_dffe41_wo <= input_is_nan_dffe41_wi;
input_is_nan_dffe42_wi <= input_is_nan_dffe3_wo;
input_is_nan_dffe42_wo <= input_is_nan_dffe42_wi;
input_is_nan_dffe4_wi <= input_is_nan_dffe41_wo;
input_is_nan_dffe4_wo <= input_is_nan_dffe4;
man_2comp_res_dataa_w <= ( pos_sign_bit_ext & datab_man_dffe1_wo);
man_2comp_res_datab_w <= ( pos_sign_bit_ext & dataa_man_dffe1_wo);
man_2comp_res_w <= ( wire_man_2comp_res_lower_w_lg_w_lg_w_lg_cout367w368w369w & wire_man_2comp_res_lower_result);
man_a_not_zero_w <= ( wire_w_lg_w_dataa_range213w214w & wire_w_lg_w_dataa_range207w208w & wire_w_lg_w_dataa_range201w202w & wire_w_lg_w_dataa_range195w196w & wire_w_lg_w_dataa_range189w190w & wire_w_lg_w_dataa_range183w184w & wire_w_lg_w_dataa_range177w178w & wire_w_lg_w_dataa_range171w172w & wire_w_lg_w_dataa_range165w166w & wire_w_lg_w_dataa_range159w160w & wire_w_lg_w_dataa_range153w154w & wire_w_lg_w_dataa_range147w148w & wire_w_lg_w_dataa_range141w142w & wire_w_lg_w_dataa_range135w136w & wire_w_lg_w_dataa_range129w130w & wire_w_lg_w_dataa_range123w124w & wire_w_lg_w_dataa_range117w118w & wire_w_lg_w_dataa_range111w112w & wire_w_lg_w_dataa_range105w106w & wire_w_lg_w_dataa_range99w100w & wire_w_lg_w_dataa_range93w94w & wire_w_lg_w_dataa_range87w88w & dataa(0));
man_add_sub_dataa_w <= ( pos_sign_bit_ext & dataa_man_dffe1_wo);
man_add_sub_datab_w <= ( pos_sign_bit_ext & datab_man_dffe1_wo);
man_add_sub_res_mag_dffe21_wi <= man_res_mag_w2;
man_add_sub_res_mag_dffe21_wo <= man_add_sub_res_mag_dffe21;
man_add_sub_res_mag_dffe23_wi <= man_add_sub_res_mag_dffe21_wo;
man_add_sub_res_mag_dffe23_wo <= man_add_sub_res_mag_dffe23_wi;
man_add_sub_res_mag_dffe26_wi <= man_add_sub_res_mag_dffe23_wo;
man_add_sub_res_mag_dffe26_wo <= man_add_sub_res_mag_dffe26_wi;
man_add_sub_res_mag_dffe27_wi <= man_add_sub_res_mag_w2;
man_add_sub_res_mag_dffe27_wo <= man_add_sub_res_mag_dffe27_wi;
man_add_sub_res_mag_w2 <= (wire_w_lg_w_man_add_sub_w_range372w379w OR wire_w_lg_w_lg_w_man_add_sub_w_range372w375w378w);
man_add_sub_res_sign_dffe21_wo <= man_add_sub_res_sign_dffe21;
man_add_sub_res_sign_dffe23_wi <= man_add_sub_res_sign_dffe21_wo;
man_add_sub_res_sign_dffe23_wo <= man_add_sub_res_sign_dffe23_wi;
man_add_sub_res_sign_dffe26_wi <= man_add_sub_res_sign_dffe23_wo;
man_add_sub_res_sign_dffe26_wo <= man_add_sub_res_sign_dffe26_wi;
man_add_sub_res_sign_dffe27_wi <= man_add_sub_res_sign_w2;
man_add_sub_res_sign_dffe27_wo <= man_add_sub_res_sign_dffe27_wi;
man_add_sub_res_sign_w2 <= (wire_w_lg_need_complement_dffe22_wo376w(0) OR (wire_w_lg_need_complement_dffe22_wo373w(0) AND man_add_sub_w(27)));
man_add_sub_w <= ( wire_man_add_sub_lower_w_lg_w_lg_w_lg_cout354w355w356w & wire_man_add_sub_lower_result);
man_all_zeros_w <= (OTHERS => '0');
man_b_not_zero_w <= ( wire_w_lg_w_datab_range216w217w & wire_w_lg_w_datab_range210w211w & wire_w_lg_w_datab_range204w205w & wire_w_lg_w_datab_range198w199w & wire_w_lg_w_datab_range192w193w & wire_w_lg_w_datab_range186w187w & wire_w_lg_w_datab_range180w181w & wire_w_lg_w_datab_range174w175w & wire_w_lg_w_datab_range168w169w & wire_w_lg_w_datab_range162w163w & wire_w_lg_w_datab_range156w157w & wire_w_lg_w_datab_range150w151w & wire_w_lg_w_datab_range144w145w & wire_w_lg_w_datab_range138w139w & wire_w_lg_w_datab_range132w133w & wire_w_lg_w_datab_range126w127w & wire_w_lg_w_datab_range120w121w & wire_w_lg_w_datab_range114w115w & wire_w_lg_w_datab_range108w109w & wire_w_lg_w_datab_range102w103w & wire_w_lg_w_datab_range96w97w & wire_w_lg_w_datab_range90w91w & datab(0));
man_dffe31_wo <= man_dffe31;
man_intermediate_res_w <= ( "00" & man_res_w3);
man_leading_zeros_cnt_w <= man_leading_zeros_dffe31_wo;
man_leading_zeros_dffe31_wi <= (NOT wire_leading_zeroes_cnt_q);
man_leading_zeros_dffe31_wo <= man_leading_zeros_dffe31;
man_nan_w <= "10000000000000000000000";
man_out_dffe5_wi <= (wire_w_lg_force_nan_w652w OR wire_w_lg_w_lg_force_nan_w630w651w);
man_out_dffe5_wo <= man_out_dffe5;
man_res_dffe4_wi <= man_rounded_res_w;
man_res_dffe4_wo <= man_res_dffe4;
man_res_is_not_zero_dffe31_wi <= man_res_not_zero_dffe26_wo;
man_res_is_not_zero_dffe31_wo <= man_res_is_not_zero_dffe31;
man_res_is_not_zero_dffe32_wi <= man_res_is_not_zero_dffe31_wo;
man_res_is_not_zero_dffe32_wo <= man_res_is_not_zero_dffe32_wi;
man_res_is_not_zero_dffe33_wi <= man_res_is_not_zero_dffe32_wo;
man_res_is_not_zero_dffe33_wo <= man_res_is_not_zero_dffe33_wi;
man_res_is_not_zero_dffe3_wi <= man_res_is_not_zero_dffe33_wo;
man_res_is_not_zero_dffe3_wo <= man_res_is_not_zero_dffe3;
man_res_is_not_zero_dffe41_wi <= man_res_is_not_zero_dffe42_wo;
man_res_is_not_zero_dffe41_wo <= man_res_is_not_zero_dffe41_wi;
man_res_is_not_zero_dffe42_wi <= man_res_is_not_zero_dffe3_wo;
man_res_is_not_zero_dffe42_wo <= man_res_is_not_zero_dffe42_wi;
man_res_is_not_zero_dffe4_wi <= man_res_is_not_zero_dffe41_wo;
man_res_is_not_zero_dffe4_wo <= man_res_is_not_zero_dffe4;
man_res_mag_w2 <= (wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w414w OR wire_w412w);
man_res_not_zero_dffe23_wi <= man_res_not_zero_w2(24);
man_res_not_zero_dffe23_wo <= man_res_not_zero_dffe23_wi;
man_res_not_zero_dffe26_wi <= man_res_not_zero_dffe23_wo;
man_res_not_zero_dffe26_wo <= man_res_not_zero_dffe26_wi;
man_res_not_zero_w2 <= ( wire_w_lg_w_man_res_not_zero_w2_range487w489w & wire_w_lg_w_man_res_not_zero_w2_range484w486w & wire_w_lg_w_man_res_not_zero_w2_range481w483w & wire_w_lg_w_man_res_not_zero_w2_range478w480w & wire_w_lg_w_man_res_not_zero_w2_range475w477w & wire_w_lg_w_man_res_not_zero_w2_range472w474w & wire_w_lg_w_man_res_not_zero_w2_range469w471w & wire_w_lg_w_man_res_not_zero_w2_range466w468w & wire_w_lg_w_man_res_not_zero_w2_range463w465w & wire_w_lg_w_man_res_not_zero_w2_range460w462w & wire_w_lg_w_man_res_not_zero_w2_range457w459w & wire_w_lg_w_man_res_not_zero_w2_range454w456w & wire_w_lg_w_man_res_not_zero_w2_range451w453w & wire_w_lg_w_man_res_not_zero_w2_range448w450w & wire_w_lg_w_man_res_not_zero_w2_range445w447w & wire_w_lg_w_man_res_not_zero_w2_range442w444w & wire_w_lg_w_man_res_not_zero_w2_range439w441w & wire_w_lg_w_man_res_not_zero_w2_range436w438w & wire_w_lg_w_man_res_not_zero_w2_range433w435w & wire_w_lg_w_man_res_not_zero_w2_range430w432w & wire_w_lg_w_man_res_not_zero_w2_range427w429w & wire_w_lg_w_man_res_not_zero_w2_range424w426w & wire_w_lg_w_man_res_not_zero_w2_range421w423w & wire_w_lg_w_man_res_not_zero_w2_range417w420w & man_add_sub_res_mag_dffe21_wo(1));
man_res_rounding_add_sub_datab_w <= ( "0000000000000000000000000" & man_rounding_add_value_w);
man_res_rounding_add_sub_w <= ( wire_man_res_rounding_add_sub_lower_w_lg_w_lg_w_lg_cout580w581w582w & wire_man_res_rounding_add_sub_lower_result);
man_res_w3 <= wire_lbarrel_shift_result(25 DOWNTO 2);
man_rounded_res_w <= (wire_w_lg_w_man_res_rounding_add_sub_w_range585w589w OR wire_w587w);
man_rounding_add_value_w <= (round_bit_dffe3_wo AND (sticky_bit_dffe3_wo OR guard_bit_dffe3_wo));
man_smaller_dffe13_wi <= man_smaller_w;
man_smaller_dffe13_wo <= man_smaller_dffe13_wi;
man_smaller_w <= (wire_w_lg_exp_amb_mux_w279w OR wire_w_lg_w_lg_exp_amb_mux_w275w278w);
need_complement_dffe22_wi <= need_complement_dffe2_wo;
need_complement_dffe22_wo <= need_complement_dffe22_wi;
need_complement_dffe2_wi <= dataa_sign_dffe25_wo;
need_complement_dffe2_wo <= need_complement_dffe2;
pos_sign_bit_ext <= (OTHERS => '0');
priority_encoder_1pads_w <= (OTHERS => '1');
result <= ( sign_out_dffe5_wo & exp_out_dffe5_wo & man_out_dffe5_wo);
round_bit_dffe21_wi <= round_bit_w;
round_bit_dffe21_wo <= round_bit_dffe21;
round_bit_dffe23_wi <= round_bit_dffe21_wo;
round_bit_dffe23_wo <= round_bit_dffe23_wi;
round_bit_dffe26_wi <= round_bit_dffe23_wo;
round_bit_dffe26_wo <= round_bit_dffe26_wi;
round_bit_dffe31_wi <= round_bit_dffe26_wo;
round_bit_dffe31_wo <= round_bit_dffe31;
round_bit_dffe32_wi <= round_bit_dffe31_wo;
round_bit_dffe32_wo <= round_bit_dffe32_wi;
round_bit_dffe33_wi <= round_bit_dffe32_wo;
round_bit_dffe33_wo <= round_bit_dffe33_wi;
round_bit_dffe3_wi <= round_bit_dffe33_wo;
round_bit_dffe3_wo <= round_bit_dffe3;
round_bit_w <= ((((wire_w397w(0) AND man_add_sub_res_mag_dffe27_wo(0)) OR ((wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) AND man_add_sub_res_mag_dffe27_wo(25)) AND man_add_sub_res_mag_dffe27_wo(1))) OR (wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w391w(0) AND man_add_sub_res_mag_dffe27_wo(2))) OR ((man_add_sub_res_mag_dffe27_wo(26) AND man_add_sub_res_mag_dffe27_wo(25)) AND man_add_sub_res_mag_dffe27_wo(2)));
rounded_res_infinity_dffe4_wi <= exp_rounded_res_infinity_w;
rounded_res_infinity_dffe4_wo <= rounded_res_infinity_dffe4;
rshift_distance_dffe13_wi <= rshift_distance_w;
rshift_distance_dffe13_wo <= rshift_distance_dffe13_wi;
rshift_distance_dffe14_wi <= rshift_distance_dffe13_wo;
rshift_distance_dffe14_wo <= rshift_distance_dffe14_wi;
rshift_distance_dffe15_wi <= rshift_distance_dffe14_wo;
rshift_distance_dffe15_wo <= rshift_distance_dffe15_wi;
rshift_distance_w <= (wire_w_lg_w_exp_diff_abs_exceed_max_w_range289w293w OR wire_w292w);
sign_dffe31_wi <= ((man_res_not_zero_dffe26_wo AND man_add_sub_res_sign_dffe26_wo) OR wire_w_lg_w_lg_man_res_not_zero_dffe26_wo503w504w(0));
sign_dffe31_wo <= sign_dffe31;
sign_dffe32_wi <= sign_dffe31_wo;
sign_dffe32_wo <= sign_dffe32_wi;
sign_dffe33_wi <= sign_dffe32_wo;
sign_dffe33_wo <= sign_dffe33_wi;
sign_out_dffe5_wi <= (wire_w_lg_force_nan_w630w(0) AND ((force_infinity_w AND infinite_output_sign_dffe4_wo) OR wire_w_lg_w_lg_force_infinity_w629w654w(0)));
sign_out_dffe5_wo <= sign_out_dffe5;
sign_res_dffe3_wi <= sign_dffe33_wo;
sign_res_dffe3_wo <= sign_res_dffe3;
sign_res_dffe41_wi <= sign_res_dffe42_wo;
sign_res_dffe41_wo <= sign_res_dffe41_wi;
sign_res_dffe42_wi <= sign_res_dffe3_wo;
sign_res_dffe42_wo <= sign_res_dffe42_wi;
sign_res_dffe4_wi <= sign_res_dffe41_wo;
sign_res_dffe4_wo <= sign_res_dffe4;
sticky_bit_cnt_dataa_w <= ( "0" & rshift_distance_dffe15_wo);
sticky_bit_cnt_datab_w <= ( "0" & wire_trailing_zeros_cnt_q);
sticky_bit_cnt_res_w <= wire_add_sub3_result;
sticky_bit_dffe1_wi <= wire_trailing_zeros_limit_comparator_agb;
sticky_bit_dffe1_wo <= sticky_bit_dffe1;
sticky_bit_dffe21_wi <= sticky_bit_w;
sticky_bit_dffe21_wo <= sticky_bit_dffe21;
sticky_bit_dffe22_wi <= sticky_bit_dffe2_wo;
sticky_bit_dffe22_wo <= sticky_bit_dffe22_wi;
sticky_bit_dffe23_wi <= sticky_bit_dffe21_wo;
sticky_bit_dffe23_wo <= sticky_bit_dffe23_wi;
sticky_bit_dffe25_wi <= sticky_bit_dffe1_wo;
sticky_bit_dffe25_wo <= sticky_bit_dffe25_wi;
sticky_bit_dffe26_wi <= sticky_bit_dffe23_wo;
sticky_bit_dffe26_wo <= sticky_bit_dffe26_wi;
sticky_bit_dffe27_wi <= sticky_bit_dffe22_wo;
sticky_bit_dffe27_wo <= sticky_bit_dffe27_wi;
sticky_bit_dffe2_wi <= sticky_bit_dffe25_wo;
sticky_bit_dffe2_wo <= sticky_bit_dffe2;
sticky_bit_dffe31_wi <= sticky_bit_dffe26_wo;
sticky_bit_dffe31_wo <= sticky_bit_dffe31;
sticky_bit_dffe32_wi <= sticky_bit_dffe31_wo;
sticky_bit_dffe32_wo <= sticky_bit_dffe32_wi;
sticky_bit_dffe33_wi <= sticky_bit_dffe32_wo;
sticky_bit_dffe33_wo <= sticky_bit_dffe33_wi;
sticky_bit_dffe3_wi <= sticky_bit_dffe33_wo;
sticky_bit_dffe3_wo <= sticky_bit_dffe3;
sticky_bit_w <= (((wire_w_lg_w397w407w(0) OR ((wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) AND man_add_sub_res_mag_dffe27_wo(25)) AND wire_w_lg_sticky_bit_dffe27_wo402w(0))) OR (wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w391w(0) AND (wire_w_lg_sticky_bit_dffe27_wo402w(0) OR man_add_sub_res_mag_dffe27_wo(1)))) OR ((man_add_sub_res_mag_dffe27_wo(26) AND man_add_sub_res_mag_dffe27_wo(25)) AND (wire_w_lg_sticky_bit_dffe27_wo402w(0) OR man_add_sub_res_mag_dffe27_wo(1))));
trailing_zeros_limit_w <= "000010";
zero_man_sign_dffe21_wi <= zero_man_sign_dffe27_wo;
zero_man_sign_dffe21_wo <= zero_man_sign_dffe21;
zero_man_sign_dffe22_wi <= zero_man_sign_dffe2_wo;
zero_man_sign_dffe22_wo <= zero_man_sign_dffe22_wi;
zero_man_sign_dffe23_wi <= zero_man_sign_dffe21_wo;
zero_man_sign_dffe23_wo <= zero_man_sign_dffe23_wi;
zero_man_sign_dffe26_wi <= zero_man_sign_dffe23_wo;
zero_man_sign_dffe26_wo <= zero_man_sign_dffe26_wi;
zero_man_sign_dffe27_wi <= zero_man_sign_dffe22_wo;
zero_man_sign_dffe27_wo <= zero_man_sign_dffe27_wi;
zero_man_sign_dffe2_wi <= (dataa_sign_dffe25_wo AND add_sub_dffe25_wo);
zero_man_sign_dffe2_wo <= zero_man_sign_dffe2;
wire_w_aligned_dataa_exp_dffe15_wo_range315w <= aligned_dataa_exp_dffe15_wo(7 DOWNTO 0);
wire_w_aligned_datab_exp_dffe15_wo_range313w <= aligned_datab_exp_dffe15_wo(7 DOWNTO 0);
wire_w_dataa_range141w(0) <= dataa(10);
wire_w_dataa_range147w(0) <= dataa(11);
wire_w_dataa_range153w(0) <= dataa(12);
wire_w_dataa_range159w(0) <= dataa(13);
wire_w_dataa_range165w(0) <= dataa(14);
wire_w_dataa_range171w(0) <= dataa(15);
wire_w_dataa_range177w(0) <= dataa(16);
wire_w_dataa_range183w(0) <= dataa(17);
wire_w_dataa_range189w(0) <= dataa(18);
wire_w_dataa_range195w(0) <= dataa(19);
wire_w_dataa_range87w(0) <= dataa(1);
wire_w_dataa_range201w(0) <= dataa(20);
wire_w_dataa_range207w(0) <= dataa(21);
wire_w_dataa_range213w(0) <= dataa(22);
wire_w_dataa_range17w(0) <= dataa(24);
wire_w_dataa_range27w(0) <= dataa(25);
wire_w_dataa_range37w(0) <= dataa(26);
wire_w_dataa_range47w(0) <= dataa(27);
wire_w_dataa_range57w(0) <= dataa(28);
wire_w_dataa_range67w(0) <= dataa(29);
wire_w_dataa_range93w(0) <= dataa(2);
wire_w_dataa_range77w(0) <= dataa(30);
wire_w_dataa_range99w(0) <= dataa(3);
wire_w_dataa_range105w(0) <= dataa(4);
wire_w_dataa_range111w(0) <= dataa(5);
wire_w_dataa_range117w(0) <= dataa(6);
wire_w_dataa_range123w(0) <= dataa(7);
wire_w_dataa_range129w(0) <= dataa(8);
wire_w_dataa_range135w(0) <= dataa(9);
wire_w_dataa_dffe11_wo_range242w <= dataa_dffe11_wo(22 DOWNTO 0);
wire_w_dataa_dffe11_wo_range232w <= dataa_dffe11_wo(30 DOWNTO 23);
wire_w_datab_range144w(0) <= datab(10);
wire_w_datab_range150w(0) <= datab(11);
wire_w_datab_range156w(0) <= datab(12);
wire_w_datab_range162w(0) <= datab(13);
wire_w_datab_range168w(0) <= datab(14);
wire_w_datab_range174w(0) <= datab(15);
wire_w_datab_range180w(0) <= datab(16);
wire_w_datab_range186w(0) <= datab(17);
wire_w_datab_range192w(0) <= datab(18);
wire_w_datab_range198w(0) <= datab(19);
wire_w_datab_range90w(0) <= datab(1);
wire_w_datab_range204w(0) <= datab(20);
wire_w_datab_range210w(0) <= datab(21);
wire_w_datab_range216w(0) <= datab(22);
wire_w_datab_range20w(0) <= datab(24);
wire_w_datab_range30w(0) <= datab(25);
wire_w_datab_range40w(0) <= datab(26);
wire_w_datab_range50w(0) <= datab(27);
wire_w_datab_range60w(0) <= datab(28);
wire_w_datab_range70w(0) <= datab(29);
wire_w_datab_range96w(0) <= datab(2);
wire_w_datab_range80w(0) <= datab(30);
wire_w_datab_range102w(0) <= datab(3);
wire_w_datab_range108w(0) <= datab(4);
wire_w_datab_range114w(0) <= datab(5);
wire_w_datab_range120w(0) <= datab(6);
wire_w_datab_range126w(0) <= datab(7);
wire_w_datab_range132w(0) <= datab(8);
wire_w_datab_range138w(0) <= datab(9);
wire_w_datab_dffe11_wo_range261w <= datab_dffe11_wo(22 DOWNTO 0);
wire_w_datab_dffe11_wo_range251w <= datab_dffe11_wo(30 DOWNTO 23);
wire_w_exp_a_all_one_w_range7w(0) <= exp_a_all_one_w(0);
wire_w_exp_a_all_one_w_range24w(0) <= exp_a_all_one_w(1);
wire_w_exp_a_all_one_w_range34w(0) <= exp_a_all_one_w(2);
wire_w_exp_a_all_one_w_range44w(0) <= exp_a_all_one_w(3);
wire_w_exp_a_all_one_w_range54w(0) <= exp_a_all_one_w(4);
wire_w_exp_a_all_one_w_range64w(0) <= exp_a_all_one_w(5);
wire_w_exp_a_all_one_w_range74w(0) <= exp_a_all_one_w(6);
wire_w_exp_a_all_one_w_range84w(0) <= exp_a_all_one_w(7);
wire_w_exp_a_not_zero_w_range2w(0) <= exp_a_not_zero_w(0);
wire_w_exp_a_not_zero_w_range19w(0) <= exp_a_not_zero_w(1);
wire_w_exp_a_not_zero_w_range29w(0) <= exp_a_not_zero_w(2);
wire_w_exp_a_not_zero_w_range39w(0) <= exp_a_not_zero_w(3);
wire_w_exp_a_not_zero_w_range49w(0) <= exp_a_not_zero_w(4);
wire_w_exp_a_not_zero_w_range59w(0) <= exp_a_not_zero_w(5);
wire_w_exp_a_not_zero_w_range69w(0) <= exp_a_not_zero_w(6);
wire_w_exp_adjustment2_add_sub_w_range518w(0) <= exp_adjustment2_add_sub_w(1);
wire_w_exp_adjustment2_add_sub_w_range521w(0) <= exp_adjustment2_add_sub_w(2);
wire_w_exp_adjustment2_add_sub_w_range524w(0) <= exp_adjustment2_add_sub_w(3);
wire_w_exp_adjustment2_add_sub_w_range527w(0) <= exp_adjustment2_add_sub_w(4);
wire_w_exp_adjustment2_add_sub_w_range530w(0) <= exp_adjustment2_add_sub_w(5);
wire_w_exp_adjustment2_add_sub_w_range533w(0) <= exp_adjustment2_add_sub_w(6);
wire_w_exp_adjustment2_add_sub_w_range557w <= exp_adjustment2_add_sub_w(7 DOWNTO 0);
wire_w_exp_adjustment2_add_sub_w_range536w(0) <= exp_adjustment2_add_sub_w(7);
wire_w_exp_adjustment2_add_sub_w_range511w(0) <= exp_adjustment2_add_sub_w(8);
wire_w_exp_amb_w_range274w <= exp_amb_w(7 DOWNTO 0);
wire_w_exp_b_all_one_w_range9w(0) <= exp_b_all_one_w(0);
wire_w_exp_b_all_one_w_range26w(0) <= exp_b_all_one_w(1);
wire_w_exp_b_all_one_w_range36w(0) <= exp_b_all_one_w(2);
wire_w_exp_b_all_one_w_range46w(0) <= exp_b_all_one_w(3);
wire_w_exp_b_all_one_w_range56w(0) <= exp_b_all_one_w(4);
wire_w_exp_b_all_one_w_range66w(0) <= exp_b_all_one_w(5);
wire_w_exp_b_all_one_w_range76w(0) <= exp_b_all_one_w(6);
wire_w_exp_b_all_one_w_range86w(0) <= exp_b_all_one_w(7);
wire_w_exp_b_not_zero_w_range5w(0) <= exp_b_not_zero_w(0);
wire_w_exp_b_not_zero_w_range22w(0) <= exp_b_not_zero_w(1);
wire_w_exp_b_not_zero_w_range32w(0) <= exp_b_not_zero_w(2);
wire_w_exp_b_not_zero_w_range42w(0) <= exp_b_not_zero_w(3);
wire_w_exp_b_not_zero_w_range52w(0) <= exp_b_not_zero_w(4);
wire_w_exp_b_not_zero_w_range62w(0) <= exp_b_not_zero_w(5);
wire_w_exp_b_not_zero_w_range72w(0) <= exp_b_not_zero_w(6);
wire_w_exp_bma_w_range272w <= exp_bma_w(7 DOWNTO 0);
wire_w_exp_diff_abs_exceed_max_w_range282w(0) <= exp_diff_abs_exceed_max_w(0);
wire_w_exp_diff_abs_exceed_max_w_range286w(0) <= exp_diff_abs_exceed_max_w(1);
wire_w_exp_diff_abs_exceed_max_w_range289w(0) <= exp_diff_abs_exceed_max_w(2);
wire_w_exp_diff_abs_w_range290w <= exp_diff_abs_w(4 DOWNTO 0);
wire_w_exp_diff_abs_w_range284w(0) <= exp_diff_abs_w(6);
wire_w_exp_diff_abs_w_range287w(0) <= exp_diff_abs_w(7);
wire_w_exp_res_max_w_range540w(0) <= exp_res_max_w(0);
wire_w_exp_res_max_w_range543w(0) <= exp_res_max_w(1);
wire_w_exp_res_max_w_range545w(0) <= exp_res_max_w(2);
wire_w_exp_res_max_w_range547w(0) <= exp_res_max_w(3);
wire_w_exp_res_max_w_range549w(0) <= exp_res_max_w(4);
wire_w_exp_res_max_w_range551w(0) <= exp_res_max_w(5);
wire_w_exp_res_max_w_range553w(0) <= exp_res_max_w(6);
wire_w_exp_res_max_w_range555w(0) <= exp_res_max_w(7);
wire_w_exp_res_not_zero_w_range516w(0) <= exp_res_not_zero_w(0);
wire_w_exp_res_not_zero_w_range520w(0) <= exp_res_not_zero_w(1);
wire_w_exp_res_not_zero_w_range523w(0) <= exp_res_not_zero_w(2);
wire_w_exp_res_not_zero_w_range526w(0) <= exp_res_not_zero_w(3);
wire_w_exp_res_not_zero_w_range529w(0) <= exp_res_not_zero_w(4);
wire_w_exp_res_not_zero_w_range532w(0) <= exp_res_not_zero_w(5);
wire_w_exp_res_not_zero_w_range535w(0) <= exp_res_not_zero_w(6);
wire_w_exp_res_not_zero_w_range538w(0) <= exp_res_not_zero_w(7);
wire_w_exp_rounded_res_max_w_range601w(0) <= exp_rounded_res_max_w(0);
wire_w_exp_rounded_res_max_w_range605w(0) <= exp_rounded_res_max_w(1);
wire_w_exp_rounded_res_max_w_range608w(0) <= exp_rounded_res_max_w(2);
wire_w_exp_rounded_res_max_w_range611w(0) <= exp_rounded_res_max_w(3);
wire_w_exp_rounded_res_max_w_range614w(0) <= exp_rounded_res_max_w(4);
wire_w_exp_rounded_res_max_w_range617w(0) <= exp_rounded_res_max_w(5);
wire_w_exp_rounded_res_max_w_range620w(0) <= exp_rounded_res_max_w(6);
wire_w_exp_rounded_res_w_range603w(0) <= exp_rounded_res_w(1);
wire_w_exp_rounded_res_w_range606w(0) <= exp_rounded_res_w(2);
wire_w_exp_rounded_res_w_range609w(0) <= exp_rounded_res_w(3);
wire_w_exp_rounded_res_w_range612w(0) <= exp_rounded_res_w(4);
wire_w_exp_rounded_res_w_range615w(0) <= exp_rounded_res_w(5);
wire_w_exp_rounded_res_w_range618w(0) <= exp_rounded_res_w(6);
wire_w_exp_rounded_res_w_range621w(0) <= exp_rounded_res_w(7);
wire_w_man_a_not_zero_w_range12w(0) <= man_a_not_zero_w(0);
wire_w_man_a_not_zero_w_range143w(0) <= man_a_not_zero_w(10);
wire_w_man_a_not_zero_w_range149w(0) <= man_a_not_zero_w(11);
wire_w_man_a_not_zero_w_range155w(0) <= man_a_not_zero_w(12);
wire_w_man_a_not_zero_w_range161w(0) <= man_a_not_zero_w(13);
wire_w_man_a_not_zero_w_range167w(0) <= man_a_not_zero_w(14);
wire_w_man_a_not_zero_w_range173w(0) <= man_a_not_zero_w(15);
wire_w_man_a_not_zero_w_range179w(0) <= man_a_not_zero_w(16);
wire_w_man_a_not_zero_w_range185w(0) <= man_a_not_zero_w(17);
wire_w_man_a_not_zero_w_range191w(0) <= man_a_not_zero_w(18);
wire_w_man_a_not_zero_w_range197w(0) <= man_a_not_zero_w(19);
wire_w_man_a_not_zero_w_range89w(0) <= man_a_not_zero_w(1);
wire_w_man_a_not_zero_w_range203w(0) <= man_a_not_zero_w(20);
wire_w_man_a_not_zero_w_range209w(0) <= man_a_not_zero_w(21);
wire_w_man_a_not_zero_w_range215w(0) <= man_a_not_zero_w(22);
wire_w_man_a_not_zero_w_range95w(0) <= man_a_not_zero_w(2);
wire_w_man_a_not_zero_w_range101w(0) <= man_a_not_zero_w(3);
wire_w_man_a_not_zero_w_range107w(0) <= man_a_not_zero_w(4);
wire_w_man_a_not_zero_w_range113w(0) <= man_a_not_zero_w(5);
wire_w_man_a_not_zero_w_range119w(0) <= man_a_not_zero_w(6);
wire_w_man_a_not_zero_w_range125w(0) <= man_a_not_zero_w(7);
wire_w_man_a_not_zero_w_range131w(0) <= man_a_not_zero_w(8);
wire_w_man_a_not_zero_w_range137w(0) <= man_a_not_zero_w(9);
wire_w_man_add_sub_res_mag_dffe21_wo_range443w(0) <= man_add_sub_res_mag_dffe21_wo(10);
wire_w_man_add_sub_res_mag_dffe21_wo_range446w(0) <= man_add_sub_res_mag_dffe21_wo(11);
wire_w_man_add_sub_res_mag_dffe21_wo_range449w(0) <= man_add_sub_res_mag_dffe21_wo(12);
wire_w_man_add_sub_res_mag_dffe21_wo_range452w(0) <= man_add_sub_res_mag_dffe21_wo(13);
wire_w_man_add_sub_res_mag_dffe21_wo_range455w(0) <= man_add_sub_res_mag_dffe21_wo(14);
wire_w_man_add_sub_res_mag_dffe21_wo_range458w(0) <= man_add_sub_res_mag_dffe21_wo(15);
wire_w_man_add_sub_res_mag_dffe21_wo_range461w(0) <= man_add_sub_res_mag_dffe21_wo(16);
wire_w_man_add_sub_res_mag_dffe21_wo_range464w(0) <= man_add_sub_res_mag_dffe21_wo(17);
wire_w_man_add_sub_res_mag_dffe21_wo_range467w(0) <= man_add_sub_res_mag_dffe21_wo(18);
wire_w_man_add_sub_res_mag_dffe21_wo_range470w(0) <= man_add_sub_res_mag_dffe21_wo(19);
wire_w_man_add_sub_res_mag_dffe21_wo_range473w(0) <= man_add_sub_res_mag_dffe21_wo(20);
wire_w_man_add_sub_res_mag_dffe21_wo_range476w(0) <= man_add_sub_res_mag_dffe21_wo(21);
wire_w_man_add_sub_res_mag_dffe21_wo_range479w(0) <= man_add_sub_res_mag_dffe21_wo(22);
wire_w_man_add_sub_res_mag_dffe21_wo_range482w(0) <= man_add_sub_res_mag_dffe21_wo(23);
wire_w_man_add_sub_res_mag_dffe21_wo_range485w(0) <= man_add_sub_res_mag_dffe21_wo(24);
wire_w_man_add_sub_res_mag_dffe21_wo_range488w(0) <= man_add_sub_res_mag_dffe21_wo(25);
wire_w_man_add_sub_res_mag_dffe21_wo_range419w(0) <= man_add_sub_res_mag_dffe21_wo(2);
wire_w_man_add_sub_res_mag_dffe21_wo_range422w(0) <= man_add_sub_res_mag_dffe21_wo(3);
wire_w_man_add_sub_res_mag_dffe21_wo_range425w(0) <= man_add_sub_res_mag_dffe21_wo(4);
wire_w_man_add_sub_res_mag_dffe21_wo_range428w(0) <= man_add_sub_res_mag_dffe21_wo(5);
wire_w_man_add_sub_res_mag_dffe21_wo_range431w(0) <= man_add_sub_res_mag_dffe21_wo(6);
wire_w_man_add_sub_res_mag_dffe21_wo_range434w(0) <= man_add_sub_res_mag_dffe21_wo(7);
wire_w_man_add_sub_res_mag_dffe21_wo_range437w(0) <= man_add_sub_res_mag_dffe21_wo(8);
wire_w_man_add_sub_res_mag_dffe21_wo_range440w(0) <= man_add_sub_res_mag_dffe21_wo(9);
wire_w_man_add_sub_res_mag_dffe27_wo_range396w(0) <= man_add_sub_res_mag_dffe27_wo(0);
wire_w_man_add_sub_res_mag_dffe27_wo_range411w <= man_add_sub_res_mag_dffe27_wo(25 DOWNTO 0);
wire_w_man_add_sub_res_mag_dffe27_wo_range387w(0) <= man_add_sub_res_mag_dffe27_wo(25);
wire_w_man_add_sub_res_mag_dffe27_wo_range413w <= man_add_sub_res_mag_dffe27_wo(26 DOWNTO 1);
wire_w_man_add_sub_res_mag_dffe27_wo_range381w(0) <= man_add_sub_res_mag_dffe27_wo(26);
wire_w_man_add_sub_w_range372w(0) <= man_add_sub_w(27);
wire_w_man_b_not_zero_w_range15w(0) <= man_b_not_zero_w(0);
wire_w_man_b_not_zero_w_range146w(0) <= man_b_not_zero_w(10);
wire_w_man_b_not_zero_w_range152w(0) <= man_b_not_zero_w(11);
wire_w_man_b_not_zero_w_range158w(0) <= man_b_not_zero_w(12);
wire_w_man_b_not_zero_w_range164w(0) <= man_b_not_zero_w(13);
wire_w_man_b_not_zero_w_range170w(0) <= man_b_not_zero_w(14);
wire_w_man_b_not_zero_w_range176w(0) <= man_b_not_zero_w(15);
wire_w_man_b_not_zero_w_range182w(0) <= man_b_not_zero_w(16);
wire_w_man_b_not_zero_w_range188w(0) <= man_b_not_zero_w(17);
wire_w_man_b_not_zero_w_range194w(0) <= man_b_not_zero_w(18);
wire_w_man_b_not_zero_w_range200w(0) <= man_b_not_zero_w(19);
wire_w_man_b_not_zero_w_range92w(0) <= man_b_not_zero_w(1);
wire_w_man_b_not_zero_w_range206w(0) <= man_b_not_zero_w(20);
wire_w_man_b_not_zero_w_range212w(0) <= man_b_not_zero_w(21);
wire_w_man_b_not_zero_w_range218w(0) <= man_b_not_zero_w(22);
wire_w_man_b_not_zero_w_range98w(0) <= man_b_not_zero_w(2);
wire_w_man_b_not_zero_w_range104w(0) <= man_b_not_zero_w(3);
wire_w_man_b_not_zero_w_range110w(0) <= man_b_not_zero_w(4);
wire_w_man_b_not_zero_w_range116w(0) <= man_b_not_zero_w(5);
wire_w_man_b_not_zero_w_range122w(0) <= man_b_not_zero_w(6);
wire_w_man_b_not_zero_w_range128w(0) <= man_b_not_zero_w(7);
wire_w_man_b_not_zero_w_range134w(0) <= man_b_not_zero_w(8);
wire_w_man_b_not_zero_w_range140w(0) <= man_b_not_zero_w(9);
wire_w_man_res_not_zero_w2_range417w(0) <= man_res_not_zero_w2(0);
wire_w_man_res_not_zero_w2_range448w(0) <= man_res_not_zero_w2(10);
wire_w_man_res_not_zero_w2_range451w(0) <= man_res_not_zero_w2(11);
wire_w_man_res_not_zero_w2_range454w(0) <= man_res_not_zero_w2(12);
wire_w_man_res_not_zero_w2_range457w(0) <= man_res_not_zero_w2(13);
wire_w_man_res_not_zero_w2_range460w(0) <= man_res_not_zero_w2(14);
wire_w_man_res_not_zero_w2_range463w(0) <= man_res_not_zero_w2(15);
wire_w_man_res_not_zero_w2_range466w(0) <= man_res_not_zero_w2(16);
wire_w_man_res_not_zero_w2_range469w(0) <= man_res_not_zero_w2(17);
wire_w_man_res_not_zero_w2_range472w(0) <= man_res_not_zero_w2(18);
wire_w_man_res_not_zero_w2_range475w(0) <= man_res_not_zero_w2(19);
wire_w_man_res_not_zero_w2_range421w(0) <= man_res_not_zero_w2(1);
wire_w_man_res_not_zero_w2_range478w(0) <= man_res_not_zero_w2(20);
wire_w_man_res_not_zero_w2_range481w(0) <= man_res_not_zero_w2(21);
wire_w_man_res_not_zero_w2_range484w(0) <= man_res_not_zero_w2(22);
wire_w_man_res_not_zero_w2_range487w(0) <= man_res_not_zero_w2(23);
wire_w_man_res_not_zero_w2_range424w(0) <= man_res_not_zero_w2(2);
wire_w_man_res_not_zero_w2_range427w(0) <= man_res_not_zero_w2(3);
wire_w_man_res_not_zero_w2_range430w(0) <= man_res_not_zero_w2(4);
wire_w_man_res_not_zero_w2_range433w(0) <= man_res_not_zero_w2(5);
wire_w_man_res_not_zero_w2_range436w(0) <= man_res_not_zero_w2(6);
wire_w_man_res_not_zero_w2_range439w(0) <= man_res_not_zero_w2(7);
wire_w_man_res_not_zero_w2_range442w(0) <= man_res_not_zero_w2(8);
wire_w_man_res_not_zero_w2_range445w(0) <= man_res_not_zero_w2(9);
wire_w_man_res_rounding_add_sub_w_range584w <= man_res_rounding_add_sub_w(22 DOWNTO 0);
wire_w_man_res_rounding_add_sub_w_range588w <= man_res_rounding_add_sub_w(23 DOWNTO 1);
wire_w_man_res_rounding_add_sub_w_range585w(0) <= man_res_rounding_add_sub_w(24);
lbarrel_shift : add_flt_stratix5_latency_altbarrel_shift_nud
PORT MAP (
aclr => aclr,
clk_en => clk_en,
clock => clock,
data => man_dffe31_wo,
distance => man_leading_zeros_cnt_w,
result => wire_lbarrel_shift_result
);
wire_rbarrel_shift_data <= ( man_smaller_dffe13_wo & "00");
rbarrel_shift : add_flt_stratix5_latency_altbarrel_shift_cfb
PORT MAP (
data => wire_rbarrel_shift_data,
distance => rshift_distance_dffe13_wo,
result => wire_rbarrel_shift_result
);
wire_leading_zeroes_cnt_data <= ( man_add_sub_res_mag_dffe21_wo(25 DOWNTO 1) & "1" & "000000");
leading_zeroes_cnt : add_flt_stratix5_latency_altpriority_encoder_qb6
PORT MAP (
data => wire_leading_zeroes_cnt_data,
q => wire_leading_zeroes_cnt_q
);
wire_trailing_zeros_cnt_data <= ( "111111111" & man_smaller_dffe13_wo(22 DOWNTO 0));
trailing_zeros_cnt : add_flt_stratix5_latency_altpriority_encoder_e48
PORT MAP (
data => wire_trailing_zeros_cnt_data,
q => wire_trailing_zeros_cnt_q
);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN both_inputs_are_infinite_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN both_inputs_are_infinite_dffe1 <= both_inputs_are_infinite_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN data_exp_dffe1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN data_exp_dffe1 <= data_exp_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN dataa_man_dffe1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN dataa_man_dffe1 <= dataa_man_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN dataa_sign_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN dataa_sign_dffe1 <= dataa_sign_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN datab_man_dffe1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN datab_man_dffe1 <= datab_man_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN datab_sign_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN datab_sign_dffe1 <= datab_sign_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN denormal_res_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN denormal_res_dffe3 <= denormal_res_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN denormal_res_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN denormal_res_dffe4 <= denormal_res_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_adj_dffe21 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_adj_dffe21 <= exp_adj_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_out_dffe5 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_out_dffe5 <= exp_out_dffe5_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe2 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe2 <= exp_res_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe21 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe21 <= exp_res_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe3 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe3 <= exp_res_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe4 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe4 <= exp_res_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe1 <= infinite_output_sign_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe2 <= infinite_output_sign_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe21 <= infinite_output_sign_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe3 <= infinite_output_sign_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe31 <= infinite_output_sign_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe4 <= infinite_output_sign_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_res_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_res_dffe3 <= infinite_res_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_res_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_res_dffe4 <= infinite_res_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe2 <= infinity_magnitude_sub_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe21 <= infinity_magnitude_sub_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe3 <= infinity_magnitude_sub_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe31 <= infinity_magnitude_sub_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe4 <= infinity_magnitude_sub_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe1 <= input_is_infinite_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe2 <= input_is_infinite_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe21 <= input_is_infinite_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe3 <= input_is_infinite_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe31 <= input_is_infinite_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe4 <= input_is_infinite_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe1 <= input_is_nan_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe2 <= input_is_nan_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe21 <= input_is_nan_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe3 <= input_is_nan_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe31 <= input_is_nan_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe4 <= input_is_nan_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_add_sub_res_mag_dffe21 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_add_sub_res_mag_dffe21 <= man_add_sub_res_mag_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_add_sub_res_sign_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_add_sub_res_sign_dffe21 <= man_add_sub_res_sign_dffe27_wo;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_dffe31 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_dffe31 <= man_add_sub_res_mag_dffe26_wo;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_leading_zeros_dffe31 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_leading_zeros_dffe31 <= man_leading_zeros_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_out_dffe5 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_out_dffe5 <= man_out_dffe5_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_dffe4 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_dffe4 <= man_res_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_is_not_zero_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_is_not_zero_dffe3 <= man_res_is_not_zero_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_is_not_zero_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_is_not_zero_dffe31 <= man_res_is_not_zero_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_is_not_zero_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_is_not_zero_dffe4 <= man_res_is_not_zero_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN need_complement_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN need_complement_dffe2 <= need_complement_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN round_bit_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN round_bit_dffe21 <= round_bit_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN round_bit_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN round_bit_dffe3 <= round_bit_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN round_bit_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN round_bit_dffe31 <= round_bit_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN rounded_res_infinity_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN rounded_res_infinity_dffe4 <= rounded_res_infinity_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe31 <= sign_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_out_dffe5 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_out_dffe5 <= sign_out_dffe5_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_res_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_res_dffe3 <= sign_res_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_res_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_res_dffe4 <= sign_res_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe1 <= sticky_bit_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe2 <= sticky_bit_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe21 <= sticky_bit_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe3 <= sticky_bit_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe31 <= sticky_bit_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN zero_man_sign_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN zero_man_sign_dffe2 <= zero_man_sign_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN zero_man_sign_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN zero_man_sign_dffe21 <= zero_man_sign_dffe21_wi;
END IF;
END IF;
END PROCESS;
add_sub1 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9
)
PORT MAP (
dataa => aligned_dataa_exp_w,
datab => aligned_datab_exp_w,
result => wire_add_sub1_result
);
add_sub2 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9
)
PORT MAP (
dataa => aligned_datab_exp_w,
datab => aligned_dataa_exp_w,
result => wire_add_sub2_result
);
add_sub3 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 6
)
PORT MAP (
dataa => sticky_bit_cnt_dataa_w,
datab => sticky_bit_cnt_datab_w,
result => wire_add_sub3_result
);
add_sub4 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9
)
PORT MAP (
dataa => exp_adjustment_add_sub_dataa_w,
datab => exp_adjustment_add_sub_datab_w,
result => wire_add_sub4_result
);
add_sub5 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => exp_adjustment2_add_sub_dataa_w,
datab => exp_adjustment2_add_sub_datab_w,
result => wire_add_sub5_result
);
add_sub6 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9
)
PORT MAP (
dataa => exp_res_rounding_adder_dataa_w,
datab => exp_rounding_adjustment_w,
result => wire_add_sub6_result
);
loop121 : FOR i IN 0 TO 13 GENERATE
wire_man_2comp_res_lower_w_lg_w_lg_cout367w368w(i) <= wire_man_2comp_res_lower_w_lg_cout367w(0) AND wire_man_2comp_res_upper0_result(i);
END GENERATE loop121;
loop122 : FOR i IN 0 TO 13 GENERATE
wire_man_2comp_res_lower_w_lg_cout366w(i) <= wire_man_2comp_res_lower_cout AND wire_man_2comp_res_upper1_result(i);
END GENERATE loop122;
wire_man_2comp_res_lower_w_lg_cout367w(0) <= NOT wire_man_2comp_res_lower_cout;
loop123 : FOR i IN 0 TO 13 GENERATE
wire_man_2comp_res_lower_w_lg_w_lg_w_lg_cout367w368w369w(i) <= wire_man_2comp_res_lower_w_lg_w_lg_cout367w368w(i) OR wire_man_2comp_res_lower_w_lg_cout366w(i);
END GENERATE loop123;
man_2comp_res_lower : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => borrow_w,
clken => clk_en,
clock => clock,
cout => wire_man_2comp_res_lower_cout,
dataa => man_2comp_res_dataa_w(13 DOWNTO 0),
datab => man_2comp_res_datab_w(13 DOWNTO 0),
result => wire_man_2comp_res_lower_result
);
man_2comp_res_upper0 : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => wire_gnd,
clken => clk_en,
clock => clock,
dataa => man_2comp_res_dataa_w(27 DOWNTO 14),
datab => man_2comp_res_datab_w(27 DOWNTO 14),
result => wire_man_2comp_res_upper0_result
);
man_2comp_res_upper1 : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => wire_vcc,
clken => clk_en,
clock => clock,
dataa => man_2comp_res_dataa_w(27 DOWNTO 14),
datab => man_2comp_res_datab_w(27 DOWNTO 14),
result => wire_man_2comp_res_upper1_result
);
loop124 : FOR i IN 0 TO 13 GENERATE
wire_man_add_sub_lower_w_lg_w_lg_cout354w355w(i) <= wire_man_add_sub_lower_w_lg_cout354w(0) AND wire_man_add_sub_upper0_result(i);
END GENERATE loop124;
loop125 : FOR i IN 0 TO 13 GENERATE
wire_man_add_sub_lower_w_lg_cout353w(i) <= wire_man_add_sub_lower_cout AND wire_man_add_sub_upper1_result(i);
END GENERATE loop125;
wire_man_add_sub_lower_w_lg_cout354w(0) <= NOT wire_man_add_sub_lower_cout;
loop126 : FOR i IN 0 TO 13 GENERATE
wire_man_add_sub_lower_w_lg_w_lg_w_lg_cout354w355w356w(i) <= wire_man_add_sub_lower_w_lg_w_lg_cout354w355w(i) OR wire_man_add_sub_lower_w_lg_cout353w(i);
END GENERATE loop126;
man_add_sub_lower : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => borrow_w,
clken => clk_en,
clock => clock,
cout => wire_man_add_sub_lower_cout,
dataa => man_add_sub_dataa_w(13 DOWNTO 0),
datab => man_add_sub_datab_w(13 DOWNTO 0),
result => wire_man_add_sub_lower_result
);
man_add_sub_upper0 : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => wire_gnd,
clken => clk_en,
clock => clock,
dataa => man_add_sub_dataa_w(27 DOWNTO 14),
datab => man_add_sub_datab_w(27 DOWNTO 14),
result => wire_man_add_sub_upper0_result
);
man_add_sub_upper1 : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => wire_vcc,
clken => clk_en,
clock => clock,
dataa => man_add_sub_dataa_w(27 DOWNTO 14),
datab => man_add_sub_datab_w(27 DOWNTO 14),
result => wire_man_add_sub_upper1_result
);
loop127 : FOR i IN 0 TO 12 GENERATE
wire_man_res_rounding_add_sub_lower_w_lg_w_lg_cout580w581w(i) <= wire_man_res_rounding_add_sub_lower_w_lg_cout580w(0) AND adder_upper_w(i);
END GENERATE loop127;
loop128 : FOR i IN 0 TO 12 GENERATE
wire_man_res_rounding_add_sub_lower_w_lg_cout579w(i) <= wire_man_res_rounding_add_sub_lower_cout AND wire_man_res_rounding_add_sub_upper1_result(i);
END GENERATE loop128;
wire_man_res_rounding_add_sub_lower_w_lg_cout580w(0) <= NOT wire_man_res_rounding_add_sub_lower_cout;
loop129 : FOR i IN 0 TO 12 GENERATE
wire_man_res_rounding_add_sub_lower_w_lg_w_lg_w_lg_cout580w581w582w(i) <= wire_man_res_rounding_add_sub_lower_w_lg_w_lg_cout580w581w(i) OR wire_man_res_rounding_add_sub_lower_w_lg_cout579w(i);
END GENERATE loop129;
man_res_rounding_add_sub_lower : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 13
)
PORT MAP (
cout => wire_man_res_rounding_add_sub_lower_cout,
dataa => man_intermediate_res_w(12 DOWNTO 0),
datab => man_res_rounding_add_sub_datab_w(12 DOWNTO 0),
result => wire_man_res_rounding_add_sub_lower_result
);
man_res_rounding_add_sub_upper1 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 13
)
PORT MAP (
cin => wire_vcc,
dataa => man_intermediate_res_w(25 DOWNTO 13),
datab => man_res_rounding_add_sub_datab_w(25 DOWNTO 13),
result => wire_man_res_rounding_add_sub_upper1_result
);
trailing_zeros_limit_comparator : lpm_compare
GENERIC MAP (
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 6
)
PORT MAP (
agb => wire_trailing_zeros_limit_comparator_agb,
dataa => sticky_bit_cnt_res_w,
datab => trailing_zeros_limit_w
);
END RTL; --add_flt_stratix5_latency_altfp_add_sub_5jj
--VALID FILE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_latency IS
PORT
(
clk_en : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END add_flt_stratix5_latency;
ARCHITECTURE RTL OF add_flt_stratix5_latency IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT add_flt_stratix5_latency_altfp_add_sub_5jj
PORT (
clk_en : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(31 DOWNTO 0);
add_flt_stratix5_latency_altfp_add_sub_5jj_component : add_flt_stratix5_latency_altfp_add_sub_5jj
PORT MAP (
clk_en => clk_en,
clock => clock,
datab => datab,
dataa => dataa,
result => sub_wire0
);
END RTL;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: FPM_FORMAT NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix V"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: WIDTH_DATA NUMERIC "32"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: DENORMAL_SUPPORT STRING "NO"
-- Retrieval info: CONSTANT: DIRECTION STRING "ADD"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix V"
-- Retrieval info: CONSTANT: OPTIMIZE STRING "SPEED"
-- Retrieval info: CONSTANT: PIPELINE NUMERIC "7"
-- Retrieval info: CONSTANT: REDUCED_FUNCTIONALITY STRING "NO"
-- Retrieval info: CONSTANT: WIDTH_EXP NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_MAN NUMERIC "23"
-- Retrieval info: USED_PORT: clk_en 0 0 0 0 INPUT NODEFVAL "clk_en"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL "dataa[31..0]"
-- Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL "datab[31..0]"
-- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
-- Retrieval info: CONNECT: @clk_en 0 0 0 0 clk_en 0 0 0 0
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
-- Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0
-- Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL add_flt_stratix5_latency.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL add_flt_stratix5_latency.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL add_flt_stratix5_latency.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL add_flt_stratix5_latency.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL add_flt_stratix5_latency_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
| gpl-3.0 | a96863950bfae339c26306265098a85a | 0.706585 | 2.435561 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/maps/clkand.vhd | 1 | 3,937 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: clkand
-- File: clkand.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Clock gating
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.gencomp.all;
use work.allclkgen.all;
entity clkand is
generic( tech : integer := 0;
ren : integer range 0 to 1 := 0); -- registered enable
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic;
tsten : in std_ulogic := '0'
);
end entity;
architecture rtl of clkand is
signal eni : std_ulogic;
begin
re : if ren = 1 generate
renproc : process(i)
begin
if falling_edge(i) then eni <= en; end if;
end process;
end generate;
ce : if ren = 0 generate eni <= en; end generate;
struct : if has_clkand(tech) = 1 generate
xil : if is_unisim(tech) = 1 generate
clkgate : clkand_unisim port map(I => i, en => eni, O => o);
end generate;
ut : if (tech = ut25) generate
clkgate : clkand_ut025crh port map(I => i, en => eni, O => o);
end generate;
rhl : if (tech = rhlib18t) generate
clkgate : clkand_rh_lib18t port map(I => i, en => eni, O => o, tsten => tsten);
end generate;
ut13 : if (tech = ut130) generate
clkgate : clkand_ut130hbd port map(I => i, en => eni, O => o, tsten => tsten);
end generate;
ut09 : if (tech = ut90) generate
clkgate : clkand_ut90nhbd port map(I => i, en => eni, O => o, tsten => tsten);
end generate;
n2x : if (tech = easic45) generate
clkgate : clkand_n2x port map(i => i, en => eni, o => o, tsten => tsten);
end generate;
saed : if (tech = saed32) generate
clkgate : clkand_saed32 port map(i => i, en => eni, o => o, tsten => tsten);
end generate;
rhs : if (tech = rhs65) generate
clkgate : clkand_rhs65 port map(i => i, en => eni, o => o, tsten => tsten);
end generate;
dar : if (tech = dare) generate
clkgate : clkand_dare port map(i => i, en => eni, o => o, tsten => tsten);
end generate;
end generate;
gen : if has_clkand(tech) = 0 generate
o <= i and (eni or tsten);
end generate;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use work.gencomp.all;
use work.allclkgen.all;
entity clkrand is
generic( tech : integer := 0);
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic;
tsten : in std_ulogic := '0'
);
end entity;
architecture rtl of clkrand is
signal eni : std_ulogic;
begin
ut13 : if (tech = ut130) generate
eni <= en or tsten;
clkgate : clkrand_ut130hbd port map(I => i, en => en, O => o);
end generate;
nonut13 : if (tech /= ut130) generate
clkgate : clkand generic map (tech, 1)
port map (i, en, o, tsten);
end generate;
end;
| gpl-3.0 | 62009d5d6c788c1a14138ee93033f88f | 0.587249 | 3.595434 | false | false | false | false |
ARC-Lab-UF/UAA | src/dsa.vhd | 1 | 17,139 | -- Copyright (c) 2015 University of Florida
--
-- This file is part of uaa.
--
-- uaa is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- uaa is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with uaa. If not, see <http://www.gnu.org/licenses/>.
-- Greg Stitt
-- David Wilson
-- University of Florida
-- Description:
-- The dsa entity implements a dual-strided adder similar to the architecture
-- described in the paper "High-Performance Reduction Circuits Using Deeply
-- Pipelined Operators on FPGAs" by Ling Zhuo, G.R. Morris and V.K. Prasanna (2007)
-- Used entities:
-- fifo, dsa_ctrl, add_wrapper
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.math_custom.all;
use work.flt_pkg.all;
use work.dsa_pkg.all;
-------------------------------------------------------------------------------
-- Generics Description
-- width : The width of the input and output in bits
-- add_core_name : A string representing different optimizations for the
-- actual adder core. See add_flt.vhd and flt_pkg.vhd for
-- more information.
-- use_bram : uses bram when true, uses LUTs or FFs when false
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Port Description:
-- clk : clock input
-- rst : reset input (asynchronous, active high)
-- hold_output : When asserted, this signal prevents the entity from
-- continuing past a valid output. When not asserted, the
-- output is valid for only a single cycle. This signal
-- makes it possible to stall the dsa if downstream
-- components cannot receive another input (active high)
-- ready : when asserted, the dsa is ready to accept new inputs. If not
-- asserted, external components must hold the current input or
-- it will be lost (active high)
-- end_of_group : should be asserted on the same cycle as the last input in a
-- group (active high)
-- input : dsa input
-- output : dsa output
-- valid_in : assert when the input to the dsa is valid and ready is
-- asserted (active high)
-- valid_out : asserted when the output from the dsa is valid. Unless
-- hold_output is asserted, valid_out is only asserted for
-- one cycle. (active high)
-------------------------------------------------------------------------------
entity dsa is
generic (
width : positive := 32;
add_core_name : string := "speed";
use_bram : boolean := true);
port (
clk : in std_logic;
rst : in std_logic;
hold_output : in std_logic; -- '1' keeps outputs from disappearing
ready : out std_logic; -- '1' when dsa can accept input
end_of_group : in std_logic; -- specifies last input in group
input : in std_logic_vector(width-1 downto 0);
output : out std_logic_vector(width-1 downto 0);
valid_in : in std_logic;
valid_out : out std_logic
);
end dsa;
architecture RTL of dsa is
constant ADD_LATENCY : natural := add_flt_latency(add_core_name);
constant BUFFER_DEPTH : natural := ADD_LATENCY;
type data_array is array(natural range <>) of std_logic_vector(width-1 downto 0);
type ibuf_array is array(natural range <>) of std_logic_vector(width downto 0);
type add_count_array is array(natural range <>) of std_logic_vector(bitsNeeded(ADD_LATENCY)-1 downto 0);
type sel_array is array(natural range <>) of std_logic_vector(1 downto 0);
-- adder signals
signal add_in1 : data_array(1 downto 0);
signal add_in2 : data_array(1 downto 0);
signal add_in1_sel : std_logic_vector(1 downto 0);
signal add_in2_sel : sel_array(1 downto 0);
signal add_out : data_array(1 downto 0);
signal add_en : std_logic_vector(1 downto 0);
signal add_valid_in : std_logic_vector(1 downto 0);
signal add_valid_out : std_logic_vector(1 downto 0);
signal add_count : add_count_array(1 downto 0);
-- ibuf signals
signal ibuf_in : ibuf_array(1 downto 0);
signal ibuf_out : data_array(1 downto 0);
signal ibuf_out_temp : ibuf_array(1 downto 0);
signal ibuf_rd : std_logic;
signal ibuf_wr : std_logic_vector(1 downto 0);
signal ibuf_empty : std_logic_vector(1 downto 0);
signal ibuf_full : std_logic_vector(1 downto 0);
signal ibuf_end_of_group : std_logic;
signal ibuf_next : std_logic;
signal ibuf_wr_count : integer range 0 to ADD_LATENCY*2;
-- obuf signals
signal obuf_out : data_array(1 downto 0);
signal obuf_empty : std_logic_vector(1 downto 0);
signal obuf_rd : std_logic_vector(1 downto 0);
signal obuf_wr : std_logic_vector(1 downto 0);
-- specifies index of adder that is procesing the earliest group
signal early_ctrl_id : unsigned(0 downto 0);
-- specifies which controller currently has access to the ibuf
signal ibuf_ctrl_id : unsigned(0 downto 0);
signal ctrl_done : std_logic_vector(1 downto 0);
signal ctrl_ibuf_access : std_logic_vector(1 downto 0);
signal ctrl_earliest : std_logic_vector(1 downto 0);
signal ctrl_ibuf_rd : std_logic_vector(1 downto 0);
-- signal ctrl_coalescing : std_logic_vector(1 downto 0);
signal ctrl_steady : std_logic_vector(1 downto 0);
signal ctrl_ibuf_give_up : std_logic_vector(1 downto 0);
constant C_ZERO : std_logic_vector(width-1 downto 0) := (others => '0');
begin
-- assign the output from the adder handling the earliest group
output <= obuf_out(to_integer(early_ctrl_id));
valid_out <= ctrl_done(to_integer(early_ctrl_id));
-- the DSA is ready for new inputs anytime the ibufs aren't empty
ready <= not (ibuf_full(0) and ibuf_full(1));
-- determine which controller has access to ibuf
process(clk, rst)
begin
if (rst = '1') then
-- initially give acces to controller 0
ibuf_ctrl_id <= to_unsigned(0, 1);
elsif (rising_edge(clk)) then
-- if the current ibuf controller gives up access, switch access
-- to the other controller
if (ctrl_ibuf_give_up(to_integer(ibuf_ctrl_id)) = '1') then
ibuf_ctrl_id <= ibuf_ctrl_id + 1;
end if;
end if;
end process;
-- give/take access to ibuf for each controller
ctrl_ibuf_access(0) <= not ibuf_ctrl_id(0);
ctrl_ibuf_access(1) <= ibuf_ctrl_id(0);
-- tell each controller if it is handling the earliest group. This will
-- prevent a controller from finishing until all earlier groups are done.
ctrl_earliest(0) <= not early_ctrl_id(0);
ctrl_earliest(1) <= early_ctrl_id(0);
-- specify which controller is processing the earliest group
process(clk, rst)
begin
if (rst = '1') then
-- controller 0 always handles the first group
early_ctrl_id <= to_unsigned(0, 1);
elsif (rising_edge(clk)) then
-- update the earliest controller each time the current earliest finishes
if (ctrl_done(to_integer(early_ctrl_id)) = '1') then
early_ctrl_id <= early_ctrl_id + 1;
end if;
end if;
end process;
------------------------------------------------
-- IBUF
-- combine end_of_group and the input so controller knows if data leaving
-- ibuf is the end of a group
ibuf_in(0) <= end_of_group & input;
-- force a zero into ibuf1 when a group ends in ibuf0
-- ibuf_in(1) <= end_of_group & input;
ibuf_in(1) <= end_of_group & input when not(end_of_group = '1' and ibuf_next = '0') else
end_of_group & C_ZERO;
ibuf_rd <= ctrl_ibuf_rd(0) when ctrl_ibuf_access(0) = '1' else ctrl_ibuf_rd(1);
-- write to each buffer any time the buffer isn't full and it is that
-- buffers turn
ibuf_wr(0) <= '1' when valid_in = '1' and ibuf_full(0) = '0' and ibuf_next = '0' else '0';
-- ibuf1 has to write everytime there is the end of a group otherwise
-- multiple groups can become misaligned if the size is odd. For example, there
-- could be an element from group3 on the ibuf0 output and group2 on the
-- ibuf1 output
ibuf_wr(1) <= '1' when valid_in = '1' and ibuf_full(1) = '0' and ibuf_next = '1' else
'1' when end_of_group = '1' and ibuf_wr(0) = '1' else
'1' when valid_in = '1' and ibuf_wr_count = 2*ADD_LATENCY else
'0';
-- determine which ibuf to write to next
process(clk, rst)
begin
if (rst = '1') then
ibuf_next <= '0';
ibuf_wr_count <= 0;
elsif (rising_edge(clk)) then
-- if valid write
if (ibuf_full(to_integer(unsigned'(""&ibuf_next))) = '0' and valid_in = '1') then
if (ibuf_wr_count = 2*ADD_LATENCY) then
-- if all the inputs for the fill state have already
-- arrived, force all future writes into ibuf(0)
ibuf_next <= '0';
else
-- switch ibufs for next write
ibuf_next <= not ibuf_next;
ibuf_wr_count <= ibuf_wr_count + 1;
end if;
if (end_of_group = '1') then
-- if this is the end of the group, the next ibuf should also
-- be 0 to ensure every group starts in ibuf(0)
ibuf_next <= '0';
ibuf_wr_count <= 0;
end if;
end if;
end if;
end process;
U_IBUF0 : entity work.fifo
generic map (width => width+1,
depth => BUFFER_DEPTH,
use_bram => use_bram,
same_cycle_output => true)
port map (clk => clk,
rst => rst,
rd => ibuf_rd,
wr => ibuf_wr(0),
empty => ibuf_empty(0),
full => ibuf_full(0),
input => ibuf_in(0),
output => ibuf_out_temp(0));
U_IBUF1 : entity work.fifo
generic map (width => width+1,
depth => BUFFER_DEPTH,
use_bram => use_bram,
same_cycle_output => true)
port map (clk => clk,
rst => rst,
rd => ibuf_rd,
wr => ibuf_wr(1),
empty => ibuf_empty(1),
full => ibuf_full(1),
input => ibuf_in(1),
output => ibuf_out_temp(1));
-- break up ibuf outputs into end_of_group flag and data to add
-- Note: these may be uninitialized until the first rising clock edge when
-- using block RAM
-- This has to verify that that ibuf isn't empty, otherwise an old value
-- can erroneously trigger and end of group
ibuf_end_of_group <= (ibuf_out_temp(0)(width) and not ibuf_empty(0)) or
(ibuf_out_temp(1)(width) and not ibuf_empty(1));
ibuf_out(0) <= ibuf_out_temp(0)(width-1 downto 0);
ibuf_out(1) <= ibuf_out_temp(1)(width-1 downto 0);
-- create obufs
process(clk, rst)
begin
if (rst = '1') then
obuf_out <= (others => (others => '0'));
obuf_empty <= (others => '1');
elsif (rising_edge(clk)) then
for i in 0 to 1 loop
-- if obuf is read, it no longer has valid data
if (obuf_rd(i) = '1') then
obuf_empty(i) <= '1';
end if;
-- if obuf is written to, store data and mark valid
if (obuf_wr(i) = '1') then
obuf_out(i) <= add_out(i);
obuf_empty(i) <= '0';
end if;
end loop;
end if;
end process;
-------------------------------------------------
-- Adder 0
U_CTRL0 : entity work.dsa_ctrl
generic map (add_latency => ADD_LATENCY)
port map (clk => clk,
rst => rst,
ibuf_empty => ibuf_empty,
ibuf_rd => ctrl_ibuf_rd(0),
ibuf_end_of_group => ibuf_end_of_group,
ibuf_give_up => ctrl_ibuf_give_up(0),
obuf_empty => obuf_empty(0),
obuf_rd => obuf_rd(0),
obuf_wr => obuf_wr(0),
add_en => add_en(0),
add_in1_sel => add_in1_sel(0),
add_in2_sel => add_in2_sel(0),
add_valid_in => add_valid_in(0),
add_valid_out => add_valid_out(0),
add_count => add_count(0),
hold_output => hold_output,
is_earliest => ctrl_earliest(0),
has_ibuf_access => ctrl_ibuf_access(0),
is_steady => ctrl_steady(0),
-- is_coalescing => ctrl_coalescing(0),
is_coalescing => open,
done => ctrl_done(0));
-- multiplexer for 1st adder input
add_in1(0) <= ibuf_out(0) when add_in1_sel(0) = SEL_IBUF_L else
obuf_out(0) when add_in1_sel(0) = SEL_OBUF;
-- multiplexer for 2nd adder input
add_in2(0) <= ibuf_out(1) when add_in2_sel(0) = SEL_IBUF_R else
add_out(0) when add_in2_sel(0) = SEL_ADD_OUT else
(others => '0');
U_ADD0 : entity work.add_wrapper
generic map (core_name => add_core_name,
width => width)
port map (clk => clk,
rst => rst,
en => add_en(0),
input1 => add_in1(0),
input2 => add_in2(0),
output => add_out(0),
valid_in => add_valid_in(0),
valid_out => add_valid_out(0),
count => add_count(0));
-------------------------------------------------
-- Adder 1
U_CTRL1 : entity work.dsa_ctrl
generic map (add_latency => ADD_LATENCY)
port map (clk => clk,
rst => rst,
ibuf_empty => ibuf_empty,
ibuf_rd => ctrl_ibuf_rd(1),
ibuf_end_of_group => ibuf_end_of_group,
ibuf_give_up => ctrl_ibuf_give_up(1),
obuf_empty => obuf_empty(1),
obuf_rd => obuf_rd(1),
obuf_wr => obuf_wr(1),
add_en => add_en(1),
add_in1_sel => add_in1_sel(1),
add_in2_sel => add_in2_sel(1),
add_valid_in => add_valid_in(1),
add_valid_out => add_valid_out(1),
add_count => add_count(1),
hold_output => hold_output,
is_earliest => ctrl_earliest(1),
has_ibuf_access => ctrl_ibuf_access(1),
is_steady => ctrl_steady(1),
-- is_coalescing => ctrl_coalescing(1),
is_coalescing => open,
done => ctrl_done(1));
-- multiplexer for 1st adder input
add_in1(1) <= ibuf_out(0) when add_in1_sel(1) = SEL_IBUF_L else
obuf_out(1) when add_in1_sel(1) = SEL_OBUF;
-- multiplexer for 2nd adder input
add_in2(1) <= ibuf_out(1) when add_in2_sel(1) = SEL_IBUF_R else
add_out(1) when add_in2_sel(1) = SEL_ADD_OUT else
(others => '0');
U_ADD1 : entity work.add_wrapper
generic map (core_name => add_core_name,
width => width)
port map (clk => clk,
rst => rst,
en => add_en(1),
input1 => add_in1(1),
input2 => add_in2(1),
output => add_out(1),
valid_in => add_valid_in(1),
valid_out => add_valid_out(1),
count => add_count(1));
end RTL;
| gpl-3.0 | 9d9107bb2089dbc88ddbfd03e6241f1e | 0.512399 | 3.823963 | false | false | false | false |
pedabraham/MDSM | crs/comparador.vhd | 1 | 1,243 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity comparador is
generic(
n:integer:=4
);
port(
A: in STD_LOGIC_VECTOR(n-1 downto 0);
B: in STD_LOGIC_VECTOR(n-1 downto 0);
CLK: in STD_LOGIC;
Clr : in STD_LOGIC;
Count : in STD_LOGIC_VECTOR(3 downto 0);
--A_out : out std_logic_vector(n-1 downto 0);
--B_out : out std_logic_vector(n-1 downto 0);
Bool: out STD_LOGIC
);
end comparador;
architecture Behavioral of comparador is
signal N_S : std_logic_vector(9 downto 0);
begin
process (A,B,CLK,Clr,Count)
begin
if(Clr = '1')then
N_S <= (others => '0');
Bool <= '0';--
elsif(CLK'event AND CLK = '1' ) then
if( A = B) then
N_S(conv_integer(Count)) <= '1';
else
N_S(conv_integer(Count)) <= '0';
end if;
end if;
if(N_S(4 downto 0) = "11111" )then
Bool <= '1';
else
Bool <= '0';
end if;
--A_out <= A;
--B_out <= B;
--else
-- Bool <= '0';
end process;
end Behavioral;
| mit | bc65f369d026f4aa8b5c64c53e461b0a | 0.483508 | 3.187179 | false | false | false | false |
pwsoft/fpga_examples | rtl/ttl/ttl_7486.vhd | 1 | 2,371 | -- -----------------------------------------------------------------------
--
-- Syntiac VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2018 by Peter Wendrich ([email protected])
-- http://www.syntiac.com
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
-- Quad 2-input EXOR gate
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.ttl_pkg.all;
-- -----------------------------------------------------------------------
entity ttl_7486 is
generic (
latency : integer := 1
);
port (
emuclk : in std_logic;
p1 : in ttl_t;
p2 : in ttl_t;
p3 : out ttl_t;
p4 : in ttl_t;
p5 : in ttl_t;
p6 : out ttl_t;
p8 : out ttl_t;
p9 : in ttl_t;
p10 : in ttl_t;
p11 : out ttl_t;
p12 : in ttl_t;
p13 : in ttl_t
);
end entity;
architecture rtl of ttl_7486 is
signal p3_loc : ttl_t;
signal p6_loc : ttl_t;
signal p8_loc : ttl_t;
signal p11_loc : ttl_t;
begin
p3_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p3_loc, q => p3);
p6_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p6_loc, q => p6);
p8_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p8_loc, q => p8);
p11_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p11_loc, q => p11);
p3_loc <= p1 xor p2;
p6_loc <= p4 xor p5;
p8_loc <= p9 xor p10;
p11_loc <= p12 xor p13;
end architecture;
| lgpl-2.1 | 2596fd55ca74b7091405dcb8db974341 | 0.56221 | 3.283934 | false | false | false | false |
pwsoft/fpga_examples | rtl/audio/audio_sigmadelta_dac.vhd | 1 | 2,283 | -- -----------------------------------------------------------------------
--
-- Syntiac VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2009 by Peter Wendrich ([email protected])
-- http://www.syntiac.com
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
--
-- Audio sigmadelta first order 1 bit converter
--
-- -----------------------------------------------------------------------
-- audioBits - Resolution of audio signal in bits
-- clk - system clock
-- clkena - system clock enable
-- d - signed audio input
-- q - sigma-delta bitstream output
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- -----------------------------------------------------------------------
entity audio_sigmadelta_dac is
generic (
audioBits : integer := 16
);
port (
clk : in std_logic;
clkena : in std_logic := '1';
d : in signed(audioBits-1 downto 0);
q : out std_logic
);
end entity;
-- -----------------------------------------------------------------------
architecture rtl of audio_sigmadelta_dac is
signal accumulator : unsigned(d'high downto 0) := (others => '0');
begin
process(clk)
variable t : unsigned(d'length downto 0);
begin
if rising_edge(clk) then
t := unsigned('0' & (not d(d'high)) & d(d'high-1 downto 0)) + ('0' & accumulator);
if clkena = '1' then
accumulator <= t(accumulator'range);
q <= t(t'high);
end if;
end if;
end process;
end architecture;
| lgpl-2.1 | d1cf8518ec4d595babf5b5b0182779a9 | 0.528252 | 4.227778 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/irqmp/irqmp.vhd | 1 | 16,161 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: irqmp
-- File: irqmp.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Multi-processor APB interrupt controller. Implements a
-- two-level interrupt controller for 15 interrupts.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.leon3.all;
entity irqmp is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ncpu : integer := 1;
eirq : integer := 0;
irqmap : integer := 0;
bootreg : integer := 1
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
irqi : in irq_out_vector(0 to ncpu-1);
irqo : out irq_in_vector(0 to ncpu-1)
);
end;
architecture rtl of irqmp is
constant REVISION : integer := 4;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_IRQMP, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
function IMAP_HIGH return integer is
begin
if irqmap = 0 then
return 0;
elsif eirq /= 0 or irqmap = 2 then
return 31;
end if;
return 15;
end function IMAP_HIGH;
constant IMAP_LOW : integer := 0; -- allow remap of irq line 0
function IMAP_LEN return integer is
begin
if irqmap = 0 then
return 1;
elsif eirq /= 0 then
return 5;
end if;
return 4;
end function IMAP_LEN;
type mask_type is array (0 to ncpu-1) of std_logic_vector(15 downto 1);
type mask2_type is array (0 to ncpu-1) of std_logic_vector(15 downto 0);
type irl_type is array (0 to ncpu-1) of std_logic_vector(3 downto 0);
type irl2_type is array (0 to ncpu-1) of std_logic_vector(4 downto 0);
type irqmap_type is array (IMAP_LOW to (IMAP_HIGH)) of std_logic_vector(IMAP_LEN-1 downto 0);
type reg_type is record
imask : mask_type;
ilevel : std_logic_vector(15 downto 1);
ipend : std_logic_vector(15 downto 1);
iforce : mask_type;
ibroadcast : std_logic_vector(15 downto 1);
irl : irl_type;
cpurst : std_logic_vector(ncpu-1 downto 0);
imap : irqmap_type;
setaddr : std_logic_vector(ncpu-1 downto 0);
newaddr : std_logic_vector(31 downto 2);
setaddrboot : std_ulogic;
forceerr : std_logic_vector(ncpu-1 downto 0);
clkcount : std_logic_vector(2 downto 0);
end record;
type ereg_type is record
imask : mask2_type;
ipend : std_logic_vector(15 downto 0);
irl : irl2_type;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RRES : reg_type := (
imask => (others => (others => '0')), ilevel => (others => '0'),
ipend => (others => '0'), iforce => (others => (others => '0')),
ibroadcast => (others => '0'), irl => (others => (others => '0')),
cpurst => (others => '0'), imap => (others => (others => '0')),
setaddr => (others => '0'), newaddr => (others => '0'), setaddrboot => '0',
forceerr => (others => '0'), clkcount => "000");
constant ERES : ereg_type := (
imask => (others => (others => '0')), ipend => (others => '0'),
irl => (others => (others => '0')));
function prioritize(b : std_logic_vector(15 downto 0)) return std_logic_vector is
variable a : std_logic_vector(15 downto 0);
variable irl : std_logic_vector(3 downto 0);
variable level : integer range 0 to 15;
begin
irl := "0000"; level := 0; a := b;
for i in 15 downto 0 loop
level := i;
if a(i) = '1' then exit; end if;
end loop;
irl := conv_std_logic_vector(level, 4);
return(irl);
end;
signal r, rin : reg_type;
signal r2, r2in : ereg_type;
begin
comb : process(rst, r, r2, apbi, irqi)
variable v : reg_type;
variable temp : mask_type;
variable prdata : std_logic_vector(31 downto 0);
variable tmpirq : std_logic_vector(15 downto 0);
variable tmpvar : std_logic_vector(15 downto 1);
variable cpurun : std_logic_vector(ncpu-1 downto 0);
variable v2 : ereg_type;
variable irl2 : std_logic_vector(3 downto 0);
variable ipend2 : std_logic_vector(ncpu-1 downto 0);
variable temp2 : mask2_type;
variable irq : std_logic_vector(NAHBIRQ-1 downto 0);
variable vcpu : std_logic_vector(3 downto 0);
variable bootreg_sel : std_ulogic;
variable paddr : std_logic_vector(19 downto 2);
begin
v := r; v.cpurst := (others => '0');
cpurun := (others => '0'); cpurun(0) := '1';
tmpvar := (others => '0'); ipend2 := (others => '0');
v2 := r2;
paddr := apbi.paddr(19 downto 2);
paddr(19 downto 8) := paddr(19 downto 8) and not std_logic_vector(to_unsigned(pmask,12));
-- prioritize interrupts
if eirq /= 0 then
for i in 0 to ncpu-1 loop
temp2(i) := r2.ipend and r2.imask(i);
ipend2(i) := orv(temp2(i));
end loop;
end if;
for i in 0 to ncpu-1 loop
temp(i) := ((r.iforce(i) or r.ipend) and r.imask(i));
if eirq /= 0 then temp(i)(eirq) := temp(i)(eirq) or ipend2(i); end if;
v.irl(i) := prioritize((temp(i) and r.ilevel) & '0');
if v.irl(i) = "0000" then
if eirq /= 0 then temp(i)(eirq) := temp(i)(eirq) or ipend2(i); end if;
v.irl(i) := prioritize((temp(i) and not r.ilevel) & '0');
end if;
end loop;
if bootreg /= 0 then
if r.clkcount/="000" then
v.clkcount := std_logic_vector(unsigned(r.clkcount)-1);
end if;
end if;
-- register read
prdata := (others => '0');
case apbi.paddr(7 downto 6) is
when "00" =>
case apbi.paddr(4 downto 2) is
when "000" => prdata(15 downto 1) := r.ilevel;
when "001" =>
prdata(15 downto 1) := r.ipend;
if eirq /= 0 then prdata(31 downto 16) := r2.ipend; end if;
when "010" => prdata(15 downto 1) := r.iforce(0);
when "011" =>
when "100" | "101" =>
prdata(31 downto 28) := conv_std_logic_vector(ncpu-1, 4);
prdata(19 downto 16) := conv_std_logic_vector(eirq, 4);
for i in 0 to ncpu -1 loop prdata(i) := irqi(i).pwd; end loop;
if ncpu > 1 then
prdata(27) := '1';
case apbi.paddr(4 downto 2) is
when "101" =>
prdata := (others => '0');
prdata(15 downto 1) := r.ibroadcast;
when others =>
end case;
end if;
if bootreg /= 0 then
prdata(26) := '1';
end if;
when "110" =>
for i in 0 to ncpu-1 loop prdata(i):=irqi(i).err; end loop;
when others =>
end case;
when "01" =>
for i in 0 to ncpu-1 loop
if i = conv_integer( apbi.paddr(5 downto 2)) then
prdata(15 downto 1) := r.imask(i);
if eirq /= 0 then prdata(31 downto 16) := r2.imask(i); end if;
end if;
end loop;
when "10" =>
for i in 0 to ncpu-1 loop
if i = conv_integer( apbi.paddr(5 downto 2)) then
prdata(15 downto 1) := r.iforce(i);
end if;
end loop;
when "11" =>
if eirq /= 0 then
for i in 0 to ncpu-1 loop
if i = conv_integer( apbi.paddr(5 downto 2)) then
prdata(4 downto 0) := r2.irl(i);
end if;
end loop;
end if;
when others =>
end case;
-- register write
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' and
((irqmap = 0 and bootreg=0) or paddr(9 downto 8) = "00") then
case apbi.paddr(7 downto 6) is
when "00" =>
case apbi.paddr(4 downto 2) is
when "000" => v.ilevel := apbi.pwdata(15 downto 1);
when "001" => v.ipend := apbi.pwdata(15 downto 1);
if eirq /= 0 then v2.ipend := apbi.pwdata(31 downto 16); end if;
when "010" => v.iforce(0) := apbi.pwdata(15 downto 1);
when "011" => v.ipend := r.ipend and not apbi.pwdata(15 downto 1);
if eirq /= 0 then v2.ipend := r2.ipend and not apbi.pwdata(31 downto 16); end if;
when "100" =>
for i in 0 to ncpu -1 loop v.cpurst(i) := apbi.pwdata(i); end loop;
when "110" =>
if bootreg /= 0 then
v.forceerr := v.forceerr or apbi.pwdata(ncpu-1 downto 0);
v.clkcount := "111";
end if;
when others =>
if ncpu > 1 then
case apbi.paddr(4 downto 2) is
when "101" =>
v.ibroadcast := apbi.pwdata(15 downto 1);
when others =>
end case;
end if;
end case;
when "01" =>
for i in 0 to ncpu-1 loop
if i = conv_integer( apbi.paddr(5 downto 2)) then
v.imask(i) := apbi.pwdata(15 downto 1);
if eirq /= 0 then v2.imask(i) := apbi.pwdata(31 downto 16); end if;
end if;
end loop;
when "10" =>
for i in 0 to ncpu-1 loop
if i = conv_integer( apbi.paddr(5 downto 2)) then
v.iforce(i) := (r.iforce(i) or apbi.pwdata(15 downto 1)) and
not apbi.pwdata(31 downto 17);
end if;
end loop;
when others =>
end case;
end if;
-- implement processor reboot / monitor regs
vcpu := apbi.paddr(5 downto 2);
bootreg_sel := '0';
if bootreg /= 0 then
if r.clkcount="000" then
if orv(r.setaddr)='1' then
if r.newaddr(2)='0' then
v.newaddr(2):='1';
else
if r.setaddrboot='1' then
v.cpurst := v.cpurst or r.setaddr;
end if;
v.setaddr := (others => '0');
end if;
end if;
for i in 0 to ncpu-1 loop
v.forceerr(i) := v.forceerr(i) and not irqi(i).err;
end loop;
end if;
-- Alias bootregs into 256B space if ncpu <= 8
if paddr(9 downto 6)="1000" then bootreg_sel:='1'; end if;
if ncpu <= 8 and paddr(9 downto 6)="0001" and apbi.paddr(5)='1' then
bootreg_sel := '1';
end if;
if ncpu <= 8 then vcpu(3):='0'; end if;
if (apbi.psel(pindex) and apbi.penable)='1' and bootreg_sel='1' then
-- Reg read
prdata := (others => '0');
-- Reg write
if apbi.pwrite='1' then
for i in 0 to ncpu-1 loop
if i = conv_integer( vcpu) then
v.setaddr(i) := '1';
v.setaddrboot := apbi.pwdata(0);
end if;
end loop;
v.newaddr := apbi.pwdata(31 downto 3) & "0";
v.clkcount := "111";
end if; -- pwrite
end if; -- psel/paddr
end if; -- bootreg/=0
-- optionally remap interrupts
irq := (others => '0');
if irqmap /= 0 then
if (apbi.psel(pindex) and apbi.penable)='1' and apbi.paddr(9 downto 8) = "11" then
prdata := (others => '0');
for i in r.imap'range loop
if i/4 = conv_integer(apbi.paddr(4 downto 2)) then
prdata(IMAP_LEN-1+(24-(i mod 4)*8) downto (24-(i mod 4)*8)) := r.imap(i);
if apbi.pwrite = '1' then
v.imap(i) := apbi.pwdata(IMAP_LEN-1+(24-(i mod 4)*8) downto (24-(i mod 4)*8));
end if;
end if;
end loop;
end if;
for i in 0 to IMAP_HIGH loop
if i > NAHBIRQ-1 then
exit;
end if;
if apbi.pirq(i) = '1' then
irq(conv_integer(r.imap(i))) := '1';
end if;
end loop;
else
irq := apbi.pirq;
v.imap := RRES.IMAP;
end if;
-- register new interrupts
for i in 1 to 15 loop
if i > NAHBIRQ-1 then
exit;
end if;
if ncpu = 1 then
v.ipend(i) := v.ipend(i) or irq(i);
else
v.ipend(i) := v.ipend(i) or (irq(i) and not r.ibroadcast(i));
for j in 0 to ncpu-1 loop
tmpvar := v.iforce(j);
tmpvar(i) := tmpvar(i) or (irq(i) and r.ibroadcast(i));
v.iforce(j) := tmpvar;
end loop;
end if;
end loop;
if eirq /= 0 then
for i in 16 to 31 loop
if i > NAHBIRQ-1 then exit; end if;
v2.ipend(i-16) := v2.ipend(i-16) or irq(i);
end loop;
end if;
-- interrupt acknowledge
for i in 0 to ncpu-1 loop
if irqi(i).intack = '1' then
tmpirq := decode(irqi(i).irl);
temp(i) := tmpirq(15 downto 1);
v.iforce(i) := v.iforce(i) and not temp(i);
v.ipend := v.ipend and not ((not r.iforce(i)) and temp(i));
if eirq /= 0 then
if eirq = conv_integer(irqi(i).irl) then
v2.irl(i) := orv(temp2(i)) & prioritize(temp2(i));
if v2.irl(i)(4) = '1' then
v2.ipend(conv_integer(v2.irl(i)(3 downto 0))) := '0';
end if;
end if;
end if;
end if;
end loop;
-- reset
if (not RESET_ALL) and (rst = '0') then
v.imask := RRES.imask; v.iforce := RRES.iforce; v.ipend := RRES.ipend;
if ncpu > 1 then
v.ibroadcast := RRES.ibroadcast;
end if;
if irqmap /= 0 then
for i in r.imap'range loop
v.imap(i) := conv_std_logic_vector(i, IMAP_LEN);
end loop;
end if;
v.forceerr := RRES.forceerr;
v.setaddr := RRES.setaddr;
v2.ipend := ERES.ipend; v2.imask := ERES.imask; v2.irl := ERES.irl;
end if;
if bootreg=0 then
v.forceerr := RRES.forceerr;
v.setaddr := RRES.setaddr;
v.newaddr := RRES.newaddr;
end if;
apbo.prdata <= prdata;
for i in 0 to ncpu-1 loop
irqo(i).irl <= r.irl(i); irqo(i).resume <= r.cpurst(i);
irqo(i).forceerr <= r.forceerr(i);
irqo(i).pwdsetaddr <= r.setaddr(i);
irqo(i).pwdnewaddr <= r.newaddr;
irqo(i).rstrun <= cpurun(i);
irqo(i).rstvec <= (others => '0'); -- Alternate reset vector
irqo(i).index <= conv_std_logic_vector(i, 4);
end loop;
rin <= v; r2in <= v2;
end process;
apbo.pirq <= (others => '0');
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
if RESET_ALL and (rst = '0') then r <= RRES; end if;
end if;
end process;
dor2regs : if eirq /= 0 generate
regs : process(clk)
begin
if rising_edge(clk) then
r2 <= r2in;
if RESET_ALL and (rst = '0') then r2 <= ERES; end if;
end if;
end process;
end generate;
nor2regs : if eirq = 0 generate
-- r2 <= ((others => "0000000000000000"), "0000000000000000", (others => "00000"));
r2.ipend <= (others => '0');
driveregs: for i in 0 to (ncpu-1) generate
r2.imask(i) <= (others => '0');
r2.irl(i) <= (others => '0');
end generate driveregs;
end generate;
-- pragma translate_off
bootmsg : report_version
generic map ("irqmp" &
": Multi-processor Interrupt Controller rev " & tost(REVISION) &
", #cpu " & tost(NCPU) & ", eirq " & tost(eirq));
-- pragma translate_on
-- pragma translate_off
cproc : process
begin
assert (irqmap = 0) or (apb_membar_size(pmask) >= 1024)
report "IRQMP: irqmap /= 0 requires pmask to give memory area >= 1024 bytes"
severity failure;
wait;
end process;
-- pragma translate_on
end;
| gpl-3.0 | 86d0aefc7f34f995d1b068197eac1559 | 0.556772 | 3.265508 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-avnet-eval-xc4vlx60/testbench.vhd | 1 | 9,292 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
use work.config.all; -- configuration
use work.debug.all;
use std.textio.all;
library grlib;
use grlib.stdlib.all;
use grlib.stdio.all;
use grlib.devices.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 10; -- system clock period
romwidth : integer := 16; -- rom data width (8/32)
romdepth : integer := 16 -- rom address depth
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal rst : std_logic := '1'; -- Reset
signal rstn: std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(22 downto 0);
signal data : std_logic_vector(31 downto 0);
signal romsn : std_logic_vector(1 downto 0);
signal oen : std_ulogic;
signal writen : std_ulogic;
signal iosn : std_ulogic;
-- ddr memory
signal ddr_clk : std_logic;
signal ddr_clkb : std_logic;
signal ddr_clk_fb : std_logic;
signal ddr_cke : std_logic;
signal ddr_csb : std_logic;
signal ddr_web : std_ulogic; -- ddr write enable
signal ddr_rasb : std_ulogic; -- ddr ras
signal ddr_casb : std_ulogic; -- ddr cas
signal ddr_dm : std_logic_vector (1 downto 0); -- ddr dm
signal ddr_dqs : std_logic_vector (1 downto 0); -- ddr dqs
signal ddr_ad : std_logic_vector (12 downto 0); -- ddr address
signal ddr_ba : std_logic_vector (1 downto 0); -- ddr bank address
signal ddr_dq : std_logic_vector (15 downto 0); -- ddr data
signal brdyn : std_ulogic;
signal bexcn : std_ulogic;
signal wdog : std_ulogic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal rtsn, ctsn : std_ulogic;
signal error : std_logic;
signal pio : std_logic_vector(15 downto 0);
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal clk50 : std_ulogic := '1';
signal clk_200p : std_ulogic := '0';
signal clk_200n : std_ulogic := '1';
signal plllock : std_ulogic;
-- pulled up high, therefore std_logic
signal txd1, rxd1 : std_logic;
signal eth_macclk, etx_clk, erx_clk, erx_dv, erx_er, erx_col, erx_crs, etx_en, etx_er : std_logic := '0';
signal erxd, etxd : std_logic_vector(3 downto 0) := (others => '0');
signal erxdt, etxdt : std_logic_vector(7 downto 0) := (others => '0');
signal emdc, emdio : std_logic; --dummy signal for the mdc,mdio in the phy which is not used
constant lresp : boolean := false;
signal resoutn : std_logic;
signal dsubren : std_ulogic;
signal dsuactn : std_ulogic;
begin
dsubren <= not dsubre;
-- clock and reset
clk <= not clk after ct * 1 ns;
clk50 <= not clk50 after 10 ns;
clk_200p <= not clk_200p after 2.5 ns;
clk_200n <= not clk_200n after 2.5 ns;
rst <= '1', '0' after 1000 ns;
rstn <= not rst;
dsuen <= '0'; dsubre <= '0'; rxd1 <= 'H';
address(0) <= '0';
ddr_dqs <= (others => 'L');
d3 : entity work.leon3mp
port map (
resetn => rst,
resoutn => resoutn,
clk_100mhz => clk,
clk_50mhz => clk50,
clk_200p => clk_200p,
clk_200n => clk_200n,
errorn => error,
address => address(22 downto 1),
data => data(31 downto 16),
testdata => data(15 downto 0),
ddr_clk0 => ddr_clk,
ddr_clk0b => ddr_clkb,
ddr_clk_fb => ddr_clk_fb,
ddr_cke0 => ddr_cke,
ddr_cs0b => ddr_csb,
ddr_web => ddr_web,
ddr_rasb => ddr_rasb,
ddr_casb => ddr_casb,
ddr_dm => ddr_dm,
ddr_dqs => ddr_dqs,
ddr_ad => ddr_ad,
ddr_ba => ddr_ba,
ddr_dq => ddr_dq,
sertx => dsutx,
serrx => dsurx,
rtsn => rtsn,
ctsn => ctsn,
dsuen => dsuen,
dsubre => dsubre,
dsuact => dsuactn,
oen => oen,
writen => writen,
iosn => iosn,
romsn => romsn(0),
emdio => emdio,
etx_clk => etx_clk,
erx_clk => erx_clk,
erxd => erxd,
erx_dv => erx_dv,
erx_er => erx_er,
erx_col => erx_col,
erx_crs => erx_crs,
etxd => etxd,
etx_en => etx_en,
etx_er => etx_er,
emdc => emdc
);
ddr_clk_fb <= ddr_clk;
ddr0: ddrram
generic map (width => 16, abits => 13, colbits => 9, rowbits => 12, implbanks => 1,
fname => sdramfile, lddelay => (300 us)*CFG_MIG_DDR2)
port map (
ck => ddr_clk, cke => ddr_cke, csn => ddr_csb,
rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web,
dm => ddr_dm, ba => ddr_ba, a => ddr_ad, dq => ddr_dq, dqs => ddr_dqs);
prom0 : for i in 0 to (romwidth/8)-1 generate
sr0 : sram generic map (index => i+4, abits => romdepth, fname => promfile)
port map (address(romdepth downto 1), data(31-i*8 downto 24-i*8), romsn(0),
writen, oen);
end generate;
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
erxd <= erxdt(3 downto 0);
etxdt <= "0000" & etxd;
p0: phy
generic map(base1000_t_fd => 0, base1000_t_hd => 0, address => 3)
port map(resoutn, emdio, etx_clk, erx_clk, erxdt, erx_dv,
erx_er, erx_col, erx_crs, etxdt, etx_en, etx_er, emdc, eth_macclk);
end generate;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 5 us;
assert (to_X01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure;
end process;
test0 : grtestmod
port map ( rstn, clk, error, address(21 downto 2), data,
iosn, oen, writen, brdyn);
data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#ef#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
--
-- txc(dsutx, 16#80#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end;
| gpl-3.0 | e878dc746c59fd722bad696568d05edf | 0.54251 | 3.41116 | false | false | false | false |
firecake/IRIS | FPGA/VHDL/vhdl/IRISv2.vhd | 1 | 12,216 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.Iris_pack.all;
entity IRIS is
port(
Clk : in std_logic; -- 40MHz clock
-- FT2232H interface
FT2232_FSClk : out std_logic;
FT2232_FSDO : in std_logic;
FT2232_FSDI : out std_logic;
FT2232_FSCTS : in std_logic;
-- ADC interface
ADC_Sck : out std_logic;
ADC_Cnv : out std_logic;
ADC_Data : in std_logic;
-- TCD1304 interface
TCD_Clk : out std_logic;
TCD_ICG : out std_logic;
TCD_SH : out std_logic
);
end entity;
architecture A1 of IRIS is
type FTState is ( S_Idle, S_Read_Byte, S_Decode, S_Read_RAM, S_Wait_CTS, S_Send_Word );
signal FT_current_state : FTstate := S_Idle;
type AState is ( S_Acq, S_Wait_ICG_To_SH, S_Wait_SH, S_Wait_ICG, S_Pix_Setup, S_Start_Conv, S_Wait_Conv, S_Clock_ADC, S_Get_ADC_Data, S_Complete );
signal Acq_current_state : Astate := S_Acq;
signal iClk : std_logic;
signal iADC_SCK : std_logic := '0';
signal iTCD_Clk : std_logic := '0';
signal iTCD_ICG : std_logic := '0';
signal iTCD_SH : std_logic := '0';
signal Data : std_logic_vector(15 downto 0) := ( others => '0' );
-- Counters
signal iClk_cpt : std_logic_vector(15 downto 0) := ( others => '0' );
signal Tempo_cpt : integer := 0;
signal Pix_cpt : integer := 0;
signal ADC_Bit_cpt : integer := 0;
-- RAM
signal iFT2232_FSClk : std_logic;
signal RAMA_Wr : std_logic_vector(0 downto 0) := (others => '0');
signal RAMA_Addr : std_logic_vector(11 downto 0) := (others => '0');
signal RAMA_Din : std_logic_vector(31 downto 0) := (others => '0');
signal RAMA_Dout : std_logic_vector(31 downto 0);
signal RAMB_Wr : std_logic_vector(0 downto 0) := (others => '0');
signal RAMB_Addr : std_logic_vector(11 downto 0) := (others => '0');
signal RAMB_Din : std_logic_vector(31 downto 0) := (others => '0');
signal RAMB_Dout : std_logic_vector(31 downto 0);
-- Rx / Tx
signal Rx_Data0 : std_logic_vector(7 downto 0) := ( others => '0' );
signal Rx_Bit_Cpt : std_logic_vector(2 downto 0) := ( others => '0' );
signal Tx_Data : std_logic_vector(9 downto 0) := ( others => '0' );
signal Word_Cpt : integer := 0;
signal Byte_Cpt : integer := 0;
signal Bit_cpt : integer := 0;
-- Acq parameters
signal Int_cpt : std_logic_vector(15 downto 0) := ( others => '0' );
signal Int_Time : std_logic_vector(7 downto 0) := ( others => '0' );
signal Start_Acq : std_logic := '0';
signal Send_Packet : std_logic := '1';
signal iReset_n : std_logic;
signal Capture : std_logic;
begin
--------------------------------------------------------------------------------------------------
--
-- Clock management
--
--------------------------------------------------------------------------------------------------
Clk_Man: Clk_Manager PORT MAP(
CLKIN_IN => Clk,
CLKIN_IBUFG_OUT => iFT2232_FSClk,
Clk0_OUT => iClk,
LOCKED_OUT => iReset_n
);
FT2232_FSClk <= not iFT2232_FSClk;
--
-- Command Format
-- -------------------------
-- | 7 0 |
-- -------------------------
-- Integration time
-- Data format :
--
-- ---------------------------------------------------------------------------
-- | STX | Data0 MSB | Data0 LSB | ... | Data 4095 MSB | Data 4095 LSB | CRC |
-- ---------------------------------------------------------------------------
--
FT2232H_manager: process( iReset_n, iClk )
begin
if iReset_n = '0'
then
FT_current_state <= S_Idle;
FT2232_FSDI <= '1';
Int_Time <= conv_std_logic_vector(0,8);
Start_Acq <= '0';
Rx_Data0 <= ( others => '1');
Rx_Bit_Cpt <= ( others => '0');
Tx_Data <= ( others => '1');
Bit_cpt <= 0;
Word_Cpt <= 0;
else
if iClk='1' and iClk'event
then
case FT_current_state is
when S_Idle =>
FT2232_FSDI <= '1';
RAMB_Addr <= ( others => '0' );
if FT2232_FSDO = '0'
then Rx_Bit_Cpt <= conv_std_logic_vector(0,3);
FT_current_state <= S_Read_Byte;
else
if FT2232_FSCTS = '1' and Send_Packet = '1'
then Start_Acq <= '0';
Word_Cpt <= 0;
FT_current_state <= S_Read_RAM;
end if;
end if;
------------------------------------------------------------------------------
-- Receive Rx_Data
------------------------------------------------------------------------------
when S_Read_Byte =>
Rx_Data0(conv_integer(Rx_Bit_Cpt)) <= FT2232_FSDO;
Rx_Bit_Cpt <= Rx_Bit_Cpt + 1;
if Rx_Bit_Cpt = 7
then FT_current_state <= S_Decode;
end if;
when S_Decode =>
Start_Acq <= '1';
Int_Time <= Rx_Data0(7 downto 0);
FT_current_state <= S_Idle;
------------------------------------------------------------------------------
-- Send Packet
------------------------------------------------------------------------------
when S_Read_RAM => FT2232_FSDI <= '1';
Byte_Cpt <= 0;
Bit_cpt <= 0;
RAMB_Addr <= conv_std_logic_vector(Word_Cpt,12);
FT_current_state <= S_Wait_CTS;
when S_Wait_CTS => FT2232_FSDI <= '1';
--Tx_Data <= '0' & conv_std_logic_vector(Byte_Cpt,8) & '0' ;
Tx_Data <= '0' & RAMB_Dout(8*(Byte_Cpt+1)-1 downto 8*Byte_Cpt) & '0';
if FT2232_FSCTS = '1'
then FT_current_state <= S_Send_Word;
end if;
when S_Send_Word =>
FT2232_FSDI <= Tx_Data(Bit_cpt);
Bit_cpt <= Bit_cpt + 1;
if Bit_cpt = 9
then
Bit_cpt <= 0;
Byte_Cpt <= Byte_Cpt + 1;
if Byte_Cpt = 3
then
Byte_Cpt <= 0;
Word_Cpt <= Word_Cpt + 1;
FT_current_state <= S_Read_RAM;
if Word_Cpt = 4095
then Start_Acq <= '0';
FT_current_state <= S_Idle;
end if;
else FT_current_state <= S_Wait_CTS;
end if;
end if;
when others => FT_current_state <= S_Idle;
end case;
end if;
end if;
end process;
--------------------------------------------------------------------------------------------------
--
-- Acquisition
--
--------------------------------------------------------------------------------------------------
ADC_SCK <= iADC_SCK;
Acq: process(iReset_n, iClk)
begin
if iReset_n = '0'
then
Acq_current_state <= S_Acq;
Int_cpt <= ( others => '0' );
iTCD_Clk <= '1';
iTCD_ICG <= '1';
iTCD_SH <= '0';
Tempo_cpt<= 0;
Pix_cpt<= 0;
ADC_Bit_cpt<= 0;
iADC_SCK <= '0';
ADC_Cnv <= '0';
Data <= ( others => '0' );
RAMA_Wr(0) <= '0';
Send_Packet <= '0';
capture <= '0';
else
if iClk='1' and iClk'event
then
iClk_cpt <= iClk_cpt + 1;
if iClk_cpt = 9
then
iClk_cpt<= ( others => '0' );
iTCD_Clk <= not iTCD_Clk;
end if;
case Acq_current_state is
when S_Acq =>
iTCD_ICG <= '0';
Send_Packet <= '0';
Tempo_cpt<= 0;
iClk_cpt<= ( others => '0' );
Acq_current_state <= S_Wait_ICG_To_SH;
when S_Wait_ICG_To_SH =>
if Start_Acq = '1' and capture ='0'
then capture <= '1';
end if;
Tempo_cpt <= Tempo_cpt + 1;
if Tempo_cpt = 19
then
iTCD_SH <= '1';
Tempo_cpt<= 0;
Acq_current_state <= S_Wait_SH;
end if;
when S_Wait_SH =>
Tempo_cpt <= Tempo_cpt + 1;
if Tempo_cpt = 199
then
iTCD_SH <= '0';
Tempo_cpt<= 0;
Acq_current_state <= S_Wait_ICG;
end if;
when S_Wait_ICG =>
Tempo_cpt <= Tempo_cpt + 1;
if Tempo_cpt = 199
then
iTCD_ICG <= '1';
Tempo_cpt<= 0;
Pix_cpt<= 0;
Acq_current_state <= S_Pix_Setup;
end if;
when S_Pix_Setup =>
RAMA_Addr <= conv_std_logic_vector(Pix_cpt,12);
Tempo_cpt <= Tempo_cpt + 1;
if Tempo_cpt = 31
then
ADC_Cnv <= '1';
Acq_current_state <= S_Start_conv;
end if;
when S_Start_conv =>
ADC_Cnv <= '0';
Tempo_cpt <= 0;
Acq_current_state <= S_Wait_Conv;
when S_Wait_Conv =>
Tempo_cpt <= Tempo_cpt + 1;
if Tempo_cpt = 14
then
Data(15) <= ADC_Data;
ADC_Bit_cpt <= 14;
Acq_current_state <= S_Clock_ADC;
end if;
when S_Clock_ADC =>
iADC_SCK <= not iADC_SCK;
Acq_current_state <= S_Get_ADC_Data;
when S_Get_ADC_Data =>
iADC_SCK <= not iADC_SCK;
ADC_Bit_cpt <= ADC_Bit_cpt - 1;
Data(ADC_Bit_cpt) <= ADC_Data;
Acq_current_state <= S_Clock_ADC;
if ADC_Bit_cpt = 0
then Tempo_cpt<= 0;
if Capture = '1' then
if Int_cpt = 0
then RAMA_Din <= X"0000" & Data(15 downto 1) & ADC_Data;
else RAMA_Din <= ( X"0000" & Data(15 downto 1) & ADC_Data ) + RAMA_Dout;
end if;
end if;
Acq_current_state <= S_Complete;
end if;
when S_Complete =>
RAMA_Wr(0) <= '1';
if Tempo_cpt = 1
then RAMA_Wr(0) <= '0';
end if;
Tempo_cpt <= Tempo_cpt + 1;
if Tempo_cpt = 1
then
Tempo_cpt<= 0;
Pix_cpt <= Pix_cpt + 1;
if Pix_cpt = NB_PIXELS
then
if Capture = '1'
then
Int_cpt <= Int_cpt + 1;
if Int_cpt = Int_Time
then Int_cpt <= ( others => '0' );
Capture <= '0';
Send_Packet <= '1';
end if;
end if;
Acq_current_state <= S_Acq;
else Acq_current_state <= S_Pix_Setup;
end if;
end if;
when others => Acq_current_state <= S_Acq;
end case;
end if;
end if;
end process;
--
-- TCD1304 signals
--
TCD_Clk <= iTCD_Clk ;
TCD_ICG <= iTCD_ICG;
TCD_SH <= iTCD_SH;
--
-- RAM
--
RAMB_Wr(0) <= '0';
RAMB_Din <= ( others => '0' );
Memory: RAM PORT MAP (
Clka => iClk,
wea => RAMA_Wr,
addra => RAMA_Addr,
dina => RAMA_Din,
douta => RAMA_Dout,
Clkb => iClk,
web => RAMB_Wr,
addrb => RAMB_Addr,
dinb => RAMB_Din,
doutb => RAMB_Dout
);
end A1;
| gpl-3.0 | 10bcc73403357fe37c0aeaf6d6ac77f5 | 0.391372 | 3.556332 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-xilinx-ml510/leon3mp.vhd | 1 | 58,226 | -----------------------------------------------------------------------------
-- LEON3/LEON4 Demonstration design
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.i2c.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.pci.all;
use gaisler.ddrpkg.all;
use gaisler.l2cache.all;
use gaisler.subsys.all;
library esa;
use esa.memoryctrl.all;
use esa.pcicomp.all;
use work.config.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.IBUFDS;
-- pragma translate_on
-- pragma translate_on
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
transtech : integer := CFG_TRANSTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
fpga_cpu_reset_b : in std_ulogic;
user_clksys : in std_ulogic; -- 100 MHz main clock
sysace_fpga_clk : in std_ulogic; -- 33 MHz
-- Flash
flash_we_b : out std_ulogic;
flash_wait : in std_ulogic;
flash_reset_b : out std_ulogic;
flash_oe_b : out std_ulogic;
flash_d : inout std_logic_vector(15 downto 0);
flash_clk : out std_ulogic;
flash_ce_b : out std_ulogic;
flash_adv_b : out std_logic;
flash_a : out std_logic_vector(21 downto 0);
--pragma translate_off
-- For debug output module
sram_bw : out std_ulogic;
sim_d : inout std_logic_vector(31 downto 16);
iosn : out std_ulogic;
--pragma translate_on
-- DDR2 slot 1
dimm1_ddr2_we_b : out std_ulogic;
dimm1_ddr2_s_b : out std_logic_vector(1 downto 0);
dimm1_ddr2_ras_b : out std_ulogic;
dimm1_ddr2_pll_clkin_p : out std_ulogic;
dimm1_ddr2_pll_clkin_n : out std_ulogic;
dimm1_ddr2_odt : out std_logic_vector(1 downto 0);
dimm1_ddr2_dqs_p : inout std_logic_vector(8 downto 0);
dimm1_ddr2_dqs_n : inout std_logic_vector(8 downto 0);
dimm1_ddr2_dqm : out std_logic_vector(8 downto 0);
dimm1_ddr2_dq : inout std_logic_vector(71 downto 0);
dimm1_ddr2_cke : out std_logic_vector(1 downto 0);
-- dimm1_ddr2_cb : inout std_logic_vector(7 downto 0);
dimm1_ddr2_cas_b : out std_ulogic;
dimm1_ddr2_ba : out std_logic_vector(2 downto 0);
dimm1_ddr2_a : out std_logic_vector(13 downto 0);
-- DDR2 slot 0
dimm0_ddr2_we_b : out std_ulogic;
dimm0_ddr2_s_b : out std_logic_vector(1 downto 0);
dimm0_ddr2_ras_b : out std_ulogic;
dimm0_ddr2_pll_clkin_p : out std_ulogic;
dimm0_ddr2_pll_clkin_n : out std_ulogic;
dimm0_ddr2_odt : out std_logic_vector(1 downto 0);
dimm0_ddr2_dqs_p : inout std_logic_vector(8 downto 0);
dimm0_ddr2_dqs_n : inout std_logic_vector(8 downto 0);
dimm0_ddr2_dqm : out std_logic_vector(8 downto 0);
dimm0_ddr2_dq : inout std_logic_vector(71 downto 0);
dimm0_ddr2_cke : out std_logic_vector(1 downto 0);
-- dimm0_ddr2_cb : inout std_logic_vector(7 downto 0);
dimm0_ddr2_cas_b : out std_ulogic;
dimm0_ddr2_ba : out std_logic_vector(2 downto 0);
dimm0_ddr2_a : out std_logic_vector(13 downto 0);
dimm0_ddr2_reset_n : out std_ulogic;
-- Ethernet PHY0
phy0_txer : out std_ulogic;
phy0_txd : out std_logic_vector(3 downto 0);
phy0_txctl_txen : out std_ulogic;
phy0_txclk : in std_ulogic;
phy0_rxer : in std_ulogic;
phy0_rxd : in std_logic_vector(3 downto 0);
phy0_rxctl_rxdv : in std_ulogic;
phy0_rxclk : in std_ulogic;
phy0_reset : out std_ulogic;
phy0_mdio : inout std_logic;
phy0_mdc : out std_ulogic;
-- phy0_int : in std_ulogic;
-- Ethernet PHY1 SGMII
sgmiiclk_qo_p : in std_logic;
sgmiiclk_qo_n : in std_logic;
phy1_reset : out std_logic;
phy1_mdio : inout std_logic;
phy1_mdc : out std_logic;
phy1_int : out std_logic;
phy1_sgmii_tx_p : out std_logic;
phy1_sgmii_tx_n : out std_logic;
phy1_sgmii_rx_p : in std_logic;
phy1_sgmii_rx_n : in std_logic;
-- System ACE MPU
sysace_mpa : out std_logic_vector(6 downto 0);
sysace_mpce : out std_ulogic;
sysace_mpirq : in std_ulogic;
sysace_mpoe : out std_ulogic;
sysace_mpwe : out std_ulogic;
sysace_mpd : inout std_logic_vector(15 downto 0);
-- GPIO/Green LEDs
dbg_led : inout std_logic_vector(3 downto 0);
-- Red/Green LEDs
opb_bus_error : out std_ulogic;
plb_bus_error : out std_ulogic;
-- LCD
-- fpga_lcd_rw : out std_ulogic;
-- fpga_lcd_rs : out std_ulogic;
-- fpga_lcd_e : out std_ulogic;
-- fpga_lcd_db : out std_logic_vector(7 downto 0);
-- DVI
dvi_xclk_p : out std_ulogic;
dvi_xclk_n : out std_ulogic;
dvi_v : out std_ulogic;
dvi_reset_b : out std_ulogic;
dvi_h : out std_ulogic;
dvi_gpio1 : inout std_logic;
dvi_de : out std_ulogic;
dvi_d : out std_logic_vector(11 downto 0);
-- PCI
pci_p_trdy_b : inout std_logic;
pci_p_stop_b : inout std_logic;
pci_p_serr_b : inout std_logic;
pci_p_rst_b : inout std_logic;
pci_p_req_b : in std_logic_vector(0 to 4);
pci_p_perr_b : inout std_logic;
pci_p_par : inout std_logic;
pci_p_lock_b : inout std_logic;
pci_p_irdy_b : inout std_logic;
pci_p_intd_b : in std_logic;
pci_p_intc_b : in std_logic;
pci_p_intb_b : in std_logic;
pci_p_inta_b : in std_logic;
pci_p_gnt_b : out std_logic_vector(0 to 4);
pci_p_frame_b : inout std_logic;
pci_p_devsel_b : inout std_logic;
pci_p_clk5_r : out std_ulogic;
pci_p_clk5 : in std_ulogic;
pci_p_clk4_r : out std_ulogic;
pci_p_clk3_r : out std_ulogic;
pci_p_clk1_r : out std_ulogic;
pci_p_clk0_r : out std_ulogic;
pci_p_cbe_b : inout std_logic_vector(3 downto 0);
pci_p_ad : inout std_logic_vector(31 downto 0);
-- pci_fpga_idsel : in std_ulogic;
sbr_pwg_rsm_rstj : inout std_logic;
sbr_nmi_r : in std_ulogic;
sbr_intr_r : in std_ulogic;
sbr_ide_rst_b : inout std_logic;
-- IIC/SMBus and sideband signals
iic_sda_dvi : inout std_logic;
iic_scl_dvi : inout std_logic;
fpga_sda : inout std_logic;
fpga_scl : inout std_logic;
iic_therm_b : in std_ulogic;
iic_reset_b : out std_ulogic;
iic_irq_b : in std_ulogic;
iic_alert_b : in std_ulogic;
-- SPI
spi_data_out : in std_logic;
spi_data_in : out std_ulogic;
spi_data_cs_b : out std_ulogic;
spi_clk : out std_ulogic;
-- UARTs
uart1_txd : out std_ulogic;
uart1_rxd : in std_ulogic;
uart1_rts_b : out std_ulogic;
uart1_cts_b : in std_ulogic;
uart0_txd : out std_ulogic;
uart0_rxd : in std_ulogic;
uart0_rts_b : out std_ulogic
-- uart0_cts_b : in std_ulogic
-- System monitor
-- test_mon_vrefp : in std_ulogic;
-- test_mon_vp0_p : in std_ulogic;
-- test_mon_vn0_n : in std_ulogic
-- test_mon_avdd : in std_ulogic
);
end;
architecture rtl of leon3mp is
component svga2ch7301c
generic (
tech : integer := 0;
idf : integer := 0;
dynamic : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
clksel : in std_logic_vector(1 downto 0);
vgao : in apbvga_out_type;
vgaclk_fb : in std_ulogic;
clk25_fb : in std_ulogic;
clk40_fb : in std_ulogic;
clk65_fb : in std_ulogic;
vgaclk : out std_ulogic;
clk25 : out std_ulogic;
clk40 : out std_ulogic;
clk65 : out std_ulogic;
dclk_p : out std_ulogic;
dclk_n : out std_ulogic;
locked : out std_ulogic;
data : out std_logic_vector(11 downto 0);
hsync : out std_ulogic;
vsync : out std_ulogic;
de : out std_ulogic
);
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
component IBUFDS
generic ( CAPACITANCE : string := "DONT_CARE";
DIFF_TERM : boolean := FALSE; IBUF_DELAY_VALUE : string := "0";
IFD_DELAY_VALUE : string := "AUTO"; IOSTANDARD : string := "DEFAULT");
port ( O : out std_ulogic; I : in std_ulogic; IB : in std_ulogic);
end component;
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := NCPU+CFG_AHB_UART+CFG_AHB_JTAG+
CFG_SVGA_ENABLE+CFG_GRETH+CFG_GRETH2+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA;
signal ddr0_clk_fb, ddr1_clk_fb : std_logic;
signal vcc, gnd : std_logic_vector(31 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal apbi, apb1i : apb_slv_in_type;
signal apbo, apb1o : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal ddr2spa_ahbsi : ahb_slv_in_type;
signal ddr2spa_ahbso : ahb_slv_out_vector_type(1 downto 0);
signal clkm, clkm2x, rstn, rstraw, flashclkl : std_ulogic;
signal clkddr, clk_200 : std_ulogic;
signal clk25, clk40, clk65 : std_ulogic;
signal cgi, cgi2, cgi3 : clkgen_in_type;
signal cgo, cgo2, cgo3 : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal sysi : leon_dsu_stat_base_in_type;
signal syso : leon_dsu_stat_base_out_type;
signal perf : l3stat_in_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal clklock, lock0, lock1, lclk, clkml0, clkml1 : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal rst : std_ulogic;
signal egtx_clk_fb : std_ulogic;
signal egtx_clk, legtx_clk, l2egtx_clk : std_ulogic;
signal sgmii_refclk, sgmii_rst: std_logic;
signal mdio_reset, mdio_o, mdio_oe, mdio_i, mdc, mdint : std_logic;
signal vgao : apbvga_out_type;
signal lcd_datal : std_logic_vector(11 downto 0);
signal lcd_hsyncl, lcd_vsyncl, lcd_del, lcd_reset_bl : std_ulogic;
signal clk_sel : std_logic_vector(1 downto 0);
signal vgalock : std_ulogic;
signal clkvga, clkvga_p, clkvga_n : std_ulogic;
signal i2ci, dvi_i2ci : i2c_in_type;
signal i2co, dvi_i2co : i2c_out_type;
signal spii : spi_in_type;
signal spio : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
constant BOARD_FREQ_200 : integer := 200000; -- input frequency in KHz
constant BOARD_FREQ : integer := 100000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant I2C_FILTER : integer := (CPU_FREQ*5+50000)/100000+1;
-- DDR clock is 200 MHz clock unless CFG_DDR2SP_NOSYNC is set. If that config
-- option is set the DDR clock is 2x CPU clock.
constant DDR_FREQ : integer :=
BOARD_FREQ_200 - (BOARD_FREQ_200 - 2*CPU_FREQ)*CFG_DDR2SP_NOSYNC;
constant IOAEN : integer := CFG_DDR2SP+CFG_GRACECTRL;
signal stati : ahbstat_in_type;
signal ddr0_clkv : std_logic_vector(2 downto 0);
signal ddr0_clkbv : std_logic_vector(2 downto 0);
signal ddr1_clkv : std_logic_vector(2 downto 0);
signal ddr1_clkbv : std_logic_vector(2 downto 0);
signal clkace : std_ulogic;
signal acei : gracectrl_in_type;
signal aceo : gracectrl_out_type;
signal sysmoni : grsysmon_in_type;
signal sysmono : grsysmon_out_type;
signal pciclk, pci_clk, pci_clk_fb : std_ulogic;
signal pci_arb_gnt : std_logic_vector(0 to 7);
signal pci_arb_req : std_logic_vector(0 to 7);
signal pci_arb_reql : std_logic_vector(0 to 4);
signal pci_reql : std_ulogic;
signal pci_host, pci_66 : std_ulogic;
signal pci_intv : std_logic_vector(3 downto 0);
signal pcii : pci_in_type;
signal pcio : pci_out_type;
signal pci_dirq : std_logic_vector(3 downto 0);
signal clkma, clkmb, clkmc : std_ulogic;
signal clk0_tb, rst0_tb, rst0_tbn : std_ulogic;
signal phy_init_done : std_ulogic;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of clkml0 : signal is true;
attribute syn_preserve of clkml0 : signal is true;
attribute syn_keep of clkml1 : signal is true;
attribute syn_preserve of clkml1 : signal is true;
attribute syn_keep of clkm : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute syn_keep of egtx_clk : signal is true;
attribute syn_preserve of egtx_clk : signal is true;
attribute syn_keep of clkvga : signal is true;
attribute syn_preserve of clkvga : signal is true;
attribute syn_keep of clk25 : signal is true;
attribute syn_preserve of clk25 : signal is true;
attribute syn_keep of clk40 : signal is true;
attribute syn_preserve of clk40 : signal is true;
attribute syn_keep of clk65 : signal is true;
attribute syn_preserve of clk65 : signal is true;
attribute syn_keep of phy_init_done : signal is true;
attribute syn_preserve of phy_init_done : signal is true;
attribute syn_keep of pciclk : signal is true;
attribute syn_preserve of pciclk : signal is true;
attribute syn_keep of sgmii_refclk : signal is true;
attribute syn_preserve of sgmii_refclk : signal is true;
attribute keep : boolean;
attribute keep of lock0 : signal is true;
attribute keep of lock1 : signal is true;
attribute keep of clkml0 : signal is true;
attribute keep of clkml1 : signal is true;
attribute keep of clkm : signal is true;
attribute keep of egtx_clk : signal is true;
attribute keep of clkvga : signal is true;
attribute keep of clk25 : signal is true;
attribute keep of clk40 : signal is true;
attribute keep of clk65 : signal is true;
attribute keep of pciclk : signal is true;
attribute keep of sgmii_refclk : signal is true;
attribute syn_noprune : boolean;
attribute syn_noprune of sysace_fpga_clk_pad : label is true;
begin
vcc <= (others => '1'); gnd <= (others => '0');
rst0_tbn <= not rst0_tb;
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
flashclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (flash_clk, flashclkl);
sysace_fpga_clk_pad : clkpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (sysace_fpga_clk, clkace);
pci_p_clk5_pad : clkpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (pci_p_clk5, pci_clk_fb);
pci_p_clk5_r_pad : outpad generic map (tech => padtech, level => pci33)
port map (pci_p_clk5_r, pci_clk);
pci_p_clk4_r_pad : outpad generic map (tech => padtech, level => pci33)
port map (pci_p_clk4_r, pci_clk);
pci_p_clk3_r_pad : outpad generic map (tech => padtech, level => pci33)
port map (pci_p_clk3_r, pci_clk);
pci_p_clk1_r_pad : outpad generic map (tech => padtech, level => pci33)
port map (pci_p_clk1_r, pci_clk);
pci_p_clk0_r_pad : outpad generic map (tech => padtech, level => pci33)
port map (pci_p_clk0_r, pci_clk);
clkgen0 : clkgen -- system clock generator
generic map (CFG_FABTECH, CFG_CLKMUL, CFG_CLKDIV, 1, 1,
1, CFG_PCIDLL, CFG_PCISYSCLK, BOARD_FREQ, 1)
port map (lclk, pci_clk_fb, clkmc, open, clkm2x, flashclkl, pciclk, cgi, cgo,
open, open, clk_200);
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; cgi.pllref <= '0';
-- clkgen1 : clkgen -- Ethernet 1G PHY clock generator
-- generic map (CFG_FABTECH, 5, 4, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
-- port map (lclk, gnd(0), egtx_clk, open, open, open, open, cgi2, cgo2);
-- cgi2.pllctrl <= "00"; cgi2.pllrst <= rstraw; --cgi2.pllref <= egtx_clk_fb;
-- egtx_clk_pad : outpad generic map (tech => padtech)
-- port map (phy_gtx_clk, egtx_clk);
clkgen2 : clkgen -- PCI clock generator
generic map (CFG_FABTECH, 2, 6, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd(0), pci_clk, open, open, open, open, cgi3, cgo3);
cgi3.pllctrl <= "00"; cgi3.pllrst <= rstraw; cgi3.pllref <= '0';
iic_reset_b_pad : outpad generic map (tech => padtech)
port map (iic_reset_b, rstn);
resetn_pad : inpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (fpga_cpu_reset_b, rst);
rst0 : rstgen -- reset generator
port map (rst, clkm, clklock, rstn, rstraw);
clklock <= lock0 and lock1 and cgo.clklock and cgo3.clklock;
clk_pad : clkpad generic map (tech => padtech, arch => 2, level => cmos, voltage => x25v)
port map (user_clksys, lclk);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, devid => XILINX_ML510,
ioen => IOAEN, nahbm => maxahbm, nahbs => 11)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON processor and DSU -----------------------------------------
----------------------------------------------------------------------
leon : leon_dsu_stat_base
generic map (
leon => CFG_LEON, ncpu => ncpu, fabtech => fabtech, memtech => memtech,
nwindows => CFG_NWIN, dsu => CFG_DSU, fpu => CFG_FPU, v8 => CFG_V8, cp => 0,
mac => CFG_MAC, pclow => pclow, notag => 0, nwp => CFG_NWP, icen => CFG_ICEN,
irepl => CFG_IREPL, isets => CFG_ISETS, ilinesize => CFG_ILINE,
isetsize => CFG_ISETSZ, isetlock => CFG_ILOCK, dcen => CFG_DCEN,
drepl => CFG_DREPL, dsets => CFG_DSETS, dlinesize => CFG_DLINE,
dsetsize => CFG_DSETSZ, dsetlock => CFG_DLOCK, dsnoop => CFG_DSNOOP,
ilram => CFG_ILRAMEN, ilramsize => CFG_ILRAMSZ, ilramstart => CFG_ILRAMADDR,
dlram => CFG_DLRAMEN, dlramsize => CFG_DLRAMSZ, dlramstart => CFG_DLRAMADDR,
mmuen => CFG_MMUEN, itlbnum => CFG_ITLBNUM, dtlbnum => CFG_DTLBNUM,
tlb_type => CFG_TLB_TYPE, tlb_rep => CFG_TLB_REP, lddel => CFG_LDDEL,
disas => disas, tbuf => CFG_ITBSZ, pwd => CFG_PWD, svt => CFG_SVT,
rstaddr => CFG_RSTADDR, smp => ncpu-1, cached => CFG_DFIXED,
wbmask => CFG_BWMASK, busw => CFG_CACHEBW, netlist => CFG_LEON_NETLIST,
ft => CFG_LEONFT_EN, npasi => CFG_NP_ASI, pwrpsr => CFG_WRPSR,
rex => CFG_REX, altwin => CFG_ALTWIN, grfpush => CFG_GRFPUSH,
dsu_hindex => 2, dsu_haddr => 16#D00#, dsu_hmask => 16#F00#, atbsz => CFG_ATBSZ,
stat => CFG_STAT_ENABLE, stat_pindex => 12, stat_paddr => 16#100#,
stat_pmask => 16#ffc#, stat_ncnt => CFG_STAT_CNT, stat_nmax => CFG_STAT_NMAX)
port map (
rstn => rstn, ahbclk => clkm, cpuclk => clkm, hclken => vcc(0),
leon_ahbmi => ahbmi, leon_ahbmo => ahbmo(CFG_NCPU-1 downto 0),
leon_ahbsi => ahbsi, leon_ahbso => ahbso,
irqi => irqi, irqo => irqo,
stat_apbi => apbi, stat_apbo => apbo(12), stat_ahbsi => ahbsi,
stati => perf,
dsu_ahbsi => ahbsi, dsu_ahbso => ahbso(2),
dsu_tahbmi => ahbmi, dsu_tahbsi => ahbsi,
sysi => sysi, syso => syso);
sysi.dsu_enable <= '1';
sysi.dsu_break <= not gpioo.val(0); -- Position on GPIO DIP switch
opb_bus_error_pad : outpad generic map (tech => padtech)
port map (opb_bus_error, syso.proc_errorn);
plb_bus_error_pad : outpad generic map (tech => padtech)
port map (plb_bus_error, syso.dsu_active);
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(NCPU));
end generate;
nodcom : if CFG_AHB_UART = 0 generate
duo.txd <= '0'; duo.rtsn <= '1';
end generate;
dsurx_pad : inpad generic map (tech => padtech, level => cmos, voltage => x33v)
port map (uart0_rxd, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech, level => cmos, voltage => x33v)
port map (uart0_txd, duo.txd);
-- dsucts_pad : inpad generic map (tech => padtech, level => cmos, voltage => x33v)
-- port map (uart0_cts_b, dui.ctsn);
dsurts_pad : outpad generic map (tech => padtech, level => cmos, voltage => x33v)
port map (uart0_rts_b, duo.rtsn);
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
memi.brdyn <= '1'; memi.bexcn <= '1';
mctrl0 : if CFG_MCTRL_LEON2 = 1 generate
mctrl0 : mctrl generic map (hindex => 3, pindex => 0,
ramaddr => 0, rammask => 0, paddr => 0, srbanks => 0,
ram8 => CFG_MCTRL_RAM8BIT, ram16 => CFG_MCTRL_RAM16BIT,
sden => CFG_MCTRL_SDEN, invclk => CFG_MCTRL_INVCLK,
sepbus => CFG_MCTRL_SEPBUS)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(3), apbi, apbo(0), wpo);
end generate;
ftmctrl0 : if CFG_MCTRLFT = 1 generate -- FT memory controller
sr1 : ftmctrl generic map (hindex => 3, pindex => 0,
ramaddr => 0, rammask => 0, paddr => 0, srbanks => 0, sden => CFG_MCTRLFT_SDEN,
ram8 => CFG_MCTRLFT_RAM8BIT, ram16 => CFG_MCTRLFT_RAM16BIT,
invclk => CFG_MCTRLFT_INVCLK,
sepbus => CFG_MCTRLFT_SEPBUS,
edac => CFG_MCTRLFT_EDAC)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(3), apbi, apbo(0), wpo);
end generate;
nomctrl: if (CFG_MCTRL_LEON2 + CFG_MCTRLFT) = 0 generate
memo.address <= (others => '0'); memo.romsn <= (others => '1');
memo.oen <= '1'; memo.wrn <= (others => '1');
memo.vbdrive <= (others => '1'); memo.writen <= '1';
end generate;
flash_reset_b_pad : outpad generic map (tech => padtech)
port map (flash_reset_b, rstn);
-- flash_wait_pad : inpad generic map (tech => padtech)
-- port map (flash_wait, );
flash_adv_b_pad : outpad generic map (tech => padtech)
port map (flash_adv_b, gnd(0));
flash_a_pads : outpadv generic map (width => 22, tech => padtech)
port map (flash_a, memo.address(22 downto 1));
flash_ce_b_pad : outpad generic map (tech => padtech)
port map (flash_ce_b, memo.romsn(0));
flash_oe_b_pad : outpad generic map (tech => padtech)
port map (flash_oe_b, memo.oen);
--pragma translate_off
rwen_pad : outpad generic map (tech => padtech)
port map (sram_bw, memo.wrn(3));
sim_d_pads : iopadvv generic map (tech => padtech, width => 16)
port map (sim_d, memo.data(15 downto 0),
memo.vbdrive(15 downto 0), memi.data(15 downto 0));
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
--pragma translate_on
flash_we_b_pad : outpad generic map (tech => padtech)
port map (flash_we_b, memo.writen);
flash_d_pads : iopadvv generic map (tech => padtech, width => 16)
port map (flash_d, memo.data(31 downto 16),
memo.vbdrive(31 downto 16), memi.data(31 downto 16));
dbg_led0_pad : outpad generic map (tech => padtech, level => cmos, voltage => x33v)
port map (dbg_led(3), phy_init_done);
clkm <= clkma; clkma <= clkmb; clkmb <= clkmc;
-----------------------------------------------------------------------------
-- L2 cache, optionally covering DDR2 SDRAM memory controller
-----------------------------------------------------------------------------
l2cen : if CFG_L2_EN /= 0 generate
l2cblock : block
signal mem_ahbsi : ahb_slv_in_type;
signal mem_ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal mem_ahbmi : ahb_mst_in_type;
signal mem_ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal l2c_stato : std_logic_vector(10 downto 0);
begin
l2c0 : l2c generic map (
hslvidx => 0, hmstidx => 0, cen => CFG_L2_PEN,
haddr => 16#400#, hmask => 16#c00#, ioaddr => 16#FF0#,
cached => CFG_L2_MAP, repl => CFG_L2_RAN, ways => CFG_L2_WAYS,
linesize => CFG_L2_LSZ, waysize => CFG_L2_SIZE,
memtech => memtech, bbuswidth => AHBDW,
bioaddr => 16#FFE#, biomask => 16#fff#,
sbus => 0, mbus => 1, arch => CFG_L2_SHARE,
ft => CFG_L2_EDAC)
port map(rst => rstn, clk => clkm, ahbsi => ahbsi, ahbso => ahbso(0),
ahbmi => mem_ahbmi, ahbmo => mem_ahbmo(0), ahbsov => mem_ahbso,
sto => l2c_stato);
memahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => 16#FFE#,
ioen => 1, nahbm => 1, nahbs => 2)
port map (rstn, clkm, mem_ahbmi, mem_ahbmo, mem_ahbsi, mem_ahbso);
mem_ahbso(1 downto 0) <= ddr2spa_ahbso;
ddr2spa_ahbsi <= mem_ahbsi;
perf.event(15 downto 7) <= (others => '0');
perf.esource(15 downto 7) <= (others => (others => '0'));
perf.event(6) <= l2c_stato(10); -- Data uncorrectable error
perf.event(5) <= l2c_stato(9); -- Data correctable error
perf.event(4) <= l2c_stato(8); -- Tag uncorrectable error
perf.event(3) <= l2c_stato(7); -- Tag correctable error
perf.event(2) <= l2c_stato(2); -- Bus access
perf.event(1) <= l2c_stato(1); -- Miss
perf.event(0) <= l2c_stato(0); -- Hit
perf.esource(6 downto 3) <= (others => (others => '0'));
perf.esource(2 downto 0) <= (others => l2c_stato(6 downto 3));
perf.req <= (others => '0');
perf.sel <= (others => '0');
perf.latcnt <= '0';
--perf.timer <= dbgi(0).timer(31 downto 0);
end block l2cblock;
end generate l2cen;
nol2c : if CFG_L2_EN = 0 generate
ahbso(1 downto 0) <= ddr2spa_ahbso;
ddr2spa_ahbsi <= ahbsi;
perf <= l3stat_in_none;
end generate;
-----------------------------------------------------------------------------
-- DDR2 SDRAM memory controller
-----------------------------------------------------------------------------
ddrsp0 : if (CFG_DDR2SP /= 0) generate
phy_init_done <= '1';
-- DDR clock selection
-- If the synchronization registers are removed in the DDR controller, we
-- assume that the user wants to run at 2x the system clock. Otherwise the
-- DDR clock is generated from the 200 MHz clock.
ddrclkselarb: if CFG_DDR2SP_NOSYNC = 0 generate
BUFGDDR : BUFG port map (I => clk_200, O => clkddr);
end generate;
ddrclksel2x: if CFG_DDR2SP_NOSYNC /= 0 generate
clkddr <= clkm2x;
end generate;
dimm0_ddr2_reset_n_pad : outpad generic map (tech => padtech, level => cmos, voltage => x33v)
port map (dimm0_ddr2_reset_n, rst);
-- Slot 0
ddrc0 : ddr2spa generic map ( fabtech => fabtech, memtech => memtech,
hindex => 0, haddr => 16#400#, hmask => 16#e00#, ioaddr => 1,
pwron => CFG_DDR2SP_INIT, MHz => DDR_FREQ/1000, TRFC => CFG_DDR2SP_TRFC,
clkmul => CFG_DDR2SP_FREQ/10 - (CFG_DDR2SP_FREQ/10-1)*CFG_DDR2SP_NOSYNC,
clkdiv => 20 - (19)*CFG_DDR2SP_NOSYNC, ahbfreq => CPU_FREQ/1000,
col => CFG_DDR2SP_COL, Mbyte => CFG_DDR2SP_SIZE, ddrbits => CFG_DDR2SP_DATAWIDTH,
ddelayb0 => CFG_DDR2SP_DELAY0, ddelayb1 => CFG_DDR2SP_DELAY1,
ddelayb2 => CFG_DDR2SP_DELAY2, ddelayb3 => CFG_DDR2SP_DELAY3,
ddelayb4 => CFG_DDR2SP_DELAY4, ddelayb5 => CFG_DDR2SP_DELAY5,
ddelayb6 => CFG_DDR2SP_DELAY6, ddelayb7 => CFG_DDR2SP_DELAY7,
cbdelayb0 => CFG_DDR2SP_DELAY0, cbdelayb1 => CFG_DDR2SP_DELAY0,
cbdelayb2 => CFG_DDR2SP_DELAY0, cbdelayb3 => CFG_DDR2SP_DELAY0,
readdly => 1, rskew => 0, oepol => 0,
dqsgating => 0, rstdel => 200, eightbanks => 1,
numidelctrl => 2 + CFG_DDR2SP_DATAWIDTH/64, norefclk => 0, odten => 3,
nosync => CFG_DDR2SP_NOSYNC, ft => CFG_DDR2SP_FTEN, ftbits => CFG_DDR2SP_FTWIDTH)
port map (rst, rstn, clkddr, clkm, clk_200, lock0, clkml0, clkml0,
ddr2spa_ahbsi, ddr2spa_ahbso(0),
ddr0_clkv, ddr0_clkbv, ddr0_clk_fb, ddr0_clk_fb,
dimm0_ddr2_cke, dimm0_ddr2_s_b, dimm0_ddr2_we_b, dimm0_ddr2_ras_b,
dimm0_ddr2_cas_b, dimm0_ddr2_dqm(CFG_DDR2SP_FTWIDTH/8+CFG_DDR2SP_DATAWIDTH/8-1 downto 0),
dimm0_ddr2_dqs_p(CFG_DDR2SP_FTWIDTH/8+CFG_DDR2SP_DATAWIDTH/8-1 downto 0),
dimm0_ddr2_dqs_n(CFG_DDR2SP_FTWIDTH/8+CFG_DDR2SP_DATAWIDTH/8-1 downto 0), dimm0_ddr2_a,
dimm0_ddr2_ba(2 downto 0), dimm0_ddr2_dq(CFG_DDR2SP_FTWIDTH+CFG_DDR2SP_DATAWIDTH-1 downto 0),
dimm0_ddr2_odt);
dimm0_ddr2_pll_clkin_p <= ddr0_clkv(0);
dimm0_ddr2_pll_clkin_n <= ddr0_clkbv(0);
-- Ground unused bank address and memory mask
-- dimm0_ddr2_ba_notused_pad : outpad generic map (tech => padtech, level => SSTL18_I)
-- port map (dimm0_ddr2_ba(2), gnd(0));
dimm0_ddr2_dqm_notused8_pad : outpad generic map (tech => padtech, level => SSTL18_I)
port map (dimm0_ddr2_dqm(8), gnd(0));
-- Tri-state unused data strobe
dimm0_dqsp_notused8_pad : iopad generic map (tech => padtech, level => SSTL18_II)
port map (dimm0_ddr2_dqs_p(8), gnd(0), vcc(0), open);
dimm0_dqsn_notused8_pad : iopad generic map (tech => padtech, level => SSTL18_II)
port map (dimm0_ddr2_dqs_n(8), gnd(0), vcc(0), open);
-- Tristate unused check bits
dimm0_cb_notused_pad : iopadv generic map (tech => padtech, width => 8, level => SSTL18_II)
port map (dimm0_ddr2_dq(71 downto 64), gnd(7 downto 0), vcc(0), open);
-- Handle signals not used with 32-bit interface
ddr032bit: if CFG_DDR2SP_DATAWIDTH /= 64 generate
dimm0_ddr2_dqm_notused30_pads : outpadv generic map (tech => padtech, width => 4, level => SSTL18_I)
port map (dimm0_ddr2_dqm(3 downto 0), gnd(3 downto 0));
dimm0_dqsp_notused30_pads : iopadv generic map (tech => padtech, width => 4, level => SSTL18_II)
port map (dimm0_ddr2_dqs_p(3 downto 0), gnd(3 downto 0), vcc(0), open);
dimm0_dqsn_notused30_pads : iopadv generic map (tech => padtech, width => 4, level => SSTL18_II)
port map (dimm0_ddr2_dqs_n(3 downto 0), gnd(3 downto 0), vcc(0), open);
dimm0_dq_notused_pads : iopadv generic map (tech => padtech, width => 32, level => SSTL18_II)
port map (dimm0_ddr2_dq(31 downto 0), gnd, vcc(0), open);
end generate;
-- Slot 1
ddrc1 : ddr2spa generic map ( fabtech => fabtech, memtech => memtech,
hindex => 1, haddr => 16#600#, hmask => 16#E00#, ioaddr => 2,
pwron => CFG_DDR2SP_INIT, MHz => DDR_FREQ/1000, TRFC => CFG_DDR2SP_TRFC,
clkmul => CFG_DDR2SP_FREQ/10 - (CFG_DDR2SP_FREQ/10-1)*CFG_DDR2SP_NOSYNC,
clkdiv => 20 - (19)*CFG_DDR2SP_NOSYNC, ahbfreq => CPU_FREQ/1000,
col => CFG_DDR2SP_COL, Mbyte => CFG_DDR2SP_SIZE, ddrbits => CFG_DDR2SP_DATAWIDTH,
ddelayb0 => CFG_DDR2SP_DELAY0, ddelayb1 => CFG_DDR2SP_DELAY1,
ddelayb2 => CFG_DDR2SP_DELAY2, ddelayb3 => CFG_DDR2SP_DELAY3,
ddelayb4 => CFG_DDR2SP_DELAY4, ddelayb5 => CFG_DDR2SP_DELAY5,
ddelayb6 => CFG_DDR2SP_DELAY6, ddelayb7 => CFG_DDR2SP_DELAY7,
readdly => 1, rskew => 0, oepol => 0,
dqsgating => 0, rstdel => 200, eightbanks => 1,
numidelctrl => 2 + CFG_DDR2SP_DATAWIDTH/64, norefclk => 0, odten => 3,
nosync => CFG_DDR2SP_NOSYNC)
port map (rst, rstn, clkddr, clkm, clk_200, lock1, clkml1, clkml1,
ddr2spa_ahbsi, ddr2spa_ahbso(1),
ddr1_clkv, ddr1_clkbv, ddr1_clk_fb, ddr1_clk_fb,
dimm1_ddr2_cke, dimm1_ddr2_s_b, dimm1_ddr2_we_b, dimm1_ddr2_ras_b,
dimm1_ddr2_cas_b, dimm1_ddr2_dqm(7 downto 4*(32/CFG_DDR2SP_DATAWIDTH)),
dimm1_ddr2_dqs_p(7 downto 4*(32/CFG_DDR2SP_DATAWIDTH)),
dimm1_ddr2_dqs_n(7 downto 4*(32/CFG_DDR2SP_DATAWIDTH)), dimm1_ddr2_a,
dimm1_ddr2_ba(2 downto 0), dimm1_ddr2_dq(63 downto 32*(32/ CFG_DDR2SP_DATAWIDTH)),
dimm1_ddr2_odt);
dimm1_ddr2_pll_clkin_p <= ddr1_clkv(0);
dimm1_ddr2_pll_clkin_n <= ddr1_clkbv(0);
-- Ground unused bank address and memory mask
-- dimm1_ddr2_ba_notused_pad : outpad generic map (tech => padtech, level => SSTL18_I)
-- port map (dimm1_ddr2_ba(2), gnd(0));
dimm1_ddr2_dqm_notused8_pad : outpad generic map (tech => padtech, level => SSTL18_I)
port map (dimm1_ddr2_dqm(8), gnd(0));
-- Tri-state unused data strobe
dimm1_dqsp_notused8_pad : iopad generic map (tech => padtech, level => SSTL18_II)
port map (dimm1_ddr2_dqs_p(8), gnd(0), vcc(0), open);
dimm1_dqsn_notused8_pad : iopad generic map (tech => padtech, level => SSTL18_II)
port map (dimm1_ddr2_dqs_n(8), gnd(0), vcc(0), open);
-- Tristate unused check bits
dimm1_cb_notused_pad : iopadv generic map (tech => padtech, width => 8, level => SSTL18_II)
port map (dimm1_ddr2_dq(71 downto 64), gnd(7 downto 0), vcc(0), open);
-- Handle signals not used with 32-bit interface
ddr132bit: if CFG_DDR2SP_DATAWIDTH /= 64 generate
dimm1_ddr2_dqm_notused30_pads : outpadv generic map (tech => padtech, width => 4, level => SSTL18_I)
port map (dimm1_ddr2_dqm(3 downto 0), gnd(3 downto 0));
dimm1_dqsp_notused30_pads : iopadv generic map (tech => padtech, width => 4, level => SSTL18_II)
port map (dimm1_ddr2_dqs_p(3 downto 0), gnd(3 downto 0), vcc(0), open);
dimm1_dqsn_notused30_pads : iopadv generic map (tech => padtech, width => 4, level => SSTL18_II)
port map (dimm1_ddr2_dqs_n(3 downto 0), gnd(3 downto 0), vcc(0), open);
dimm1_dq_notused_pads : iopadv generic map (tech => padtech, width => 32, level => SSTL18_II)
port map (dimm1_ddr2_dq(31 downto 0), gnd, vcc(0), open);
end generate;
end generate;
-- noddr : if (CFG_DDR2SP = 0) generate lock0 <= '1'; lock1 <= '1'; end generate;
----------------------------------------------------------------------
--- System ACE I/F Controller ---------------------------------------
----------------------------------------------------------------------
grace: if CFG_GRACECTRL = 1 generate
grace0 : gracectrl generic map (hindex => 5, hirq => 5,
haddr => 16#000#, hmask => 16#fff#, split => CFG_SPLIT)
port map (rstn, clkm, clkace, ahbsi, ahbso(5), acei, aceo);
end generate;
nograce: if CFG_GRACECTRL = 0 generate
aceo <= gracectrl_none;
end generate nograce;
sysace_mpa_pads : outpadv generic map (width => 7, tech => padtech)
port map (sysace_mpa, aceo.addr);
sysace_mpce_pad : outpad generic map (tech => padtech)
port map (sysace_mpce, aceo.cen);
sysace_mpd_pads : iopadv generic map (tech => padtech, width => 16)
port map (sysace_mpd, aceo.do, aceo.doen, acei.di);
sysace_mpoe_pad : outpad generic map (tech => padtech)
port map (sysace_mpoe, aceo.oen);
sysace_mpwe_pad : outpad generic map (tech => padtech)
port map (sysace_mpwe, aceo.wen);
sysace_mpirq_pad : inpad generic map (tech => padtech)
port map (sysace_mpirq, acei.irq);
----------------------------------------------------------------------
--- AHB ROM ---------------------------------------------------------
----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 10, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map (rstn, clkm, ahbsi, ahbso(10));
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 4, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(4), apbi, apbo);
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0';
end generate;
noua1: if CFG_UART1_ENABLE = 0 generate u1o.txd <= '0'; u1o.rtsn <= '1'; end generate;
ua1rx_pad : inpad generic map (tech => padtech) port map (uart1_rxd, u1i.rxd);
ua1tx_pad : outpad generic map (tech => padtech) port map (uart1_txd, u1o.txd);
ua1cts_pad : inpad generic map (tech => padtech) port map (uart1_cts_b, u1i.ctsn);
ua1rts_pad : outpad generic map (tech => padtech) port map (uart1_rts_b, u1o.rtsn);
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
pci_dirq(3 downto 1) <= (others => '0');
pci_dirq(0) <= orv(irqi(0).irl);
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti <= gpti_dhalt_drive(syso.dsu_tstop);
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(memtech => memtech, pindex => 14, paddr => 14,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
clk0 => 40000, clk1 => 40000, clk2 => 25000, clk3 => 15385, burstlen => 6)
port map(rstn, clkm, clkvga, apbi, apbo(14), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), clk_sel);
dvi0 : svga2ch7301c generic map (tech => fabtech, idf => 2)
port map (lclk, rstraw, clk_sel, vgao, clkvga, clk25, clk40, clk65,
clkvga, clk25, clk40, clk65, clkvga_p, clkvga_n,
vgalock, lcd_datal, lcd_hsyncl, lcd_vsyncl, lcd_del);
i2cdvi : i2cmst
generic map (pindex => 6, paddr => 6, pmask => 16#FFF#,
pirq => 6, filter => I2C_FILTER)
port map (rstn, clkm, apbi, apbo(6), dvi_i2ci, dvi_i2co);
end generate;
novga : if CFG_SVGA_ENABLE = 0 generate
apbo(14) <= apb_none; apbo(6) <= apb_none;
lcd_datal <= (others => '0'); clkvga_p <= '0'; clkvga_n <= '0';
lcd_hsyncl <= '0'; lcd_vsyncl <= '0'; lcd_del <= '0';
dvi_i2co.scloen <= '1'; dvi_i2co.sdaoen <= '1';
end generate;
dvi_d_pad : outpadv generic map (width => 12, tech => padtech)
port map (dvi_d, lcd_datal);
dvi_xclk_p_pad : outpad generic map (tech => padtech)
port map (dvi_xclk_p, clkvga_p);
dvi_xclk_n_pad : outpad generic map (tech => padtech)
port map (dvi_xclk_n, clkvga_n);
dvi_h_pad : outpad generic map (tech => padtech)
port map (dvi_h, lcd_hsyncl);
dvi_v_pad : outpad generic map (tech => padtech)
port map (dvi_v, lcd_vsyncl);
dvi_de_pad : outpad generic map (tech => padtech)
port map (dvi_de, lcd_del);
dvi_reset_b_pad : outpad generic map (tech => padtech)
port map (dvi_reset_b, rstn);
iic_scl_dvi_pad : iopad generic map (tech => padtech)
port map (iic_scl_dvi, dvi_i2co.scl, dvi_i2co.scloen, dvi_i2ci.scl);
iic_sda_dvi_pad : iopad generic map (tech => padtech)
port map (iic_sda_dvi, dvi_i2co.sda, dvi_i2co.sdaoen, dvi_i2ci.sda);
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 8, paddr => 8, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(8),
gpioi => gpioi, gpioo => gpioo);
end generate;
nogpio0: if CFG_GRGPIO_ENABLE = 0 generate
gpioo.oen <= (others => '1'); gpioo.val <= (others => '0');
gpioo.dout <= (others => '1');
end generate;
dbg_led_0 : inpad generic map (tech => padtech)
port map (dbg_led(0), gpioi.din(0));
dbg_led_pads : iopadvv generic map (tech => padtech, width => 2, level => cmos, voltage => x33v)
port map (dbg_led(2 downto 1), gpioo.dout(2 downto 1), gpioo.oen(2 downto 1),
gpioi.din(2 downto 1));
dvi_gpio_pad : iopad generic map (tech => padtech)
port map (dvi_gpio1, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
iic_therm_b_pad : inpad generic map (tech => padtech)
port map (iic_therm_b, gpioi.din(9));
iic_irq_b_pad : inpad generic map (tech => padtech)
port map (iic_irq_b, gpioi.din(10));
iic_alert_b_pad : inpad generic map (tech => padtech)
port map (iic_alert_b, gpioi.din(11));
sbr_pwg_rsm_rstj_pad : iopad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (sbr_pwg_rsm_rstj, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
sbr_nmi_r_pad : inpad generic map (tech => padtech)
port map (sbr_nmi_r, gpioi.din(6));
sbr_intr_r_pad : inpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (sbr_intr_r, gpioi.din(5));
sbr_ide_rst_b_pad : iopad generic map (tech => padtech)
port map (sbr_ide_rst_b, gpioo.dout(8), gpioo.oen(8), gpioi.din(8));
i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master
i2c0 : i2cmst
generic map (pindex => 9, paddr => 9, pmask => 16#FFF#,
pirq => 3, filter => I2C_FILTER)
port map (rstn, clkm, apbi, apbo(9), i2ci, i2co);
end generate;
noi2cm: if CFG_I2C_ENABLE = 0 generate
i2co.scloen <= '1'; i2co.sdaoen <= '1';
i2co.scl <= '0'; i2co.sda <= '0';
end generate;
i2c_scl_pad : iopad generic map (tech => padtech)
port map (fpga_scl, i2co.scl, i2co.scloen, i2ci.scl);
i2c_sda_pad : iopad generic map (tech => padtech)
port map (fpga_sda, i2co.sda, i2co.sdaoen, i2ci.sda);
spic: if CFG_SPICTRL_ENABLE = 1 generate -- SPI controller
spi1 : spictrl
generic map (pindex => 10, paddr => 10, pmask => 16#fff#, pirq => 12,
fdepth => CFG_SPICTRL_FIFO, slvselen => CFG_SPICTRL_SLVREG,
slvselsz => CFG_SPICTRL_SLVS, odmode => 0, netlist => 0,
syncram => CFG_SPICTRL_SYNCRAM, ft => CFG_SPICTRL_FT)
port map (rstn, clkm, apbi, apbo(10), spii, spio, slvsel);
spii.spisel <= '1'; -- Master only
miso_pad : inpad generic map (tech => padtech)
port map (spi_data_out, spii.miso);
mosi_pad : outpad generic map (tech => padtech)
port map (spi_data_in, spio.mosi);
sck_pad : outpad generic map (tech => padtech)
port map (spi_clk, spio.sck);
slvsel_pad : outpad generic map (tech => padtech)
port map (spi_data_cs_b, slvsel(0));
end generate spic;
nospi: if CFG_SPICTRL_ENABLE = 0 generate
miso_pad : inpad generic map (tech => padtech)
port map (spi_data_out, spii.miso);
mosi_pad : outpad generic map (tech => padtech)
port map (spi_data_in, vcc(0));
sck_pad : outpad generic map (tech => padtech)
port map (spi_clk, gnd(0));
slvsel_pad : outpad generic map (tech => padtech)
port map (spi_data_cs_b, vcc(0));
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
stati <= ahbstat_in_none;
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
apb1 : apbctrl -- AHB/APB bridge
generic map (hindex => 6, haddr => CFG_APBADDR + 1, nslaves => 3)
port map (rstn, clkm, ahbsi, ahbso(6), apb1i, apb1o);
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth1 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(hindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 11, paddr => 11, pirq => 4, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 7,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
apbi => apbi, apbo => apbo(11), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (phy0_mdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2, level => cmos, voltage => x25v)
port map (phy0_txclk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2, level => cmos, voltage => x25v)
port map (phy0_rxclk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (phy0_rxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (phy0_rxctl_rxdv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (phy0_rxer, ethi.rx_er);
-- Collision detect and carrier sense are not connected on the
-- board.
ethi.rx_col <= '0';
ethi.rx_crs <= ethi.rx_dv;
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (phy0_txd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (phy0_txctl_txen, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (phy0_txer, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (phy0_mdc, etho.mdc);
erst_pad : outpad generic map (tech => padtech)
port map (phy0_reset, rstn);
-- ethi.gtx_clk <= egtx_clk;
end generate;
eth2 : if CFG_GRETH2 = 1 generate -- Gaisler ethernet MAC
sgmii_rst <= not rst;
refclk_bufds : IBUFDS
port map (
I => sgmiiclk_qo_p,
IB => sgmiiclk_qo_n,
O => sgmii_refclk);
e2 : greths generic map(hindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+CFG_GRETH,
pindex => 2, paddr => 2, pirq => 10,
fabtech => fabtech, memtech => memtech, transtech => transtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH2_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 7,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH21G)
port map(
rst => rstn,
clk => clkm,
ahbmi => ahbmi,
ahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+CFG_GRETH),
apbi => apb1i,
apbo => apb1o(2),
-- High-speed Serial Interface
clk_125 => sgmii_refclk,
rst_125 => sgmii_rst,
eth_rx_p => phy1_sgmii_rx_p,
eth_rx_n => phy1_sgmii_rx_n,
eth_tx_p => phy1_sgmii_tx_p,
eth_tx_n => phy1_sgmii_tx_n,
-- MDIO interface
reset => mdio_reset,
mdio_o => mdio_o,
mdio_oe => mdio_oe,
mdio_i => mdio_i,
mdc => mdc,
mdint => mdint,
-- Control signals
phyrstaddr => "00000",
edcladdr => "0000",
edclsepahb => '0',
edcldisable => '0'
);
e2mdio_pad : iopad generic map (tech => padtech)
port map (phy1_mdio, mdio_o, mdio_oe, mdio_i);
e2mdc_pad : outpad generic map (tech => padtech)
port map (phy1_mdc, mdc);
e2rst_pad : outpad generic map (tech => padtech)
port map (phy1_reset, mdio_reset);
e2int_pad : outpad generic map (tech => padtech)
port map (phy1_int, mdint);
end generate;
-----------------------------------------------------------------------
--- PCI ------------------------------------------------------------
----------------------------------------------------------------------
pp : if (CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET) /= 0 generate
pci0 : grpci2
generic map (
memtech => memtech,
oepol => 0,
hmindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+CFG_GRETH+CFG_GRETH2,
hdmindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+CFG_GRETH+CFG_GRETH2+1,
hsindex => 7,
haddr => 16#800#,
hmask => 16#c00#,
ioaddr => 16#400#,
pindex => 4,
paddr => 4,
irq => 5,
irqmode => 0,
master => CFG_GRPCI2_MASTER,
target => CFG_GRPCI2_TARGET,
dma => CFG_GRPCI2_DMA,
tracebuffer => CFG_GRPCI2_TRACE,
vendorid => CFG_GRPCI2_VID,
deviceid => CFG_GRPCI2_DID,
classcode => CFG_GRPCI2_CLASS,
revisionid => CFG_GRPCI2_RID,
cap_pointer => CFG_GRPCI2_CAP,
ext_cap_pointer => CFG_GRPCI2_NCAP,
iobase => CFG_AHBIO,
extcfg => CFG_GRPCI2_EXTCFG,
bar0 => CFG_GRPCI2_BAR0,
bar1 => CFG_GRPCI2_BAR1,
bar2 => CFG_GRPCI2_BAR2,
bar3 => CFG_GRPCI2_BAR3,
bar4 => CFG_GRPCI2_BAR4,
bar5 => CFG_GRPCI2_BAR5,
fifo_depth => CFG_GRPCI2_FDEPTH,
fifo_count => CFG_GRPCI2_FCOUNT,
conv_endian => CFG_GRPCI2_ENDIAN,
deviceirq => CFG_GRPCI2_DEVINT,
deviceirqmask => CFG_GRPCI2_DEVINTMSK,
hostirq => CFG_GRPCI2_HOSTINT,
hostirqmask => CFG_GRPCI2_HOSTINTMSK,
nsync => 2,
hostrst => 1,
bypass => CFG_GRPCI2_BYPASS,
debug => 0,
tbapben => 0,
tbpindex => 5,
tbpaddr => 16#400#,
tbpmask => 16#C00#
)
port map (
rstn,
clkm,
pciclk,
pci_dirq,
pcii,
pcio,
apbi,
apbo(4),
ahbsi,
ahbso(7),
ahbmi,
ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+CFG_GRETH+CFG_GRETH2),
ahbmi,
ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+CFG_GRETH+CFG_GRETH2+1)
);
pcia0 : if CFG_PCI_ARB = 1 generate -- PCI arbiter
pciarb0 : pciarb generic map (pindex => 13, paddr => 13, nb_agents => CFG_PCI_ARB_NGNT,
apb_en => CFG_PCI_ARBAPB)
port map (clk => pciclk, rst_n => pcii.rst, req_n => pci_arb_req, frame_n => pcii.frame,
gnt_n => pci_arb_gnt, pclk => clkm, prst_n => rstn, apbi => apbi, apbo => apbo(13));
-- Internal connection of req(2)
pci_arb_req(0 to 4) <= pci_arb_reql(0 to 1) & pci_reql & pci_arb_reql(3 to 4);
pci_arb_req(5 to 7) <= (others => '1');
end generate;
end generate;
nopcia0: if CFG_GRPCI2_MASTER = 0 or CFG_PCI_ARB = 0 generate
pci_arb_gnt <= (others => '1');
end generate;
nopci_mtf: if CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET = 0 generate
pcio <= pci_out_none;
end generate;
pgnt_pad : outpadv generic map (tech => padtech, width => 5, level => pci33)
port map (pci_p_gnt_b, pci_arb_gnt(0 to 4));
preq_pad : inpadv generic map (tech => padtech, width => 5, level => pci33)
port map (pci_p_req_b, pci_arb_reql);
pcipads0 : pcipads -- PCI pads
generic map (padtech => padtech, host => 2, int => 14, no66 => 1, onchipreqgnt => 1,
drivereset => 1, constidsel => 1)
port map (pci_rst => pci_p_rst_b, pci_gnt => pci_arb_gnt(2), pci_idsel => '0', --pci_fpga_idsel,
pci_lock => pci_p_lock_b, pci_ad => pci_p_ad, pci_cbe => pci_p_cbe_b,
pci_frame => pci_p_frame_b, pci_irdy => pci_p_irdy_b, pci_trdy => pci_p_trdy_b,
pci_devsel => pci_p_devsel_b, pci_stop => pci_p_stop_b, pci_perr => pci_p_perr_b,
pci_par => pci_p_par, pci_req => pci_reql, pci_serr => pci_p_serr_b,
pci_host => pci_host, pci_66 => pci_66, pcii => pcii, pcio => pcio, pci_int => pci_intv);
pci_intv <= pci_p_intd_b & pci_p_intc_b & pci_p_intb_b & pci_p_inta_b;
pci_host <= '0'; -- Always host
pci_66 <= '0';
-----------------------------------------------------------------------
--- SYSTEM MONITOR ---------------------------------------------------
-----------------------------------------------------------------------
grsmon: if CFG_GRSYSMON = 1 generate
sysm0 : grsysmon generic map (tech => fabtech, hindex => 8,
hirq => 1, caddr => 16#003#, cmask => 16#fff#,
saddr => 16#004#, smask => 16#ffe#, split => CFG_SPLIT,
extconvst => 0, wrdalign => 1, INIT_40 => X"0000",
INIT_41 => X"0000", INIT_42 => X"0800", INIT_43 => X"0000",
INIT_44 => X"0000", INIT_45 => X"0000", INIT_46 => X"0000",
INIT_47 => X"0000", INIT_48 => X"0000", INIT_49 => X"0000",
INIT_4A => X"0000", INIT_4B => X"0000", INIT_4C => X"0000",
INIT_4D => X"0000", INIT_4E => X"0000", INIT_4F => X"0000",
INIT_50 => X"0000", INIT_51 => X"0000", INIT_52 => X"0000",
INIT_53 => X"0000", INIT_54 => X"0000", INIT_55 => X"0000",
INIT_56 => X"0000", INIT_57 => X"0000",
SIM_MONITOR_FILE => "sysmon.txt")
port map (rstn, clkm, ahbsi, ahbso(8), sysmoni, sysmono);
sysmoni.convst <= '0';
sysmoni.convstclk <= '0';
sysmoni.vauxn <= (others => '0');
sysmoni.vauxp <= (others => '0');
-- sysmoni.vn <= test_mon_vn0_n;
-- sysmoni.vp <= test_mon_vp0_p;
end generate grsmon;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 9, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(9));
end generate;
-----------------------------------------------------------------------
--- AHB DEBUG --------------------------------------------------------
-----------------------------------------------------------------------
-- dma0 : ahbdma
-- generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_GRETH2+CFG_AHB_JTAG,
-- pindex => 13, paddr => 13, dbuf => 6)
-- port map (rstn, clkm, apbi, apbo(13), ahbmi,
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_GRETH2+CFG_AHB_JTAG));
-- at0 : ahbtrace
-- generic map ( hindex => 7, ioaddr => 16#200#, iomask => 16#E00#,
-- tech => memtech, irq => 0, kbytes => 8)
-- port map ( rstn, clkm, ahbmi, ahbsi, ahbso(7));
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (NCPU+CFG_AHB_UART+CFG_ETH+CFG_AHB_ETH+CFG_AHB_JTAG) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => system_table(XILINX_ML510),
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-3.0 | a5bf3ed7b609f70dcac4b9a296ff2394 | 0.571635 | 3.311871 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/testgrouppolito/pr/d2prc_edac.vhd | 1 | 24,522 | ------------------------------------------------------------------------------
-- Copyright (c) 2014, Pascal Trotta - Testgroup (Politecnico di Torino)
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright notice, this
-- list of conditions and the following disclaimer in the documentation and/or other
-- materials provided with the distribution.
--
-- THIS SOURCE CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-- OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
-----------------------------------------------------------------------------
-- Entity: d2prc_edac
-- File: d2prc_edac.vhd
-- Author: Pascal Trotta (TestGroup research group - Politecnico di Torino)
-- Contacts: [email protected] www.testgroup.polito.it
-- Description: dprc secded mode (see the DPR IP-core user manual for operations details).
-- Last revision: 14/08/2015
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.DMA2AHB_Package.all;
library testgrouppolito;
use testgrouppolito.dprc_pkg.all;
library techmap;
use techmap.gencomp.all;
entity d2prc_edac is
generic (
technology : integer := virtex4; -- Target technology
fifo_depth : integer := 9); -- true FIFO depth = 2**fifo_depth
port (
rstn : in std_ulogic; -- Asynchronous Reset input (active low)
clkm : in std_ulogic; -- Clock input
clk100 : in std_ulogic; -- 100 MHz Clock input
dmai : out DMA_In_Type; -- dma signals input
dmao : in DMA_Out_Type; -- dma signals output
icapi : out icap_in_type; -- icap input signals
icapo : in icap_out_type; -- icap output signals
apbregi : in dprc_apbregin_type; -- values from apb registers (control, address, rm_reset)
apbcontrol : out dprc_apbcontrol_type; -- control signals for apb register
rm_reset : out std_logic_vector(31 downto 0)); -- Reconfigurable modules reset (1 bit for each different reconfigurable partition);
end d2prc_edac;
architecture d2prc_edac_rtl of d2prc_edac is
type icap_state is (IDLE, START, READ_LENGTH, WRITE_ICAP, WRITE_ICAP_VERIFY, END_CONFIG, ABORT, ICAP_ERROR_LATENCY, ABORT_DED);
signal pstate, nstate : icap_state;
type ahb_state is (IDLE_AHB, START_AHB, GRANTED, WAIT_WRITE_END, BUS_CNTL_ERROR, FIFO_FULL, ICAP_ERROR, SECDED_ERROR);
signal present_state, next_state : ahb_state;
-- fifo types
type ififo_type is record
wen : std_ulogic;
waddress : std_logic_vector(fifo_depth downto 0);
waddress_gray : std_logic_vector(fifo_depth downto 0);
idata : std_logic_vector(31 downto 0);
full : std_ulogic;
end record;
type ofifo_type is record
ren : std_ulogic;
raddress : std_logic_vector(fifo_depth downto 0);
raddress_gray : std_logic_vector(fifo_depth downto 0);
odata : std_logic_vector(31 downto 0);
empty : std_ulogic;
end record;
-- cdc control signals for async_dprc
type cdc_async is record
start : std_ulogic;
stop : std_ulogic;
icap_errn : std_ulogic;
icap_end : std_ulogic;
secded_err : std_ulogic;
end record;
signal fifo_in, regfifo_in : ififo_type;
signal fifo_out, regfifo_out : ofifo_type;
signal raddr_sync, waddr_sync : std_logic_vector(fifo_depth downto 0);
signal cdc_ahb, rcdc_ahb, cdc_icap, rcdc_icap : cdc_async;
type regs_ahb is record
c_grant : std_logic_vector(19 downto 0);
c_ready : std_logic_vector(19 downto 0);
c_latency : std_logic_vector(2 downto 0);
rm_reset : std_logic_vector(31 downto 0);
address : std_logic_vector(31 downto 0);
rst_persist : std_ulogic;
end record;
type regs_icap is record
c_bitstream : std_logic_vector(19 downto 0);
c_latency : std_logic_vector(2 downto 0);
end record;
signal reg, regin : regs_ahb;
signal regicap, reginicap :regs_icap;
signal rstact : std_ulogic;
type encoded_data_buffer_in is record
renable : std_logic;
renable_d : std_logic;
raddress : std_logic_vector(2 downto 0);
raddress_d : std_logic_vector(2 downto 0);
idata : std_logic_vector(31 downto 0);
wenable : std_logic;
waddress : std_logic_vector(2 downto 0);
words_cnt : std_logic_vector(19 downto 0);
end record;
signal data_buf, rdata_buf : encoded_data_buffer_in;
signal data_buf_odata : std_logic_vector(31 downto 0);
signal secded5, r_secded5 : std_logic_vector(31 downto 0);
type decoding_type is record
encoded : std_logic_vector(38 downto 0);
parity : std_logic_vector(6 downto 0);
end record;
signal dec_sig, rdec_sig : decoding_type;
signal sec_cnt, rsec_cnt, rsec_cnt_ahb : std_logic_vector(19 downto 0);
begin
-- fixed signals
dmai.Data <= (others => '0');
dmai.Beat <= HINCR;
dmai.Size <= HSIZE32;
dmai.Store <= '0'; --Only read transfer requests
dmai.Reset <= not(rstn);
dmai.Address <= reg.address;
rm_reset <= reg.rm_reset;
fifo_in.idata <= dmao.Data;
-------------------------------
-- ahb bus clock domain
-------------------------------
ahbcomb: process(raddr_sync, regfifo_in, fifo_in, rcdc_ahb, cdc_ahb, reg, present_state, rstn, rstact, apbregi, dmao, rsec_cnt_ahb)
variable vfifo_in : ififo_type;
variable vcdc_ahb : cdc_async;
variable regv : regs_ahb;
variable raddr_sync_decoded : std_logic_vector(fifo_depth downto 0);
begin
apbcontrol.timer_clear <= '0';
apbcontrol.status_clr <= '0';
dmai.Request <= '0';
dmai.Burst <= '0';
dmai.Lock <= '0';
apbcontrol.status_value(23 downto 4) <= rsec_cnt_ahb;
apbcontrol.status_value(31 downto 24) <= (others=>'0');
apbcontrol.status_value(3 downto 0) <= (others=>'0');
apbcontrol.status_en <= '0';
apbcontrol.control_clr <= '0';
apbcontrol.timer_en <= '0';
rstact <= '0';
regv := reg;
vcdc_ahb := rcdc_ahb;
vcdc_ahb.start := '0';
vcdc_ahb.stop := '0';
-- initialize fifo signals
vfifo_in.waddress := regfifo_in.waddress;
vfifo_in.full := '0';
fifo_in.wen <= '0';
-- fifo full generation
gray_decoder(raddr_sync,fifo_depth,raddr_sync_decoded);
if (vfifo_in.waddress(fifo_depth)=raddr_sync_decoded(fifo_depth) and (vfifo_in.waddress(fifo_depth-1 downto 0)-raddr_sync_decoded(fifo_depth-1 downto 0))>(2**fifo_depth-16)) then
vfifo_in.full := '1';
elsif (vfifo_in.waddress(fifo_depth)/= raddr_sync_decoded(fifo_depth) and (raddr_sync_decoded(fifo_depth-1 downto 0)-vfifo_in.waddress(fifo_depth-1 downto 0))<16) then
vfifo_in.full := '1';
end if;
case present_state is
when IDLE_AHB =>
if (apbregi.control(19 downto 0)/=X"00000") then
next_state <= START_AHB;
apbcontrol.timer_clear <= '1'; -- clear timer register
apbcontrol.status_clr <= '1'; -- clear status register
regv.c_grant := apbregi.control(19 downto 0);
regv.c_ready := apbregi.control(19 downto 0);
regv.address := apbregi.address;
vcdc_ahb.start := '1'; -- start icap write controller
else
next_state <= IDLE_AHB;
end if;
when START_AHB =>
if (dmao.Grant and dmao.Ready)='1' then
next_state <= GRANTED;
else
next_state <= START_AHB;
end if;
dmai.Request <= '1'; -- Request data
dmai.Burst <= '1'; -- Burst transfer
dmai.Lock <= '1'; -- Locked transfer
vcdc_ahb.start := '1'; -- start icap write controller
fifo_in.wen <= dmao.Ready;
when GRANTED =>
if (regv.c_grant=0) then -- if the number of granted requests is equal to the bitstream words, no more requests are needed
next_state <= WAIT_WRITE_END;
elsif (vfifo_in.full='1') then
next_state<=FIFO_FULL;
else
next_state <= GRANTED;
dmai.Request <= '1'; -- Request data
dmai.Burst <= '1'; -- Burst transfer
dmai.Lock <= '1'; -- Locked transfer
end if;
fifo_in.wen <= dmao.Ready;
when FIFO_FULL =>
if ((regv.c_grant=regv.c_ready) and (vfifo_in.full='0')) then
next_state <= GRANTED;
else
next_state <= FIFO_FULL;
end if;
fifo_in.wen <= dmao.Ready;
when WAIT_WRITE_END =>
if (cdc_ahb.icap_end='1') then
next_state <= IDLE_AHB;
regv.rst_persist := '0';
apbcontrol.status_value(3 downto 0) <= "1111";
apbcontrol.status_en <= '1'; -- Write Status Register
apbcontrol.control_clr <= '1'; -- Clear Control Register
vfifo_in.waddress := (others=>'0');
else
next_state <= WAIT_WRITE_END;
end if;
fifo_in.wen <= dmao.Ready;
when BUS_CNTL_ERROR =>
next_state <= IDLE_AHB;
regv.rst_persist := '1';
apbcontrol.status_value(3 downto 0) <= "0100";
apbcontrol.status_en <= '1'; -- Write Status Register
apbcontrol.control_clr <= '1'; -- Clear Control Register
vfifo_in.waddress := (others=>'0');
vcdc_ahb.stop := '1';
when ICAP_ERROR =>
next_state <= IDLE_AHB;
regv.rst_persist := '1';
apbcontrol.status_value(3 downto 0) <= "1000";
apbcontrol.status_en <= '1'; -- Write Status Register
apbcontrol.control_clr <= '1'; -- Clear Control Register
vfifo_in.waddress := (others=>'0');
when SECDED_ERROR =>
next_state <= IDLE_AHB;
regv.rst_persist := '1';
apbcontrol.status_value(3 downto 0) <= "0010";
apbcontrol.status_en <= '1'; -- Write Status Register
apbcontrol.control_clr <= '1'; -- Clear Control Register
vfifo_in.waddress := (others=>'0');
end case;
if (present_state/=IDLE_AHB) and (cdc_ahb.icap_errn='0') then
next_state <= ICAP_ERROR;
end if;
if (present_state/=IDLE_AHB) and (cdc_ahb.secded_err='1') then
next_state <= SECDED_ERROR;
end if;
if (present_state/=IDLE_AHB) then
apbcontrol.timer_en <= '1'; -- Enable timer
rstact <= '1';
if dmao.Ready='1' then
regv.c_ready:=regv.c_ready-1;
end if;
if dmao.Grant='1' then
regv.c_grant:=regv.c_grant-1;
regv.address:=regv.address+4;
end if;
end if;
if (dmao.Fault or dmao.Retry)='1' then
next_state <= BUS_CNTL_ERROR;
vcdc_ahb.stop := '1';
end if;
-- write fifo
if fifo_in.wen = '1' then
vfifo_in.waddress := vfifo_in.waddress +1;
end if;
gray_encoder(vfifo_in.waddress,vfifo_in.waddress_gray);
-- latched fifo write address
fifo_in.waddress <= vfifo_in.waddress;
fifo_in.waddress_gray <= vfifo_in.waddress_gray;
-- update fifo full
fifo_in.full <= vfifo_in.full;
-- reconfigurable modules synchrounous reset generation (active high)
for i in 0 to 31 loop
regv.rm_reset(i) := not(rstn) or (apbregi.rm_reset(i) and (rstact or regv.rst_persist));
end loop;
-- registers assignment
cdc_ahb.start <= vcdc_ahb.start;
cdc_ahb.stop <= vcdc_ahb.stop;
regin <= regv;
end process;
ahbreg: process(clkm,rstn)
begin
if rstn='0' then
regfifo_in.waddress <= (others =>'0');
regfifo_in.waddress_gray <= (others =>'0');
rcdc_ahb.start <= '0';
rcdc_ahb.stop <= '0';
present_state <= IDLE_AHB;
reg.rm_reset <= (others=>'0');
reg.c_grant <= (others=>'0');
reg.c_ready <= (others=>'0');
reg.c_latency <= (others=>'0');
reg.address <= (others=>'0');
reg.rst_persist <= '0';
elsif rising_edge(clkm) then
regfifo_in <= fifo_in;
rcdc_ahb <= cdc_ahb;
present_state <= next_state;
reg <= regin;
end if;
end process;
-------------------------------
-- synchronization registers
-------------------------------
-- input d is already registered in the source clock domain
syn_gen0: for i in 0 to fifo_depth generate -- fifo addresses
syncreg_inst0: syncreg generic map (tech => technology, stages => 2)
port map(clk => clk100, d => regfifo_in.waddress_gray(i), q => waddr_sync(i));
syncreg_inst1: syncreg generic map (tech => technology, stages => 2)
port map(clk => clkm, d => regfifo_out.raddress_gray(i), q => raddr_sync(i));
end generate;
-- CDC control signals
syncreg_inst2: syncreg generic map (tech => technology, stages => 2)
port map(clk => clkm, d => rcdc_icap.icap_errn, q => cdc_ahb.icap_errn);
syncreg_inst3: syncreg generic map (tech => technology, stages => 2)
port map(clk => clkm, d => rcdc_icap.icap_end, q => cdc_ahb.icap_end);
syncreg_inst4: syncreg generic map (tech => technology, stages => 2)
port map(clk => clk100, d => rcdc_ahb.start, q => cdc_icap.start);
syncreg_inst5: syncreg generic map (tech => technology, stages => 2)
port map(clk => clk100, d => rcdc_ahb.stop, q => cdc_icap.stop);
syncreg_inst6: syncreg generic map (tech => technology, stages => 2)
port map(clk => clkm, d => rcdc_icap.secded_err, q => cdc_ahb.secded_err);
syn_gen1: for i in 0 to 19 generate
syncreg_inst1: syncreg generic map (tech => technology, stages => 2)
port map(clk => clkm, d => rsec_cnt(i), q => rsec_cnt_ahb(i));
end generate;
-------------------------------
-- icap clock domain
-------------------------------
icapcomb: process(waddr_sync, regfifo_out, fifo_out, cdc_icap, pstate, regicap, icapo, rdata_buf, data_buf_odata, rdec_sig, r_secded5, rsec_cnt)
variable vfifo_out : ofifo_type;
variable vcdc_icap : cdc_async;
variable vregicap : regs_icap;
variable vdata_buf : encoded_data_buffer_in;
variable vdec_sig : decoding_type;
variable checkbits : std_logic_vector(31 downto 0);
variable v_secded5 : std_logic_vector(31 downto 0);
variable status : std_logic_vector(1 downto 0);
variable vsec_cnt : std_logic_vector(19 downto 0);
variable decoded_data : std_logic_vector(31 downto 0);
begin
icapi.cen <= '1';
icapi.wen <= '1';
vcdc_icap.icap_end := '0';
vcdc_icap.icap_errn := '1';
vcdc_icap.secded_err := '0';
vregicap := regicap;
-- initialize buffer signals
vdata_buf.renable := rdata_buf.renable;
vdata_buf.renable_d := vdata_buf.renable;
vdata_buf.wenable := '0';
vdata_buf.idata := fifo_out.odata;
vdata_buf.raddress := rdata_buf.raddress;
vdata_buf.raddress_d := vdata_buf.raddress;
vdata_buf.waddress := rdata_buf.waddress;
vdata_buf.words_cnt := rdata_buf.words_cnt;
vdec_sig := rdec_sig;
v_secded5 := r_secded5;
vsec_cnt := rsec_cnt;
-- initialize fifo signals
vfifo_out.raddress := regfifo_out.raddress;
vfifo_out.empty := '0';
vfifo_out.ren := '0';
-- fifo empty generation
gray_encoder(vfifo_out.raddress,vfifo_out.raddress_gray);
if (vfifo_out.raddress_gray=waddr_sync) then
vfifo_out.empty := '1';
end if;
case pstate is
when IDLE =>
if (cdc_icap.start='1') then
nstate <= START;
else
nstate <= IDLE;
end if;
vdata_buf.words_cnt := (others => '0');
when START =>
if (fifo_out.empty='0') then
vfifo_out.ren := '1';
nstate <= READ_LENGTH;
else
nstate <= START;
end if;
icapi.wen <= '0';
vsec_cnt := (others=>'0'); -- reset SEC counter
when READ_LENGTH =>
nstate <= WRITE_ICAP;
-- Extract bitstream length removing out checkbits (i.e, bitstream length is represented on 20 bits, its value will be checked later)
vregicap.c_bitstream := fifo_out.odata(25 downto 17)&fifo_out.odata(15 downto 9)&fifo_out.odata(7 downto 5)&fifo_out.odata(3);
if (fifo_out.empty='0') then
vfifo_out.ren := '1';
end if;
icapi.wen <= '0';
when WRITE_ICAP =>
if (icapo.odata(7) = '1') then -- if the ICAP is correctly initialized, then monitor ICAP status
nstate <= WRITE_ICAP_VERIFY;
elsif (vregicap.c_bitstream=0) then
nstate <= ICAP_ERROR_LATENCY;
elsif (fifo_out.empty='0') then
nstate <= WRITE_ICAP;
vfifo_out.ren := '1';
else
nstate <= WRITE_ICAP;
end if;
icapi.wen <= '0';
if vdata_buf.words_cnt/=x"00000" then -- do not send first word to ICAP (i.e., bitstream words count)
icapi.cen <= not(rdata_buf.renable_d);
end if;
when WRITE_ICAP_VERIFY =>
if (icapo.odata(7) = '0') then -- verify ICAP status for configuration errors
nstate <= ABORT;
vcdc_icap.icap_errn:='0'; -- signal icap error to the ahb clock domain
elsif (vregicap.c_bitstream=0) then
nstate <= ICAP_ERROR_LATENCY;
elsif (fifo_out.empty='0') then
nstate <= WRITE_ICAP_VERIFY;
vfifo_out.ren := '1';
else
nstate <= WRITE_ICAP_VERIFY;
end if;
icapi.wen <= '0';
if vdata_buf.words_cnt/=x"00000" then
icapi.cen <= not(rdata_buf.renable_d);
end if;
when END_CONFIG =>
nstate <= IDLE;
vfifo_out.raddress := (others=>'0');
vcdc_icap.icap_end := '1';
when ABORT =>
if (vregicap.c_latency=4) then
nstate <= IDLE;
vregicap.c_latency := (others=>'0');
else
nstate <= ABORT;
vregicap.c_latency := vregicap.c_latency+1;
end if;
icapi.cen <= '0'; -- continue abort sequence
vcdc_icap.icap_errn:='0'; -- signal icap error to the ahb clock domain
vfifo_out.raddress := (others=>'0');
when ABORT_DED =>
if (vregicap.c_latency=4) then
nstate <= IDLE;
vregicap.c_latency := (others=>'0');
else
nstate <= ABORT_DED;
vregicap.c_latency := vregicap.c_latency+1;
end if;
icapi.cen <= '0'; -- continue abort sequence
vcdc_icap.secded_err := '1'; -- uncorrectable error
vfifo_out.raddress := (others=>'0');
vdata_buf.raddress := (others=>'0');
vdata_buf.waddress := (others=>'0');
vdata_buf.renable := '0';
when ICAP_ERROR_LATENCY =>
if (icapo.odata(7) = '0') then -- verify ICAP status for configuration errors
nstate <= ABORT;
vregicap.c_latency := (others=>'0');
vcdc_icap.icap_errn:='0'; -- signal icap error to the ahb clock domain
elsif (vregicap.c_latency=7) then -- to ensure that the last SECDED has been also verified
nstate <= END_CONFIG;
vregicap.c_latency := (others=>'0');
vcdc_icap.icap_end := '1';
else
nstate <= ICAP_ERROR_LATENCY;
vregicap.c_latency := vregicap.c_latency+1;
end if;
icapi.wen <= '0';
icapi.cen <= not(rdata_buf.renable_d);
end case;
if (cdc_icap.stop='1') then
nstate <= ABORT;
vregicap.c_latency := (others=>'0');
vfifo_out.ren := '1';
end if;
-- read fifo
if vfifo_out.ren = '1' then
vfifo_out.raddress := vfifo_out.raddress +1;
end if;
if regfifo_out.ren = '1' then
vregicap.c_bitstream := vregicap.c_bitstream -1; -- because fifo introduces 1-cycle latency on output data
end if;
-- latched fifo read address
fifo_out.raddress <= vfifo_out.raddress;
fifo_out.raddress_gray <= vfifo_out.raddress_gray;
-- update fifo empty
fifo_out.empty <= vfifo_out.empty;
cdc_icap.icap_errn <= vcdc_icap.icap_errn;
cdc_icap.icap_end <= vcdc_icap.icap_end;
cdc_icap.secded_err <= vcdc_icap.secded_err;
reginicap <= vregicap;
fifo_out.ren <= vfifo_out.ren;
-- read data from FIFO and write into 4-elements RAM (the 5th element of each SECDED group is stored in a register)
if (regfifo_out.ren = '1') then
if (rdata_buf.waddress/="100") then
vdata_buf.wenable := '1';
vdata_buf.waddress := vdata_buf.waddress + '1';
else
vdata_buf.waddress := (others=>'0');
v_secded5 := fifo_out.odata;
vdata_buf.renable := '1'; -- start decoding at the next cycle
end if;
end if;
-- decoding and error correction/detection
if rdata_buf.raddress="100" then
vdata_buf.renable := '0';
vdata_buf.raddress := (others=>'0');
end if;
if vdata_buf.renable = '1' then
vdata_buf.raddress := vdata_buf.raddress + '1';
end if;
if rdata_buf.renable = '1' then
vdec_sig.encoded := r_secded5(to_integer(unsigned(rdata_buf.raddress_d))*8+6 downto to_integer(unsigned(rdata_buf.raddress_d))*8)&data_buf_odata;
end if;
parity_gen(vdec_sig.encoded,vdec_sig.parity);
syndrome_gen_check(rdec_sig.encoded, rdec_sig.parity, decoded_data, status);
icapi.idata <= decoded_data;
if rdata_buf.renable_d='1' then
if ((status="10") or ((status="01") and (vdata_buf.words_cnt=x"00000"))) then -- abort is double error or if single error on bitstream size word
nstate <= ABORT_DED;
elsif status="01" then
vsec_cnt := rsec_cnt + '1';
end if;
end if;
if rdata_buf.renable_d = '1' then
vdata_buf.words_cnt := vdata_buf.words_cnt + '1'; -- counts words sent to the ICAP (debug)
end if;
dec_sig <= vdec_sig;
-- update buffer signals
data_buf <= vdata_buf;
secded5 <= v_secded5;
sec_cnt <= vsec_cnt;
end process;
icapreg: process(clk100,rstn)
begin
if rstn='0' then
regfifo_out.raddress <= (others =>'0');
regfifo_out.raddress_gray <= (others =>'0');
regfifo_out.ren <= '0';
regicap.c_bitstream <= (others =>'0');
regicap.c_latency <= (others =>'0');
rcdc_icap.start <= '0';
rcdc_icap.stop <= '0';
rcdc_icap.secded_err <= '0';
rdata_buf.raddress <= (others =>'0');
rdata_buf.raddress_d <= (others =>'0');
rdata_buf.waddress <= (others =>'0');
rdata_buf.renable <= '0';
rdata_buf.renable_d <= '0';
rdata_buf.idata <= (others =>'0');
rdata_buf.wenable <= '0';
rdata_buf.words_cnt <= (others =>'0');
rdec_sig.encoded <= (others=>'0');
rdec_sig.parity <= (others=>'0');
r_secded5 <= (others=>'0');
rsec_cnt <= (others=>'0');
elsif rising_edge(clk100) then
regfifo_out <= fifo_out;
pstate <= nstate;
regicap <= reginicap;
rcdc_icap <= cdc_icap;
rdata_buf <= data_buf;
rdec_sig <= dec_sig;
r_secded5 <= secded5;
rsec_cnt <= sec_cnt;
end if;
end process;
ram0 : syncram_2p generic map ( tech => technology, abits => fifo_depth, dbits => 32, sepclk => 1) -- 2**fifo_depth 32-bit data RAM
port map (clk100, fifo_out.ren, fifo_out.raddress(fifo_depth-1 downto 0), fifo_out.odata, clkm, fifo_in.wen, fifo_in.waddress(fifo_depth-1 downto 0), fifo_in.idata);
ram1 : syncram_2p generic map ( tech => technology, abits => 2, dbits => 32, sepclk => 0)
port map (clk100, data_buf.renable, rdata_buf.raddress(1 downto 0), data_buf_odata, clk100, data_buf.wenable, rdata_buf.waddress(1 downto 0), data_buf.idata);
end d2prc_edac_rtl;
| gpl-3.0 | ec2ce17b131564b9cdae0fdde195622c | 0.594364 | 3.597711 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-altera-ep2sgx90-av/config.vhd | 1 | 7,370 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := stratix2;
constant CFG_MEMTECH : integer := stratix2;
constant CFG_PADTECH : integer := stratix2;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := stratix2;
constant CFG_CLKMUL : integer := (2);
constant CFG_CLKDIV : integer := (2);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 4;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 4;
constant CFG_DSETSZ : integer := 8;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 0*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 4 + 64*0;
constant CFG_ATBSZ : integer := 4;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 1;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 1;
constant CFG_AHB_MONERR : integer := 1;
constant CFG_AHB_MONWAR : integer := 1;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#02007A#;
constant CFG_ETH_ENL : integer := 16#CC0001#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDR2SP : integer := 1;
constant CFG_DDR2SP_INIT : integer := 1;
constant CFG_DDR2SP_FREQ : integer := (200);
constant CFG_DDR2SP_TRFC : integer := (130);
constant CFG_DDR2SP_DATAWIDTH : integer := (64);
constant CFG_DDR2SP_FTEN : integer := 0;
constant CFG_DDR2SP_FTWIDTH : integer := 0;
constant CFG_DDR2SP_COL : integer := (10);
constant CFG_DDR2SP_SIZE : integer := (512);
constant CFG_DDR2SP_DELAY0 : integer := (0);
constant CFG_DDR2SP_DELAY1 : integer := (0);
constant CFG_DDR2SP_DELAY2 : integer := (0);
constant CFG_DDR2SP_DELAY3 : integer := (0);
constant CFG_DDR2SP_DELAY4 : integer := (0);
constant CFG_DDR2SP_DELAY5 : integer := (0);
constant CFG_DDR2SP_DELAY6 : integer := (0);
constant CFG_DDR2SP_DELAY7 : integer := (0);
constant CFG_DDR2SP_NOSYNC : integer := 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 64;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#FFFF#;
constant CFG_GRGPIO_WIDTH : integer := (32);
-- GRLIB debugging
constant CFG_DUART : integer := 1;
end;
| gpl-3.0 | e597ca7337e85fa9ca80fe4b1d323efe | 0.654817 | 3.589868 | false | false | false | false |
pwsoft/fpga_examples | rtl/video/video_vga_master.vhd | 1 | 5,512 | -- -----------------------------------------------------------------------
--
-- Syntiac VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2009 by Peter Wendrich ([email protected])
-- http://www.syntiac.com
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
--
-- VGA Video sync and timing generator
--
-- -----------------------------------------------------------------------
--
-- clk - video clock
-- clkDiv - Clock divider. 0=clk, 1=clk/2, 2=clk/3 ... 15=clk/16
-- hSync - Horizontal sync (sync polarity is set with hSyncPol)
-- vSync - Vertical sync (sync polarity is set with vSyncPol)
-- genlock_hold - Delay start of vertical sync while genlock hold is one.
-- This is used to sync the vga timing to another video source.
-- endOfPixel - Pixel clock is high each (clkDiv+1) clocks.
-- When clkDiv=0 is stays high continuously
-- endOfLine - High when the last pixel on the current line is displayed.
-- endOfFrame - High when the last pixel on the last line is displayed.
-- currentX - X coordinate of current pixel.
-- currentY - Y coordinate of current pixel.
--
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
-- -----------------------------------------------------------------------
entity video_vga_master is
generic (
clkDivBits : integer := 4
);
port (
-- System
clk : in std_logic;
clkDiv : in unsigned((clkDivBits-1) downto 0);
-- Sync outputs
hSync : out std_logic;
vSync : out std_logic;
-- Sync inputs
genlock_hold : in std_logic := '0';
-- Control outputs
endOfPixel : out std_logic;
endOfLine : out std_logic;
endOfFrame : out std_logic;
currentX : out unsigned(11 downto 0);
currentY : out unsigned(11 downto 0);
-- Configuration
hSyncPol : in std_logic := '1';
vSyncPol : in std_logic := '1';
xSize : in unsigned(11 downto 0);
ySize : in unsigned(11 downto 0);
xSyncFr : in unsigned(11 downto 0);
xSyncTo : in unsigned(11 downto 0);
ySyncFr : in unsigned(11 downto 0);
ySyncTo : in unsigned(11 downto 0)
);
end entity;
-- -----------------------------------------------------------------------
architecture rtl of video_vga_master is
signal clkDivCnt : unsigned(clkDiv'high downto 0) := (others => '0');
signal xCounter : unsigned(11 downto 0) := (others => '0');
signal yCounter : unsigned(11 downto 0) := (others => '0');
signal xCounterInc : unsigned(11 downto 0) := (others => '0');
signal yCounterInc : unsigned(11 downto 0) := (others => '0');
signal newPixel : std_logic := '0';
signal hSync_reg : std_logic;
signal vSync_reg : std_logic;
signal pixel_reg : std_logic := '0';
signal line_reg : std_logic := '0';
signal frame_reg : std_logic := '0';
begin
-- -----------------------------------------------------------------------
-- Copy of local signals as outputs (for vga-slaves)
hSync <= hSync_reg;
vSync <= vSync_reg;
currentX <= xCounter;
currentY <= yCounter;
endOfPixel <= pixel_reg;
endOfLine <= line_reg;
endOfFrame <= frame_reg;
-- -----------------------------------------------------------------------
-- X & Y counters
process(clk)
begin
if rising_edge(clk) then
yCounterInc <= yCounter + 1;
pixel_reg <= '0';
line_reg <= '0';
frame_reg <= '0';
if newPixel = '1' then
pixel_reg <= '1';
xCounter <= xCounterInc;
if xCounterInc = xSize then
line_reg <= '1';
xCounter <= (others => '0');
if (genlock_hold = '0') or (yCounterInc < ySyncFr) then
yCounter <= yCounterInc;
end if;
if yCounterInc = ySize then
frame_reg <= '1';
yCounter <= (others => '0');
end if;
end if;
end if;
end if;
end process;
xCounterInc <= xCounter + 1;
-- -----------------------------------------------------------------------
-- Clock divider
process(clk)
begin
if rising_edge(clk) then
newPixel <= '0';
clkDivCnt <= clkDivCnt + 1;
if clkDivCnt = clkDiv then
clkDivCnt <= (others => '0');
newPixel <= '1';
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- hSync
process(clk)
begin
if rising_edge(clk) then
hSync_reg <= not hSyncPol;
if xCounter >= xSyncFr
and xCounter < xSyncTo then
hSync_reg <= hSyncPol;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- vSync
process(clk)
begin
if rising_edge(clk) then
if xCounter = xSyncFr then
vSync_reg <= not vSyncPol;
if yCounter >= ySyncFr
and yCounter < ySyncTo then
vSync_reg <= vSyncPol;
end if;
end if;
end if;
end process;
end architecture;
| lgpl-2.1 | 79ac1177dbae290e0a6ead219ba03bf2 | 0.545174 | 3.706792 | false | false | false | false |
pwsoft/fpga_examples | rtl/designs/gigatron/gigatron_tb.vhd | 1 | 2,246 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity gigatron_tb is
end entity;
architecture rtl of gigatron_tb is
signal clk : std_logic := '0';
signal stop : std_logic := '0';
signal reset : std_logic := '1';
signal spi_req : std_logic;
signal red : unsigned(4 downto 0);
signal grn : unsigned(4 downto 0);
signal blu : unsigned(4 downto 0);
signal hsync : std_logic;
signal vsync : std_logic;
signal ram_data : unsigned(15 downto 0);
signal ram_addr : unsigned(12 downto 0);
signal ram_ba : unsigned(1 downto 0);
signal ram_we : std_logic;
signal ram_ras : std_logic;
signal ram_cas : std_logic;
signal ram_ldqm : std_logic;
signal ram_udqm : std_logic;
signal rom_a : unsigned(15 downto 0);
signal rom_q : unsigned(15 downto 0);
begin
clk <= (not stop) and (not clk) after 5 ns;
gigatron_inst : entity work.gigatron_top
generic map (
clk_ticks_per_usec => 100,
romload_size => 32
)
port map (
clk => clk,
reset => reset,
flashslot => "11000",
joystick => (others => '1'),
-- SPI interface
spi_cs_n => open,
spi_req => spi_req,
spi_ack => spi_req,
spi_d => open,
spi_q => X"00",
-- SDRAM interface
ram_data => ram_data,
ram_addr => ram_addr,
ram_ba => ram_ba,
ram_we => ram_we,
ram_ras => ram_ras,
ram_cas => ram_cas,
ram_ldqm => ram_ldqm,
ram_udqm => ram_udqm,
-- Video
red => red,
grn => grn,
blu => blu,
hsync => hsync,
vsync => vsync
);
rom_inst : entity work.gigatron_tb_rom
port map (
a => rom_a,
q => rom_q
);
sdram_emu_blk : block
signal oe_reg : std_logic := '0';
signal a_reg : unsigned(15 downto 0) := (others => '0');
begin
rom_a <= a_reg;
ram_data <= rom_q when oe_reg = '1' else (others => '0');
process(clk)
begin
if rising_edge(clk) then
if ram_ras = '0' then
a_reg(15 downto 9) <= ram_addr(6 downto 0);
oe_reg <= '0';
end if;
if (ram_cas = '0') and (ram_we = '1') then
a_reg(8 downto 0) <= ram_addr(8 downto 0);
oe_reg <= '1';
end if;
end if;
end process;
end block;
process
begin
reset <= '1';
wait for 1 us;
reset <= '0';
wait for 1000000 us;
stop <= '1';
wait;
end process;
end architecture;
| lgpl-2.1 | 50f4231fe22a4564f6cda7ff3cba1c3f | 0.593054 | 2.654846 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/subsys/subsys.vhd | 1 | 6,206 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: subsys
-- File: subsys.vhd
-- Author: Cobham Gaisler AB
-- Description: Package for GRLIB subsystems
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
package subsys is
type leon_dsu_stat_base_out_type is record
dsu_active : std_ulogic;
dsu_tstop : std_ulogic;
proc_error : std_ulogic;
proc_errorn : std_ulogic;
end record;
type leon_dsu_stat_base_in_type is record
dsu_enable : std_ulogic;
dsu_break : std_ulogic;
end record;
component leon_dsu_stat_base
generic (
-- LEON selection
leon : integer range 0 to 4 := 0;
ncpu : integer range 1 to 16 := 1;
-- LEON configuration
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 63 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 7 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 31 := 0; -- support SMP systems
cached : integer := 0; -- cacheability table
clk2x : integer := 0;
wbmask : integer := 0; -- Wide-bus mask
busw : integer := 64; -- AHB/Cache data width (64/128)
netlist : integer := 0; -- Use netlist
ft : integer := 0; -- FT option
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0;
rex : integer range 0 to 1 := 0;
altwin : integer range 0 to 1 := 0;
ahbpipe : integer := 0;
--
grfpush : integer range 0 to 1 := 0;
-- DSU
dsu_hindex : integer := 2;
dsu_haddr : integer := 16#900#;
dsu_hmask : integer := 16#F00#;
atbsz : integer := 4;
--
stat : integer range 0 to 1 := 0;
stat_pindex : integer := 0;
stat_paddr : integer := 0;
stat_pmask : integer := 16#ffc#;
stat_ncnt : integer := 1;
stat_nmax : integer := 0
--
);
port (
rstn : in std_ulogic;
--
ahbclk : in std_ulogic; -- bus clock
cpuclk : in std_ulogic; -- cpu clock
hclken : in std_ulogic; -- bus clock enable qualifier
--
leon_ahbmi : in ahb_mst_in_type;
leon_ahbmo : out ahb_mst_out_vector_type(ncpu-1 downto 0);
leon_ahbsi : in ahb_slv_in_type;
leon_ahbso : in ahb_slv_out_vector;
--
irqi : in irq_in_vector(0 to ncpu-1);
irqo : out irq_out_vector(0 to ncpu-1);
--
stat_apbi : in apb_slv_in_type;
stat_apbo : out apb_slv_out_type;
stat_ahbsi : in ahb_slv_in_type;
stati : in l3stat_in_type;
--
dsu_ahbsi : in ahb_slv_in_type;
dsu_ahbso : out ahb_slv_out_type;
dsu_tahbmi : in ahb_mst_in_type;
dsu_tahbsi : in ahb_slv_in_type;
--
sysi : in leon_dsu_stat_base_in_type;
syso : out leon_dsu_stat_base_out_type
);
end component;
end;
package body subsys is
end;
| gpl-3.0 | 1c7d92f9880863414906ab1fef901854 | 0.522559 | 3.752116 | false | false | false | false |
pwsoft/fpga_examples | rtl/video/video_dither.vhd | 1 | 2,560 | -- -----------------------------------------------------------------------
--
-- Syntiac VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2009 by Peter Wendrich ([email protected])
-- http://www.syntiac.com
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
--
-- Video dither block. Converts high precision video signal to
-- lower precision by dithering. The dither input can for example
-- come from the current X and Y coordinates or a pseudo random source.
--
-- If bypass input is 1 the dither algorithm is disabled and the output
-- is equal to the input.
--
-- This component has a delay of one clock cycle.
--
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- -----------------------------------------------------------------------
entity video_dither is
generic (
dBits : integer := 8;
qBits : integer := 5;
ditherBits : integer := 4
);
port (
clk : in std_logic;
clkEna : in std_logic := '1';
bypass : in std_logic := '0';
dither : in unsigned(ditherBits-1 downto 0);
d : in unsigned(dBits-1 downto 0);
q : out unsigned(qBits-1 downto 0)
);
end entity;
-- -----------------------------------------------------------------------
architecture rtl of video_dither is
constant tempBits : integer := qBits + ditherBits + 1;
begin
process(clk)
variable t : unsigned((tempBits-1) downto 0);
begin
if rising_edge(clk) then
if clkEna = '1' then
t := ("0" & d & to_unsigned(0, t'high-d'length)) + dither;
if t(t'high) = '1' then
q <= (others => '1');
else
q <= t((t'high-1) downto (t'high-qBits));
end if;
if bypass = '1' then
q <= d(d'high downto (d'high-q'high));
end if;
end if;
end if;
end process;
end architecture;
| lgpl-2.1 | 9e9eda83ef13e3e5a5be57deb3c710a9 | 0.560547 | 3.838081 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/i2c/i2c2ahb_apb.vhd | 1 | 7,393 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: i2c2ahb_apb
-- File: i2c2ahb_apb.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- Contact: [email protected]
-- Description: Simple I2C-slave providing a bridge to AMBA AHB
-- This entity provides an APB interface for setting defining the
-- AHB address window that can be accessed from I2C.
-- See i2c2ahbx.vhd and GRIP for documentation
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.i2c.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.conv_std_logic;
use grlib.stdlib.conv_std_logic_vector;
entity i2c2ahb_apb is
generic (
-- AHB Configuration
hindex : integer := 0;
--
ahbaddrh : integer := 0;
ahbaddrl : integer := 0;
ahbmaskh : integer := 0;
ahbmaskl : integer := 0;
resen : integer := 0;
-- APB configuration
pindex : integer := 0; -- slave bus index
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
-- I2C configuration
i2cslvaddr : integer range 0 to 127 := 0;
i2ccfgaddr : integer range 0 to 127 := 0;
oepol : integer range 0 to 1 := 0;
--
filter : integer range 2 to 512 := 2
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
--
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
-- I2C signals
i2ci : in i2c_in_type;
i2co : out i2c_out_type
);
end entity i2c2ahb_apb;
architecture rtl of i2c2ahb_apb is
-- Register offsets
constant CTRL_OFF : std_logic_vector(4 downto 2) := "000";
constant STS_OFF : std_logic_vector(4 downto 2) := "001";
constant ADDR_OFF : std_logic_vector(4 downto 2) := "010";
constant MASK_OFF : std_logic_vector(4 downto 2) := "011";
constant SLVA_OFF : std_logic_vector(4 downto 2) := "100";
constant SLVC_OFF : std_logic_vector(4 downto 2) := "101";
-- AMBA PnP
constant PCONFIG : apb_config_type := (
0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_I2C2AHB, 0, 0, pirq),
1 => apb_iobar(paddr, pmask));
type apb_reg_type is record
i2c2ahbi : i2c2ahb_in_type;
irq : std_ulogic;
irqen : std_ulogic;
prot : std_ulogic;
protx : std_ulogic;
wr : std_ulogic;
dma : std_ulogic;
dmax : std_ulogic;
end record;
signal r, rin : apb_reg_type;
signal i2c2ahbo : i2c2ahb_out_type;
begin
bridge : i2c2ahbx
generic map (hindex => hindex, oepol => oepol, filter => filter)
port map (rstn => rstn, clk => clk, ahbi => ahbi, ahbo => ahbo,
i2ci => i2ci, i2co => i2co, i2c2ahbi => r.i2c2ahbi,
i2c2ahbo => i2c2ahbo);
comb: process (r, rstn, apbi, i2c2ahbo)
variable v : apb_reg_type;
variable apbaddr : std_logic_vector(4 downto 2);
variable apbout : std_logic_vector(31 downto 0);
variable irqout : std_logic_vector(NAHBIRQ-1 downto 0);
begin
v := r; apbaddr := apbi.paddr(apbaddr'range); apbout := (others => '0');
v.irq := '0'; irqout := (others => '0'); irqout(pirq) := r.irq;
v.protx := i2c2ahbo.prot; v.dmax := i2c2ahbo.dma;
---------------------------------------------------------------------------
-- APB register interface
---------------------------------------------------------------------------
-- read registers
if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
case apbaddr is
when CTRL_OFF => apbout(1 downto 0) := r.irqen & r.i2c2ahbi.en;
when STS_OFF => apbout(2 downto 0) := r.prot & r.wr & r.dma;
when ADDR_OFF => apbout := r.i2c2ahbi.haddr;
when MASK_OFF => apbout := r.i2c2ahbi.hmask;
when SLVA_OFF => apbout(6 downto 0) := r.i2c2ahbi.slvaddr;
when SLVC_OFF => apbout(6 downto 0) := r.i2c2ahbi.cfgaddr;
when others => null;
end case;
end if;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbaddr is
when CTRL_OFF => v.irqen := apbi.pwdata(1); v.i2c2ahbi.en := apbi.pwdata(0);
when STS_OFF => v.dma := r.dma and not apbi.pwdata(0);
v.prot := r.prot and not apbi.pwdata(2);
when ADDR_OFF => v.i2c2ahbi.haddr := apbi.pwdata;
when MASK_OFF => v.i2c2ahbi.hmask := apbi.pwdata;
when SLVA_OFF => v.i2c2ahbi.slvaddr := apbi.pwdata(6 downto 0);
when SLVC_OFF => v.i2c2ahbi.cfgaddr := apbi.pwdata(6 downto 0);
when others => null;
end case;
end if;
-- interrupt and status register handling
if ((i2c2ahbo.dma and not r.dmax) or
(i2c2ahbo.prot and not r.protx)) = '1' then
v.dma := '1'; v.prot := r.prot or i2c2ahbo.prot; v.wr := i2c2ahbo.wr;
if (r.irqen and not r.dma) = '1' then v.irq := '1'; end if;
end if;
---------------------------------------------------------------------------
-- reset
---------------------------------------------------------------------------
if rstn = '0' then
v.i2c2ahbi.en := conv_std_logic(resen = 1);
v.i2c2ahbi.haddr := conv_std_logic_vector(ahbaddrh, 16) &
conv_std_logic_vector(ahbaddrl, 16);
v.i2c2ahbi.hmask := conv_std_logic_vector(ahbmaskh, 16) &
conv_std_logic_vector(ahbmaskl, 16);
v.i2c2ahbi.slvaddr := conv_std_logic_vector(i2cslvaddr, 7);
v.i2c2ahbi.cfgaddr := conv_std_logic_vector(i2ccfgaddr, 7);
v.irqen := '0'; v.prot := '0'; v.wr := '0'; v.dma := '0';
end if;
---------------------------------------------------------------------------
-- signal assignments
---------------------------------------------------------------------------
-- update registers
rin <= v;
-- update outputs
apbo.prdata <= apbout;
apbo.pirq <= irqout;
apbo.pconfig <= PCONFIG;
apbo.pindex <= pindex;
end process comb;
reg: process(clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process reg;
-- Boot message provided in i2c2ahbx...
end architecture rtl;
| gpl-3.0 | 9a0f07e049f8b89bfc182057871e9201 | 0.548898 | 3.537321 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/tech/atc18/components/atmel_simprims.vhd | 1 | 7,922 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: Various
-- File: atmel_simprims.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: ATMEL ATC18 behavioural models
-- Modelled after IO33/PCILIB data sheets
------------------------------------------------------------------------------
-- pragma translate_off
-- input pad
library ieee;
use ieee.std_logic_1164.all;
entity pc33d00z is port (pad : in std_logic; cin : out std_logic); end;
architecture rtl of pc33d00z is begin cin <= to_x01(pad) after 1 ns; end;
-- input pad with pull-up
library ieee;
use ieee.std_logic_1164.all;
entity pc33d00uz is port (pad : inout std_logic; cin : out std_logic); end;
architecture rtl of pc33d00uz is
begin cin <= to_x01(pad) after 1 ns; pad <= 'H'; end;
-- input schmitt pad
library ieee;
use ieee.std_logic_1164.all;
entity pc33d20z is port (pad : in std_logic; cin : out std_logic); end;
architecture rtl of pc33d20z is begin cin <= to_x01(pad) after 1 ns; end;
-- input schmitt pad with pull-up
library ieee;
use ieee.std_logic_1164.all;
entity pc33d20uz is port (pad : inout std_logic; cin : out std_logic); end;
architecture rtl of pc33d20uz is
begin cin <= to_x01(pad) after 1 ns; pad <= 'H'; end;
-- output pads
library ieee; use ieee.std_logic_1164.all;
entity pt33o01z is port (i : in std_logic; pad : out std_logic); end;
architecture rtl of pt33o01z is begin pad <= to_x01(i) after 2 ns; end;
library ieee; use ieee.std_logic_1164.all;
entity pt33o02z is port (i : in std_logic; pad : out std_logic); end;
architecture rtl of pt33o02z is begin pad <= to_x01(i) after 2 ns; end;
library ieee; use ieee.std_logic_1164.all;
entity pt33o04z is port (i : in std_logic; pad : out std_logic); end;
architecture rtl of pt33o04z is begin pad <= to_x01(i) after 2 ns; end;
library ieee; use ieee.std_logic_1164.all;
entity pt33o08z is port (i : in std_logic; pad : out std_logic); end;
architecture rtl of pt33o08z is begin pad <= to_x01(i) after 2 ns; end;
-- output tri-state pads
library ieee; use ieee.std_logic_1164.all;
entity pt33t01z is port (i, oen : in std_logic; pad : out std_logic); end;
architecture rtl of pt33t01z is
begin pad <= to_x01(i) after 2 ns when oen = '0' else 'H' after 2 ns; end;
library ieee; use ieee.std_logic_1164.all;
entity pt33t02z is port (i, oen : in std_logic; pad : out std_logic); end;
architecture rtl of pt33t02z is
begin pad <= to_x01(i) after 2 ns when oen = '0' else 'H' after 2 ns; end;
library ieee; use ieee.std_logic_1164.all;
entity pt33t04z is port (i, oen : in std_logic; pad : out std_logic); end;
architecture rtl of pt33t04z is
begin pad <= to_x01(i) after 2 ns when oen = '0' else 'H' after 2 ns; end;
library ieee; use ieee.std_logic_1164.all;
entity pt33t08z is port (i, oen : in std_logic; pad : out std_logic); end;
architecture rtl of pt33t08z is
begin pad <= to_x01(i) after 2 ns when oen = '0' else 'H' after 2 ns; end;
-- output tri-state pads with pull-up
library ieee; use ieee.std_logic_1164.all;
entity pt33t01uz is port (i, oen : in std_logic; pad : out std_logic); end;
architecture rtl of pt33t01uz is
begin pad <= to_x01(i) after 2 ns when oen = '0' else 'H' after 2 ns; end;
library ieee; use ieee.std_logic_1164.all;
entity pt33t02uz is port (i, oen : in std_logic; pad : out std_logic); end;
architecture rtl of pt33t02uz is
begin pad <= to_x01(i) after 2 ns when oen = '0' else 'H' after 2 ns; end;
library ieee; use ieee.std_logic_1164.all;
entity pt33t04uz is port (i, oen : in std_logic; pad : out std_logic); end;
architecture rtl of pt33t04uz is
begin pad <= to_x01(i) after 2 ns when oen = '0' else 'H' after 2 ns; end;
-- bidirectional pad
library ieee; use ieee.std_logic_1164.all;
entity pt33b01z is
port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end;
architecture rtl of pt33b01z is
begin
pad <= to_x01(i) after 2 ns when oen = '0' else 'Z' after 2 ns;
cin <= to_x01(pad) after 1 ns;
end;
library ieee; use ieee.std_logic_1164.all;
entity pt33b02z is
port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end;
architecture rtl of pt33b02z is
begin
pad <= to_x01(i) after 2 ns when oen = '0' else 'Z' after 2 ns;
cin <= to_x01(pad) after 1 ns;
end;
library ieee; use ieee.std_logic_1164.all;
entity pt33b08z is
port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end;
architecture rtl of pt33b08z is
begin
pad <= to_x01(i) after 2 ns when oen = '0' else 'Z' after 2 ns;
cin <= to_x01(pad) after 1 ns;
end;
library ieee; use ieee.std_logic_1164.all;
entity pt33b04z is
port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end;
architecture rtl of pt33b04z is
begin
pad <= to_x01(i) after 2 ns when oen = '0' else 'Z' after 2 ns;
cin <= to_x01(pad) after 1 ns;
end;
-- bidirectional pads with pull-up
library ieee;
use ieee.std_logic_1164.all;
entity pt33b01uz is
port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end;
architecture rtl of pt33b01uz is
begin
pad <= to_x01(i) after 2 ns when oen = '0' else 'H' after 2 ns;
cin <= to_x01(pad) after 1 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity pt33b02uz is
port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end;
architecture rtl of pt33b02uz is
begin
pad <= to_x01(i) after 2 ns when oen = '0' else 'H' after 2 ns;
cin <= to_x01(pad) after 1 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity pt33b08uz is
port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end;
architecture rtl of pt33b08uz is
begin
pad <= to_x01(i) after 2 ns when oen = '0' else 'H' after 2 ns;
cin <= to_x01(pad) after 1 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity pt33b04uz is
port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end;
architecture rtl of pt33b04uz is
begin
pad <= to_x01(i) after 2 ns when oen = '0' else 'H' after 2 ns;
cin <= to_x01(pad) after 1 ns;
end;
-- PCI output pad
library ieee; use ieee.std_logic_1164.all;
entity pp33o01z is port (i : in std_logic; pad : out std_logic); end;
architecture rtl of pp33o01z is begin pad <= to_x01(i) after 2 ns; end;
-- PCI bidirectional pad
library ieee; use ieee.std_logic_1164.all;
entity pp33b01z is
port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end;
architecture rtl of pp33b01z is
begin
pad <= to_x01(i) after 2 ns when oen = '0' else 'Z' after 2 ns;
cin <= to_x01(pad) after 1 ns;
end;
-- PCI output tri-state pad
library ieee; use ieee.std_logic_1164.all;
entity pp33t01z is port (i, oen : in std_logic; pad : out std_logic); end;
architecture rtl of pp33t01z is
begin pad <= to_x01(i) after 2 ns when oen = '0' else 'Z' after 2 ns; end;
-- pragma translate_on
| gpl-3.0 | 75cd418122ac9b4e3cde49518f68113e | 0.667634 | 2.875499 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/sim/phy.vhd | 1 | 24,648 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
----------------------------------------------------------------------------
-- Entity: phy
-- File: phy.vhd
-- Description: Simulation model of an Ethernet PHY
-- Author: Marko Isomaki
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
library grlib;
use ieee.std_logic_1164.all;
use grlib.stdlib.all;
entity phy is
generic(
address : integer range 0 to 31 := 0;
extended_regs : integer range 0 to 1 := 1;
aneg : integer range 0 to 1 := 1;
base100_t4 : integer range 0 to 1 := 0;
base100_x_fd : integer range 0 to 1 := 1;
base100_x_hd : integer range 0 to 1 := 1;
fd_10 : integer range 0 to 1 := 1;
hd_10 : integer range 0 to 1 := 1;
base100_t2_fd : integer range 0 to 1 := 1;
base100_t2_hd : integer range 0 to 1 := 1;
base1000_x_fd : integer range 0 to 1 := 0;
base1000_x_hd : integer range 0 to 1 := 0;
base1000_t_fd : integer range 0 to 1 := 1;
base1000_t_hd : integer range 0 to 1 := 1;
rmii : integer range 0 to 1 := 0;
rgmii : integer range 0 to 1 := 0
);
port(
rstn : in std_logic;
mdio : inout std_logic;
tx_clk : out std_logic;
rx_clk : out std_logic;
rxd : out std_logic_vector(7 downto 0);
rx_dv : out std_logic;
rx_er : out std_logic;
rx_col : out std_logic;
rx_crs : out std_logic;
txd : in std_logic_vector(7 downto 0);
tx_en : in std_logic;
tx_er : in std_logic;
mdc : in std_logic;
gtx_clk : in std_logic
);
end;
architecture behavioral of phy is
type mdio_state_type is (idle, start_of_frame, start_of_frame2, op, phyad, regad,
ta, rdata, wdata);
type ctrl_reg_type is record
reset : std_ulogic;
loopback : std_ulogic;
speedsel : std_logic_vector(1 downto 0);
anegen : std_ulogic;
powerdown : std_ulogic;
isolate : std_ulogic;
restartaneg : std_ulogic;
duplexmode : std_ulogic;
coltest : std_ulogic;
end record;
type status_reg_type is record
base100_t4 : std_ulogic;
base100_x_fd : std_ulogic;
base100_x_hd : std_ulogic;
fd_10 : std_ulogic;
hd_10 : std_ulogic;
base100_t2_fd : std_ulogic;
base100_t2_hd : std_ulogic;
extstat : std_ulogic;
mfpreamblesup : std_ulogic;
anegcmpt : std_ulogic;
remfault : std_ulogic;
anegability : std_ulogic;
linkstat : std_ulogic;
jabdetect : std_ulogic;
extcap : std_ulogic;
end record;
type aneg_ab_type is record
next_page : std_ulogic;
remote_fault : std_ulogic;
tech_ability : std_logic_vector(7 downto 0);
selector : std_logic_vector(4 downto 0);
end record;
type aneg_exp_type is record
par_detct_flt : std_ulogic;
lp_np_able : std_ulogic;
np_able : std_ulogic;
page_rx : std_ulogic;
lp_aneg_able : std_ulogic;
end record;
type aneg_nextpage_type is record
next_page : std_ulogic;
message_page : std_ulogic;
ack2 : std_ulogic;
toggle : std_ulogic;
message : std_logic_vector(10 downto 0);
end record;
type mst_slv_ctrl_type is record
tmode : std_logic_vector(2 downto 0);
manualcfgen : std_ulogic;
cfgval : std_ulogic;
porttype : std_ulogic;
base1000_t_fd : std_ulogic;
base1000_t_hd : std_ulogic;
end record;
type mst_slv_status_type is record
cfgfault : std_ulogic;
cfgres : std_ulogic;
locrxstate : std_ulogic;
remrxstate : std_ulogic;
lpbase1000_t_fd : std_ulogic;
lpbase1000_t_hd : std_ulogic;
idlerrcnt : std_logic_vector(7 downto 0);
end record;
type extended_status_reg_type is record
base1000_x_fd : std_ulogic;
base1000_x_hd : std_ulogic;
base1000_t_fd : std_ulogic;
base1000_t_hd : std_ulogic;
end record;
type reg_type is record
state : mdio_state_type;
cnt : integer;
op : std_logic_vector(1 downto 0);
phyad : std_logic_vector(4 downto 0);
regad : std_logic_vector(4 downto 0);
wr : std_ulogic;
regtmp : std_logic_vector(15 downto 0);
-- MII management registers
ctrl : ctrl_reg_type;
status : status_reg_type;
anegadv : aneg_ab_type;
aneglp : aneg_ab_type;
anegexp : aneg_exp_type;
anegnptx : aneg_nextpage_type;
anegnplp : aneg_nextpage_type;
mstslvctrl : mst_slv_ctrl_type;
mstslvstat : mst_slv_status_type;
extstatus : extended_status_reg_type;
rstcnt : integer;
anegcnt : integer;
end record;
signal r, rin : reg_type;
signal int_clk : std_ulogic := '0';
signal clkslow : std_ulogic := '0';
signal rcnt : integer;
signal anegact : std_ulogic;
begin
--mdio signal pull-up
int_clk <= not int_clk after 10 ns when rmii = 1 else
not int_clk after 4 ns when r.ctrl.speedsel = "01" else
not int_clk after 20 ns when r.ctrl.speedsel = "10" else
not int_clk after 200 ns when r.ctrl.speedsel = "00";
clkslow <= not clkslow after 20 ns when r.ctrl.speedsel = "10" else
not clkslow after 200 ns;
-- rstdelay : process
-- begin
-- loop
-- rstd <= '0';
-- while r.ctrl.reset /= '1' loop
-- wait on r.ctrl.reset;
-- end loop;
-- rstd <= '1';
-- while rstn = '0' loop
-- wait on rstn;
-- end loop;
-- wait on rstn for 3 us;
-- rstd <= '0';
-- wait on rstn until r.ctrl.reset = '0' for 5 us;
-- end loop;
-- end process;
anegproc : process is
begin
loop
anegact <= '0';
while rstn /= '1' loop
wait on rstn;
end loop;
while rstn = '1' loop
if r.ctrl.anegen = '0' then
anegact <= '0';
wait on rstn, r.ctrl.anegen, r.ctrl.restartaneg;
else
if r.ctrl.restartaneg = '1' then
anegact <= '1';
wait on rstn, r.ctrl.restartaneg, r.ctrl.anegen for 2 us;
anegact <= '0';
wait on rstn, r.ctrl.anegen until r.ctrl.restartaneg = '0';
if (rstn and r.ctrl.anegen) = '1' then
wait on rstn, r.ctrl.anegen, r.ctrl.restartaneg;
end if;
else
anegact <= '0';
wait on rstn, r.ctrl.restartaneg, r.ctrl.anegen;
end if;
end if;
end loop;
end loop;
end process;
mdiocomb : process(rstn, r, anegact, mdio) is
variable v : reg_type;
begin
v := r;
if anegact = '0' then
v.ctrl.restartaneg := '0';
end if;
case r.state is
when idle =>
mdio <= 'Z';
if to_X01(mdio) = '1' then
v.cnt := v.cnt + 1;
if v.cnt = 31 then
v.state := start_of_frame; v.cnt := 0;
end if;
else
v.cnt := 0;
end if;
when start_of_frame =>
if to_X01(mdio) = '0' then
v.state := start_of_frame2;
elsif to_X01(mdio) /= '1' then
v.state := idle;
end if;
when start_of_frame2 =>
if to_X01(mdio) = '1' then
v.state := op;
else
v.state := idle;
end if;
when op =>
v.cnt := v.cnt + 1;
v.op := r.op(0) & to_X01(mdio);
if r.cnt = 1 then
if (v.op = "01") or (v.op = "10") then
v.state := phyad; v.cnt := 0;
else
v.state := idle; v.cnt := 0;
end if;
end if;
when phyad =>
v.phyad := r.phyad(3 downto 0) & to_X01(mdio);
v.cnt := v.cnt + 1;
if r.cnt = 4 then
v.state := regad; v.cnt := 0;
end if;
when regad =>
v.regad := r.regad(3 downto 0) & to_X01(mdio);
v.cnt := v.cnt + 1;
if r.cnt = 4 then
v.cnt := 0;
if conv_integer(r.phyad) = address then
v.state := ta;
else
v.state := idle;
end if;
end if;
when ta =>
v.cnt := r.cnt + 1;
if r.cnt = 0 then
if (r.op = "01") and to_X01(mdio) /= '1' then
v.cnt := 0; v.state := idle;
end if;
else
if r.op = "10" then
mdio <= '0'; v.cnt := 0; v.state := rdata;
case r.regad is
when "00000" => --ctrl (basic)
v.regtmp := r.ctrl.reset & r.ctrl.loopback &
r.ctrl.speedsel(1) & r.ctrl.anegen & r.ctrl.powerdown &
r.ctrl.isolate & r.ctrl.restartaneg & r.ctrl.duplexmode &
r.ctrl.coltest & r.ctrl.speedsel(0) & "000000";
when "00001" => --statuc (basic)
v.regtmp := r.status.base100_t4 & r.status.base100_x_fd &
r.status.base100_x_hd & r.status.fd_10 & r.status.hd_10 &
r.status.base100_t2_fd & r.status.base100_t2_hd &
r.status.extstat & '0' & r.status.mfpreamblesup &
r.status.anegcmpt & r.status.remfault & r.status.anegability &
r.status.linkstat & r.status.jabdetect & r.status.extcap;
when "00010" => --PHY ID (extended)
if extended_regs = 1 then
v.regtmp := X"BBCD";
else
v.cnt := 0; v.state := idle;
end if;
when "00011" => --PHY ID (extended)
if extended_regs = 1 then
v.regtmp := X"9C83";
else
v.cnt := 0; v.state := idle;
end if;
when "00100" => --Auto-neg adv. (extended)
if extended_regs = 1 then
v.regtmp := r.anegadv.next_page & '0' & r.anegadv.remote_fault &
r.anegadv.tech_ability & r.anegadv.selector;
else
v.cnt := 0; v.state := idle;
end if;
when "00101" => --Auto-neg link partner ability (extended)
if extended_regs = 1 then
v.regtmp := r.aneglp.next_page & '0' & r.aneglp.remote_fault &
r.aneglp.tech_ability & r.aneglp.selector;
else
v.cnt := 0; v.state := idle;
end if;
when "00110" => --Auto-neg expansion (extended)
if extended_regs = 1 then
v.regtmp := "00000000000" & r.anegexp.par_detct_flt &
r.anegexp.lp_np_able & r.anegexp.np_able & r.anegexp.page_rx &
r.anegexp.lp_aneg_able;
else
v.cnt := 0; v.state := idle;
end if;
when "00111" => --Auto-neg next page (extended)
if extended_regs = 1 then
v.regtmp := r.anegnptx.next_page & '0' & r.anegnptx.message_page &
r.anegnptx.ack2 & r.anegnptx.toggle & r.anegnptx.message;
else
v.cnt := 0; v.state := idle;
end if;
when "01000" => --Auto-neg link partner received next page (extended)
if extended_regs = 1 then
v.regtmp := r.anegnplp.next_page & '0' & r.anegnplp.message_page &
r.anegnplp.ack2 & r.anegnplp.toggle & r.anegnplp.message;
else
v.cnt := 0; v.state := idle;
end if;
when "01001" => --Master-slave control (extended)
if extended_regs = 1 then
v.regtmp := r.mstslvctrl.tmode & r.mstslvctrl.manualcfgen &
r.mstslvctrl.cfgval & r.mstslvctrl.porttype &
r.mstslvctrl.base1000_t_fd & r.mstslvctrl.base1000_t_hd &
"00000000";
else
v.cnt := 0; v.state := idle;
end if;
when "01010" => --Master-slave status (extended)
if extended_regs = 1 then
v.regtmp := r.mstslvstat.cfgfault & r.mstslvstat.cfgres &
r.mstslvstat.locrxstate & r.mstslvstat.remrxstate &
r.mstslvstat.lpbase1000_t_fd & r.mstslvstat.lpbase1000_t_hd &
"00" & r.mstslvstat.idlerrcnt;
else
v.cnt := 0; v.state := idle;
end if;
when "01111" =>
if (base1000_x_fd = 1) or (base1000_x_hd = 1) or
(base1000_t_fd = 1) or (base1000_t_hd = 1) then
v.regtmp := r.extstatus.base1000_x_fd &
r.extstatus.base1000_x_hd &
r.extstatus.base1000_t_fd &
r.extstatus.base1000_t_hd & X"000";
else
v.regtmp := (others => '0');
end if;
when others =>
--PHY shall not drive MDIO when unimplemented registers
--are accessed
v.cnt := 0; v.state := idle;
v.regtmp := (others => '0');
end case;
if r.ctrl.reset = '1' then
if r.regad = "00000" then
v.regtmp := X"8000";
else
v.regtmp := X"0000";
end if;
end if;
else
if to_X01(mdio) /= '0'then
v.cnt := 0; v.state := idle;
else
v.cnt := 0; v.state := wdata;
end if;
end if;
end if;
when rdata =>
v.cnt := r.cnt + 1;
mdio <= r.regtmp(15-r.cnt);
if r.cnt = 15 then
v.state := idle; v.cnt := 0;
end if;
when wdata =>
v.cnt := r.cnt + 1;
v.regtmp := r.regtmp(14 downto 0) & to_X01(mdio);
if r.cnt = 15 then
v.state := idle; v.cnt := 0;
if r.ctrl.reset = '0' then
case r.regad is
when "00000" =>
v.ctrl.reset := v.regtmp(15);
v.ctrl.loopback := v.regtmp(14);
v.ctrl.speedsel(1) := v.regtmp(13);
v.ctrl.anegen := v.regtmp(12);
v.ctrl.powerdown := v.regtmp(11);
v.ctrl.isolate := v.regtmp(10);
v.ctrl.restartaneg := v.regtmp(9);
v.ctrl.duplexmode := v.regtmp(8);
v.ctrl.coltest := v.regtmp(7);
v.ctrl.speedsel(0) := v.regtmp(6);
when "00100" =>
if extended_regs = 1 then
v.anegadv.remote_fault := r.regtmp(13);
v.anegadv.tech_ability := r.regtmp(12 downto 5);
v.anegadv.selector := r.regtmp(4 downto 0);
end if;
when "00111" =>
if extended_regs = 1 then
v.anegnptx.next_page := r.regtmp(15);
v.anegnptx.message_page := r.regtmp(13);
v.anegnptx.ack2 := r.regtmp(12);
v.anegnptx.message := r.regtmp(10 downto 0);
end if;
when "01001" =>
if extended_regs = 1 then
v.mstslvctrl.tmode := r.regtmp(15 downto 13);
v.mstslvctrl.manualcfgen := r.regtmp(12);
v.mstslvctrl.cfgval := r.regtmp(11);
v.mstslvctrl.porttype := r.regtmp(10);
v.mstslvctrl.base1000_t_fd := r.regtmp(9);
v.mstslvctrl.base1000_t_hd := r.regtmp(8);
end if;
when others => --no writable bits for other regs
null;
end case;
end if;
end if;
when others =>
null;
end case;
if r.rstcnt > 19 then
v.ctrl.reset := '0'; v.rstcnt := 0;
else
v.rstcnt := r.rstcnt + 1;
end if;
if (v.ctrl.reset and not r.ctrl.reset) = '1' then
v.rstcnt := 0;
end if;
if r.ctrl.anegen = '1' then
if r.anegcnt < 10 then
v.anegcnt := r.anegcnt + 1;
else
v.status.anegcmpt := '1';
if (base1000_x_fd = 1) or (base1000_x_hd = 1) or
(r.mstslvctrl.base1000_t_fd = '1') or
(r.mstslvctrl.base1000_t_hd = '1') then
v.ctrl.speedsel(1 downto 0) := "01";
elsif (r.anegadv.tech_ability(4) = '1') or
(r.anegadv.tech_ability(3) = '1') or
(r.anegadv.tech_ability(2) = '1') or
(base100_t2_fd = 1) or (base100_t2_hd = 1) then
v.ctrl.speedsel(1 downto 0) := "10";
else
v.ctrl.speedsel(1 downto 0) := "00";
end if;
if ((base1000_x_fd = 1) or (r.mstslvctrl.base1000_t_fd = '1')) or
(((base100_t2_fd = 1) or (r.anegadv.tech_ability(3) = '1')) and
(r.mstslvctrl.base1000_t_hd = '0') and (base1000_x_hd = 0)) or
((r.anegadv.tech_ability(1) = '1') and (base100_t2_hd = 0) and
(r.anegadv.tech_ability(4) = '0') and
(r.anegadv.tech_ability(2) = '0')) then
v.ctrl.duplexmode := '1';
else
v.ctrl.duplexmode := '0';
end if;
end if;
end if;
if r.ctrl.restartaneg = '1' then
v.anegcnt := 0;
v.status.anegcmpt := '0';
v.ctrl.restartaneg := '0';
end if;
rin <= v;
end process;
reg : process(rstn, mdc) is
begin
if rising_edge(mdc) then
r <= rin;
end if;
-- -- RESET DELAY
-- if rstd = '1' then
-- r.ctrl.reset <= '1';
-- else
-- r.ctrl.reset <= '0';
-- end if;
-- RESET
if (r.ctrl.reset or not rstn) = '1' then
r.ctrl.loopback <= '1'; r.anegcnt <= 0;
if (base1000_x_hd = 1) or (base1000_x_fd = 1) or (base1000_t_hd = 1) or
(base1000_t_fd = 1) then
r.ctrl.speedsel <= "01";
elsif (base100_x_hd = 1) or (base100_t2_hd = 1) or (base100_x_fd = 1) or
(base100_t2_fd = 1) or (base100_t4 = 1) then
r.ctrl.speedsel <= "10";
else
r.ctrl.speedsel <= "00";
end if;
r.ctrl.anegen <= conv_std_logic(aneg = 1);
r.ctrl.powerdown <= '0';
r.ctrl.isolate <= '0';
r.ctrl.restartaneg <= '0';
if (base100_x_hd = 0) and (hd_10 = 0) and (base100_t2_hd = 0) and
(base1000_x_hd = 0) and (base1000_t_hd = 0) then
r.ctrl.duplexmode <= '1';
else
r.ctrl.duplexmode <= '0';
end if;
r.ctrl.coltest <= '0';
r.status.base100_t4 <= conv_std_logic(base100_t4 = 1);
r.status.base100_x_fd <= conv_std_logic(base100_x_fd = 1);
r.status.base100_x_hd <= conv_std_logic(base100_x_hd = 1);
r.status.fd_10 <= conv_std_logic(fd_10 = 1);
r.status.hd_10 <= conv_std_logic(hd_10 = 1);
r.status.base100_t2_fd <= conv_std_logic(base100_t2_fd = 1);
r.status.base100_t2_hd <= conv_std_logic(base100_t2_hd = 1);
r.status.extstat <= conv_std_logic((base1000_x_fd = 1) or
(base1000_x_hd = 1) or
(base1000_t_fd = 1) or
(base1000_t_hd = 1));
r.status.mfpreamblesup <= '0';
r.status.anegcmpt <= '0';
r.status.remfault <= '0';
r.status.anegability <= conv_std_logic(aneg = 1);
r.status.linkstat <= '0';
r.status.jabdetect <= '0';
r.status.extcap <= conv_std_logic(extended_regs = 1);
r.anegadv.next_page <= '0';
r.anegadv.remote_fault <= '0';
r.anegadv.tech_ability <= "000" & conv_std_logic(base100_t4 = 1) &
conv_std_logic(base100_x_fd = 1) & conv_std_logic(base100_x_hd = 1) &
conv_std_logic(fd_10 = 1) & conv_std_logic(hd_10 = 1);
r.anegadv.selector <= "00001";
r.aneglp.next_page <= '0';
r.aneglp.remote_fault <= '0';
r.aneglp.tech_ability <= "000" & conv_std_logic(base100_t4 = 1) &
conv_std_logic(base100_x_fd = 1) & conv_std_logic(base100_x_hd = 1) &
conv_std_logic(fd_10 = 1) & conv_std_logic(hd_10 = 1);
r.aneglp.selector <= "00001";
r.anegexp.par_detct_flt <= '0';
r.anegexp.lp_np_able <= '0';
r.anegexp.np_able <= '0';
r.anegexp.page_rx <= '0';
r.anegexp.lp_aneg_able <= '0';
r.anegnptx.next_page <= '0';
r.anegnptx.message_page <= '1';
r.anegnptx.ack2 <= '0';
r.anegnptx.toggle <= '0';
r.anegnptx.message <= "00000000001";
r.anegnplp.next_page <= '0';
r.anegnplp.message_page <= '1';
r.anegnplp.ack2 <= '0';
r.anegnplp.toggle <= '0';
r.anegnplp.message <= "00000000001";
r.mstslvctrl.tmode <= (others => '0');
r.mstslvctrl.manualcfgen <= '0';
r.mstslvctrl.cfgval <= '0';
r.mstslvctrl.porttype <= '0';
r.mstslvctrl.base1000_t_fd <= conv_std_logic(base1000_t_fd = 1);
r.mstslvctrl.base1000_t_hd <= conv_std_logic(base1000_t_fd = 1);
r.mstslvstat.cfgfault <= '0';
r.mstslvstat.cfgres <= '1';
r.mstslvstat.locrxstate <= '1';
r.mstslvstat.remrxstate <= '1';
r.mstslvstat.lpbase1000_t_fd <= conv_std_logic(base1000_t_fd = 1);
r.mstslvstat.lpbase1000_t_hd <= conv_std_logic(base1000_t_fd = 1);
r.mstslvstat.idlerrcnt <= (others => '0');
r.extstatus.base1000_x_fd <= conv_std_logic(base1000_x_fd = 1);
r.extstatus.base1000_x_hd <= conv_std_logic(base1000_x_hd = 1);
r.extstatus.base1000_t_fd <= conv_std_logic(base1000_t_fd = 1);
r.extstatus.base1000_t_hd <= conv_std_logic(base1000_t_hd = 1);
end if;
if rstn = '0' then
r.cnt <= 0; r.state <= idle; r.rstcnt <= 0;
r.ctrl.reset <= '1';
end if;
end process;
loopback_sel : process(r.ctrl.loopback, int_clk, gtx_clk, r.ctrl.speedsel, txd, tx_en) is
begin
if r.ctrl.loopback = '1' then
if rmii = 0 then
rx_col <= '0'; rx_crs <= tx_en; rx_dv <= tx_en; rx_er <= tx_er;
rxd <= txd;
if r.ctrl.speedsel /= "01" then
rx_clk <= int_clk; tx_clk <= int_clk;
else
rx_clk <= gtx_clk; tx_clk <= clkslow;
end if;
else
rx_dv <= '1'; rx_er <= '1'; --unused should not affect anything
rx_col <= '0'; rx_crs <= tx_en;
if tx_en = '0' then
rxd(1 downto 0) <= "00";
else
rxd(1 downto 0) <= txd(1 downto 0);
end if;
if rgmii = 1 then
if (gtx_clk = '1' and tx_en = '0') then
rxd(3 downto 0) <= r.ctrl.duplexmode & r.ctrl.speedsel & r.status.linkstat;
end if;
end if;
rx_clk <= '0'; tx_clk <= '0';
end if;
else
rx_col <= '0'; rx_crs <= '0'; rx_dv <= '0'; rx_er <= '0';
rxd <= (others => '0');
if rgmii = 1 then
if (gtx_clk = '1') then
rxd(3 downto 0) <= r.ctrl.duplexmode & r.ctrl.speedsel & r.status.linkstat;
end if;
end if;
if rmii = 0 then
if r.ctrl.speedsel /= "01" then
rx_clk <= int_clk; tx_clk <= int_clk after 3 ns;
else
rx_clk <= gtx_clk; tx_clk <= clkslow;
end if;
else
rx_clk <= int_clk; tx_clk <= int_clk after 3 ns;
end if;
end if;
end process;
end;
-- pragma translate_on
| gpl-3.0 | 395fe593a543f106fdd9397ecb522214 | 0.492616 | 3.385249 | false | false | false | false |
freecores/cryptopan_core | rtl/sbox.vhd | 1 | 12,595 | --
-- This file is part of the Crypto-PAn core.
--
-- Copyright (c) 2007 The University of Waikato, Hamilton, New Zealand.
-- Authors: Anthony Blake ([email protected])
--
-- All rights reserved.
--
-- This code has been developed by the University of Waikato WAND
-- research group. For further information please see http://www.wand.net.nz/
--
-- This source file is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This source is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with libtrace; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--
library ieee;
use ieee.std_logic_1164.all;
use work.cryptopan.all;
entity sbox is
port (
clk : in std_logic;
reset : in std_logic;
addra : in std_logic_vector(7 downto 0);
douta : out std_logic_vector(7 downto 0));
end sbox;
architecture rtl of sbox is
signal data : std_logic_vector(7 downto 0);
attribute syn_romstyle : string;
attribute syn_romstyle of data : signal is "logic";
begin
CLKLOGIC : process (clk, reset)
begin
if reset = '1' then
douta <= (others => '0');
elsif clk'event and clk = '1' then
douta <= data;
end if;
end process CLKLOGIC;
DATALOGIC : process (addra)
begin
case addra is
when "00000000" => data <= X"63";
when "00000001" => data <= X"7C";
when "00000010" => data <= X"77";
when "00000011" => data <= X"7B";
when "00000100" => data <= X"F2";
when "00000101" => data <= X"6B";
when "00000110" => data <= X"6F";
when "00000111" => data <= X"C5";
when "00001000" => data <= X"30";
when "00001001" => data <= X"01";
when "00001010" => data <= X"67";
when "00001011" => data <= X"2B";
when "00001100" => data <= X"FE";
when "00001101" => data <= X"D7";
when "00001110" => data <= X"AB";
when "00001111" => data <= X"76";
when "00010000" => data <= X"CA";
when "00010001" => data <= X"82";
when "00010010" => data <= X"C9";
when "00010011" => data <= X"7D";
when "00010100" => data <= X"FA";
when "00010101" => data <= X"59";
when "00010110" => data <= X"47";
when "00010111" => data <= X"F0";
when "00011000" => data <= X"AD";
when "00011001" => data <= X"D4";
when "00011010" => data <= X"A2";
when "00011011" => data <= X"AF";
when "00011100" => data <= X"9C";
when "00011101" => data <= X"A4";
when "00011110" => data <= X"72";
when "00011111" => data <= X"C0";
when "00100000" => data <= X"B7";
when "00100001" => data <= X"FD";
when "00100010" => data <= X"93";
when "00100011" => data <= X"26";
when "00100100" => data <= X"36";
when "00100101" => data <= X"3F";
when "00100110" => data <= X"F7";
when "00100111" => data <= X"CC";
when "00101000" => data <= X"34";
when "00101001" => data <= X"A5";
when "00101010" => data <= X"E5";
when "00101011" => data <= X"F1";
when "00101100" => data <= X"71";
when "00101101" => data <= X"D8";
when "00101110" => data <= X"31";
when "00101111" => data <= X"15";
when "00110000" => data <= X"04";
when "00110001" => data <= X"C7";
when "00110010" => data <= X"23";
when "00110011" => data <= X"C3";
when "00110100" => data <= X"18";
when "00110101" => data <= X"96";
when "00110110" => data <= X"05";
when "00110111" => data <= X"9A";
when "00111000" => data <= X"07";
when "00111001" => data <= X"12";
when "00111010" => data <= X"80";
when "00111011" => data <= X"E2";
when "00111100" => data <= X"EB";
when "00111101" => data <= X"27";
when "00111110" => data <= X"B2";
when "00111111" => data <= X"75";
when "01000000" => data <= X"09";
when "01000001" => data <= X"83";
when "01000010" => data <= X"2C";
when "01000011" => data <= X"1A";
when "01000100" => data <= X"1B";
when "01000101" => data <= X"6E";
when "01000110" => data <= X"5A";
when "01000111" => data <= X"A0";
when "01001000" => data <= X"52";
when "01001001" => data <= X"3B";
when "01001010" => data <= X"D6";
when "01001011" => data <= X"B3";
when "01001100" => data <= X"29";
when "01001101" => data <= X"E3";
when "01001110" => data <= X"2F";
when "01001111" => data <= X"84";
when "01010000" => data <= X"53";
when "01010001" => data <= X"D1";
when "01010010" => data <= X"00";
when "01010011" => data <= X"ED";
when "01010100" => data <= X"20";
when "01010101" => data <= X"FC";
when "01010110" => data <= X"B1";
when "01010111" => data <= X"5B";
when "01011000" => data <= X"6A";
when "01011001" => data <= X"CB";
when "01011010" => data <= X"BE";
when "01011011" => data <= X"39";
when "01011100" => data <= X"4A";
when "01011101" => data <= X"4C";
when "01011110" => data <= X"58";
when "01011111" => data <= X"CF";
when "01100000" => data <= X"D0";
when "01100001" => data <= X"EF";
when "01100010" => data <= X"AA";
when "01100011" => data <= X"FB";
when "01100100" => data <= X"43";
when "01100101" => data <= X"4D";
when "01100110" => data <= X"33";
when "01100111" => data <= X"85";
when "01101000" => data <= X"45";
when "01101001" => data <= X"F9";
when "01101010" => data <= X"02";
when "01101011" => data <= X"7F";
when "01101100" => data <= X"50";
when "01101101" => data <= X"3C";
when "01101110" => data <= X"9F";
when "01101111" => data <= X"A8";
when "01110000" => data <= X"51";
when "01110001" => data <= X"A3";
when "01110010" => data <= X"40";
when "01110011" => data <= X"8F";
when "01110100" => data <= X"92";
when "01110101" => data <= X"9D";
when "01110110" => data <= X"38";
when "01110111" => data <= X"F5";
when "01111000" => data <= X"BC";
when "01111001" => data <= X"B6";
when "01111010" => data <= X"DA";
when "01111011" => data <= X"21";
when "01111100" => data <= X"10";
when "01111101" => data <= X"FF";
when "01111110" => data <= X"F3";
when "01111111" => data <= X"D2";
when "10000000" => data <= X"CD";
when "10000001" => data <= X"0C";
when "10000010" => data <= X"13";
when "10000011" => data <= X"EC";
when "10000100" => data <= X"5F";
when "10000101" => data <= X"97";
when "10000110" => data <= X"44";
when "10000111" => data <= X"17";
when "10001000" => data <= X"C4";
when "10001001" => data <= X"A7";
when "10001010" => data <= X"7E";
when "10001011" => data <= X"3D";
when "10001100" => data <= X"64";
when "10001101" => data <= X"5D";
when "10001110" => data <= X"19";
when "10001111" => data <= X"73";
when "10010000" => data <= X"60";
when "10010001" => data <= X"81";
when "10010010" => data <= X"4F";
when "10010011" => data <= X"DC";
when "10010100" => data <= X"22";
when "10010101" => data <= X"2A";
when "10010110" => data <= X"90";
when "10010111" => data <= X"88";
when "10011000" => data <= X"46";
when "10011001" => data <= X"EE";
when "10011010" => data <= X"B8";
when "10011011" => data <= X"14";
when "10011100" => data <= X"DE";
when "10011101" => data <= X"5E";
when "10011110" => data <= X"0B";
when "10011111" => data <= X"DB";
when "10100000" => data <= X"E0";
when "10100001" => data <= X"32";
when "10100010" => data <= X"3A";
when "10100011" => data <= X"0A";
when "10100100" => data <= X"49";
when "10100101" => data <= X"06";
when "10100110" => data <= X"24";
when "10100111" => data <= X"5C";
when "10101000" => data <= X"C2";
when "10101001" => data <= X"D3";
when "10101010" => data <= X"AC";
when "10101011" => data <= X"62";
when "10101100" => data <= X"91";
when "10101101" => data <= X"95";
when "10101110" => data <= X"E4";
when "10101111" => data <= X"79";
when "10110000" => data <= X"E7";
when "10110001" => data <= X"C8";
when "10110010" => data <= X"37";
when "10110011" => data <= X"6D";
when "10110100" => data <= X"8D";
when "10110101" => data <= X"D5";
when "10110110" => data <= X"4E";
when "10110111" => data <= X"A9";
when "10111000" => data <= X"6C";
when "10111001" => data <= X"56";
when "10111010" => data <= X"F4";
when "10111011" => data <= X"EA";
when "10111100" => data <= X"65";
when "10111101" => data <= X"7A";
when "10111110" => data <= X"AE";
when "10111111" => data <= X"08";
when "11000000" => data <= X"BA";
when "11000001" => data <= X"78";
when "11000010" => data <= X"25";
when "11000011" => data <= X"2E";
when "11000100" => data <= X"1C";
when "11000101" => data <= X"A6";
when "11000110" => data <= X"B4";
when "11000111" => data <= X"C6";
when "11001000" => data <= X"E8";
when "11001001" => data <= X"DD";
when "11001010" => data <= X"74";
when "11001011" => data <= X"1F";
when "11001100" => data <= X"4B";
when "11001101" => data <= X"BD";
when "11001110" => data <= X"8B";
when "11001111" => data <= X"8A";
when "11010000" => data <= X"70";
when "11010001" => data <= X"3E";
when "11010010" => data <= X"B5";
when "11010011" => data <= X"66";
when "11010100" => data <= X"48";
when "11010101" => data <= X"03";
when "11010110" => data <= X"F6";
when "11010111" => data <= X"0E";
when "11011000" => data <= X"61";
when "11011001" => data <= X"35";
when "11011010" => data <= X"57";
when "11011011" => data <= X"B9";
when "11011100" => data <= X"86";
when "11011101" => data <= X"C1";
when "11011110" => data <= X"1D";
when "11011111" => data <= X"9E";
when "11100000" => data <= X"E1";
when "11100001" => data <= X"F8";
when "11100010" => data <= X"98";
when "11100011" => data <= X"11";
when "11100100" => data <= X"69";
when "11100101" => data <= X"D9";
when "11100110" => data <= X"8E";
when "11100111" => data <= X"94";
when "11101000" => data <= X"9B";
when "11101001" => data <= X"1E";
when "11101010" => data <= X"87";
when "11101011" => data <= X"E9";
when "11101100" => data <= X"CE";
when "11101101" => data <= X"55";
when "11101110" => data <= X"28";
when "11101111" => data <= X"DF";
when "11110000" => data <= X"8C";
when "11110001" => data <= X"A1";
when "11110010" => data <= X"89";
when "11110011" => data <= X"0D";
when "11110100" => data <= X"BF";
when "11110101" => data <= X"E6";
when "11110110" => data <= X"42";
when "11110111" => data <= X"68";
when "11111000" => data <= X"41";
when "11111001" => data <= X"99";
when "11111010" => data <= X"2D";
when "11111011" => data <= X"0F";
when "11111100" => data <= X"B0";
when "11111101" => data <= X"54";
when "11111110" => data <= X"BB";
when "11111111" => data <= X"16";
when others => null;
end case;
end process DATALOGIC;
end rtl;
| gpl-2.0 | 124e7ca0575246057772ee481c027cea | 0.48678 | 2.994532 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-gr-xc3s-1500/leon3mp.vhd | 1 | 38,722 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.can.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.spacewire.all;
use gaisler.grusb.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_ulogic;
clk : in std_ulogic; -- 50 MHz main clock
clk3 : in std_ulogic; -- 25 MHz ethernet clock
pllref : in std_ulogic;
errorn : out std_ulogic;
wdogn : out std_ulogic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_ulogic;
writen : out std_ulogic;
read : out std_ulogic;
iosn : out std_ulogic;
bexcn : in std_ulogic; -- DSU rx data
brdyn : in std_ulogic; -- DSU rx data
romsn : out std_logic_vector (1 downto 0);
sdclk : out std_ulogic;
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_ulogic; -- sdram write enable
sdrasn : out std_ulogic; -- sdram ras
sdcasn : out std_ulogic; -- sdram cas
sddqm : out std_logic_vector (3 downto 0); -- sdram dqm
dsuen : in std_ulogic;
dsubre : in std_ulogic;
dsuact : out std_ulogic;
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
ctsn1 : in std_ulogic; -- UART1 rx data
rtsn1 : out std_ulogic; -- UART1 rx data
txd2 : out std_ulogic; -- UART2 tx data
rxd2 : in std_ulogic; -- UART2 rx data
ctsn2 : in std_ulogic; -- UART1 rx data
rtsn2 : out std_ulogic; -- UART1 rx data
pio : inout std_logic_vector(17 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
emdint : in std_ulogic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
emdc : out std_ulogic;
ps2clk : inout std_logic_vector(1 downto 0);
ps2data : inout std_logic_vector(1 downto 0);
vid_clock : out std_ulogic;
vid_blankn : out std_ulogic;
vid_syncn : out std_ulogic;
vid_hsync : out std_ulogic;
vid_vsync : out std_ulogic;
vid_r : out std_logic_vector(7 downto 0);
vid_g : out std_logic_vector(7 downto 0);
vid_b : out std_logic_vector(7 downto 0);
spw_clk : in std_ulogic;
spw_rxdp : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxdn : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxsp : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxsn : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txdp : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txdn : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txsp : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txsn : out std_logic_vector(0 to CFG_SPW_NUM-1);
usb_clkout : in std_ulogic;
usb_d : inout std_logic_vector(15 downto 0);
usb_linestate : in std_logic_vector(1 downto 0);
usb_opmode : out std_logic_vector(1 downto 0);
usb_reset : out std_ulogic;
usb_rxactive : in std_ulogic;
usb_rxerror : in std_ulogic;
usb_rxvalid : in std_ulogic;
usb_suspend : out std_ulogic;
usb_termsel : out std_ulogic;
usb_txready : in std_ulogic;
usb_txvalid : out std_ulogic;
usb_validh : inout std_ulogic;
usb_xcvrsel : out std_ulogic;
usb_vbus : in std_ulogic
);
end;
architecture rtl of leon3mp is
attribute syn_netlist_hierarchy : boolean;
attribute syn_netlist_hierarchy of rtl : architecture is false;
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := CFG_NCPU+CFG_AHB_UART+CFG_GRETH+
CFG_AHB_JTAG+CFG_SPW_NUM*CFG_SPW_EN+CFG_GRUSB_DCL+CFG_SVGA_ENABLE+
CFG_GRUSBDC;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal sdo2 : sdctrl_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, sdclkl : std_ulogic;
signal cgi, cgi2 : clkgen_in_type;
signal cgo, cgo2 : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal can_lrx, can_ltx : std_logic_vector(0 to 7);
signal lclk, rst, ndsuact, wdogl : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal ethclk : std_ulogic;
signal kbdi : ps2_in_type;
signal kbdo : ps2_out_type;
signal moui : ps2_in_type;
signal mouo : ps2_out_type;
signal vgao : apbvga_out_type;
constant BOARD_FREQ : integer := 50000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := CFG_CAN + CFG_GRUSBDC;
signal spwi : grspw_in_type_vector(0 to CFG_SPW_NUM-1);
signal spwo : grspw_out_type_vector(0 to CFG_SPW_NUM-1);
signal spw_rxclk : std_logic_vector(0 to CFG_SPW_NUM*CFG_SPW_PORTS);
signal dtmp : std_logic_vector(0 to CFG_SPW_NUM*CFG_SPW_PORTS-1);
signal stmp : std_logic_vector(0 to CFG_SPW_NUM*CFG_SPW_PORTS-1);
signal spw_rxtxclk : std_ulogic;
signal spw_rxclkn : std_ulogic;
signal spw_clkl : std_ulogic;
signal spw_clkln : std_ulogic;
signal stati : ahbstat_in_type;
signal uclk : std_ulogic;
signal usbi : grusb_in_type;
signal usbo : grusb_out_type;
constant SPW_LOOP_BACK : integer := 0;
signal dac_clk, video_clk, clk50 : std_logic; -- signals to vga_clkgen.
signal clk_sel : std_logic_vector(1 downto 0);
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of clk50 : signal is true;
attribute syn_preserve of clk50 : signal is true;
attribute keep of clk50 : signal is true;
attribute syn_keep of video_clk : signal is true;
attribute syn_preserve of video_clk : signal is true;
attribute keep of video_clk : signal is true;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
pllref_pad : clkpad generic map (tech => padtech) port map (pllref, cgi.pllref);
ethclk_pad : inpad generic map (tech => padtech) port map(clk3, ethclk);
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
CFG_CLK_NOFB, 0, 0, 0, BOARD_FREQ)
port map (lclk, lclk, clkm, open, open, sdclkl, open, cgi, cgo, open, clk50);
sdclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (sdclk, sdclkl);
resetn_pad : inpad generic map (tech => padtech) port map (resetn, rst);
rst0 : rstgen -- reset generator
port map (rst, clkm, cgo.clklock, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1, 0, 0,
CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, ndsuact);
ndsuact <= not dsuo.active;
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (rxd2, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (txd2, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "00";
brdyn_pad : inpad generic map (tech => padtech) port map (brdyn, memi.brdyn);
bexcn_pad : inpad generic map (tech => padtech) port map (bexcn, memi.bexcn);
mctrl0 : mctrl generic map (hindex => 0, pindex => 0,
paddr => 0, srbanks => 2, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN,
invclk => CFG_CLK_NOFB, sepbus => CFG_MCTRL_SEPBUS,
pageburst => CFG_MCTRL_PAGE)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
sdpads : if CFG_MCTRL_SDEN = 1 generate -- SDRAM controller
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo.sdwen);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo.casn);
sddqm_pad : outpadv generic map (width =>4, tech => padtech)
port map (sddqm, sdo.dqm(3 downto 0));
end generate;
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, sdo.sdcsn);
addr_pad : outpadv generic map (width => 28, tech => padtech)
port map (address, memo.address(27 downto 0));
rams_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramsn, memo.ramsn(4 downto 0));
roms_pad : outpadv generic map (width => 2, tech => padtech)
port map (romsn, memo.romsn(1 downto 0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
rwen_pad : outpadv generic map (width => 4, tech => padtech)
port map (rwen, memo.wrn);
roen_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramoen, memo.ramoen(4 downto 0));
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
read_pad : outpad generic map (tech => padtech)
port map (read, memo.read);
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
bdr : for i in 0 to 3 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0';
rxd1_pad : inpad generic map (tech => padtech) port map (rxd1, u1i.rxd);
txd1_pad : outpad generic map (tech => padtech) port map (txd1, u1o.txd);
cts1_pad : inpad generic map (tech => padtech) port map (ctsn1, u1i.ctsn);
rts1_pad : outpad generic map (tech => padtech) port map (rtsn1, u1o.rtsn);
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
ua2 : if CFG_UART2_ENABLE /= 0 generate
uart2 : apbuart -- UART 2
generic map (pindex => 9, paddr => 9, pirq => 3, fifosize => CFG_UART2_FIFO)
port map (rstn, clkm, apbi, apbo(9), u2i, u2o);
u2i.extclk <= '0';
rxd2_pad : inpad generic map (tech => padtech) port map (rxd2, u2i.rxd);
txd2_pad : outpad generic map (tech => padtech) port map (txd2, u2o.txd);
cts2_pad : inpad generic map (tech => padtech) port map (ctsn2, u2i.ctsn);
rts2_pad : outpad generic map (tech => padtech) port map (rtsn2, u2o.rtsn);
end generate;
noua1 : if CFG_UART2_ENABLE = 0 generate
apbo(9) <= apb_none; rtsn2 <= '0';
end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW, wdog => CFG_GPT_WDOGEN*CFG_GPT_WDOG)
port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
gpti <= gpti_dhalt_drive(dsuo.tstop);
end generate;
wden : if CFG_GPT_WDOGEN /= 0 generate
wdogl <= gpto.wdogn or not rstn;
wdogn_pad : odpad generic map (tech => padtech) port map (wdogn, wdogl);
end generate;
wddis : if CFG_GPT_WDOGEN = 0 generate
wdogn_pad : odpad generic map (tech => padtech) port map (wdogn, vcc(0));
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
kbd : if CFG_KBD_ENABLE /= 0 generate
ps21 : apbps2 generic map(pindex => 4, paddr => 4, pirq => 4)
port map(rstn, clkm, apbi, apbo(4), moui, mouo);
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
end generate;
nokbd : if CFG_KBD_ENABLE = 0 generate
apbo(4) <= apb_none; mouo <= ps2o_none;
apbo(5) <= apb_none; kbdo <= ps2o_none;
end generate;
kbdclk_pad : iopad generic map (tech => padtech)
port map (ps2clk(0),kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
kbdata_pad : iopad generic map (tech => padtech)
port map (ps2data(0), kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
mouclk_pad : iopad generic map (tech => padtech)
port map (ps2clk(1),mouo.ps2_clk_o, mouo.ps2_clk_oe, moui.ps2_clk_i);
mouata_pad : iopad generic map (tech => padtech)
port map (ps2data(1), mouo.ps2_data_o, mouo.ps2_data_oe, moui.ps2_data_i);
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, ethclk, apbi, apbo(6), vgao);
video_clock_pad : outpad generic map ( tech => padtech)
port map (vid_clock, video_clk);
video_clk <= not ethclk;
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
clk0 => 40000, clk1 => 1000000000/((BOARD_FREQ * CFG_CLKMUL)/CFG_CLKDIV),
clk2 => 20000, clk3 => 15385, burstlen => 6)
port map(rstn, clkm, video_clk, apbi, apbo(6), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), clk_sel);
vgaclk0 : entity work.vga_clkgen
port map (rstn, clk_sel, ethclk, clkm, clk50, video_clk);
dac_clk <= not video_clk;
video_clock_pad : outpad generic map ( tech => padtech)
port map (vid_clock, dac_clk);
end generate;
novga : if (CFG_VGA_ENABLE = 0 and CFG_SVGA_ENABLE = 0) generate
apbo(6) <= apb_none; vgao <= vgao_none;
video_clk <= not clkm;
video_clock_pad : outpad generic map ( tech => padtech)
port map (vid_clock, video_clk);
end generate;
blank_pad : outpad generic map (tech => padtech)
port map (vid_blankn, vgao.blank);
comp_sync_pad : outpad generic map (tech => padtech)
port map (vid_syncn, vgao.comp_sync);
vert_sync_pad : outpad generic map (tech => padtech)
port map (vid_vsync, vgao.vsync);
horiz_sync_pad : outpad generic map (tech => padtech)
port map (vid_hsync, vgao.hsync);
video_out_r_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_r, vgao.video_out_r);
video_out_g_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_g, vgao.video_out_g);
video_out_b_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_b, vgao.video_out_b);
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 8, paddr => 8, imask => CFG_GRGPIO_IMASK, nbits => 18)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(8),
gpioi => gpioi, gpioo => gpioo);
p0 : if (CFG_CAN = 0) or (CFG_CAN_NUM = 1) generate
pio_pads : for i in 1 to 2 generate
pio_pad : iopad generic map (tech => padtech)
port map (pio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
p1 : if (CFG_CAN = 0) generate
pio_pads : for i in 4 to 5 generate
pio_pad : iopad generic map (tech => padtech)
port map (pio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
pio_pad0 : iopad generic map (tech => padtech)
port map (pio(0), gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
pio_pad1 : iopad generic map (tech => padtech)
port map (pio(3), gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
pio_pads : for i in 6 to 17 generate
pio_pad : iopad generic map (tech => padtech)
port map (pio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
stati <= ahbstat_in_none;
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 1,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 13, paddr => 13, pirq => 6, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, enable_mdint => 1,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
apbi => apbi, apbo => apbo(13), ethi => ethi, etho => etho);
end generate;
ethpads : if (CFG_GRETH = 1) generate -- eth pads
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
emdint_pad : inpad generic map (tech => padtech)
port map (emdint, ethi.mdint);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- Multi-core CAN ---------------------------------------------------
-----------------------------------------------------------------------
can0 : if CFG_CAN = 1 generate
can0 : can_mc generic map (slvndx => 4, ioaddr => CFG_CANIO,
iomask => 16#FF0#, irq => CFG_CANIRQ, memtech => memtech,
ncores => CFG_CAN_NUM, sepirq => CFG_CANSEPIRQ)
port map (rstn, clkm, ahbsi, ahbso(4), can_lrx, can_ltx );
can_tx_pad1 : iopad generic map (tech => padtech)
port map (pio(5), can_ltx(0), gnd(0), gpioi.din(5));
can_rx_pad1 : iopad generic map (tech => padtech)
port map (pio(4), gnd(0), vcc(0), can_lrx(0));
canpas : if CFG_CAN_NUM = 2 generate
can_tx_pad2 : iopad generic map (tech => padtech)
port map (pio(2), can_ltx(1), gnd(0), gpioi.din(2));
can_rx_pad2 : iopad generic map (tech => padtech)
port map (pio(1), gnd(0), vcc(0), can_lrx(1));
end generate;
end generate;
-- standby controlled by pio(3) and pio(0)
-----------------------------------------------------------------------
--- SPACEWIRE -------------------------------------------------------
-----------------------------------------------------------------------
spw : if CFG_SPW_EN > 0 generate
core0: if CFG_SPW_GRSPW = 1 generate
spw_clkl <= clkm;
spw_rxclkn <= not spw_rxtxclk;
end generate;
core1 : if CFG_SPW_GRSPW = 2 generate
cgi2.pllctrl <= "00"; cgi2.pllrst <= rstraw;
clkgen_spw_rx : clkgen -- clock generator
generic map (clktech, 12, 2, 0,
1, 0, 0, 0, 25000)
port map (ethclk, ethclk, spw_clkl, spw_clkln, open, open, open, cgi2, cgo2, open, open);
spw_rxclkn <= spw_clkln;
end generate;
spw_rxtxclk <= spw_clkl;
swloop : for i in 0 to CFG_SPW_NUM-1 generate
-- GRSPW2 PHY
spw2_input : if CFG_SPW_GRSPW = 2 generate
spw_inputloop: for j in 0 to CFG_SPW_PORTS-1 generate
spw_phy0 : grspw2_phy
generic map(
scantest => 0,
tech => fabtech,
input_type => CFG_SPW_INPUT,
rxclkbuftype => 2)
port map(
rstn => rstn,
rxclki => spw_rxtxclk,
rxclkin => spw_rxclkn,
nrxclki => spw_rxtxclk,
di => dtmp(i*CFG_SPW_PORTS+j),
si => stmp(i*CFG_SPW_PORTS+j),
do => spwi(i).d(j*2+1 downto j*2),
dov => spwi(i).dv(j*2+1 downto j*2),
dconnect => spwi(i).dconnect(j*2+1 downto j*2),
rxclko => spw_rxclk(i*CFG_SPW_PORTS+j));
end generate spw_inputloop;
oneport : if CFG_SPW_PORTS = 1 generate
spwi(i).d(3 downto 2) <= "00"; -- For second port
spwi(i).dv(3 downto 2) <= "00"; -- For second port
spwi(i).dconnect(3 downto 2) <= "00"; -- For second port
end generate;
spwi(i).nd <= (others => '0'); -- Only used in GRSPW
end generate spw2_input;
-- GRSPW PHY
spw1_input: if CFG_SPW_GRSPW = 1 generate
spw_inputloop: for j in 0 to CFG_SPW_PORTS-1 generate
spw_phy0 : grspw_phy
generic map(
tech => fabtech,
rxclkbuftype => 2,
scantest => 0)
port map(
rxrst => spwo(i).rxrst,
di => dtmp(i*CFG_SPW_PORTS+j),
si => stmp(i*CFG_SPW_PORTS+j),
rxclko => spw_rxclk(i*CFG_SPW_PORTS+j),
do => spwi(i).d(j),
ndo => spwi(i).nd(j*5+4 downto j*5),
dconnect => spwi(i).dconnect(j*2+1 downto j*2));
end generate spw_inputloop;
oneport : if CFG_SPW_PORTS = 1 generate
spwi(i).d(1) <= '0'; -- For second port
spwi(i).d(3 downto 2) <= "00"; -- For GRSPW2 second port
spwi(i).nd(9 downto 5) <= "00000"; -- For second port
spwi(i).dconnect(3 downto 2) <= "00"; -- For second port
end generate;
spwi(i).dv <= (others => '0'); -- Only used in GRSPW2
end generate spw1_input;
spwi(i).s(1 downto 0) <= "00"; -- Only used in PHY
sw0 : grspwm generic map(tech => memtech,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE+i,
sysfreq => CPU_FREQ, usegen => 1,
pindex => 10+i, paddr => 10+i, pirq => 10+i,
nsync => 1, rmap => CFG_SPW_RMAP, rxunaligned => CFG_SPW_RXUNAL,
rmapcrc => CFG_SPW_RMAPCRC, fifosize1 => CFG_SPW_AHBFIFO,
fifosize2 => CFG_SPW_RXFIFO, rxclkbuftype => 2, dmachan => CFG_SPW_DMACHAN,
rmapbufs => CFG_SPW_RMAPBUF, ft => CFG_SPW_FT, ports => CFG_SPW_PORTS,
spwcore => CFG_SPW_GRSPW, netlist => CFG_SPW_NETLIST,
rxtx_sameclk => CFG_SPW_RTSAME, input_type => CFG_SPW_INPUT,
output_type => CFG_SPW_OUTPUT)
port map(rstn, clkm, spw_rxclk(i*CFG_SPW_PORTS), spw_rxclk(i*CFG_SPW_PORTS+1),
spw_rxtxclk, spw_rxtxclk, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE+i),
apbi, apbo(10+i), spwi(i), spwo(i));
spwi(i).tickin <= '0'; spwi(i).rmapen <= '1';
spwi(i).clkdiv10 <= conv_std_logic_vector(CPU_FREQ/10000-1, 8) when CFG_SPW_GRSPW = 1
else conv_std_logic_vector((25*12/20)-1, 8);
spwi(i).dcrstval <= (others => '0');
spwi(i).timerrstval <= (others => '0');
swportloop1: for j in 0 to CFG_SPW_PORTS-1 generate
spwlb0 : if SPW_LOOP_BACK = 1 generate
dtmp(CFG_SPW_PORTS*i+j) <= spwo(i).d(j);
stmp(CFG_SPW_PORTS*i+j) <= spwo(i).s(j);
end generate;
nospwlb0 : if SPW_LOOP_BACK = 0 generate
spw_rxd_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxdp(CFG_SPW_PORTS*i+j), spw_rxdn(CFG_SPW_PORTS*i+j),
dtmp(CFG_SPW_PORTS*i+j));
spw_rxs_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxsp(CFG_SPW_PORTS*i+j), spw_rxsn(CFG_SPW_PORTS*i+j),
stmp(CFG_SPW_PORTS*i+j));
spw_txd_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txdp(CFG_SPW_PORTS*i+j), spw_txdn(CFG_SPW_PORTS*i+j),
spwo(i).d(j), gnd(0));
spw_txs_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txsp(CFG_SPW_PORTS*i+j), spw_txsn(CFG_SPW_PORTS*i+j),
spwo(i).s(j), gnd(0));
end generate;
end generate;
end generate;
end generate;
-------------------------------------------------------------------------------
--- USB -----------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Note that the GRUSBDC and GRUSB_DCL can not be instantiated at the same
-- time (board has only one USB transceiver), therefore they share AHB
-- master/slave indexes
-----------------------------------------------------------------------------
-- Shared pads
-----------------------------------------------------------------------------
usbpads: if (CFG_GRUSBDC + CFG_GRUSB_DCL) = 0 generate
usbo.oen <= '1'; usbo.reset <= '1';
end generate;
usb_clk_pad : clkpad generic map (tech => padtech, arch => 2)
port map (usb_clkout, uclk);
usb_d_pad: iopadv generic map(tech => padtech, width => 16, slew => 1)
port map (usb_d, usbo.dataout, usbo.oen, usbi.datain);
usb_txready_pad : inpad generic map (tech => padtech)
port map (usb_txready,usbi.txready);
usb_rxvalid_pad : inpad generic map (tech => padtech)
port map (usb_rxvalid,usbi.rxvalid);
usb_rxerror_pad : inpad generic map (tech => padtech)
port map (usb_rxerror,usbi.rxerror);
usb_rxactive_pad : inpad generic map (tech => padtech)
port map (usb_rxactive,usbi.rxactive);
usb_linestate_pad : inpadv generic map (tech => padtech, width => 2)
port map (usb_linestate,usbi.linestate);
usb_vbus_pad : inpad generic map (tech => padtech)
port map (usb_vbus, usbi.vbusvalid);
usb_reset_pad : outpad generic map (tech => padtech, slew => 1)
port map (usb_reset,usbo.reset);
usb_suspend_pad : outpad generic map (tech => padtech, slew => 1)
port map (usb_suspend,usbo.suspendm);
usb_termsel_pad : outpad generic map (tech => padtech, slew => 1)
port map (usb_termsel,usbo.termselect);
usb_xcvrsel_pad : outpad generic map (tech => padtech, slew => 1)
port map (usb_xcvrsel,usbo.xcvrselect(0));
usb_txvalid_pad : outpad generic map (tech => padtech, slew => 1)
port map (usb_txvalid,usbo.txvalid);
usb_opmode_pad : outpadv generic map (tech =>padtech ,width =>2, slew =>1)
port map (usb_opmode,usbo.opmode);
usb_validh_pad:iopad generic map(tech => padtech, slew => 1)
port map (usb_validh, usbo.txvalidh, usbo.oen, usbi.rxvalidh);
-----------------------------------------------------------------------------
-- USB 2.0 Device Controller
-----------------------------------------------------------------------------
usbdc0: if CFG_GRUSBDC = 1 generate
usbdc0: grusbdc
generic map(
hsindex => 5, hirq => 7, haddr => 16#004#, hmask => 16#FFC#,
hmindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+
CFG_SVGA_ENABLE+CFG_SPW_NUM*CFG_SPW_EN,
aiface => CFG_GRUSBDC_AIFACE, uiface => 0, dwidth => CFG_GRUSBDC_DW,
nepi => CFG_GRUSBDC_NEPI, nepo => CFG_GRUSBDC_NEPO,
i0 => CFG_GRUSBDC_I0, i1 => CFG_GRUSBDC_I1,
i2 => CFG_GRUSBDC_I2, i3 => CFG_GRUSBDC_I3,
i4 => CFG_GRUSBDC_I4, i5 => CFG_GRUSBDC_I5,
i6 => CFG_GRUSBDC_I6, i7 => CFG_GRUSBDC_I7,
i8 => CFG_GRUSBDC_I8, i9 => CFG_GRUSBDC_I9,
i10 => CFG_GRUSBDC_I10, i11 => CFG_GRUSBDC_I11,
i12 => CFG_GRUSBDC_I12, i13 => CFG_GRUSBDC_I13,
i14 => CFG_GRUSBDC_I14, i15 => CFG_GRUSBDC_I15,
o0 => CFG_GRUSBDC_O0, o1 => CFG_GRUSBDC_O1,
o2 => CFG_GRUSBDC_O2, o3 => CFG_GRUSBDC_O3,
o4 => CFG_GRUSBDC_O4, o5 => CFG_GRUSBDC_O5,
o6 => CFG_GRUSBDC_O6, o7 => CFG_GRUSBDC_O7,
o8 => CFG_GRUSBDC_O8, o9 => CFG_GRUSBDC_O9,
o10 => CFG_GRUSBDC_O10, o11 => CFG_GRUSBDC_O11,
o12 => CFG_GRUSBDC_O12, o13 => CFG_GRUSBDC_O13,
o14 => CFG_GRUSBDC_O14, o15 => CFG_GRUSBDC_O15,
memtech => memtech)
port map(
uclk => uclk,
usbi => usbi,
usbo => usbo,
hclk => clkm,
hrst => rstn,
ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+
CFG_SVGA_ENABLE+CFG_SPW_NUM*CFG_SPW_EN),
ahbsi => ahbsi,
ahbso => ahbso(5)
);
end generate usbdc0;
-----------------------------------------------------------------------------
-- USB DCL
-----------------------------------------------------------------------------
usb_dcl0: if CFG_GRUSB_DCL = 1 generate
usb_dcl0: grusb_dcl
generic map (
hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+
CFG_SVGA_ENABLE+CFG_SPW_NUM*CFG_SPW_EN,
memtech => memtech, uiface => 0, dwidth => CFG_GRUSB_DCL_DW)
port map (
uclk, usbi, usbo, clkm, rstn, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE+
CFG_SPW_NUM*CFG_SPW_EN));
end generate usb_dcl0;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 GR-XC3S-1500 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-3.0 | 2cd3c27cc9661996dec5ec622b529278 | 0.557073 | 3.494135 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-gr-pci-xc5v/testbench.vhd | 1 | 18,756 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
use gaisler.gr1553b_pkg.all;
use work.debug.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 21; -- ram address depth
srambanks : integer := 2; -- number of ram banks
rsedac : integer := CFG_MCTRLFT_EDAC/3 -- use RS encoding
);
port (
pci_rst : inout std_ulogic; -- PCI bus
pci_clk : in std_ulogic;
pci_gnt : in std_ulogic;
pci_idsel : in std_ulogic;
pci_lock : inout std_ulogic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_ulogic;
pci_irdy : inout std_ulogic;
pci_trdy : inout std_ulogic;
pci_devsel : inout std_ulogic;
pci_stop : inout std_ulogic;
pci_perr : inout std_ulogic;
pci_par : inout std_ulogic;
pci_req : inout std_ulogic;
pci_serr : inout std_ulogic;
pci_host : in std_ulogic := '1';
pci_66 : in std_ulogic := '0'
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(27 downto 0);
signal data : std_logic_vector(31 downto 0);
signal ramsn : std_logic_vector(4 downto 0);
signal ramoen : std_logic_vector(4 downto 0);
signal rwen : std_logic_vector(3 downto 0);
signal rwenx : std_logic_vector(3 downto 0);
signal romsn : std_logic_vector(1 downto 0);
signal iosn : std_ulogic;
signal oen : std_ulogic;
signal read : std_ulogic;
signal writen : std_ulogic;
signal brdyn : std_ulogic;
signal bexcn : std_ulogic;
signal wdogn : std_logic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal error : std_logic;
signal gpio : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal sdcke : std_logic_vector ( 1 downto 0); -- clk en
signal sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
signal sdwen : std_ulogic; -- write en
signal sdrasn : std_ulogic; -- row addr stb
signal sdcasn : std_ulogic; -- col addr stb
signal sddqm : std_logic_vector ( 7 downto 0); -- data i/o mask
signal sdclk : std_ulogic;
signal plllock : std_ulogic;
signal txd1, rxd1 : std_ulogic;
signal txd2, rxd2 : std_ulogic;
signal etx_clk, erx_clk, erx_dv, erx_er, erx_col : std_logic := '0';
signal eth_gtxclk, erx_crs, etx_en, etx_er : std_logic :='0';
signal eth_macclk : std_logic := '0';
signal erxd, etxd : std_logic_vector(7 downto 0) := (others => '0');
signal emdc, emdio : std_logic; --dummy signal for the mdc,mdio in the phy which is not used
signal emddis : std_logic;
signal epwrdwn : std_logic;
signal ereset : std_logic;
signal esleep : std_logic;
signal epause : std_logic;
signal emdintn : std_logic;
constant lresp : boolean := false;
signal sa : std_logic_vector(14 downto 0);
signal sd : std_logic_vector(63 downto 0);
signal pci_arb_req, pci_arb_gnt : std_logic_vector(0 to 3);
signal can_txd : std_logic_vector(0 to CFG_CAN_NUM-1);
signal can_rxd : std_logic_vector(0 to CFG_CAN_NUM-1);
signal can_stb : std_ulogic;
signal spw_clk : std_ulogic := '0';
signal spw_rxdp : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_rxdn : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_rxsp : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_rxsn : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_txdp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txdn : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txsp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txsn : std_logic_vector(0 to CFG_SPW_NUM-1);
signal usb_clkout : std_ulogic := '0';
signal usb_d : std_logic_vector(7 downto 0);
signal usb_resetn : std_ulogic;
signal usb_nxt : std_ulogic;
signal usb_stp : std_ulogic;
signal usb_dir : std_ulogic;
signal usb_id : std_ulogic;
signal usb_fault : std_ulogic;
signal usb_enablen : std_ulogic;
signal usb_csn : std_ulogic;
signal usb_faultn : std_ulogic;
signal usb_clock : std_ulogic;
signal usb_vbus : std_ulogic;
signal cb : std_logic_vector(7 downto 0);
signal busainen : std_logic_vector(0 to 0);
signal busainp : std_logic_vector(0 to 0);
signal busainn : std_logic_vector(0 to 0);
signal busaoutin : std_logic_vector(0 to 0);
signal busaoutp : std_logic_vector(0 to 0);
signal busaoutn : std_logic_vector(0 to 0);
signal busbinen : std_logic_vector(0 to 0);
signal busbinp : std_logic_vector(0 to 0);
signal busbinn : std_logic_vector(0 to 0);
signal busboutin : std_logic_vector(0 to 0);
signal busboutp : std_logic_vector(0 to 0);
signal busboutn : std_logic_vector(0 to 0);
signal milbusA,milbusB: wire1553;
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
spw_clk <= not spw_clk after 10 ns;
rst <= dsurst;
dsuen <= '1'; dsubre <= '0'; rxd1 <= '1';
can_rxd <= (others => 'H'); bexcn <= '1'; wdogn <= 'H';
gpio(2 downto 0) <= "LHL";
gpio(CFG_GRGPIO_WIDTH-1 downto 3) <= (others => 'H');
pci_arb_req <= "HHHH";
eth_macclk <= not eth_macclk after 4 ns;
emdintn <= 'H';
-- spacewire loop-back
spw_rxdp <= spw_txdp; spw_rxdn <= spw_txdn;
spw_rxsp <= spw_txsp; spw_rxsn <= spw_txsn;
d3 : entity work.leon3mp
generic map ( fabtech, memtech, padtech, clktech, disas, dbguart, pclow )
port map (rst, clk, sdclk, error, wdogn, address(27 downto 0), data, cb,
sa, sd, sdclk, sdcke, sdcsn, sdwen,
sdrasn, sdcasn, sddqm, dsutx, dsurx, dsuen, dsubre, dsuact, txd1, rxd1,
txd2, rxd2,
ramsn, ramoen, rwen, oen, writen, read, iosn, romsn, brdyn, bexcn, gpio,
emdio, eth_macclk, etx_clk, erx_clk, erxd, erx_dv, erx_er,
erx_col, erx_crs, emdintn, etxd, etx_en, etx_er, emdc,
pci_rst, pci_clk, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr, pci_par,
pci_req, pci_serr, pci_host, pci_66, pci_arb_req, pci_arb_gnt,
can_txd, can_rxd,
spw_clk, spw_rxdp, spw_rxdn, spw_rxsp, spw_rxsn, spw_txdp,
spw_txdn, spw_txsp, spw_txsn,
usb_clkout, usb_d, usb_nxt, usb_stp, usb_dir,
-- usb_id, usb_fault, usb_enablen, usb_csn, usb_faultn, usb_clock, usb_vbus,
usb_resetn,
busainen,busainp,busainn,busaoutin,busaoutp,busaoutn,
busbinen,busbinp,busbinn,busboutin,busboutp,busboutn
);
cbbits : if CFG_MCTRLFT_EDAC /= 0 generate
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
u2: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(1),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u3: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(1),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
cb0: ftmt48lc16m16a2 generic map (index => 8+rsedac*7, fname => sdramfile)
PORT MAP(
Dq => sd(47 downto 32), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(5 downto 4));
cb1: ftmt48lc16m16a2 generic map (index => 8+rsedac*7, fname => sdramfile)
PORT MAP(
Dq => sd(47 downto 32), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(1),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(5 downto 4));
end generate;
nocbbits : if CFG_MCTRLFT_EDAC = 0 generate
u0: mt48lc16m16a2 generic map (index => 64, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 80, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
u2: mt48lc16m16a2 generic map (index => 64, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(1),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u3: mt48lc16m16a2 generic map (index => 80, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(1),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
u5: mt48lc16m16a2 generic map (index => 48, fname => sdramfile)
PORT MAP(
Dq => sd(47 downto 32), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(5 downto 4));
u7: mt48lc16m16a2 generic map (index => 48, fname => sdramfile)
PORT MAP(
Dq => sd(47 downto 32), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(1),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(5 downto 4));
end generate;
u4: mt48lc16m16a2 generic map (index => 32, fname => sdramfile)
PORT MAP(
Dq => sd(63 downto 48), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(7 downto 6));
u6: mt48lc16m16a2 generic map (index => 32, fname => sdramfile)
PORT MAP(
Dq => sd(63 downto 48), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(7 downto 6));
prom0 : for i in 0 to (romwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => romdepth, fname => promfile)
port map (address(romdepth+1 downto 2), data(31-i*8 downto 24-i*8), romsn(0),
rwen(i), oen);
end generate;
sram0 : for i in 0 to (sramwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
port map (address(sramdepth+1 downto 2), data(31-i*8 downto 24-i*8), ramsn(0),
rwen(0), ramoen(0));
end generate;
sramcb0 : sramft generic map (index => 7, abits => sramdepth, fname => sramfile)
port map (address(sramdepth+1 downto 2), cb(7 downto 0), ramsn(0), rwen(0), ramoen(0));
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
p0: phy
generic map(address => 1)
port map(rst, emdio, etx_clk, erx_clk, erxd, erx_dv,
erx_er, erx_col, erx_crs, etxd, etx_en, etx_er, emdc, eth_macclk);
end generate;
usbtr: if (CFG_GRUSBHC = 1) generate
u0: ulpi
port map (usb_clkout, usb_d, usb_nxt, usb_stp, usb_dir, usb_resetn);
end generate usbtr;
error <= 'H'; -- ERROR pull-up
miltr: if (CFG_GR1553B_ENABLE = 1) generate
x: simtrans1553
port map (milbusA,milbusB,
busainen(0), busaoutin(0),
busaoutp(0), busaoutn(0), busainp(0), busainn(0),
busbinen(0), busboutin(0),
busboutp(0), busboutn(0), busbinp(0), busbinn(0));
end generate;
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, oen, writen, brdyn);
-- data <= buskeep(data), (others => 'H') after 250 ns;
data <= buskeep(data) after 5 ns;
-- sd <= buskeep(sd), (others => 'H') after 250 ns;
sd <= buskeep(sd) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
| gpl-3.0 | 73e90b593dc49d6b1180fb19daed1c1c | 0.573257 | 3.080309 | false | false | false | false |
yishinli/emc2 | src/hal/drivers/m5i20/hostmot5_src/threeph.vhd | 1 | 2,822 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity threeph is
Port (
clk: in STD_LOGIC;
ibus: in STD_LOGIC_VECTOR (15 downto 0);
obus: out STD_LOGIC_VECTOR (15 downto 0);
crload: in STD_LOGIC;
crread: in STD_LOGIC;
rateload: in STD_LOGIC;
rateread: in STD_LOGIC;
phaseouta: out STD_LOGIC;
phaseoutb: out STD_LOGIC;
phaseoutc: out STD_LOGIC
);
end threeph;
architecture behavioral of threeph is
signal prescale: STD_LOGIC_VECTOR (12 downto 0);
signal creg: STD_LOGIC_VECTOR (2 downto 0);
signal phaseacc: STD_LOGIC_VECTOR (16 downto 0);
alias phasemsb: std_logic is phaseacc(16);
signal phstate: STD_LOGIC_VECTOR (2 downto 0);
signal oldphasemsb: std_logic;
signal phaselatch: STD_LOGIC_VECTOR (15 downto 0);
signal phasea : std_logic;
signal phaseb : std_logic;
signal phasec : std_logic;
begin
athreephase: process (clk,
crread,
rateread)
begin
if clk'event and clk = '1' then
if creg(0) = '0' then
phstate <= "000";
end if;
phaseacc <= phaseacc + phaselatch;
oldphasemsb <= phasemsb;
if oldphasemsb /= phasemsb then
prescale <= prescale + 1;
if prescale = 0 then
phstate <= phstate +1;
if phstate = 5 then
phstate <= "000";
end if;
end if; -- prescale = 0
end if; -- old /= new
if rateload = '1' then
phaselatch <= ibus;
end if;
if crload = '1' then
creg <= ibus(2 downto 0);
end if;
end if; -- clk
if crread = '1' and rateread = '0' then
obus(2 downto 0) <= creg;
obus(15 downto 3) <= "0000000000000";
elsif rateread = '1' and crread = '0' then
obus <= phaselatch;
else
obus <= "ZZZZZZZZZZZZZZZZ";
end if;
case phstate is
when "000" =>
phasea <= '1';
phaseb <= '0';
phasec <= '1';
when "001" =>
phasea <= '1';
phaseb <= '0';
phasec <= '0';
when "010" =>
phasea <= '1';
phaseb <= '1';
phasec <= '0';
when "011" =>
phasea <= '0';
phaseb <= '1';
phasec <= '0';
when "100" =>
phasea <= '0';
phaseb <= '1';
phasec <= '1';
when "101" =>
phasea <= '0';
phaseb <= '0';
phasec <= '1';
when others => -- start
phasea <= '1';
phaseb <= '0';
phasec <= '1';
end case;
if creg(1) = '1' then
if creg(2) = '0' then
phaseouta <= phasea;
phaseoutb <= phaseb;
phaseoutc <= phasec;
else
phaseouta <= phaseb;
phaseoutb <= phasea;
phaseoutc <= phasec;
end if;
else
phaseouta <= 'Z';
phaseoutb <= 'Z';
phaseoutc <= 'Z';
end if;
end process;
end behavioral;
| lgpl-2.1 | e7aabccc8fa828bd52132294e9bc004f | 0.541814 | 2.888434 | false | false | false | false |
kdgwill/VHDL_Framer_Example | VHDL_Framer_Example/Example2/Ram.vhd | 1 | 7,117 | -- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: Ram.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 173 11/01/2011 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY Ram IS
PORT
(
address : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END Ram;
ARCHITECTURE SYN OF ram IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_port_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
clock0 : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren_a : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(31 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
intended_device_family => "Cyclone V",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 22,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
widthad_a => 5,
width_a => 32,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
data_a => data,
wren_a => wren,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "22"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "5"
-- Retrieval info: PRIVATE: WidthData NUMERIC "32"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "22"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 5 0 INPUT NODEFVAL "address[4..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-- Retrieval info: CONNECT: @address_a 0 0 5 0 address 0 0 5 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL Ram.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Ram.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Ram.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Ram.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Ram_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
| gpl-3.0 | ad540d7459f4bc0d525676100b1fc7f6 | 0.653646 | 3.443154 | false | false | false | false |
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