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EliasLuiz/TCC | Leon3/lib/gaisler/srmmu/mmutlbcam.vhd | 1 | 9,961 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mmutlbcam
-- File: mmutlbcam.vhd
-- Author: Konrad Eisele, Jiri Gaisler, Gaisler Research
-- Description: MMU TLB logic
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
use gaisler.libmmu.all;
entity mmutlbcam is
generic (
tlb_type : integer range 0 to 3 := 1;
mmupgsz : integer range 0 to 5 := 0
);
port (
rst : in std_logic;
clk : in std_logic;
tlbcami : in mmutlbcam_in_type;
tlbcamo : out mmutlbcam_out_type
);
end mmutlbcam;
architecture rtl of mmutlbcam is
constant M_TLB_FASTWRITE : integer range 0 to 3 := conv_integer(conv_std_logic_vector(tlb_type,2) and conv_std_logic_vector(2,2)); -- fast writebuffer
type tlbcam_rtype is record
btag : tlbcam_reg;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant ASYNC_RESET : boolean := GRLIB_CONFIG_ARRAY(grlib_async_reset_enable) = 1;
constant RRES : tlbcam_rtype := (btag => tlbcam_reg_none);
signal r,c : tlbcam_rtype;
begin
p0: process (rst, r, tlbcami)
variable v : tlbcam_rtype;
variable hm, hf : std_logic;
variable h_i1, h_i2, h_i3, h_c : std_logic;
variable h_l2, h_l3 : std_logic;
variable h_su_cnt : std_logic;
variable blvl : std_logic_vector(1 downto 0);
variable bet : std_logic_vector(1 downto 0);
variable bsu : std_logic;
variable blvl_decode : std_logic_vector(3 downto 0);
variable bet_decode : std_logic_vector(3 downto 0);
variable ref, modified : std_logic;
variable tlbcamo_pteout : std_logic_vector(31 downto 0);
variable tlbcamo_LVL : std_logic_vector(1 downto 0);
variable tlbcamo_NEEDSYNC : std_logic;
variable tlbcamo_WBNEEDSYNC : std_logic;
variable vaddr_r : std_logic_vector(31 downto 12);
variable vaddr_i : std_logic_vector(31 downto 12);
variable pagesize : integer range 0 to 3;
begin
v := r;
--#init
h_i1 := '0'; h_i2 := '0'; h_i3 := '0'; h_c := '0';
hm := '0'; pagesize := 0;
hf := r.btag.VALID;
blvl := r.btag.LVL;
bet := r.btag.ET;
bsu := r.btag.SU;
bet_decode := decode(bet);
blvl_decode := decode(blvl);
ref := r.btag.R;
modified := r.btag.M;
tlbcamo_pteout := (others => '0');
tlbcamo_lvl := (others => '0');
vaddr_r := r.btag.I1 & r.btag.I2 & r.btag.I3;
vaddr_i := tlbcami.tagin.I1 & tlbcami.tagin.I2 & tlbcami.tagin.I3;
-- prepare tag comparision
pagesize := MMU_getpagesize(mmupgsz,tlbcami.mmctrl);
case pagesize is
when 1 =>
-- 8k tag comparision [ 7 6 6 ]
if (vaddr_r(P8K_VA_I1_U downto P8K_VA_I1_D) = vaddr_i(P8K_VA_I1_U downto P8K_VA_I1_D)) then h_i1 := '1'; else h_i1 := '0'; end if;
if (vaddr_r(P8K_VA_I2_U downto P8K_VA_I2_D) = vaddr_i(P8K_VA_I2_U downto P8K_VA_I2_D)) then h_i2 := '1'; else h_i2 := '0'; end if;
if (vaddr_r(P8K_VA_I3_U downto P8K_VA_I3_D) = vaddr_i(P8K_VA_I3_U downto P8K_VA_I3_D)) then h_i3 := '1'; else h_i3 := '0'; end if;
if (r.btag.CTX = tlbcami.tagin.CTX) then h_c := '1'; else h_c := '0'; end if;
when 2 =>
-- 16k tag comparision [ 6 6 6 ]
if (vaddr_r(P16K_VA_I1_U downto P16K_VA_I1_D) = vaddr_i(P16K_VA_I1_U downto P16K_VA_I1_D)) then h_i1 := '1'; else h_i1 := '0'; end if;
if (vaddr_r(P16K_VA_I2_U downto P16K_VA_I2_D) = vaddr_i(P16K_VA_I2_U downto P16K_VA_I2_D)) then h_i2 := '1'; else h_i2 := '0'; end if;
if (vaddr_r(P16K_VA_I3_U downto P16K_VA_I3_D) = vaddr_i(P16K_VA_I3_U downto P16K_VA_I3_D)) then h_i3 := '1'; else h_i3 := '0'; end if;
if (r.btag.CTX = tlbcami.tagin.CTX) then h_c := '1'; else h_c := '0'; end if;
when 3 =>
-- 32k tag comparision [ 4 7 6 ]
if (vaddr_r(P32K_VA_I1_U downto P32K_VA_I1_D) = vaddr_i(P32K_VA_I1_U downto P32K_VA_I1_D)) then h_i1 := '1'; else h_i1 := '0'; end if;
if (vaddr_r(P32K_VA_I2_U downto P32K_VA_I2_D) = vaddr_i(P32K_VA_I2_U downto P32K_VA_I2_D)) then h_i2 := '1'; else h_i2 := '0'; end if;
if (vaddr_r(P32K_VA_I3_U downto P32K_VA_I3_D) = vaddr_i(P32K_VA_I3_U downto P32K_VA_I3_D)) then h_i3 := '1'; else h_i3 := '0'; end if;
if (r.btag.CTX = tlbcami.tagin.CTX) then h_c := '1'; else h_c := '0'; end if;
when others => -- standard 4k tag comparision [ 8 6 6 ]
if (r.btag.I1 = tlbcami.tagin.I1) then h_i1 := '1'; else h_i1 := '0'; end if;
if (r.btag.I2 = tlbcami.tagin.I2) then h_i2 := '1'; else h_i2 := '0'; end if;
if (r.btag.I3 = tlbcami.tagin.I3) then h_i3 := '1'; else h_i3 := '0'; end if;
if (r.btag.CTX = tlbcami.tagin.CTX) then h_c := '1'; else h_c := '0'; end if;
end case;
-- #level 2 hit (segment)
h_l2 := h_i1 and h_i2 ;
-- #level 3 hit (page)
h_l3 := h_i1 and h_i2 and h_i3;
-- # context + su
h_su_cnt := h_c or bsu;
--# translation (match) op
case blvl is
when LVL_PAGE => hm := h_l3 and h_c and r.btag.VALID;
when LVL_SEGMENT => hm := h_l2 and h_c and r.btag.VALID;
when LVL_REGION => hm := h_i1 and h_c and r.btag.VALID;
when LVL_CTX => hm := h_c and r.btag.VALID;
when others => hm := 'X';
end case;
--# translation: update ref/mod bit
tlbcamo_NEEDSYNC := '0';
if (tlbcami.trans_op and hm ) = '1' then
v.btag.R := '1';
v.btag.M := r.btag.M or tlbcami.tagin.M;
tlbcamo_NEEDSYNC := (not r.btag.R) or (tlbcami.tagin.M and (not r.btag.M)); -- cam: ref/modified changed, write back synchronously
end if;
tlbcamo_WBNEEDSYNC := '0';
if ( hm ) = '1' then
tlbcamo_WBNEEDSYNC := (not r.btag.R) or (tlbcami.tagin.M and (not r.btag.M)); -- cam: ref/modified changed, write back synchronously
end if;
--# flush operation
-- tlbcam only stores PTEs, tlb does not store PTDs
case tlbcami.tagin.TYP is
when FPTY_PAGE => -- page
hf := hf and h_su_cnt and h_l3 and (blvl_decode(0)); -- only level 3 (page)
when FPTY_SEGMENT => -- segment
hf := hf and h_su_cnt and h_l2 and (blvl_decode(0) or blvl_decode(1)); -- only level 2+3 (segment,page)
when FPTY_REGION => -- region
hf := hf and h_su_cnt and h_i1 and (not blvl_decode(3)); -- only level 1+2+3 (region,segment,page)
when FPTY_CTX => -- context
hf := hf and (h_c and (not bsu));
when FPTY_N => -- entire
when others =>
hf := '0';
end case;
--# flush: invalidate on flush hit
--if (tlbcami.flush_op and hf ) = '1' then
if (tlbcami.flush_op ) = '1' then
v.btag.VALID := '0';
end if;
--# write op
if ( tlbcami.write_op = '1' ) then
v.btag := tlbcami.tagwrite;
end if;
--# reset
if ((not ASYNC_RESET) and (not RESET_ALL) and (rst = '0')) or (tlbcami.mmuen = '0') then
v.btag.VALID := RRES.btag.VALID;
end if;
tlbcamo_pteout(PTE_PPN_U downto PTE_PPN_D) := r.btag.PPN;
tlbcamo_pteout(PTE_C) := r.btag.C;
tlbcamo_pteout(PTE_M) := r.btag.M;
tlbcamo_pteout(PTE_R) := r.btag.R;
tlbcamo_pteout(PTE_ACC_U downto PTE_ACC_D) := r.btag.ACC;
tlbcamo_pteout(PT_ET_U downto PT_ET_D) := r.btag.ET;
tlbcamo_LVL(1 downto 0) := r.btag.LVL;
--# drive signals
tlbcamo.pteout <= tlbcamo_pteout;
tlbcamo.LVL <= tlbcamo_LVL;
--tlbcamo.hit <= (tlbcami.trans_op and hm) or (tlbcami.flush_op and hf);
tlbcamo.hit <= (hm) or (tlbcami.flush_op and hf);
tlbcamo.ctx <= r.btag.CTX; -- for diagnostic only
tlbcamo.valid <= r.btag.VALID; -- for diagnostic only
tlbcamo.vaddr <= r.btag.I1 & r.btag.I2 & r.btag.I3 & "000000000000"; -- for diagnostic only
tlbcamo.NEEDSYNC <= tlbcamo_NEEDSYNC;
tlbcamo.WBNEEDSYNC <= tlbcamo_WBNEEDSYNC;
c <= v;
end process p0;
syncrregs : if not ASYNC_RESET generate
p1: process (clk)
begin
if rising_edge(clk) then
r <= c;
if RESET_ALL and (rst = '0') then
r <= RRES;
end if;
end if;
end process p1;
end generate;
asyncrregs : if ASYNC_RESET generate
p1: process (clk, rst)
begin
if rst = '0' then
r <= RRES;
elsif rising_edge(clk) then
r <= c;
end if;
end process p1;
end generate;
end rtl;
| gpl-3.0 | a14af88dffc4f6749b4752f738e90896 | 0.561891 | 2.999398 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-gr-xc6s/config.vhd | 1 | 9,565 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := spartan6;
constant CFG_MEMTECH : integer := spartan6;
constant CFG_PADTECH : integer := spartan6;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := spartan6;
constant CFG_CLKMUL : integer := (2);
constant CFG_CLKDIV : integer := (2);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 1;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 4;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 2;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 4;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 2;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 1*2 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 4 + 64*0;
constant CFG_ATBSZ : integer := 4;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 16;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000000#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDR2SP : integer := 0;
constant CFG_DDR2SP_INIT : integer := 0;
constant CFG_DDR2SP_FREQ : integer := 100;
constant CFG_DDR2SP_TRFC : integer := 130;
constant CFG_DDR2SP_DATAWIDTH : integer := 64;
constant CFG_DDR2SP_FTEN : integer := 0;
constant CFG_DDR2SP_FTWIDTH : integer := 0;
constant CFG_DDR2SP_COL : integer := 9;
constant CFG_DDR2SP_SIZE : integer := 8;
constant CFG_DDR2SP_DELAY0 : integer := 0;
constant CFG_DDR2SP_DELAY1 : integer := 0;
constant CFG_DDR2SP_DELAY2 : integer := 0;
constant CFG_DDR2SP_DELAY3 : integer := 0;
constant CFG_DDR2SP_DELAY4 : integer := 0;
constant CFG_DDR2SP_DELAY5 : integer := 0;
constant CFG_DDR2SP_DELAY6 : integer := 0;
constant CFG_DDR2SP_DELAY7 : integer := 0;
constant CFG_DDR2SP_NOSYNC : integer := 0;
-- Xilinx MIG
constant CFG_MIG_DDR2 : integer := 1;
constant CFG_MIG_RANKS : integer := (1);
constant CFG_MIG_COLBITS : integer := (10);
constant CFG_MIG_ROWBITS : integer := (13);
constant CFG_MIG_BANKBITS: integer := (2);
constant CFG_MIG_HMASK : integer := 16#F00#;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 8;
constant CFG_GRETH_FT : integer := 0;
constant CFG_GRETH_EDCLFT : integer := 0;
-- CAN 2.0 interface
constant CFG_CAN : integer := 0;
constant CFG_CAN_NUM : integer := 1;
constant CFG_CANIO : integer := 16#0#;
constant CFG_CANIRQ : integer := 0;
constant CFG_CANSEPIRQ: integer := 0;
constant CFG_CAN_SYNCRST : integer := 0;
constant CFG_CANFT : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- UART 2
constant CFG_UART2_ENABLE : integer := 0;
constant CFG_UART2_FIFO : integer := 1;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- Spacewire interface
constant CFG_SPW_EN : integer := 0;
constant CFG_SPW_NUM : integer := 1;
constant CFG_SPW_AHBFIFO : integer := 4;
constant CFG_SPW_RXFIFO : integer := 16;
constant CFG_SPW_RMAP : integer := 0;
constant CFG_SPW_RMAPBUF : integer := 4;
constant CFG_SPW_RMAPCRC : integer := 0;
constant CFG_SPW_NETLIST : integer := 0;
constant CFG_SPW_FT : integer := 0;
constant CFG_SPW_GRSPW : integer := 2;
constant CFG_SPW_RXUNAL : integer := 0;
constant CFG_SPW_DMACHAN : integer := 1;
constant CFG_SPW_PORTS : integer := 1;
constant CFG_SPW_INPUT : integer := 2;
constant CFG_SPW_OUTPUT : integer := 0;
constant CFG_SPW_RTSAME : integer := 0;
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 1;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 1;
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 1;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#0B#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 0;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := (1);
constant CFG_SPIMCTRL_ASCALER : integer := (8);
constant CFG_SPIMCTRL_PWRUPCNT : integer := (0);
constant CFG_SPIMCTRL_OFFSET : integer := 16#0#;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 1;
constant CFG_SPICTRL_NUM : integer := (1);
constant CFG_SPICTRL_SLVS : integer := (1);
constant CFG_SPICTRL_FIFO : integer := (1);
constant CFG_SPICTRL_SLVREG : integer := 1;
constant CFG_SPICTRL_ODMODE : integer := 0;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 0;
constant CFG_SPICTRL_MAXWLEN : integer := (0);
constant CFG_SPICTRL_SYNCRAM : integer := 0;
constant CFG_SPICTRL_FT : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-3.0 | 24b8ac28a769b11e863d30ec816873ec | 0.65426 | 3.550483 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/inferred/fifo_inferred.vhd | 1 | 8,515 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: fifo_inferred.vhd
-- Authors: Pascal Trotta
-- Andrea Gianarro - Cobham Gaisler AB
-- Description: Behavioural fifo generators
------------------------------------------------------------------------------
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.">";
use ieee.std_logic_unsigned."<";
use techmap.gencomp.all;
library grlib;
use grlib.config.all;
use grlib.config_types.all;
use grlib.stdlib.all;
entity generic_fifo is
generic (
tech : integer := 0; -- target technology
abits : integer := 10; -- fifo address bits (actual fifo depth = 2**abits)
dbits : integer := 32; -- fifo data width
sepclk : integer := 1; -- 1 = asynchrounous read/write clocks, 0 = synchronous read/write clocks
pfull : integer := 100; -- almost full threshold (max 2**abits - 3)
pempty : integer := 10; -- almost empty threshold (min 2)
fwft : integer := 0 -- 1 = first word fall trough mode, 0 = standard mode
);
port (
rclk : in std_logic; -- read clock
rrstn : in std_logic; -- read clock domain synchronous reset
wrstn : in std_logic; -- write clock domain synchronous reset
renable : in std_logic; -- read enable
rfull : out std_logic; -- fifo full (synchronized in read clock domain)
rempty : out std_logic; -- fifo empty
aempty : out std_logic; -- fifo almost empty (depending on pempty threshold)
rusedw : out std_logic_vector(abits-1 downto 0); -- fifo used words (synchronized in read clock domain)
dataout : out std_logic_vector(dbits-1 downto 0); -- fifo data output
wclk : in std_logic; -- write clock
write : in std_logic; -- write enable
wfull : out std_logic; -- fifo full
afull : out std_logic; -- fifo almost full (depending on pfull threshold)
wempty : out std_logic; -- fifo empty (synchronized in write clock domain)
wusedw : out std_logic_vector(abits-1 downto 0); -- fifo used words (synchronized in write clock domain)
datain : in std_logic_vector(dbits-1 downto 0)); -- fifo data input
end;
architecture rtl_fifo of generic_fifo is
type wr_fifo_type is record
waddr : std_logic_vector(abits downto 0);
waddr_gray : std_logic_vector(abits downto 0);
full : std_logic;
end record;
type rd_fifo_type is record
raddr : std_logic_vector(abits downto 0);
raddr_gray : std_logic_vector(abits downto 0);
empty : std_logic;
end record;
signal wr_r, wr_rin : wr_fifo_type;
signal rd_r, rd_rin : rd_fifo_type;
signal wr_raddr_gray, rd_waddr_gray : std_logic_vector(abits downto 0);
begin
---------------------
-- write clock domain
---------------------
wr_comb: process(wr_r, write, wr_raddr_gray, wrstn, rd_r.raddr)
variable wr_v : wr_fifo_type;
variable v_wusedw : std_logic_vector(abits downto 0);
variable v_raddr : std_logic_vector(abits downto 0);
begin
-- initialize fifo signals on write side
wr_v := wr_r;
wr_v.full := '0';
afull <= '0';
if sepclk = 1 then
v_raddr := gray_decoder(wr_raddr_gray);
else
v_raddr := rd_r.raddr;
end if;
-- fifo full generation and compute wusedw
-- decode read address coming from read clock domain
v_wusedw := wr_r.waddr - v_raddr;
wr_v.full := v_wusedw(abits);
-- write fifo
if write = '1' then
wr_v.waddr := wr_r.waddr + 1;
end if;
if sepclk = 1 then
wr_v.waddr_gray := gray_encoder(wr_v.waddr);
end if;
-- synchronous reset
if wrstn = '0' then
wr_v.waddr := (others =>'0');
wr_v.waddr_gray := (others =>'0');
wr_v.full := '0';
end if;
-- assign wusedw and almost full fifo output
if v_wusedw > pfull then
afull <= '1';
end if;
-- signal assignment
wfull <= wr_v.full;
wusedw <= v_wusedw(abits-1 downto 0);
-- update fifo signals
wr_rin <= wr_v;
end process;
wr_sync: process(wclk)
begin
if rising_edge(wclk) then
wr_r <= wr_rin;
end if;
end process;
sync_reg: if sepclk = 1 generate
-----------------------------------
-- sync regs for dual clock FIFO --
-----------------------------------
-- transfer write address (encoded) in read clock domain
-- transfer read address (encoded) in write clock domain
-- transfer empty in write clock domain
-- transfer full in read block domain
-- Note: input d is already registered in the source clock domain
syn_gen0: for i in 0 to abits generate -- fifo addresses
syncreg_inst0: syncreg generic map (tech => tech, stages => 2)
port map(clk => rclk, d => wr_r.waddr_gray(i), q => rd_waddr_gray(i));
syncreg_inst1: syncreg generic map (tech => tech, stages => 2)
port map(clk => wclk, d => rd_r.raddr_gray(i), q => wr_raddr_gray(i));
end generate;
syncreg_inst2: syncreg generic map (tech => tech, stages => 2)
port map(clk => wclk, d => rd_r.empty, q => wempty);
syncreg_inst3: syncreg generic map (tech => tech, stages => 2)
port map(clk => rclk, d => wr_r.full, q => rfull);
end generate;
no_sync_reg: if sepclk = 0 generate
---------------------------------------
-- single clock FIFO logic (no sync) --
---------------------------------------
wempty <= rd_r.empty;
rfull <= wr_r.full;
end generate;
--------------------
-- read clock domain
--------------------
rd_comb: process(rd_r, renable, rd_waddr_gray, rrstn, wr_r.waddr)
variable rd_v : rd_fifo_type;
variable v_rusedw : std_logic_vector(abits downto 0);
variable v_waddr : std_logic_vector(abits downto 0);
begin
-- initialize fifo signals on read side
rd_v := rd_r;
rd_v.empty := '0';
aempty <= '0';
if sepclk = 1 then
v_waddr := gray_decoder(rd_waddr_gray);
else
v_waddr := wr_r.waddr;
end if;
-- fifo empty generation and compute rusedw fifo output
-- decode write address coming from write clock domain
v_rusedw := v_waddr - rd_r.raddr;
if conv_integer(v_rusedw) = 0 then
rd_v.empty := '1';
end if;
-- read fifo
if renable = '1' then
rd_v.raddr := rd_r.raddr + 1;
end if;
if sepclk = 1 then
rd_v.raddr_gray := gray_encoder(rd_v.raddr);
end if;
-- synchronous reset
if rrstn = '0' then
rd_v.raddr := (others =>'0');
rd_v.raddr_gray := (others =>'0');
rd_v.empty := '1';
end if;
-- assign almost empty
if v_rusedw < pempty then
aempty <= '1';
end if;
-- signal assignment
rempty <= rd_v.empty;
rusedw <= v_rusedw(abits-1 downto 0);
-- update fifo signals
rd_rin <= rd_v;
end process;
rd_sync: process(rclk)
begin
if rising_edge(rclk) then
rd_r <= rd_rin;
end if;
end process;
-- memory instantiation
nofwft_gen: if fwft = 0 generate
ram0 : syncram_2p generic map ( tech => tech, abits => abits, dbits => dbits, sepclk => sepclk)
port map (rclk, renable, rd_rin.raddr(abits-1 downto 0), dataout, wclk, write, wr_rin.waddr(abits-1 downto 0), datain);
end generate;
fwft_gen: if fwft = 1 generate
ram0 : syncram_2p generic map ( tech => tech, abits => abits, dbits => dbits, sepclk => sepclk)
port map (rclk, '1', rd_rin.raddr(abits-1 downto 0), dataout, wclk, write, wr_r.waddr(abits-1 downto 0), datain);
end generate;
end;
| gpl-3.0 | b3865102b10cac96095478e200a4761d | 0.596594 | 3.662366 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-xilinx-zc702/config.vhd | 2 | 5,499 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := zynq7000;
constant CFG_MEMTECH : integer := zynq7000;
constant CFG_PADTECH : integer := zynq7000;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := zynq7000;
constant CFG_CLKMUL : integer := (8);
constant CFG_CLKDIV : integer := (32);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 1;
constant CFG_NWP : integer := (1);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 1*2 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 0 + 0 + 0;
constant CFG_ETH_BUF : integer := 1;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000009#;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB ROM
constant CFG_AHBROMEN : integer := 1;
constant CFG_AHBROPIP : integer := 1;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#100#;
constant CFG_ROMMASK : integer := 16#E00# + 16#100#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (16);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-3.0 | 02f9641ae88370ba2b9cb77ea130c631 | 0.641026 | 3.644135 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/memctrl/sdctrl.vhd | 1 | 29,783 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: sdctrl
-- File: sdctrl.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: 32-bit SDRAM memory controller.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.memctrl.all;
entity sdctrl is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
pwron : integer := 0;
sdbits : integer := 32;
oepol : integer := 0;
pageburst : integer := 0;
mobile : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end;
architecture rtl of sdctrl is
constant WPROTEN : boolean := wprot = 1;
constant SDINVCLK : boolean := invclk = 1;
constant BUS64 : boolean := (sdbits = 64);
constant REVISION : integer := 1;
constant PM_PD : std_logic_vector(2 downto 0) := "001";
constant PM_SR : std_logic_vector(2 downto 0) := "010";
constant PM_DPD : std_logic_vector(2 downto 0) := "101";
constant std_rammask: Std_Logic_Vector(31 downto 20) :=
Conv_Std_Logic_Vector(hmask, 12);
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_SDCTRL, 0, REVISION, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
5 => ahb_iobar(ioaddr, iomask),
others => zero32);
type mcycletype is (midle, active, leadout);
type sdcycletype is (act1, act2, act3, rd1, rd2, rd3, rd4, rd5, rd6, rd7, rd8,
wr1, wr2, wr3, wr4, wr5, sidle,
sref, pd, dpd);
type icycletype is (iidle, pre, ref, lmode, emode, finish);
-- sdram configuration register
type sdram_cfg_type is record
command : std_logic_vector(2 downto 0);
csize : std_logic_vector(1 downto 0);
bsize : std_logic_vector(2 downto 0);
casdel : std_ulogic; -- CAS to data delay: 2/3 clock cycles
trfc : std_logic_vector(2 downto 0);
trp : std_ulogic; -- precharge to activate: 2/3 clock cycles
refresh : std_logic_vector(14 downto 0);
renable : std_ulogic;
pageburst : std_ulogic;
mobileen : std_logic_vector(1 downto 0); -- Mobile SD support, Mobile SD enabled
ds : std_logic_vector(3 downto 0); -- ds(1:0) (ds(3:2) used to detect update)
tcsr : std_logic_vector(3 downto 0); -- tcrs(1:0) (tcrs(3:2) used to detect update)
pasr : std_logic_vector(5 downto 0); -- pasr(2:0) (pasr(5:3) used to detect update)
pmode : std_logic_vector(2 downto 0); -- Power-Saving mode
txsr : std_logic_vector(3 downto 0); -- Exit Self Refresh timing
cke : std_ulogic; -- Clock enable
end record;
-- local registers
type reg_type is record
hready : std_ulogic;
hsel : std_ulogic;
bdrive : std_ulogic;
nbdrive : std_ulogic;
burst : std_ulogic;
wprothit : std_ulogic;
hio : std_ulogic;
startsd : std_ulogic;
mstate : mcycletype;
sdstate : sdcycletype;
cmstate : mcycletype;
istate : icycletype;
icnt : std_logic_vector(2 downto 0);
haddr : std_logic_vector(31 downto 0);
hrdata : std_logic_vector(sdbits-1 downto 0);
hwdata : std_logic_vector(31 downto 0);
hwrite : std_ulogic;
htrans : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
size : std_logic_vector(1 downto 0);
cfg : sdram_cfg_type;
trfc : std_logic_vector(3 downto 0);
refresh : std_logic_vector(14 downto 0);
sdcsn : std_logic_vector(1 downto 0);
sdwen : std_ulogic;
rasn : std_ulogic;
casn : std_ulogic;
dqm : std_logic_vector(7 downto 0);
address : std_logic_vector(16 downto 2); -- memory address
bsel : std_ulogic;
idlecnt : std_logic_vector(3 downto 0); -- Counter, 16 idle clock sycles before entering Power-Saving mode
sref_tmpcom : std_logic_vector(2 downto 0); -- Save SD command when exit sref
pwron : std_ulogic;
end record;
signal r, ri : reg_type;
signal rbdrive, ribdrive : std_logic_vector(31 downto 0);
attribute syn_preserve : boolean;
attribute syn_preserve of rbdrive : signal is true;
begin
ctrl : process(rst, ahbsi, r, sdi, rbdrive)
variable v : reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable dataout : std_logic_vector(31 downto 0); -- data from memory
variable regsd : std_logic_vector(31 downto 0); -- data from registers
variable dqm : std_logic_vector(7 downto 0);
variable raddr : std_logic_vector(12 downto 0);
variable adec : std_ulogic;
variable rams : std_logic_vector(1 downto 0);
variable ba : std_logic_vector(1 downto 0);
variable haddr : std_logic_vector(31 downto 0);
variable dout : std_logic_vector(31 downto 0);
variable hsize : std_logic_vector(1 downto 0);
variable hwrite : std_ulogic;
variable htrans : std_logic_vector(1 downto 0);
variable hready : std_ulogic;
variable vbdrive : std_logic_vector(31 downto 0);
variable bdrive : std_ulogic;
variable lline : std_logic_vector(2 downto 0);
variable lineburst : boolean;
variable haddr_tmp : std_logic_vector(31 downto 0);
variable arefresh : std_logic;
variable hwdata : std_logic_vector(31 downto 0);
begin
-- Variable default settings to avoid latches
v := r; startsd := '0'; v.hresp := HRESP_OKAY; vbdrive := rbdrive; arefresh := '0';
v.hrdata(sdbits-1 downto sdbits-32) := sdi.data(sdbits-1 downto sdbits-32);
v.hrdata(31 downto 0) := sdi.data(31 downto 0);
hwdata := ahbreadword(ahbsi.hwdata, r.haddr(4 downto 2)); v.hwdata := hwdata;
lline := not r.cfg.casdel & r.cfg.casdel & r.cfg.casdel;
if (pageburst = 0) or ((pageburst = 2) and r.cfg.pageburst = '0') then
lineburst := true;
else lineburst := false; end if;
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
v.size := ahbsi.hsize(1 downto 0); v.hwrite := ahbsi.hwrite;
v.htrans := ahbsi.htrans;
if ahbsi.htrans(1) = '1' then
v.hio := ahbsi.hmbsel(1);
v.hsel := '1'; v.hready := v.hio;
end if;
v.haddr := ahbsi.haddr;
-- addr must be masked since address range can be smaller than
-- total banksize. this can result in wrong chip select being
-- asserted
for i in 31 downto 20 loop
v.haddr(i) := ahbsi.haddr(i) and not std_rammask(i);
end loop;
end if;
if (r.hsel = '1') and (ahbsi.hready = '0') then
haddr := r.haddr; hsize := r.size;
htrans := r.htrans; hwrite := r.hwrite;
else
haddr := ahbsi.haddr; hsize := ahbsi.hsize(1 downto 0);
htrans := ahbsi.htrans; hwrite := ahbsi.hwrite;
-- addr must be masked since address range can be smaller than
-- total banksize. this can result in wrong chip select being
-- asserted
for i in 31 downto 20 loop
haddr(i) := ahbsi.haddr(i) and not std_rammask(i);
end loop;
end if;
if fast = 1 then haddr := r.haddr; end if;
if ahbsi.hready = '1' then v.hsel := ahbsi.hsel(hindex); end if;
-- main state
case r.size is
when "00" =>
case r.haddr(1 downto 0) is
when "00" => dqm := "11110111";
when "01" => dqm := "11111011";
when "10" => dqm := "11111101";
when others => dqm := "11111110";
end case;
when "01" =>
if r.haddr(1) = '0' then dqm := "11110011"; else dqm := "11111100"; end if;
when others => dqm := "11110000";
end case;
if BUS64 and (r.bsel = '1') then dqm := dqm(3 downto 0) & "1111"; end if;
-- main FSM
case r.mstate is
when midle =>
if ((v.hsel and htrans(1) and not v.hio) = '1') then
if (r.sdstate = sidle) and (r.cfg.command = "000")
and (r.cmstate = midle) and (v.hio = '0')
then
if fast = 0 then startsd := '1'; else v.startsd := '1'; end if;
v.mstate := active;
elsif ((r.sdstate = sref) or (r.sdstate = pd) or (r.sdstate = dpd))
and (r.cfg.command = "000") and (r.cmstate = midle) and (v.hio = '0')
then
v.startsd := '1';
if r.sdstate = dpd then -- Error response when on Deep Power-Down mode
v.hresp := HRESP_ERROR;
else
v.mstate := active;
end if;
end if;
end if;
when others => null;
end case;
startsd := startsd or r.startsd;
-- generate row and column address size
case r.cfg.csize is
when "00" => raddr := haddr(22 downto 10);
when "01" => raddr := haddr(23 downto 11);
when "10" => raddr := haddr(24 downto 12);
when others =>
if r.cfg.bsize = "111" then raddr := haddr(26 downto 14);
else raddr := haddr(25 downto 13); end if;
end case;
-- generate bank address
ba := genmux(r.cfg.bsize, haddr(28 downto 21)) &
genmux(r.cfg.bsize, haddr(27 downto 20));
-- generate chip select
if BUS64 then
adec := genmux(r.cfg.bsize, haddr(30 downto 23));
v.bsel := genmux(r.cfg.bsize, r.haddr(29 downto 22));
else
adec := genmux(r.cfg.bsize, haddr(29 downto 22)); v.bsel := '0';
end if;
rams := adec & not adec;
-- sdram access FSM
if r.trfc /= "0000" then v.trfc := r.trfc - 1; end if;
if r.idlecnt /= "0000" then v.idlecnt := r.idlecnt - 1; end if;
case r.sdstate is
when sidle =>
if (startsd = '1') and (r.cfg.command = "000") and (r.cmstate = midle) then
v.address(16 downto 2) := ba & raddr;
v.sdcsn := not rams(1 downto 0); v.rasn := '0'; v.sdstate := act1;
v.startsd := '0';
elsif (r.idlecnt = "0000") and (r.cfg.command = "000")
and (r.cmstate = midle) and (r.cfg.mobileen(1) = '1') then
case r.cfg.pmode is
when PM_SR =>
v.cfg.cke := '0'; v.sdstate := sref;
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc; -- Control minimum duration of Self Refresh mode (= tRAS)
when PM_PD => v.cfg.cke := '0'; v.sdstate := pd;
when PM_DPD =>
v.cfg.cke := '0'; v.sdstate := dpd;
v.sdcsn := (others => '0'); v.sdwen := '0'; v.rasn := '1'; v.casn := '1';
when others =>
end case;
end if;
when act1 =>
v.rasn := '1'; v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc;
if r.cfg.casdel = '1' then v.sdstate := act2; else
v.sdstate := act3;
v.hready := r.hwrite and ahbsi.htrans(0) and ahbsi.htrans(1);
end if;
if WPROTEN then
v.wprothit := sdi.wprot;
if sdi.wprot = '1' then v.hresp := HRESP_ERROR; end if;
end if;
when act2 =>
v.sdstate := act3;
v.hready := r.hwrite and ahbsi.htrans(0) and ahbsi.htrans(1);
if WPROTEN and (r.wprothit = '1') then
v.hresp := HRESP_ERROR; v.hready := '0';
end if;
when act3 =>
v.casn := '0';
v.address(14 downto 2) := r.haddr(13 downto 12) & '0' & r.haddr(11 downto 2);
v.dqm := dqm; v.burst := r.hready;
if r.hwrite = '1' then
v.sdstate := wr1; v.sdwen := '0'; v.bdrive := '0';
if ahbsi.htrans = "11" or (r.hready = '0') then v.hready := '1'; end if;
if WPROTEN and (r.wprothit = '1') then
v.hresp := HRESP_ERROR; v.hready := '1';
v.sdstate := wr1; v.sdwen := '1'; v.bdrive := '1'; v.casn := '1';
end if;
else v.sdstate := rd1; end if;
when wr1 =>
v.address(14 downto 2) := r.haddr(13 downto 12) & '0' & r.haddr(11 downto 2);
if (((r.burst and r.hready) = '1') and (r.htrans = "11"))
and not (WPROTEN and (r.wprothit = '1'))
then
v.hready := ahbsi.htrans(0) and ahbsi.htrans(1) and r.hready;
if ((r.haddr(5 downto 2) = "1111") and (r.cfg.command = "100")) then -- exit on refresh
v.hready := '0';
end if;
else
v.sdstate := wr2; v.bdrive := '1'; v.casn := '1'; v.sdwen := '1';
v.dqm := (others => '1');
end if;
when wr2 =>
if (r.trfc(2 downto 1) = "00") then
if (r.cfg.trp = '0') then v.rasn := '0'; v.sdwen := '0'; end if;
v.sdstate := wr3;
end if;
when wr3 =>
if (r.cfg.trp = '1') then
v.rasn := '0'; v.sdwen := '0'; v.sdstate := wr4;
else
v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1'; v.sdstate := sidle;
v.idlecnt := (others => '1');
end if;
when wr4 =>
v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1';
if (r.cfg.trp = '1') then v.sdstate := wr5;
else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
when wr5 =>
v.sdstate := sidle; v.idlecnt := (others => '1');
when rd1 =>
v.casn := '1'; v.sdstate := rd7;
if lineburst and (ahbsi.htrans = "11") then
if r.haddr(4 downto 2) = "111" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
when rd7 =>
v.casn := '1';
if r.cfg.casdel = '1' then
v.sdstate := rd2;
if lineburst and (ahbsi.htrans = "11") then
if r.haddr(4 downto 2) = "110" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
else
v.sdstate := rd3;
if ahbsi.htrans /= "11" then
if (r.trfc(3 downto 1) = "000") then v.rasn := '0'; v.sdwen := '0'; end if;
elsif lineburst then
if r.haddr(4 downto 2) = "110" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
end if;
when rd2 =>
v.casn := '1'; v.sdstate := rd3;
if ahbsi.htrans /= "11" then
if (r.trfc(2 downto 1) = "00") then v.rasn := '0'; v.sdwen := '0'; end if;
elsif lineburst then
if r.haddr(4 downto 2) = "101" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
if v.sdwen = '0' then v.dqm := (others => '1'); end if;
when rd3 =>
v.sdstate := rd4; v.hready := '1'; v.casn := '1';
if r.sdwen = '0' then
v.rasn := '1'; v.sdwen := '1'; v.sdcsn := "11"; v.dqm := (others => '1');
elsif lineburst and (ahbsi.htrans = "11") and (r.casn = '1') then
if r.haddr(4 downto 2) = ("10" & not r.cfg.casdel) then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
when rd4 =>
v.hready := '1'; v.casn := '1';
if (ahbsi.htrans /= "11") or (r.sdcsn = "11") or
((r.haddr(5 downto 2) = "1111") and (r.cfg.command = "100")) -- exit on refresh
then
v.hready := '0'; v.dqm := (others => '1');
if (r.sdcsn /= "11") then
v.rasn := '0'; v.sdwen := '0'; v.sdstate := rd5;
else
if r.cfg.trp = '1' then v.sdstate := rd6;
else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
end if;
elsif lineburst then
if (r.haddr(4 downto 2) = lline) and (r.casn = '1') then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
when rd5 =>
if r.cfg.trp = '1' then v.sdstate := rd6; else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1'; v.dqm := (others => '1');
v.casn := '1';
when rd6 =>
v.sdstate := sidle; v.idlecnt := (others => '1'); v.dqm := (others => '1');
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1';
when sref =>
if (startsd = '1' and (r.hio = '0'))
or (r.cfg.command /= "000") or r.cfg.pmode /= PM_SR then
if r.trfc = "0000" then -- Minimum duration (= tRAS)
v.cfg.cke := '1';
v.sdcsn := (others => '0'); v.rasn := '1'; v.casn := '1';
end if;
if r.cfg.cke = '1' then
if (r.idlecnt = "0000") then -- tXSR ns with NOP
v.sdstate := sidle;
v.idlecnt := (others => '1');
v.sref_tmpcom := r.cfg.command;
v.cfg.command := "100";
end if;
else
v.idlecnt := r.cfg.txsr;
end if;
end if;
when pd =>
if (startsd = '1' and (r.hio = '0'))
or (r.cfg.command /= "000") or r.cfg.pmode /= PM_PD then
v.cfg.cke := '1';
v.sdstate := sidle;
v.idlecnt := (others => '1');
end if;
when dpd =>
v.sdcsn := (others => '1'); v.sdwen := '1'; v.rasn := '1'; v.casn := '1';
v.cfg.renable := '0';
if (startsd = '1' and r.hio = '0') then
v.hready := '1'; -- ack all accesses with Error response
v.startsd := '0';
v.hresp := HRESP_ERROR;
elsif r.cfg.pmode /= PM_DPD then
v.cfg.cke := '1';
if r.cfg.cke = '1' then
v.sdstate := sidle;
v.idlecnt := (others => '1');
v.cfg.renable := '1';
end if;
end if;
when others =>
v.sdstate := sidle; v.idlecnt := (others => '1');
end case;
-- sdram commands
case r.cmstate is
when midle =>
if r.sdstate = sidle then
case r.cfg.command is
when "010" => -- precharge
v.sdcsn := (others => '0'); v.rasn := '0'; v.sdwen := '0';
v.address(12) := '1'; v.cmstate := active;
when "100" => -- auto-refresh
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.cmstate := active;
when "110" => -- Lodad Mode Reg
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active;
if lineburst then
v.address(16 downto 2) := "0000010001" & r.cfg.casdel & "0011";
else
v.address(16 downto 2) := "0000010001" & r.cfg.casdel & "0111";
end if;
when "111" => -- Load Ext-Mode Reg
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active;
v.address(16 downto 2) := "10000000" & r.cfg.ds(1 downto 0) & r.cfg.tcsr(1 downto 0)
& r.cfg.pasr(2 downto 0);
when others => null;
end case;
end if;
when active =>
v.sdcsn := (others => '1'); v.rasn := '1'; v.casn := '1';
v.sdwen := '1'; --v.cfg.command := "000";
v.cfg.command := r.sref_tmpcom; v.sref_tmpcom := "000";
v.cmstate := leadout; v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc;
when leadout =>
if r.trfc = "0000" then v.cmstate := midle; end if;
end case;
-- sdram init
case r.istate is
when iidle =>
v.cfg.cke := '1';
if (r.cfg.renable = '1' or (pwron /= 0 and r.pwron = '1')) and r.cfg.cke = '1' then
v.cfg.command := "010"; v.istate := pre;
end if;
when pre =>
if r.cfg.command = "000" then
v.cfg.command := "100"; v.istate := ref; v.icnt := "111";
end if;
when ref =>
if r.cfg.command = "000" then
v.cfg.command := "100"; v.icnt := r.icnt - 1;
if r.icnt = "000" then v.istate := lmode; v.cfg.command := "110"; end if;
end if;
when lmode =>
if r.cfg.command = "000" then
if r.cfg.mobileen = "11" then
v.cfg.command := "111"; v.istate := emode;
else
v.istate := finish;
end if;
end if;
when emode =>
if r.cfg.command = "000" then
v.istate := finish;
end if;
when others =>
if pwron /= 0 then v.pwron := '0'; end if;
if r.cfg.renable = '0' and r.sdstate /= dpd then
v.istate := iidle;
end if;
end case;
if (ahbsi.hready and ahbsi.hsel(hindex) ) = '1' then
if ahbsi.htrans(1) = '0' then v.hready := '1'; end if;
end if;
if (r.hsel and r.hio and not r.hready) = '1' then v.hready := '1'; end if;
-- second part of main fsm
case r.mstate is
when active =>
if v.hready = '1' then
v.mstate := midle;
end if;
when others => null;
end case;
-- sdram refresh counter
-- pragma translate_off
if not is_x(r.cfg.refresh) then
-- pragma translate_on
if (r.cfg.renable = '1') and (r.istate = finish) and r.sdstate /= sref then
v.refresh := r.refresh - 1;
if (v.refresh(14) and not r.refresh(14)) = '1' then
v.refresh := r.cfg.refresh;
v.cfg.command := "100";
arefresh := '1';
end if;
end if;
-- pragma translate_off
end if;
-- pragma translate_on
-- AHB register access
if (r.hsel and r.hio and r.hwrite and r.htrans(1)) = '1' then
if r.haddr(3 downto 2) = "00" then
if pageburst = 2 then v.cfg.pageburst := hwdata(17); end if;
v.cfg.command := hwdata(20 downto 18);
v.cfg.csize := hwdata(22 downto 21);
v.cfg.bsize := hwdata(25 downto 23);
v.cfg.casdel := hwdata(26);
v.cfg.trfc := hwdata(29 downto 27);
v.cfg.trp := hwdata(30);
v.cfg.renable := hwdata(31);
v.cfg.refresh := hwdata(14 downto 0);
v.refresh := (others => '0');
elsif r.haddr(3 downto 2) = "01" then
if r.cfg.mobileen(1) = '1' and mobile /= 3 then v.cfg.mobileen(0) := hwdata(31); end if;
if r.cfg.pmode = "000" then
v.cfg.cke := hwdata(30);
end if;
if r.cfg.mobileen(1) = '1' then
v.cfg.txsr := hwdata(23 downto 20);
v.cfg.pmode := hwdata(18 downto 16);
v.cfg.ds(3 downto 2) := hwdata( 6 downto 5);
v.cfg.tcsr(3 downto 2) := hwdata( 4 downto 3);
v.cfg.pasr(5 downto 3) := hwdata( 2 downto 0);
end if;
end if;
end if;
-- Disable CS and DPD when Mobile SDR is Disabled
if r.cfg.mobileen(0) = '0' then v.cfg.pmode(2) := '0'; end if;
-- Update EMR when ds, tcsr or pasr change
if r.cfg.command = "000" and arefresh = '0' and r.cfg.mobileen(0) = '1' then
if r.cfg.ds(1 downto 0) /= r.cfg.ds(3 downto 2) then
v.cfg.command := "111"; v.cfg.ds(1 downto 0) := r.cfg.ds(3 downto 2);
end if;
if r.cfg.tcsr(1 downto 0) /= r.cfg.tcsr(3 downto 2) then
v.cfg.command := "111"; v.cfg.tcsr(1 downto 0) := r.cfg.tcsr(3 downto 2);
end if;
if r.cfg.pasr(2 downto 0) /= r.cfg.pasr(5 downto 3) then
v.cfg.command := "111"; v.cfg.pasr(2 downto 0) := r.cfg.pasr(5 downto 3);
end if;
end if;
regsd := (others => '0');
if r.haddr(3 downto 2) = "00" then
regsd(31 downto 18) := r.cfg.renable & r.cfg.trp & r.cfg.trfc &
r.cfg.casdel & r.cfg.bsize & r.cfg.csize & r.cfg.command;
if not lineburst then regsd(17) := '1'; end if;
regsd(16) := r.cfg.mobileen(1);
if BUS64 then regsd(15) := '1'; end if;
regsd(14 downto 0) := r.cfg.refresh;
elsif r.haddr(3 downto 2) = "01" then
regsd(31) := r.cfg.mobileen(0);
regsd(30) := r.cfg.cke;
regsd(23 downto 0) := r.cfg.txsr & '0' & r.cfg.pmode & "000000000" &
r.cfg.ds(1 downto 0) & r.cfg.tcsr(1 downto 0) & r.cfg.pasr(2 downto 0);
end if;
if (r.hsel and r.hio) = '1' then dout := regsd;
else
if BUS64 and r.bsel = '1' then dout := r.hrdata(63 downto 32);
else dout := r.hrdata(31 downto 0); end if;
end if;
v.nbdrive := not v.bdrive;
if oepol = 1 then bdrive := r.nbdrive; vbdrive := (others => v.nbdrive);
else bdrive := r.bdrive; vbdrive := (others => v.bdrive);end if;
-- reset
if rst = '0' then
v.sdstate := sidle;
v.mstate := midle;
v.istate := iidle;
v.cmstate := midle;
v.hsel := '0';
v.cfg.command := "000";
v.cfg.csize := "10";
v.cfg.bsize := "000";
v.cfg.casdel := '1';
v.cfg.trfc := "111";
v.cfg.renable := '0';
v.cfg.trp := '1';
v.dqm := (others => '1');
v.sdwen := '1';
v.rasn := '1';
v.casn := '1';
v.hready := '1';
v.bsel := '0';
v.startsd := '0';
if pwron /= 0 then v.pwron := '1'; end if;
if (pageburst = 2) then
v.cfg.pageburst := '0';
end if;
if mobile >= 2 then v.cfg.mobileen := "11";
elsif mobile = 1 then v.cfg.mobileen := "10";
else v.cfg.mobileen := "00"; end if;
v.cfg.txsr := (others => '1');
v.cfg.pmode := (others => '0');
v.cfg.ds := (others => '0');
v.cfg.tcsr := (others => '0');
v.cfg.pasr := (others => '0');
if mobile >= 2 then v.cfg.cke := '0';
else v.cfg.cke := '1'; end if;
v.sref_tmpcom := "000";
v.idlecnt := (others => '1');
v.hio := '0';
end if;
if pwron = 0 then v.pwron := '0'; end if;
if not WPROTEN then v.wprothit := '0'; end if;
ri <= v;
ribdrive <= vbdrive;
ahbso.hready <= r.hready;
ahbso.hresp <= r.hresp;
ahbso.hrdata <= ahbdrivedata(dout);
end process;
--sdo.sdcke <= (others => '1');
sdo.sdcke <= (others => r.cfg.cke);
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
driveundriven : block
begin
sdo.qdrive <= '0';
sdo.nbdrive <= '0';
sdo.ce <= '0';
sdo.moben <= '0';
sdo.cal_rst <= '0';
sdo.oct <= '0';
sdo.dqs_gate <= '0';
sdo.xsdcsn <= (others => '1');
sdo.data(127 downto sdbits) <= (others => '0');
sdo.cb <= (others => '0');
sdo.ba <= (others => '0');
sdo.sdck <= (others => '0');
sdo.cal_en <= (others => '0');
sdo.cal_inc <= (others => '0');
sdo.cal_pll <= (others => '0');
sdo.odt <= (others => '0');
sdo.conf <= (others => '0');
sdo.vcbdrive <= (others => '0');
sdo.cbdqm <= (others => '0');
sdo.cbcal_en <= (others => '0');
sdo.cbcal_inc <= (others => '0');
sdo.read_pend <= (others => '0');
sdo.regwdata <= (others => '0');
sdo.regwrite <= (others => '0');
end block driveundriven;
regs : process(clk, rst) begin
if rising_edge(clk) then
r <= ri; rbdrive <= ribdrive;
if rst = '0' then r.icnt <= (others => '0'); end if;
end if;
if (rst = '0') then
r.sdcsn <= (others => '1'); r.bdrive <= '1'; r.nbdrive <= '0';
if oepol = 0 then rbdrive <= (others => '1');
else rbdrive <= (others => '0'); end if;
end if;
end process;
rgen : if not SDINVCLK generate
sdo.address <= r.address;
sdo.bdrive <= r.nbdrive when oepol = 1 else r.bdrive;
sdo.vbdrive <= zero32 & rbdrive;
sdo.sdcsn <= r.sdcsn;
sdo.sdwen <= r.sdwen;
sdo.dqm <= "11111111" & r.dqm;
sdo.rasn <= r.rasn;
sdo.casn <= r.casn;
drivebus: for i in 0 to sdbits/64 generate
sdo.data(31+32*i downto 32*i) <= r.hwdata;
end generate;
end generate;
ngen : if SDINVCLK generate
nregs : process(clk, rst) begin
if falling_edge(clk) then
sdo.address <= r.address;
if oepol = 1 then sdo.bdrive <= r.nbdrive;
else sdo.bdrive <= r.bdrive; end if;
sdo.vbdrive <= zero32 & rbdrive;
sdo.sdcsn <= r.sdcsn;
sdo.sdwen <= r.sdwen;
sdo.dqm <= "11111111" & r.dqm;
sdo.rasn <= r.rasn;
sdo.casn <= r.casn;
for i in 0 to sdbits/64 loop
sdo.data(31+32*i downto 32*i) <= r.hwdata;
end loop;
end if;
if rst = '0' then sdo.sdcsn <= (others => '1'); end if;
end process;
end generate;
-- pragma translate_off
bootmsg : report_version
generic map ("sdctrl" & tost(hindex) &
": PC133 SDRAM controller rev " & tost(REVISION));
-- pragma translate_on
end;
| gpl-3.0 | f303b7e8d168ba2b086e94c89d016528 | 0.524494 | 3.25284 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-altera-ep3sl150/config.vhd | 1 | 6,961 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := stratix3;
constant CFG_MEMTECH : integer := stratix3;
constant CFG_PADTECH : integer := stratix3;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := stratix3;
constant CFG_CLKMUL : integer := (30);
constant CFG_CLKDIV : integer := (10);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0058#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000012#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- SSRAM controller
constant CFG_SSCTRL : integer := 0;
constant CFG_SSCTRLP16 : integer := 0;
-- DDR controller
constant CFG_DDR2SP : integer := 1;
constant CFG_DDR2SP_INIT : integer := 1;
constant CFG_DDR2SP_FREQ : integer := (200);
constant CFG_DDR2SP_TRFC : integer := (130);
constant CFG_DDR2SP_DATAWIDTH : integer := (64);
constant CFG_DDR2SP_FTEN : integer := 0;
constant CFG_DDR2SP_FTWIDTH : integer := 0;
constant CFG_DDR2SP_COL : integer := (10);
constant CFG_DDR2SP_SIZE : integer := (256);
constant CFG_DDR2SP_DELAY0 : integer := (0);
constant CFG_DDR2SP_DELAY1 : integer := (0);
constant CFG_DDR2SP_DELAY2 : integer := (0);
constant CFG_DDR2SP_DELAY3 : integer := (0);
constant CFG_DDR2SP_DELAY4 : integer := (0);
constant CFG_DDR2SP_DELAY5 : integer := (0);
constant CFG_DDR2SP_DELAY6 : integer := (0);
constant CFG_DDR2SP_DELAY7 : integer := (0);
constant CFG_DDR2SP_NOSYNC : integer := 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 16;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#6#;
constant CFG_GRGPIO_WIDTH : integer := (3);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-3.0 | 6f61a9123c04354a5a12aafaf2041c34 | 0.646172 | 3.540692 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-digilent-nexys-video/testbench.vhd | 1 | 8,368 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2016 Cobham Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
use work.debug.all;
use work.config.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
USE_MIG_INTERFACE_MODEL : boolean := false;
clkperiod : integer := 10 -- system clock period
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sdramfile : string := "ram.srec"; -- sdram contents
constant ct : integer := clkperiod/2;
-- MIG Simulation parameters
constant SIM_BYPASS_INIT_CAL : string := "FAST";
-- # = "OFF" - Complete memory init &
-- calibration sequence
-- # = "SKIP" - Not supported
-- # = "FAST" - Complete memory init & use
-- abbreviated calib sequence
constant SIMULATION : string := "TRUE";
-- Should be TRUE during design simulations and
-- FALSE during implementations
signal sysclk : std_ulogic := '0';
-- LEDs
signal led : std_logic_vector(7 downto 0);
-- Buttons
signal btnc : std_ulogic;
signal btnd : std_ulogic;
signal btnl : std_ulogic;
signal btnr : std_ulogic;
signal cpu_resetn : std_ulogic;
-- Switches
signal sw : std_logic_vector(7 downto 0);
-- USB-RS232 interface
signal uart_tx_in : std_logic;
signal uart_rx_out : std_logic;
-- DDR3
signal ddr3_dq : std_logic_vector(15 downto 0);
signal ddr3_dqs_p : std_logic_vector(1 downto 0);
signal ddr3_dqs_n : std_logic_vector(1 downto 0);
signal ddr3_addr : std_logic_vector(14 downto 0);
signal ddr3_ba : std_logic_vector(2 downto 0);
signal ddr3_ras_n : std_logic;
signal ddr3_cas_n : std_logic;
signal ddr3_we_n : std_logic;
signal ddr3_reset_n : std_logic;
signal ddr3_ck_p : std_logic_vector(0 downto 0);
signal ddr3_ck_n : std_logic_vector(0 downto 0);
signal ddr3_cke : std_logic_vector(0 downto 0);
signal ddr3_dm : std_logic_vector(1 downto 0);
signal ddr3_odt : std_logic_vector(0 downto 0);
-- Fan PWM
signal fan_pwm : std_ulogic;
-- SPI
signal qspi_cs : std_logic;
signal qspi_dq : std_logic_vector(3 downto 0);
signal scl : std_ulogic;
signal gnd : std_ulogic;
signal phy_gtxclk : std_logic := '0';
signal phy_txer : std_ulogic;
signal phy_txd : std_logic_vector(7 downto 0);
signal phy_txctl_txen : std_ulogic;
signal phy_txclk : std_ulogic;
signal phy_rxer : std_ulogic;
signal phy_rxd : std_logic_vector(7 downto 0);
signal phy_rxctl_rxdv : std_ulogic;
signal phy_rxclk : std_ulogic;
signal phy_reset : std_ulogic;
signal phy_mdio : std_logic;
signal phy_mdc : std_ulogic;
signal phy_crs : std_ulogic;
signal phy_col : std_ulogic;
signal phy_int : std_ulogic;
signal phy_rxdl : std_logic_vector(7 downto 0);
signal phy_txdl : std_logic_vector(7 downto 0);
begin
gnd <= '0';
-- clock and reset
sysclk <= not sysclk after ct * 1 ns;
cpu_resetn <= '0', '1' after 100 ns;
d3 : entity work.leon3mp
generic map (fabtech, memtech, padtech, clktech, disas, dbguart, pclow,
SIM_BYPASS_INIT_CAL, SIMULATION, USE_MIG_INTERFACE_MODEL)
port map (
sysclk => sysclk, led => led,
btnc => btnc, btnd => btnd, btnl => btnl, btnr => btnr,
cpu_resetn => cpu_resetn,
sw => sw,
uart_tx_in => uart_tx_in, uart_rx_out => uart_rx_out,
ddr3_dq => ddr3_dq, ddr3_dqs_p => ddr3_dqs_p, ddr3_dqs_n => ddr3_dqs_n,
ddr3_addr => ddr3_addr, ddr3_ba => ddr3_ba,
ddr3_ras_n => ddr3_ras_n, ddr3_cas_n => ddr3_cas_n,
ddr3_we_n => ddr3_we_n, ddr3_reset_n => ddr3_reset_n,
ddr3_ck_p => ddr3_ck_p, ddr3_ck_n => ddr3_ck_n,
ddr3_cke => ddr3_cke, ddr3_dm => ddr3_dm, ddr3_odt => ddr3_odt,
fan_pwm => fan_pwm,
qspi_cs => qspi_cs, qspi_dq => qspi_dq, scl => scl,
phy_txclk => phy_gtxclk,
phy_txd => phy_txd(3 downto 0),
phy_txctl_txen => phy_txctl_txen,
phy_rxd => phy_rxd(3 downto 0)'delayed(0 ns),
phy_rxctl_rxdv => phy_rxctl_rxdv'delayed(0 ns),
phy_rxclk => phy_rxclk'delayed(0 ns),
phy_reset => phy_reset,
phy_mdio => phy_mdio,
phy_mdc => phy_mdc,
phy_int => '0'
);
ddr3mem0 : ddr3ram
generic map(
width => 16, abits => 15, colbits => 10, rowbits => 13,
implbanks => 8, fname => sdramfile, speedbin=>1, density => 3, lddelay => (0 ns))
-- swap => CFG_MIG_7SERIES)
port map (ck => ddr3_ck_p(0), ckn => ddr3_ck_n(0), cke => ddr3_cke(0), csn => gnd,
odt => ddr3_odt(0), rasn => ddr3_ras_n, casn => ddr3_cas_n, wen => ddr3_we_n,
dm => ddr3_dm, ba => ddr3_ba, a => ddr3_addr,
resetn => ddr3_reset_n,
dq => ddr3_dq(15 downto 0),
dqs => ddr3_dqs_p, dqsn => ddr3_dqs_n, doload => led(4));
spimem0: if CFG_SPIMCTRL = 1 generate
s0 : spi_flash generic map (ftype => 4, debug => 0, fname => promfile,
readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => CFG_SPIMCTRL_DUALOUTPUT)
port map (scl, qspi_dq(0), qspi_dq(1), qspi_cs);
end generate spimem0;
phy0 : if (CFG_GRETH = 1) generate
phy_mdio <= 'H';
phy_int <= '0';
p0: phy
generic map (
address => 7,
extended_regs => 1,
aneg => 1,
base100_t4 => 1,
base100_x_fd => 1,
base100_x_hd => 1,
fd_10 => 1,
hd_10 => 1,
base100_t2_fd => 1,
base100_t2_hd => 1,
base1000_x_fd => 1,
base1000_x_hd => 1,
base1000_t_fd => 1,
base1000_t_hd => 1,
rmii => 0,
rgmii => 1
)
port map(phy_reset, phy_mdio, phy_txclk, phy_rxclk, phy_rxd,
phy_rxctl_rxdv, phy_rxer, phy_col, phy_crs, phy_txd,
phy_txctl_txen, phy_txer, phy_mdc, phy_gtxclk);
end generate;
iuerr : process
begin
wait for 10 us;
assert (to_X01(led(3)) = '0')
report "*** IU in error mode, simulation halted ***"
severity failure;
end process;
end;
| gpl-3.0 | e9b624fcb73ba03a32b54601909629a8 | 0.539436 | 3.586798 | false | false | false | false |
yishinli/emc2 | src/hal/drivers/mesa-hostmot2/firmware/src/wordrb.vhd | 1 | 3,495 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
-- http://www.mesanet.com
--
-- This program is is licensed under a disjunctive dual license giving you
-- the choice of one of the two following sets of free software/open source
-- licensing terms:
--
-- * GNU General Public License (GPL), version 2.0 or later
-- * 3-clause BSD License
--
--
-- The GNU GPL License:
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- The 3-clause BSD License:
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- * Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- * Neither the name of Mesa Electronics nor the names of its
-- contributors may be used to endorse or promote products
-- derived from this software without specific prior written
-- permission.
--
--
-- Disclaimer:
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
entity wordrb is
generic (size : integer;
buswidth : integer);
port (
obus: out STD_LOGIC_VECTOR (31 downto 0);
readport: in STD_LOGIC;
portdata: in STD_LOGIC_VECTOR (size-1 downto 0) );
end wordrb;
architecture behavioral of wordrb is
begin
awordiorb: process (portdata,readport)
begin
obus <= (others => 'Z');
if readport = '1' then
obus(size-1 downto 0) <= portdata;
obus(buswidth -1 downto size) <= (others => '0');
end if;
end process;
end behavioral;
| lgpl-2.1 | fe878e7c5e4c0a88a31b42c5005ee177 | 0.688698 | 4.026498 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/misc/grgprbank.vhd | 1 | 5,174 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grgprbank
-- File: grgprbank.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: General purpose register bank
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
entity grgprbank is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
regbits: integer range 1 to 32 := 32;
nregs : integer range 1 to 32 := 1;
rstval : integer := 0;
extrst : integer := 0;
rdataen: integer := 0;
wproten: integer := 0;
partrstmsk: integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
rego : out std_logic_vector(nregs*regbits-1 downto 0);
resval : in std_logic_vector(nregs*regbits-1 downto 0);
rdata : in std_logic_vector(nregs*regbits-1 downto 0);
wprot : in std_logic_vector(nregs-1 downto 0);
partrst : in std_ulogic
);
end;
architecture rtl of grgprbank is
constant nregsp2: integer := 2**log2(nregs);
subtype regtype is std_logic_vector(regbits-1 downto 0);
type regbank is array(nregsp2-1 downto 0) of regtype;
type grgprbank_regs is record
regs: regbank;
end record;
signal r,nr: grgprbank_regs;
constant pconfig: apb_config_type := (
0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_GPREGBANK, 0, 0, 0),
1 => apb_iobar(paddr, pmask));
begin
comb: process(r,rst,apbi,resval,rdata,wprot,partrst)
variable v: grgprbank_regs;
variable o: apb_slv_out_type;
variable rd: regbank;
variable wprotx: std_logic_vector(nregsp2-1 downto 0);
begin
-- Init vars
v := r;
o := apb_none;
o.pindex := pindex;
o.pconfig := pconfig;
for x in nregs-1 downto 0 loop
rd(x) := rdata(x*regbits+regbits-1 downto x*regbits);
end loop;
wprotx := (others => '0');
wprotx(nregs-1 downto 0) := wprot;
-- APB Interface
if nregs > 1 then
o.prdata(regbits-1 downto 0) := r.regs(to_integer(unsigned(apbi.paddr(1+log2(nregs) downto 2))));
if rdataen /= 0 then
o.prdata(regbits-1 downto 0) := rd(to_integer(unsigned(apbi.paddr(1+log2(nregs) downto 2))));
end if;
if apbi.penable='1' and apbi.psel(pindex)='1' and apbi.pwrite='1' then
if wproten=0 or (wprotx(to_integer(unsigned(apbi.paddr(1+log2(nregs) downto 2))))='0') then
v.regs(to_integer(unsigned(apbi.paddr(1+log2(nregs) downto 2)))) := apbi.pwdata(regbits-1 downto 0);
end if;
end if;
else
o.prdata(regbits-1 downto 0) := r.regs(0);
if apbi.penable='1' and apbi.psel(pindex)='1' and apbi.pwrite='1' then
v.regs(0) := apbi.pwdata(regbits-1 downto 0);
end if;
end if;
-- Partial reset
if partrstmsk/=0 then
if partrst='0' then
for x in 0 to nregs-1 loop
if ((partrstmsk / (2**x)) mod 2) = 1 then
if extrst=0 then
v.regs(x) := std_logic_vector(to_unsigned(rstval,regbits));
else
v.regs(x) := resval(x*regbits+regbits-1 downto x*regbits);
end if;
end if;
end loop;
end if;
end if;
-- Reset
if rst='0' then
v.regs := (others => std_logic_vector(to_unsigned(rstval,regbits)));
if extrst/=0 then
for x in nregs-1 downto 0 loop
v.regs(x) := resval(x*regbits+regbits-1 downto x*regbits);
end loop;
end if;
end if;
-- clear unused part of reg bank so it can be pruned
if nregs < nregsp2 then
for x in nregsp2-1 downto nregs loop
v.regs(x) := (others => '0');
end loop;
end if;
-- Drive outputs
nr <= v;
apbo <= o;
for x in nregs-1 downto 0 loop
rego(x*regbits+regbits-1 downto x*regbits) <= r.regs(x);
end loop;
end process;
regs: process(clk)
begin
if rising_edge(clk) then r <= nr; end if;
end process;
end;
| gpl-3.0 | 2e51423095475b54e9eb469a57073ada | 0.59683 | 3.50542 | false | false | false | false |
ggaray/nicsim-vhd | buffmngr.vhd | 1 | 21,427 | -- NICSim-vhd: A VHDL-based modelling and simulation of NIC's buffers
-- Copyright (C) 2013 Godofredo R. Garay <godofredo.garay (-at-) gmail.com>
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
use std.textio.all;
library ieee;
--use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity buffmngr is
port (
pktarrival : in bit; -- The rising edge indicates that the first bit of the packet arrives at the NIC
pktsize : in integer; -- in bytes
transfer_start_req : out bit := '1';
transfer_end : in bit;
ethclk : in bit;
pciclk : in bit;
pktreceived : out bit := '0'; -- The rising edge indicates that all the bits have been received
payload_size_in_data_blocks : out integer := 0;
buffer_fill_level_in_bytes : out integer := 0;
buffer_fill_level_in_data_units : out integer := 0;
max_buffer_fill_level : out integer := 0;
dropped_packets_count : out integer := 0;
buffer_size_in_data_units : out integer := 10
);
end buffmngr;
architecture V1 of buffmngr is
--------------- Buffer configuration ---------------
constant buffer_size : integer := 10000; -- Number of memory locations
--------------- Bus width configuration ---------------
--constant bus_width_in_bits : integer := 32; -- PCI 33/32
constant bus_width_in_bits : integer := 64; -- PCI 66/64, PCI-X 133/64
constant bus_width_in_bytes : integer := bus_width_in_bits/8; -- PCI bus
-- ***To be removed
--constant bus_width_in_bytes : integer := 4; -- PCI bus
--constant bus_width_in_bytes : integer := 8; -- PCI-X bus
--------------- Descriptor size configuration ---------------
constant descriptor_size_in_bytes : integer := 16; -- Descriptor size in bytes
-- ****** In the future, constant pcilck_period should be removed a function based on the pciclk signal should be implemented
--constant pciclk_period : time := 0.03030303 us; -- PCI 33
--constant pciclk_period : time := 0.015151515 us; -- PCI 66
constant pciclk_period : time := 0.007518797 us; -- PCI-X 133
--constant pciclk_period : time := 0.003759398 us; -- PCI-X 266
--constant pciclk_period : time := 0.001876173 us; -- PCI-X 533
-- ******* to be removed, this constant is not used
--constant descriptor_size_in_dwords : integer := 4;
--constant descriptor_size_in_dwords : integer := 2; -- Descriptor size in data blocks (PCI-X bus)
-- ******* to be removed, constant packet_identification_latency is not used
--constant packet_identification_latency : time := 2 us;
--------------- Size of the Ethernet frame fields ---------------
constant preamble_in_bytes : integer := 7;
constant sof_in_bytes : integer := 1;
constant destination_address_in_bytes : integer := 6;
constant source_address_in_bytes : integer := 6;
constant length_in_bytes : integer := 2;
constant checksum_in_bytes : integer := 4;
--constant header_fields_length_in_octets : integer := 22; -- In octets
--constant trailer_fields_length_in_octets : integer := 4; -- In octets
-- Data structure used for data FIFO (implemented as a circular buffer)
type memory_array is
array (integer range 1 to buffer_size) of real;
shared variable nic_buffer_memory : memory_array;
-- FIFO pointers for implementing buffer ring
-- buff_in_ptr: pointer to the memory location for storing the next
-- received packet
shared variable buff_in_ptr : integer := 1;
-- buff_out_ptr: Pointer to the memory location of the next packet
-- to transfer from the NIC to the system memory
shared variable buff_out_ptr : integer := 0;
signal pktreceived_value : bit := '0';
-- Variables used for statistics and debugging
shared variable buff_fill_level : integer := 0; -- in bytes
shared variable occupancy : integer := 0; -- in memory locations
shared variable max_buff_fill_level : integer := 0; -- in bytes
shared variable total_received_packets : integer := 0;
shared variable total_dropped_packets : integer := 0;
shared variable input_packet_size : integer := 0;
-- Auxiliary procedure inc is used to increment pointers
procedure inc (variable ptr : inout integer) is
begin
if ptr = buffer_size
then ptr := 1;
else ptr := ptr + 1;
end if;
end procedure inc;
-- Architecture begin
begin
pktreceived <= pktreceived_value;
network_to_nic_packet_arrival: process
--file buffer_fill_level_output_file : text open write_mode is "pkt_arrival_fsm.out";
variable output_line : line;
variable total_bits_received_count : integer := 0;
variable pktsize_in_bits : integer := 0;
variable payload_size_in_octets : integer;
type pkt_arrival_state is (idle, waiting_end_of_packet, updating_buffer);
variable arrival_state : pkt_arrival_state := idle;
variable next_arrival_state : pkt_arrival_state := idle;
begin
wait until ethclk'event and ethclk = '1';
case arrival_state is
when idle =>
total_bits_received_count := 0;
pktsize_in_bits := 0;
if pktarrival = '0'
then
--write(output_line, string'("state = idle, pktarrival = '0' "));
--writeline(buffer_fill_level_output_file, output_line);
next_arrival_state := idle;
elsif pktarrival = '1'
then pktsize_in_bits := pktsize * 8;
-- Here, packet payload size (in octets) is computed. The actual size of the input packet (pktsize) is measured in octets.
payload_size_in_octets := pktsize - (preamble_in_bytes + sof_in_bytes + destination_address_in_bytes
+ source_address_in_bytes + length_in_bytes + checksum_in_bytes);
next_arrival_state := waiting_end_of_packet;
--write(output_line, string'("state = idle, pktarrival = '1' "));
--writeline(buffer_fill_level_output_file, output_line);
end if;
when waiting_end_of_packet =>
--write(output_line, string'("waiting_end_of_packet "));
--write(output_line, string'(" occupancy = "));
--write(output_line, occupancy);
if total_bits_received_count = pktsize_in_bits
then --write(output_line, string'(" total_bits_received_count = pktsize_in_bits "));
--write(output_line, string'(" total_bits_received_count = "));
--write(output_line, total_bits_received_count);
--write(output_line, string'(" pktsize_in_bits = "));
--write(output_line, pktsize_in_bits);
--writeline(buffer_fill_level_output_file, output_line);
pktreceived_value <= '1';
total_received_packets := total_received_packets + 1;
next_arrival_state := updating_buffer;
else total_bits_received_count := total_bits_received_count + 1;
--write(output_line, string'(" total_bits_received_count := total_bits_received_count + 1 "));
--write(output_line, string'(" total_bits_received_count = "));
--write(output_line, total_bits_received_count);
--write(output_line, string'(" pktsize_in_bits = "));
--write(output_line, pktsize_in_bits);
--writeline(buffer_fill_level_output_file, output_line);
next_arrival_state := waiting_end_of_packet;
end if;
when updating_buffer =>
--write(output_line, string'(" updating_buffer "));
--write(output_line, string'(" occupancy = "));
--write(output_line, occupancy);
if occupancy = 0
-- Packet payload is stored in the memory location pointed by buff_in_ptr.
-- Data are stored in data block units. The size of a data block depends on the bus width.
then --nic_buffer_memory(buff_in_ptr) := real(payload_size_in_octets)/real(4);
nic_buffer_memory(buff_in_ptr) := real(payload_size_in_octets)/real(bus_width_in_bytes);
--write(output_line, string'(" nic_buffer_memory(buff_in_ptr) := "));
--write(output_line, nic_buffer_memory(buff_in_ptr));
buff_out_ptr := 1;
inc(buff_in_ptr);
occupancy := occupancy + 1;
wait until pciclk'event and pciclk = '1';
buff_fill_level :=
buff_fill_level + (pktsize - (preamble_in_bytes + sof_in_bytes)) + descriptor_size_in_bytes;
input_packet_size := pktsize;
wait for pciclk_period;
input_packet_size := 0;
--write(output_line, string'(" buff_in_ptr = "));
--write(output_line, buff_in_ptr);
--writeline(buffer_fill_level_output_file, output_line);
pktreceived_value <= '0';
next_arrival_state := idle;
elsif occupancy > 0
and occupancy < buffer_size - 1
then --nic_buffer_memory(buff_in_ptr) := payload_size_in_octets/4;
--write(output_line, string'("if occupancy > 0 and and occupancy < buffer_size - 1"));
--write(output_line, string'(" occupancy ="));
--write(output_line, occupancy);
--nic_buffer_memory(buff_in_ptr) := real(payload_size_in_octets)/real(4);
nic_buffer_memory(buff_in_ptr) := real(payload_size_in_octets)/real(bus_width_in_bytes);
--write(output_line, string'(" nic_buffer_memory(buff_in_ptr) := "));
--write(output_line, nic_buffer_memory(buff_in_ptr));
inc(buff_in_ptr);
--write(output_line, string'(" buff_in_ptr = "));
--write(output_line, buff_in_ptr);
occupancy := occupancy + 1;
wait until pciclk'event and pciclk = '1';
buff_fill_level :=
buff_fill_level + (pktsize - (preamble_in_bytes + sof_in_bytes)) + descriptor_size_in_bytes;
input_packet_size := pktsize;
wait for pciclk_period;
input_packet_size := 0;
--writeline(buffer_fill_level_output_file, output_line);
pktreceived_value <= '0';
next_arrival_state := idle;
elsif occupancy = buffer_size - 1
then --nic_buffer_memory(buff_in_ptr) := payload_size_in_octets/4;
--nic_buffer_memory(buff_in_ptr) := real(payload_size_in_octets)/real(4);
nic_buffer_memory(buff_in_ptr) := real(payload_size_in_octets)/real(bus_width_in_bytes);
occupancy := occupancy + 1;
wait until pciclk'event and pciclk = '1';
buff_fill_level :=
buff_fill_level + (pktsize - (preamble_in_bytes + sof_in_bytes)) + descriptor_size_in_bytes;
input_packet_size := pktsize;
wait for pciclk_period;
input_packet_size := 0;
pktreceived_value <= '0';
next_arrival_state := idle;
elsif occupancy = buffer_size
then total_dropped_packets := total_dropped_packets + 1;
input_packet_size := pktsize;
wait for pciclk_period;
input_packet_size := 0;
assert false
report "total_dropped_packets := total_dropped_packets + 1"
severity warning;
pktreceived_value <= '0';
next_arrival_state := idle;
end if;
-- Total packets received is used for statistics
-- total_received_packets := total_received_packets + 1;
-- input_packet size is used for statistics
-- input_packet_size := pktsize;
-- wait for pciclk_period;
-- input_packet_size := 0;
-- else total_dropped_packets := total_dropped_packets + 1;
-- input_packet_size := pktsize;
-- wait for pciclk_period;
-- input_packet_size := 0;
-- end if;
-- arrival_next_state := idle;
end case;
arrival_state := next_arrival_state;
-- wait until pktarrival'event and pktarrival = '1';
-- Variable packets_received_count is used for obtaining statistics
--wait until pciclk'event and pciclk = '1';
--buff_fill_level := buff_fill_level + 1;
-- wait for packet_identification_latency;
--nic_buffer_memory(buff_in_ptr) := pktsize;
--buff_fill_level := buff_fill_level + pktsize;
end process network_to_nic_packet_arrival;
nic_to_memory_packet_transfer: process
-- States of Packet Transfer FSM
type pkt_transfer_state is (idle,
requesting_transfer,
transferring,
updating_buffer);
variable transfer_state : pkt_transfer_state := idle;
variable next_transfer_state : pkt_transfer_state := idle;
begin
--wait until pciclk'event and pciclk = '1';
wait until ethclk'event and ethclk = '1';
case transfer_state is
when idle =>
transfer_start_req <= '1';
payload_size_in_data_blocks <= 0;
buff_out_ptr := 0;
if buff_fill_level = 0
then next_transfer_state := idle;
elsif buff_fill_level > 0 and transfer_end = '0'
then assert false
report "pkt_transfer_fsm: requesting_transfer"
severity note;
next_transfer_state := requesting_transfer;
end if;
when requesting_transfer =>
--if buff_out_ptr = buffer_size
--then buff_out_ptr := 1;
--else buff_out_ptr := buff_out_ptr + 1;
--end if;
inc(buff_out_ptr);
payload_size_in_data_blocks <= integer(ceil(nic_buffer_memory(buff_out_ptr)));
--transfer_start_req <= '1';
--wait for pciclk_period;
assert false
report "pkt_transfer_fsm: transferring"
severity note;
transfer_start_req <= '0';
next_transfer_state := transferring;
when transferring =>
--wait until transfer_end'event and transfer_end = '1';
if transfer_end = '0'
then next_transfer_state := transferring;
elsif transfer_end = '1'
then assert false
report "pkt_transfer_fsm: updating_buffer"
severity note;
next_transfer_state := updating_buffer;
end if;
when updating_buffer =>
--wait until transfer_end'event and transfer_end = '1';
if occupancy = buffer_size
then wait until pciclk'event and pciclk = '0';
buff_fill_level := buff_fill_level -
(integer(nic_buffer_memory(buff_out_ptr)*real(bus_width_in_bytes)) + destination_address_in_bytes
+ source_address_in_bytes + length_in_bytes + checksum_in_bytes + descriptor_size_in_bytes);
-- (integer(nic_buffer_memory(buff_out_ptr)*real(bus_width_in_bytes)) + preamble_in_bytes + sof_in_bytes
-- + descriptor_size_in_bytes);
-- (integer(nic_buffer_memory(buff_out_ptr)*real(4)) + header_fields_length_in_octets + trailer_fields_length_in_octets);
occupancy := occupancy - 1;
inc(buff_in_ptr);
inc(buff_out_ptr);
next_transfer_state := idle;
elsif occupancy = 1
then wait until pciclk'event and pciclk = '0';
buff_fill_level := buff_fill_level -
(integer(nic_buffer_memory(buff_out_ptr)*real(bus_width_in_bytes)) + destination_address_in_bytes
+ source_address_in_bytes + length_in_bytes + checksum_in_bytes + descriptor_size_in_bytes);
-- (integer(nic_buffer_memory(buff_out_ptr)*real(bus_width_in_bytes)) + preamble_in_bytes + sof_in_bytes
-- + descriptor_size_in_bytes);
-- (integer(nic_buffer_memory(buff_out_ptr)*real(4)) + header_fields_length_in_octets + trailer_fields_length_in_octets);
occupancy := occupancy - 1;
-- Reset pointers to buffer empty state
buff_out_ptr := 0;
buff_in_ptr := 1;
next_transfer_state := idle;
elsif occupancy > 1
and occupancy < buffer_size
then wait until pciclk'event and pciclk = '0';
buff_fill_level := buff_fill_level -
(integer(nic_buffer_memory(buff_out_ptr)*real(bus_width_in_bytes)) + destination_address_in_bytes
+ source_address_in_bytes + length_in_bytes + checksum_in_bytes + descriptor_size_in_bytes);
-- (integer(nic_buffer_memory(buff_out_ptr)*real(bus_width_in_bytes)) + preamble_in_bytes + sof_in_bytes
-- + descriptor_size_in_bytes);
-- (integer(nic_buffer_memory(buff_out_ptr)*real(4)) + header_fields_length_in_octets + trailer_fields_length_in_octets);
occupancy := occupancy - 1;
inc(buff_out_ptr);
assert false
report "pkt_transfer_fsm: idle"
severity note;
next_transfer_state := idle;
end if;
end case;
transfer_state := next_transfer_state;
end process nic_to_memory_packet_transfer;
-- traffic_monitor_fsm: process
-- type traffic_monitor_state is (waiting_zero, waiting_one);
-- variable monitor_state : traffic_monitor_state := idle;
-- variable next_monitor_state : traffic_monitor_state := idle;
-- begin
-- wait until pciclk'event and pciclk = '1';
-- case monitor_state is
-- when waiting_zero =>
-- if transfer_start_req_value = '1'
-- then total_cycles_count := total_cycles_count + 1;
-- next_monitor_state := waiting_zero;
-- elsif transfer_start_req_value = '0'
-- then total_cycles_count := total_cycles_count + 1;
-- total_packets_plus_descriptors_size := total_packets_plus_descriptors_size
-- + ((pktsize - header_fields) + descriptor_size);
-- end if;
-- when waiting_one =>
-- if transfer_start_req_value = '0'
-- then total_cycles_count := total_cycles_count + 1;
-- next_monitor_state := waiting_one;
-- elsif transfer_start_req_value = '1'
-- total_cycles_count := total_cycles_count + 1;
-- next_monitor_state := waiting_zero;
-- end case;
-- transfer_state := next_transfer_state;
-- end process traffic_monitor_fsm;
-- transfer_end_driver: process
-- -- Auxiliary function for verifying buffer empty condition
-- function buffer_empty (in_ptr : in integer; out_ptr : in integer)
-- return boolean is
-- variable result : boolean := false;
-- begin
-- if in_ptr = out_ptr
-- then result := true;
-- end if;
-- return result;
-- end function buffer_empty;
-- begin
-- wait until transfer_end'event and transfer_end = '1';
-- wait until pciclk'event and pciclk = '0';
-- buff_fill_level := buff_fill_level - nic_buffer_memory(buff_out_ptr);
-- occupancy := occupancy - 1;
-- if buffer_empty(buff_in_ptr, buff_out_ptr)
-- then buff_out_ptr := 0;
-- else buff_out_ptr := buff_out_ptr + 1;
-- end if;
-- end process transfer_end_driver;
max_buff_fill_level_monitor: process
begin
wait until pciclk'event and pciclk = '1';
if buff_fill_level > max_buff_fill_level
then max_buff_fill_level := buff_fill_level;
end if;
end process max_buff_fill_level_monitor;
output_driver: process
begin
wait until pciclk'event and pciclk = '0';
buffer_fill_level_in_bytes <= buff_fill_level;
max_buffer_fill_level <= max_buff_fill_level;
dropped_packets_count <= total_dropped_packets;
buffer_size_in_data_units <= buffer_size;
end process output_driver;
-- print_out_statistics: process
-- file buffer_fill_level_output_file : text open write_mode is "buffer.out";
-- variable output_line : line;
-- variable clock_counter : integer := 1;
-- variable verbosity : integer := 1; **** Output verbosity management has not been implemented yet...
-- begin
-- case verbosity is
-- when 0 =>
-- wait for 1 ns;
-- when 1 =>
-- wait for 1 ns;
-- when 2 =>
-- wait for 1 ns;
-- end case;
--wait until pciclk'event and pciclk = '1';
-- wait until pciclk'event and pciclk = '0';
-- write(output_line, string'("clock "));
-- write(output_line, clock_counter);
-- write(output_line, string'(": "));
-- write(output_line, string'("FIFO size = "));
-- write(output_line, buffer_size);
-- write(output_line, string'(": "));
-- write(output_line, string'("occupancy = "));
-- -- write(output_line, occupancy);
-- write(output_line, string'("("));
-- write(output_line, real(occupancy)/real(buffer_size));
-- write(output_line, string'(" %) "));
-- write(output_line, string'(": "));
-- write(output_line, string'("fill level = "));
-- write(output_line, buff_fill_level);
-- write(output_line, string'(": "));
-- write(output_line, string'("max fill level = "));
-- write(output_line, max_buff_fill_level);
-- write(output_line, string'(": "));
-- write(output_line, string'("input pkt size = "));
-- write(output_line, input_packet_size);
-- write(output_line, string'(": "));
-- write(output_line, string'("total packet arrivals = "));
-- write(output_line, total_received_packets + total_dropped_packets);
-- write(output_line, string'(": "));
-- write(output_line, string'("received = "));
-- write(output_line, total_received_packets);
-- write(output_line, string'(": "));
-- write(output_line, string'("dropped = "));
-- write(output_line, total_dropped_packets);
-- writeline(buffer_fill_level_output_file, output_line);
-- clock_counter := clock_counter + 1;
--end process print_out_statistics;
end V1;
| gpl-3.0 | acdb5b6c448db901736e6f8e73e42ce0 | 0.628646 | 3.171082 | false | false | false | false |
hoglet67/CoPro6502 | src/T6502/T65_ALU.vhd | 1 | 8,522 | -- ****
-- T65(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 303 ost(ML) July 2014
-- ALU opcodes to vhdl types
-- Ver 300 Bugfixes by ehenciak added
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- 6502 compatible microprocessor core
--
-- Version : 0245
--
-- Copyright (c) 2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t65/
--
-- Limitations :
--
-- File history :
--
-- 0245 : First version
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T65_Pack.all;
entity T65_ALU is
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816
Op : in T_ALU_OP;
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
P_In : in std_logic_vector(7 downto 0);
P_Out : out std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0)
);
end T65_ALU;
architecture rtl of T65_ALU is
-- AddSub variables (temporary signals)
signal ADC_Z : std_logic;
signal ADC_C : std_logic;
signal ADC_V : std_logic;
signal ADC_N : std_logic;
signal ADC_Q : std_logic_vector(7 downto 0);
signal SBC_Z : std_logic;
signal SBC_C : std_logic;
signal SBC_V : std_logic;
signal SBC_N : std_logic;
signal SBC_Q : std_logic_vector(7 downto 0);
begin
process (P_In, BusA, BusB)
variable AL : unsigned(6 downto 0);
variable AH : unsigned(6 downto 0);
variable C : std_logic;
begin
AL := resize(unsigned(BusA(3 downto 0) & P_In(Flag_C)), 7) + resize(unsigned(BusB(3 downto 0) & "1"), 7);
AH := resize(unsigned(BusA(7 downto 4) & AL(5)), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7);
-- pragma translate_off
if is_x(std_logic_vector(AL)) then AL := "0000000"; end if;
if is_x(std_logic_vector(AH)) then AH := "0000000"; end if;
-- pragma translate_on
if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then
ADC_Z <= '1';
else
ADC_Z <= '0';
end if;
if AL(5 downto 1) > 9 and P_In(Flag_D) = '1' then
AL(6 downto 1) := AL(6 downto 1) + 6;
end if;
C := AL(6) or AL(5);
AH := resize(unsigned(BusA(7 downto 4) & C), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7);
ADC_N <= AH(4);
ADC_V <= (AH(4) xor BusA(7)) and not (BusA(7) xor BusB(7));
-- pragma translate_off
if is_x(std_logic_vector(AH)) then AH := "0000000"; end if;
-- pragma translate_on
if AH(5 downto 1) > 9 and P_In(Flag_D) = '1' then
AH(6 downto 1) := AH(6 downto 1) + 6;
end if;
ADC_C <= AH(6) or AH(5);
ADC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));
end process;
process (Op, P_In, BusA, BusB)
variable AL : unsigned(6 downto 0);
variable AH : unsigned(5 downto 0);
variable C : std_logic;
variable CT : std_logic;
begin
CT:='0';
if( Op=ALU_OP_AND or --"0001" These OpCodes used to have LSB set
Op=ALU_OP_ADC or --"0011"
Op=ALU_OP_EQ2 or --"0101"
Op=ALU_OP_SBC or --"0111"
Op=ALU_OP_ROL or --"1001"
Op=ALU_OP_ROR or --"1011"
Op=ALU_OP_EQ3 or --"1101"
Op=ALU_OP_INC --"1111"
) then
CT:='1';
end if;
C := P_In(Flag_C) or not CT;--was: or not Op(0);
AL := resize(unsigned(BusA(3 downto 0) & C), 7) - resize(unsigned(BusB(3 downto 0) & "1"), 6);
AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(5)), 6);
-- pragma translate_off
if is_x(std_logic_vector(AL)) then AL := "0000000"; end if;
if is_x(std_logic_vector(AH)) then AH := "000000"; end if;
-- pragma translate_on
if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then
SBC_Z <= '1';
else
SBC_Z <= '0';
end if;
SBC_C <= not AH(5);
SBC_V <= (AH(4) xor BusA(7)) and (BusA(7) xor BusB(7));
SBC_N <= AH(4);
if P_In(Flag_D) = '1' then
if AL(5) = '1' then
AL(5 downto 1) := AL(5 downto 1) - 6;
end if;
AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(6)), 6);
if AH(5) = '1' then
AH(5 downto 1) := AH(5 downto 1) - 6;
end if;
end if;
SBC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));
end process;
process (Op, P_In, BusA, BusB,
ADC_Z, ADC_C, ADC_V, ADC_N, ADC_Q,
SBC_Z, SBC_C, SBC_V, SBC_N, SBC_Q)
variable Q_t : std_logic_vector(7 downto 0);
begin
-- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC
-- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC
P_Out <= P_In;
Q_t := BusA;
case Op is
when ALU_OP_OR=>
Q_t := BusA or BusB;
when ALU_OP_AND=>
Q_t := BusA and BusB;
when ALU_OP_EOR=>
Q_t := BusA xor BusB;
when ALU_OP_ADC=>
P_Out(Flag_V) <= ADC_V;
P_Out(Flag_C) <= ADC_C;
Q_t := ADC_Q;
when ALU_OP_EQ2|ALU_OP_EQ3=>
-- LDA
when ALU_OP_CMP=>
P_Out(Flag_C) <= SBC_C;
when ALU_OP_SBC=>
P_Out(Flag_V) <= SBC_V;
P_Out(Flag_C) <= SBC_C;
Q_t := SBC_Q;
when ALU_OP_ASL=>
Q_t := BusA(6 downto 0) & "0";
P_Out(Flag_C) <= BusA(7);
when ALU_OP_ROL=>
Q_t := BusA(6 downto 0) & P_In(Flag_C);
P_Out(Flag_C) <= BusA(7);
when ALU_OP_LSR=>
Q_t := "0" & BusA(7 downto 1);
P_Out(Flag_C) <= BusA(0);
when ALU_OP_ROR=>
Q_t := P_In(Flag_C) & BusA(7 downto 1);
P_Out(Flag_C) <= BusA(0);
when ALU_OP_BIT=>
P_Out(Flag_V) <= BusB(6);
when ALU_OP_DEC=>
Q_t := std_logic_vector(unsigned(BusA) - 1);
when ALU_OP_INC=>
Q_t := std_logic_vector(unsigned(BusA) + 1);
when others =>
--EQ1,EQ2,EQ3 passes BusA to Q_t
end case;
case Op is
when ALU_OP_ADC=>
P_Out(Flag_N) <= ADC_N;
P_Out(Flag_Z) <= ADC_Z;
when ALU_OP_CMP|ALU_OP_SBC=>
P_Out(Flag_N) <= SBC_N;
P_Out(Flag_Z) <= SBC_Z;
when ALU_OP_EQ1=>
when ALU_OP_BIT=>
P_Out(Flag_N) <= BusB(7);
if (BusA and BusB) = "00000000" then
P_Out(Flag_Z) <= '1';
else
P_Out(Flag_Z) <= '0';
end if;
when others =>
P_Out(Flag_N) <= Q_t(7);
if Q_t = "00000000" then
P_Out(Flag_Z) <= '1';
else
P_Out(Flag_Z) <= '0';
end if;
end case;
Q <= Q_t;
end process;
end;
| gpl-3.0 | 0f6f045841e4f259b960e046706de790 | 0.561723 | 3.070991 | false | false | false | false |
hoglet67/CoPro6502 | src/LX9Co_CoProZ80.vhd | 1 | 7,253 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity LX9CoProZ80 is
port (
-- GOP Signals
fastclk : in std_logic;
test : inout std_logic_vector(8 downto 1);
sw : in std_logic_vector(3 downto 0);
-- Tube signals (use 16 out of 22 DIL pins)
h_phi2 : in std_logic; -- 1,2,12,21,23 are global clocks
h_addr : in std_logic_vector(2 downto 0);
h_data : inout std_logic_vector(7 downto 0);
h_rdnw : in std_logic;
h_cs_b : in std_logic;
h_rst_b : in std_logic;
h_irq_b : inout std_logic;
-- Ram Signals
ram_ub_b : out std_logic;
ram_lb_b : out std_logic;
ram_cs : out std_logic;
ram_oe : out std_logic;
ram_wr : out std_logic;
ram_addr : out std_logic_vector (18 downto 0);
ram_data : inout std_logic_vector (7 downto 0)
);
end LX9CoProZ80;
architecture BEHAVIORAL of LX9CoProZ80 is
-------------------------------------------------
-- clock and reset signals
-------------------------------------------------
signal cpu_clk : std_logic;
signal cpu_clken : std_logic;
signal bootmode : std_logic;
signal RSTn : std_logic;
signal RSTn_sync : std_logic;
-------------------------------------------------
-- parasite signals
-------------------------------------------------
signal p_cs_b : std_logic;
signal tube_cs_b : std_logic;
signal p_data_out : std_logic_vector (7 downto 0);
-------------------------------------------------
-- ram/rom signals
-------------------------------------------------
signal ram_cs_b : std_logic;
signal ram_oe_int : std_logic;
signal ram_wr_int : std_logic;
signal rom_cs_b : std_logic;
signal rom_data_out : std_logic_vector (7 downto 0);
-------------------------------------------------
-- cpu signals
-------------------------------------------------
signal cpu_rd_n : std_logic;
signal cpu_wr_n : std_logic;
signal cpu_iorq_n : std_logic;
signal cpu_mreq_n : std_logic;
signal cpu_m1_n : std_logic;
signal cpu_addr : std_logic_vector (15 downto 0);
signal cpu_din : std_logic_vector (7 downto 0);
signal cpu_dout : std_logic_vector (7 downto 0);
signal cpu_IRQ_n : std_logic;
signal cpu_NMI_n : std_logic;
signal cpu_IRQ_n_sync : std_logic;
signal cpu_NMI_n_sync : std_logic;
begin
---------------------------------------------------------------------
-- instantiated components
---------------------------------------------------------------------
inst_ICAP_config : entity work.ICAP_config port map (
fastclk => fastclk,
sw_in => sw,
sw_out => open,
h_addr => h_addr,
h_cs_b => h_cs_b,
h_data => h_data,
h_phi2 => h_phi2,
h_rdnw => h_rdnw,
h_rst_b => h_rst_b
);
inst_dcm_32_16 : entity work.dcm_32_16 port map (
CLKIN_IN => fastclk,
CLK0_OUT => cpu_clk,
CLK0_OUT1 => open,
CLK2X_OUT => open);
inst_tuberom : entity work.tuberom_z80 port map (
CLK => cpu_clk,
ADDR => cpu_addr(11 downto 0),
DATA => rom_data_out
);
inst_Z80 : entity work.T80se port map (
RESET_n => RSTn_sync,
CLK_n => cpu_clk,
CLKEN => cpu_clken,
WAIT_n => '1',
INT_n => cpu_IRQ_n_sync,
NMI_n => cpu_NMI_n_sync,
BUSRQ_n => '1',
M1_n => cpu_m1_n,
MREQ_n => cpu_mreq_n,
IORQ_n => cpu_iorq_n,
RD_n => cpu_rd_n,
WR_n => cpu_wr_n,
RFSH_n => open,
HALT_n => open,
BUSAK_n => open,
A => cpu_addr,
DI => cpu_din,
DO => cpu_dout
);
inst_tube: entity work.tube port map (
h_addr => h_addr,
h_cs_b => h_cs_b,
h_data => h_data,
h_phi2 => h_phi2,
h_rdnw => h_rdnw,
h_rst_b => h_rst_b,
h_irq_b => h_irq_b,
p_addr => cpu_addr(2 downto 0),
p_cs_b => tube_cs_b,
p_data_in => cpu_dout,
p_data_out => p_data_out,
p_phi2 => cpu_clk,
p_rdnw => cpu_wr_n,
p_rst_b => RSTn,
p_nmi_b => cpu_NMI_n,
p_irq_b => cpu_IRQ_n
);
tube_cs_b <= not ((not p_cs_b) and cpu_clken);
p_cs_b <= '0' when cpu_mreq_n = '1' and cpu_iorq_n = '0' and cpu_addr(7 downto 3) = "00000" else '1';
rom_cs_b <= '0' when cpu_mreq_n = '0' and cpu_rd_n = '0' and bootmode = '1' else '1';
ram_cs_b <= '0' when cpu_mreq_n = '0' and rom_cs_b = '1' else '1';
cpu_din <=
p_data_out when p_cs_b = '0' else
rom_data_out when rom_cs_b = '0' else
ram_data when ram_cs_b = '0' else
x"fe";
ram_ub_b <= '0';
ram_lb_b <= '0';
ram_cs <= ram_cs_b;
ram_oe_int <= not ((not ram_cs_b) and (not cpu_rd_n));
ram_oe <= ram_oe_int;
ram_wr_int <= not ((not ram_cs_b) and (not cpu_wr_n));
ram_wr <= ram_wr_int;
ram_addr <= "000" & cpu_addr;
ram_data <= cpu_dout when cpu_wr_n = '0' else "ZZZZZZZZ";
--------------------------------------------------------
-- test signals
--------------------------------------------------------
-- default to hi-impedence, to avoid conflicts with
-- a Raspberry Pi connected to the test connector
test <= (others => 'Z');
--------------------------------------------------------
-- boot mode generator
--------------------------------------------------------
boot_gen : process(cpu_clk, RSTn_sync)
begin
if RSTn_sync = '0' then
bootmode <= '1';
elsif rising_edge(cpu_clk) then
if (cpu_mreq_n = '0' and cpu_m1_n = '0') then
if (cpu_addr = x"0066") then
bootmode <= '1';
elsif cpu_addr(15) = '1' then
bootmode <= '0';
end if;
end if;
end if;
end process;
--------------------------------------------------------
-- synchronize interrupts etc into Z80 core
--------------------------------------------------------
sync_gen : process(cpu_clk, RSTn_sync)
begin
if RSTn_sync = '0' then
cpu_NMI_n_sync <= '1';
cpu_IRQ_n_sync <= '1';
elsif rising_edge(cpu_clk) then
if (cpu_clken = '1') then
cpu_NMI_n_sync <= cpu_NMI_n;
cpu_IRQ_n_sync <= cpu_IRQ_n;
end if;
end if;
end process;
--------------------------------------------------------
-- clock enable generator
--------------------------------------------------------
clk_gen : process(cpu_clk)
begin
if rising_edge(cpu_clk) then
cpu_clken <= not cpu_clken;
RSTn_sync <= RSTn;
end if;
end process;
end BEHAVIORAL;
| gpl-3.0 | 59df9bf1ea4c1d954f46eb40ab19fcab | 0.419688 | 3.462053 | false | false | false | false |
pwsoft/fpga_examples | rtl/general/gen_bin2gray.vhd | 1 | 2,001 | -- -----------------------------------------------------------------------
--
-- Syntiac's generic VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2012 by Peter Wendrich ([email protected])
-- http://www.syntiac.com/fpga64.html
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
--
-- gen_bin2gray.vhd
--
-- -----------------------------------------------------------------------
--
-- Convert binary to gray-code
--
-- -----------------------------------------------------------------------
-- d - binary input
-- q - gray-code output
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- -----------------------------------------------------------------------
entity gen_bin2gray is
generic (
bits : integer := 4
);
port (
d : in unsigned(bits-1 downto 0) := (others => '0');
q : out unsigned(bits-1 downto 0)
);
end entity;
-- -----------------------------------------------------------------------
architecture rtl of gen_bin2gray is
begin
process(d)
begin
for i in 0 to bits-1 loop
if i = (bits-1) then
q(i) <= d(i);
else
q(i) <= d(i) xor d(i+1);
end if;
end loop;
end process;
end architecture;
| lgpl-2.1 | d1d1d5309c97282cfa9b5585d2efea2f | 0.47926 | 4.3125 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/grdware/mul_dware.vhd | 1 | 4,125 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: misc
-- File: mul_dware.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Dware multipliers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library Dware;
use DWARE.DWpackages.all;
use DWARE.DW_Foundation_comp_arith.all;
entity mul_dw is
generic (
a_width : positive := 2; -- multiplier word width
b_width : positive := 2; -- multiplicand word width
num_stages : positive := 2; -- number of pipeline stages
stall_mode : natural range 0 to 1 := 1 -- '0': non-stallable; '1': stallable
);
port(a : in std_logic_vector(a_width-1 downto 0);
b : in std_logic_vector(b_width-1 downto 0);
clk : in std_logic;
en : in std_logic;
sign : in std_logic;
product : out std_logic_vector(a_width+b_width-1 downto 0));
end;
architecture rtl of mul_dw is
component DW02_mult
generic( A_width: NATURAL; -- multiplier wordlength
B_width: NATURAL); -- multiplicand wordlength
port(A : in std_logic_vector(A_width-1 downto 0);
B : in std_logic_vector(B_width-1 downto 0);
TC : in std_logic; -- signed -> '1', unsigned -> '0'
PRODUCT : out std_logic_vector(A_width+B_width-1 downto 0));
end component;
signal gnd : std_ulogic;
begin
gnd <= '0';
np : if num_stages = 1 generate
u0 : DW02_mult
generic map ( a_width => a_width, b_width => b_width)
port map (a => a, b => b, TC => sign, product => product);
end generate;
pipe : if num_stages > 1 generate
u0 : DW_mult_pipe
generic map ( a_width => a_width, b_width => b_width,
num_stages => num_stages, stall_mode => stall_mode, rst_mode => 0)
port map (a => a, b => b, TC => sign, clk => clk, product => product,
rst_n => gnd, en => en);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library Dware;
use DWARE.DWpackages.all;
use DWARE.DW_Foundation_comp_arith.all;
entity dw_mul_61x61 is
port(A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end;
architecture rtl of dw_mul_61x61 is
signal gnd : std_ulogic;
signal pin, p : std_logic_vector(121 downto 0);
begin
gnd <= '0';
-- u0 : DW02_mult_2_stage
-- generic map ( A_width => A'length, B_width => B'length )
-- port map ( A => A, B => B, TC => gnd, CLK => CLK, PRODUCT => pin );
u0 : DW_mult_pipe
generic map ( a_width => 61, b_width => 61,
num_stages => 2, stall_mode => 0, rst_mode => 0)
port map (a => a, b => b, TC => gnd, clk => clk, product => pin,
rst_n => gnd, en => gnd);
reg0 : process(CLK)
begin
if rising_edge(CLK) then
p <= pin;
end if;
end process;
PRODUCT <= p;
end;
| gpl-3.0 | 5d50b0b2179054cb7d01a65f1df4b951 | 0.566545 | 3.552972 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-ztex-ufm-115/testbench.vhd | 1 | 7,520 | -------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2011 Aeroflex Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
use work.debug.all;
use work.config.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sdramfile : string := "ram.srec"; -- sdram contents
constant lresp : boolean := false;
signal reset : std_ulogic := '1';
signal clk48 : std_ulogic := '0';
signal errorn : std_logic;
signal mcb3_dram_dq : std_logic_vector(15 downto 0);
signal mcb3_rzq : std_logic;
signal mcb3_zio : std_logic;
signal mcb3_dram_dqs : std_logic_vector(1 downto 0);
signal mcb3_dram_dqs_n : std_logic_vector(1 downto 0);
signal mcb3_dram_a : std_logic_vector(12 downto 0);
signal mcb3_dram_ba : std_logic_vector(2 downto 0);
signal mcb3_dram_cke : std_logic;
signal mcb3_dram_ras_n : std_logic;
signal mcb3_dram_cas_n : std_logic;
signal mcb3_dram_we_n : std_logic;
signal mcb3_dram_dm : std_logic_vector(1 downto 0);
signal mcb3_dram_udm : std_logic;
signal mcb3_dram_ck : std_logic;
signal mcb3_dram_ck_n : std_logic;
signal dsubre : std_ulogic; -- Debug Unit break (connect to button)
signal dsuact : std_ulogic; -- Debug Unit break (connect to button)
signal dsurx : std_ulogic;
signal dsutx : std_ulogic;
signal rxd1 : std_ulogic;
signal txd1 : std_ulogic;
signal sd_dat : std_logic;
signal sd_cmd : std_logic;
signal sd_sck : std_logic;
signal sd_dat3 : std_logic;
signal csb : std_logic := '0'; -- dummy
begin
-- clock and reset
clk48 <= not clk48 after 10.417 ns;
reset <= '1', '0' after 300 ns;
dsubre <= '0';
sd_dat <= 'H';
sd_cmd <= 'H';
sd_sck <= 'H';
d3 : entity work.leon3mp
generic map (fabtech, memtech, padtech, clktech, disas, dbguart, pclow)
port map (
reset => reset,
clk48 => clk48,
-- Processor error output
errorn => errorn,
-- DDR SDRAM
mcb3_dram_dq => mcb3_dram_dq,
mcb3_rzq => mcb3_rzq,
mcb3_zio => mcb3_zio,
mcb3_dram_udqs => mcb3_dram_dqs(1),
mcb3_dram_udqs_n => mcb3_dram_dqs_n(1),
mcb3_dram_dqs => mcb3_dram_dqs(0),
mcb3_dram_dqs_n => mcb3_dram_dqs_n(0),
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_dm => mcb3_dram_dm(0),
mcb3_dram_udm => mcb3_dram_dm(1),
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
-- Debug support unit
dsubre => dsubre,
dsuact => dsuact,
-- AHB UART (debug link)
dsurx => dsurx,
dsutx => dsutx,
-- UART
rxd1 => rxd1,
txd1 => txd1,
-- SD card
sd_dat => sd_dat,
sd_cmd => sd_cmd,
sd_sck => sd_sck,
sd_dat3 => sd_dat3
);
migddr2mem : if (CFG_MIG_DDR2 = 1) generate
ddr0 : ddr2ram
generic map(width => 16, abits => 13, babits => 3, colbits => 10, rowbits => 13,
implbanks => 1, fname => sdramfile, speedbin=>9, density => 2,
lddelay => 115 us)
port map (ck => mcb3_dram_ck, ckn => mcb3_dram_ck_n, cke => mcb3_dram_cke, csn => csb,
odt => '0', rasn => mcb3_dram_ras_n, casn => mcb3_dram_cas_n, wen => mcb3_dram_we_n,
dm => mcb3_dram_dm, ba => mcb3_dram_ba, a => mcb3_dram_a(12 downto 0),
dq => mcb3_dram_dq, dqs => mcb3_dram_dqs, dqsn => mcb3_dram_dqs_n);
end generate;
--spimem0: if CFG_SPIMCTRL = 1 generate
-- s0 : spi_flash generic map (ftype => 4, debug => 0, fname => promfile,
-- readcmd => CFG_SPIMCTRL_READCMD,
-- dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
-- dualoutput => 0) -- Dual output is not supported in this design
-- port map (spi_clk, spi_mosi, data(24), spi_sel_n);
--end generate spimem0;
iuerr : process
begin
wait for 5 us;
assert (to_X01(errorn) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure;
end process;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#ef#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
--
-- txc(dsutx, 16#80#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end;
| gpl-3.0 | b393b9882a07b26e995a05ae13182155 | 0.545213 | 3.331856 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-digilent-xup/leon3mp.vhd | 1 | 22,639 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.net.all;
use gaisler.jtag.all;
-- pragma translate_off
use gaisler.sim.all;
-- pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
sysace_clk : in std_ulogic;
errorn : out std_ulogic;
dsuen : in std_ulogic;
dsubre : in std_ulogic;
dsuact : out std_ulogic;
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb : in std_logic;
ddr_clk_fb_out : out std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (7 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (7 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (63 downto 0); -- ddr data
rxd : in std_ulogic;
txd : out std_ulogic;
led_rx : out std_ulogic;
led_tx : out std_ulogic;
-- gpio : inout std_logic_vector(31 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
emdc : out std_ulogic;
eresetn : out std_ulogic;
etx_slew : out std_logic_vector(1 downto 0);
ps2clk : inout std_logic_vector(1 downto 0);
ps2data : inout std_logic_vector(1 downto 0);
vid_clock : out std_ulogic;
vid_blankn : out std_ulogic;
vid_syncn : out std_ulogic;
vid_hsync : out std_ulogic;
vid_vsync : out std_ulogic;
vid_r : out std_logic_vector(7 downto 0);
vid_g : out std_logic_vector(7 downto 0);
vid_b : out std_logic_vector(7 downto 0);
cf_mpa : out std_logic_vector(6 downto 0);
cf_mpd : inout std_logic_vector(15 downto 0);
cf_mp_ce_z : out std_ulogic;
cf_mp_oe_z : out std_ulogic;
cf_mp_we_z : out std_ulogic;
cf_mpirq : in std_ulogic
);
end;
architecture rtl of leon3mp is
signal gpio : std_logic_vector(31 downto 0); -- I/O port
constant maxahbm : integer := NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, pciclk, ddrlock : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal lclk, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal rxd1 : std_logic;
signal txd1 : std_logic;
signal duart, rserrx, rsertx, rdsuen, ldsuen : std_logic;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal kbdi : ps2_in_type;
signal kbdo : ps2_out_type;
signal moui : ps2_in_type;
signal mouo : ps2_out_type;
signal vgao : apbvga_out_type;
signal clkace : std_ulogic;
signal acei : gracectrl_in_type;
signal aceo : gracectrl_out_type;
signal ldsubre, lresetn, lock, clkml, clk1x : std_ulogic;
constant BOARD_FREQ : integer := 100000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := 1;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute keep of ddrlock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute syn_keep of ddrlock : signal is true;
attribute syn_preserve of ddrlock : signal is true;
signal dac_clk,video_clk, clkvga : std_logic; -- Signals to vgaclock.
signal clk_sel : std_logic_vector(1 downto 0);
signal clkval : std_logic_vector(1 downto 0);
attribute keep of clkvga : signal is true;
attribute syn_keep of clkvga : signal is true;
attribute syn_preserve of clkvga : signal is true;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
lock <= ddrlock and cgo.clklock;
sysace_clk_pad : clkpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (sysace_clk, clkace);
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
clkgen0 : clkgen -- clock generator
generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, pciclk, clkm, open, open, open, pciclk, cgi, cgo, open, clk1x);
resetn_pad : inpad generic map (tech => padtech) port map (resetn, lresetn);
rst0 : rstgen -- reset generator
port map (lresetn, clkm, lock, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, ldsubre);
dsui.break <= not ldsubre;
ndsuact <= not dsuo.active;
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, ndsuact);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 4)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
dui.rxd <= rxd when dsuen = '1' else '1';
end generate;
led_rx <= rxd;
led_tx <= duo.txd when dsuen = '1' else u1o.txd;
txd <= duo.txd when dsuen = '1' else u1o.txd;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
-- DDR RAM
ddrsp0 : if (CFG_DDRSP /= 0) generate
ddr0 : ddrspa generic map (
fabtech => fabtech, memtech => 0, ddrbits => 64,
hindex => 3, haddr => 16#400#, hmask => 16#C00#, ioaddr => 1,
pwron => CFG_DDRSP_INIT, MHz => BOARD_FREQ/1000,
clkmul => CFG_DDRSP_FREQ/5, clkdiv => 20, col => CFG_DDRSP_COL,
Mbyte => CFG_DDRSP_SIZE, ahbfreq => CPU_FREQ/1000,
rskew => CFG_DDRSP_RSKEW )
port map (lresetn, rstn, clk1x, clkm, ddrlock, clkml, clkml,
ahbsi, ahbso(3),
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq);
end generate;
noddr : if (CFG_DDRSP = 0) generate ddrlock <= '1'; end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd; u1i.ctsn <= '0'; u1i.extclk <= '0'; --txd1 <= u1o.txd;
end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti <= gpti_dhalt_drive(dsuo.tstop);
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
kbd : if CFG_KBD_ENABLE /= 0 generate
ps21 : apbps2 generic map(pindex => 7, paddr => 7, pirq => 4)
port map(rstn, clkm, apbi, apbo(7), moui, mouo);
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
end generate;
kbdclk_pad : iopad generic map (tech => padtech)
port map (ps2clk(0),kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
kbdata_pad : iopad generic map (tech => padtech)
port map (ps2data(0), kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
mouclk_pad : iopad generic map (tech => padtech)
port map (ps2clk(1),mouo.ps2_clk_o, mouo.ps2_clk_oe, moui.ps2_clk_i);
mouata_pad : iopad generic map (tech => padtech)
port map (ps2data(1), mouo.ps2_data_o, mouo.ps2_data_oe, moui.ps2_data_i);
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, clkm, apbi, apbo(6), vgao);
video_clock_pad : outpad generic map ( tech => padtech)
port map (vid_clock, clkm);
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG, clk0 => 40000,
clk1 => 20000, clk2 => CFG_CLKDIV*10000/CFG_CLKMUL, burstlen => 5)
port map(rstn, clkm, clkvga, apbi, apbo(6), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), clk_sel);
clkdiv : process(clk1x, rstn)
begin
if rstn = '0' then clkval <= "00";
elsif rising_edge(clk1x) then
clkval <= clkval + 1;
end if;
end process;
video_clk <= clkval(1) when clk_sel = "00" else clkval(0) when clk_sel = "01" else clkm;
b1 : techbuf generic map (2, virtex2) port map (video_clk, clkvga);
dac_clk <= not video_clk;
video_clock_pad : outpad generic map ( tech => padtech)
port map (vid_clock, clkvga);
end generate;
novga : if (CFG_VGA_ENABLE = 0 and CFG_SVGA_ENABLE = 0) generate
apbo(6) <= apb_none; vgao <= vgao_none;
end generate;
vga_pads : if (CFG_VGA_ENABLE /= 0 or CFG_SVGA_ENABLE /=0) generate
blank_pad : outpad generic map (tech => padtech)
port map (vid_blankn, vgao.blank);
comp_sync_pad : outpad generic map (tech => padtech)
port map (vid_syncn, vgao.comp_sync);
vert_sync_pad : outpad generic map (tech => padtech)
port map (vid_vsync, vgao.vsync);
horiz_sync_pad : outpad generic map (tech => padtech)
port map (vid_hsync, vgao.hsync);
video_out_r_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_r, vgao.video_out_r);
video_out_g_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_g, vgao.video_out_g);
video_out_b_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_b, vgao.video_out_b);
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : greth generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 11, paddr => 11, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE), apbi => apbi,
apbo => apbo(11), ethi => ethi, etho => etho);
end generate;
ethpads : if (CFG_GRETH = 1) generate -- eth pads
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
end generate;
etx_slew <= "00";
eresetn <= rstn;
----------------------------------------------------------------------
--- System ACE I/F Controller ---------------------------------------
----------------------------------------------------------------------
grace: if CFG_GRACECTRL = 1 generate
grace0 : gracectrl generic map (hindex => 5, hirq => 6,
haddr => 16#003#, hmask => 16#fff#, split => CFG_SPLIT)
port map (rstn, clkm, clkace, ahbsi, ahbso(5), acei, aceo);
end generate;
nograce: if CFG_GRACECTRL = 0 generate
aceo.addr <= (others => '0'); aceo.cen <= '1'; aceo.do <= (others => '0');
aceo.doen <= '1'; aceo.oen <= '1'; aceo.wen <= '0';
end generate nograce;
cf_mpa_pads : outpadv generic map
(width => 7, tech => padtech, level => cmos, voltage => x25v)
port map (cf_mpa, aceo.addr);
cf_mp_ce_z_pad : outpad generic map
(tech => padtech, level => cmos, voltage => x25v)
port map (cf_mp_ce_z, aceo.cen);
cf_mpd_pads : iopadv generic map
(tech => padtech, width => 16, level => cmos, voltage => x25v)
port map (cf_mpd, aceo.do, aceo.doen, acei.di);
cf_mp_oe_z_pad : outpad generic map
(tech => padtech, level => cmos, voltage => x25v)
port map (cf_mp_oe_z, aceo.oen);
cf_mp_we_z_pad : outpad generic map
(tech => padtech, level => cmos, voltage => x25v)
port map (cf_mp_we_z, aceo.wen);
cf_mpirq_pad : inpad generic map
(tech => padtech, level => cmos, voltage => x25v)
port map (cf_mpirq, acei.irq);
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 0, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(0));
end generate;
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0 : ahbrep generic map (hindex => 4, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(4));
-- pragma translate_on
-----------------------------------------------------------------------
--- Debug ----------------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
-- dma0 : ahbdma
-- generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+1,
-- pindex => 13, paddr => 13, dbuf => 6)
-- port map (rstn, clkm, apbi, apbo(13), ahbmi,
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+1));
-- pragma translate_on
--
-- at0 : ahbtrace
-- generic map ( hindex => 7, ioaddr => 16#200#, iomask => 16#E00#,
-- tech => memtech, irq => 0, kbytes => 8)
-- port map ( rstn, clkm, ahbmi, ahbsi, ahbso(7));
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Digilent Virtex2-Pro XUP Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-3.0 | fbd491c9380db841e1c4b48e19109f12 | 0.555634 | 3.588366 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-ztex-ufm-111/config.vhd | 1 | 5,992 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := spartan6;
constant CFG_MEMTECH : integer := spartan6;
constant CFG_PADTECH : integer := spartan6;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := spartan6;
constant CFG_CLKMUL : integer := (3);
constant CFG_CLKDIV : integer := (2);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (2);
constant CFG_NOTAG : integer := 1;
constant CFG_NWP : integer := (0);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 1;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 8;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 0*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 0 + 64*0;
constant CFG_ATBSZ : integer := 0;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 1;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Xilinx MIG
constant CFG_MIG_DDR2 : integer := 1;
constant CFG_MIG_RANKS : integer := (1);
constant CFG_MIG_COLBITS : integer := (10);
constant CFG_MIG_ROWBITS : integer := (13);
constant CFG_MIG_BANKBITS: integer := (2);
constant CFG_MIG_HMASK : integer := 16#FC0#;
-- AHB ROM
constant CFG_AHBROMEN : integer := 1;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#100#;
constant CFG_ROMMASK : integer := 16#E00# + 16#100#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 1;
constant CFG_AHBRSZ : integer := 4;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 0;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := 1;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 1;
constant CFG_SPICTRL_NUM : integer := (1);
constant CFG_SPICTRL_SLVS : integer := (1);
constant CFG_SPICTRL_FIFO : integer := (2);
constant CFG_SPICTRL_SLVREG : integer := 1;
constant CFG_SPICTRL_ODMODE : integer := 1;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 0;
constant CFG_SPICTRL_MAXWLEN : integer := (0);
constant CFG_SPICTRL_SYNCRAM : integer := 0;
constant CFG_SPICTRL_FT : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-3.0 | e775876c9f6b3eabe637938f49beb270 | 0.644025 | 3.649208 | false | false | false | false |
GLADICOS/SPACEWIRESYSTEMC | rtl/RTL_SL/spwrecv.vhd | 2 | 9,394 | --
-- SpaceWire Receiver
--
-- This entity decodes the sequence of incoming data bits into tokens.
-- Data bits are passed to this entity from the Receiver Front-end
-- in groups of rxchunk bits at a time.
--
-- The bitrate of the incoming SpaceWire signal must be strictly less
-- than rxchunk times the system clock frequency.
--
library ieee;
use ieee.std_logic_1164.all, ieee.numeric_std.all;
use work.spwpkg.all;
entity spwrecv is
generic (
-- Disconnect timeout, expressed in system clock cycles.
-- Should be 850 ns (727 ns .. 1000 ns) according to the standard.
disconnect_time: integer range 1 to 255;
-- Nr of bits sampled per system clock.
rxchunk: integer range 1 to 4
);
port (
-- System clock.
clk: in std_logic;
-- High to enable receiver; low to disable and reset receiver.
rxen: in std_logic;
-- Output signals to spwlink.
recvo: out spw_recv_out_type;
-- High if there has been recent activity on the input lines.
inact: in std_logic;
-- High if inbits contains a valid group of received bits.
inbvalid: in std_logic;
-- Received bits from receiver front-end.
inbits: in std_logic_vector(rxchunk-1 downto 0)
);
end entity spwrecv;
architecture spwrecv_arch of spwrecv is
-- registers
type regs_type is record
-- receiver state
bit_seen: std_ulogic; -- got a bit transition
null_seen: std_ulogic; -- got a NULL token
-- input shift register
bitshift: std_logic_vector(8 downto 0);
bitcnt: std_logic_vector(9 downto 0); -- one-hot counter
-- parity flag
parity: std_ulogic;
-- decoding
control: std_ulogic; -- next code is control code
escaped: std_ulogic; -- last code was ESC
-- output registers
gotfct: std_ulogic;
tick_out: std_ulogic;
rxchar: std_ulogic;
rxflag: std_ulogic;
timereg: std_logic_vector(7 downto 0);
datareg: std_logic_vector(7 downto 0);
-- disconnect timer
disccnt: unsigned(7 downto 0);
-- error flags
errpar: std_ulogic;
erresc: std_ulogic;
end record;
-- Initial state
constant regs_reset: regs_type := (
bit_seen => '0',
null_seen => '0',
bitshift => (others => '1'),
bitcnt => (others => '0'),
parity => '0',
control => '0',
escaped => '0',
gotfct => '0',
tick_out => '0',
rxchar => '0',
rxflag => '0',
timereg => (others => '0'),
datareg => (others => '0'),
disccnt => "00000000",
errpar => '0',
erresc => '0' );
-- registers
signal r: regs_type := regs_reset;
signal rin: regs_type;
begin
-- combinatorial process
process (r, rxen, inact, inbvalid, inbits)
variable v: regs_type;
variable v_inbit: std_ulogic;
begin
v := r;
v_inbit := '0';
-- disconnect timer
if inact = '1' then
-- activity on input; reset timer
v.disccnt := to_unsigned(disconnect_time, v.disccnt'length);
elsif r.disccnt /= 0 then
-- count down
v.disccnt := r.disccnt - 1;
end if;
-- assume no new token
v.gotfct := '0';
v.tick_out := '0';
v.rxchar := '0';
if inbvalid = '1' then
-- process incoming bits
for i in 0 to rxchunk-1 loop
v_inbit := inbits(i);
-- got a bit transition
v.bit_seen := '1';
if v.bitcnt(0) = '1' then
-- received new token
-- note that this will not happen before null_seen='1'
if (v.parity xor v_inbit) = '0' then
-- Parity check failed.
v.errpar := '1';
else
if v.control = '1' then
-- received control code
case v.bitshift(7 downto 6) is
when "00" => -- FCT or NULL
v.gotfct := not r.escaped;
v.escaped := '0';
when "10" => -- EOP
if r.escaped = '1' then
v.erresc := '1';
end if;
v.escaped := '0';
v.rxchar := not r.escaped;
v.rxflag := '1';
v.datareg := "00000000";
when "01" => -- EEP
if r.escaped = '1' then
v.erresc := '1';
end if;
v.escaped := '0';
v.rxchar := not r.escaped;
v.rxflag := '1';
v.datareg := "00000001";
when others => -- ESC
if r.escaped = '1' then
v.erresc := '1';
end if;
v.escaped := '1';
end case;
else
-- received 8-bit character
if r.escaped = '1' then
-- received Time-Code
v.tick_out := '1';
v.timereg := v.bitshift(7 downto 0);
else
-- received data character
v.rxflag := '0';
v.rxchar := '1';
v.datareg := v.bitshift(7 downto 0);
end if;
v.escaped := '0';
end if;
end if;
-- prepare for next code
v.parity := '0';
v.control := v_inbit;
if v_inbit = '1' then
-- next word will be control code.
v.bitcnt := (3 => '1', others => '0');
else
-- next word will be a data byte.
v.bitcnt := (9 => '1', others => '0');
end if;
else
-- wait until next code is completely received;
-- accumulate parity
v.bitcnt := '0' & v.bitcnt(9 downto 1);
v.parity := v.parity xor v_inbit;
end if;
-- detect first NULL
if v.null_seen = '0' then
if v.bitshift = "000101110" then
-- got first NULL pattern
v.null_seen := '1';
v.control := v_inbit; -- should always be '1'
v.parity := '0';
v.bitcnt := (3 => '1', others => '0');
end if;
end if;
-- shift new bit into register.
v.bitshift := v_inbit & v.bitshift(v.bitshift'high downto 1);
end loop;
end if;
-- synchronous reset
if rxen = '0' then
v.bit_seen := '0';
v.null_seen := '0';
v.bitshift := "111111111";
v.bitcnt := (others => '0');
v.gotfct := '0';
v.tick_out := '0';
v.rxchar := '0';
v.rxflag := '0';
v.escaped := '0';
v.timereg := "00000000";
v.datareg := "00000000";
v.disccnt := to_unsigned(0, v.disccnt'length);
v.errpar := '0';
v.erresc := '0';
end if;
-- drive outputs
recvo.gotbit <= r.bit_seen;
recvo.gotnull <= r.null_seen;
recvo.gotfct <= r.gotfct;
recvo.tick_out <= r.tick_out;
recvo.ctrl_out <= r.timereg(7 downto 6);
recvo.time_out <= r.timereg(5 downto 0);
recvo.rxchar <= r.rxchar;
recvo.rxflag <= r.rxflag;
recvo.rxdata <= r.datareg;
if r.bit_seen = '1' and r.disccnt = 0 then
recvo.errdisc <= '1';
else
recvo.errdisc <= '0';
end if;
recvo.errpar <= r.errpar;
recvo.erresc <= r.erresc;
-- update registers
rin <= v;
end process;
-- update registers on rising edge of system clock
process (clk) is
begin
if rising_edge(clk) then
r <= rin;
end if;
end process;
end architecture spwrecv_arch;
| gpl-3.0 | 1f82a9895e6a0f8071a8f21d7e9f7f57 | 0.404833 | 4.315113 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/grlib/sparc/sparc_disas.vhd | 1 | 28,338 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: sparc_disas
-- File: sparc_disas.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: SPARC disassembler according to SPARC V8 manual
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
use grlib.sparc.all;
use grlib.testlib.print;
use std.textio.all;
package sparc_disas is
function tostf(v:std_logic_vector) return string;
procedure print_insn(ndx: integer; pc, op, res : std_logic_vector(31 downto 0);
valid, trap, wr : boolean;
rex: boolean := false);
procedure print_fpinsn(ndx: integer; pc, op : std_logic_vector(31 downto 0);
res : std_logic_vector(63 downto 0);
dpres, valid, trap, wr : boolean);
function ins2st(pc, op : std_logic_vector(31 downto 0); rex: boolean := false) return string;
end;
package body sparc_disas is
type base_type is (hex, dec);
subtype nibble is std_logic_vector(3 downto 0);
type pc_op_type is record
pc, op : std_logic_vector(31 downto 0);
end record;
function tostd(v:std_logic_vector) return string;
function tosth(v:std_logic_vector) return string;
function tostrd(n:integer) return string;
function tohex(n:nibble) return character is
begin
case n is
when "0000" => return('0');
when "0001" => return('1');
when "0010" => return('2');
when "0011" => return('3');
when "0100" => return('4');
when "0101" => return('5');
when "0110" => return('6');
when "0111" => return('7');
when "1000" => return('8');
when "1001" => return('9');
when "1010" => return('a');
when "1011" => return('b');
when "1100" => return('c');
when "1101" => return('d');
when "1110" => return('e');
when "1111" => return('f');
when others => return('X');
end case;
end;
type carr is array (0 to 9) of character;
constant darr : carr := ('0', '1', '2', '3', '4', '5', '6', '7', '8', '9');
function tostd(v:std_logic_vector) return string is
variable s : string(1 to 2);
variable val : integer;
begin
val := conv_integer(v); s(1) := darr(val / 10); s(2) := darr(val mod 10);
return(s);
end;
function tosth(v:std_logic_vector) return string is
constant vlen : natural := v'length; --'
constant slen : natural := (vlen+3)/4;
variable vv : std_logic_vector(vlen-1 downto 0);
variable s : string(1 to slen);
begin
vv := v;
for i in slen downto 1 loop
s(i) := tohex(vv(3 downto 0));
vv(vlen-5 downto 0) := vv(vlen-1 downto 4);
end loop;
return(s);
end;
function tostf(v:std_logic_vector) return string is
constant vlen : natural := v'length; --'
constant slen : natural := (vlen+3)/4;
variable vv : std_logic_vector(vlen-1 downto 0);
variable s : string(1 to slen);
begin
vv := v;
for i in slen downto 1 loop
s(i) := tohex(vv(3 downto 0));
vv(vlen-5 downto 0) := vv(vlen-1 downto 4);
end loop;
return("0x" & s);
end;
function tostrd(n:integer) return string is
variable len : integer := 0;
variable tmp : string(10 downto 1);
variable v : integer := n;
begin
for i in 0 to 9 loop
tmp(i+1) := darr(v mod 10);
if tmp(i+1) /= '0' then
len := i;
end if;
v := v/10;
end loop;
return(tmp(len+1 downto 1));
end;
function ireg2st(v : std_logic_vector) return string is
variable ctmp : character;
variable reg : std_logic_vector(4 downto 0);
begin
reg := v;
case reg(4 downto 3) is
when "00" => ctmp := 'g'; when "01" => ctmp := 'o';
when "10" => ctmp := 'l'; when "11" => ctmp := 'i';
when others => ctmp := 'X';
end case;
if v(4 downto 0) = "11110" then return("%fp");
elsif v(4 downto 0) = "01110" then return("%sp");
else return('%' & ctmp & tost('0' & reg(2 downto 0))); end if;
end;
function simm13dec(insn : pc_op_type; base : base_type; merge : boolean) return string is
variable simm : std_logic_vector(12 downto 0) := insn.op(12 downto 0);
variable rs1 : std_logic_vector(4 downto 0) := insn.op(18 downto 14);
variable i : std_ulogic := insn.op(13);
variable sig : character;
variable fill : std_logic_vector(31 downto 13) := (others => simm(12));
begin
if i = '0' then
return("");
else
if (simm(12) = '1') and (base = dec) then
sig := '-'; simm := (not simm) + 1;
else
sig := '+';
end if;
if base = dec then
if merge then
if rs1 = "00000" then
return(tost(simm));
else
return(sig & tost(simm));
end if;
else
if rs1 = "00000" then
return(tost(simm));
else
if sig = '-' then
return(", " & sig & tost(simm));
else
return(", " & tost(simm));
end if;
end if;
end if;
else
if rs1 = "00000" then
if simm(12) = '1' then return(tost(fill & simm));
else return(tost(simm)); end if;
else
if simm(12) = '1' then return(", " & tost(fill & simm));
else return(", " & tost(simm)); end if;
end if;
end if;
end if;
end;
function freg2(insn : pc_op_type) return string is
variable rs1, rs2, rd : std_logic_vector(4 downto 0);
variable i : std_ulogic;
begin
rs2 := insn.op(4 downto 0);
rd := insn.op(29 downto 25);
return("%f" & tostd(rs2) &
", %f" & tostd(rd));
end;
function creg3(insn : pc_op_type) return string is
variable rs1, rs2, rd : std_logic_vector(4 downto 0);
variable i : std_ulogic;
begin
rs1 := insn.op(18 downto 14);
rs2 := insn.op(4 downto 0);
rd := insn.op(29 downto 25);
return("%c" & tostd(rs1) & ", %c" & tostd(rs2) & ", %c" & tostd(rd));
end;
function freg3(insn : pc_op_type) return string is
variable rs1, rs2, rd : std_logic_vector(4 downto 0);
variable i : std_ulogic;
begin
rs1 := insn.op(18 downto 14);
rs2 := insn.op(4 downto 0);
rd := insn.op(29 downto 25);
return("%f" & tostd(rs1) & ", %f" & tostd(rs2) & ", %f" & tostd(rd));
end;
function fregc(insn : pc_op_type) return string is
variable rs1, rs2 : std_logic_vector(4 downto 0);
variable i : std_ulogic;
begin
rs1 := insn.op(18 downto 14);
rs2 := insn.op(4 downto 0);
return("%f" & tostd(rs1) & ", %f" & tostd(rs2));
end;
function regimm(insn : pc_op_type; base : base_type; merge : boolean) return string is
variable rs1, rs2 : std_logic_vector(4 downto 0);
variable i : std_ulogic;
begin
rs1 := insn.op(18 downto 14);
rs2 := insn.op(4 downto 0);
i := insn.op(13);
if i = '0' then
if (rs1 = "00000") then
if (rs2 = "00000") then return("0");
else return(ireg2st(rs2)); end if;
else
if (rs2 = "00000") then return(ireg2st(rs1));
elsif merge then return(ireg2st(rs1) & " + " & ireg2st(rs2));
else return(ireg2st(rs1) & ", " & ireg2st(rs2)); end if;
end if;
else
if (rs1 = "00000") then return(simm13dec(insn, base, merge));
elsif insn.op(12 downto 0) = "0000000000000" then return(ireg2st(rs1));
else return(ireg2st(rs1) & simm13dec(insn, base, merge)); end if;
end if;
end;
function regres(insn : pc_op_type; base : base_type) return string is
variable rs1, rs2, rd : std_logic_vector(4 downto 0);
variable i : std_ulogic;
begin
rd := insn.op(29 downto 25);
return(regimm(insn, base,false) & ", " & ireg2st(rd ));
end;
function branchop(insn : pc_op_type) return string is
variable slice : std_logic_vector(28 downto 25);
begin
slice := insn.op(28 downto 25);
case slice is
when "0000" => return("n");
when "0001" => return("e");
when "0010" => return("le");
when "0011" => return("l");
when "0100" => return("leu");
when "0101" => return("cs");
when "0110" => return("neg");
when "0111" => return("vs");
when "1000" => return("a");
when "1001" => return("ne");
when "1010" => return("g");
when "1011" => return("ge");
when "1100" => return("gu");
when "1101" => return("cc");
when "1110" => return("pos");
when "1111" => return("vc");
when others => return("XXX");
end case;
end;
function fbranchop(insn : pc_op_type) return string is
variable slice : std_logic_vector(28 downto 25);
begin
slice := insn.op(28 downto 25);
case slice is
when "0000" => return("n");
when "0001" => return("ne");
when "0010" => return("lg");
when "0011" => return("ul");
when "0100" => return("l");
when "0101" => return("ug");
when "0110" => return("g");
when "0111" => return("u");
when "1000" => return("a");
when "1001" => return("e");
when "1010" => return("ue");
when "1011" => return("ge");
when "1100" => return("uge");
when "1101" => return("le");
when "1110" => return("ule");
when "1111" => return("o");
when others => return("XXX");
end case;
end;
function ldparcp(insn : pc_op_type; rd : std_logic_vector; base : base_type) return string is
begin
return("[" & regimm(insn,dec,true) & "]" & ", " & "%c" & tost(rd));
end;
function ldparf(insn : pc_op_type; rd : std_logic_vector; base : base_type) return string is
begin
return("[" & regimm(insn,dec,true) & "]" & ", " & "%f" & tostd(rd));
end;
function ldpar(insn : pc_op_type; rd : std_logic_vector; base : base_type) return string is
begin
return("[" & regimm(insn,dec,true) & "]" & ", " & ireg2st(rd));
end;
function ldpara(insn : pc_op_type; rd : std_logic_vector; base : base_type) return string is
begin
return("[" & regimm(insn,dec,true) & "]" & " " & tost(insn.op(12 downto 5)) & ", " & ireg2st(rd));
end;
function ldpara_cas(insn : pc_op_type; rs1, rs2, rd : std_logic_vector; base : base_type) return string is
begin
return("[" & ireg2st(rs1) & "]" & " " & tost(insn.op(12 downto 5)) & ", " &
ireg2st(rs2) & ", " & ireg2st(rd));
end;
function stparc(insn : pc_op_type; rd : std_logic_vector; base : base_type) return string is
begin
if rd = "00000" then
return("[" & regimm(insn,dec,true) & "]");
else
return(ireg2st(rd) & ", [" & regimm(insn,dec,true) & "]");
end if;
end;
function stparcp(insn : pc_op_type; rd : std_logic_vector; base : base_type) return string is
begin
return("%c" & tost(rd) & ", [" & regimm(insn,dec,true) & "]");
end;
function stparf(insn : pc_op_type; rd : std_logic_vector; base : base_type) return string is
begin
return("%f" & tostd(rd) & ", [" & regimm(insn,dec,true) & "]");
end;
function stpar(insn : pc_op_type; rd : std_logic_vector; base : base_type) return string is
begin
return(ireg2st(rd) & ", [" & regimm(insn,dec,true) & "]");
end;
function stpara(insn : pc_op_type; rd : std_logic_vector; base : base_type) return string is
begin
return(ireg2st(rd) & ", [" & regimm(insn,dec,true) & "]" & " " & tost(insn.op(12 downto 5)));
end;
function ins2st(pc, op : std_logic_vector(31 downto 0); rex: boolean := false) return string is
constant STMAX : natural := 9;
constant bl2 : string(1 to 2) := (others => ' ');
constant bb : string(1 to 4) := (others => ' ');
variable op1 : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable opf : std_logic_vector(8 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable rs1, rs2, rd : std_logic_vector(4 downto 0);
variable addr : std_logic_vector(31 downto 0);
variable annul : std_ulogic;
variable i : std_ulogic;
variable simm : std_logic_vector(12 downto 0);
variable insn : pc_op_type;
variable bbr : string(1 to 4);
begin
op1 := op(31 downto 30);
op2 := op(24 downto 22);
op3 := op(24 downto 19);
opf := op(13 downto 5);
cond := op(28 downto 25);
annul := op(29);
rs1 := op(18 downto 14);
rs2 := op(4 downto 0);
rd := op(29 downto 25);
i := op(13);
simm := op(12 downto 0);
insn.op := op;
insn.pc := pc;
if rex then bbr:=" R "; else bbr:=bb; end if;
case op1 is
when CALL =>
addr := pc + (op(29 downto 0) & "00");
return(tostf(pc) & bbr & "call" & bl2 & tost(addr));
when FMT2 =>
case op2 is
when SETHI =>
if rd = "00000" then
return(tostf(pc) & bbr & "nop");
else
return(tostf(pc) & bbr & "sethi" & bl2 & "%hi(" &
tost(op(21 downto 0) & "0000000000") & "), " & ireg2st(rd));
end if;
when BICC | FBFCC =>
addr(31 downto 24) := (others => '0');
addr(1 downto 0) := (others => '0');
addr(23 downto 2) := op(21 downto 0);
if addr(23) = '1' then
addr(31 downto 24) := (others => '1');
else
addr(31 downto 24) := (others => '0');
end if;
addr := addr + pc;
if op2 = BICC then
if op(29) = '1' then
return(tostf(pc) & bbr & 'b' & branchop(insn) & ",a" & bl2 &
tost(addr));
else
return(tostf(pc) & bbr & 'b' & branchop(insn) & bl2 &
tost(addr));
end if;
else
if op(29) = '1' then
return(tostf(pc) & bbr & "fb" & fbranchop(insn) & ",a" & bl2 &
tost(addr));
else
return(tostf(pc) & bbr & "fb" & fbranchop(insn) & bl2 &
tost(addr));
end if;
end if;
-- when CBCCC => cptrap := '1';
when others => return(tostf(pc) & bbr & "unimp");
end case;
when FMT3 =>
case op3 is
when IAND => return(tostf(pc) & bbr & "and" & bl2 & regres(insn,hex));
when IADD =>
if (i='0' and simm(12)='1') then
insn.op(13):='1';
return (tostf(pc) & bbr & "addrex" & bl2 & regres(insn,dec));
end if;
return(tostf(pc) & bbr & "add" & bl2 & regres(insn,dec));
when IOR =>
if ((i = '0') and (rs1 = "00000") and (rs2 = "00000")) then
return(tostf(pc) & bbr & "clr" & bl2 & ireg2st(rd));
elsif ((i = '1') and (simm = "0000000000000")) or (rs1 = "00000") then
return(tostf(pc) & bbr & "mov" & bl2 & regres(insn,hex));
else
return(tostf(pc) & bbr & "or " & bl2 & regres(insn,hex));
end if;
when IXOR => return(tostf(pc) & bbr & "xor" & bl2 & regres(insn,hex));
when ISUB => return(tostf(pc) & bbr & "sub" & bl2 & regres(insn,dec));
when ANDN => return(tostf(pc) & bbr & "andn" & bl2 & regres(insn,hex));
when ORN => return(tostf(pc) & bbr & "orn" & bl2 & regres(insn,hex));
when IXNOR =>
if ((i = '0') and ((rs1 = rd) or (rs2 = "00000"))) then
return(tostf(pc) & bbr & "not" & bl2 & ireg2st(rd));
else
return(tostf(pc) & bbr & "xnor" & bl2 & ireg2st(rd));
end if;
when ADDX => return(tostf(pc) & bbr & "addx" & bl2 & regres(insn,dec));
when SUBX => return(tostf(pc) & bbr & "subx" & bl2 & regres(insn,dec));
when ADDCC => return(tostf(pc) & bbr & "addcc" & bl2 & regres(insn,dec));
when ANDCC => return(tostf(pc) & bbr & "andcc" & bl2 & regres(insn,hex));
when ORCC => return(tostf(pc) & bbr & "orcc" & bl2 & regres(insn,hex));
when XORCC => return(tostf(pc) & bbr & "xorcc" & bl2 & regres(insn,hex));
when SUBCC => return(tostf(pc) & bbr & "subcc" & bl2 & regres(insn,dec));
when ANDNCC => return(tostf(pc) & bbr & "andncc" & bl2 & regres(insn,hex));
when ORNCC => return(tostf(pc) & bbr & "orncc" & bl2 & regres(insn,hex));
when XNORCC => return(tostf(pc) & bbr & "xnorcc" & bl2 & regres(insn,hex));
when ADDXCC => return(tostf(pc) & bbr & "addxcc" & bl2 & regres(insn,hex));
when UMAC => return(tostf(pc) & bbr & "umac" & bl2 & regres(insn,dec));
when SMAC => return(tostf(pc) & bbr & "smac" & bl2 & regres(insn,dec));
when UMUL => return(tostf(pc) & bbr & "umul" & bl2 & regres(insn,dec));
when SMUL => return(tostf(pc) & bbr & "smul" & bl2 & regres(insn,dec));
when UMULCC => return(tostf(pc) & bbr & "umulcc" & bl2 & regres(insn,dec));
when SMULCC => return(tostf(pc) & bbr & "smulcc" & bl2 & regres(insn,dec));
when SUBXCC => return(tostf(pc) & bbr & "subxcc" & bl2 & regres(insn,dec));
when UDIV => return(tostf(pc) & bbr & "udiv" & bl2 & regres(insn,dec));
when SDIV => return(tostf(pc) & bbr & "sdiv" & bl2 & regres(insn,dec));
when UDIVCC => return(tostf(pc) & bbr & "udivcc" & bl2 & regres(insn,dec));
when SDIVCC => return(tostf(pc) & bbr & "sdivcc" & bl2 & regres(insn,dec));
when TADDCC => return(tostf(pc) & bbr & "taddcc" & bl2 & regres(insn,dec));
when TSUBCC => return(tostf(pc) & bbr & "tsubcc" & bl2 & regres(insn,dec));
when TADDCCTV => return(tostf(pc) & bbr & "taddcctv" & bl2 & regres(insn,dec));
when TSUBCCTV => return(tostf(pc) & bbr & "tsubcctv" & bl2 & regres(insn,dec));
when MULSCC => return(tostf(pc) & bbr & "mulscc" & bl2 & regres(insn,dec));
when ISLL => return(tostf(pc) & bbr & "sll" & bl2 & regres(insn,dec));
when ISRL => return(tostf(pc) & bbr & "srl" & bl2 & regres(insn,dec));
when ISRA => return(tostf(pc) & bbr & "sra" & bl2 & regres(insn,dec));
when RDY =>
if rs1 /= "00000" then
return(tostf(pc) & bbr & "mov" & bl2 & "%asr" &
tostd(rs1) & ", " & ireg2st(rd));
else
return(tostf(pc) & bbr & "mov" & bl2 & "%y, " & ireg2st(rd));
end if;
when RDPSR => return(tostf(pc) & bbr & "mov" & bl2 & "%psr, " & ireg2st(rd));
when RDWIM => return(tostf(pc) & bbr & "mov" & bl2 & "%wim, " & ireg2st(rd));
when RDTBR => return(tostf(pc) & bbr & "mov" & bl2 & "%tbr, " & ireg2st(rd));
when WRY =>
if (rs1 = "00000") or (rs2 = "00000") then
if rd /= "00000" then
return(tostf(pc) & bbr & "mov" & bl2
& regimm(insn,hex,false) & ", %asr" & tostd(rd));
else
return(tostf(pc) & bbr & "mov" & bl2 & regimm(insn,hex,false) & ", %y");
end if;
else
if rd /= "00000" then
return(tostf(pc) & bbr & "wr " & bl2 & "%asr"
& regimm(insn,hex,false) & ", %asr" & tostd(rd));
else
return(tostf(pc) & bbr & "wr " & bl2 & regimm(insn,hex,false) & ", %y");
end if;
end if;
when WRPSR =>
if (rs1 = "00000") or (rs2 = "00000") then
return(tostf(pc) & bbr & "mov" & bl2 & regimm(insn,hex,false) & ", %psr");
else
return(tostf(pc) & bbr & "wr " & bl2 & regimm(insn,hex,false) & ", %psr");
end if;
when WRWIM =>
if (rs1 = "00000") or (rs2 = "00000") then
return(tostf(pc) & bbr & "mov" & bl2 & regimm(insn,hex,false) & ", %wim");
else
return(tostf(pc) & bbr & "wr " & bl2 & regimm(insn,hex,false) & ", %wim");
end if;
when WRTBR =>
if (rs1 = "00000") or (rs2 = "00000") then
return(tostf(pc) & bbr & "mov" & bl2 & regimm(insn,hex,false) & ", %tbr");
else
return(tostf(pc) & bbr & "wr " & bl2 & regimm(insn,hex,false) & ", %tbr");
end if;
when JMPL =>
if (rd = "00000") then
if (i = '1') and (simm = "0000000001000") then
if (rs1 = "11111") then return(tostf(pc) & bbr & "ret");
elsif (rs1 = "01111") then return(tostf(pc) & bbr & "retl");
else return(tostf(pc) & bbr & "jmp" & bl2 & regimm(insn,dec,true));
end if;
else return(tostf(pc) & bbr & "jmp" & bl2 & regimm(insn,dec,true));
end if;
else return(tostf(pc) & bbr & "jmpl" & bl2 & regres(insn,dec));
end if;
when TICC =>
return(tostf(pc) & bbr & 't' & branchop(insn) & bl2 & regimm(insn,hex,false));
when FLUSH =>
return(tostf(pc) & bbr & "flush" & bl2 & regimm(insn,hex,false));
when RETT =>
return(tostf(pc) & bbr & "rett" & bl2 & regimm(insn,dec,true));
when RESTORE =>
if (rd = "00000") then
return(tostf(pc) & bbr & "restore");
else
return(tostf(pc) & bbr & "restore" & bl2 & regres(insn,hex));
end if;
when SAVE =>
if (i='0' and simm(12)='1') then
insn.op(13):='1';
return (tostf(pc) & bbr & "saverex" & bl2 & regres(insn,dec));
elsif (rd = "00000") then return(tostf(pc) & bbr & "save");
else return(tostf(pc) & bbr & "save" & bl2 & regres(insn,dec)); end if;
when FPOP1 =>
case opf is
when FITOS => return(tostf(pc) & bbr & "fitos" & bl2 & freg2(insn));
when FITOD => return(tostf(pc) & bbr & "fitod" & bl2 & freg2(insn));
when FSTOI => return(tostf(pc) & bbr & "fstoi" & bl2 & freg2(insn));
when FDTOI => return(tostf(pc) & bbr & "fdtoi" & bl2 & freg2(insn));
when FSTOD => return(tostf(pc) & bbr & "fstod" & bl2 & freg2(insn));
when FDTOS => return(tostf(pc) & bbr & "fdtos" & bl2 & freg2(insn));
when FMOVS => return(tostf(pc) & bbr & "fmovs" & bl2 & freg2(insn));
when FNEGS => return(tostf(pc) & bbr & "fnegs" & bl2 & freg2(insn));
when FABSS => return(tostf(pc) & bbr & "fabss" & bl2 & freg2(insn));
when FSQRTS => return(tostf(pc) & bbr & "fsqrts" & bl2 & freg2(insn));
when FSQRTD => return(tostf(pc) & bbr & "fsqrtd" & bl2 & freg2(insn));
when FADDS => return(tostf(pc) & bbr & "fadds" & bl2 & freg3(insn));
when FADDD => return(tostf(pc) & bbr & "faddd" & bl2 & freg3(insn));
when FSUBS => return(tostf(pc) & bbr & "fsubs" & bl2 & freg3(insn));
when FSUBD => return(tostf(pc) & bbr & "fsubd" & bl2 & freg3(insn));
when FMULS => return(tostf(pc) & bbr & "fmuls" & bl2 & freg3(insn));
when FMULD => return(tostf(pc) & bbr & "fmuld" & bl2 & freg3(insn));
when FSMULD => return(tostf(pc) & bbr & "fsmuld" & bl2 & freg3(insn));
when FDIVS => return(tostf(pc) & bbr & "fdivs" & bl2 & freg3(insn));
when FDIVD => return(tostf(pc) & bbr & "fdivd" & bl2 & freg3(insn));
when others => return(tostf(pc) & bbr & "unknown FOP1: " & tost(op));
end case;
when FPOP2 =>
case opf is
when FCMPS => return(tostf(pc) & bbr & "fcmps" & bl2 & fregc(insn));
when FCMPD => return(tostf(pc) & bbr & "fcmpd" & bl2 & fregc(insn));
when FCMPES => return(tostf(pc) & bbr & "fcmpes" & bl2 & fregc(insn));
when FCMPED => return(tostf(pc) & bbr & "fcmped" & bl2 & fregc(insn));
when others => return(tostf(pc) & bbr & "unknown FOP2: " & tost(insn.op));
end case;
when CPOP1 =>
return(tostf(pc) & bbr & "cpop1" & bl2 & tost("000"&opf) & ", " &creg3(insn));
when CPOP2 =>
return(tostf(pc) & bbr & "cpop2" & bl2 & tost("000"&opf) & ", " &creg3(insn));
when others => return(tostf(pc) & bbr & "unknown opcode: " & tost(insn.op));
end case;
when LDST =>
case op3 is
when STC =>
return(tostf(pc) & bbr & "st" & bl2 & stparcp(insn, rd, dec));
when STF =>
return(tostf(pc) & bbr & "st" & bl2 & stparf(insn, rd, dec));
when ST =>
if rd = "00000" then
return(tostf(pc) & bbr & "clr" & bl2 & stparc(insn, rd, dec));
else
return(tostf(pc) & bbr & "st" & bl2 & stpar(insn, rd, dec));
end if;
when STB =>
if rd = "00000" then
return(tostf(pc) & bbr & "clrb" & bl2 & stparc(insn, rd, dec));
else
return(tostf(pc) & bbr & "stb" & bl2 & stpar(insn, rd, dec));
end if;
when STH =>
if rd = "00000" then
return(tostf(pc) & bbr & "clrh" & bl2 & stparc(insn, rd, dec));
else
return(tostf(pc) & bbr & "sth" & bl2 & stpar(insn, rd, dec));
end if;
when STDC =>
return(tostf(pc) & bbr & "std" & bl2 & stparcp(insn, rd, dec));
when STDF =>
return(tostf(pc) & bbr & "std" & bl2 & stparf(insn, rd, dec));
when STCSR =>
return(tostf(pc) & bbr & "st" & bl2 & "%csr, [" & regimm(insn,dec,true) & "]");
when STFSR =>
return(tostf(pc) & bbr & "st" & bl2 & "%fsr, [" & regimm(insn,dec,true) & "]");
when STDCQ =>
return(tostf(pc) & bbr & "std" & bl2 & "%cq, [" & regimm(insn,dec,true) & "]");
when STDFQ =>
return(tostf(pc) & bbr & "std" & bl2 & "%fq, [" & regimm(insn,dec,true) & "]");
when ISTD =>
return(tostf(pc) & bbr & "std" & bl2 & stpar(insn, rd, dec));
when STA =>
return(tostf(pc) & bbr & "sta" & bl2 & stpara(insn, rd, dec));
when STBA =>
return(tostf(pc) & bbr & "stba" & bl2 & stpara(insn, rd, dec));
when STHA =>
return(tostf(pc) & bbr & "stha" & bl2 & stpara(insn, rd, dec));
when STDA =>
return(tostf(pc) & bbr & "stda" & bl2 & stpara(insn, rd, dec));
when LDC =>
return(tostf(pc) & bbr & "ld" & bl2 & ldparcp(insn, rd, dec));
when LDF =>
return(tostf(pc) & bbr & "ld" & bl2 & ldparf(insn, rd, dec));
when LDCSR =>
return(tostf(pc) & bbr & "ld" & bl2 & "[" & regimm(insn,dec,true) & "]" & ", %csr");
when LDFSR =>
return(tostf(pc) & bbr & "ld" & bl2 & "[" & regimm(insn,dec,true) & "]" & ", %fsr");
when LD =>
return(tostf(pc) & bbr & "ld" & bl2 & ldpar(insn, rd, dec));
when LDUB =>
return(tostf(pc) & bbr & "ldub" & bl2 & ldpar(insn, rd, dec));
when LDUH =>
return(tostf(pc) & bbr & "lduh" & bl2 & ldpar(insn, rd, dec));
when LDDC =>
return(tostf(pc) & bbr & "ldd" & bl2 & ldparcp(insn, rd, dec));
when LDDF =>
return(tostf(pc) & bbr & "ldd" & bl2 & ldparf(insn, rd, dec));
when LDD =>
return(tostf(pc) & bbr & "ldd" & bl2 & ldpar(insn, rd, dec));
when LDSB =>
return(tostf(pc) & bbr & "ldsb" & bl2 & ldpar(insn, rd, dec));
when LDSH =>
return(tostf(pc) & bbr & "ldsh" & bl2 & ldpar(insn, rd, dec));
when LDSTUB =>
return(tostf(pc) & bbr & "ldstub" & bl2 & ldpar(insn, rd, dec));
when SWAP =>
return(tostf(pc) & bbr & "swap" & bl2 & ldpar(insn, rd, dec));
when LDA =>
return(tostf(pc) & bbr & "lda" & bl2 & ldpara(insn, rd, dec));
when LDUBA =>
return(tostf(pc) & bbr & "lduba" & bl2 & ldpara(insn, rd, dec));
when LDUHA =>
return(tostf(pc) & bbr & "lduha" & bl2 & ldpara(insn, rd, dec));
when LDDA =>
return(tostf(pc) & bbr & "ldda" & bl2 & ldpara(insn, rd, dec));
when LDSBA =>
return(tostf(pc) & bbr & "ldsba" & bl2 & ldpara(insn, rd, dec));
when LDSHA =>
return(tostf(pc) & bbr & "ldsha" & bl2 & ldpara(insn, rd, dec));
when LDSTUBA =>
return(tostf(pc) & bbr & "ldstuba" & bl2 & ldpara(insn, rd, dec));
when SWAPA =>
return(tostf(pc) & bbr & "swapa" & bl2 & ldpara(insn, rd, dec));
when CASA =>
return(tostf(pc) & bbr & "casa" & bl2 & ldpara_cas(insn, rs1, rs2, rd, dec));
when others => return(tostf(pc) & bbr & "unknown opcode: " & tost(op));
end case;
when others => return(tostf(pc) & bbr & "unknown opcode: " & tost(op));
end case;
end;
procedure print_insn(ndx: integer; pc, op, res : std_logic_vector(31 downto 0);
valid, trap, wr : boolean;
rex: boolean := false) is
begin
if valid then
if trap then grlib.testlib.print ("cpu" & tost(ndx) &": " & ins2st(pc, op, rex) & " (trapped)");
elsif wr then grlib.testlib.print ("cpu" & tost(ndx) & ": " & ins2st(pc, op, rex) & " [" & tost(res) & "]");
else grlib.testlib.print ("cpu" & tost(ndx) & ": " & ins2st(pc, op, rex)); end if;
end if;
end;
procedure print_fpinsn(ndx: integer; pc, op : std_logic_vector(31 downto 0);
res : std_logic_vector(63 downto 0);
dpres, valid, trap, wr : boolean) is
variable t : natural;
begin
if valid then
t := now / 1 ns;
if trap then grlib.testlib.print ("cpu" & tost(ndx) &": " & ins2st(pc, op) & " (trapped)");
elsif wr then
if dpres then grlib.testlib.print ("cpu" & tost(ndx) & ": " & ins2st(pc, op) & " [" & tost(res) & "]");
else grlib.testlib.print ("cpu" & tost(ndx) & ": " & ins2st(pc, op) & " [" & tost(res(63 downto 32)) & "]"); end if;
else grlib.testlib.print ("cpu" & tost(ndx) & ": " & ins2st(pc, op)); end if;
end if;
end;
end;
-- pragma translate_on
| gpl-3.0 | 835e70dfaeb5bbecfa23941963513c47 | 0.564578 | 2.911239 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/i2c/i2c2ahb.vhd | 1 | 3,078 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: i2c2ahb
-- File: i2c2ahb.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- Contact: [email protected]
-- Description: Simple I2C-slave providing a bridge to AMBA AHB
-- See i2c2ahbx.vhd and GRIP for documentation
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.conv_std_logic_vector;
library gaisler;
use gaisler.i2c.all;
entity i2c2ahb is
generic (
-- AHB Configuration
hindex : integer := 0;
--
ahbaddrh : integer := 0;
ahbaddrl : integer := 0;
ahbmaskh : integer := 0;
ahbmaskl : integer := 0;
-- I2C configuration
i2cslvaddr : integer range 0 to 127 := 0;
i2ccfgaddr : integer range 0 to 127 := 0;
oepol : integer range 0 to 1 := 0;
--
filter : integer range 2 to 512 := 2
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
-- I2C signals
i2ci : in i2c_in_type;
i2co : out i2c_out_type
);
end entity i2c2ahb;
architecture rtl of i2c2ahb is
signal i2c2ahbi : i2c2ahb_in_type;
begin
bridge : i2c2ahbx
generic map (
hindex => hindex,
oepol => oepol,
filter => filter)
port map (
rstn => rstn,
clk => clk,
ahbi => ahbi,
ahbo => ahbo,
i2ci => i2ci,
i2co => i2co,
i2c2ahbi => i2c2ahbi,
i2c2ahbo => open);
i2c2ahbi.en <= '1';
i2c2ahbi.haddr <= conv_std_logic_vector(ahbaddrh, 16) &
conv_std_logic_vector(ahbaddrl, 16);
i2c2ahbi.hmask <= conv_std_logic_vector(ahbmaskh, 16) &
conv_std_logic_vector(ahbmaskl, 16);
i2c2ahbi.slvaddr <= conv_std_logic_vector(i2cslvaddr, 7);
i2c2ahbi.cfgaddr <= conv_std_logic_vector(i2ccfgaddr, 7);
end architecture rtl;
| gpl-3.0 | 61574ebd9bea3e20c56704f601620e63 | 0.586095 | 3.583236 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/maps/allpads.vhd | 1 | 33,150 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
----------------------------------------------------------------------------
-- Package: allpads
-- File: allpads.vhd
-- Author: Jiri Gaisler et al. - Aeroflex Gaisler
-- Description: All tech pads
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
package allpads is
component apa3_clkpad
generic (level : integer := 0; voltage : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic);
end component;
component apa3_clkpad_ds
generic (level : integer := lvds);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end component;
component apa3_inpad
generic (level : integer := 0; voltage : integer := 0;
filter : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic);
end component;
component apa3_inpad_ds
generic (level : integer := lvds);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end component;
component apa3_iopad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0;
filter : integer := 0);
port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end component;
component apa3_iopad_ds
generic (level : integer := lvds);
port (padp, padn : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end component;
component apa3_odpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_ulogic; i, en : in std_ulogic);
end component;
component apa3_outpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_ulogic; i : in std_ulogic);
end component;
component apa3_outpad_ds
generic (level : integer := lvds);
port (padp, padn : out std_ulogic; i : in std_ulogic);
end component;
component apa3_toutpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_ulogic; i, en : in std_ulogic);
end component;
component apa3_toutpad_ds
generic (level : integer := lvds);
port (padp, padn : out std_ulogic; i, en : in std_ulogic);
end component;
component apa3e_clkpad
generic (level : integer := 0; voltage : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic);
end component;
component apa3e_clkpad_ds
generic (level : integer := lvds);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end component;
component apa3e_inpad
generic (level : integer := 0; voltage : integer := 0;
filter : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic);
end component;
component apa3e_inpad_ds
generic (level : integer := lvds);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end component;
component apa3e_iopad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0;
filter : integer := 0);
port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end component;
component apa3e_iopad_ds
generic (level : integer := lvds);
port (padp, padn : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end component;
component apa3e_odpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_ulogic; i, en : in std_ulogic);
end component;
component apa3e_outpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_ulogic; i : in std_ulogic);
end component;
component apa3e_outpad_ds
generic (level : integer := lvds);
port (padp, padn : out std_ulogic; i : in std_ulogic);
end component;
component apa3e_toutpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_ulogic; i, en : in std_ulogic);
end component;
component apa3e_toutpad_ds
generic (level : integer := lvds);
port (padp, padn : out std_ulogic; i, en : in std_ulogic);
end component;
component igloo2_clkpad
port (pad : in std_ulogic; o : out std_ulogic);
end component;
component igloo2_clkpad_ds
port (padp, padn : in std_ulogic; o : out std_ulogic);
end component;
component igloo2_inpad
port (pad : in std_ulogic; o : out std_ulogic);
end component;
component igloo2_inpad_ds
port (padp, padn : in std_ulogic; o : out std_ulogic);
end component;
component igloo2_iopad
port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end component;
component igloo2_iopad_ds
port (padp, padn : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end component;
component igloo2_outpad
port (pad : out std_ulogic; i : in std_ulogic);
end component;
component igloo2_outpad_ds
port (padp, padn : out std_ulogic; i : in std_ulogic);
end component;
component igloo2_toutpad
port (pad : out std_ulogic; i, en : in std_ulogic);
end component;
component igloo2_toutpad_ds
port (padp, padn : out std_ulogic; i, en : in std_ulogic);
end component;
component apa3l_clkpad
generic (level : integer := 0; voltage : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic);
end component;
component apa3l_clkpad_ds
generic (level : integer := lvds);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end component;
component apa3l_inpad
generic (level : integer := 0; voltage : integer := 0;
filter : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic);
end component;
component apa3l_inpad_ds
generic (level : integer := lvds);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end component;
component apa3l_iopad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0;
filter : integer := 0);
port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end component;
component apa3l_iopad_ds
generic (level : integer := lvds);
port (padp, padn : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end component;
component apa3l_odpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_ulogic; i, en : in std_ulogic);
end component;
component apa3l_outpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_ulogic; i : in std_ulogic);
end component;
component apa3l_outpad_ds
generic (level : integer := lvds);
port (padp, padn : out std_ulogic; i : in std_ulogic);
end component;
component apa3l_toutpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_ulogic; i, en : in std_ulogic);
end component;
component apa3l_toutpad_ds
generic (level : integer := lvds);
port (padp, padn : out std_ulogic; i, en : in std_ulogic);
end component;
component fusion_clkpad
generic (level : integer := 0; voltage : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic);
end component;
component fusion_clkpad_ds
generic (level : integer := lvds);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end component;
component fusion_inpad
generic (level : integer := 0; voltage : integer := 0;
filter : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic);
end component;
component fusion_inpad_ds
generic (level : integer := lvds);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end component;
component fusion_iopad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0;
filter : integer := 0);
port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end component;
component fusion_iopad_ds
generic (level : integer := lvds);
port (padp, padn : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end component;
component fusion_odpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_ulogic; i, en : in std_ulogic);
end component;
component fusion_outpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_ulogic; i : in std_ulogic);
end component;
component fusion_outpad_ds
generic (level : integer := lvds);
port (padp, padn : out std_ulogic; i : in std_ulogic);
end component;
component fusion_toutpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_ulogic; i, en : in std_ulogic);
end component;
component fusion_toutpad_ds
generic (level : integer := lvds);
port (padp, padn : out std_ulogic; i, en : in std_ulogic);
end component;
component axcel_inpad
generic (level : integer := 0; voltage : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic);
end component;
component axcel_iopad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end component;
component axcel_outpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_ulogic; i : in std_ulogic);
end component;
component axcel_odpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_ulogic; i : in std_ulogic);
end component;
component axcel_toutpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_ulogic; i, en : in std_ulogic);
end component;
component axcel_clkpad
generic (level : integer := 0; voltage : integer := 0; arch : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic);
end component;
component axcel_inpad_ds
generic (level : integer := lvds; voltage : integer := x33v);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end component;
component axcel_outpad_ds
generic (level : integer := lvds; voltage : integer := x33v);
port (padp, padn : out std_ulogic; i : in std_ulogic);
end component;
component atc18_inpad
generic (level : integer := 0; voltage : integer := 0);
port (pad : in std_logic; o : out std_logic);
end component;
component atc18_iopad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
end component;
component atc18_outpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i : in std_logic);
end component;
component atc18_odpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i : in std_logic);
end component;
component atc18_toutpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i, en : in std_logic);
end component;
component atc18_clkpad
generic (level : integer := 0; voltage : integer := 0);
port (pad : in std_logic; o : out std_logic);
end component;
component ihp25_inpad
generic(level : integer := 0; voltage : integer := 0);
port (pad : in std_logic; o : out std_logic);
end component;
component ihp25rh_inpad
generic(level : integer := 0; voltage : integer := 0);
port (pad : in std_logic; o : out std_logic);
end component;
component ihp25_iopad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
end component;
component ihp25rh_iopad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
end component;
component ihp25_outpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i : in std_logic);
end component;
component ihp25rh_outpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i : in std_logic);
end component;
component ihp25_toutpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_ulogic; i, en : in std_logic);
end component;
component ihp25rh_toutpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_ulogic; i, en : in std_logic);
end component;
component ihp25_clkpad
generic (level : integer := 0; voltage : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic);
end component;
component ihp25rh_clkpad
generic (level : integer := 0; voltage : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic);
end component;
component rhumc_inpad
generic (level : integer := 0; voltage : integer := 0; filter : integer := 0);
port (pad : in std_logic; o : out std_logic);
end component;
component rhumc_iopad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
end component;
component rhumc_outpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i : in std_logic);
end component;
component rhumc_toutpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i, en : in std_logic);
end component;
component saed32_inpad
generic (level : integer := 0; voltage : integer := 0; filter : integer := 0);
port (pad : in std_logic; o : out std_logic);
end component;
component saed32_iopad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
end component;
component saed32_outpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i : in std_logic);
end component;
component saed32_toutpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i, en : in std_logic);
end component;
component dare_inpad
generic (level : integer := 0; voltage : integer := 0; filter : integer := 0);
port (pad : in std_logic; o : out std_logic);
end component;
component dare_iopad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
end component;
component dare_outpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i : in std_logic);
end component;
component dare_toutpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i, en : in std_logic);
end component;
component rhs65_inpad
generic (level : integer := 0; voltage : integer := 0; filter : integer := 0);
port (pad : in std_logic; o : out std_logic);
end component;
component rhs65_iopad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : inout std_logic; i, en : in std_logic; o : out std_logic;
test, ti, ten: in std_ulogic);
end component;
component rhs65_outpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i : in std_logic);
end component;
component rhs65_toutpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i, en : in std_logic;
test, ti, ten: in std_ulogic);
end component;
component umc_inpad
generic (level : integer := 0; voltage : integer := 0; filter : integer := 0);
port (pad : in std_logic; o : out std_logic);
end component;
component umc_iopad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
end component;
component umc_outpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i : in std_logic);
end component;
component umc_toutpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i, en : in std_logic);
end component;
component unisim_inpad
generic (level : integer := 0; voltage : integer := x33v);
port (pad : in std_ulogic; o : out std_ulogic);
end component;
component unisim_iopad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12);
port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end component;
component unisim_outpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12);
port (pad : out std_ulogic; i : in std_ulogic);
end component;
component unisim_odpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12);
port (pad : out std_ulogic; i : in std_ulogic);
end component;
component unisim_toutpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12);
port (pad : out std_ulogic; i, en : in std_ulogic);
end component;
component unisim_skew_outpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; skew : integer := 0);
port (pad : out std_ulogic; i : in std_ulogic; rst : in std_ulogic;
o : out std_ulogic);
end component;
component unisim_clkpad
generic (level : integer := 0; voltage : integer := x33v; arch : integer := 0; hf : integer := 0;
tech : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic; rstn : std_ulogic := '1'; lock : out std_ulogic);
end component;
component unisim_inpad_ds
generic (level : integer := lvds; voltage : integer := x33v; term : integer := 0);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end component;
component unisim_iopad_ds
generic (level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; term : integer := 0);
port (padp, padn : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end component;
component unisim_outpad_ds
generic (level : integer := lvds; slew : integer := 0; voltage : integer := x33v);
port (padp, padn : out std_ulogic; i : in std_ulogic);
end component;
component unisim_clkpad_ds is
generic (level : integer := lvds; voltage : integer := x33v; term : integer := 0);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end component;
component virtex4_inpad_ds
generic (level : integer := lvds; voltage : integer := x33v);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end component;
component virtex4_clkpad_ds is
generic (level : integer := lvds; voltage : integer := x33v);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end component;
component rh_lib18t_inpad
generic ( voltage : integer := 0; filter : integer := 0);
port (pad : in std_logic; o : out std_logic);
end component;
component rh_lib18t_iopad
generic ( strength : integer := 4);
port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
end component;
component rh_lib18t_inpad_ds is
port (padp, padn : in std_ulogic; o : out std_ulogic; en : in std_ulogic);
end component;
component rh_lib18t_outpad_ds is
port (padp, padn : out std_ulogic; i, en : in std_ulogic);
end component;
component ut025crh_inpad
generic ( level : integer := 0; voltage : integer := 0; filter : integer := 0);
port (pad : in std_logic; o : out std_logic);
end component;
component ut025crh_iopad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end component;
component ut025crh_outpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_ulogic; i : in std_ulogic);
end component;
component ut025crh_toutpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_ulogic; i, en : in std_ulogic);
end component;
component ut025crh_lvds_combo
generic (voltage : integer := 0; width : integer := 1);
port (odpadp, odpadn, ospadp, ospadn : out std_logic_vector(0 to width-1);
odval, osval, en : in std_logic_vector(0 to width-1);
idpadp, idpadn, ispadp, ispadn : in std_logic_vector(0 to width-1);
idval, isval : out std_logic_vector(0 to width-1));
end component;
component ut130hbd_inpad
generic ( level : integer := 0; voltage : integer := 0; filter : integer := 0);
port (pad : in std_logic; o : out std_logic);
end component;
component ut130hbd_iopad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0;
filter : integer :=0 );
port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end component;
component ut130hbd_outpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_ulogic; i : in std_ulogic);
end component;
component ut130hbd_toutpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_ulogic; i, en : in std_ulogic);
end component;
component ut130hbd_lvds_combo
generic (voltage : integer := 0; width : integer := 1);
port (odpadp, odpadn, ospadp, ospadn : out std_logic_vector(0 to width-1);
odval, osval, en : in std_logic_vector(0 to width-1);
idpadp, idpadn, ispadp, ispadn : in std_logic_vector(0 to width-1);
idval, isval : out std_logic_vector(0 to width-1);
powerdown : in std_logic_vector(0 to width-1);
powerdownrx : in std_logic_vector(0 to width-1);
lvdsref : out std_logic);
end component;
component ut90nhbd_inpad is
generic (
level : integer := 0;
voltage : integer := 0;
filter : integer := 0);
port (
pad : in std_ulogic;
o : out std_ulogic);
end component;
component ut90nhbd_iopad is
generic(
level : integer := 0;
slew : integer := 0;
voltage : integer := 0;
strength : integer := 0);
port(
pad : inout std_ulogic;
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic;
slewctrl : in std_ulogic);
end component;
component ut90nhbd_outpad is
generic (
level : integer := 0;
slew : integer := 0;
voltage : integer := 0;
strength : integer := 0);
port(
pad : out std_ulogic;
i : in std_ulogic;
slewctrl : in std_ulogic);
end component;
component ut90nhbd_toutpad is
generic (
level : integer := 0;
slew : integer := 0;
voltage : integer := 0;
strength : integer := 0);
port (
pad : out std_ulogic;
i : in std_ulogic;
en : in std_ulogic;
slewctrl : in std_ulogic);
end component;
component rhumc_lvds_combo
generic (voltage : integer := 0; width : integer := 1);
port (odpadp, odpadn, ospadp, ospadn : out std_logic_vector(0 to width-1);
odval, osval, en : in std_logic_vector(0 to width-1);
idpadp, idpadn, ispadp, ispadn : in std_logic_vector(0 to width-1);
idval, isval : out std_logic_vector(0 to width-1);
powerdown : in std_logic_vector(0 to width-1);
powerdownrx : in std_logic_vector(0 to width-1);
lvdsref : out std_logic);
end component;
component umc_lvds_combo
generic (voltage : integer := 0; width : integer := 1);
port (odpadp, odpadn, ospadp, ospadn : out std_logic_vector(0 to width-1);
odval, osval, en : in std_logic_vector(0 to width-1);
idpadp, idpadn, ispadp, ispadn : in std_logic_vector(0 to width-1);
idval, isval : out std_logic_vector(0 to width-1);
lvdsref : in std_logic);
end component;
component peregrine_inpad is
generic (level : integer := 0; voltage : integer := 0; filter : integer := 0;
strength : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic);
end component;
component peregrine_iopad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end component;
component peregrine_toutpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_ulogic; i, en : in std_ulogic);
end component;
component nextreme_inpad
generic (level : integer := 0; voltage : integer := 0);
port (pad : in std_logic; o : out std_logic);
end component;
component nextreme_iopad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
end component;
component nextreme_toutpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i, en : in std_logic);
end component;
component atc18rha_inpad
generic (level : integer := 0; voltage : integer := 0);
port (pad : in std_logic; o : out std_logic);
end component;
component atc18rha_iopad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
end component;
component atc18rha_outpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i : in std_logic);
end component;
component atc18rha_odpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i : in std_logic);
end component;
component atc18rha_toutpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i, en : in std_logic);
end component;
component atc18rha_clkpad
generic (level : integer := 0; voltage : integer := 0);
port (pad : in std_logic; o : out std_logic);
end component;
constant n2x_padcontrol_bits: integer := 22;
constant n2x_padcontrol_none: std_logic_vector(n2x_padcontrol_bits-1 downto 0) := (others => '0');
component n2x_inpad
generic (level : integer := 0; voltage : integer := x33v; reg : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic;
clk : in std_ulogic := '0'; rstn : in std_ulogic := '0');
end component;
component n2x_iopad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
reg : integer := 0);
port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic;
compen, compupd: in std_ulogic;
pcomp, ncomp: in std_logic_vector(4 downto 0);
pslew, nslew: in std_logic_vector(3 downto 0);
clk : in std_ulogic := '0'; rstn : in std_ulogic := '0');
end component;
component n2x_outpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 12;
reg : integer := 0);
port (pad : out std_ulogic; i : in std_ulogic;
compen, compupd: in std_ulogic;
pcomp, ncomp: in std_logic_vector(4 downto 0);
pslew, nslew: in std_logic_vector(3 downto 0);
clk : in std_ulogic := '0'; rstn : in std_ulogic := '0');
end component;
component n2x_toutpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 12;
reg : integer := 0);
port (pad : out std_ulogic; i, en : in std_ulogic;
compen, compupd: in std_ulogic;
pcomp, ncomp: in std_logic_vector(4 downto 0);
pslew, nslew: in std_logic_vector(3 downto 0);
clk : in std_ulogic := '0'; rstn : in std_ulogic := '0');
end component;
component n2x_inpad_ds
generic (level : integer := lvds; voltage : integer := x33v);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end component;
component n2x_iopad_ds
generic (level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12);
port (padp, padn : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end component;
component n2x_outpad_ds
generic (level : integer := lvds; voltage : integer := x33v);
port (padp, padn : out std_ulogic; i : in std_ulogic);
end component;
component n2x_inpad_ddr
generic (level : integer := 0; voltage : integer := x33v);
port (pad : in std_ulogic; o1, o2 : out std_ulogic; c1, c2 : in std_ulogic;
ce : in std_ulogic; r : in std_ulogic; s : in std_ulogic);
end component;
component n2x_inpad_ddrv
generic (level : integer := 0; voltage : integer := x33v; width : integer := 1);
port (
pad : in std_logic_vector(width-1 downto 0);
o1, o2 : out std_logic_vector(width-1 downto 0);
c1, c2 : in std_ulogic; ce : in std_ulogic;
r : in std_ulogic; s : in std_ulogic);
end component;
component n2x_sdram_phy
generic (
level : integer := 0;
voltage : integer := x33v;
strength : integer := 12;
aw : integer := 15; -- # address bits
dw : integer := 32; -- # data bits
ncs : integer := 2;
reg : integer := 0); -- 1: include registers on all signals
port (
-- SDRAM interface
addr : out std_logic_vector(aw-1 downto 0);
dq : inout std_logic_vector(dw-1 downto 0);
cke : out std_logic_vector(ncs-1 downto 0);
sn : out std_logic_vector(ncs-1 downto 0);
wen : out std_ulogic;
rasn : out std_ulogic;
casn : out std_ulogic;
dqm : out std_logic_vector(dw/8-1 downto 0);
-- Interface toward memory controller
laddr : in std_logic_vector(aw-1 downto 0);
ldq_din : out std_logic_vector(dw-1 downto 0);
ldq_dout : in std_logic_vector(dw-1 downto 0);
ldq_oen : in std_logic_vector(dw-1 downto 0);
lcke : in std_logic_vector(ncs-1 downto 0);
lsn : in std_logic_vector(ncs-1 downto 0);
lwen : in std_ulogic;
lrasn : in std_ulogic;
lcasn : in std_ulogic;
ldqm : in std_logic_vector(dw/8-1 downto 0);
-- Only used when reg generic is non-zero
rstn : in std_ulogic; -- Registered pads reset
clk : in std_ulogic; -- SDRAM clock for registered pads
-- Optional pad configuration inputs
cfgi_cmd : in std_logic_vector(19 downto 0) := "00000000000000000000"; -- CMD pads
cfgi_dq : in std_logic_vector(19 downto 0) := "00000000000000000000" -- DQ pads
);
end component;
end;
| gpl-3.0 | b9d3a4f7e983c1e30624d1bb1d6f8e4b | 0.634148 | 3.423879 | false | false | false | false |
yishinli/emc2 | src/hal/drivers/mesa-hostmot2/firmware/src/irqlogic.vhd | 1 | 5,161 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
-- http://www.mesanet.com
--
-- This program is is licensed under a disjunctive dual license giving you
-- the choice of one of the two following sets of free software/open source
-- licensing terms:
--
-- * GNU General Public License (GPL), version 2.0 or later
-- * 3-clause BSD License
--
--
-- The GNU GPL License:
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- The 3-clause BSD License:
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- * Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- * Neither the name of Mesa Electronics nor the names of its
-- contributors may be used to endorse or promote products
-- derived from this software without specific prior written
-- permission.
--
--
-- Disclaimer:
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
entity irqlogic is
generic (
buswidth : integer;
dividerwidth : integer
);
port (
clk : in std_logic;
ibus : in std_logic_vector (buswidth-1 downto 0);
obus : out std_logic_vector (buswidth-1 downto 0);
loaddiv : in std_logic;
readdiv : in std_logic;
loadstatus : in std_logic;
readstatus : in std_logic;
clear : in std_logic;
ratesource : in std_logic_vector (7 downto 0);
int : out std_logic);
end irqlogic;
architecture Behavioral of irqlogic is
signal irqdiv : std_logic_vector (dividerwidth-1 downto 0);
alias irqdivmsb : std_logic is irqdiv(dividerwidth-1);
signal divlatch : std_logic_vector (dividerwidth-1 downto 0);
signal statusreg : std_logic_vector(4 downto 0);
alias mask : std_logic is statusreg(1);
alias irqff : std_logic is statusreg(0);
alias ratesel : std_logic_vector(2 downto 0) is statusreg(4 downto 2);
signal rated : std_logic_vector(1 downto 0);
signal rate : std_logic;
begin
PeriodicIRQlogic : process (clk,statusreg,irqff,readstatus, readdiv, divlatch)
begin
if rising_edge(clk) then
rated <= rated(0) & rate;
if loadstatus = '1' then
statusreg <= ibus(4 downto 0);
end if;
if loaddiv = '1' then
divlatch <= ibus(dividerwidth-1 downto 0);
irqdiv <= ibus(dividerwidth-1 downto 0);
end if;
if rated = "10" then -- falling edge of rate source
if irqdivmsb = '1' then -- note special case where divider latch MSB is set = divide by 1
irqdiv <= divlatch;
irqff <= '1';
else
irqdiv <= irqdiv -1;
end if;
end if; -- rate falling edge
if clear = '1' then
irqff <= '0';
end if;
end if; -- (clk)
obus <= (others => 'Z');
if readstatus = '1' then
obus(4 downto 0) <= statusreg;
obus(buswidth-1 downto 5) <= (others => '0');
end if;
if readdiv = '1' then
obus(dividerwidth-1 downto 0) <= divlatch;
obus(buswidth-1 downto dividerwidth) <= (others => '0');
end if;
int <= not (irqff and mask);
rate <= ratesource(CONV_INTEGER(ratesel)); -- we chose ratesource from appropriate PWM ref gen bit
end process;
end Behavioral;
| lgpl-2.1 | 7750ae2d758ba3322b4da72c99171da5 | 0.670606 | 3.678546 | false | false | false | false |
18545/FPGA | src/debounce.vhd | 1 | 913 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Description: Convert the push button to a 1PPS that can be used to restart
-- camera initialisation
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity debounce is
Port ( clk : in STD_LOGIC;
i : in STD_LOGIC;
o : out STD_LOGIC);
end debounce;
architecture Behavioral of debounce is
signal c : unsigned(23 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if i = '1' then
if c = x"FFFFFF" then
o <= '1';
else
o <= '0';
end if;
c <= c+1;
else
c <= (others => '0');
o <= '0';
end if;
end if;
end process;
end Behavioral;
| mit | c11ca6da6f19284d74afd8818b55037f | 0.454545 | 3.741803 | false | false | false | false |
firecake/IRIS | FPGA/VHDL/ipcore_dir/RAM/simulation/bmg_stim_gen.vhd | 1 | 16,231 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For TDP
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For TDP
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_TDP IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_TDP;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_TDP IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLKA : IN STD_LOGIC;
CLKB : IN STD_LOGIC;
TB_RST : IN STD_LOGIC;
ADDRA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
WEB : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
ADDRB : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
DINB : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC_VECTOR(1 DOWNTO 0):=(OTHERS => '0')
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
CONSTANT ADDR_ZERO : STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
CONSTANT DATA_PART_CNT_A : INTEGER:= DIVROUNDUP(32,32);
CONSTANT DATA_PART_CNT_B : INTEGER:= DIVROUNDUP(32,32);
SIGNAL WRITE_ADDR_A : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_B : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT_A : STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT_A : STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT_B : STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT_B : STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_A : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_B : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINB_INT : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL MAX_COUNT : STD_LOGIC_VECTOR(10 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(4096,11);
SIGNAL DO_WRITE_A : STD_LOGIC := '0';
SIGNAL DO_READ_A : STD_LOGIC := '0';
SIGNAL DO_WRITE_B : STD_LOGIC := '0';
SIGNAL DO_READ_B : STD_LOGIC := '0';
SIGNAL COUNT_NO : STD_LOGIC_VECTOR (10 DOWNTO 0):=(OTHERS => '0');
SIGNAL DO_READ_RA : STD_LOGIC := '0';
SIGNAL DO_READ_RB : STD_LOGIC := '0';
SIGNAL DO_READ_REG_A: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
SIGNAL DO_READ_REG_B: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
SIGNAL COUNT : integer := 0;
SIGNAL COUNT_B : integer := 0;
CONSTANT WRITE_CNT_A : integer := 6;
CONSTANT READ_CNT_A : integer := 6;
CONSTANT WRITE_CNT_B : integer := 4;
CONSTANT READ_CNT_B : integer := 4;
signal porta_wr_rd : std_logic:='0';
signal portb_wr_rd : std_logic:='0';
signal porta_wr_rd_complete: std_logic:='0';
signal portb_wr_rd_complete: std_logic:='0';
signal incr_cnt : std_logic :='0';
signal incr_cnt_b : std_logic :='0';
SIGNAL PORTB_WR_RD_HAPPENED: STD_LOGIC :='0';
SIGNAL LATCH_PORTA_WR_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_L1 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_L2 :STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_R1 :STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_R2 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_HAPPENED: STD_LOGIC :='0';
SIGNAL LATCH_PORTB_WR_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_L1 :STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_L2 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_R1 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_R2 :STD_LOGIC :='0';
BEGIN
WRITE_ADDR_INT_A(11 DOWNTO 0) <= WRITE_ADDR_A(11 DOWNTO 0);
READ_ADDR_INT_A(11 DOWNTO 0) <= READ_ADDR_A(11 DOWNTO 0);
ADDRA <= IF_THEN_ELSE(DO_WRITE_A='1',WRITE_ADDR_INT_A,READ_ADDR_INT_A) ;
WRITE_ADDR_INT_B(11 DOWNTO 0) <= WRITE_ADDR_B(11 DOWNTO 0);
--To avoid collision during idle period, negating the read_addr of port A
READ_ADDR_INT_B(11 DOWNTO 0) <= IF_THEN_ELSE( (DO_WRITE_B='0' AND DO_READ_B='0'),ADDR_ZERO,READ_ADDR_B(11 DOWNTO 0));
ADDRB <= IF_THEN_ELSE(DO_WRITE_B='1',WRITE_ADDR_INT_B,READ_ADDR_INT_B) ;
DINA <= DINA_INT ;
DINB <= DINB_INT ;
CHECK_DATA(0) <= DO_READ_A;
CHECK_DATA(1) <= DO_READ_B;
RD_ADDR_GEN_INST_A:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 4096,
RST_INC => 1 )
PORT MAP(
CLK => CLKA,
RST => TB_RST,
EN => DO_READ_A,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR_A
);
WR_ADDR_GEN_INST_A:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH =>4096 ,
RST_INC => 1 )
PORT MAP(
CLK => CLKA,
RST => TB_RST,
EN => DO_WRITE_A,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR_A
);
RD_ADDR_GEN_INST_B:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 4096 ,
RST_INC => 1 )
PORT MAP(
CLK => CLKB,
RST => TB_RST,
EN => DO_READ_B,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR_B
);
WR_ADDR_GEN_INST_B:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 4096 ,
RST_INC => 1 )
PORT MAP(
CLK => CLKB,
RST => TB_RST,
EN => DO_WRITE_B,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR_B
);
WR_DATA_GEN_INST_A:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>32,
DOUT_WIDTH => 32,
DATA_PART_CNT => 1,
SEED => 2)
PORT MAP (
CLK =>CLKA,
RST => TB_RST,
EN => DO_WRITE_A,
DATA_OUT => DINA_INT
);
WR_DATA_GEN_INST_B:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>32,
DOUT_WIDTH =>32 ,
DATA_PART_CNT =>1,
SEED => 2)
PORT MAP (
CLK =>CLKB,
RST => TB_RST,
EN => DO_WRITE_B,
DATA_OUT => DINB_INT
);
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
LATCH_PORTB_WR_RD_COMPLETE<='0';
ELSIF(PORTB_WR_RD_COMPLETE='1') THEN
LATCH_PORTB_WR_RD_COMPLETE <='1';
ELSIF(PORTA_WR_RD_HAPPENED='1') THEN
LATCH_PORTB_WR_RD_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTB_WR_RD_L1 <='0';
PORTB_WR_RD_L2 <='0';
ELSE
PORTB_WR_RD_L1 <= LATCH_PORTB_WR_RD_COMPLETE;
PORTB_WR_RD_L2 <= PORTB_WR_RD_L1;
END IF;
END IF;
END PROCESS;
PORTA_WR_RD_EN: PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTA_WR_RD <='1';
ELSE
PORTA_WR_RD <= PORTB_WR_RD_L2;
END IF;
END IF;
END PROCESS;
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTA_WR_RD_R1 <='0';
PORTA_WR_RD_R2 <='0';
ELSE
PORTA_WR_RD_R1 <=PORTA_WR_RD;
PORTA_WR_RD_R2 <=PORTA_WR_RD_R1;
END IF;
END IF;
END PROCESS;
PORTA_WR_RD_HAPPENED <= PORTA_WR_RD_R2;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
LATCH_PORTA_WR_RD_COMPLETE<='0';
ELSIF(PORTA_WR_RD_COMPLETE='1') THEN
LATCH_PORTA_WR_RD_COMPLETE <='1';
ELSIF(PORTB_WR_RD_HAPPENED='1') THEN
LATCH_PORTA_WR_RD_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTA_WR_RD_L1 <='0';
PORTA_WR_RD_L2 <='0';
ELSE
PORTA_WR_RD_L1 <= LATCH_PORTA_WR_RD_COMPLETE;
PORTA_WR_RD_L2 <= PORTA_WR_RD_L1;
END IF;
END IF;
END PROCESS;
PORTB_EN: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTB_WR_RD <='0';
ELSE
PORTB_WR_RD <= PORTA_WR_RD_L2;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTB_WR_RD_R1 <='0';
PORTB_WR_RD_R2 <='0';
ELSE
PORTB_WR_RD_R1 <=PORTB_WR_RD;
PORTB_WR_RD_R2 <=PORTB_WR_RD_R1;
END IF;
END IF;
END PROCESS;
---double registered of porta complete on portb clk
PORTB_WR_RD_HAPPENED <= PORTB_WR_RD_R2;
PORTA_WR_RD_COMPLETE <= '1' when count=(WRITE_CNT_A+READ_CNT_A) else '0';
start_counter: process(clka)
begin
if(rising_edge(clka)) then
if(TB_RST='1') then
incr_cnt <= '0';
elsif(porta_wr_rd ='1') then
incr_cnt <='1';
elsif(porta_wr_rd_complete='1') then
incr_cnt <='0';
end if;
end if;
end process;
COUNTER: process(clka)
begin
if(rising_edge(clka)) then
if(TB_RST='1') then
count <= 0;
elsif(incr_cnt='1') then
count<=count+1;
end if;
if(count=(WRITE_CNT_A+READ_CNT_A)) then
count<=0;
end if;
end if;
end process;
DO_WRITE_A<='1' when (count <WRITE_CNT_A and incr_cnt='1') else '0';
DO_READ_A <='1' when (count >WRITE_CNT_A and incr_cnt='1') else '0';
PORTB_WR_RD_COMPLETE <= '1' when count_b=(WRITE_CNT_B+READ_CNT_B) else '0';
startb_counter: process(clkb)
begin
if(rising_edge(clkb)) then
if(TB_RST='1') then
incr_cnt_b <= '0';
elsif(portb_wr_rd ='1') then
incr_cnt_b <='1';
elsif(portb_wr_rd_complete='1') then
incr_cnt_b <='0';
end if;
end if;
end process;
COUNTER_B: process(clkb)
begin
if(rising_edge(clkb)) then
if(TB_RST='1') then
count_b <= 0;
elsif(incr_cnt_b='1') then
count_b<=count_b+1;
end if;
if(count_b=WRITE_CNT_B+READ_CNT_B) then
count_b<=0;
end if;
end if;
end process;
DO_WRITE_B<='1' when (count_b <WRITE_CNT_B and incr_cnt_b='1') else '0';
DO_READ_B <='1' when (count_b >WRITE_CNT_B and incr_cnt_b='1') else '0';
BEGIN_SHIFT_REG_A: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_TDP
PORT MAP(
Q => DO_READ_REG_A(0),
CLK =>CLKA,
RST=>TB_RST,
D =>DO_READ_A
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_TDP
PORT MAP(
Q => DO_READ_REG_A(I),
CLK =>CLKA,
RST=>TB_RST,
D =>DO_READ_REG_A(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG_A;
BEGIN_SHIFT_REG_B: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_TDP
PORT MAP(
Q => DO_READ_REG_B(0),
CLK =>CLKB,
RST=>TB_RST,
D =>DO_READ_B
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_TDP
PORT MAP(
Q => DO_READ_REG_B(I),
CLK =>CLKB,
RST=>TB_RST,
D =>DO_READ_REG_B(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG_B;
REGCEA_PROCESS: PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
DO_READ_RA <= '0';
ELSE
DO_READ_RA <= DO_READ_A;
END IF;
END IF;
END PROCESS;
REGCEB_PROCESS: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
DO_READ_RB <= '0';
ELSE
DO_READ_RB <= DO_READ_B;
END IF;
END IF;
END PROCESS;
---REGCEB SHOULD BE SET AT THE CORE OUTPUT REGISTER/EMBEEDED OUTPUT REGISTER
--- WHEN CORE OUTPUT REGISTER IS SET REGCE SHOUD BE SET TO '1' WHEN THE READ DATA IS AVAILABLE AT THE CORE OUTPUT REGISTER
--WHEN CORE OUTPUT REGISTER IS '0' AND OUTPUT_PRIMITIVE_REG ='1', REGCE SHOULD BE SET WHEN THE DATA IS AVAILABLE AT THE PRIMITIVE OUTPUT REGISTER.
-- HERE, TO GENERAILIZE REGCE IS ASSERTED
WEA(0) <= IF_THEN_ELSE(DO_WRITE_A='1','1','0') ;
WEB(0) <= IF_THEN_ELSE(DO_WRITE_B='1','1','0') ;
END ARCHITECTURE;
| gpl-3.0 | 334db8d724ca9fc0870e9df8b2e6966f | 0.556528 | 3.21597 | false | false | false | false |
yishinli/emc2 | src/hal/drivers/m5i20/hostmot5_src/wordpr24.vhd | 1 | 1,328 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity wordpr24 is
Port (
clear: in STD_LOGIC;
clk: in STD_LOGIC;
ibus: in STD_LOGIC_VECTOR (23 downto 0);
obus: out STD_LOGIC_VECTOR (23 downto 0);
loadport: in STD_LOGIC;
loadddr: in STD_LOGIC;
readddr: in STD_LOGIC;
portdata: out STD_LOGIC_VECTOR (23 downto 0)
);
end wordpr24;
architecture behavioral of wordpr24 is
signal outreg: STD_LOGIC_VECTOR (23 downto 0);
signal ddrreg: STD_LOGIC_VECTOR (23 downto 0);
signal tsoutreg: STD_LOGIC_VECTOR (23 downto 0);
begin
awordioport: process (
clk,
ibus,
loadport,
loadddr,
readddr,
outreg,ddrreg)
begin
if clk'event and clk = '1' then
if loadport = '1' then
outreg <= ibus;
end if;
if loadddr = '1' then
ddrreg <= ibus;
end if;
if clear = '1' then ddrreg <= x"000000"; end if;
end if; -- clk
for i in 0 to 23 loop
if ddrreg(i) = '1' then
tsoutreg(i) <= outreg(i);
else
tsoutreg(i) <= 'Z';
end if;
end loop;
portdata <= tsoutreg;
if readddr = '1' then
obus <= ddrreg;
else
obus <= "ZZZZZZZZZZZZZZZZZZZZZZZZ";
end if;
end process;
end behavioral;
| lgpl-2.1 | 2066d74b715630b863c55dc58e37948c | 0.591114 | 2.899563 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/cycloneiii/cycloneiii_ddr_phy.vhd | 1 | 22,061 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: cycloneiii_ddr_phy
-- File: cycloneiii_ddr_phy.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: DDR PHY for Altera FPGAs
------------------------------------------------------------------------------
LIBRARY cycloneiii;
USE cycloneiii.all;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY altdqs_cyciii_adqs_n7i2 IS
generic (width : integer := 2; period : string := "10000ps");
PORT
(
dll_delayctrlout : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
dqinclk : OUT STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_h : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_l : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_padio : INOUT STD_LOGIC_VECTOR (width-1 downto 0);
dqsundelayedout : OUT STD_LOGIC_VECTOR (width-1 downto 0);
inclk : IN STD_LOGIC := '0';
oe : IN STD_LOGIC_VECTOR (width-1 downto 0) := (OTHERS => '1');
outclk : IN STD_LOGIC_VECTOR (width-1 downto 0);
outclkena : IN STD_LOGIC_VECTOR (width-1 downto 0) := (OTHERS => '1')
);
END altdqs_cyciii_adqs_n7i2;
ARCHITECTURE RTL OF altdqs_cyciii_adqs_n7i2 IS
-- ATTRIBUTE synthesis_clearbox : boolean;
-- ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS true;
SIGNAL wire_cyciii_dll1_delayctrlout : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_cyciii_dll1_dqsupdate : STD_LOGIC;
SIGNAL wire_cyciii_dll1_offsetctrlout : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_cyciii_io2a_combout : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_cyciii_io2a_datain : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_cyciii_io2a_ddiodatain : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_cyciii_io2a_dqsbusout : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_cyciii_io2a_oe : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_cyciii_io2a_outclk : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_cyciii_io2a_outclkena : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL delay_ctrl : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL dqs_update : STD_LOGIC;
SIGNAL offset_ctrl : STD_LOGIC_VECTOR (5 DOWNTO 0);
COMPONENT cycloneiii_dll
GENERIC
(
DELAY_BUFFER_MODE : STRING := "low";
DELAY_CHAIN_LENGTH : NATURAL := 12;
DELAYCTRLOUT_MODE : STRING := "normal";
INPUT_FREQUENCY : STRING;
JITTER_REDUCTION : STRING := "false";
OFFSETCTRLOUT_MODE : STRING := "static";
SIM_LOOP_DELAY_INCREMENT : NATURAL := 0;
SIM_LOOP_INTRINSIC_DELAY : NATURAL := 0;
SIM_VALID_LOCK : NATURAL := 5;
SIM_VALID_LOCKCOUNT : NATURAL := 0;
STATIC_DELAY_CTRL : NATURAL := 0;
STATIC_OFFSET : STRING;
USE_UPNDNIN : STRING := "false";
USE_UPNDNINCLKENA : STRING := "false";
lpm_type : STRING := "cycloneiii_dll"
);
PORT
(
addnsub : IN STD_LOGIC := '1';
aload : IN STD_LOGIC := '0';
clk : IN STD_LOGIC;
delayctrlout : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
dqsupdate : OUT STD_LOGIC;
offset : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
offsetctrlout : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
upndnin : IN STD_LOGIC := '0';
upndninclkena : IN STD_LOGIC := '1';
upndnout : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT cycloneiii_io
GENERIC
(
BUS_HOLD : STRING := "false";
DDIO_MODE : STRING := "none";
DDIOINCLK_INPUT : STRING := "negated_inclk";
DQS_CTRL_LATCHES_ENABLE : STRING := "false";
DQS_DELAY_BUFFER_MODE : STRING := "none";
DQS_EDGE_DETECT_ENABLE : STRING := "false";
DQS_INPUT_FREQUENCY : STRING := "unused";
DQS_OFFSETCTRL_ENABLE : STRING := "false";
DQS_OUT_MODE : STRING := "none";
DQS_PHASE_SHIFT : NATURAL := 0;
EXTEND_OE_DISABLE : STRING := "false";
GATED_DQS : STRING := "false";
INCLK_INPUT : STRING := "normal";
INPUT_ASYNC_RESET : STRING := "none";
INPUT_POWER_UP : STRING := "low";
INPUT_REGISTER_MODE : STRING := "none";
INPUT_SYNC_RESET : STRING := "none";
OE_ASYNC_RESET : STRING := "none";
OE_POWER_UP : STRING := "low";
OE_REGISTER_MODE : STRING := "none";
OE_SYNC_RESET : STRING := "none";
OPEN_DRAIN_OUTPUT : STRING := "false";
OPERATION_MODE : STRING;
OUTPUT_ASYNC_RESET : STRING := "none";
OUTPUT_POWER_UP : STRING := "low";
OUTPUT_REGISTER_MODE : STRING := "none";
OUTPUT_SYNC_RESET : STRING := "none";
SIM_DQS_DELAY_INCREMENT : NATURAL := 0;
SIM_DQS_INTRINSIC_DELAY : NATURAL := 0;
SIM_DQS_OFFSET_INCREMENT : NATURAL := 0;
TIE_OFF_OE_CLOCK_ENABLE : STRING := "false";
TIE_OFF_OUTPUT_CLOCK_ENABLE : STRING := "false";
lpm_type : STRING := "cycloneiii_io"
);
PORT
(
areset : IN STD_LOGIC := '0';
combout : OUT STD_LOGIC;
datain : IN STD_LOGIC := '0';
ddiodatain : IN STD_LOGIC := '0';
ddioinclk : IN STD_LOGIC := '0';
ddioregout : OUT STD_LOGIC;
delayctrlin : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
dqsbusout : OUT STD_LOGIC;
dqsupdateen : IN STD_LOGIC := '1';
inclk : IN STD_LOGIC := '0';
inclkena : IN STD_LOGIC := '1';
linkin : IN STD_LOGIC := '0';
linkout : OUT STD_LOGIC;
oe : IN STD_LOGIC := '1';
offsetctrlin : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
outclk : IN STD_LOGIC := '0';
outclkena : IN STD_LOGIC := '1';
padio : INOUT STD_LOGIC;
regout : OUT STD_LOGIC;
sreset : IN STD_LOGIC := '0';
terminationcontrol : IN STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
BEGIN
delay_ctrl <= wire_cyciii_dll1_delayctrlout;
dll_delayctrlout <= delay_ctrl;
dqinclk <= wire_cyciii_io2a_dqsbusout;
dqs_update <= wire_cyciii_dll1_dqsupdate;
dqsundelayedout <= wire_cyciii_io2a_combout;
offset_ctrl <= wire_cyciii_dll1_offsetctrlout;
cyciii_dll1 : cycloneiii_dll
GENERIC MAP (
DELAY_BUFFER_MODE => "low",
DELAY_CHAIN_LENGTH => 12,
DELAYCTRLOUT_MODE => "normal",
INPUT_FREQUENCY => period, --"10000ps",
JITTER_REDUCTION => "false",
OFFSETCTRLOUT_MODE => "static",
SIM_LOOP_DELAY_INCREMENT => 132,
SIM_LOOP_INTRINSIC_DELAY => 3840,
SIM_VALID_LOCK => 1,
SIM_VALID_LOCKCOUNT => 46,
STATIC_OFFSET => "0",
USE_UPNDNIN => "false",
USE_UPNDNINCLKENA => "false"
)
PORT MAP (
clk => inclk,
delayctrlout => wire_cyciii_dll1_delayctrlout,
dqsupdate => wire_cyciii_dll1_dqsupdate,
offsetctrlout => wire_cyciii_dll1_offsetctrlout
);
wire_cyciii_io2a_datain <= dqs_datain_h;
wire_cyciii_io2a_ddiodatain <= dqs_datain_l;
wire_cyciii_io2a_oe <= oe;
wire_cyciii_io2a_outclk <= outclk;
wire_cyciii_io2a_outclkena <= outclkena;
loop0 : FOR i IN 0 TO width-1 GENERATE
cyciii_io2a : cycloneiii_io
GENERIC MAP (
DDIO_MODE => "output",
DQS_CTRL_LATCHES_ENABLE => "true",
DQS_DELAY_BUFFER_MODE => "low",
DQS_EDGE_DETECT_ENABLE => "false",
DQS_INPUT_FREQUENCY => period, --"10000ps",
DQS_OFFSETCTRL_ENABLE => "true",
DQS_OUT_MODE => "delay_chain3",
DQS_PHASE_SHIFT => 9000,
EXTEND_OE_DISABLE => "false",
GATED_DQS => "false",
OE_ASYNC_RESET => "none",
OE_POWER_UP => "low",
OE_REGISTER_MODE => "register",
OE_SYNC_RESET => "none",
OPEN_DRAIN_OUTPUT => "false",
OPERATION_MODE => "bidir",
OUTPUT_ASYNC_RESET => "none",
OUTPUT_POWER_UP => "low",
OUTPUT_REGISTER_MODE => "register",
OUTPUT_SYNC_RESET => "none",
SIM_DQS_DELAY_INCREMENT => 22,
SIM_DQS_INTRINSIC_DELAY => 960,
SIM_DQS_OFFSET_INCREMENT => 11,
TIE_OFF_OE_CLOCK_ENABLE => "false",
TIE_OFF_OUTPUT_CLOCK_ENABLE => "false"
)
PORT MAP (
combout => wire_cyciii_io2a_combout(i),
datain => wire_cyciii_io2a_datain(i),
ddiodatain => wire_cyciii_io2a_ddiodatain(i),
delayctrlin => delay_ctrl,
dqsbusout => wire_cyciii_io2a_dqsbusout(i),
dqsupdateen => dqs_update,
oe => wire_cyciii_io2a_oe(i),
offsetctrlin => offset_ctrl,
outclk => wire_cyciii_io2a_outclk(i),
outclkena => wire_cyciii_io2a_outclkena(i),
padio => dqs_padio(i)
);
END GENERATE loop0;
END RTL; --altdqs_cyciii_adqs_n7i2
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY altdqs_cyciii IS
generic (width : integer := 2; period : string := "10000ps");
PORT
(
dqs_datain_h : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_l : IN STD_LOGIC_VECTOR (width-1 downto 0);
inclk : IN STD_LOGIC ;
oe : IN STD_LOGIC_VECTOR (width-1 downto 0);
outclk : IN STD_LOGIC_VECTOR (width-1 downto 0);
dll_delayctrlout : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
dqinclk : OUT STD_LOGIC_VECTOR (width-1 downto 0);
dqs_padio : INOUT STD_LOGIC_VECTOR (width-1 downto 0);
dqsundelayedout : OUT STD_LOGIC_VECTOR (width-1 downto 0)
);
END;
ARCHITECTURE RTL OF altdqs_cyciii IS
-- ATTRIBUTE synthesis_clearbox: boolean;
-- ATTRIBUTE synthesis_clearbox OF RTL: ARCHITECTURE IS TRUE;
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL sub_wire3_bv : BIT_VECTOR (width-1 downto 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (width-1 downto 0);
COMPONENT altdqs_cyciii_adqs_n7i2
generic (width : integer := 2; period : string := "10000ps");
PORT (
outclk : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_padio : INOUT STD_LOGIC_VECTOR (width-1 downto 0);
outclkena : IN STD_LOGIC_VECTOR (width-1 downto 0);
oe : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_h : IN STD_LOGIC_VECTOR (width-1 downto 0);
inclk : IN STD_LOGIC ;
dqs_datain_l : IN STD_LOGIC_VECTOR (width-1 downto 0);
dll_delayctrlout : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
dqinclk : OUT STD_LOGIC_VECTOR (width-1 downto 0);
dqsundelayedout : OUT STD_LOGIC_VECTOR (width-1 downto 0)
);
END COMPONENT;
BEGIN
sub_wire3_bv(width-1 downto 0) <= (others => '1');
sub_wire3 <= To_stdlogicvector(sub_wire3_bv);
dll_delayctrlout <= sub_wire0(5 DOWNTO 0);
dqinclk <= not sub_wire1(width-1 downto 0);
dqsundelayedout <= sub_wire2(width-1 downto 0);
altdqs_cyciii_adqs_n7i2_component : altdqs_cyciii_adqs_n7i2
generic map (width, period)
PORT MAP (
outclk => outclk,
outclkena => sub_wire3,
oe => oe,
dqs_datain_h => dqs_datain_h,
inclk => inclk,
dqs_datain_l => dqs_datain_l,
dll_delayctrlout => sub_wire0,
dqinclk => sub_wire1,
dqsundelayedout => sub_wire2,
dqs_padio => dqs_padio
);
END RTL;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
------------------------------------------------------------------
-- CYCLONEIII DDR PHY --------------------------------------------
------------------------------------------------------------------
entity cycloneiii_ddr_phy is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end;
architecture rtl of cycloneiii_ddr_phy is
signal vcc, gnd, dqsn, oe, lockl : std_logic;
signal ddr_clk_fb_outr : std_ulogic;
signal ddr_clk_fbl, fbclk : std_ulogic;
signal ddr_rasnr, ddr_casnr, ddr_wenr : std_ulogic;
signal ddr_clkl, ddr_clkbl : std_logic_vector(2 downto 0);
signal ddr_csnr, ddr_ckenr, ckel : std_logic_vector(1 downto 0);
signal clk_0ro, clk_90ro, clk_180ro, clk_270ro : std_ulogic;
signal clk_0r, clk_90r, clk_180r, clk_270r : std_ulogic;
signal clk0r, clk90r, clk180r, clk270r : std_ulogic;
signal locked, vlockl, ddrclkfbl : std_ulogic;
signal clk4, clk5 : std_logic;
signal ddr_dqin : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqout : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqoen : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_adr : std_logic_vector (13 downto 0); -- ddr address
signal ddr_bar : std_logic_vector (1 downto 0); -- ddr address
signal ddr_dmr : std_logic_vector (dbits/8-1 downto 0); -- ddr address
signal ddr_dqsin : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoen : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoutl : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsdel, dqsclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal da : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dqinl : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dllrst : std_logic_vector(0 to 3);
signal dll0rst : std_logic_vector(0 to 3);
signal mlock, mclkfb, mclk, mclkfx, mclk0 : std_ulogic;
signal gndv : std_logic_vector (dbits-1 downto 0); -- ddr dqs
signal pclkout : std_logic_vector (5 downto 1);
signal ddr_clkin : std_logic_vector(0 to 2);
signal dqinclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsoclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsnv : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
component altdqs_cyciii
generic (width : integer := 2; period : string := "10000ps");
PORT
(
dqs_datain_h : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_l : IN STD_LOGIC_VECTOR (width-1 downto 0);
inclk : IN STD_LOGIC ;
oe : IN STD_LOGIC_VECTOR (width-1 downto 0);
outclk : IN STD_LOGIC_VECTOR (width-1 downto 0);
dll_delayctrlout : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
dqinclk : OUT STD_LOGIC_VECTOR (width-1 downto 0);
dqs_padio : INOUT STD_LOGIC_VECTOR (width-1 downto 0);
dqsundelayedout : OUT STD_LOGIC_VECTOR (width-1 downto 0)
);
END component;
type phasevec is array (1 to 3) of string(1 to 4);
type phasevecarr is array (10 to 13) of phasevec;
constant phasearr : phasevecarr := (
("2500", "5000", "7500"), ("2273", "4545", "6818"), -- 100 & 110 MHz
("2083", "4167", "6250"), ("1923", "3846", "5769")); -- 120 & 130 MHz
type periodtype is array (10 to 13) of string(1 to 6);
constant periodstr : periodtype := ("9999ps", "9090ps", "8333ps", "7692ps");
begin
oe <= not oen; vcc <= '1'; gnd <= '0'; gndv <= (others => '0');
mclk <= clk;
-- clkout <= clk_270r;
-- clkout <= clk_0r when DDR_FREQ >= 110 else clk_270r;
clkout <= clk_90r when DDR_FREQ > 120 else clk_0r;
clk0r <= clk_270r; clk90r <= clk_0r;
clk180r <= clk_90r; clk270r <= clk_180r;
dll : altpll
generic map (
intended_device_family => "CycloneIII",
operation_mode => "NORMAL",
inclk0_input_frequency => 1000000/MHz,
inclk1_input_frequency => 1000000/MHz,
clk4_multiply_by => clk_mul, clk4_divide_by => clk_div,
clk3_multiply_by => clk_mul, clk3_divide_by => clk_div,
clk2_multiply_by => clk_mul, clk2_divide_by => clk_div,
clk1_multiply_by => clk_mul, clk1_divide_by => clk_div,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk3_phase_shift => phasearr(DDR_FREQ/10)(3),
clk2_phase_shift => phasearr(DDR_FREQ/10)(2),
clk1_phase_shift => phasearr(DDR_FREQ/10)(1)
-- clk3_phase_shift => "6250", clk2_phase_shift => "4167", clk1_phase_shift => "2083"
-- clk3_phase_shift => "7500", clk2_phase_shift => "5000", clk1_phase_shift => "2500"
)
port map ( inclk(0) => mclk, inclk(1) => gnd, clk(0) => clk_0r,
clk(1) => clk_90r, clk(2) => clk_180r, clk(3) => clk_270r,
clk(4) => clk4, clk(5) => clk5, locked => lockl);
rstdel : process (mclk, rst, lockl)
begin
if rst = '0' then dllrst <= (others => '1');
elsif rising_edge(mclk) then
dllrst <= dllrst(1 to 3) & '0';
end if;
end process;
rdel : if rstdelay /= 0 generate
rcnt : process (clk_0r)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk_0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-- Generate external DDR clock
-- fbclkpad : altddio_out generic map (width => 1)
-- port map ( datain_h(0) => vcc, datain_l(0) => gnd,
-- outclock => clk90r, dataout(0) => ddr_clk_fb_out);
ddrclocks : for i in 0 to 2 generate
clkpad : altddio_out generic map (width => 1, INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h(0) => vcc, datain_l(0) => gnd,
outclock => clk90r, dataout(0) => ddr_clk(i));
clknpad : altddio_out generic map (width => 1, INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h(0) => gnd, datain_l(0) => vcc,
outclock => clk90r, dataout(0) => ddr_clkb(i));
end generate;
csnpads : altddio_out generic map (width => 2, INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h => csn(1 downto 0), datain_l => csn(1 downto 0),
outclock => clk0r, dataout => ddr_csb(1 downto 0));
ckepads : altddio_out generic map (width => 2, INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h => ckel(1 downto 0), datain_l => ckel(1 downto 0),
outclock => clk0r, dataout => ddr_cke(1 downto 0));
ddrbanks : for i in 0 to 1 generate
ckel(i) <= cke(i) and locked;
end generate;
rasnpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h(0) => rasn, datain_l(0) => rasn,
outclock => clk0r, dataout(0) => ddr_rasb);
casnpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h(0) => casn, datain_l(0) => casn,
outclock => clk0r, dataout(0) => ddr_casb);
wenpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h(0) => wen, datain_l(0) => wen,
outclock => clk0r, dataout(0) => ddr_web);
dmpads : altddio_out generic map (width => dbits/8,
INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map (
datain_h => dm(dbits/8*2-1 downto dbits/8),
datain_l => dm(dbits/8-1 downto 0),
outclock => clk0r, dataout => ddr_dm
);
bapads : altddio_out generic map (width => 2)
port map (
datain_h => ba, datain_l => ba,
outclock => clk0r, dataout => ddr_ba
);
addrpads : altddio_out generic map (width => 14)
port map (
datain_h => addr, datain_l => addr,
outclock => clk0r, dataout => ddr_ad
);
-- DQS generation
dqsnv <= (others => dqsn);
dqsoclk <= (others => clk90r);
altdqs0 : altdqs_cyciii generic map (dbits/8, periodstr(DDR_FREQ/10))
port map (dqs_datain_h => dqsnv, dqs_datain_l => gndv(dbits/8-1 downto 0),
inclk => clk270r, oe => ddr_dqsoen, outclk => dqsoclk,
dll_delayctrlout => open, dqinclk => dqinclk, dqs_padio => ddr_dqs,
dqsundelayedout => open );
-- Data bus
dqgen : for i in 0 to dbits/8-1 generate
qi : altddio_bidir generic map (width => 8, oe_reg =>"REGISTERED",
INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map (
datain_l => dqout(i*8+7 downto i*8),
datain_h => dqout(i*8+7+dbits downto dbits+i*8),
inclock => dqinclk(i), --clk270r,
outclock => clk0r, oe => oe,
dataout_h => dqin(i*8+7 downto i*8),
dataout_l => dqin(i*8+7+dbits downto dbits+i*8), --dqinl(i*8+7 downto i*8),
padio => ddr_dq(i*8+7 downto i*8));
end generate;
dqsreg : process(clk180r)
begin
if rising_edge(clk180r) then
dqsn <= oe;
end if;
end process;
oereg : process(clk0r)
begin
if rising_edge(clk0r) then
ddr_dqsoen(dbits/8-1 downto 0) <= (others => not dqsoen);
end if;
end process;
end;
| gpl-3.0 | f739e8a79cbc741288fe71c336fe84dd | 0.629663 | 2.972379 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/eth/core/greth_pkg.vhd | 1 | 24,186 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
package grethpkg is
--gigabit sync types
type data_sync_type is array (0 to 3) of std_logic_vector(31 downto 0);
type ctrl_sync_type is array (0 to 3) of std_logic_vector(1 downto 0);
constant HTRANS_IDLE: std_logic_vector(1 downto 0) := "00";
constant HTRANS_NONSEQ: std_logic_vector(1 downto 0) := "10";
constant HTRANS_SEQ: std_logic_vector(1 downto 0) := "11";
constant HBURST_INCR: std_logic_vector(2 downto 0) := "001";
constant HSIZE_WORD: std_logic_vector(2 downto 0) := "010";
constant HRESP_OKAY: std_logic_vector(1 downto 0) := "00";
constant HRESP_ERROR: std_logic_vector(1 downto 0) := "01";
constant HRESP_RETRY: std_logic_vector(1 downto 0) := "10";
constant HRESP_SPLIT: std_logic_vector(1 downto 0) := "11";
--receiver constants
constant maxsizerx : std_logic_vector(15 downto 0) :=
conv_std_logic_vector(1500, 16);
constant minpload : std_logic_vector(10 downto 0) :=
conv_std_logic_vector(60, 11);
type ahb_fifo_in_type is record
renable : std_ulogic;
raddress : std_logic_vector(4 downto 0);
write : std_ulogic;
data : std_logic_vector(31 downto 0);
waddress : std_logic_vector(4 downto 0);
end record;
type ahb_fifo_out_type is record
data : std_logic_vector(31 downto 0);
end record;
type nchar_fifo_in_type is record
renable : std_ulogic;
raddress : std_logic_vector(5 downto 0);
write : std_ulogic;
data : std_logic_vector(8 downto 0);
waddress : std_logic_vector(5 downto 0);
end record;
type nchar_fifo_out_type is record
data : std_logic_vector(8 downto 0);
end record;
type rmapbuf_in_type is record
renable : std_ulogic;
raddress : std_logic_vector(7 downto 0);
write : std_ulogic;
data : std_logic_vector(7 downto 0);
waddress : std_logic_vector(7 downto 0);
end record;
type rmapbuf_out_type is record
data : std_logic_vector(7 downto 0);
end record;
type ahbc_mst_in_type is record
hgrant : std_ulogic; -- bus grant
hready : std_ulogic; -- transfer done
hresp : std_logic_vector(1 downto 0); -- response type
hrdata : std_logic_vector(31 downto 0); -- read data bus
end record;
type ahbc_mst_out_type is record
hbusreq : std_ulogic; -- bus request
hlock : std_ulogic; -- lock request
htrans : std_logic_vector(1 downto 0); -- transfer type
haddr : std_logic_vector(31 downto 0); -- address bus (byte)
hwrite : std_ulogic; -- read/write
hsize : std_logic_vector(2 downto 0); -- transfer size
hburst : std_logic_vector(2 downto 0); -- burst type
hprot : std_logic_vector(3 downto 0); -- protection control
hwdata : std_logic_vector(31 downto 0); -- write data bus
end record;
type apbc_slv_in_type is record
psel : std_ulogic; -- slave select
penable : std_ulogic; -- strobe
paddr : std_logic_vector(31 downto 0); -- address bus (byte)
pwrite : std_ulogic; -- write
pwdata : std_logic_vector(31 downto 0); -- write data bus
end record;
type apbc_slv_out_type is record
prdata : std_logic_vector(31 downto 0); -- read data bus
end record;
type eth_tx_ahb_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
end record;
type eth_tx_ahb_out_type is record
grant : std_ulogic;
data : std_logic_vector(31 downto 0);
ready : std_ulogic;
error : std_ulogic;
retry : std_ulogic;
end record;
type eth_rx_ahb_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
end record;
type eth_rx_ahb_out_type is record
grant : std_ulogic;
ready : std_ulogic;
error : std_ulogic;
retry : std_ulogic;
data : std_logic_vector(31 downto 0);
end record;
type eth_rx_gbit_ahb_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
end record;
type gbit_host_tx_type is record
full_duplex : std_ulogic;
start : std_ulogic;
read_ack : std_ulogic;
data : std_logic_vector(31 downto 0);
datavalid : std_ulogic;
valid : std_ulogic;
len : std_logic_vector(10 downto 0);
rx_col : std_ulogic;
rx_crs : std_ulogic;
end record;
type gbit_tx_host_type is record
txd : std_logic_vector(3 downto 0);
tx_en : std_ulogic;
done : std_ulogic;
read : std_ulogic;
restart : std_ulogic;
status : std_logic_vector(1 downto 0);
end record;
type gbit_rx_host_type is record
sync_start : std_ulogic;
done : std_ulogic;
write : std_logic_vector(3 downto 0);
dataout : data_sync_type;
byte_count : std_logic_vector(10 downto 0);
status : std_logic_vector(3 downto 0);
gotframe : std_ulogic;
mcasthash : std_logic_vector(5 downto 0);
end record;
type gbit_host_rx_type is record
full_duplex : std_ulogic;
gbit : std_ulogic;
doneack : std_ulogic;
writeack : std_logic_vector(3 downto 0);
speed : std_ulogic;
writeok : std_logic_vector(3 downto 0);
rxenable : std_ulogic;
rxd : std_logic_vector(7 downto 0);
rx_dv : std_ulogic;
rx_er : std_ulogic;
rx_col : std_ulogic;
rx_crs : std_ulogic;
rx_en : std_ulogic;
end record;
type gbit_gtx_host_type is record
txd : std_logic_vector(7 downto 0);
tx_en : std_ulogic;
tx_er : std_ulogic;
done : std_ulogic;
restart : std_ulogic;
read : std_logic_vector(3 downto 0);
status : std_logic_vector(2 downto 0);
end record;
type gbit_host_gtx_type is record
rx_col : std_ulogic;
rx_crs : std_ulogic;
full_duplex : std_ulogic;
burstmode : std_ulogic;
txen : std_ulogic;
start_sync : std_ulogic;
readack : std_logic_vector(3 downto 0);
valid : std_logic_vector(3 downto 0);
data : data_sync_type;
len : std_logic_vector(10 downto 0);
end record;
type host_tx_type is record
rx_col : std_ulogic;
rx_crs : std_ulogic;
full_duplex : std_ulogic;
start : std_ulogic;
readack : std_ulogic;
speed : std_ulogic;
data : std_logic_vector(31 downto 0);
datavalid : std_ulogic;
valid : std_ulogic;
len : std_logic_vector(10 downto 0);
end record;
type tx_host_type is record
txd : std_logic_vector(3 downto 0);
tx_en : std_ulogic;
tx_er : std_ulogic;
done : std_ulogic;
read : std_ulogic;
restart : std_ulogic;
status : std_logic_vector(1 downto 0);
end record;
type rx_host_type is record
dataout : std_logic_vector(31 downto 0);
start : std_ulogic;
done : std_ulogic;
write : std_ulogic;
status : std_logic_vector(3 downto 0);
gotframe : std_ulogic;
byte_count : std_logic_vector(10 downto 0);
lentype : std_logic_vector(15 downto 0);
mcasthash : std_logic_vector(5 downto 0);
end record;
type host_rx_type is record
writeack : std_ulogic;
doneack : std_ulogic;
speed : std_ulogic;
writeok : std_ulogic;
rxd : std_logic_vector(3 downto 0);
rx_dv : std_ulogic;
rx_crs : std_ulogic;
rx_er : std_ulogic;
enable : std_ulogic;
rx_en : std_ulogic;
end record;
component greth_rx is
generic(
nsync : integer range 1 to 2 := 2;
rmii : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
maxsize : integer;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxi : in host_rx_type;
rxo : out rx_host_type
);
end component;
component greth_tx is
generic(
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
nsync : integer range 1 to 2 := 2;
rmii : integer range 0 to 1 := 0;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txi : in host_tx_type;
txo : out tx_host_type
);
end component;
component eth_rstgen is
generic(acthigh : integer := 0);
port (
rstin : in std_ulogic;
clk : in std_ulogic;
clklock : in std_ulogic;
rstout : out std_ulogic;
rstoutraw : out std_ulogic
);
end component;
component greth_gbit_tx is
generic(
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
nsync : integer range 1 to 2 := 2;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txi : in gbit_host_tx_type;
txo : out gbit_tx_host_type);
end component;
component greth_gbit_gtx is
generic(
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
nsync : integer range 1 to 2 := 2;
iotest : integer := 0);
port(
rst : in std_ulogic;
clk : in std_ulogic;
gtxi : in gbit_host_gtx_type;
gtxo : out gbit_gtx_host_type;
iotmact : in std_ulogic;
iotdata : in std_logic_vector(9 downto 0)
);
end component;
component greth_gbit_rx is
generic(
multicast : integer range 0 to 1 := 0;
nsync : integer range 1 to 2 := 2;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxi : in gbit_host_rx_type;
rxo : out gbit_rx_host_type;
iotdata : out std_logic_vector(9 downto 0));
end component;
component eth_ahb_mst is
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahbc_mst_in_type;
ahbmo : out ahbc_mst_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type;
rmsti : in eth_rx_ahb_in_type;
rmsto : out eth_rx_ahb_out_type
);
end component;
component eth_ahb_mst_gbit is
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahbc_mst_in_type;
ahbmo : out ahbc_mst_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type;
rmsti : in eth_rx_gbit_ahb_in_type;
rmsto : out eth_rx_ahb_out_type);
end component;
component eth_edcl_ahb_mst is
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahbc_mst_in_type;
ahbmo : out ahbc_mst_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type
);
end component;
function mirror(din : in std_logic_vector) return std_logic_vector;
function crc32_4(d : in std_logic_vector(3 downto 0);
crc : in std_logic_vector(31 downto 0))
return std_logic_vector;
function crc16_2(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(25 downto 0))
return std_logic_vector;
function crc16(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(15 downto 0))
return std_logic_vector;
function validlen(len : in std_logic_vector(10 downto 0);
bcnt : in std_logic_vector(10 downto 0);
usesz : in std_ulogic)
return std_ulogic;
function getfifosize(edcl, fifosize, ebufsize : in integer) return integer;
function setburstlength(fifosize : in integer) return integer;
function calccrc(d : in std_logic_vector(3 downto 0);
crc : in std_logic_vector(31 downto 0))
return std_logic_vector;
--16-bit one's complement adder
function crcadder(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(17 downto 0))
return std_logic_vector;
end package;
package body grethpkg is
function mirror(din : in std_logic_vector)
return std_logic_vector is
variable do : std_logic_vector(din'range);
begin
for i in 0 to din'length-1 loop
do(din'high-i) := din(i+din'low);
end loop;
return do;
end function;
function crc32_4(d : in std_logic_vector(3 downto 0);
crc : in std_logic_vector(31 downto 0))
return std_logic_vector is
variable ncrc : std_logic_vector(31 downto 0);
variable tc : std_logic_vector(3 downto 0);
begin
tc(0) := d(0) xor crc(31); tc(1) := d(1) xor crc(30);
tc(2) := d(2) xor crc(29); tc(3) := d(3) xor crc(28);
ncrc(31) := crc(27);
ncrc(30) := crc(26);
ncrc(29) := tc(0) xor crc(25);
ncrc(28) := tc(1) xor crc(24);
ncrc(27) := tc(2) xor crc(23);
ncrc(26) := tc(0) xor tc(3) xor crc(22);
ncrc(25) := tc(0) xor tc(1) xor crc(21);
ncrc(24) := tc(1) xor tc(2) xor crc(20);
ncrc(23) := tc(2) xor tc(3) xor crc(19);
ncrc(22) := tc(3) xor crc(18);
ncrc(21) := crc(17);
ncrc(20) := crc(16);
ncrc(19) := tc(0) xor crc(15);
ncrc(18) := tc(1) xor crc(14);
ncrc(17) := tc(2) xor crc(13);
ncrc(16) := tc(3) xor crc(12);
ncrc(15) := tc(0) xor crc(11);
ncrc(14) := tc(0) xor tc(1) xor crc(10);
ncrc(13) := tc(0) xor tc(1) xor tc(2) xor crc(9);
ncrc(12) := tc(1) xor tc(2) xor tc(3) xor crc(8);
ncrc(11) := tc(0) xor tc(2) xor tc(3) xor crc(7);
ncrc(10) := tc(0) xor tc(1) xor tc(3) xor crc(6);
ncrc(9) := tc(1) xor tc(2) xor crc(5);
ncrc(8) := tc(0) xor tc(2) xor tc(3) xor crc(4);
ncrc(7) := tc(0) xor tc(1) xor tc(3) xor crc(3);
ncrc(6) := tc(1) xor tc(2) xor crc(2);
ncrc(5) := tc(0) xor tc(2) xor tc(3) xor crc(1);
ncrc(4) := tc(0) xor tc(1) xor tc(3) xor crc(0);
ncrc(3) := tc(0) xor tc(1) xor tc(2);
ncrc(2) := tc(1) xor tc(2) xor tc(3);
ncrc(1) := tc(2) xor tc(3);
ncrc(0) := tc(3);
return ncrc;
end function;
--16-bit one's complement adder
function crc16(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(15 downto 0))
return std_logic_vector is
variable vd1 : std_logic_vector(16 downto 0);
variable vd2 : std_logic_vector(16 downto 0);
variable sum : std_logic_vector(16 downto 0);
begin
vd1 := '0' & d1; vd2 := '0' & d2;
sum := vd1 + vd2;
sum(15 downto 0) := sum(15 downto 0) + sum(16);
return sum(15 downto 0);
end function;
--16-bit one's complement adder for ip/tcp checksum detection
function crc16_2(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(25 downto 0))
return std_logic_vector is
variable vd1 : std_logic_vector(25 downto 0);
variable vd2 : std_logic_vector(25 downto 0);
variable sum : std_logic_vector(25 downto 0);
begin
vd1 := "0000000000" & d1; vd2 := d2;
sum := vd1 + vd2;
return sum;
end function;
function validlen(len : in std_logic_vector(10 downto 0);
bcnt : in std_logic_vector(10 downto 0);
usesz : in std_ulogic)
return std_ulogic is
variable valid : std_ulogic;
begin
valid := '1';
if usesz = '1' then
if len > minpload then
if bcnt /= len then
valid := '0';
end if;
else
if bcnt /= minpload then
valid := '0';
end if;
end if;
end if;
return valid;
end function;
function setburstlength(fifosize : in integer) return integer is
begin
if fifosize <= 64 then
return fifosize/2;
else
return 32;
end if;
end function;
function getfifosize(edcl, fifosize, ebufsize : in integer) return integer is
begin
if (edcl /= 0) and (ebufsize > fifosize) then
return ebufsize;
else
return fifosize;
end if;
end function;
function calccrc(d : in std_logic_vector(3 downto 0);
crc : in std_logic_vector(31 downto 0))
return std_logic_vector is
variable ncrc : std_logic_vector(31 downto 0);
variable tc : std_logic_vector(3 downto 0);
begin
tc(0) := d(0) xor crc(31); tc(1) := d(1) xor crc(30);
tc(2) := d(2) xor crc(29); tc(3) := d(3) xor crc(28);
ncrc(31) := crc(27);
ncrc(30) := crc(26);
ncrc(29) := tc(0) xor crc(25);
ncrc(28) := tc(1) xor crc(24);
ncrc(27) := tc(2) xor crc(23);
ncrc(26) := tc(0) xor tc(3) xor crc(22);
ncrc(25) := tc(0) xor tc(1) xor crc(21);
ncrc(24) := tc(1) xor tc(2) xor crc(20);
ncrc(23) := tc(2) xor tc(3) xor crc(19);
ncrc(22) := tc(3) xor crc(18);
ncrc(21) := crc(17);
ncrc(20) := crc(16);
ncrc(19) := tc(0) xor crc(15);
ncrc(18) := tc(1) xor crc(14);
ncrc(17) := tc(2) xor crc(13);
ncrc(16) := tc(3) xor crc(12);
ncrc(15) := tc(0) xor crc(11);
ncrc(14) := tc(0) xor tc(1) xor crc(10);
ncrc(13) := tc(0) xor tc(1) xor tc(2) xor crc(9);
ncrc(12) := tc(1) xor tc(2) xor tc(3) xor crc(8);
ncrc(11) := tc(0) xor tc(2) xor tc(3) xor crc(7);
ncrc(10) := tc(0) xor tc(1) xor tc(3) xor crc(6);
ncrc(9) := tc(1) xor tc(2) xor crc(5);
ncrc(8) := tc(0) xor tc(2) xor tc(3) xor crc(4);
ncrc(7) := tc(0) xor tc(1) xor tc(3) xor crc(3);
ncrc(6) := tc(1) xor tc(2) xor crc(2);
ncrc(5) := tc(0) xor tc(2) xor tc(3) xor crc(1);
ncrc(4) := tc(0) xor tc(1) xor tc(3) xor crc(0);
ncrc(3) := tc(0) xor tc(1) xor tc(2);
ncrc(2) := tc(1) xor tc(2) xor tc(3);
ncrc(1) := tc(2) xor tc(3);
ncrc(0) := tc(3);
return ncrc;
end function;
--function calccrc_8(data : in std_logic_vector( 7 downto 0);
-- crc : in std_logic_vector(31 downto 0))
-- return std_logic_vector is
-- variable ncrc : std_logic_vector(31 downto 0);
-- variable d : std_logic_vector(7 downto 0);
--begin
-- d(7) := data(0); d(6) := data(1); d(5) := data(2); d(4) := data(3);
-- d(3) := data(4); d(2) := data(5); d(1) := data(6); d(0) := data(7);
-- ncrc(0) := d(6) xor d(0) xor crc(24) xor crc(30);
-- ncrc(1) := d(7) xor d(6) xor d(1) xor d(0) xor crc(24) xor crc(25) xor crc(30) xor crc(31);
-- ncrc(2) := d(7) xor d(6) xor d(2) xor d(1) xor d(0) xor crc(24) xor crc(25) xor crc(26) xor crc(30) xor crc(31);
-- ncrc(3) := d(7) xor d(3) xor d(2) xor d(1) xor crc(25) xor crc(26) xor crc(27) xor crc(31);
-- ncrc(4) := d(6) xor d(4) xor d(3) xor d(2) xor d(0) xor crc(24) xor crc(26) xor crc(27) xor crc(28) xor crc(30);
-- ncrc(5) := d(7) xor d(6) xor d(5) xor d(4) xor d(3) xor d(1) xor d(0) xor crc(24) xor crc(25) xor crc(27) xor crc(28) xor crc(29) xor crc(30) xor crc(31);
-- ncrc(6) := d(7) xor d(6) xor d(5) xor d(4) xor d(2) xor d(1) xor crc(25) xor crc(26) xor crc(28) xor crc(29) xor crc(30) xor crc(31);
-- ncrc(7) := d(7) xor d(5) xor d(3) xor d(2) xor d(0) xor crc(24) xor crc(26) xor crc(27) xor crc(29) xor crc(31);
-- ncrc(8) := d(4) xor d(3) xor d(1) xor d(0) xor crc(0) xor crc(24) xor crc(25) xor crc(27) xor crc(28);
-- ncrc(9) := d(5) xor d(4) xor d(2) xor d(1) xor crc(1) xor crc(25) xor crc(26) xor crc(28) xor crc(29);
-- ncrc(10) := d(5) xor d(3) xor d(2) xor d(0) xor crc(2) xor crc(24) xor crc(26) xor crc(27) xor crc(29);
-- ncrc(11) := d(4) xor d(3) xor d(1) xor d(0) xor crc(3) xor crc(24) xor crc(25) xor crc(27) xor crc(28);
-- ncrc(12) := d(6) xor d(5) xor d(4) xor d(2) xor d(1) xor d(0) xor crc(4) xor crc(24) xor crc(25) xor crc(26) xor crc(28) xor crc(29) xor crc(30);
-- ncrc(13) := d(7) xor d(6) xor d(5) xor d(3) xor d(2) xor d(1) xor crc(5) xor crc(25) xor crc(26) xor crc(27) xor crc(29) xor crc(30) xor crc(31);
-- ncrc(14) := d(7) xor d(6) xor d(4) xor d(3) xor d(2) xor crc(6) xor crc(26) xor crc(27) xor crc(28) xor crc(30) xor crc(31);
-- ncrc(15) := d(7) xor d(5) xor d(4) xor d(3) xor crc(7) xor crc(27) xor crc(28) xor crc(29) xor crc(31);
-- ncrc(16) := d(5) xor d(4) xor d(0) xor crc(8) xor crc(24) xor crc(28) xor crc(29);
-- ncrc(17) := d(6) xor d(5) xor d(1) xor crc(9) xor crc(25) xor crc(29) xor crc(30);
-- ncrc(18) := d(7) xor d(6) xor d(2) xor crc(10) xor crc(26) xor crc(30) xor crc(31);
-- ncrc(19) := d(7) xor d(3) xor crc(11) xor crc(27) xor crc(31);
-- ncrc(20) := d(4) xor crc(12) xor crc(28);
-- ncrc(21) := d(5) xor crc(13) xor crc(29);
-- ncrc(22) := d(0) xor crc(14) xor crc(24);
-- ncrc(23) := d(6) xor d(1) xor d(0) xor crc(15) xor crc(24) xor crc(25) xor crc(30);
-- ncrc(24) := d(7) xor d(2) xor d(1) xor crc(16) xor crc(25) xor crc(26) xor crc(31);
-- ncrc(25) := d(3) xor d(2) xor crc(17) xor crc(26) xor crc(27);
-- ncrc(26) := d(6) xor d(4) xor d(3) xor d(0) xor crc(18) xor crc(24) xor crc(27) xor crc(28) xor crc(30);
-- ncrc(27) := d(7) xor d(5) xor d(4) xor d(1) xor crc(19) xor crc(25) xor crc(28) xor crc(29) xor crc(31);
-- ncrc(28) := d(6) xor d(5) xor d(2) xor crc(20) xor crc(26) xor crc(29) xor crc(30);
-- ncrc(29) := d(7) xor d(6) xor d(3) xor crc(21) xor crc(27) xor crc(30) xor crc(31);
-- ncrc(30) := d(7) xor d(4) xor crc(22) xor crc(28) xor crc(31);
-- ncrc(31) := d(5) xor crc(23) xor crc(29);
-- return ncrc;
--end function;
--16-bit one's complement adder
function crcadder(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(17 downto 0))
return std_logic_vector is
variable vd1 : std_logic_vector(17 downto 0);
variable vd2 : std_logic_vector(17 downto 0);
variable sum : std_logic_vector(17 downto 0);
begin
vd1 := "00" & d1; vd2 := d2;
sum := vd1 + vd2;
return sum;
end function;
end package body;
| gpl-3.0 | 1830d8ba6f2deefcbc7db24a5f30084a | 0.549946 | 3.054945 | false | false | false | false |
pwsoft/fpga_examples | quartus/chameleon/chameleon1_gigatron/pll8.vhd | 1 | 19,669 | -- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll8.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll8 IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
c3 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END pll8;
ARCHITECTURE SYN OF pll8 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC ;
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire8_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire8 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
clk3_divide_by : NATURAL;
clk3_duty_cycle : NATURAL;
clk3_multiply_by : NATURAL;
clk3_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire8_bv(0 DOWNTO 0) <= "0";
sub_wire8 <= To_stdlogicvector(sub_wire8_bv);
sub_wire5 <= sub_wire0(2);
sub_wire4 <= sub_wire0(0);
sub_wire2 <= sub_wire0(3);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
c3 <= sub_wire2;
locked <= sub_wire3;
c0 <= sub_wire4;
c2 <= sub_wire5;
sub_wire6 <= inclk0;
sub_wire7 <= sub_wire8(0 DOWNTO 0) & sub_wire6;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 2,
clk0_duty_cycle => 50,
clk0_multiply_by => 25,
clk0_phase_shift => "0",
clk1_divide_by => 2,
clk1_duty_cycle => 50,
clk1_multiply_by => 25,
clk1_phase_shift => "5000",
clk2_divide_by => 4,
clk2_duty_cycle => 50,
clk2_multiply_by => 75,
clk2_phase_shift => "0",
clk3_divide_by => 4,
clk3_duty_cycle => 50,
clk3_multiply_by => 75,
clk3_phase_shift => "3333",
compensate_clock => "CLK0",
inclk0_input_frequency => 125000,
intended_device_family => "Cyclone III",
lpm_hint => "CBX_MODULE_PREFIX=pll8",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_USED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "ON",
width_clock => 5
)
PORT MAP (
inclk => sub_wire7,
clk => sub_wire0,
locked => sub_wire3
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "2"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "2"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "150.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "150.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "8.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "25"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "25"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "150.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "150.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "180.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "180.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll8.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "25"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "25"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "5000"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "4"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "75"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "4"
-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "75"
-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "3333"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "125000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll8.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll8.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll8.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll8.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll8.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll8_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll8_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll8_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
| lgpl-2.1 | 6bba4b3b03cf15f44b475700125c8081 | 0.700798 | 3.265648 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/ddr/ddrintpkg.vhd | 1 | 17,763 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: ddrintpkg
-- File: ddrintpkg.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Internal components and types for DDR SDRAM controllers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.ddrpkg.all;
package ddrintpkg is
-----------------------------------------------------------------------------
-- DDR2SPA types and components
-----------------------------------------------------------------------------
component ddr2buf is
generic (
tech : integer := 0;
wabits : integer := 6;
wdbits : integer := 8;
rabits : integer := 6;
rdbits : integer := 8;
sepclk : integer := 0;
wrfst : integer := 0;
testen : integer := 0);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((rabits -1) downto 0);
dataout : out std_logic_vector((rdbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
writebig : in std_ulogic;
waddress : in std_logic_vector((wabits -1) downto 0);
datain : in std_logic_vector((wdbits -1) downto 0);
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0));
end component;
type ddr_request_type is record
startaddr : std_logic_vector(31 downto 0);
endaddr : std_logic_vector(9 downto 0);
hsize : std_logic_vector(2 downto 0);
hwrite : std_ulogic;
hio : std_ulogic;
maskdata : std_ulogic;
maskcb : std_ulogic;
burst : std_ulogic;
end record;
type ddr_response_type is record
done_tog : std_ulogic;
rctr_gray : std_logic_vector(3 downto 0);
readerr : std_ulogic;
end record;
constant ddr_request_none: ddr_request_type :=
((others => '0'), (others => '0'), "000", '0','0','0','0','0');
constant ddr_response_none: ddr_response_type := ('0',"0000",'0');
component ddr2spax_ahb is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
burstlen : integer := 8;
nosync : integer := 0;
ahbbits : integer := ahbdw;
revision : integer := 0;
devid : integer := GAISLER_DDR2SP;
ddrbits : integer := 32;
regarea : integer := 0
);
port (
rst : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
request : out ddr_request_type;
start_tog : out std_logic;
response : in ddr_response_type;
wbwaddr : out std_logic_vector(log2(burstlen) downto 0);
wbwdata : out std_logic_vector(ahbbits-1 downto 0);
wbwrite : out std_logic;
wbwritebig: out std_logic;
rbraddr : out std_logic_vector(log2(burstlen*32/ahbbits)-1 downto 0);
rbrdata : in std_logic_vector(ahbbits-1 downto 0);
hwidth : in std_logic;
beid : in std_logic_vector(3 downto 0)
);
end component;
component ft_ddr2spax_ahb is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
burstlen : integer := 8;
nosync : integer := 0;
ahbbits : integer := 64;
bufbits : integer := 96;
ddrbits : integer := 16;
hwidthen : integer := 0;
revision : integer := 0;
devid : integer := GAISLER_DDR2SP
);
port (
rst : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
ce : out std_logic;
request : out ddr_request_type;
start_tog : out std_logic;
response : in ddr_response_type;
wbwaddr : out std_logic_vector(log2(burstlen)-2 downto 0);
wbwdata : out std_logic_vector(bufbits-1 downto 0);
wbwrite : out std_logic;
wbwritebig : out std_logic;
rbraddr : out std_logic_vector(log2(burstlen*32/ahbbits)-1 downto 0);
rbrdata : in std_logic_vector(bufbits-1 downto 0);
hwidth : in std_logic;
synccfg : in std_logic;
request2 : out ddr_request_type;
start_tog2 : out std_logic;
beid : in std_logic_vector(3 downto 0)
);
end component;
constant FTFE_BEID_DDR2 : std_logic_vector(3 downto 0) := "0000";
constant FTFE_BEID_SDR : std_logic_vector(3 downto 0) := "0001";
constant FTFE_BEID_DDR1 : std_logic_vector(3 downto 0) := "0010";
constant FTFE_BEID_SSR : std_logic_vector(3 downto 0) := "0011";
constant FTFE_BEID_LPDDR2: std_logic_vector(3 downto 0) := "0100";
component ddr2spax_ddr is
generic (
ddrbits : integer := 32;
burstlen : integer := 8;
MHz : integer := 100;
TRFC : integer := 130;
col : integer := 9;
Mbyte : integer := 8;
pwron : integer := 0;
oepol : integer := 0;
readdly : integer := 1;
odten : integer := 0;
octen : integer := 0;
dqsgating : integer := 0;
nosync : integer := 0;
eightbanks : integer range 0 to 1 := 0; -- Set to 1 if 8 banks instead of 4
dqsse : integer range 0 to 1 := 0; -- single ended DQS
ddr_syncrst: integer range 0 to 1 := 0;
chkbits : integer := 0;
bigmem : integer range 0 to 1 := 0;
raspipe : integer range 0 to 1 := 0;
hwidthen : integer range 0 to 1 := 0;
phytech : integer := 0;
hasdqvalid : integer := 0;
rstdel : integer := 200;
phyptctrl : integer := 0;
scantest : integer := 0;
dis_caslat : integer := 0;
dis_init : integer := 0;
cke_rst : integer := 0
);
port (
ddr_rst : in std_ulogic;
clk_ddr : in std_ulogic;
request : in ddr_request_type;
start_tog: in std_logic;
response : out ddr_response_type;
sdi : in ddrctrl_in_type;
sdo : out ddrctrl_out_type;
wbraddr : out std_logic_vector(log2((16*burstlen)/ddrbits) downto 0);
wbrdata : in std_logic_vector(2*(ddrbits+chkbits)-1 downto 0);
rbwaddr : out std_logic_vector(log2((16*burstlen)/ddrbits)-1 downto 0);
rbwdata : out std_logic_vector(2*(ddrbits+chkbits)-1 downto 0);
rbwrite : out std_logic;
hwidth : in std_ulogic;
-- dynamic sync (nosync=2)
reqsel : in std_ulogic;
frequest : in ddr_request_type;
response2: out ddr_response_type;
testen : in std_ulogic;
testrst : in std_ulogic;
testoen : in std_ulogic
);
end component;
-----------------------------------------------------------------------------
-- DDRSPA types and components
-----------------------------------------------------------------------------
component ddr1spax_ddr is
generic (
ddrbits : integer := 32;
burstlen : integer := 8;
MHz : integer := 100;
col : integer := 9;
Mbyte : integer := 8;
pwron : integer := 0;
oepol : integer := 0;
mobile : integer := 0;
confapi : integer := 0;
conf0 : integer := 0;
conf1 : integer := 0;
nosync : integer := 0;
ddr_syncrst: integer range 0 to 1 := 0;
chkbits : integer := 0;
hasdqvalid : integer := 0;
readdly : integer := 0;
regoutput : integer := 1;
ddr400 : integer := 1;
rstdel : integer := 200;
phyptctrl : integer := 0;
scantest : integer := 0
);
port (
ddr_rst : in std_ulogic;
clk_ddr : in std_ulogic;
request : in ddr_request_type;
start_tog: in std_logic;
response : out ddr_response_type;
sdi : in ddrctrl_in_type;
sdo : out ddrctrl_out_type;
wbraddr : out std_logic_vector(log2((16*burstlen)/ddrbits) downto 0);
wbrdata : in std_logic_vector(2*(ddrbits+chkbits)-1 downto 0);
rbwaddr : out std_logic_vector(log2((16*burstlen)/ddrbits)-1 downto 0);
rbwdata : out std_logic_vector(2*(ddrbits+chkbits)-1 downto 0);
rbwrite : out std_logic;
reqsel : in std_ulogic;
frequest : in ddr_request_type;
response2: out ddr_response_type;
testen : in std_ulogic;
testrst : in std_ulogic;
testoen : in std_ulogic
);
end component;
-----------------------------------------------------------------------------
-- Other components re-using sub-components above
-----------------------------------------------------------------------------
component ahb2avl_async_be is
generic (
avldbits : integer := 32;
avlabits : integer := 20;
ahbbits : integer := ahbdw;
burstlen : integer := 8;
nosync : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
avlsi : out ddravl_slv_in_type;
avlso : in ddravl_slv_out_type;
request: in ddr_request_type;
start_tog: in std_ulogic;
response: out ddr_response_type;
wbraddr : out std_logic_vector(log2((32*burstlen)/avldbits) downto 0);
wbrdata : in std_logic_vector(avldbits-1 downto 0);
rbwaddr : out std_logic_vector(log2((32*burstlen)/avldbits)-1 downto 0);
rbwdata : out std_logic_vector(avldbits-1 downto 0);
rbwrite : out std_logic
);
end component;
-----------------------------------------------------------------------------
-- Gray-code routines
-----------------------------------------------------------------------------
function lin2gray(l: std_logic_vector) return std_logic_vector;
function gray2lin(g: std_logic_vector) return std_logic_vector;
function nextgray(g: std_logic_vector) return std_logic_vector;
-----------------------------------------------------------------------------
-- Data-mask routines
-----------------------------------------------------------------------------
function maskfirst(addr: std_logic_vector(9 downto 0); ddrbits: integer) return std_logic_vector;
function masklast(addr: std_logic_vector(9 downto 0); hsize: std_logic_vector(2 downto 0); ddrbits: integer) return std_logic_vector;
function masksub32(addr: std_logic_vector(9 downto 0); hsize: std_logic_vector(2 downto 0); ddrbits: integer) return std_logic_vector;
end package;
package body ddrintpkg is
function lin2gray(l: std_logic_vector) return std_logic_vector is
variable lx,r: std_logic_vector(l'length-1 downto 0);
begin
lx := l;
r(l'length-1) := lx(l'length-1);
if l'length > 1 then
r(l'length-2 downto 0) := lx(l'length-1 downto 1) xor lx(l'length-2 downto 0);
end if;
return r;
end lin2gray;
function gray2lin(g: std_logic_vector) return std_logic_vector is
variable x: std_logic_vector(15 downto 0);
variable r: std_logic_vector(g'length-1 downto 0);
begin
x := (others => '0');
x(g'length-1 downto 0) := g;
if g'length > 1 then
x(14 downto 0) := x(14 downto 0) xor x(15 downto 1);
end if;
if g'length > 2 then
x(13 downto 0) := x(13 downto 0) xor x(15 downto 2);
end if;
if g'length > 4 then
x(11 downto 0) := x(11 downto 0) xor x(15 downto 4);
end if;
if g'length > 8 then
x(7 downto 0) := x(7 downto 0) xor x(15 downto 8);
end if;
r := x(g'length-1 downto 0);
return r;
end gray2lin;
function nextgray(g: std_logic_vector) return std_logic_vector is
variable gx,r: std_logic_vector(g'length-1 downto 0);
variable gx3,r3: std_logic_vector(2 downto 0) := "000";
variable l,nl: std_logic_vector(g'length-1 downto 0);
begin
gx := g;
if gx'length = 1 then
r(0) := not gx(0);
elsif gx'length = 2 then
r(1) := gx(0);
r(0) := not gx(1);
elsif gx'length = 3 then
-- r(2) := (gx(1) or gx(0)) and (not gx(2) or not gx(0));
-- r(1) := (gx(1) or gx(0)) and (gx(2) or not gx(0));
-- r(0) := gx(2) xor gx(1);
gx3 := gx(2 downto 0);
case gx3 is
when "000" => r3 := "001";
when "001" => r3 := "011";
when "011" => r3 := "010";
when "010" => r3 := "110";
when "110" => r3 := "111";
when "111" => r3 := "101";
when "101" => r3 := "100";
when others => r3 := "000";
end case;
r(2 downto 0) := r3;
else
l := gray2lin(g);
nl := std_logic_vector(unsigned(l)+1);
r := lin2gray(nl);
end if;
return r;
end nextgray;
function maskfirst(addr: std_logic_vector(9 downto 0); ddrbits: integer) return std_logic_vector is
variable r: std_logic_vector(ddrbits/4-1 downto 0);
variable a32: std_logic_vector(3 downto 2);
variable a432: std_logic_vector(4 downto 2);
begin
r := (others => '0');
a32 := addr(3 downto 2);
a432 := addr(4 downto 2);
case ddrbits is
when 32 =>
if addr(2)='0' then r := "00000000";
else r := "11110000";
end if;
when 64 =>
case a32 is
when "00" => r := x"0000";
when "01" => r := x"F000";
when "10" => r := x"FF00";
when others => r := x"FFF0";
end case;
when 128 =>
case a432 is
when "000" => r := x"00000000";
when "001" => r := x"F0000000";
when "010" => r := x"FF000000";
when "011" => r := x"FFF00000";
when "100" => r := x"FFFF0000";
when "101" => r := x"FFFFF000";
when "110" => r := x"FFFFFF00";
when others => r := x"FFFFFFF0";
end case;
when others =>
--pragma translate_off
assert ddrbits=16 report "Unsupported DDR width" severity failure;
--pragma translate_on
null;
end case;
return r;
end maskfirst;
function masklast(addr: std_logic_vector(9 downto 0);
hsize: std_logic_vector(2 downto 0); ddrbits: integer)
return std_logic_vector is
variable r: std_logic_vector(ddrbits/4-1 downto 0);
variable xaddr: std_logic_vector(9 downto 0);
variable a32: std_logic_vector(3 downto 2);
variable a432: std_logic_vector(4 downto 2);
begin
xaddr := addr;
if hsize(2)='1' then
xaddr(3 downto 2) := "11";
xaddr(3 downto 2) := "11";
end if;
if hsize(2)='1' and hsize(0)='1' then
xaddr(4) := '1';
end if;
if hsize(1 downto 0)="11" then
xaddr(2) := '1';
end if;
a32 := xaddr(3 downto 2);
a432 := xaddr(4 downto 2);
r := (others => '0');
case ddrbits is
when 32 =>
if xaddr(2)='0' then r := "00001111";
else r := "00000000";
end if;
when 64 =>
case a32 is
when "00" => r := x"0FFF";
when "01" => r := x"00FF";
when "10" => r := x"000F";
when others => r := x"0000";
end case;
when 128 =>
case a432 is
when "000" => r := x"0FFFFFFF";
when "001" => r := x"00FFFFFF";
when "010" => r := x"000FFFFF";
when "011" => r := x"0000FFFF";
when "100" => r := x"00000FFF";
when "101" => r := x"000000FF";
when "110" => r := x"0000000F";
when others => r := x"00000000";
end case;
when others =>
--pragma translate_off
assert ddrbits=16 report "Unsupported DDR width" severity failure;
--pragma translate_on
null;
end case;
return r;
end masklast;
function masksub32(addr: std_logic_vector(9 downto 0); hsize: std_logic_vector(2 downto 0); ddrbits: integer)
return std_logic_vector is
variable r: std_logic_vector(ddrbits/4-1 downto 0);
variable r16: std_logic_vector(3 downto 0);
variable a10: std_logic_vector(1 downto 0);
begin
r16 := (others => '0');
if hsize(2 downto 1)="00" then
r16 := addr(1) & addr(1) & (not addr(1)) & (not addr(1));
if hsize(0)='0' then
r16 := r16 or (addr(0) & (not addr(0)) & addr(0) & (not addr(0)));
end if;
end if;
r := (others => '0');
for x in 0 to ddrbits/16-1 loop
r(x*4+3 downto x*4) := r16;
end loop;
return r;
end masksub32;
end;
| gpl-3.0 | 749595a0ace391dca59614a4fc560355 | 0.530766 | 3.609632 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-terasic-de0-nano/clkgen_de0.vhd | 1 | 3,590 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library altera_mf;
-- pragma translate_off
use altera_mf.altpll;
-- pragma translate_on
entity clkgen_de0 is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic
);
end;
architecture rtl of clkgen_de0 is
component altpll
generic (
intended_device_family : string := "Stratix" ;
operation_mode : string := "NORMAL" ;
compensate_clock : string := "CLK0" ;
inclk0_input_frequency : positive;
width_clock : positive := 6;
clk0_multiply_by : positive := 1;
clk0_divide_by : positive := 1;
clk1_multiply_by : positive := 1;
clk1_divide_by : positive := 1;
clk2_multiply_by : positive := 1;
clk2_divide_by : positive := 1
);
port (
inclk : in std_logic_vector(1 downto 0);
clk : out std_logic_vector(width_clock-1 downto 0);
locked : out std_logic
);
end component;
signal clkout : std_logic_vector (5 downto 0);
signal inclk : std_logic_vector (1 downto 0);
constant clk_period : integer := 1000000000/clk_freq;
constant CLK_MUL2X : integer := clk_mul * 2;
begin
inclk <= '0' & inclk0;
c0 <= clkout(0); c0_2x <= clkout(1);
sden : if sdramen = 1 generate
altpll0 : altpll
generic map (
intended_device_family => "Cyclone II",
operation_mode => "ZERO_DELAY_BUFFER",
compensate_clock => "CLK2",
inclk0_input_frequency => clk_period,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => 5, clk1_divide_by => 10,
clk2_multiply_by => clk_mul, clk2_divide_by => clk_div)
port map (inclk => inclk, clk => clkout, locked => locked);
e0 <= clkout(2);
end generate;
nosd : if sdramen = 0 generate
altpll0 : altpll
generic map (
intended_device_family => "Cyclone II",
operation_mode => "NORMAL",
inclk0_input_frequency => clk_period,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => 5, clk1_divide_by => 10)
port map (inclk => inclk, clk => clkout, locked => locked);
e0 <= '0';
end generate;
end;
| gpl-3.0 | 78f0cc64269c655c9f1e77c0f020ad95 | 0.595543 | 3.674514 | false | false | false | false |
hoglet67/CoPro6502 | src/DCM/dcm_32_14.vhd | 1 | 2,065 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity dcm_32_14 is
port (CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic);
end dcm_32_14;
architecture BEHAVIORAL of dcm_32_14 is
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKFX_BUFG_INST : BUFG
port map (I => CLKFX_BUF, O => CLK0_OUT);
DCM_INST : DCM
generic map(CLK_FEEDBACK => "NONE",
CLKDV_DIVIDE => 4.0, -- 14.000 = 32.000 * 7/16
CLKFX_DIVIDE => 16,
CLKFX_MULTIPLY => 7,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => 31.25,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => true,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => false)
port map (CLKFB => GND_BIT,
CLKIN => CLKIN_IN,
DSSEN => GND_BIT,
PSCLK => GND_BIT,
PSEN => GND_BIT,
PSINCDEC => GND_BIT,
RST => GND_BIT,
CLKDV => open,
CLKFX => CLKFX_BUF,
CLKFX180 => open,
CLK0 => open,
CLK2X => open,
CLK2X180 => open,
CLK90 => open,
CLK180 => open,
CLK270 => open,
LOCKED => open,
PSDONE => open,
STATUS => open);
end BEHAVIORAL;
| gpl-3.0 | 14be0fa5ffd804c40ea3e1f6eba16560 | 0.404843 | 4.231557 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-digilent-nexys3/leon3mp.vhd | 1 | 19,411 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2013 Aeroflex Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.net.all;
use gaisler.jtag.all;
--pragma translate_off
use gaisler.sim.all;
--pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
clk : in std_ulogic;
-- onBoard Cellular RAM, Numonyx StrataFlash and Numonyx Quad Flash
MemOE : out std_ulogic;
MemWR : out std_ulogic;
RamAdv : out std_ulogic;
RamCS : out std_ulogic;
RamClk : out std_ulogic;
RamCRE : out std_ulogic;
RamLB : out std_ulogic;
RamUB : out std_ulogic;
RamWait : out std_ulogic;
FlashRp : out std_ulogic;
FlashCS : out std_ulogic;
QuadSpiFlashCS : out std_ulogic;
QuadSpiFlashSck : out std_ulogic;
QuadSpiFlashDB : inout std_logic_vector(0 downto 0);
address : out std_logic_vector(25 downto 0);
data : inout std_logic_vector(15 downto 0);
-- 7 segment display
--seg : out std_logic_vector(7 downto 0);
--an : out std_logic_vector(3 downto 0);
-- LEDs
led : out std_logic_vector(7 downto 0);
-- Switches
sw : in std_logic_vector(7 downto 0);
-- Buttons
btn : in std_logic_vector(4 downto 0); -- reset on btn0
-- VGA Connector
--vgaRed : out std_logic_vector(2 downto 0);
--vgaGreen : out std_logic_vector(2 downto 0);
--vgaBlue : out std_logic_vector(2 downto 1);
--Hsync : out std_ulogic;
--Vsync : out std_ulogic;
-- 12 pin connectors
--ja : inout std_logic_vector(7 downto 0);
--jb : inout std_logic_vector(7 downto 0);
--jc : inout std_logic_vector(7 downto 0);
--jd : inout std_logic_vector(7 downto 0);
-- SMSC ethernet PHY
PhyRstn : out std_ulogic;
PhyCrs : in std_ulogic;
PhyCol : in std_ulogic;
PhyClk25Mhz : out std_ulogic;
PhyTxd : out std_logic_vector(3 downto 0);
PhyTxEn : out std_ulogic;
PhyTxClk : in std_ulogic;
PhyTxEr : out std_ulogic;
PhyRxd : in std_logic_vector(3 downto 0);
PhyRxDv : in std_ulogic;
PhyRxEr : in std_ulogic;
PhyRxClk : in std_ulogic;
PhyMdc : out std_ulogic;
PhyMdio : inout std_logic;
-- Pic USB-HID interface
--PS2KeyboardData : inout std_logic;
--PS2KeyboardClk : inout std_logic;
--PS2MouseData : inout std_logic;
--PS2MouseClk : inout std_logic;
--PicGpio : out std_logic_vector(1 downto 0);
-- USB-RS232 interface
RsRx : in std_logic;
RsTx : out std_logic
);
end;
architecture rtl of leon3mp is
signal vcc : std_logic;
signal gnd : std_logic;
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal gpti : gptimer_in_type;
signal spii : spi_in_type;
signal spio : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal spmi : spimctrl_in_type;
signal spmo : spimctrl_out_type;
signal clkm, rstn, clkml : std_ulogic;
signal tck, tms, tdi, tdo : std_ulogic;
signal rstraw : std_logic;
signal lock : std_logic;
-- RS232 APB Uart
signal rxd1 : std_logic;
signal txd1 : std_logic;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of lock : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_keep of clkm : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute keep of lock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
constant BOARD_FREQ : integer := 100000; -- CLK input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1';
gnd <= '0';
led(7 downto 4) <= (others =>'0'); -- unused leds off
cgi.pllctrl <= "00";
cgi.pllrst <= rstraw;
rst0 : rstgen generic map (acthigh => 1)
port map (btn(0), clkm, lock, rstn, rstraw);
lock <= cgo.clklock;
-- clock generator
clkgen0 : clkgen
generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (clk, gnd, clkm, open, open, open, open, cgi, cgo, open, open, open);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH,
nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
-- LEON3 processor
leon3gen : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR,
CFG_NCPU-1, CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
led(3) <= not dbgo(0).error;
led(2) <= not dsuo.active;
-- LEON3 Debug Support Unit
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
-- Debug UART
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (RsRx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (RsTx, duo.txd);
led(0) <= not dui.rxd;
led(1) <= not duo.txd;
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd);
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 5, pindex => 0, paddr => 0, iomask => 0,
ram8 => CFG_MCTRL_RAM8BIT, ram16 => CFG_MCTRL_RAM16BIT,srbanks=>1)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(5), apbi, apbo(0), wpo, open);
end generate;
memi.brdyn <= '1';
memi.bexcn <= '1';
memi.writen <= '1';
memi.wrn <= "1111";
memi.bwidth <= "01";
mg0 : if (CFG_MCTRL_LEON2 = 0) generate
apbo(0) <= apb_none;
ahbso(5) <= ahbs_none;
memo.bdrive(0) <= '1';
end generate;
mgpads : if (CFG_MCTRL_LEON2 /= 0) generate
addr_pad : outpadv generic map (tech => padtech, width => 26)
port map (address, memo.address(26 downto 1));
oen_pad : outpad generic map (tech => padtech)
port map (MemOE, memo.oen);
cs_pad : outpad generic map (tech => padtech)
port map (RamCS, memo.ramsn(0));
lb_pad : outpad generic map (tech => padtech)
port map (RamLB, memo.mben(0));
ub_pad : outpad generic map (tech => padtech)
port map (RamUB, memo.mben(1));
wri_pad : outpad generic map (tech => padtech)
port map (MemWR, memo.writen);
fce_pad : outpad generic map (tech => padtech)
port map (FlashCS, memo.romsn(0));
frp_pad : outpad generic map (tech => padtech)
port map (FlashRp, rstn);
end generate;
bdr : iopadv generic map (tech => padtech, width => 8)
port map (data(7 downto 0), memo.data(23 downto 16),
memo.bdrive(1), memi.data(23 downto 16));
bdr2 : iopadv generic map (tech => padtech, width => 8)
port map (data(15 downto 8), memo.data(31 downto 24),
memo.bdrive(0), memi.data(31 downto 24));
RamCRE <= '0';
RamClk <= '0';
RamAdv <= '0';
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
-- APB Bridge
apb0 : apbctrl
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
-- Interrupt controller
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
-- Time Unit
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW,
ntimers => CFG_GPT_NTIM, nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti <= gpti_dhalt_drive(dsuo.tstop);
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
-- Console UART.
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1;
u1i.ctsn <= '0';
u1i.extclk <= '0';
txd1 <= u1o.txd;
-- The USB UART is curently mapped to ahbuart.
-- serrx_pad : inpad generic map (tech => padtech) port map (RsRx, rxd1);
-- sertx_pad : outpad generic map (tech => padtech) port map (RsTx, txd1);
-- led(0) <= not rxd1;
-- led(1) <= not txd1;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
nospi: if CFG_SPICTRL_ENABLE = 0 and CFG_SPIMCTRL = 0 generate
apbo(7) <= apb_none;
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm
generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 15, paddr => 15, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 7,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G)
port map(rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
apbi => apbi, apbo => apbo(15), ethi => ethi, etho => etho);
PhyRstn<=rstn;
end generate;
ethpads : if (CFG_GRETH = 1) generate -- eth pads
emdio_pad : iopad generic map (tech => padtech)
port map (PhyMdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (PhyTxClk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (PhyRxClk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (PhyRxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (PhyRxDv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (PhyRxEr, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (PhyCol, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (PhyCrs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (PhyTxd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (PhyTxEn, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (PhyTxEr, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (PhyMdc, etho.mdc);
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram
generic map (hindex => 3, haddr => CFG_AHBRADDR, tech => CFG_MEMTECH,
kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
-- Test report module, only used for simulation ----------------------
-----------------------------------------------------------------------
--pragma translate_off
test0 : ahbrep generic map (hindex => 4, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(4));
--pragma translate_on
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+1) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Demonstration design for Digilent NEXYS 3 board",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end rtl;
| gpl-3.0 | 0c26efe240d2bf3cd76bc6c4540aa35f | 0.525475 | 3.899357 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/unisim/sysmon_unisim.vhd | 1 | 6,617 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity:
-- File: sysmon_unisim.vhd
-- Author: Jan Andersson - Gaisler Research
-- Description: Xilinx System Monitor
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.SYSMON;
-- pragma translate_on
-------------------------------------------------------------------------------
-- Virtex 5 System Monitor
-------------------------------------------------------------------------------
entity sysmon_virtex5 is
generic (
INIT_40 : bit_vector := X"0000";
INIT_41 : bit_vector := X"0000";
INIT_42 : bit_vector := X"0800";
INIT_43 : bit_vector := X"0000";
INIT_44 : bit_vector := X"0000";
INIT_45 : bit_vector := X"0000";
INIT_46 : bit_vector := X"0000";
INIT_47 : bit_vector := X"0000";
INIT_48 : bit_vector := X"0000";
INIT_49 : bit_vector := X"0000";
INIT_4A : bit_vector := X"0000";
INIT_4B : bit_vector := X"0000";
INIT_4C : bit_vector := X"0000";
INIT_4D : bit_vector := X"0000";
INIT_4E : bit_vector := X"0000";
INIT_4F : bit_vector := X"0000";
INIT_50 : bit_vector := X"0000";
INIT_51 : bit_vector := X"0000";
INIT_52 : bit_vector := X"0000";
INIT_53 : bit_vector := X"0000";
INIT_54 : bit_vector := X"0000";
INIT_55 : bit_vector := X"0000";
INIT_56 : bit_vector := X"0000";
INIT_57 : bit_vector := X"0000";
SIM_MONITOR_FILE : string := "design.txt");
port (
alm : out std_logic_vector(2 downto 0);
busy : out std_ulogic;
channel : out std_logic_vector(4 downto 0);
do : out std_logic_vector(15 downto 0);
drdy : out std_ulogic;
eoc : out std_ulogic;
eos : out std_ulogic;
jtagbusy : out std_ulogic;
jtaglocked : out std_ulogic;
jtagmodified : out std_ulogic;
ot : out std_ulogic;
convst : in std_ulogic;
convstclk : in std_ulogic;
daddr : in std_logic_vector(6 downto 0);
dclk : in std_ulogic;
den : in std_ulogic;
di : in std_logic_vector(15 downto 0);
dwe : in std_ulogic;
reset : in std_ulogic;
vauxn : in std_logic_vector(15 downto 0);
vauxp : in std_logic_vector(15 downto 0);
vn : in std_ulogic;
vp : in std_ulogic);
end sysmon_virtex5;
architecture struct of sysmon_virtex5 is
component SYSMON
generic (
INIT_40 : bit_vector := X"0000";
INIT_41 : bit_vector := X"0000";
INIT_42 : bit_vector := X"0800";
INIT_43 : bit_vector := X"0000";
INIT_44 : bit_vector := X"0000";
INIT_45 : bit_vector := X"0000";
INIT_46 : bit_vector := X"0000";
INIT_47 : bit_vector := X"0000";
INIT_48 : bit_vector := X"0000";
INIT_49 : bit_vector := X"0000";
INIT_4A : bit_vector := X"0000";
INIT_4B : bit_vector := X"0000";
INIT_4C : bit_vector := X"0000";
INIT_4D : bit_vector := X"0000";
INIT_4E : bit_vector := X"0000";
INIT_4F : bit_vector := X"0000";
INIT_50 : bit_vector := X"0000";
INIT_51 : bit_vector := X"0000";
INIT_52 : bit_vector := X"0000";
INIT_53 : bit_vector := X"0000";
INIT_54 : bit_vector := X"0000";
INIT_55 : bit_vector := X"0000";
INIT_56 : bit_vector := X"0000";
INIT_57 : bit_vector := X"0000";
SIM_MONITOR_FILE : string := "design.txt"
);
port (
ALM : out std_logic_vector(2 downto 0);
BUSY : out std_ulogic;
CHANNEL : out std_logic_vector(4 downto 0);
DO : out std_logic_vector(15 downto 0);
DRDY : out std_ulogic;
EOC : out std_ulogic;
EOS : out std_ulogic;
JTAGBUSY : out std_ulogic;
JTAGLOCKED : out std_ulogic;
JTAGMODIFIED : out std_ulogic;
OT : out std_ulogic;
CONVST : in std_ulogic;
CONVSTCLK : in std_ulogic;
DADDR : in std_logic_vector(6 downto 0);
DCLK : in std_ulogic;
DEN : in std_ulogic;
DI : in std_logic_vector(15 downto 0);
DWE : in std_ulogic;
RESET : in std_ulogic;
VAUXN : in std_logic_vector(15 downto 0);
VAUXP : in std_logic_vector(15 downto 0);
VN : in std_ulogic;
VP : in std_ulogic
);
end component;
begin -- struct
sysmon0 : SYSMON
generic map (INIT_40 => INIT_40, INIT_41 => INIT_41, INIT_42 => INIT_42,
INIT_43 => INIT_43, INIT_44 => INIT_44, INIT_45 => INIT_45,
INIT_46 => INIT_46, INIT_47 => INIT_47, INIT_48 => INIT_48,
INIT_49 => INIT_49, INIT_4A => INIT_4A, INIT_4B => INIT_4B,
INIT_4C => INIT_4C, INIT_4D => INIT_4D, INIT_4E => INIT_4E,
INIT_4F => INIT_4F, INIT_50 => INIT_50, INIT_51 => INIT_51,
INIT_52 => INIT_52, INIT_53 => INIT_53, INIT_54 => INIT_54,
INIT_55 => INIT_55, INIT_56 => INIT_56, INIT_57 => INIT_57,
SIM_MONITOR_FILE => SIM_MONITOR_FILE)
port map (alm => alm, busy => busy, channel => channel, do => do,
drdy => drdy, eoc => eoc, eos => eos, jtagbusy => jtagbusy,
jtaglocked => jtaglocked, jtagmodified => jtagmodified,
ot => ot, convst => convst, convstclk => convstclk,
daddr => daddr, dclk => dclk, den => den, di => di,
dwe => dwe, reset => reset, vauxn => vauxn, vauxp => vauxp,
vn => vn, vp => vp);
end struct;
| gpl-3.0 | 9525d98d94105a4ed89cd5e525925f43 | 0.534381 | 3.572894 | false | false | false | false |
kdgwill/VHDL_Framer_Example | VHDL_Framer_Example/Example1/dataValidation.vhd | 2 | 3,493 | ---------------------------------------------------------------------------------
--DataValidation------------------------------------------------------------
--By Kyle Williams, 04/07/2011--------------------------------------------------
--PROJECT DESCRIPTION------------------------------------------------------------
--5--check that data read from ram matches what was written in the ram-----------
----------------Define Libraries to be used--------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
-----------------ENTITY FOR DATA VALIDATION------------------------------------------
ENTITY dataValidation IS
GENERIC ( bits : INTEGER := 8;-- # of bits per word
words : INTEGER := 32 ); -- # of words in the memory);
PORT (
reset : IN STD_Logic;
clock : IN STD_LOGIC;
enable : IN STD_LOGIC;
wr_ena : IN STD_LOGIC; -- write enable
ctrl_out : IN STD_LOGIC_VECTOR (bits -1 DOWNTO 0);
ram_out : IN STD_LOGIC_VECTOR (bits -1 DOWNTO 0);
data_Valid : OUT STD_LOGIC;
validOffset : OUT Integer
);
END dataValidation;
-----------------BEHAVIOR OF DATA VALIDATION-----------------------------------------
ARCHITECTURE dataValidation OF dataValidation IS
TYPE vector_array is ARRAY (0 to words -1) of STD_LOGIC_VECTOR (bits-1 DOWNTO 0);--1Dx1D
Signal mem : vector_array;--matrix
Signal S_data_Valid : STD_Logic;
-------------------PROCEDUREE------------------------------
BEGIN
PROCESS(clock,reset,wr_ena)
Variable temp_addr: Integer;
Variable ram_in : STD_LOGIC_VECTOR (bits -1 DOWNTO 0);
Variable S_validOffset:Integer;
BEGIN
IF(reset='0')THEN
temp_addr:=0;
ram_in:="00000000";
S_validOffset := 0;
ELSIF(rising_edge(clock) AND wr_ena = '0' AND enable = '1' AND ctrl_out /= ram_in)THEN
ram_in:=ctrl_out;
mem(temp_addr) <= ram_in;
IF(temp_addr <= words-2)THEN--for some reason compare with 32 instead of 31 look into this
temp_addr := temp_addr+1;
ELSE
temp_addr := 0;
END IF;
IF(S_data_valid = '0')THEN
S_validOffset:=S_validOffset+1;
ELSE
S_validOffset:=0;
END IF;
END IF;
validOffset <= S_validOffset;
End PROCESS;
PROCESS(clock,reset,wr_ena)
Variable ram_out2 : STD_LOGIC_VECTOR (bits -1 DOWNTO 0);
Variable temp_addr2 : Integer;
BEGIN
IF(reset='0')THEN
temp_addr2:=0;
ram_out2:=ram_out;
S_data_Valid <= '0';
--single problem need to detect when ram_out is not null
ELSIF(rising_edge(clock) AND wr_ena = '0' AND enable = '1' AND ram_out /= ram_out2)THEN
IF(mem(temp_addr2) = ram_out)THEN
S_data_valid <= '1';
--Only Increment when find correct Value
IF(temp_addr2 <= words-2)THEN
temp_addr2 := temp_addr2+1;
ELSE
temp_addr2 := 0;
END IF;
ELSE
S_data_valid <= '0';
END IF;
ram_out2:=ram_out;
END IF;
data_valid <= S_data_valid;
--ASSERT (ram_out = ctrl_out)
-- REPORT "DATA READ INTO RAM DOES'T MATCH WHAT WAS WRITTEN INTO RAM"
-- SEVERITY warning;
END PROCESS;
END dataValidation;
| gpl-3.0 | 4094123de7859dfc8a4175c1a945fc09 | 0.490982 | 4.028835 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-digilent-basys3/leon3mp.vhd | 1 | 15,737 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2016 Cobham Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.jtag.all;
--pragma translate_off
use gaisler.sim.all;
library unisim;
use unisim.STARTUPE2;
--pragma translate_on
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
use_ahbram_sim : integer := 0
);
port (
clk : in std_ulogic;
-- Switches
sw : in std_logic_vector(15 downto 0);
-- LEDs
led : out std_logic_vector(15 downto 0);
-- Buttons
btnc : in std_ulogic;
btnu : in std_ulogic;
btnl : in std_ulogic;
btnr : in std_ulogic;
btnd : in std_ulogic;
-- VGA connector
vgared : out std_logic_vector(3 downto 0);
vgablue : out std_logic_vector(3 downto 0);
vgagreen : out std_logic_vector(3 downto 0);
hsync : out std_ulogic;
vsync : out std_ulogic;
-- USB-RS232 interface
rstx : in std_logic;
rsrx : out std_logic;
-- SPI
--pragma translate_off
spi_sim_sck : out std_ulogic;
--pragma translate_on
qspicsn : out std_ulogic;
qspidb : inout std_logic_vector(3 downto 0)
);
end;
architecture rtl of leon3mp is
component STARTUPE2
generic (
PROG_USR : string := "FALSE";
SIM_CCLK_FREQ : real := 0.0
);
port (
CFGCLK : out std_ulogic;
CFGMCLK : out std_ulogic;
EOS : out std_ulogic;
PREQ : out std_ulogic;
CLK : in std_ulogic;
GSR : in std_ulogic;
GTS : in std_ulogic;
KEYCLEARB : in std_ulogic;
PACK : in std_ulogic;
USRCCLKO : in std_ulogic;
USRCCLKTS : in std_ulogic;
USRDONEO : in std_ulogic;
USRDONETS : in std_ulogic
);
end component;
signal vcc : std_logic;
signal gnd : std_logic;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal cgi : clkgen_in_type;
signal cgo, cgo1 : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal spmi : spimctrl_in_type;
signal spmo : spimctrl_out_type;
signal clkm : std_ulogic
-- pragma translate_off
:= '0'
-- pragma translate_on
;
signal rstn : std_ulogic;
signal tck, tms, tdi, tdo : std_ulogic;
signal rstraw : std_ulogic;
signal lbtnc : std_ulogic;
-- RS232 APB Uart
signal rxd1 : std_logic;
signal txd1 : std_logic;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of clkm : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute keep of clkm : signal is true;
constant BOARD_FREQ : integer := 100000; -- CLK input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1';
gnd <= '0';
cgi.pllctrl <= "00";
cgi.pllrst <= rstraw;
btnc_pad : inpad generic map (tech => padtech) port map (btnc, lbtnc);
rst0 : rstgen generic map (acthigh => 1)
port map (lbtnc, clkm, cgo.clklock, rstn, rstraw);
-- clock generator
clkgen0 : clkgen
generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (clk, gnd, clkm, open, open, open, open, cgi, cgo, open, open, open);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
nahbs => 6)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
-- LEON3 processor
leon3gen : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR,
CFG_NCPU-1, CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR,
CFG_REX, CFG_ALTWIN)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
led(3) <= not dbgo(0).error;
led(2) <= not dsuo.active;
-- LEON3 Debug Support Unit
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#, ahbpf => CFG_AHBPF,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
--dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsui.enable <= '1';
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
-- Debug UART
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
dui.rxd <= rxd1;
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
urx_pad : inpad generic map (tech => padtech) port map (rstx, rxd1);
utx_pad : outpad generic map (tech => padtech) port map (rsrx, txd1);
txd1 <= duo.txd when sw(0) = '1' else u1o.txd;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd);
end generate;
----------------------------------------------------------------------
--- SPI Memory controller -------------------------------------------
----------------------------------------------------------------------
spi_gen: if CFG_SPIMCTRL = 1 generate
-- OPTIONALY set the offset generic (only affect reads).
-- The first 4MB are used for loading the FPGA.
-- For dual ouptut: readcmd => 16#3B#, dualoutput => 1
spimctrl1 : spimctrl
generic map (hindex => 0, hirq => 7, faddr => 16#000#, fmask => 16#ff0#,
ioaddr => 16#700#, iomask => 16#fff#, spliten => CFG_SPLIT,
sdcard => CFG_SPIMCTRL_SDCARD, readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => CFG_SPIMCTRL_DUALOUTPUT, scaler => CFG_SPIMCTRL_SCALER,
altscaler => CFG_SPIMCTRL_ASCALER)
port map (rstn, clkm, ahbsi, ahbso(0), spmi, spmo);
spi_mosi_pad : outpad generic map (tech => padtech)
port map (qspidb(0), spmo.mosi);
spi_miso_pad : inpad generic map (tech => padtech)
port map (qspidb(1), spmi.miso);
spi_slvsel0_pad : outpad generic map (tech => padtech)
port map (qspicsn, spmo.csn);
--spi_sck_pad : outpad generic map (tech => padtech) -- FIXME
-- port map (scl, spmo.sck);
spicclk: STARTUPE2
port map (--CFGCLK => open, CFGMCLK => open, EOS => open, PREQ => open,
CLK => '0', GSR => '0', GTS => '0', KEYCLEARB => '0', PACK => '0',
USRCCLKO => spmo.sck, USRCCLKTS => '0', USRDONEO => '1', USRDONETS => '0' );
--pragma translate_off
spi_sim_sck <= spmo.sck;
--pragma translate_on
end generate;
nospi: if CFG_SPIMCTRL = 0 generate
ahbso(0) <= ahbs_none;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
-- APB Bridge
apb0 : apbctrl
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
-- Interrupt controller
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
-- Timer Unit
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW,
ntimers => CFG_GPT_NTIM, nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti <= gpti_dhalt_drive(dsuo.tstop);
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1;
u1i.ctsn <= '0';
u1i.extclk <= '0';
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 4, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(4));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(4) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
--pragma translate_off
phys : if use_ahbram_sim = 0 generate
--pragma translate_on
ahbram0 : ahbram
generic map (hindex => 3, haddr => CFG_AHBRADDR, tech => CFG_MEMTECH,
kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(3));
--pragma translate_off
end generate;
simram : if use_ahbram_sim /= 0 generate
ahbram0 : ahbram_sim
generic map (hindex => 3, haddr => CFG_AHBRADDR, tech => CFG_MEMTECH,
kbytes => 1024, pipe => CFG_AHBRPIPE, fname => "ram.srec")
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
--pragma translate_on
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
-- Test report module, only used for simulation ----------------------
-----------------------------------------------------------------------
--pragma translate_off
test0 : ahbrep generic map (hindex => 5, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(5));
--pragma translate_on
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Demonstration design for Digilent Basys3 board",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end rtl;
| gpl-3.0 | c57e19387356f8b546e79c35fcd4c99e | 0.510771 | 4.079057 | false | false | false | false |
ARC-Lab-UF/UAA | src/add_flt_stratix5_speed.vhd | 1 | 291,541 | -- megafunction wizard: %ALTFP_ADD_SUB%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altfp_add_sub
-- ============================================================
-- File Name: add_flt_stratix5_speed.vhd
-- Megafunction Name(s):
-- altfp_add_sub
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
--altfp_add_sub CBX_AUTO_BLACKBOX="ALL" DENORMAL_SUPPORT="NO" DEVICE_FAMILY="Stratix V" DIRECTION="ADD" OPTIMIZE="SPEED" PIPELINE=14 REDUCED_FUNCTIONALITY="NO" WIDTH_EXP=8 WIDTH_MAN=23 clk_en clock dataa datab result
--VERSION_BEGIN 13.1 cbx_altbarrel_shift 2013:10:23:18:05:48:SJ cbx_altfp_add_sub 2013:10:23:18:05:48:SJ cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_cycloneii 2013:10:23:18:05:48:SJ cbx_lpm_add_sub 2013:10:23:18:05:48:SJ cbx_lpm_compare 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ cbx_stratix 2013:10:23:18:05:48:SJ cbx_stratixii 2013:10:23:18:05:48:SJ VERSION_END
--altbarrel_shift CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix V" PIPELINE=1 SHIFTDIR="LEFT" WIDTH=26 WIDTHDIST=5 aclr clk_en clock data distance result
--VERSION_BEGIN 13.1 cbx_altbarrel_shift 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--synthesis_resources = reg 27
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_speed_altbarrel_shift_nud IS
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (25 DOWNTO 0);
distance : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (25 DOWNTO 0)
);
END add_flt_stratix5_speed_altbarrel_shift_nud;
ARCHITECTURE RTL OF add_flt_stratix5_speed_altbarrel_shift_nud IS
SIGNAL dir_pipe : STD_LOGIC_VECTOR(0 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL sbit_piper1d : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w681w682w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w677w678w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w702w703w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w698w699w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w724w725w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w720w721w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w746w747w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w742w743w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w768w769w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w764w765w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w673w674w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w694w695w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w716w717w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w738w739w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w760w761w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range668w681w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range668w677w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range689w702w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range689w698w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range711w724w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range711w720w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range733w746w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range733w742w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range755w768w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range755w764w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_dir_w_range665w680w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_dir_w_range687w701w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_dir_w_range708w723w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_dir_w_range730w745w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_dir_w_range752w767w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range668w673w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range689w694w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range711w716w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range733w738w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range755w760w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range668w681w682w683w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range689w702w703w704w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range711w724w725w726w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range733w746w747w748w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range755w768w769w770w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w684w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w705w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w727w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w749w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w771w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL dir_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL direction_w : STD_LOGIC;
SIGNAL pad_w : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sbit_w : STD_LOGIC_VECTOR (155 DOWNTO 0);
SIGNAL sel_w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL smux_w : STD_LOGIC_VECTOR (129 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w676w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w679w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w697w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w700w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w719w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w722w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w741w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w744w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w763w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w766w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_dir_w_range665w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_dir_w_range687w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_dir_w_range708w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_dir_w_range730w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_dir_w_range752w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sbit_w_range728w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sbit_w_range750w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sbit_w_range663w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sbit_w_range686w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sbit_w_range706w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sel_w_range668w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sel_w_range689w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sel_w_range711w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sel_w_range733w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sel_w_range755w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_smux_w_range759w : STD_LOGIC_VECTOR (25 DOWNTO 0);
BEGIN
loop0 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w681w682w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range668w681w(0) AND wire_lbarrel_shift_w679w(i);
END GENERATE loop0;
loop1 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w677w678w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range668w677w(0) AND wire_lbarrel_shift_w676w(i);
END GENERATE loop1;
loop2 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w702w703w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range689w702w(0) AND wire_lbarrel_shift_w700w(i);
END GENERATE loop2;
loop3 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w698w699w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range689w698w(0) AND wire_lbarrel_shift_w697w(i);
END GENERATE loop3;
loop4 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w724w725w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range711w724w(0) AND wire_lbarrel_shift_w722w(i);
END GENERATE loop4;
loop5 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w720w721w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range711w720w(0) AND wire_lbarrel_shift_w719w(i);
END GENERATE loop5;
loop6 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w746w747w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range733w746w(0) AND wire_lbarrel_shift_w744w(i);
END GENERATE loop6;
loop7 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w742w743w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range733w742w(0) AND wire_lbarrel_shift_w741w(i);
END GENERATE loop7;
loop8 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w768w769w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range755w768w(0) AND wire_lbarrel_shift_w766w(i);
END GENERATE loop8;
loop9 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w764w765w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range755w764w(0) AND wire_lbarrel_shift_w763w(i);
END GENERATE loop9;
loop10 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w673w674w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range668w673w(0) AND wire_lbarrel_shift_w_sbit_w_range663w(i);
END GENERATE loop10;
loop11 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w694w695w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range689w694w(0) AND wire_lbarrel_shift_w_sbit_w_range686w(i);
END GENERATE loop11;
loop12 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w716w717w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range711w716w(0) AND wire_lbarrel_shift_w_sbit_w_range706w(i);
END GENERATE loop12;
loop13 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w738w739w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range733w738w(0) AND wire_lbarrel_shift_w_sbit_w_range728w(i);
END GENERATE loop13;
loop14 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w760w761w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range755w760w(0) AND wire_lbarrel_shift_w_sbit_w_range750w(i);
END GENERATE loop14;
wire_lbarrel_shift_w_lg_w_sel_w_range668w681w(0) <= wire_lbarrel_shift_w_sel_w_range668w(0) AND wire_lbarrel_shift_w_lg_w_dir_w_range665w680w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range668w677w(0) <= wire_lbarrel_shift_w_sel_w_range668w(0) AND wire_lbarrel_shift_w_dir_w_range665w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range689w702w(0) <= wire_lbarrel_shift_w_sel_w_range689w(0) AND wire_lbarrel_shift_w_lg_w_dir_w_range687w701w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range689w698w(0) <= wire_lbarrel_shift_w_sel_w_range689w(0) AND wire_lbarrel_shift_w_dir_w_range687w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range711w724w(0) <= wire_lbarrel_shift_w_sel_w_range711w(0) AND wire_lbarrel_shift_w_lg_w_dir_w_range708w723w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range711w720w(0) <= wire_lbarrel_shift_w_sel_w_range711w(0) AND wire_lbarrel_shift_w_dir_w_range708w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range733w746w(0) <= wire_lbarrel_shift_w_sel_w_range733w(0) AND wire_lbarrel_shift_w_lg_w_dir_w_range730w745w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range733w742w(0) <= wire_lbarrel_shift_w_sel_w_range733w(0) AND wire_lbarrel_shift_w_dir_w_range730w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range755w768w(0) <= wire_lbarrel_shift_w_sel_w_range755w(0) AND wire_lbarrel_shift_w_lg_w_dir_w_range752w767w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range755w764w(0) <= wire_lbarrel_shift_w_sel_w_range755w(0) AND wire_lbarrel_shift_w_dir_w_range752w(0);
wire_lbarrel_shift_w_lg_w_dir_w_range665w680w(0) <= NOT wire_lbarrel_shift_w_dir_w_range665w(0);
wire_lbarrel_shift_w_lg_w_dir_w_range687w701w(0) <= NOT wire_lbarrel_shift_w_dir_w_range687w(0);
wire_lbarrel_shift_w_lg_w_dir_w_range708w723w(0) <= NOT wire_lbarrel_shift_w_dir_w_range708w(0);
wire_lbarrel_shift_w_lg_w_dir_w_range730w745w(0) <= NOT wire_lbarrel_shift_w_dir_w_range730w(0);
wire_lbarrel_shift_w_lg_w_dir_w_range752w767w(0) <= NOT wire_lbarrel_shift_w_dir_w_range752w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range668w673w(0) <= NOT wire_lbarrel_shift_w_sel_w_range668w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range689w694w(0) <= NOT wire_lbarrel_shift_w_sel_w_range689w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range711w716w(0) <= NOT wire_lbarrel_shift_w_sel_w_range711w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range733w738w(0) <= NOT wire_lbarrel_shift_w_sel_w_range733w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range755w760w(0) <= NOT wire_lbarrel_shift_w_sel_w_range755w(0);
loop15 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range668w681w682w683w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w681w682w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w677w678w(i);
END GENERATE loop15;
loop16 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range689w702w703w704w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w702w703w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w698w699w(i);
END GENERATE loop16;
loop17 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range711w724w725w726w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w724w725w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w720w721w(i);
END GENERATE loop17;
loop18 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range733w746w747w748w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w746w747w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w742w743w(i);
END GENERATE loop18;
loop19 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range755w768w769w770w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w768w769w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w764w765w(i);
END GENERATE loop19;
loop20 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w684w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range668w681w682w683w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w673w674w(i);
END GENERATE loop20;
loop21 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w705w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range689w702w703w704w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w694w695w(i);
END GENERATE loop21;
loop22 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w727w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range711w724w725w726w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w716w717w(i);
END GENERATE loop22;
loop23 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w749w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range733w746w747w748w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w738w739w(i);
END GENERATE loop23;
loop24 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w771w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range755w768w769w770w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w760w761w(i);
END GENERATE loop24;
dir_w <= ( dir_pipe(0) & dir_w(3 DOWNTO 0) & direction_w);
direction_w <= '0';
pad_w <= (OTHERS => '0');
result <= sbit_w(155 DOWNTO 130);
sbit_w <= ( sbit_piper1d & smux_w(103 DOWNTO 0) & data);
sel_w <= ( distance(4 DOWNTO 0));
smux_w <= ( wire_lbarrel_shift_w771w & wire_lbarrel_shift_w749w & wire_lbarrel_shift_w727w & wire_lbarrel_shift_w705w & wire_lbarrel_shift_w684w);
wire_lbarrel_shift_w676w <= ( pad_w(0) & sbit_w(25 DOWNTO 1));
wire_lbarrel_shift_w679w <= ( sbit_w(24 DOWNTO 0) & pad_w(0));
wire_lbarrel_shift_w697w <= ( pad_w(1 DOWNTO 0) & sbit_w(51 DOWNTO 28));
wire_lbarrel_shift_w700w <= ( sbit_w(49 DOWNTO 26) & pad_w(1 DOWNTO 0));
wire_lbarrel_shift_w719w <= ( pad_w(3 DOWNTO 0) & sbit_w(77 DOWNTO 56));
wire_lbarrel_shift_w722w <= ( sbit_w(73 DOWNTO 52) & pad_w(3 DOWNTO 0));
wire_lbarrel_shift_w741w <= ( pad_w(7 DOWNTO 0) & sbit_w(103 DOWNTO 86));
wire_lbarrel_shift_w744w <= ( sbit_w(95 DOWNTO 78) & pad_w(7 DOWNTO 0));
wire_lbarrel_shift_w763w <= ( pad_w(15 DOWNTO 0) & sbit_w(129 DOWNTO 120));
wire_lbarrel_shift_w766w <= ( sbit_w(113 DOWNTO 104) & pad_w(15 DOWNTO 0));
wire_lbarrel_shift_w_dir_w_range665w(0) <= dir_w(0);
wire_lbarrel_shift_w_dir_w_range687w(0) <= dir_w(1);
wire_lbarrel_shift_w_dir_w_range708w(0) <= dir_w(2);
wire_lbarrel_shift_w_dir_w_range730w(0) <= dir_w(3);
wire_lbarrel_shift_w_dir_w_range752w(0) <= dir_w(4);
wire_lbarrel_shift_w_sbit_w_range728w <= sbit_w(103 DOWNTO 78);
wire_lbarrel_shift_w_sbit_w_range750w <= sbit_w(129 DOWNTO 104);
wire_lbarrel_shift_w_sbit_w_range663w <= sbit_w(25 DOWNTO 0);
wire_lbarrel_shift_w_sbit_w_range686w <= sbit_w(51 DOWNTO 26);
wire_lbarrel_shift_w_sbit_w_range706w <= sbit_w(77 DOWNTO 52);
wire_lbarrel_shift_w_sel_w_range668w(0) <= sel_w(0);
wire_lbarrel_shift_w_sel_w_range689w(0) <= sel_w(1);
wire_lbarrel_shift_w_sel_w_range711w(0) <= sel_w(2);
wire_lbarrel_shift_w_sel_w_range733w(0) <= sel_w(3);
wire_lbarrel_shift_w_sel_w_range755w(0) <= sel_w(4);
wire_lbarrel_shift_w_smux_w_range759w <= smux_w(129 DOWNTO 104);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN dir_pipe <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN dir_pipe(0) <= ( dir_w(4));
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sbit_piper1d <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sbit_piper1d <= wire_lbarrel_shift_w_smux_w_range759w;
END IF;
END IF;
END PROCESS;
END RTL; --add_flt_stratix5_speed_altbarrel_shift_nud
--altbarrel_shift CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix V" PIPELINE=2 REGISTER_OUTPUT="NO" SHIFTDIR="RIGHT" WIDTH=26 WIDTHDIST=5 aclr clk_en clock data distance result
--VERSION_BEGIN 13.1 cbx_altbarrel_shift 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--synthesis_resources = reg 58
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_speed_altbarrel_shift_u1g IS
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (25 DOWNTO 0);
distance : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (25 DOWNTO 0)
);
END add_flt_stratix5_speed_altbarrel_shift_u1g;
ARCHITECTURE RTL OF add_flt_stratix5_speed_altbarrel_shift_u1g IS
SIGNAL dir_pipe : STD_LOGIC_VECTOR(1 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL sbit_piper1d : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL sbit_piper2d : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL sel_pipec2r1d : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sel_pipec3r1d : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sel_pipec4r1d : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sel_pipec4r2d : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range783w796w797w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range783w792w793w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range804w817w818w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range804w813w814w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range827w839w840w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range827w835w836w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range846w858w859w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range846w854w855w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range867w879w880w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range867w875w876w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range783w788w789w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range804w809w810w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range827w831w832w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range846w850w851w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range867w871w872w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range783w796w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range783w792w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range804w817w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range804w813w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range827w839w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range827w835w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range846w858w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range846w854w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range867w879w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range867w875w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_dir_w_range780w795w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_dir_w_range802w816w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_dir_w_range825w838w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_dir_w_range844w857w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_dir_w_range865w878w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range783w788w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range804w809w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range827w831w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range846w850w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range867w871w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range783w796w797w798w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range804w817w818w819w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range827w839w840w841w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range846w858w859w860w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range867w879w880w881w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w799w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w820w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w842w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w861w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w882w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL dir_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL direction_w : STD_LOGIC;
SIGNAL pad_w : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sbit_w : STD_LOGIC_VECTOR (155 DOWNTO 0);
SIGNAL sel_w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL smux_w : STD_LOGIC_VECTOR (129 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w791w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w794w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w812w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w815w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w834w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w837w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w853w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w856w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w874w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w877w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_dir_w_range780w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_dir_w_range802w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_dir_w_range825w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_dir_w_range844w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_dir_w_range865w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sbit_w_range843w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sbit_w_range862w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sbit_w_range778w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sbit_w_range801w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sbit_w_range821w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sel_w_range783w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sel_w_range804w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sel_w_range827w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sel_w_range846w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sel_w_range867w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_smux_w_range849w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_smux_w_range808w : STD_LOGIC_VECTOR (25 DOWNTO 0);
BEGIN
loop25 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range783w796w797w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range783w796w(0) AND wire_rbarrel_shift_w794w(i);
END GENERATE loop25;
loop26 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range783w792w793w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range783w792w(0) AND wire_rbarrel_shift_w791w(i);
END GENERATE loop26;
loop27 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range804w817w818w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range804w817w(0) AND wire_rbarrel_shift_w815w(i);
END GENERATE loop27;
loop28 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range804w813w814w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range804w813w(0) AND wire_rbarrel_shift_w812w(i);
END GENERATE loop28;
loop29 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range827w839w840w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range827w839w(0) AND wire_rbarrel_shift_w837w(i);
END GENERATE loop29;
loop30 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range827w835w836w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range827w835w(0) AND wire_rbarrel_shift_w834w(i);
END GENERATE loop30;
loop31 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range846w858w859w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range846w858w(0) AND wire_rbarrel_shift_w856w(i);
END GENERATE loop31;
loop32 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range846w854w855w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range846w854w(0) AND wire_rbarrel_shift_w853w(i);
END GENERATE loop32;
loop33 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range867w879w880w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range867w879w(0) AND wire_rbarrel_shift_w877w(i);
END GENERATE loop33;
loop34 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range867w875w876w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range867w875w(0) AND wire_rbarrel_shift_w874w(i);
END GENERATE loop34;
loop35 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range783w788w789w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range783w788w(0) AND wire_rbarrel_shift_w_sbit_w_range778w(i);
END GENERATE loop35;
loop36 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range804w809w810w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range804w809w(0) AND wire_rbarrel_shift_w_sbit_w_range801w(i);
END GENERATE loop36;
loop37 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range827w831w832w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range827w831w(0) AND wire_rbarrel_shift_w_sbit_w_range821w(i);
END GENERATE loop37;
loop38 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range846w850w851w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range846w850w(0) AND wire_rbarrel_shift_w_sbit_w_range843w(i);
END GENERATE loop38;
loop39 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range867w871w872w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range867w871w(0) AND wire_rbarrel_shift_w_sbit_w_range862w(i);
END GENERATE loop39;
wire_rbarrel_shift_w_lg_w_sel_w_range783w796w(0) <= wire_rbarrel_shift_w_sel_w_range783w(0) AND wire_rbarrel_shift_w_lg_w_dir_w_range780w795w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range783w792w(0) <= wire_rbarrel_shift_w_sel_w_range783w(0) AND wire_rbarrel_shift_w_dir_w_range780w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range804w817w(0) <= wire_rbarrel_shift_w_sel_w_range804w(0) AND wire_rbarrel_shift_w_lg_w_dir_w_range802w816w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range804w813w(0) <= wire_rbarrel_shift_w_sel_w_range804w(0) AND wire_rbarrel_shift_w_dir_w_range802w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range827w839w(0) <= wire_rbarrel_shift_w_sel_w_range827w(0) AND wire_rbarrel_shift_w_lg_w_dir_w_range825w838w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range827w835w(0) <= wire_rbarrel_shift_w_sel_w_range827w(0) AND wire_rbarrel_shift_w_dir_w_range825w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range846w858w(0) <= wire_rbarrel_shift_w_sel_w_range846w(0) AND wire_rbarrel_shift_w_lg_w_dir_w_range844w857w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range846w854w(0) <= wire_rbarrel_shift_w_sel_w_range846w(0) AND wire_rbarrel_shift_w_dir_w_range844w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range867w879w(0) <= wire_rbarrel_shift_w_sel_w_range867w(0) AND wire_rbarrel_shift_w_lg_w_dir_w_range865w878w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range867w875w(0) <= wire_rbarrel_shift_w_sel_w_range867w(0) AND wire_rbarrel_shift_w_dir_w_range865w(0);
wire_rbarrel_shift_w_lg_w_dir_w_range780w795w(0) <= NOT wire_rbarrel_shift_w_dir_w_range780w(0);
wire_rbarrel_shift_w_lg_w_dir_w_range802w816w(0) <= NOT wire_rbarrel_shift_w_dir_w_range802w(0);
wire_rbarrel_shift_w_lg_w_dir_w_range825w838w(0) <= NOT wire_rbarrel_shift_w_dir_w_range825w(0);
wire_rbarrel_shift_w_lg_w_dir_w_range844w857w(0) <= NOT wire_rbarrel_shift_w_dir_w_range844w(0);
wire_rbarrel_shift_w_lg_w_dir_w_range865w878w(0) <= NOT wire_rbarrel_shift_w_dir_w_range865w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range783w788w(0) <= NOT wire_rbarrel_shift_w_sel_w_range783w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range804w809w(0) <= NOT wire_rbarrel_shift_w_sel_w_range804w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range827w831w(0) <= NOT wire_rbarrel_shift_w_sel_w_range827w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range846w850w(0) <= NOT wire_rbarrel_shift_w_sel_w_range846w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range867w871w(0) <= NOT wire_rbarrel_shift_w_sel_w_range867w(0);
loop40 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range783w796w797w798w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range783w796w797w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range783w792w793w(i);
END GENERATE loop40;
loop41 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range804w817w818w819w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range804w817w818w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range804w813w814w(i);
END GENERATE loop41;
loop42 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range827w839w840w841w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range827w839w840w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range827w835w836w(i);
END GENERATE loop42;
loop43 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range846w858w859w860w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range846w858w859w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range846w854w855w(i);
END GENERATE loop43;
loop44 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range867w879w880w881w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range867w879w880w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range867w875w876w(i);
END GENERATE loop44;
loop45 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w799w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range783w796w797w798w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range783w788w789w(i);
END GENERATE loop45;
loop46 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w820w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range804w817w818w819w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range804w809w810w(i);
END GENERATE loop46;
loop47 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w842w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range827w839w840w841w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range827w831w832w(i);
END GENERATE loop47;
loop48 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w861w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range846w858w859w860w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range846w850w851w(i);
END GENERATE loop48;
loop49 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w882w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range867w879w880w881w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range867w871w872w(i);
END GENERATE loop49;
dir_w <= ( dir_w(4) & dir_pipe(1) & dir_w(2) & dir_pipe(0) & dir_w(0) & direction_w);
direction_w <= '1';
pad_w <= (OTHERS => '0');
result <= sbit_w(155 DOWNTO 130);
sbit_w <= ( smux_w(129 DOWNTO 104) & sbit_piper2d & smux_w(77 DOWNTO 52) & sbit_piper1d & smux_w(25 DOWNTO 0) & data);
sel_w <= ( sel_pipec4r2d & sel_pipec3r1d & sel_pipec2r1d & distance(1 DOWNTO 0));
smux_w <= ( wire_rbarrel_shift_w882w & wire_rbarrel_shift_w861w & wire_rbarrel_shift_w842w & wire_rbarrel_shift_w820w & wire_rbarrel_shift_w799w);
wire_rbarrel_shift_w791w <= ( pad_w(0) & sbit_w(25 DOWNTO 1));
wire_rbarrel_shift_w794w <= ( sbit_w(24 DOWNTO 0) & pad_w(0));
wire_rbarrel_shift_w812w <= ( pad_w(1 DOWNTO 0) & sbit_w(51 DOWNTO 28));
wire_rbarrel_shift_w815w <= ( sbit_w(49 DOWNTO 26) & pad_w(1 DOWNTO 0));
wire_rbarrel_shift_w834w <= ( pad_w(3 DOWNTO 0) & sbit_w(77 DOWNTO 56));
wire_rbarrel_shift_w837w <= ( sbit_w(73 DOWNTO 52) & pad_w(3 DOWNTO 0));
wire_rbarrel_shift_w853w <= ( pad_w(7 DOWNTO 0) & sbit_w(103 DOWNTO 86));
wire_rbarrel_shift_w856w <= ( sbit_w(95 DOWNTO 78) & pad_w(7 DOWNTO 0));
wire_rbarrel_shift_w874w <= ( pad_w(15 DOWNTO 0) & sbit_w(129 DOWNTO 120));
wire_rbarrel_shift_w877w <= ( sbit_w(113 DOWNTO 104) & pad_w(15 DOWNTO 0));
wire_rbarrel_shift_w_dir_w_range780w(0) <= dir_w(0);
wire_rbarrel_shift_w_dir_w_range802w(0) <= dir_w(1);
wire_rbarrel_shift_w_dir_w_range825w(0) <= dir_w(2);
wire_rbarrel_shift_w_dir_w_range844w(0) <= dir_w(3);
wire_rbarrel_shift_w_dir_w_range865w(0) <= dir_w(4);
wire_rbarrel_shift_w_sbit_w_range843w <= sbit_w(103 DOWNTO 78);
wire_rbarrel_shift_w_sbit_w_range862w <= sbit_w(129 DOWNTO 104);
wire_rbarrel_shift_w_sbit_w_range778w <= sbit_w(25 DOWNTO 0);
wire_rbarrel_shift_w_sbit_w_range801w <= sbit_w(51 DOWNTO 26);
wire_rbarrel_shift_w_sbit_w_range821w <= sbit_w(77 DOWNTO 52);
wire_rbarrel_shift_w_sel_w_range783w(0) <= sel_w(0);
wire_rbarrel_shift_w_sel_w_range804w(0) <= sel_w(1);
wire_rbarrel_shift_w_sel_w_range827w(0) <= sel_w(2);
wire_rbarrel_shift_w_sel_w_range846w(0) <= sel_w(3);
wire_rbarrel_shift_w_sel_w_range867w(0) <= sel_w(4);
wire_rbarrel_shift_w_smux_w_range849w <= smux_w(103 DOWNTO 78);
wire_rbarrel_shift_w_smux_w_range808w <= smux_w(51 DOWNTO 26);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN dir_pipe <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN dir_pipe <= ( dir_w(3) & dir_w(1));
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sbit_piper1d <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sbit_piper1d <= wire_rbarrel_shift_w_smux_w_range808w;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sbit_piper2d <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sbit_piper2d <= wire_rbarrel_shift_w_smux_w_range849w;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sel_pipec2r1d <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sel_pipec2r1d <= distance(2);
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sel_pipec3r1d <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sel_pipec3r1d <= distance(3);
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sel_pipec4r1d <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sel_pipec4r1d <= distance(4);
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sel_pipec4r2d <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sel_pipec4r2d <= sel_pipec4r1d;
END IF;
END IF;
END PROCESS;
END RTL; --add_flt_stratix5_speed_altbarrel_shift_u1g
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" PIPELINE=1 WIDTH=32 WIDTHAD=5 aclr clk_en clock data q
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" PIPELINE=0 WIDTH=16 WIDTHAD=4 data q
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=8 WIDTHAD=3 data q zero
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=4 WIDTHAD=2 data q zero
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=2 WIDTHAD=1 data q zero
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_speed_altpriority_encoder_3e8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END add_flt_stratix5_speed_altpriority_encoder_3e8;
ARCHITECTURE RTL OF add_flt_stratix5_speed_altpriority_encoder_3e8 IS
BEGIN
q(0) <= ( data(1));
zero <= (NOT (data(0) OR data(1)));
END RTL; --add_flt_stratix5_speed_altpriority_encoder_3e8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_speed_altpriority_encoder_6e8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END add_flt_stratix5_speed_altpriority_encoder_6e8;
ARCHITECTURE RTL OF add_flt_stratix5_speed_altpriority_encoder_6e8 IS
SIGNAL wire_altpriority_encoder13_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder13_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder14_w_lg_w_lg_zero916w917w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder14_w_lg_zero918w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder14_w_lg_zero916w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder14_w_lg_w_lg_zero918w919w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder14_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder14_zero : STD_LOGIC;
COMPONENT add_flt_stratix5_speed_altpriority_encoder_3e8
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder14_w_lg_zero916w & wire_altpriority_encoder14_w_lg_w_lg_zero918w919w);
zero <= (wire_altpriority_encoder13_zero AND wire_altpriority_encoder14_zero);
altpriority_encoder13 : add_flt_stratix5_speed_altpriority_encoder_3e8
PORT MAP (
data => data(1 DOWNTO 0),
q => wire_altpriority_encoder13_q,
zero => wire_altpriority_encoder13_zero
);
wire_altpriority_encoder14_w_lg_w_lg_zero916w917w(0) <= wire_altpriority_encoder14_w_lg_zero916w(0) AND wire_altpriority_encoder14_q(0);
wire_altpriority_encoder14_w_lg_zero918w(0) <= wire_altpriority_encoder14_zero AND wire_altpriority_encoder13_q(0);
wire_altpriority_encoder14_w_lg_zero916w(0) <= NOT wire_altpriority_encoder14_zero;
wire_altpriority_encoder14_w_lg_w_lg_zero918w919w(0) <= wire_altpriority_encoder14_w_lg_zero918w(0) OR wire_altpriority_encoder14_w_lg_w_lg_zero916w917w(0);
altpriority_encoder14 : add_flt_stratix5_speed_altpriority_encoder_3e8
PORT MAP (
data => data(3 DOWNTO 2),
q => wire_altpriority_encoder14_q,
zero => wire_altpriority_encoder14_zero
);
END RTL; --add_flt_stratix5_speed_altpriority_encoder_6e8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_speed_altpriority_encoder_be8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END add_flt_stratix5_speed_altpriority_encoder_be8;
ARCHITECTURE RTL OF add_flt_stratix5_speed_altpriority_encoder_be8 IS
SIGNAL wire_altpriority_encoder11_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder11_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder12_w_lg_w_lg_zero906w907w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder12_w_lg_zero908w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder12_w_lg_zero906w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder12_w_lg_w_lg_zero908w909w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder12_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder12_zero : STD_LOGIC;
COMPONENT add_flt_stratix5_speed_altpriority_encoder_6e8
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder12_w_lg_zero906w & wire_altpriority_encoder12_w_lg_w_lg_zero908w909w);
zero <= (wire_altpriority_encoder11_zero AND wire_altpriority_encoder12_zero);
altpriority_encoder11 : add_flt_stratix5_speed_altpriority_encoder_6e8
PORT MAP (
data => data(3 DOWNTO 0),
q => wire_altpriority_encoder11_q,
zero => wire_altpriority_encoder11_zero
);
loop50 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder12_w_lg_w_lg_zero906w907w(i) <= wire_altpriority_encoder12_w_lg_zero906w(0) AND wire_altpriority_encoder12_q(i);
END GENERATE loop50;
loop51 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder12_w_lg_zero908w(i) <= wire_altpriority_encoder12_zero AND wire_altpriority_encoder11_q(i);
END GENERATE loop51;
wire_altpriority_encoder12_w_lg_zero906w(0) <= NOT wire_altpriority_encoder12_zero;
loop52 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder12_w_lg_w_lg_zero908w909w(i) <= wire_altpriority_encoder12_w_lg_zero908w(i) OR wire_altpriority_encoder12_w_lg_w_lg_zero906w907w(i);
END GENERATE loop52;
altpriority_encoder12 : add_flt_stratix5_speed_altpriority_encoder_6e8
PORT MAP (
data => data(7 DOWNTO 4),
q => wire_altpriority_encoder12_q,
zero => wire_altpriority_encoder12_zero
);
END RTL; --add_flt_stratix5_speed_altpriority_encoder_be8
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=8 WIDTHAD=3 data q
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=4 WIDTHAD=2 data q
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=2 WIDTHAD=1 data q
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_speed_altpriority_encoder_3v7 IS
PORT
(
data : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END add_flt_stratix5_speed_altpriority_encoder_3v7;
ARCHITECTURE RTL OF add_flt_stratix5_speed_altpriority_encoder_3v7 IS
BEGIN
q(0) <= ( data(1));
END RTL; --add_flt_stratix5_speed_altpriority_encoder_3v7
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_speed_altpriority_encoder_6v7 IS
PORT
(
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END add_flt_stratix5_speed_altpriority_encoder_6v7;
ARCHITECTURE RTL OF add_flt_stratix5_speed_altpriority_encoder_6v7 IS
SIGNAL wire_altpriority_encoder17_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_w_lg_w_lg_zero941w942w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_w_lg_zero943w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_w_lg_zero941w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_w_lg_w_lg_zero943w944w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_zero : STD_LOGIC;
COMPONENT add_flt_stratix5_speed_altpriority_encoder_3v7
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT;
COMPONENT add_flt_stratix5_speed_altpriority_encoder_3e8
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder18_w_lg_zero941w & wire_altpriority_encoder18_w_lg_w_lg_zero943w944w);
altpriority_encoder17 : add_flt_stratix5_speed_altpriority_encoder_3v7
PORT MAP (
data => data(1 DOWNTO 0),
q => wire_altpriority_encoder17_q
);
wire_altpriority_encoder18_w_lg_w_lg_zero941w942w(0) <= wire_altpriority_encoder18_w_lg_zero941w(0) AND wire_altpriority_encoder18_q(0);
wire_altpriority_encoder18_w_lg_zero943w(0) <= wire_altpriority_encoder18_zero AND wire_altpriority_encoder17_q(0);
wire_altpriority_encoder18_w_lg_zero941w(0) <= NOT wire_altpriority_encoder18_zero;
wire_altpriority_encoder18_w_lg_w_lg_zero943w944w(0) <= wire_altpriority_encoder18_w_lg_zero943w(0) OR wire_altpriority_encoder18_w_lg_w_lg_zero941w942w(0);
altpriority_encoder18 : add_flt_stratix5_speed_altpriority_encoder_3e8
PORT MAP (
data => data(3 DOWNTO 2),
q => wire_altpriority_encoder18_q,
zero => wire_altpriority_encoder18_zero
);
END RTL; --add_flt_stratix5_speed_altpriority_encoder_6v7
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_speed_altpriority_encoder_bv7 IS
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
);
END add_flt_stratix5_speed_altpriority_encoder_bv7;
ARCHITECTURE RTL OF add_flt_stratix5_speed_altpriority_encoder_bv7 IS
SIGNAL wire_altpriority_encoder15_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_w_lg_w_lg_zero932w933w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_w_lg_zero934w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_w_lg_zero932w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_w_lg_w_lg_zero934w935w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_zero : STD_LOGIC;
COMPONENT add_flt_stratix5_speed_altpriority_encoder_6v7
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END COMPONENT;
COMPONENT add_flt_stratix5_speed_altpriority_encoder_6e8
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder16_w_lg_zero932w & wire_altpriority_encoder16_w_lg_w_lg_zero934w935w);
altpriority_encoder15 : add_flt_stratix5_speed_altpriority_encoder_6v7
PORT MAP (
data => data(3 DOWNTO 0),
q => wire_altpriority_encoder15_q
);
loop53 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder16_w_lg_w_lg_zero932w933w(i) <= wire_altpriority_encoder16_w_lg_zero932w(0) AND wire_altpriority_encoder16_q(i);
END GENERATE loop53;
loop54 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder16_w_lg_zero934w(i) <= wire_altpriority_encoder16_zero AND wire_altpriority_encoder15_q(i);
END GENERATE loop54;
wire_altpriority_encoder16_w_lg_zero932w(0) <= NOT wire_altpriority_encoder16_zero;
loop55 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder16_w_lg_w_lg_zero934w935w(i) <= wire_altpriority_encoder16_w_lg_zero934w(i) OR wire_altpriority_encoder16_w_lg_w_lg_zero932w933w(i);
END GENERATE loop55;
altpriority_encoder16 : add_flt_stratix5_speed_altpriority_encoder_6e8
PORT MAP (
data => data(7 DOWNTO 4),
q => wire_altpriority_encoder16_q,
zero => wire_altpriority_encoder16_zero
);
END RTL; --add_flt_stratix5_speed_altpriority_encoder_bv7
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_speed_altpriority_encoder_uv8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END add_flt_stratix5_speed_altpriority_encoder_uv8;
ARCHITECTURE RTL OF add_flt_stratix5_speed_altpriority_encoder_uv8 IS
SIGNAL wire_altpriority_encoder10_w_lg_w_lg_zero897w898w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder10_w_lg_zero899w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder10_w_lg_zero897w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder10_w_lg_w_lg_zero899w900w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder10_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder10_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder9_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
COMPONENT add_flt_stratix5_speed_altpriority_encoder_be8
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT add_flt_stratix5_speed_altpriority_encoder_bv7
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder10_w_lg_zero897w & wire_altpriority_encoder10_w_lg_w_lg_zero899w900w);
loop56 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder10_w_lg_w_lg_zero897w898w(i) <= wire_altpriority_encoder10_w_lg_zero897w(0) AND wire_altpriority_encoder10_q(i);
END GENERATE loop56;
loop57 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder10_w_lg_zero899w(i) <= wire_altpriority_encoder10_zero AND wire_altpriority_encoder9_q(i);
END GENERATE loop57;
wire_altpriority_encoder10_w_lg_zero897w(0) <= NOT wire_altpriority_encoder10_zero;
loop58 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder10_w_lg_w_lg_zero899w900w(i) <= wire_altpriority_encoder10_w_lg_zero899w(i) OR wire_altpriority_encoder10_w_lg_w_lg_zero897w898w(i);
END GENERATE loop58;
altpriority_encoder10 : add_flt_stratix5_speed_altpriority_encoder_be8
PORT MAP (
data => data(15 DOWNTO 8),
q => wire_altpriority_encoder10_q,
zero => wire_altpriority_encoder10_zero
);
altpriority_encoder9 : add_flt_stratix5_speed_altpriority_encoder_bv7
PORT MAP (
data => data(7 DOWNTO 0),
q => wire_altpriority_encoder9_q
);
END RTL; --add_flt_stratix5_speed_altpriority_encoder_uv8
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" PIPELINE=0 WIDTH=16 WIDTHAD=4 data q zero
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_speed_altpriority_encoder_ue9 IS
PORT
(
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
zero : OUT STD_LOGIC
);
END add_flt_stratix5_speed_altpriority_encoder_ue9;
ARCHITECTURE RTL OF add_flt_stratix5_speed_altpriority_encoder_ue9 IS
SIGNAL wire_altpriority_encoder19_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder19_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder20_w_lg_w_lg_zero953w954w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder20_w_lg_zero955w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder20_w_lg_zero953w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder20_w_lg_w_lg_zero955w956w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder20_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder20_zero : STD_LOGIC;
COMPONENT add_flt_stratix5_speed_altpriority_encoder_be8
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder20_w_lg_zero953w & wire_altpriority_encoder20_w_lg_w_lg_zero955w956w);
zero <= (wire_altpriority_encoder19_zero AND wire_altpriority_encoder20_zero);
altpriority_encoder19 : add_flt_stratix5_speed_altpriority_encoder_be8
PORT MAP (
data => data(7 DOWNTO 0),
q => wire_altpriority_encoder19_q,
zero => wire_altpriority_encoder19_zero
);
loop59 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder20_w_lg_w_lg_zero953w954w(i) <= wire_altpriority_encoder20_w_lg_zero953w(0) AND wire_altpriority_encoder20_q(i);
END GENERATE loop59;
loop60 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder20_w_lg_zero955w(i) <= wire_altpriority_encoder20_zero AND wire_altpriority_encoder19_q(i);
END GENERATE loop60;
wire_altpriority_encoder20_w_lg_zero953w(0) <= NOT wire_altpriority_encoder20_zero;
loop61 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder20_w_lg_w_lg_zero955w956w(i) <= wire_altpriority_encoder20_w_lg_zero955w(i) OR wire_altpriority_encoder20_w_lg_w_lg_zero953w954w(i);
END GENERATE loop61;
altpriority_encoder20 : add_flt_stratix5_speed_altpriority_encoder_be8
PORT MAP (
data => data(15 DOWNTO 8),
q => wire_altpriority_encoder20_q,
zero => wire_altpriority_encoder20_zero
);
END RTL; --add_flt_stratix5_speed_altpriority_encoder_ue9
--synthesis_resources = reg 5
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_speed_altpriority_encoder_ou8 IS
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END add_flt_stratix5_speed_altpriority_encoder_ou8;
ARCHITECTURE RTL OF add_flt_stratix5_speed_altpriority_encoder_ou8 IS
SIGNAL wire_altpriority_encoder7_q : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_w_lg_w_lg_zero887w888w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_w_lg_zero889w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_w_lg_zero887w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_w_lg_w_lg_zero889w890w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_q : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_zero : STD_LOGIC;
SIGNAL pipeline_q_dffe : STD_LOGIC_VECTOR(4 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL tmp_q_wire : STD_LOGIC_VECTOR (4 DOWNTO 0);
COMPONENT add_flt_stratix5_speed_altpriority_encoder_uv8
PORT
(
data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
COMPONENT add_flt_stratix5_speed_altpriority_encoder_ue9
PORT
(
data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= pipeline_q_dffe;
tmp_q_wire <= ( wire_altpriority_encoder8_w_lg_zero887w & wire_altpriority_encoder8_w_lg_w_lg_zero889w890w);
altpriority_encoder7 : add_flt_stratix5_speed_altpriority_encoder_uv8
PORT MAP (
data => data(15 DOWNTO 0),
q => wire_altpriority_encoder7_q
);
loop62 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder8_w_lg_w_lg_zero887w888w(i) <= wire_altpriority_encoder8_w_lg_zero887w(0) AND wire_altpriority_encoder8_q(i);
END GENERATE loop62;
loop63 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder8_w_lg_zero889w(i) <= wire_altpriority_encoder8_zero AND wire_altpriority_encoder7_q(i);
END GENERATE loop63;
wire_altpriority_encoder8_w_lg_zero887w(0) <= NOT wire_altpriority_encoder8_zero;
loop64 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder8_w_lg_w_lg_zero889w890w(i) <= wire_altpriority_encoder8_w_lg_zero889w(i) OR wire_altpriority_encoder8_w_lg_w_lg_zero887w888w(i);
END GENERATE loop64;
altpriority_encoder8 : add_flt_stratix5_speed_altpriority_encoder_ue9
PORT MAP (
data => data(31 DOWNTO 16),
q => wire_altpriority_encoder8_q,
zero => wire_altpriority_encoder8_zero
);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN pipeline_q_dffe <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN pipeline_q_dffe <= tmp_q_wire;
END IF;
END IF;
END PROCESS;
END RTL; --add_flt_stratix5_speed_altpriority_encoder_ou8
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" PIPELINE=2 WIDTH=32 WIDTHAD=5 aclr clk_en clock data q
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" PIPELINE=1 WIDTH=16 WIDTHAD=4 aclr clk_en clock data q zero
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" PIPELINE=0 WIDTH=8 WIDTHAD=3 data q zero
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=4 WIDTHAD=2 data q zero
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=2 WIDTHAD=1 data q zero
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_speed_altpriority_encoder_nh8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END add_flt_stratix5_speed_altpriority_encoder_nh8;
ARCHITECTURE RTL OF add_flt_stratix5_speed_altpriority_encoder_nh8 IS
SIGNAL wire_altpriority_encoder27_w_lg_w_data_range1008w1010w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_w_data_range1008w : STD_LOGIC_VECTOR (0 DOWNTO 0);
BEGIN
wire_altpriority_encoder27_w_lg_w_data_range1008w1010w(0) <= NOT wire_altpriority_encoder27_w_data_range1008w(0);
q <= ( wire_altpriority_encoder27_w_lg_w_data_range1008w1010w);
zero <= (NOT (data(0) OR data(1)));
wire_altpriority_encoder27_w_data_range1008w(0) <= data(0);
END RTL; --add_flt_stratix5_speed_altpriority_encoder_nh8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_speed_altpriority_encoder_qh8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END add_flt_stratix5_speed_altpriority_encoder_qh8;
ARCHITECTURE RTL OF add_flt_stratix5_speed_altpriority_encoder_qh8 IS
SIGNAL wire_altpriority_encoder27_w_lg_w_lg_zero1000w1001w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_w_lg_zero1002w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_w_lg_zero1000w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_w_lg_w_lg_zero1002w1003w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder28_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder28_zero : STD_LOGIC;
COMPONENT add_flt_stratix5_speed_altpriority_encoder_nh8
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder27_zero & wire_altpriority_encoder27_w_lg_w_lg_zero1002w1003w);
zero <= (wire_altpriority_encoder27_zero AND wire_altpriority_encoder28_zero);
wire_altpriority_encoder27_w_lg_w_lg_zero1000w1001w(0) <= wire_altpriority_encoder27_w_lg_zero1000w(0) AND wire_altpriority_encoder27_q(0);
wire_altpriority_encoder27_w_lg_zero1002w(0) <= wire_altpriority_encoder27_zero AND wire_altpriority_encoder28_q(0);
wire_altpriority_encoder27_w_lg_zero1000w(0) <= NOT wire_altpriority_encoder27_zero;
wire_altpriority_encoder27_w_lg_w_lg_zero1002w1003w(0) <= wire_altpriority_encoder27_w_lg_zero1002w(0) OR wire_altpriority_encoder27_w_lg_w_lg_zero1000w1001w(0);
altpriority_encoder27 : add_flt_stratix5_speed_altpriority_encoder_nh8
PORT MAP (
data => data(1 DOWNTO 0),
q => wire_altpriority_encoder27_q,
zero => wire_altpriority_encoder27_zero
);
altpriority_encoder28 : add_flt_stratix5_speed_altpriority_encoder_nh8
PORT MAP (
data => data(3 DOWNTO 2),
q => wire_altpriority_encoder28_q,
zero => wire_altpriority_encoder28_zero
);
END RTL; --add_flt_stratix5_speed_altpriority_encoder_qh8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_speed_altpriority_encoder_2h9 IS
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END add_flt_stratix5_speed_altpriority_encoder_2h9;
ARCHITECTURE RTL OF add_flt_stratix5_speed_altpriority_encoder_2h9 IS
SIGNAL wire_altpriority_encoder25_w_lg_w_lg_zero990w991w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder25_w_lg_zero992w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder25_w_lg_zero990w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder25_w_lg_w_lg_zero992w993w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder25_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder25_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder26_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder26_zero : STD_LOGIC;
COMPONENT add_flt_stratix5_speed_altpriority_encoder_qh8
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder25_zero & wire_altpriority_encoder25_w_lg_w_lg_zero992w993w);
zero <= (wire_altpriority_encoder25_zero AND wire_altpriority_encoder26_zero);
loop65 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder25_w_lg_w_lg_zero990w991w(i) <= wire_altpriority_encoder25_w_lg_zero990w(0) AND wire_altpriority_encoder25_q(i);
END GENERATE loop65;
loop66 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder25_w_lg_zero992w(i) <= wire_altpriority_encoder25_zero AND wire_altpriority_encoder26_q(i);
END GENERATE loop66;
wire_altpriority_encoder25_w_lg_zero990w(0) <= NOT wire_altpriority_encoder25_zero;
loop67 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder25_w_lg_w_lg_zero992w993w(i) <= wire_altpriority_encoder25_w_lg_zero992w(i) OR wire_altpriority_encoder25_w_lg_w_lg_zero990w991w(i);
END GENERATE loop67;
altpriority_encoder25 : add_flt_stratix5_speed_altpriority_encoder_qh8
PORT MAP (
data => data(3 DOWNTO 0),
q => wire_altpriority_encoder25_q,
zero => wire_altpriority_encoder25_zero
);
altpriority_encoder26 : add_flt_stratix5_speed_altpriority_encoder_qh8
PORT MAP (
data => data(7 DOWNTO 4),
q => wire_altpriority_encoder26_q,
zero => wire_altpriority_encoder26_zero
);
END RTL; --add_flt_stratix5_speed_altpriority_encoder_2h9
--synthesis_resources = reg 5
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_speed_altpriority_encoder_d6b IS
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
zero : OUT STD_LOGIC
);
END add_flt_stratix5_speed_altpriority_encoder_d6b;
ARCHITECTURE RTL OF add_flt_stratix5_speed_altpriority_encoder_d6b IS
SIGNAL wire_altpriority_encoder23_w_lg_w_lg_zero975w976w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder23_w_lg_zero977w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder23_w_lg_zero975w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder23_w_lg_w_lg_zero977w978w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder23_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder23_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder24_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder24_zero : STD_LOGIC;
SIGNAL pipeline_q_dffe : STD_LOGIC_VECTOR(3 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL pipeline_zero_n_dffe : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_pipeline_zero_n_dffe_w_lg_q987w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_w_lg_tmp_q_wire984w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_w_lg_tmp_zero_wire985w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL tmp_q_wire : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL tmp_zero_wire : STD_LOGIC;
COMPONENT add_flt_stratix5_speed_altpriority_encoder_2h9
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
loop68 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder21_w_lg_tmp_q_wire984w(i) <= NOT tmp_q_wire(i);
END GENERATE loop68;
wire_altpriority_encoder21_w_lg_tmp_zero_wire985w(0) <= NOT tmp_zero_wire;
q <= (NOT pipeline_q_dffe);
tmp_q_wire <= ( wire_altpriority_encoder23_zero & wire_altpriority_encoder23_w_lg_w_lg_zero977w978w);
tmp_zero_wire <= (wire_altpriority_encoder23_zero AND wire_altpriority_encoder24_zero);
zero <= wire_pipeline_zero_n_dffe_w_lg_q987w(0);
loop69 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder23_w_lg_w_lg_zero975w976w(i) <= wire_altpriority_encoder23_w_lg_zero975w(0) AND wire_altpriority_encoder23_q(i);
END GENERATE loop69;
loop70 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder23_w_lg_zero977w(i) <= wire_altpriority_encoder23_zero AND wire_altpriority_encoder24_q(i);
END GENERATE loop70;
wire_altpriority_encoder23_w_lg_zero975w(0) <= NOT wire_altpriority_encoder23_zero;
loop71 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder23_w_lg_w_lg_zero977w978w(i) <= wire_altpriority_encoder23_w_lg_zero977w(i) OR wire_altpriority_encoder23_w_lg_w_lg_zero975w976w(i);
END GENERATE loop71;
altpriority_encoder23 : add_flt_stratix5_speed_altpriority_encoder_2h9
PORT MAP (
data => data(7 DOWNTO 0),
q => wire_altpriority_encoder23_q,
zero => wire_altpriority_encoder23_zero
);
altpriority_encoder24 : add_flt_stratix5_speed_altpriority_encoder_2h9
PORT MAP (
data => data(15 DOWNTO 8),
q => wire_altpriority_encoder24_q,
zero => wire_altpriority_encoder24_zero
);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN pipeline_q_dffe <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN pipeline_q_dffe <= wire_altpriority_encoder21_w_lg_tmp_q_wire984w;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN pipeline_zero_n_dffe <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN pipeline_zero_n_dffe <= wire_altpriority_encoder21_w_lg_tmp_zero_wire985w(0);
END IF;
END IF;
END PROCESS;
wire_pipeline_zero_n_dffe_w_lg_q987w(0) <= NOT pipeline_zero_n_dffe;
END RTL; --add_flt_stratix5_speed_altpriority_encoder_d6b
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" PIPELINE=1 WIDTH=16 WIDTHAD=4 aclr clk_en clock data q
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" PIPELINE=0 WIDTH=8 WIDTHAD=3 data q
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=4 WIDTHAD=2 data q
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=2 WIDTHAD=1 data q
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_speed_altpriority_encoder_n28 IS
PORT
(
data : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END add_flt_stratix5_speed_altpriority_encoder_n28;
ARCHITECTURE RTL OF add_flt_stratix5_speed_altpriority_encoder_n28 IS
SIGNAL wire_altpriority_encoder34_w_lg_w_data_range1045w1047w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder34_w_data_range1045w : STD_LOGIC_VECTOR (0 DOWNTO 0);
BEGIN
wire_altpriority_encoder34_w_lg_w_data_range1045w1047w(0) <= NOT wire_altpriority_encoder34_w_data_range1045w(0);
q <= ( wire_altpriority_encoder34_w_lg_w_data_range1045w1047w);
wire_altpriority_encoder34_w_data_range1045w(0) <= data(0);
END RTL; --add_flt_stratix5_speed_altpriority_encoder_n28
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_speed_altpriority_encoder_q28 IS
PORT
(
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END add_flt_stratix5_speed_altpriority_encoder_q28;
ARCHITECTURE RTL OF add_flt_stratix5_speed_altpriority_encoder_q28 IS
SIGNAL wire_altpriority_encoder33_w_lg_w_lg_zero1038w1039w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder33_w_lg_zero1040w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder33_w_lg_zero1038w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder33_w_lg_w_lg_zero1040w1041w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder33_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder33_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder34_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT add_flt_stratix5_speed_altpriority_encoder_nh8
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT add_flt_stratix5_speed_altpriority_encoder_n28
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder33_zero & wire_altpriority_encoder33_w_lg_w_lg_zero1040w1041w);
wire_altpriority_encoder33_w_lg_w_lg_zero1038w1039w(0) <= wire_altpriority_encoder33_w_lg_zero1038w(0) AND wire_altpriority_encoder33_q(0);
wire_altpriority_encoder33_w_lg_zero1040w(0) <= wire_altpriority_encoder33_zero AND wire_altpriority_encoder34_q(0);
wire_altpriority_encoder33_w_lg_zero1038w(0) <= NOT wire_altpriority_encoder33_zero;
wire_altpriority_encoder33_w_lg_w_lg_zero1040w1041w(0) <= wire_altpriority_encoder33_w_lg_zero1040w(0) OR wire_altpriority_encoder33_w_lg_w_lg_zero1038w1039w(0);
altpriority_encoder33 : add_flt_stratix5_speed_altpriority_encoder_nh8
PORT MAP (
data => data(1 DOWNTO 0),
q => wire_altpriority_encoder33_q,
zero => wire_altpriority_encoder33_zero
);
altpriority_encoder34 : add_flt_stratix5_speed_altpriority_encoder_n28
PORT MAP (
data => data(3 DOWNTO 2),
q => wire_altpriority_encoder34_q
);
END RTL; --add_flt_stratix5_speed_altpriority_encoder_q28
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_speed_altpriority_encoder_229 IS
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
);
END add_flt_stratix5_speed_altpriority_encoder_229;
ARCHITECTURE RTL OF add_flt_stratix5_speed_altpriority_encoder_229 IS
SIGNAL wire_altpriority_encoder31_w_lg_w_lg_zero1029w1030w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder31_w_lg_zero1031w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder31_w_lg_zero1029w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder31_w_lg_w_lg_zero1031w1032w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder31_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder31_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder32_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
COMPONENT add_flt_stratix5_speed_altpriority_encoder_qh8
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT add_flt_stratix5_speed_altpriority_encoder_q28
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder31_zero & wire_altpriority_encoder31_w_lg_w_lg_zero1031w1032w);
loop72 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder31_w_lg_w_lg_zero1029w1030w(i) <= wire_altpriority_encoder31_w_lg_zero1029w(0) AND wire_altpriority_encoder31_q(i);
END GENERATE loop72;
loop73 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder31_w_lg_zero1031w(i) <= wire_altpriority_encoder31_zero AND wire_altpriority_encoder32_q(i);
END GENERATE loop73;
wire_altpriority_encoder31_w_lg_zero1029w(0) <= NOT wire_altpriority_encoder31_zero;
loop74 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder31_w_lg_w_lg_zero1031w1032w(i) <= wire_altpriority_encoder31_w_lg_zero1031w(i) OR wire_altpriority_encoder31_w_lg_w_lg_zero1029w1030w(i);
END GENERATE loop74;
altpriority_encoder31 : add_flt_stratix5_speed_altpriority_encoder_qh8
PORT MAP (
data => data(3 DOWNTO 0),
q => wire_altpriority_encoder31_q,
zero => wire_altpriority_encoder31_zero
);
altpriority_encoder32 : add_flt_stratix5_speed_altpriority_encoder_q28
PORT MAP (
data => data(7 DOWNTO 4),
q => wire_altpriority_encoder32_q
);
END RTL; --add_flt_stratix5_speed_altpriority_encoder_229
--synthesis_resources = reg 4
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_speed_altpriority_encoder_ena IS
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END add_flt_stratix5_speed_altpriority_encoder_ena;
ARCHITECTURE RTL OF add_flt_stratix5_speed_altpriority_encoder_ena IS
SIGNAL wire_altpriority_encoder29_w_lg_w_lg_zero1017w1018w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder29_w_lg_zero1019w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder29_w_lg_zero1017w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder29_w_lg_w_lg_zero1019w1020w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder29_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder29_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder30_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL pipeline_q_dffe : STD_LOGIC_VECTOR(3 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_altpriority_encoder22_w_lg_tmp_q_wire1025w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL tmp_q_wire : STD_LOGIC_VECTOR (3 DOWNTO 0);
COMPONENT add_flt_stratix5_speed_altpriority_encoder_2h9
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT add_flt_stratix5_speed_altpriority_encoder_229
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
);
END COMPONENT;
BEGIN
loop75 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder22_w_lg_tmp_q_wire1025w(i) <= NOT tmp_q_wire(i);
END GENERATE loop75;
q <= (NOT pipeline_q_dffe);
tmp_q_wire <= ( wire_altpriority_encoder29_zero & wire_altpriority_encoder29_w_lg_w_lg_zero1019w1020w);
loop76 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder29_w_lg_w_lg_zero1017w1018w(i) <= wire_altpriority_encoder29_w_lg_zero1017w(0) AND wire_altpriority_encoder29_q(i);
END GENERATE loop76;
loop77 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder29_w_lg_zero1019w(i) <= wire_altpriority_encoder29_zero AND wire_altpriority_encoder30_q(i);
END GENERATE loop77;
wire_altpriority_encoder29_w_lg_zero1017w(0) <= NOT wire_altpriority_encoder29_zero;
loop78 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder29_w_lg_w_lg_zero1019w1020w(i) <= wire_altpriority_encoder29_w_lg_zero1019w(i) OR wire_altpriority_encoder29_w_lg_w_lg_zero1017w1018w(i);
END GENERATE loop78;
altpriority_encoder29 : add_flt_stratix5_speed_altpriority_encoder_2h9
PORT MAP (
data => data(7 DOWNTO 0),
q => wire_altpriority_encoder29_q,
zero => wire_altpriority_encoder29_zero
);
altpriority_encoder30 : add_flt_stratix5_speed_altpriority_encoder_229
PORT MAP (
data => data(15 DOWNTO 8),
q => wire_altpriority_encoder30_q
);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN pipeline_q_dffe <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN pipeline_q_dffe <= wire_altpriority_encoder22_w_lg_tmp_q_wire1025w;
END IF;
END IF;
END PROCESS;
END RTL; --add_flt_stratix5_speed_altpriority_encoder_ena
--synthesis_resources = reg 14
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_speed_altpriority_encoder_dna IS
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END add_flt_stratix5_speed_altpriority_encoder_dna;
ARCHITECTURE RTL OF add_flt_stratix5_speed_altpriority_encoder_dna IS
SIGNAL wire_altpriority_encoder21_w_lg_w_lg_zero963w964w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_w_lg_zero965w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_w_lg_zero963w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_w_lg_w_lg_zero965w966w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_q : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder22_q : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL pipeline_q_dffe : STD_LOGIC_VECTOR(4 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_trailing_zeros_cnt_w_lg_tmp_q_wire971w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL tmp_q_wire : STD_LOGIC_VECTOR (4 DOWNTO 0);
COMPONENT add_flt_stratix5_speed_altpriority_encoder_d6b
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT add_flt_stratix5_speed_altpriority_encoder_ena
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
BEGIN
loop79 : FOR i IN 0 TO 4 GENERATE
wire_trailing_zeros_cnt_w_lg_tmp_q_wire971w(i) <= NOT tmp_q_wire(i);
END GENERATE loop79;
q <= (NOT pipeline_q_dffe);
tmp_q_wire <= ( wire_altpriority_encoder21_zero & wire_altpriority_encoder21_w_lg_w_lg_zero965w966w);
loop80 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder21_w_lg_w_lg_zero963w964w(i) <= wire_altpriority_encoder21_w_lg_zero963w(0) AND wire_altpriority_encoder21_q(i);
END GENERATE loop80;
loop81 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder21_w_lg_zero965w(i) <= wire_altpriority_encoder21_zero AND wire_altpriority_encoder22_q(i);
END GENERATE loop81;
wire_altpriority_encoder21_w_lg_zero963w(0) <= NOT wire_altpriority_encoder21_zero;
loop82 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder21_w_lg_w_lg_zero965w966w(i) <= wire_altpriority_encoder21_w_lg_zero965w(i) OR wire_altpriority_encoder21_w_lg_w_lg_zero963w964w(i);
END GENERATE loop82;
altpriority_encoder21 : add_flt_stratix5_speed_altpriority_encoder_d6b
PORT MAP (
aclr => aclr,
clk_en => clk_en,
clock => clock,
data => data(15 DOWNTO 0),
q => wire_altpriority_encoder21_q,
zero => wire_altpriority_encoder21_zero
);
altpriority_encoder22 : add_flt_stratix5_speed_altpriority_encoder_ena
PORT MAP (
aclr => aclr,
clk_en => clk_en,
clock => clock,
data => data(31 DOWNTO 16),
q => wire_altpriority_encoder22_q
);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN pipeline_q_dffe <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN pipeline_q_dffe <= wire_trailing_zeros_cnt_w_lg_tmp_q_wire971w;
END IF;
END IF;
END PROCESS;
END RTL; --add_flt_stratix5_speed_altpriority_encoder_dna
LIBRARY lpm;
USE lpm.all;
--synthesis_resources = lpm_add_sub 14 lpm_compare 1 reg 816
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_speed_altfp_add_sub_jkj IS
PORT
(
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END add_flt_stratix5_speed_altfp_add_sub_jkj;
ARCHITECTURE RTL OF add_flt_stratix5_speed_altfp_add_sub_jkj IS
SIGNAL wire_lbarrel_shift_result : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_data : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_result : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_leading_zeroes_cnt_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL wire_leading_zeroes_cnt_q : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_trailing_zeros_cnt_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL wire_trailing_zeros_cnt_q : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe12 : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_dataa_exp_dffe13 : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_dataa_exp_dffe14 : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_dataa_exp_dffe15 : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_dataa_man_dffe12 : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_dataa_man_dffe13 : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_dataa_man_dffe14 : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_dataa_man_dffe15 : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_dataa_sign_dffe12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL aligned_dataa_sign_dffe13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL aligned_dataa_sign_dffe14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL aligned_dataa_sign_dffe15 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL aligned_datab_exp_dffe12 : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_datab_exp_dffe13 : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_datab_exp_dffe14 : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_datab_exp_dffe15 : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_datab_man_dffe12 : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_datab_man_dffe13 : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_datab_man_dffe14 : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_datab_man_dffe15 : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_datab_sign_dffe12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL aligned_datab_sign_dffe13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL aligned_datab_sign_dffe14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL aligned_datab_sign_dffe15 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL both_inputs_are_infinite_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL data_exp_dffe1 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL dataa_man_dffe1 : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL dataa_sign_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL datab_man_dffe1 : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL datab_sign_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL denormal_res_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL denormal_res_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL denormal_res_dffe41 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL exp_adj_dffe21 : STD_LOGIC_VECTOR(1 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_adj_dffe23 : STD_LOGIC_VECTOR(1 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_amb_mux_dffe13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL exp_amb_mux_dffe14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL exp_amb_mux_dffe15 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL exp_intermediate_res_dffe41 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_out_dffe5 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe2 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe21 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe23 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe27 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe3 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe4 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe27 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe41 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_res_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_res_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_res_dffe41 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe27 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe41 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_dataa_infinite_dffe12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_dataa_infinite_dffe13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_dataa_infinite_dffe14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_dataa_infinite_dffe15 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_dataa_nan_dffe12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_datab_infinite_dffe12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_datab_infinite_dffe13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_datab_infinite_dffe14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_datab_infinite_dffe15 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_datab_nan_dffe12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe27 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe41 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe15 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe27 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe41 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_add_sub_res_mag_dffe21 : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_add_sub_res_mag_dffe23 : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_add_sub_res_mag_dffe27 : STD_LOGIC_VECTOR(27 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_add_sub_res_sign_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_add_sub_res_sign_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_add_sub_res_sign_dffe27 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_dffe31 : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_leading_zeros_dffe31 : STD_LOGIC_VECTOR(4 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_out_dffe5 : STD_LOGIC_VECTOR(22 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_res_dffe4 : STD_LOGIC_VECTOR(22 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_res_is_not_zero_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_res_is_not_zero_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_res_is_not_zero_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_res_is_not_zero_dffe41 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_res_not_zero_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_res_rounding_add_sub_result_reg : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_smaller_dffe13 : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL need_complement_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL round_bit_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL round_bit_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL round_bit_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL round_bit_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL rounded_res_infinity_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL rshift_distance_dffe13 : STD_LOGIC_VECTOR(4 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL rshift_distance_dffe14 : STD_LOGIC_VECTOR(4 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL rshift_distance_dffe15 : STD_LOGIC_VECTOR(4 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL sign_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_out_dffe5 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_res_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_res_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_res_dffe41 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe27 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL zero_man_sign_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL zero_man_sign_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL zero_man_sign_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL zero_man_sign_dffe27 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_add_sub1_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_add_sub2_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_add_sub3_result : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_add_sub4_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_add_sub5_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_add_sub6_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_man_2comp_res_lower_w_lg_w_lg_cout367w368w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_2comp_res_lower_w_lg_cout366w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_2comp_res_lower_w_lg_cout367w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_2comp_res_lower_w_lg_w_lg_w_lg_cout367w368w369w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_2comp_res_lower_cout : STD_LOGIC;
SIGNAL wire_man_2comp_res_lower_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_gnd : STD_LOGIC;
SIGNAL wire_man_2comp_res_upper0_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_vcc : STD_LOGIC;
SIGNAL wire_man_2comp_res_upper1_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_lower_w_lg_w_lg_cout354w355w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_lower_w_lg_cout353w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_lower_w_lg_cout354w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_add_sub_lower_w_lg_w_lg_w_lg_cout354w355w356w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_lower_cout : STD_LOGIC;
SIGNAL wire_man_add_sub_lower_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_upper0_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_upper1_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_lower_w_lg_w_lg_cout580w581w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_lower_w_lg_cout579w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_lower_w_lg_cout580w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_lower_w_lg_w_lg_w_lg_cout580w581w582w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_lower_cout : STD_LOGIC;
SIGNAL wire_man_res_rounding_add_sub_lower_result : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_upper1_result : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_trailing_zeros_limit_comparator_agb : STD_LOGIC;
SIGNAL wire_w248w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w267w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w397w407w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_force_zero_w634w635w636w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_force_zero_w634w635w645w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_denormal_result_w558w559w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w324w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w331w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w317w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_amb_mux_w276w279w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_amb_mux_w276w277w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_infinity_w629w639w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_infinity_w629w648w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_infinity_w629w654w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_nan_w630w642w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_nan_w630w651w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w243w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w234w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_dataa_infinite_dffe11_wo246w247w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w262w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w253w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_datab_infinite_dffe11_wo265w266w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_datab_infinite_dffe15_wo337w338w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_man_res_not_zero_dffe26_wo503w504w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w293w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_w397w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w383w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_w412w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_man_add_sub_w_range372w375w378w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL wire_w587w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_zero_w634w637w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_zero_w634w646w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_dffe15_wo330w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_dffe15_wo323w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_dffe15_wo314w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_w280w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_w274w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_force_infinity_w640w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_force_infinity_w649w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_force_nan_w643w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_force_nan_w652w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_need_complement_dffe22_wo376w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range17w23w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range27w33w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range37w43w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range47w53w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range57w63w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range67w73w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range77w83w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range20w25w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range30w35w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range40w45w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range50w55w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range60w65w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range70w75w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range80w85w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_a_all_one_w_range84w220w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_b_all_one_w_range86w226w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_diff_abs_exceed_max_w_range290w294w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range540w542w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range543w544w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range545w546w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range547w548w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range549w550w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range551w552w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range553w554w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range555w561w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range601w604w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range605w607w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range608w610w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range611w613w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range614w616w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range617w619w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range620w622w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w391w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w384w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w414w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_w_range372w379w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_rounding_add_sub_w_range585w589w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_zero_w634w635w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_add_sub_dffe25_wo491w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_add_sub_w2342w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_denormal_result_w558w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_dffe15_wo316w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_w276w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_force_infinity_w629w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_force_nan_w630w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_force_zero_w628w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_dataa_denormal_dffe11_wo233w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_dataa_infinite_dffe11_wo246w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_dataa_zero_dffe11_wo245w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_datab_denormal_dffe11_wo252w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_datab_infinite_dffe11_wo265w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_datab_infinite_dffe15_wo337w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_datab_zero_dffe11_wo264w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_man_res_is_not_zero_dffe4_wo627w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_man_res_not_zero_dffe26_wo503w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_need_complement_dffe22_wo373w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_sticky_bit_dffe1_wo343w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_adjustment2_add_sub_w_range511w560w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_diff_abs_exceed_max_w_range290w292w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_a_not_zero_w_range215w219w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range387w390w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_w_range372w375w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_b_not_zero_w_range218w225w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_rounding_add_sub_w_range585w586w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_force_zero_w634w637w638w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_force_zero_w634w646w647w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_infinity_w640w641w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_infinity_w649w650w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_force_zero_w634w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_sticky_bit_dffe27_wo402w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range141w142w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range147w148w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range153w154w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range159w160w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range165w166w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range171w172w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range177w178w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range183w184w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range189w190w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range195w196w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range87w88w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range201w202w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range207w208w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range213w214w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range17w18w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range27w28w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range37w38w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range47w48w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range57w58w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range67w68w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range93w94w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range77w78w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range99w100w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range105w106w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range111w112w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range117w118w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range123w124w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range129w130w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range135w136w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range144w145w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range150w151w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range156w157w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range162w163w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range168w169w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range174w175w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range180w181w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range186w187w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range192w193w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range198w199w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range90w91w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range204w205w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range210w211w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range216w217w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range20w21w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range30w31w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range40w41w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range50w51w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range60w61w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range70w71w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range96w97w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range80w81w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range102w103w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range108w109w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range114w115w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range120w121w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range126w127w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range132w133w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range138w139w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_diff_abs_exceed_max_w_range283w286w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_diff_abs_exceed_max_w_range287w289w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range516w519w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range520w522w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range523w525w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range526w528w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range529w531w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range532w534w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range535w537w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range538w539w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range417w420w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range448w450w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range451w453w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range454w456w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range457w459w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range460w462w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range463w465w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range466w468w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range469w471w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range472w474w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range475w477w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range421w423w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range478w480w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range481w483w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range484w486w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range487w489w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range424w426w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range427w429w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range430w432w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range433w435w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range436w438w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range439w441w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range442w444w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range445w447w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL aclr : STD_LOGIC;
SIGNAL add_sub_dffe25_wi : STD_LOGIC;
SIGNAL add_sub_dffe25_wo : STD_LOGIC;
SIGNAL add_sub_w2 : STD_LOGIC;
SIGNAL adder_upper_w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe12_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe12_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe13_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe13_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe14_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe14_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe15_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe15_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe12_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe12_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe13_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe13_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe14_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe14_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe15_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe15_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe15_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL aligned_dataa_sign_dffe12_wi : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe12_wo : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe13_wi : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe13_wo : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe14_wi : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe14_wo : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe15_wi : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe15_wo : STD_LOGIC;
SIGNAL aligned_dataa_sign_w : STD_LOGIC;
SIGNAL aligned_datab_exp_dffe12_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe12_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe13_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe13_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe14_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe14_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe15_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe15_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_man_dffe12_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe12_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe13_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe13_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe14_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe14_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe15_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL aligned_datab_man_dffe15_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe15_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL aligned_datab_sign_dffe12_wi : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe12_wo : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe13_wi : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe13_wo : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe14_wi : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe14_wo : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe15_wi : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe15_wo : STD_LOGIC;
SIGNAL aligned_datab_sign_w : STD_LOGIC;
SIGNAL borrow_w : STD_LOGIC;
SIGNAL both_inputs_are_infinite_dffe1_wi : STD_LOGIC;
SIGNAL both_inputs_are_infinite_dffe1_wo : STD_LOGIC;
SIGNAL both_inputs_are_infinite_dffe25_wi : STD_LOGIC;
SIGNAL both_inputs_are_infinite_dffe25_wo : STD_LOGIC;
SIGNAL data_exp_dffe1_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL data_exp_dffe1_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL dataa_dffe11_wi : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL dataa_dffe11_wo : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL dataa_man_dffe1_wi : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL dataa_man_dffe1_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL dataa_sign_dffe1_wi : STD_LOGIC;
SIGNAL dataa_sign_dffe1_wo : STD_LOGIC;
SIGNAL dataa_sign_dffe25_wi : STD_LOGIC;
SIGNAL dataa_sign_dffe25_wo : STD_LOGIC;
SIGNAL datab_dffe11_wi : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL datab_dffe11_wo : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL datab_man_dffe1_wi : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL datab_man_dffe1_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL datab_sign_dffe1_wi : STD_LOGIC;
SIGNAL datab_sign_dffe1_wo : STD_LOGIC;
SIGNAL denormal_flag_w : STD_LOGIC;
SIGNAL denormal_res_dffe32_wi : STD_LOGIC;
SIGNAL denormal_res_dffe32_wo : STD_LOGIC;
SIGNAL denormal_res_dffe33_wi : STD_LOGIC;
SIGNAL denormal_res_dffe33_wo : STD_LOGIC;
SIGNAL denormal_res_dffe3_wi : STD_LOGIC;
SIGNAL denormal_res_dffe3_wo : STD_LOGIC;
SIGNAL denormal_res_dffe41_wi : STD_LOGIC;
SIGNAL denormal_res_dffe41_wo : STD_LOGIC;
SIGNAL denormal_res_dffe42_wi : STD_LOGIC;
SIGNAL denormal_res_dffe42_wo : STD_LOGIC;
SIGNAL denormal_res_dffe4_wi : STD_LOGIC;
SIGNAL denormal_res_dffe4_wo : STD_LOGIC;
SIGNAL denormal_result_w : STD_LOGIC;
SIGNAL exp_a_all_one_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_a_not_zero_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_adj_0pads : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL exp_adj_dffe21_wi : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adj_dffe21_wo : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adj_dffe23_wi : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adj_dffe23_wo : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adj_dffe26_wi : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adj_dffe26_wo : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adjust_by_add1 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adjust_by_add2 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adjustment2_add_sub_dataa_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adjustment2_add_sub_datab_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adjustment2_add_sub_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adjustment_add_sub_dataa_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adjustment_add_sub_datab_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adjustment_add_sub_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_all_ones_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_all_zeros_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_amb_mux_dffe13_wi : STD_LOGIC;
SIGNAL exp_amb_mux_dffe13_wo : STD_LOGIC;
SIGNAL exp_amb_mux_dffe14_wi : STD_LOGIC;
SIGNAL exp_amb_mux_dffe14_wo : STD_LOGIC;
SIGNAL exp_amb_mux_dffe15_wi : STD_LOGIC;
SIGNAL exp_amb_mux_dffe15_wo : STD_LOGIC;
SIGNAL exp_amb_mux_w : STD_LOGIC;
SIGNAL exp_amb_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_b_all_one_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_b_not_zero_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_bma_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_diff_abs_exceed_max_w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL exp_diff_abs_max_w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL exp_diff_abs_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_intermediate_res_dffe41_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_intermediate_res_dffe41_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_intermediate_res_dffe42_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_intermediate_res_dffe42_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_intermediate_res_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_out_dffe5_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_out_dffe5_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe21_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe21_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe22_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe22_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe23_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe23_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe25_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe25_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe26_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe26_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe27_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe27_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe2_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe2_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe32_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe32_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe33_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe33_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe3_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe3_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe4_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe4_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_max_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_not_zero_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_res_rounding_adder_dataa_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_res_rounding_adder_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_rounded_res_infinity_w : STD_LOGIC;
SIGNAL exp_rounded_res_max_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_rounded_res_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_rounding_adjustment_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_value : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL force_infinity_w : STD_LOGIC;
SIGNAL force_nan_w : STD_LOGIC;
SIGNAL force_zero_w : STD_LOGIC;
SIGNAL guard_bit_dffe3_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe1_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe1_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe21_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe21_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe22_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe22_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe23_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe23_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe25_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe25_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe26_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe26_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe27_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe27_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe2_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe2_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe31_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe31_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe32_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe32_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe33_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe33_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe3_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe3_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe41_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe41_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe42_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe42_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe4_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe4_wo : STD_LOGIC;
SIGNAL infinite_res_dff32_wi : STD_LOGIC;
SIGNAL infinite_res_dff32_wo : STD_LOGIC;
SIGNAL infinite_res_dff33_wi : STD_LOGIC;
SIGNAL infinite_res_dff33_wo : STD_LOGIC;
SIGNAL infinite_res_dffe3_wi : STD_LOGIC;
SIGNAL infinite_res_dffe3_wo : STD_LOGIC;
SIGNAL infinite_res_dffe41_wi : STD_LOGIC;
SIGNAL infinite_res_dffe41_wo : STD_LOGIC;
SIGNAL infinite_res_dffe42_wi : STD_LOGIC;
SIGNAL infinite_res_dffe42_wo : STD_LOGIC;
SIGNAL infinite_res_dffe4_wi : STD_LOGIC;
SIGNAL infinite_res_dffe4_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe21_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe21_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe22_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe22_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe23_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe23_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe26_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe26_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe27_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe27_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe2_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe2_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe31_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe31_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe32_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe32_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe33_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe33_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe3_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe3_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe41_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe41_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe42_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe42_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe4_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe4_wo : STD_LOGIC;
SIGNAL input_dataa_denormal_dffe11_wi : STD_LOGIC;
SIGNAL input_dataa_denormal_dffe11_wo : STD_LOGIC;
SIGNAL input_dataa_denormal_w : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe11_wi : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe11_wo : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe12_wi : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe12_wo : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe13_wi : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe13_wo : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe14_wi : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe14_wo : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe15_wi : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe15_wo : STD_LOGIC;
SIGNAL input_dataa_infinite_w : STD_LOGIC;
SIGNAL input_dataa_nan_dffe11_wi : STD_LOGIC;
SIGNAL input_dataa_nan_dffe11_wo : STD_LOGIC;
SIGNAL input_dataa_nan_dffe12_wi : STD_LOGIC;
SIGNAL input_dataa_nan_dffe12_wo : STD_LOGIC;
SIGNAL input_dataa_nan_w : STD_LOGIC;
SIGNAL input_dataa_zero_dffe11_wi : STD_LOGIC;
SIGNAL input_dataa_zero_dffe11_wo : STD_LOGIC;
SIGNAL input_dataa_zero_w : STD_LOGIC;
SIGNAL input_datab_denormal_dffe11_wi : STD_LOGIC;
SIGNAL input_datab_denormal_dffe11_wo : STD_LOGIC;
SIGNAL input_datab_denormal_w : STD_LOGIC;
SIGNAL input_datab_infinite_dffe11_wi : STD_LOGIC;
SIGNAL input_datab_infinite_dffe11_wo : STD_LOGIC;
SIGNAL input_datab_infinite_dffe12_wi : STD_LOGIC;
SIGNAL input_datab_infinite_dffe12_wo : STD_LOGIC;
SIGNAL input_datab_infinite_dffe13_wi : STD_LOGIC;
SIGNAL input_datab_infinite_dffe13_wo : STD_LOGIC;
SIGNAL input_datab_infinite_dffe14_wi : STD_LOGIC;
SIGNAL input_datab_infinite_dffe14_wo : STD_LOGIC;
SIGNAL input_datab_infinite_dffe15_wi : STD_LOGIC;
SIGNAL input_datab_infinite_dffe15_wo : STD_LOGIC;
SIGNAL input_datab_infinite_w : STD_LOGIC;
SIGNAL input_datab_nan_dffe11_wi : STD_LOGIC;
SIGNAL input_datab_nan_dffe11_wo : STD_LOGIC;
SIGNAL input_datab_nan_dffe12_wi : STD_LOGIC;
SIGNAL input_datab_nan_dffe12_wo : STD_LOGIC;
SIGNAL input_datab_nan_w : STD_LOGIC;
SIGNAL input_datab_zero_dffe11_wi : STD_LOGIC;
SIGNAL input_datab_zero_dffe11_wo : STD_LOGIC;
SIGNAL input_datab_zero_w : STD_LOGIC;
SIGNAL input_is_infinite_dffe1_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe1_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe21_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe21_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe22_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe22_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe23_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe23_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe25_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe25_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe26_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe26_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe27_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe27_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe2_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe2_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe31_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe31_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe32_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe32_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe33_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe33_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe3_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe3_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe41_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe41_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe42_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe42_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe4_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe4_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe13_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe13_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe14_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe14_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe15_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe15_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe1_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe1_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe21_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe21_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe22_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe22_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe23_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe23_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe25_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe25_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe26_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe26_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe27_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe27_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe2_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe2_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe31_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe31_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe32_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe32_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe33_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe33_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe3_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe3_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe41_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe41_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe42_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe42_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe4_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe4_wo : STD_LOGIC;
SIGNAL man_2comp_res_dataa_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_2comp_res_datab_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_2comp_res_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_a_not_zero_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_add_sub_dataa_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_add_sub_datab_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe21_wi : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe21_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe23_wi : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe23_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe26_wi : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe26_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe27_wi : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe27_wo : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_add_sub_res_mag_w2 : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_add_sub_res_sign_dffe21_wo : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe23_wi : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe23_wo : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe26_wi : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe26_wo : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe27_wi : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe27_wo : STD_LOGIC;
SIGNAL man_add_sub_res_sign_w2 : STD_LOGIC;
SIGNAL man_add_sub_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_all_zeros_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_b_not_zero_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_dffe31_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_intermediate_res_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_leading_zeros_cnt_w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL man_leading_zeros_dffe31_wi : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL man_leading_zeros_dffe31_wo : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL man_nan_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_out_dffe5_wi : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_out_dffe5_wo : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_res_dffe4_wi : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_res_dffe4_wo : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_res_is_not_zero_dffe31_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe31_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe32_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe32_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe33_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe33_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe3_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe3_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe41_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe41_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe42_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe42_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe4_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe4_wo : STD_LOGIC;
SIGNAL man_res_mag_w2 : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_res_not_zero_dffe23_wi : STD_LOGIC;
SIGNAL man_res_not_zero_dffe23_wo : STD_LOGIC;
SIGNAL man_res_not_zero_dffe26_wi : STD_LOGIC;
SIGNAL man_res_not_zero_dffe26_wo : STD_LOGIC;
SIGNAL man_res_not_zero_w2 : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL man_res_rounding_add_sub_datab_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_res_rounding_add_sub_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_res_w3 : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL man_rounded_res_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_rounding_add_value_w : STD_LOGIC;
SIGNAL man_smaller_dffe13_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL man_smaller_dffe13_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL man_smaller_w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL need_complement_dffe22_wi : STD_LOGIC;
SIGNAL need_complement_dffe22_wo : STD_LOGIC;
SIGNAL need_complement_dffe2_wi : STD_LOGIC;
SIGNAL need_complement_dffe2_wo : STD_LOGIC;
SIGNAL pos_sign_bit_ext : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL priority_encoder_1pads_w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL round_bit_dffe21_wi : STD_LOGIC;
SIGNAL round_bit_dffe21_wo : STD_LOGIC;
SIGNAL round_bit_dffe23_wi : STD_LOGIC;
SIGNAL round_bit_dffe23_wo : STD_LOGIC;
SIGNAL round_bit_dffe26_wi : STD_LOGIC;
SIGNAL round_bit_dffe26_wo : STD_LOGIC;
SIGNAL round_bit_dffe31_wi : STD_LOGIC;
SIGNAL round_bit_dffe31_wo : STD_LOGIC;
SIGNAL round_bit_dffe32_wi : STD_LOGIC;
SIGNAL round_bit_dffe32_wo : STD_LOGIC;
SIGNAL round_bit_dffe33_wi : STD_LOGIC;
SIGNAL round_bit_dffe33_wo : STD_LOGIC;
SIGNAL round_bit_dffe3_wi : STD_LOGIC;
SIGNAL round_bit_dffe3_wo : STD_LOGIC;
SIGNAL round_bit_w : STD_LOGIC;
SIGNAL rounded_res_infinity_dffe4_wi : STD_LOGIC;
SIGNAL rounded_res_infinity_dffe4_wo : STD_LOGIC;
SIGNAL rshift_distance_dffe13_wi : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_dffe13_wo : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_dffe14_wi : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_dffe14_wo : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_dffe15_wi : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_dffe15_wo : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sign_dffe31_wi : STD_LOGIC;
SIGNAL sign_dffe31_wo : STD_LOGIC;
SIGNAL sign_dffe32_wi : STD_LOGIC;
SIGNAL sign_dffe32_wo : STD_LOGIC;
SIGNAL sign_dffe33_wi : STD_LOGIC;
SIGNAL sign_dffe33_wo : STD_LOGIC;
SIGNAL sign_out_dffe5_wi : STD_LOGIC;
SIGNAL sign_out_dffe5_wo : STD_LOGIC;
SIGNAL sign_res_dffe3_wi : STD_LOGIC;
SIGNAL sign_res_dffe3_wo : STD_LOGIC;
SIGNAL sign_res_dffe41_wi : STD_LOGIC;
SIGNAL sign_res_dffe41_wo : STD_LOGIC;
SIGNAL sign_res_dffe42_wi : STD_LOGIC;
SIGNAL sign_res_dffe42_wo : STD_LOGIC;
SIGNAL sign_res_dffe4_wi : STD_LOGIC;
SIGNAL sign_res_dffe4_wo : STD_LOGIC;
SIGNAL sticky_bit_cnt_dataa_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sticky_bit_cnt_datab_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sticky_bit_cnt_res_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sticky_bit_dffe1_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe1_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe21_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe21_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe22_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe22_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe23_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe23_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe25_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe25_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe26_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe26_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe27_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe27_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe2_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe2_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe31_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe31_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe32_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe32_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe33_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe33_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe3_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe3_wo : STD_LOGIC;
SIGNAL sticky_bit_w : STD_LOGIC;
SIGNAL trailing_zeros_limit_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL zero_man_sign_dffe21_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe21_wo : STD_LOGIC;
SIGNAL zero_man_sign_dffe22_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe22_wo : STD_LOGIC;
SIGNAL zero_man_sign_dffe23_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe23_wo : STD_LOGIC;
SIGNAL zero_man_sign_dffe26_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe26_wo : STD_LOGIC;
SIGNAL zero_man_sign_dffe27_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe27_wo : STD_LOGIC;
SIGNAL zero_man_sign_dffe2_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe2_wo : STD_LOGIC;
SIGNAL wire_w_aligned_dataa_exp_dffe15_wo_range315w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_aligned_datab_exp_dffe15_wo_range313w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_dataa_range141w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range147w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range153w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range159w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range165w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range171w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range177w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range183w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range189w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range195w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range87w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range201w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range207w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range213w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range17w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range27w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range37w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range47w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range57w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range67w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range93w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range77w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range99w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range105w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range111w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range117w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range123w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range129w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range135w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_dffe11_wo_range242w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_dataa_dffe11_wo_range232w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_datab_range144w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range150w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range156w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range162w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range168w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range174w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range180w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range186w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range192w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range198w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range90w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range204w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range210w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range216w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range20w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range30w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range40w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range50w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range60w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range70w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range96w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range80w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range102w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range108w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range114w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range120w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range126w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range132w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range138w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_dffe11_wo_range261w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_datab_dffe11_wo_range251w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range7w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range24w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range34w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range44w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range54w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range64w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range74w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range84w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range2w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range19w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range29w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range39w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range49w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range59w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range69w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range518w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range521w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range524w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range527w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range530w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range533w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range557w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range536w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range511w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_amb_w_range275w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range9w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range26w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range36w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range46w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range56w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range66w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range76w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range86w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range5w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range22w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range32w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range42w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range52w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range62w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range72w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_bma_w_range273w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_exceed_max_w_range283w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_exceed_max_w_range287w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_exceed_max_w_range290w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_w_range291w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_w_range285w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_w_range288w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range540w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range543w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range545w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range547w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range549w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range551w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range553w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range555w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range516w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range520w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range523w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range526w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range529w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range532w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range535w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range538w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range601w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range605w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range608w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range611w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range614w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range617w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range620w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range603w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range606w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range609w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range612w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range615w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range618w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range621w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range12w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range143w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range149w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range155w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range161w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range167w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range173w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range179w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range185w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range191w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range197w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range89w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range203w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range209w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range215w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range95w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range101w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range107w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range113w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range119w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range125w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range131w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range137w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range443w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range446w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range449w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range452w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range455w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range458w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range461w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range464w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range467w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range470w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range473w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range476w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range479w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range482w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range485w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range488w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range419w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range422w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range425w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range428w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range431w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range434w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range437w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range440w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe27_wo_range396w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe27_wo_range411w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe27_wo_range387w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe27_wo_range413w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe27_wo_range381w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_w_range372w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range15w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range146w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range152w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range158w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range164w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range170w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range176w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range182w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range188w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range194w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range200w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range92w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range206w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range212w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range218w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range98w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range104w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range110w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range116w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range122w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range128w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range134w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range140w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range417w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range448w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range451w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range454w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range457w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range460w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range463w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range466w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range469w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range472w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range475w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range421w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range478w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range481w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range484w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range487w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range424w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range427w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range430w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range433w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range436w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range439w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range442w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range445w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_rounding_add_sub_w_range584w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_man_res_rounding_add_sub_w_range588w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_man_res_rounding_add_sub_w_range585w : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT add_flt_stratix5_speed_altbarrel_shift_nud
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
distance : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR(25 DOWNTO 0)
);
END COMPONENT;
COMPONENT add_flt_stratix5_speed_altbarrel_shift_u1g
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
distance : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR(25 DOWNTO 0)
);
END COMPONENT;
COMPONENT add_flt_stratix5_speed_altpriority_encoder_ou8
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT;
COMPONENT add_flt_stratix5_speed_altpriority_encoder_dna
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT;
COMPONENT lpm_add_sub
GENERIC
(
LPM_DIRECTION : STRING := "DEFAULT";
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "SIGNED";
LPM_WIDTH : NATURAL;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_add_sub"
);
PORT
(
aclr : IN STD_LOGIC := '0';
add_sub : IN STD_LOGIC := '1';
cin : IN STD_LOGIC := 'Z';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
cout : OUT STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
overflow : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT lpm_compare
GENERIC
(
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "UNSIGNED";
LPM_WIDTH : NATURAL;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_compare"
);
PORT
(
aclr : IN STD_LOGIC := '0';
aeb : OUT STD_LOGIC;
agb : OUT STD_LOGIC;
ageb : OUT STD_LOGIC;
alb : OUT STD_LOGIC;
aleb : OUT STD_LOGIC;
aneb : OUT STD_LOGIC;
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
BEGIN
wire_gnd <= '0';
wire_vcc <= '1';
wire_w248w(0) <= wire_w_lg_w_lg_input_dataa_infinite_dffe11_wo246w247w(0) AND wire_w_lg_input_dataa_zero_dffe11_wo245w(0);
wire_w267w(0) <= wire_w_lg_w_lg_input_datab_infinite_dffe11_wo265w266w(0) AND wire_w_lg_input_datab_zero_dffe11_wo264w(0);
wire_w_lg_w397w407w(0) <= wire_w397w(0) AND sticky_bit_dffe27_wo;
loop83 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_w_lg_force_zero_w634w635w636w(i) <= wire_w_lg_w_lg_force_zero_w634w635w(0) AND exp_res_dffe4_wo(i);
END GENERATE loop83;
loop84 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_w_lg_force_zero_w634w635w645w(i) <= wire_w_lg_w_lg_force_zero_w634w635w(0) AND man_res_dffe4_wo(i);
END GENERATE loop84;
loop85 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_denormal_result_w558w559w(i) <= wire_w_lg_denormal_result_w558w(0) AND wire_w_exp_adjustment2_add_sub_w_range557w(i);
END GENERATE loop85;
loop86 : FOR i IN 0 TO 25 GENERATE
wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w324w(i) <= wire_w_lg_exp_amb_mux_dffe15_wo316w(0) AND aligned_dataa_man_dffe15_w(i);
END GENERATE loop86;
loop87 : FOR i IN 0 TO 25 GENERATE
wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w331w(i) <= wire_w_lg_exp_amb_mux_dffe15_wo316w(0) AND wire_rbarrel_shift_result(i);
END GENERATE loop87;
loop88 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w317w(i) <= wire_w_lg_exp_amb_mux_dffe15_wo316w(0) AND wire_w_aligned_dataa_exp_dffe15_wo_range315w(i);
END GENERATE loop88;
loop89 : FOR i IN 0 TO 23 GENERATE
wire_w_lg_w_lg_exp_amb_mux_w276w279w(i) <= wire_w_lg_exp_amb_mux_w276w(0) AND aligned_datab_man_dffe12_wo(i);
END GENERATE loop89;
loop90 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_exp_amb_mux_w276w277w(i) <= wire_w_lg_exp_amb_mux_w276w(0) AND wire_w_exp_amb_w_range275w(i);
END GENERATE loop90;
loop91 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_force_infinity_w629w639w(i) <= wire_w_lg_force_infinity_w629w(0) AND wire_w_lg_w_lg_w_lg_force_zero_w634w637w638w(i);
END GENERATE loop91;
loop92 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_force_infinity_w629w648w(i) <= wire_w_lg_force_infinity_w629w(0) AND wire_w_lg_w_lg_w_lg_force_zero_w634w646w647w(i);
END GENERATE loop92;
wire_w_lg_w_lg_force_infinity_w629w654w(0) <= wire_w_lg_force_infinity_w629w(0) AND sign_res_dffe4_wo;
loop93 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_force_nan_w630w642w(i) <= wire_w_lg_force_nan_w630w(0) AND wire_w_lg_w_lg_force_infinity_w640w641w(i);
END GENERATE loop93;
loop94 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_force_nan_w630w651w(i) <= wire_w_lg_force_nan_w630w(0) AND wire_w_lg_w_lg_force_infinity_w649w650w(i);
END GENERATE loop94;
loop95 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w243w(i) <= wire_w_lg_input_dataa_denormal_dffe11_wo233w(0) AND wire_w_dataa_dffe11_wo_range242w(i);
END GENERATE loop95;
loop96 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w234w(i) <= wire_w_lg_input_dataa_denormal_dffe11_wo233w(0) AND wire_w_dataa_dffe11_wo_range232w(i);
END GENERATE loop96;
wire_w_lg_w_lg_input_dataa_infinite_dffe11_wo246w247w(0) <= wire_w_lg_input_dataa_infinite_dffe11_wo246w(0) AND wire_w_lg_input_dataa_denormal_dffe11_wo233w(0);
loop97 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w262w(i) <= wire_w_lg_input_datab_denormal_dffe11_wo252w(0) AND wire_w_datab_dffe11_wo_range261w(i);
END GENERATE loop97;
loop98 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w253w(i) <= wire_w_lg_input_datab_denormal_dffe11_wo252w(0) AND wire_w_datab_dffe11_wo_range251w(i);
END GENERATE loop98;
wire_w_lg_w_lg_input_datab_infinite_dffe11_wo265w266w(0) <= wire_w_lg_input_datab_infinite_dffe11_wo265w(0) AND wire_w_lg_input_datab_denormal_dffe11_wo252w(0);
wire_w_lg_w_lg_input_datab_infinite_dffe15_wo337w338w(0) <= wire_w_lg_input_datab_infinite_dffe15_wo337w(0) AND aligned_dataa_sign_dffe15_wo;
wire_w_lg_w_lg_man_res_not_zero_dffe26_wo503w504w(0) <= wire_w_lg_man_res_not_zero_dffe26_wo503w(0) AND zero_man_sign_dffe26_wo;
loop99 : FOR i IN 0 TO 4 GENERATE
wire_w293w(i) <= wire_w_lg_w_exp_diff_abs_exceed_max_w_range290w292w(0) AND wire_w_exp_diff_abs_w_range291w(i);
END GENERATE loop99;
wire_w397w(0) <= wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) AND wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range387w390w(0);
loop100 : FOR i IN 0 TO 1 GENERATE
wire_w383w(i) <= wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) AND exp_adjust_by_add1(i);
END GENERATE loop100;
loop101 : FOR i IN 0 TO 25 GENERATE
wire_w412w(i) <= wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) AND wire_w_man_add_sub_res_mag_dffe27_wo_range411w(i);
END GENERATE loop101;
loop102 : FOR i IN 0 TO 27 GENERATE
wire_w_lg_w_lg_w_man_add_sub_w_range372w375w378w(i) <= wire_w_lg_w_man_add_sub_w_range372w375w(0) AND man_add_sub_w(i);
END GENERATE loop102;
loop103 : FOR i IN 0 TO 22 GENERATE
wire_w587w(i) <= wire_w_lg_w_man_res_rounding_add_sub_w_range585w586w(0) AND wire_w_man_res_rounding_add_sub_w_range584w(i);
END GENERATE loop103;
loop104 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_force_zero_w634w637w(i) <= wire_w_lg_force_zero_w634w(0) AND exp_all_zeros_w(i);
END GENERATE loop104;
loop105 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_force_zero_w634w646w(i) <= wire_w_lg_force_zero_w634w(0) AND man_all_zeros_w(i);
END GENERATE loop105;
loop106 : FOR i IN 0 TO 25 GENERATE
wire_w_lg_exp_amb_mux_dffe15_wo330w(i) <= exp_amb_mux_dffe15_wo AND aligned_datab_man_dffe15_w(i);
END GENERATE loop106;
loop107 : FOR i IN 0 TO 25 GENERATE
wire_w_lg_exp_amb_mux_dffe15_wo323w(i) <= exp_amb_mux_dffe15_wo AND wire_rbarrel_shift_result(i);
END GENERATE loop107;
loop108 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_exp_amb_mux_dffe15_wo314w(i) <= exp_amb_mux_dffe15_wo AND wire_w_aligned_datab_exp_dffe15_wo_range313w(i);
END GENERATE loop108;
loop109 : FOR i IN 0 TO 23 GENERATE
wire_w_lg_exp_amb_mux_w280w(i) <= exp_amb_mux_w AND aligned_dataa_man_dffe12_wo(i);
END GENERATE loop109;
loop110 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_exp_amb_mux_w274w(i) <= exp_amb_mux_w AND wire_w_exp_bma_w_range273w(i);
END GENERATE loop110;
loop111 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_force_infinity_w640w(i) <= force_infinity_w AND exp_all_ones_w(i);
END GENERATE loop111;
loop112 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_force_infinity_w649w(i) <= force_infinity_w AND man_all_zeros_w(i);
END GENERATE loop112;
loop113 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_force_nan_w643w(i) <= force_nan_w AND exp_all_ones_w(i);
END GENERATE loop113;
loop114 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_force_nan_w652w(i) <= force_nan_w AND man_nan_w(i);
END GENERATE loop114;
wire_w_lg_need_complement_dffe22_wo376w(0) <= need_complement_dffe22_wo AND wire_w_lg_w_man_add_sub_w_range372w375w(0);
wire_w_lg_w_dataa_range17w23w(0) <= wire_w_dataa_range17w(0) AND wire_w_exp_a_all_one_w_range7w(0);
wire_w_lg_w_dataa_range27w33w(0) <= wire_w_dataa_range27w(0) AND wire_w_exp_a_all_one_w_range24w(0);
wire_w_lg_w_dataa_range37w43w(0) <= wire_w_dataa_range37w(0) AND wire_w_exp_a_all_one_w_range34w(0);
wire_w_lg_w_dataa_range47w53w(0) <= wire_w_dataa_range47w(0) AND wire_w_exp_a_all_one_w_range44w(0);
wire_w_lg_w_dataa_range57w63w(0) <= wire_w_dataa_range57w(0) AND wire_w_exp_a_all_one_w_range54w(0);
wire_w_lg_w_dataa_range67w73w(0) <= wire_w_dataa_range67w(0) AND wire_w_exp_a_all_one_w_range64w(0);
wire_w_lg_w_dataa_range77w83w(0) <= wire_w_dataa_range77w(0) AND wire_w_exp_a_all_one_w_range74w(0);
wire_w_lg_w_datab_range20w25w(0) <= wire_w_datab_range20w(0) AND wire_w_exp_b_all_one_w_range9w(0);
wire_w_lg_w_datab_range30w35w(0) <= wire_w_datab_range30w(0) AND wire_w_exp_b_all_one_w_range26w(0);
wire_w_lg_w_datab_range40w45w(0) <= wire_w_datab_range40w(0) AND wire_w_exp_b_all_one_w_range36w(0);
wire_w_lg_w_datab_range50w55w(0) <= wire_w_datab_range50w(0) AND wire_w_exp_b_all_one_w_range46w(0);
wire_w_lg_w_datab_range60w65w(0) <= wire_w_datab_range60w(0) AND wire_w_exp_b_all_one_w_range56w(0);
wire_w_lg_w_datab_range70w75w(0) <= wire_w_datab_range70w(0) AND wire_w_exp_b_all_one_w_range66w(0);
wire_w_lg_w_datab_range80w85w(0) <= wire_w_datab_range80w(0) AND wire_w_exp_b_all_one_w_range76w(0);
wire_w_lg_w_exp_a_all_one_w_range84w220w(0) <= wire_w_exp_a_all_one_w_range84w(0) AND wire_w_lg_w_man_a_not_zero_w_range215w219w(0);
wire_w_lg_w_exp_b_all_one_w_range86w226w(0) <= wire_w_exp_b_all_one_w_range86w(0) AND wire_w_lg_w_man_b_not_zero_w_range218w225w(0);
loop115 : FOR i IN 0 TO 4 GENERATE
wire_w_lg_w_exp_diff_abs_exceed_max_w_range290w294w(i) <= wire_w_exp_diff_abs_exceed_max_w_range290w(0) AND exp_diff_abs_max_w(i);
END GENERATE loop115;
wire_w_lg_w_exp_res_max_w_range540w542w(0) <= wire_w_exp_res_max_w_range540w(0) AND wire_w_exp_adjustment2_add_sub_w_range518w(0);
wire_w_lg_w_exp_res_max_w_range543w544w(0) <= wire_w_exp_res_max_w_range543w(0) AND wire_w_exp_adjustment2_add_sub_w_range521w(0);
wire_w_lg_w_exp_res_max_w_range545w546w(0) <= wire_w_exp_res_max_w_range545w(0) AND wire_w_exp_adjustment2_add_sub_w_range524w(0);
wire_w_lg_w_exp_res_max_w_range547w548w(0) <= wire_w_exp_res_max_w_range547w(0) AND wire_w_exp_adjustment2_add_sub_w_range527w(0);
wire_w_lg_w_exp_res_max_w_range549w550w(0) <= wire_w_exp_res_max_w_range549w(0) AND wire_w_exp_adjustment2_add_sub_w_range530w(0);
wire_w_lg_w_exp_res_max_w_range551w552w(0) <= wire_w_exp_res_max_w_range551w(0) AND wire_w_exp_adjustment2_add_sub_w_range533w(0);
wire_w_lg_w_exp_res_max_w_range553w554w(0) <= wire_w_exp_res_max_w_range553w(0) AND wire_w_exp_adjustment2_add_sub_w_range536w(0);
wire_w_lg_w_exp_res_max_w_range555w561w(0) <= wire_w_exp_res_max_w_range555w(0) AND wire_w_lg_w_exp_adjustment2_add_sub_w_range511w560w(0);
wire_w_lg_w_exp_rounded_res_max_w_range601w604w(0) <= wire_w_exp_rounded_res_max_w_range601w(0) AND wire_w_exp_rounded_res_w_range603w(0);
wire_w_lg_w_exp_rounded_res_max_w_range605w607w(0) <= wire_w_exp_rounded_res_max_w_range605w(0) AND wire_w_exp_rounded_res_w_range606w(0);
wire_w_lg_w_exp_rounded_res_max_w_range608w610w(0) <= wire_w_exp_rounded_res_max_w_range608w(0) AND wire_w_exp_rounded_res_w_range609w(0);
wire_w_lg_w_exp_rounded_res_max_w_range611w613w(0) <= wire_w_exp_rounded_res_max_w_range611w(0) AND wire_w_exp_rounded_res_w_range612w(0);
wire_w_lg_w_exp_rounded_res_max_w_range614w616w(0) <= wire_w_exp_rounded_res_max_w_range614w(0) AND wire_w_exp_rounded_res_w_range615w(0);
wire_w_lg_w_exp_rounded_res_max_w_range617w619w(0) <= wire_w_exp_rounded_res_max_w_range617w(0) AND wire_w_exp_rounded_res_w_range618w(0);
wire_w_lg_w_exp_rounded_res_max_w_range620w622w(0) <= wire_w_exp_rounded_res_max_w_range620w(0) AND wire_w_exp_rounded_res_w_range621w(0);
wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w391w(0) <= wire_w_man_add_sub_res_mag_dffe27_wo_range381w(0) AND wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range387w390w(0);
loop116 : FOR i IN 0 TO 1 GENERATE
wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w384w(i) <= wire_w_man_add_sub_res_mag_dffe27_wo_range381w(0) AND exp_adjust_by_add2(i);
END GENERATE loop116;
loop117 : FOR i IN 0 TO 25 GENERATE
wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w414w(i) <= wire_w_man_add_sub_res_mag_dffe27_wo_range381w(0) AND wire_w_man_add_sub_res_mag_dffe27_wo_range413w(i);
END GENERATE loop117;
loop118 : FOR i IN 0 TO 27 GENERATE
wire_w_lg_w_man_add_sub_w_range372w379w(i) <= wire_w_man_add_sub_w_range372w(0) AND man_2comp_res_w(i);
END GENERATE loop118;
loop119 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_man_res_rounding_add_sub_w_range585w589w(i) <= wire_w_man_res_rounding_add_sub_w_range585w(0) AND wire_w_man_res_rounding_add_sub_w_range588w(i);
END GENERATE loop119;
wire_w_lg_w_lg_force_zero_w634w635w(0) <= NOT wire_w_lg_force_zero_w634w(0);
wire_w_lg_add_sub_dffe25_wo491w(0) <= NOT add_sub_dffe25_wo;
wire_w_lg_add_sub_w2342w(0) <= NOT add_sub_w2;
wire_w_lg_denormal_result_w558w(0) <= NOT denormal_result_w;
wire_w_lg_exp_amb_mux_dffe15_wo316w(0) <= NOT exp_amb_mux_dffe15_wo;
wire_w_lg_exp_amb_mux_w276w(0) <= NOT exp_amb_mux_w;
wire_w_lg_force_infinity_w629w(0) <= NOT force_infinity_w;
wire_w_lg_force_nan_w630w(0) <= NOT force_nan_w;
wire_w_lg_force_zero_w628w(0) <= NOT force_zero_w;
wire_w_lg_input_dataa_denormal_dffe11_wo233w(0) <= NOT input_dataa_denormal_dffe11_wo;
wire_w_lg_input_dataa_infinite_dffe11_wo246w(0) <= NOT input_dataa_infinite_dffe11_wo;
wire_w_lg_input_dataa_zero_dffe11_wo245w(0) <= NOT input_dataa_zero_dffe11_wo;
wire_w_lg_input_datab_denormal_dffe11_wo252w(0) <= NOT input_datab_denormal_dffe11_wo;
wire_w_lg_input_datab_infinite_dffe11_wo265w(0) <= NOT input_datab_infinite_dffe11_wo;
wire_w_lg_input_datab_infinite_dffe15_wo337w(0) <= NOT input_datab_infinite_dffe15_wo;
wire_w_lg_input_datab_zero_dffe11_wo264w(0) <= NOT input_datab_zero_dffe11_wo;
wire_w_lg_man_res_is_not_zero_dffe4_wo627w(0) <= NOT man_res_is_not_zero_dffe4_wo;
wire_w_lg_man_res_not_zero_dffe26_wo503w(0) <= NOT man_res_not_zero_dffe26_wo;
wire_w_lg_need_complement_dffe22_wo373w(0) <= NOT need_complement_dffe22_wo;
wire_w_lg_sticky_bit_dffe1_wo343w(0) <= NOT sticky_bit_dffe1_wo;
wire_w_lg_w_exp_adjustment2_add_sub_w_range511w560w(0) <= NOT wire_w_exp_adjustment2_add_sub_w_range511w(0);
wire_w_lg_w_exp_diff_abs_exceed_max_w_range290w292w(0) <= NOT wire_w_exp_diff_abs_exceed_max_w_range290w(0);
wire_w_lg_w_man_a_not_zero_w_range215w219w(0) <= NOT wire_w_man_a_not_zero_w_range215w(0);
wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range387w390w(0) <= NOT wire_w_man_add_sub_res_mag_dffe27_wo_range387w(0);
wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) <= NOT wire_w_man_add_sub_res_mag_dffe27_wo_range381w(0);
wire_w_lg_w_man_add_sub_w_range372w375w(0) <= NOT wire_w_man_add_sub_w_range372w(0);
wire_w_lg_w_man_b_not_zero_w_range218w225w(0) <= NOT wire_w_man_b_not_zero_w_range218w(0);
wire_w_lg_w_man_res_rounding_add_sub_w_range585w586w(0) <= NOT wire_w_man_res_rounding_add_sub_w_range585w(0);
loop120 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_w_lg_force_zero_w634w637w638w(i) <= wire_w_lg_w_lg_force_zero_w634w637w(i) OR wire_w_lg_w_lg_w_lg_force_zero_w634w635w636w(i);
END GENERATE loop120;
loop121 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_w_lg_force_zero_w634w646w647w(i) <= wire_w_lg_w_lg_force_zero_w634w646w(i) OR wire_w_lg_w_lg_w_lg_force_zero_w634w635w645w(i);
END GENERATE loop121;
loop122 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_force_infinity_w640w641w(i) <= wire_w_lg_force_infinity_w640w(i) OR wire_w_lg_w_lg_force_infinity_w629w639w(i);
END GENERATE loop122;
loop123 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_force_infinity_w649w650w(i) <= wire_w_lg_force_infinity_w649w(i) OR wire_w_lg_w_lg_force_infinity_w629w648w(i);
END GENERATE loop123;
wire_w_lg_force_zero_w634w(0) <= force_zero_w OR denormal_flag_w;
wire_w_lg_sticky_bit_dffe27_wo402w(0) <= sticky_bit_dffe27_wo OR wire_w_man_add_sub_res_mag_dffe27_wo_range396w(0);
wire_w_lg_w_dataa_range141w142w(0) <= wire_w_dataa_range141w(0) OR wire_w_man_a_not_zero_w_range137w(0);
wire_w_lg_w_dataa_range147w148w(0) <= wire_w_dataa_range147w(0) OR wire_w_man_a_not_zero_w_range143w(0);
wire_w_lg_w_dataa_range153w154w(0) <= wire_w_dataa_range153w(0) OR wire_w_man_a_not_zero_w_range149w(0);
wire_w_lg_w_dataa_range159w160w(0) <= wire_w_dataa_range159w(0) OR wire_w_man_a_not_zero_w_range155w(0);
wire_w_lg_w_dataa_range165w166w(0) <= wire_w_dataa_range165w(0) OR wire_w_man_a_not_zero_w_range161w(0);
wire_w_lg_w_dataa_range171w172w(0) <= wire_w_dataa_range171w(0) OR wire_w_man_a_not_zero_w_range167w(0);
wire_w_lg_w_dataa_range177w178w(0) <= wire_w_dataa_range177w(0) OR wire_w_man_a_not_zero_w_range173w(0);
wire_w_lg_w_dataa_range183w184w(0) <= wire_w_dataa_range183w(0) OR wire_w_man_a_not_zero_w_range179w(0);
wire_w_lg_w_dataa_range189w190w(0) <= wire_w_dataa_range189w(0) OR wire_w_man_a_not_zero_w_range185w(0);
wire_w_lg_w_dataa_range195w196w(0) <= wire_w_dataa_range195w(0) OR wire_w_man_a_not_zero_w_range191w(0);
wire_w_lg_w_dataa_range87w88w(0) <= wire_w_dataa_range87w(0) OR wire_w_man_a_not_zero_w_range12w(0);
wire_w_lg_w_dataa_range201w202w(0) <= wire_w_dataa_range201w(0) OR wire_w_man_a_not_zero_w_range197w(0);
wire_w_lg_w_dataa_range207w208w(0) <= wire_w_dataa_range207w(0) OR wire_w_man_a_not_zero_w_range203w(0);
wire_w_lg_w_dataa_range213w214w(0) <= wire_w_dataa_range213w(0) OR wire_w_man_a_not_zero_w_range209w(0);
wire_w_lg_w_dataa_range17w18w(0) <= wire_w_dataa_range17w(0) OR wire_w_exp_a_not_zero_w_range2w(0);
wire_w_lg_w_dataa_range27w28w(0) <= wire_w_dataa_range27w(0) OR wire_w_exp_a_not_zero_w_range19w(0);
wire_w_lg_w_dataa_range37w38w(0) <= wire_w_dataa_range37w(0) OR wire_w_exp_a_not_zero_w_range29w(0);
wire_w_lg_w_dataa_range47w48w(0) <= wire_w_dataa_range47w(0) OR wire_w_exp_a_not_zero_w_range39w(0);
wire_w_lg_w_dataa_range57w58w(0) <= wire_w_dataa_range57w(0) OR wire_w_exp_a_not_zero_w_range49w(0);
wire_w_lg_w_dataa_range67w68w(0) <= wire_w_dataa_range67w(0) OR wire_w_exp_a_not_zero_w_range59w(0);
wire_w_lg_w_dataa_range93w94w(0) <= wire_w_dataa_range93w(0) OR wire_w_man_a_not_zero_w_range89w(0);
wire_w_lg_w_dataa_range77w78w(0) <= wire_w_dataa_range77w(0) OR wire_w_exp_a_not_zero_w_range69w(0);
wire_w_lg_w_dataa_range99w100w(0) <= wire_w_dataa_range99w(0) OR wire_w_man_a_not_zero_w_range95w(0);
wire_w_lg_w_dataa_range105w106w(0) <= wire_w_dataa_range105w(0) OR wire_w_man_a_not_zero_w_range101w(0);
wire_w_lg_w_dataa_range111w112w(0) <= wire_w_dataa_range111w(0) OR wire_w_man_a_not_zero_w_range107w(0);
wire_w_lg_w_dataa_range117w118w(0) <= wire_w_dataa_range117w(0) OR wire_w_man_a_not_zero_w_range113w(0);
wire_w_lg_w_dataa_range123w124w(0) <= wire_w_dataa_range123w(0) OR wire_w_man_a_not_zero_w_range119w(0);
wire_w_lg_w_dataa_range129w130w(0) <= wire_w_dataa_range129w(0) OR wire_w_man_a_not_zero_w_range125w(0);
wire_w_lg_w_dataa_range135w136w(0) <= wire_w_dataa_range135w(0) OR wire_w_man_a_not_zero_w_range131w(0);
wire_w_lg_w_datab_range144w145w(0) <= wire_w_datab_range144w(0) OR wire_w_man_b_not_zero_w_range140w(0);
wire_w_lg_w_datab_range150w151w(0) <= wire_w_datab_range150w(0) OR wire_w_man_b_not_zero_w_range146w(0);
wire_w_lg_w_datab_range156w157w(0) <= wire_w_datab_range156w(0) OR wire_w_man_b_not_zero_w_range152w(0);
wire_w_lg_w_datab_range162w163w(0) <= wire_w_datab_range162w(0) OR wire_w_man_b_not_zero_w_range158w(0);
wire_w_lg_w_datab_range168w169w(0) <= wire_w_datab_range168w(0) OR wire_w_man_b_not_zero_w_range164w(0);
wire_w_lg_w_datab_range174w175w(0) <= wire_w_datab_range174w(0) OR wire_w_man_b_not_zero_w_range170w(0);
wire_w_lg_w_datab_range180w181w(0) <= wire_w_datab_range180w(0) OR wire_w_man_b_not_zero_w_range176w(0);
wire_w_lg_w_datab_range186w187w(0) <= wire_w_datab_range186w(0) OR wire_w_man_b_not_zero_w_range182w(0);
wire_w_lg_w_datab_range192w193w(0) <= wire_w_datab_range192w(0) OR wire_w_man_b_not_zero_w_range188w(0);
wire_w_lg_w_datab_range198w199w(0) <= wire_w_datab_range198w(0) OR wire_w_man_b_not_zero_w_range194w(0);
wire_w_lg_w_datab_range90w91w(0) <= wire_w_datab_range90w(0) OR wire_w_man_b_not_zero_w_range15w(0);
wire_w_lg_w_datab_range204w205w(0) <= wire_w_datab_range204w(0) OR wire_w_man_b_not_zero_w_range200w(0);
wire_w_lg_w_datab_range210w211w(0) <= wire_w_datab_range210w(0) OR wire_w_man_b_not_zero_w_range206w(0);
wire_w_lg_w_datab_range216w217w(0) <= wire_w_datab_range216w(0) OR wire_w_man_b_not_zero_w_range212w(0);
wire_w_lg_w_datab_range20w21w(0) <= wire_w_datab_range20w(0) OR wire_w_exp_b_not_zero_w_range5w(0);
wire_w_lg_w_datab_range30w31w(0) <= wire_w_datab_range30w(0) OR wire_w_exp_b_not_zero_w_range22w(0);
wire_w_lg_w_datab_range40w41w(0) <= wire_w_datab_range40w(0) OR wire_w_exp_b_not_zero_w_range32w(0);
wire_w_lg_w_datab_range50w51w(0) <= wire_w_datab_range50w(0) OR wire_w_exp_b_not_zero_w_range42w(0);
wire_w_lg_w_datab_range60w61w(0) <= wire_w_datab_range60w(0) OR wire_w_exp_b_not_zero_w_range52w(0);
wire_w_lg_w_datab_range70w71w(0) <= wire_w_datab_range70w(0) OR wire_w_exp_b_not_zero_w_range62w(0);
wire_w_lg_w_datab_range96w97w(0) <= wire_w_datab_range96w(0) OR wire_w_man_b_not_zero_w_range92w(0);
wire_w_lg_w_datab_range80w81w(0) <= wire_w_datab_range80w(0) OR wire_w_exp_b_not_zero_w_range72w(0);
wire_w_lg_w_datab_range102w103w(0) <= wire_w_datab_range102w(0) OR wire_w_man_b_not_zero_w_range98w(0);
wire_w_lg_w_datab_range108w109w(0) <= wire_w_datab_range108w(0) OR wire_w_man_b_not_zero_w_range104w(0);
wire_w_lg_w_datab_range114w115w(0) <= wire_w_datab_range114w(0) OR wire_w_man_b_not_zero_w_range110w(0);
wire_w_lg_w_datab_range120w121w(0) <= wire_w_datab_range120w(0) OR wire_w_man_b_not_zero_w_range116w(0);
wire_w_lg_w_datab_range126w127w(0) <= wire_w_datab_range126w(0) OR wire_w_man_b_not_zero_w_range122w(0);
wire_w_lg_w_datab_range132w133w(0) <= wire_w_datab_range132w(0) OR wire_w_man_b_not_zero_w_range128w(0);
wire_w_lg_w_datab_range138w139w(0) <= wire_w_datab_range138w(0) OR wire_w_man_b_not_zero_w_range134w(0);
wire_w_lg_w_exp_diff_abs_exceed_max_w_range283w286w(0) <= wire_w_exp_diff_abs_exceed_max_w_range283w(0) OR wire_w_exp_diff_abs_w_range285w(0);
wire_w_lg_w_exp_diff_abs_exceed_max_w_range287w289w(0) <= wire_w_exp_diff_abs_exceed_max_w_range287w(0) OR wire_w_exp_diff_abs_w_range288w(0);
wire_w_lg_w_exp_res_not_zero_w_range516w519w(0) <= wire_w_exp_res_not_zero_w_range516w(0) OR wire_w_exp_adjustment2_add_sub_w_range518w(0);
wire_w_lg_w_exp_res_not_zero_w_range520w522w(0) <= wire_w_exp_res_not_zero_w_range520w(0) OR wire_w_exp_adjustment2_add_sub_w_range521w(0);
wire_w_lg_w_exp_res_not_zero_w_range523w525w(0) <= wire_w_exp_res_not_zero_w_range523w(0) OR wire_w_exp_adjustment2_add_sub_w_range524w(0);
wire_w_lg_w_exp_res_not_zero_w_range526w528w(0) <= wire_w_exp_res_not_zero_w_range526w(0) OR wire_w_exp_adjustment2_add_sub_w_range527w(0);
wire_w_lg_w_exp_res_not_zero_w_range529w531w(0) <= wire_w_exp_res_not_zero_w_range529w(0) OR wire_w_exp_adjustment2_add_sub_w_range530w(0);
wire_w_lg_w_exp_res_not_zero_w_range532w534w(0) <= wire_w_exp_res_not_zero_w_range532w(0) OR wire_w_exp_adjustment2_add_sub_w_range533w(0);
wire_w_lg_w_exp_res_not_zero_w_range535w537w(0) <= wire_w_exp_res_not_zero_w_range535w(0) OR wire_w_exp_adjustment2_add_sub_w_range536w(0);
wire_w_lg_w_exp_res_not_zero_w_range538w539w(0) <= wire_w_exp_res_not_zero_w_range538w(0) OR wire_w_exp_adjustment2_add_sub_w_range511w(0);
wire_w_lg_w_man_res_not_zero_w2_range417w420w(0) <= wire_w_man_res_not_zero_w2_range417w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range419w(0);
wire_w_lg_w_man_res_not_zero_w2_range448w450w(0) <= wire_w_man_res_not_zero_w2_range448w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range449w(0);
wire_w_lg_w_man_res_not_zero_w2_range451w453w(0) <= wire_w_man_res_not_zero_w2_range451w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range452w(0);
wire_w_lg_w_man_res_not_zero_w2_range454w456w(0) <= wire_w_man_res_not_zero_w2_range454w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range455w(0);
wire_w_lg_w_man_res_not_zero_w2_range457w459w(0) <= wire_w_man_res_not_zero_w2_range457w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range458w(0);
wire_w_lg_w_man_res_not_zero_w2_range460w462w(0) <= wire_w_man_res_not_zero_w2_range460w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range461w(0);
wire_w_lg_w_man_res_not_zero_w2_range463w465w(0) <= wire_w_man_res_not_zero_w2_range463w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range464w(0);
wire_w_lg_w_man_res_not_zero_w2_range466w468w(0) <= wire_w_man_res_not_zero_w2_range466w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range467w(0);
wire_w_lg_w_man_res_not_zero_w2_range469w471w(0) <= wire_w_man_res_not_zero_w2_range469w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range470w(0);
wire_w_lg_w_man_res_not_zero_w2_range472w474w(0) <= wire_w_man_res_not_zero_w2_range472w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range473w(0);
wire_w_lg_w_man_res_not_zero_w2_range475w477w(0) <= wire_w_man_res_not_zero_w2_range475w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range476w(0);
wire_w_lg_w_man_res_not_zero_w2_range421w423w(0) <= wire_w_man_res_not_zero_w2_range421w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range422w(0);
wire_w_lg_w_man_res_not_zero_w2_range478w480w(0) <= wire_w_man_res_not_zero_w2_range478w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range479w(0);
wire_w_lg_w_man_res_not_zero_w2_range481w483w(0) <= wire_w_man_res_not_zero_w2_range481w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range482w(0);
wire_w_lg_w_man_res_not_zero_w2_range484w486w(0) <= wire_w_man_res_not_zero_w2_range484w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range485w(0);
wire_w_lg_w_man_res_not_zero_w2_range487w489w(0) <= wire_w_man_res_not_zero_w2_range487w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range488w(0);
wire_w_lg_w_man_res_not_zero_w2_range424w426w(0) <= wire_w_man_res_not_zero_w2_range424w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range425w(0);
wire_w_lg_w_man_res_not_zero_w2_range427w429w(0) <= wire_w_man_res_not_zero_w2_range427w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range428w(0);
wire_w_lg_w_man_res_not_zero_w2_range430w432w(0) <= wire_w_man_res_not_zero_w2_range430w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range431w(0);
wire_w_lg_w_man_res_not_zero_w2_range433w435w(0) <= wire_w_man_res_not_zero_w2_range433w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range434w(0);
wire_w_lg_w_man_res_not_zero_w2_range436w438w(0) <= wire_w_man_res_not_zero_w2_range436w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range437w(0);
wire_w_lg_w_man_res_not_zero_w2_range439w441w(0) <= wire_w_man_res_not_zero_w2_range439w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range440w(0);
wire_w_lg_w_man_res_not_zero_w2_range442w444w(0) <= wire_w_man_res_not_zero_w2_range442w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range443w(0);
wire_w_lg_w_man_res_not_zero_w2_range445w447w(0) <= wire_w_man_res_not_zero_w2_range445w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range446w(0);
aclr <= '0';
add_sub_dffe25_wi <= add_sub_w2;
add_sub_dffe25_wo <= add_sub_dffe25_wi;
add_sub_w2 <= (NOT (dataa_sign_dffe1_wo XOR datab_sign_dffe1_wo));
adder_upper_w <= man_intermediate_res_w(25 DOWNTO 13);
aligned_dataa_exp_dffe12_wi <= aligned_dataa_exp_w;
aligned_dataa_exp_dffe12_wo <= aligned_dataa_exp_dffe12;
aligned_dataa_exp_dffe13_wi <= aligned_dataa_exp_dffe12_wo;
aligned_dataa_exp_dffe13_wo <= aligned_dataa_exp_dffe13;
aligned_dataa_exp_dffe14_wi <= aligned_dataa_exp_dffe13_wo;
aligned_dataa_exp_dffe14_wo <= aligned_dataa_exp_dffe14;
aligned_dataa_exp_dffe15_wi <= aligned_dataa_exp_dffe14_wo;
aligned_dataa_exp_dffe15_wo <= aligned_dataa_exp_dffe15;
aligned_dataa_exp_w <= ( "0" & wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w234w);
aligned_dataa_man_dffe12_wi <= aligned_dataa_man_w(25 DOWNTO 2);
aligned_dataa_man_dffe12_wo <= aligned_dataa_man_dffe12;
aligned_dataa_man_dffe13_wi <= aligned_dataa_man_dffe12_wo;
aligned_dataa_man_dffe13_wo <= aligned_dataa_man_dffe13;
aligned_dataa_man_dffe14_wi <= aligned_dataa_man_dffe13_wo;
aligned_dataa_man_dffe14_wo <= aligned_dataa_man_dffe14;
aligned_dataa_man_dffe15_w <= ( aligned_dataa_man_dffe15_wo & "00");
aligned_dataa_man_dffe15_wi <= aligned_dataa_man_dffe14_wo;
aligned_dataa_man_dffe15_wo <= aligned_dataa_man_dffe15;
aligned_dataa_man_w <= ( wire_w248w & wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w243w & "00");
aligned_dataa_sign_dffe12_wi <= aligned_dataa_sign_w;
aligned_dataa_sign_dffe12_wo <= aligned_dataa_sign_dffe12;
aligned_dataa_sign_dffe13_wi <= aligned_dataa_sign_dffe12_wo;
aligned_dataa_sign_dffe13_wo <= aligned_dataa_sign_dffe13;
aligned_dataa_sign_dffe14_wi <= aligned_dataa_sign_dffe13_wo;
aligned_dataa_sign_dffe14_wo <= aligned_dataa_sign_dffe14;
aligned_dataa_sign_dffe15_wi <= aligned_dataa_sign_dffe14_wo;
aligned_dataa_sign_dffe15_wo <= aligned_dataa_sign_dffe15;
aligned_dataa_sign_w <= dataa_dffe11_wo(31);
aligned_datab_exp_dffe12_wi <= aligned_datab_exp_w;
aligned_datab_exp_dffe12_wo <= aligned_datab_exp_dffe12;
aligned_datab_exp_dffe13_wi <= aligned_datab_exp_dffe12_wo;
aligned_datab_exp_dffe13_wo <= aligned_datab_exp_dffe13;
aligned_datab_exp_dffe14_wi <= aligned_datab_exp_dffe13_wo;
aligned_datab_exp_dffe14_wo <= aligned_datab_exp_dffe14;
aligned_datab_exp_dffe15_wi <= aligned_datab_exp_dffe14_wo;
aligned_datab_exp_dffe15_wo <= aligned_datab_exp_dffe15;
aligned_datab_exp_w <= ( "0" & wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w253w);
aligned_datab_man_dffe12_wi <= aligned_datab_man_w(25 DOWNTO 2);
aligned_datab_man_dffe12_wo <= aligned_datab_man_dffe12;
aligned_datab_man_dffe13_wi <= aligned_datab_man_dffe12_wo;
aligned_datab_man_dffe13_wo <= aligned_datab_man_dffe13;
aligned_datab_man_dffe14_wi <= aligned_datab_man_dffe13_wo;
aligned_datab_man_dffe14_wo <= aligned_datab_man_dffe14;
aligned_datab_man_dffe15_w <= ( aligned_datab_man_dffe15_wo & "00");
aligned_datab_man_dffe15_wi <= aligned_datab_man_dffe14_wo;
aligned_datab_man_dffe15_wo <= aligned_datab_man_dffe15;
aligned_datab_man_w <= ( wire_w267w & wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w262w & "00");
aligned_datab_sign_dffe12_wi <= aligned_datab_sign_w;
aligned_datab_sign_dffe12_wo <= aligned_datab_sign_dffe12;
aligned_datab_sign_dffe13_wi <= aligned_datab_sign_dffe12_wo;
aligned_datab_sign_dffe13_wo <= aligned_datab_sign_dffe13;
aligned_datab_sign_dffe14_wi <= aligned_datab_sign_dffe13_wo;
aligned_datab_sign_dffe14_wo <= aligned_datab_sign_dffe14;
aligned_datab_sign_dffe15_wi <= aligned_datab_sign_dffe14_wo;
aligned_datab_sign_dffe15_wo <= aligned_datab_sign_dffe15;
aligned_datab_sign_w <= datab_dffe11_wo(31);
borrow_w <= (wire_w_lg_sticky_bit_dffe1_wo343w(0) AND wire_w_lg_add_sub_w2342w(0));
both_inputs_are_infinite_dffe1_wi <= (input_dataa_infinite_dffe15_wo AND input_datab_infinite_dffe15_wo);
both_inputs_are_infinite_dffe1_wo <= both_inputs_are_infinite_dffe1;
both_inputs_are_infinite_dffe25_wi <= both_inputs_are_infinite_dffe1_wo;
both_inputs_are_infinite_dffe25_wo <= both_inputs_are_infinite_dffe25_wi;
data_exp_dffe1_wi <= (wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w317w OR wire_w_lg_exp_amb_mux_dffe15_wo314w);
data_exp_dffe1_wo <= data_exp_dffe1;
dataa_dffe11_wi <= dataa;
dataa_dffe11_wo <= dataa_dffe11_wi;
dataa_man_dffe1_wi <= (wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w324w OR wire_w_lg_exp_amb_mux_dffe15_wo323w);
dataa_man_dffe1_wo <= dataa_man_dffe1;
dataa_sign_dffe1_wi <= aligned_dataa_sign_dffe15_wo;
dataa_sign_dffe1_wo <= dataa_sign_dffe1;
dataa_sign_dffe25_wi <= dataa_sign_dffe1_wo;
dataa_sign_dffe25_wo <= dataa_sign_dffe25_wi;
datab_dffe11_wi <= datab;
datab_dffe11_wo <= datab_dffe11_wi;
datab_man_dffe1_wi <= (wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w331w OR wire_w_lg_exp_amb_mux_dffe15_wo330w);
datab_man_dffe1_wo <= datab_man_dffe1;
datab_sign_dffe1_wi <= aligned_datab_sign_dffe15_wo;
datab_sign_dffe1_wo <= datab_sign_dffe1;
denormal_flag_w <= (((wire_w_lg_force_nan_w630w(0) AND wire_w_lg_force_infinity_w629w(0)) AND wire_w_lg_force_zero_w628w(0)) AND denormal_res_dffe4_wo);
denormal_res_dffe32_wi <= denormal_result_w;
denormal_res_dffe32_wo <= denormal_res_dffe32_wi;
denormal_res_dffe33_wi <= denormal_res_dffe32_wo;
denormal_res_dffe33_wo <= denormal_res_dffe33_wi;
denormal_res_dffe3_wi <= denormal_res_dffe33_wo;
denormal_res_dffe3_wo <= denormal_res_dffe3;
denormal_res_dffe41_wi <= denormal_res_dffe42_wo;
denormal_res_dffe41_wo <= denormal_res_dffe41;
denormal_res_dffe42_wi <= denormal_res_dffe3_wo;
denormal_res_dffe42_wo <= denormal_res_dffe42_wi;
denormal_res_dffe4_wi <= denormal_res_dffe41_wo;
denormal_res_dffe4_wo <= denormal_res_dffe4;
denormal_result_w <= ((NOT exp_res_not_zero_w(8)) OR exp_adjustment2_add_sub_w(8));
exp_a_all_one_w <= ( wire_w_lg_w_dataa_range77w83w & wire_w_lg_w_dataa_range67w73w & wire_w_lg_w_dataa_range57w63w & wire_w_lg_w_dataa_range47w53w & wire_w_lg_w_dataa_range37w43w & wire_w_lg_w_dataa_range27w33w & wire_w_lg_w_dataa_range17w23w & dataa(23));
exp_a_not_zero_w <= ( wire_w_lg_w_dataa_range77w78w & wire_w_lg_w_dataa_range67w68w & wire_w_lg_w_dataa_range57w58w & wire_w_lg_w_dataa_range47w48w & wire_w_lg_w_dataa_range37w38w & wire_w_lg_w_dataa_range27w28w & wire_w_lg_w_dataa_range17w18w & dataa(23));
exp_adj_0pads <= (OTHERS => '0');
exp_adj_dffe21_wi <= (wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w384w OR wire_w383w);
exp_adj_dffe21_wo <= exp_adj_dffe21;
exp_adj_dffe23_wi <= exp_adj_dffe21_wo;
exp_adj_dffe23_wo <= exp_adj_dffe23;
exp_adj_dffe26_wi <= exp_adj_dffe23_wo;
exp_adj_dffe26_wo <= exp_adj_dffe26_wi;
exp_adjust_by_add1 <= "01";
exp_adjust_by_add2 <= "10";
exp_adjustment2_add_sub_dataa_w <= exp_value;
exp_adjustment2_add_sub_datab_w <= exp_adjustment_add_sub_w;
exp_adjustment2_add_sub_w <= wire_add_sub5_result;
exp_adjustment_add_sub_dataa_w <= ( priority_encoder_1pads_w & wire_leading_zeroes_cnt_q);
exp_adjustment_add_sub_datab_w <= ( exp_adj_0pads & exp_adj_dffe26_wo);
exp_adjustment_add_sub_w <= wire_add_sub4_result;
exp_all_ones_w <= (OTHERS => '1');
exp_all_zeros_w <= (OTHERS => '0');
exp_amb_mux_dffe13_wi <= exp_amb_mux_w;
exp_amb_mux_dffe13_wo <= exp_amb_mux_dffe13;
exp_amb_mux_dffe14_wi <= exp_amb_mux_dffe13_wo;
exp_amb_mux_dffe14_wo <= exp_amb_mux_dffe14;
exp_amb_mux_dffe15_wi <= exp_amb_mux_dffe14_wo;
exp_amb_mux_dffe15_wo <= exp_amb_mux_dffe15;
exp_amb_mux_w <= exp_amb_w(8);
exp_amb_w <= wire_add_sub1_result;
exp_b_all_one_w <= ( wire_w_lg_w_datab_range80w85w & wire_w_lg_w_datab_range70w75w & wire_w_lg_w_datab_range60w65w & wire_w_lg_w_datab_range50w55w & wire_w_lg_w_datab_range40w45w & wire_w_lg_w_datab_range30w35w & wire_w_lg_w_datab_range20w25w & datab(23));
exp_b_not_zero_w <= ( wire_w_lg_w_datab_range80w81w & wire_w_lg_w_datab_range70w71w & wire_w_lg_w_datab_range60w61w & wire_w_lg_w_datab_range50w51w & wire_w_lg_w_datab_range40w41w & wire_w_lg_w_datab_range30w31w & wire_w_lg_w_datab_range20w21w & datab(23));
exp_bma_w <= wire_add_sub2_result;
exp_diff_abs_exceed_max_w <= ( wire_w_lg_w_exp_diff_abs_exceed_max_w_range287w289w & wire_w_lg_w_exp_diff_abs_exceed_max_w_range283w286w & exp_diff_abs_w(5));
exp_diff_abs_max_w <= (OTHERS => '1');
exp_diff_abs_w <= (wire_w_lg_w_lg_exp_amb_mux_w276w277w OR wire_w_lg_exp_amb_mux_w274w);
exp_intermediate_res_dffe41_wi <= exp_intermediate_res_dffe42_wo;
exp_intermediate_res_dffe41_wo <= exp_intermediate_res_dffe41;
exp_intermediate_res_dffe42_wi <= exp_intermediate_res_w;
exp_intermediate_res_dffe42_wo <= exp_intermediate_res_dffe42_wi;
exp_intermediate_res_w <= exp_res_dffe3_wo;
exp_out_dffe5_wi <= (wire_w_lg_force_nan_w643w OR wire_w_lg_w_lg_force_nan_w630w642w);
exp_out_dffe5_wo <= exp_out_dffe5;
exp_res_dffe21_wi <= exp_res_dffe27_wo;
exp_res_dffe21_wo <= exp_res_dffe21;
exp_res_dffe22_wi <= exp_res_dffe2_wo;
exp_res_dffe22_wo <= exp_res_dffe22_wi;
exp_res_dffe23_wi <= exp_res_dffe21_wo;
exp_res_dffe23_wo <= exp_res_dffe23;
exp_res_dffe25_wi <= data_exp_dffe1_wo;
exp_res_dffe25_wo <= exp_res_dffe25_wi;
exp_res_dffe26_wi <= exp_res_dffe23_wo;
exp_res_dffe26_wo <= exp_res_dffe26_wi;
exp_res_dffe27_wi <= exp_res_dffe22_wo;
exp_res_dffe27_wo <= exp_res_dffe27;
exp_res_dffe2_wi <= exp_res_dffe25_wo;
exp_res_dffe2_wo <= exp_res_dffe2;
exp_res_dffe32_wi <= wire_w_lg_w_lg_denormal_result_w558w559w;
exp_res_dffe32_wo <= exp_res_dffe32_wi;
exp_res_dffe33_wi <= exp_res_dffe32_wo;
exp_res_dffe33_wo <= exp_res_dffe33_wi;
exp_res_dffe3_wi <= exp_res_dffe33_wo;
exp_res_dffe3_wo <= exp_res_dffe3;
exp_res_dffe4_wi <= exp_rounded_res_w;
exp_res_dffe4_wo <= exp_res_dffe4;
exp_res_max_w <= ( wire_w_lg_w_exp_res_max_w_range553w554w & wire_w_lg_w_exp_res_max_w_range551w552w & wire_w_lg_w_exp_res_max_w_range549w550w & wire_w_lg_w_exp_res_max_w_range547w548w & wire_w_lg_w_exp_res_max_w_range545w546w & wire_w_lg_w_exp_res_max_w_range543w544w & wire_w_lg_w_exp_res_max_w_range540w542w & exp_adjustment2_add_sub_w(0));
exp_res_not_zero_w <= ( wire_w_lg_w_exp_res_not_zero_w_range538w539w & wire_w_lg_w_exp_res_not_zero_w_range535w537w & wire_w_lg_w_exp_res_not_zero_w_range532w534w & wire_w_lg_w_exp_res_not_zero_w_range529w531w & wire_w_lg_w_exp_res_not_zero_w_range526w528w & wire_w_lg_w_exp_res_not_zero_w_range523w525w & wire_w_lg_w_exp_res_not_zero_w_range520w522w & wire_w_lg_w_exp_res_not_zero_w_range516w519w & exp_adjustment2_add_sub_w(0));
exp_res_rounding_adder_dataa_w <= ( "0" & exp_intermediate_res_dffe41_wo);
exp_res_rounding_adder_w <= wire_add_sub6_result;
exp_rounded_res_infinity_w <= exp_rounded_res_max_w(7);
exp_rounded_res_max_w <= ( wire_w_lg_w_exp_rounded_res_max_w_range620w622w & wire_w_lg_w_exp_rounded_res_max_w_range617w619w & wire_w_lg_w_exp_rounded_res_max_w_range614w616w & wire_w_lg_w_exp_rounded_res_max_w_range611w613w & wire_w_lg_w_exp_rounded_res_max_w_range608w610w & wire_w_lg_w_exp_rounded_res_max_w_range605w607w & wire_w_lg_w_exp_rounded_res_max_w_range601w604w & exp_rounded_res_w(0));
exp_rounded_res_w <= exp_res_rounding_adder_w(7 DOWNTO 0);
exp_rounding_adjustment_w <= ( "00000000" & man_res_rounding_add_sub_w(24));
exp_value <= ( "0" & exp_res_dffe26_wo);
force_infinity_w <= ((input_is_infinite_dffe4_wo OR rounded_res_infinity_dffe4_wo) OR infinite_res_dffe4_wo);
force_nan_w <= (infinity_magnitude_sub_dffe4_wo OR input_is_nan_dffe4_wo);
force_zero_w <= wire_w_lg_man_res_is_not_zero_dffe4_wo627w(0);
guard_bit_dffe3_wo <= man_res_w3(0);
infinite_output_sign_dffe1_wi <= (wire_w_lg_w_lg_input_datab_infinite_dffe15_wo337w338w(0) OR (input_datab_infinite_dffe15_wo AND aligned_datab_sign_dffe15_wo));
infinite_output_sign_dffe1_wo <= infinite_output_sign_dffe1;
infinite_output_sign_dffe21_wi <= infinite_output_sign_dffe27_wo;
infinite_output_sign_dffe21_wo <= infinite_output_sign_dffe21;
infinite_output_sign_dffe22_wi <= infinite_output_sign_dffe2_wo;
infinite_output_sign_dffe22_wo <= infinite_output_sign_dffe22_wi;
infinite_output_sign_dffe23_wi <= infinite_output_sign_dffe21_wo;
infinite_output_sign_dffe23_wo <= infinite_output_sign_dffe23;
infinite_output_sign_dffe25_wi <= infinite_output_sign_dffe1_wo;
infinite_output_sign_dffe25_wo <= infinite_output_sign_dffe25_wi;
infinite_output_sign_dffe26_wi <= infinite_output_sign_dffe23_wo;
infinite_output_sign_dffe26_wo <= infinite_output_sign_dffe26_wi;
infinite_output_sign_dffe27_wi <= infinite_output_sign_dffe22_wo;
infinite_output_sign_dffe27_wo <= infinite_output_sign_dffe27;
infinite_output_sign_dffe2_wi <= infinite_output_sign_dffe25_wo;
infinite_output_sign_dffe2_wo <= infinite_output_sign_dffe2;
infinite_output_sign_dffe31_wi <= infinite_output_sign_dffe26_wo;
infinite_output_sign_dffe31_wo <= infinite_output_sign_dffe31;
infinite_output_sign_dffe32_wi <= infinite_output_sign_dffe31_wo;
infinite_output_sign_dffe32_wo <= infinite_output_sign_dffe32_wi;
infinite_output_sign_dffe33_wi <= infinite_output_sign_dffe32_wo;
infinite_output_sign_dffe33_wo <= infinite_output_sign_dffe33_wi;
infinite_output_sign_dffe3_wi <= infinite_output_sign_dffe33_wo;
infinite_output_sign_dffe3_wo <= infinite_output_sign_dffe3;
infinite_output_sign_dffe41_wi <= infinite_output_sign_dffe42_wo;
infinite_output_sign_dffe41_wo <= infinite_output_sign_dffe41;
infinite_output_sign_dffe42_wi <= infinite_output_sign_dffe3_wo;
infinite_output_sign_dffe42_wo <= infinite_output_sign_dffe42_wi;
infinite_output_sign_dffe4_wi <= infinite_output_sign_dffe41_wo;
infinite_output_sign_dffe4_wo <= infinite_output_sign_dffe4;
infinite_res_dff32_wi <= wire_w_lg_w_exp_res_max_w_range555w561w(0);
infinite_res_dff32_wo <= infinite_res_dff32_wi;
infinite_res_dff33_wi <= infinite_res_dff32_wo;
infinite_res_dff33_wo <= infinite_res_dff33_wi;
infinite_res_dffe3_wi <= infinite_res_dff33_wo;
infinite_res_dffe3_wo <= infinite_res_dffe3;
infinite_res_dffe41_wi <= infinite_res_dffe42_wo;
infinite_res_dffe41_wo <= infinite_res_dffe41;
infinite_res_dffe42_wi <= infinite_res_dffe3_wo;
infinite_res_dffe42_wo <= infinite_res_dffe42_wi;
infinite_res_dffe4_wi <= infinite_res_dffe41_wo;
infinite_res_dffe4_wo <= infinite_res_dffe4;
infinity_magnitude_sub_dffe21_wi <= infinity_magnitude_sub_dffe27_wo;
infinity_magnitude_sub_dffe21_wo <= infinity_magnitude_sub_dffe21;
infinity_magnitude_sub_dffe22_wi <= infinity_magnitude_sub_dffe2_wo;
infinity_magnitude_sub_dffe22_wo <= infinity_magnitude_sub_dffe22_wi;
infinity_magnitude_sub_dffe23_wi <= infinity_magnitude_sub_dffe21_wo;
infinity_magnitude_sub_dffe23_wo <= infinity_magnitude_sub_dffe23;
infinity_magnitude_sub_dffe26_wi <= infinity_magnitude_sub_dffe23_wo;
infinity_magnitude_sub_dffe26_wo <= infinity_magnitude_sub_dffe26_wi;
infinity_magnitude_sub_dffe27_wi <= infinity_magnitude_sub_dffe22_wo;
infinity_magnitude_sub_dffe27_wo <= infinity_magnitude_sub_dffe27;
infinity_magnitude_sub_dffe2_wi <= (wire_w_lg_add_sub_dffe25_wo491w(0) AND both_inputs_are_infinite_dffe25_wo);
infinity_magnitude_sub_dffe2_wo <= infinity_magnitude_sub_dffe2;
infinity_magnitude_sub_dffe31_wi <= infinity_magnitude_sub_dffe26_wo;
infinity_magnitude_sub_dffe31_wo <= infinity_magnitude_sub_dffe31;
infinity_magnitude_sub_dffe32_wi <= infinity_magnitude_sub_dffe31_wo;
infinity_magnitude_sub_dffe32_wo <= infinity_magnitude_sub_dffe32_wi;
infinity_magnitude_sub_dffe33_wi <= infinity_magnitude_sub_dffe32_wo;
infinity_magnitude_sub_dffe33_wo <= infinity_magnitude_sub_dffe33_wi;
infinity_magnitude_sub_dffe3_wi <= infinity_magnitude_sub_dffe33_wo;
infinity_magnitude_sub_dffe3_wo <= infinity_magnitude_sub_dffe3;
infinity_magnitude_sub_dffe41_wi <= infinity_magnitude_sub_dffe42_wo;
infinity_magnitude_sub_dffe41_wo <= infinity_magnitude_sub_dffe41;
infinity_magnitude_sub_dffe42_wi <= infinity_magnitude_sub_dffe3_wo;
infinity_magnitude_sub_dffe42_wo <= infinity_magnitude_sub_dffe42_wi;
infinity_magnitude_sub_dffe4_wi <= infinity_magnitude_sub_dffe41_wo;
infinity_magnitude_sub_dffe4_wo <= infinity_magnitude_sub_dffe4;
input_dataa_denormal_dffe11_wi <= input_dataa_denormal_w;
input_dataa_denormal_dffe11_wo <= input_dataa_denormal_dffe11_wi;
input_dataa_denormal_w <= ((NOT exp_a_not_zero_w(7)) AND man_a_not_zero_w(22));
input_dataa_infinite_dffe11_wi <= input_dataa_infinite_w;
input_dataa_infinite_dffe11_wo <= input_dataa_infinite_dffe11_wi;
input_dataa_infinite_dffe12_wi <= input_dataa_infinite_dffe11_wo;
input_dataa_infinite_dffe12_wo <= input_dataa_infinite_dffe12;
input_dataa_infinite_dffe13_wi <= input_dataa_infinite_dffe12_wo;
input_dataa_infinite_dffe13_wo <= input_dataa_infinite_dffe13;
input_dataa_infinite_dffe14_wi <= input_dataa_infinite_dffe13_wo;
input_dataa_infinite_dffe14_wo <= input_dataa_infinite_dffe14;
input_dataa_infinite_dffe15_wi <= input_dataa_infinite_dffe14_wo;
input_dataa_infinite_dffe15_wo <= input_dataa_infinite_dffe15;
input_dataa_infinite_w <= wire_w_lg_w_exp_a_all_one_w_range84w220w(0);
input_dataa_nan_dffe11_wi <= input_dataa_nan_w;
input_dataa_nan_dffe11_wo <= input_dataa_nan_dffe11_wi;
input_dataa_nan_dffe12_wi <= input_dataa_nan_dffe11_wo;
input_dataa_nan_dffe12_wo <= input_dataa_nan_dffe12;
input_dataa_nan_w <= (exp_a_all_one_w(7) AND man_a_not_zero_w(22));
input_dataa_zero_dffe11_wi <= input_dataa_zero_w;
input_dataa_zero_dffe11_wo <= input_dataa_zero_dffe11_wi;
input_dataa_zero_w <= ((NOT exp_a_not_zero_w(7)) AND wire_w_lg_w_man_a_not_zero_w_range215w219w(0));
input_datab_denormal_dffe11_wi <= input_datab_denormal_w;
input_datab_denormal_dffe11_wo <= input_datab_denormal_dffe11_wi;
input_datab_denormal_w <= ((NOT exp_b_not_zero_w(7)) AND man_b_not_zero_w(22));
input_datab_infinite_dffe11_wi <= input_datab_infinite_w;
input_datab_infinite_dffe11_wo <= input_datab_infinite_dffe11_wi;
input_datab_infinite_dffe12_wi <= input_datab_infinite_dffe11_wo;
input_datab_infinite_dffe12_wo <= input_datab_infinite_dffe12;
input_datab_infinite_dffe13_wi <= input_datab_infinite_dffe12_wo;
input_datab_infinite_dffe13_wo <= input_datab_infinite_dffe13;
input_datab_infinite_dffe14_wi <= input_datab_infinite_dffe13_wo;
input_datab_infinite_dffe14_wo <= input_datab_infinite_dffe14;
input_datab_infinite_dffe15_wi <= input_datab_infinite_dffe14_wo;
input_datab_infinite_dffe15_wo <= input_datab_infinite_dffe15;
input_datab_infinite_w <= wire_w_lg_w_exp_b_all_one_w_range86w226w(0);
input_datab_nan_dffe11_wi <= input_datab_nan_w;
input_datab_nan_dffe11_wo <= input_datab_nan_dffe11_wi;
input_datab_nan_dffe12_wi <= input_datab_nan_dffe11_wo;
input_datab_nan_dffe12_wo <= input_datab_nan_dffe12;
input_datab_nan_w <= (exp_b_all_one_w(7) AND man_b_not_zero_w(22));
input_datab_zero_dffe11_wi <= input_datab_zero_w;
input_datab_zero_dffe11_wo <= input_datab_zero_dffe11_wi;
input_datab_zero_w <= ((NOT exp_b_not_zero_w(7)) AND wire_w_lg_w_man_b_not_zero_w_range218w225w(0));
input_is_infinite_dffe1_wi <= (input_dataa_infinite_dffe15_wo OR input_datab_infinite_dffe15_wo);
input_is_infinite_dffe1_wo <= input_is_infinite_dffe1;
input_is_infinite_dffe21_wi <= input_is_infinite_dffe27_wo;
input_is_infinite_dffe21_wo <= input_is_infinite_dffe21;
input_is_infinite_dffe22_wi <= input_is_infinite_dffe2_wo;
input_is_infinite_dffe22_wo <= input_is_infinite_dffe22_wi;
input_is_infinite_dffe23_wi <= input_is_infinite_dffe21_wo;
input_is_infinite_dffe23_wo <= input_is_infinite_dffe23;
input_is_infinite_dffe25_wi <= input_is_infinite_dffe1_wo;
input_is_infinite_dffe25_wo <= input_is_infinite_dffe25_wi;
input_is_infinite_dffe26_wi <= input_is_infinite_dffe23_wo;
input_is_infinite_dffe26_wo <= input_is_infinite_dffe26_wi;
input_is_infinite_dffe27_wi <= input_is_infinite_dffe22_wo;
input_is_infinite_dffe27_wo <= input_is_infinite_dffe27;
input_is_infinite_dffe2_wi <= input_is_infinite_dffe25_wo;
input_is_infinite_dffe2_wo <= input_is_infinite_dffe2;
input_is_infinite_dffe31_wi <= input_is_infinite_dffe26_wo;
input_is_infinite_dffe31_wo <= input_is_infinite_dffe31;
input_is_infinite_dffe32_wi <= input_is_infinite_dffe31_wo;
input_is_infinite_dffe32_wo <= input_is_infinite_dffe32_wi;
input_is_infinite_dffe33_wi <= input_is_infinite_dffe32_wo;
input_is_infinite_dffe33_wo <= input_is_infinite_dffe33_wi;
input_is_infinite_dffe3_wi <= input_is_infinite_dffe33_wo;
input_is_infinite_dffe3_wo <= input_is_infinite_dffe3;
input_is_infinite_dffe41_wi <= input_is_infinite_dffe42_wo;
input_is_infinite_dffe41_wo <= input_is_infinite_dffe41;
input_is_infinite_dffe42_wi <= input_is_infinite_dffe3_wo;
input_is_infinite_dffe42_wo <= input_is_infinite_dffe42_wi;
input_is_infinite_dffe4_wi <= input_is_infinite_dffe41_wo;
input_is_infinite_dffe4_wo <= input_is_infinite_dffe4;
input_is_nan_dffe13_wi <= (input_dataa_nan_dffe12_wo OR input_datab_nan_dffe12_wo);
input_is_nan_dffe13_wo <= input_is_nan_dffe13;
input_is_nan_dffe14_wi <= input_is_nan_dffe13_wo;
input_is_nan_dffe14_wo <= input_is_nan_dffe14;
input_is_nan_dffe15_wi <= input_is_nan_dffe14_wo;
input_is_nan_dffe15_wo <= input_is_nan_dffe15;
input_is_nan_dffe1_wi <= input_is_nan_dffe15_wo;
input_is_nan_dffe1_wo <= input_is_nan_dffe1;
input_is_nan_dffe21_wi <= input_is_nan_dffe27_wo;
input_is_nan_dffe21_wo <= input_is_nan_dffe21;
input_is_nan_dffe22_wi <= input_is_nan_dffe2_wo;
input_is_nan_dffe22_wo <= input_is_nan_dffe22_wi;
input_is_nan_dffe23_wi <= input_is_nan_dffe21_wo;
input_is_nan_dffe23_wo <= input_is_nan_dffe23;
input_is_nan_dffe25_wi <= input_is_nan_dffe1_wo;
input_is_nan_dffe25_wo <= input_is_nan_dffe25_wi;
input_is_nan_dffe26_wi <= input_is_nan_dffe23_wo;
input_is_nan_dffe26_wo <= input_is_nan_dffe26_wi;
input_is_nan_dffe27_wi <= input_is_nan_dffe22_wo;
input_is_nan_dffe27_wo <= input_is_nan_dffe27;
input_is_nan_dffe2_wi <= input_is_nan_dffe25_wo;
input_is_nan_dffe2_wo <= input_is_nan_dffe2;
input_is_nan_dffe31_wi <= input_is_nan_dffe26_wo;
input_is_nan_dffe31_wo <= input_is_nan_dffe31;
input_is_nan_dffe32_wi <= input_is_nan_dffe31_wo;
input_is_nan_dffe32_wo <= input_is_nan_dffe32_wi;
input_is_nan_dffe33_wi <= input_is_nan_dffe32_wo;
input_is_nan_dffe33_wo <= input_is_nan_dffe33_wi;
input_is_nan_dffe3_wi <= input_is_nan_dffe33_wo;
input_is_nan_dffe3_wo <= input_is_nan_dffe3;
input_is_nan_dffe41_wi <= input_is_nan_dffe42_wo;
input_is_nan_dffe41_wo <= input_is_nan_dffe41;
input_is_nan_dffe42_wi <= input_is_nan_dffe3_wo;
input_is_nan_dffe42_wo <= input_is_nan_dffe42_wi;
input_is_nan_dffe4_wi <= input_is_nan_dffe41_wo;
input_is_nan_dffe4_wo <= input_is_nan_dffe4;
man_2comp_res_dataa_w <= ( pos_sign_bit_ext & datab_man_dffe1_wo);
man_2comp_res_datab_w <= ( pos_sign_bit_ext & dataa_man_dffe1_wo);
man_2comp_res_w <= ( wire_man_2comp_res_lower_w_lg_w_lg_w_lg_cout367w368w369w & wire_man_2comp_res_lower_result);
man_a_not_zero_w <= ( wire_w_lg_w_dataa_range213w214w & wire_w_lg_w_dataa_range207w208w & wire_w_lg_w_dataa_range201w202w & wire_w_lg_w_dataa_range195w196w & wire_w_lg_w_dataa_range189w190w & wire_w_lg_w_dataa_range183w184w & wire_w_lg_w_dataa_range177w178w & wire_w_lg_w_dataa_range171w172w & wire_w_lg_w_dataa_range165w166w & wire_w_lg_w_dataa_range159w160w & wire_w_lg_w_dataa_range153w154w & wire_w_lg_w_dataa_range147w148w & wire_w_lg_w_dataa_range141w142w & wire_w_lg_w_dataa_range135w136w & wire_w_lg_w_dataa_range129w130w & wire_w_lg_w_dataa_range123w124w & wire_w_lg_w_dataa_range117w118w & wire_w_lg_w_dataa_range111w112w & wire_w_lg_w_dataa_range105w106w & wire_w_lg_w_dataa_range99w100w & wire_w_lg_w_dataa_range93w94w & wire_w_lg_w_dataa_range87w88w & dataa(0));
man_add_sub_dataa_w <= ( pos_sign_bit_ext & dataa_man_dffe1_wo);
man_add_sub_datab_w <= ( pos_sign_bit_ext & datab_man_dffe1_wo);
man_add_sub_res_mag_dffe21_wi <= man_res_mag_w2;
man_add_sub_res_mag_dffe21_wo <= man_add_sub_res_mag_dffe21;
man_add_sub_res_mag_dffe23_wi <= man_add_sub_res_mag_dffe21_wo;
man_add_sub_res_mag_dffe23_wo <= man_add_sub_res_mag_dffe23;
man_add_sub_res_mag_dffe26_wi <= man_add_sub_res_mag_dffe23_wo;
man_add_sub_res_mag_dffe26_wo <= man_add_sub_res_mag_dffe26_wi;
man_add_sub_res_mag_dffe27_wi <= man_add_sub_res_mag_w2;
man_add_sub_res_mag_dffe27_wo <= man_add_sub_res_mag_dffe27;
man_add_sub_res_mag_w2 <= (wire_w_lg_w_man_add_sub_w_range372w379w OR wire_w_lg_w_lg_w_man_add_sub_w_range372w375w378w);
man_add_sub_res_sign_dffe21_wo <= man_add_sub_res_sign_dffe21;
man_add_sub_res_sign_dffe23_wi <= man_add_sub_res_sign_dffe21_wo;
man_add_sub_res_sign_dffe23_wo <= man_add_sub_res_sign_dffe23;
man_add_sub_res_sign_dffe26_wi <= man_add_sub_res_sign_dffe23_wo;
man_add_sub_res_sign_dffe26_wo <= man_add_sub_res_sign_dffe26_wi;
man_add_sub_res_sign_dffe27_wi <= man_add_sub_res_sign_w2;
man_add_sub_res_sign_dffe27_wo <= man_add_sub_res_sign_dffe27;
man_add_sub_res_sign_w2 <= (wire_w_lg_need_complement_dffe22_wo376w(0) OR (wire_w_lg_need_complement_dffe22_wo373w(0) AND man_add_sub_w(27)));
man_add_sub_w <= ( wire_man_add_sub_lower_w_lg_w_lg_w_lg_cout354w355w356w & wire_man_add_sub_lower_result);
man_all_zeros_w <= (OTHERS => '0');
man_b_not_zero_w <= ( wire_w_lg_w_datab_range216w217w & wire_w_lg_w_datab_range210w211w & wire_w_lg_w_datab_range204w205w & wire_w_lg_w_datab_range198w199w & wire_w_lg_w_datab_range192w193w & wire_w_lg_w_datab_range186w187w & wire_w_lg_w_datab_range180w181w & wire_w_lg_w_datab_range174w175w & wire_w_lg_w_datab_range168w169w & wire_w_lg_w_datab_range162w163w & wire_w_lg_w_datab_range156w157w & wire_w_lg_w_datab_range150w151w & wire_w_lg_w_datab_range144w145w & wire_w_lg_w_datab_range138w139w & wire_w_lg_w_datab_range132w133w & wire_w_lg_w_datab_range126w127w & wire_w_lg_w_datab_range120w121w & wire_w_lg_w_datab_range114w115w & wire_w_lg_w_datab_range108w109w & wire_w_lg_w_datab_range102w103w & wire_w_lg_w_datab_range96w97w & wire_w_lg_w_datab_range90w91w & datab(0));
man_dffe31_wo <= man_dffe31;
man_intermediate_res_w <= ( "00" & man_res_w3);
man_leading_zeros_cnt_w <= man_leading_zeros_dffe31_wo;
man_leading_zeros_dffe31_wi <= (NOT wire_leading_zeroes_cnt_q);
man_leading_zeros_dffe31_wo <= man_leading_zeros_dffe31;
man_nan_w <= "10000000000000000000000";
man_out_dffe5_wi <= (wire_w_lg_force_nan_w652w OR wire_w_lg_w_lg_force_nan_w630w651w);
man_out_dffe5_wo <= man_out_dffe5;
man_res_dffe4_wi <= man_rounded_res_w;
man_res_dffe4_wo <= man_res_dffe4;
man_res_is_not_zero_dffe31_wi <= man_res_not_zero_dffe26_wo;
man_res_is_not_zero_dffe31_wo <= man_res_is_not_zero_dffe31;
man_res_is_not_zero_dffe32_wi <= man_res_is_not_zero_dffe31_wo;
man_res_is_not_zero_dffe32_wo <= man_res_is_not_zero_dffe32_wi;
man_res_is_not_zero_dffe33_wi <= man_res_is_not_zero_dffe32_wo;
man_res_is_not_zero_dffe33_wo <= man_res_is_not_zero_dffe33_wi;
man_res_is_not_zero_dffe3_wi <= man_res_is_not_zero_dffe33_wo;
man_res_is_not_zero_dffe3_wo <= man_res_is_not_zero_dffe3;
man_res_is_not_zero_dffe41_wi <= man_res_is_not_zero_dffe42_wo;
man_res_is_not_zero_dffe41_wo <= man_res_is_not_zero_dffe41;
man_res_is_not_zero_dffe42_wi <= man_res_is_not_zero_dffe3_wo;
man_res_is_not_zero_dffe42_wo <= man_res_is_not_zero_dffe42_wi;
man_res_is_not_zero_dffe4_wi <= man_res_is_not_zero_dffe41_wo;
man_res_is_not_zero_dffe4_wo <= man_res_is_not_zero_dffe4;
man_res_mag_w2 <= (wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w414w OR wire_w412w);
man_res_not_zero_dffe23_wi <= man_res_not_zero_w2(24);
man_res_not_zero_dffe23_wo <= man_res_not_zero_dffe23;
man_res_not_zero_dffe26_wi <= man_res_not_zero_dffe23_wo;
man_res_not_zero_dffe26_wo <= man_res_not_zero_dffe26_wi;
man_res_not_zero_w2 <= ( wire_w_lg_w_man_res_not_zero_w2_range487w489w & wire_w_lg_w_man_res_not_zero_w2_range484w486w & wire_w_lg_w_man_res_not_zero_w2_range481w483w & wire_w_lg_w_man_res_not_zero_w2_range478w480w & wire_w_lg_w_man_res_not_zero_w2_range475w477w & wire_w_lg_w_man_res_not_zero_w2_range472w474w & wire_w_lg_w_man_res_not_zero_w2_range469w471w & wire_w_lg_w_man_res_not_zero_w2_range466w468w & wire_w_lg_w_man_res_not_zero_w2_range463w465w & wire_w_lg_w_man_res_not_zero_w2_range460w462w & wire_w_lg_w_man_res_not_zero_w2_range457w459w & wire_w_lg_w_man_res_not_zero_w2_range454w456w & wire_w_lg_w_man_res_not_zero_w2_range451w453w & wire_w_lg_w_man_res_not_zero_w2_range448w450w & wire_w_lg_w_man_res_not_zero_w2_range445w447w & wire_w_lg_w_man_res_not_zero_w2_range442w444w & wire_w_lg_w_man_res_not_zero_w2_range439w441w & wire_w_lg_w_man_res_not_zero_w2_range436w438w & wire_w_lg_w_man_res_not_zero_w2_range433w435w & wire_w_lg_w_man_res_not_zero_w2_range430w432w & wire_w_lg_w_man_res_not_zero_w2_range427w429w & wire_w_lg_w_man_res_not_zero_w2_range424w426w & wire_w_lg_w_man_res_not_zero_w2_range421w423w & wire_w_lg_w_man_res_not_zero_w2_range417w420w & man_add_sub_res_mag_dffe21_wo(1));
man_res_rounding_add_sub_datab_w <= ( "0000000000000000000000000" & man_rounding_add_value_w);
man_res_rounding_add_sub_w <= man_res_rounding_add_sub_result_reg;
man_res_w3 <= wire_lbarrel_shift_result(25 DOWNTO 2);
man_rounded_res_w <= (wire_w_lg_w_man_res_rounding_add_sub_w_range585w589w OR wire_w587w);
man_rounding_add_value_w <= (round_bit_dffe3_wo AND (sticky_bit_dffe3_wo OR guard_bit_dffe3_wo));
man_smaller_dffe13_wi <= man_smaller_w;
man_smaller_dffe13_wo <= man_smaller_dffe13;
man_smaller_w <= (wire_w_lg_exp_amb_mux_w280w OR wire_w_lg_w_lg_exp_amb_mux_w276w279w);
need_complement_dffe22_wi <= need_complement_dffe2_wo;
need_complement_dffe22_wo <= need_complement_dffe22_wi;
need_complement_dffe2_wi <= dataa_sign_dffe25_wo;
need_complement_dffe2_wo <= need_complement_dffe2;
pos_sign_bit_ext <= (OTHERS => '0');
priority_encoder_1pads_w <= (OTHERS => '1');
result <= ( sign_out_dffe5_wo & exp_out_dffe5_wo & man_out_dffe5_wo);
round_bit_dffe21_wi <= round_bit_w;
round_bit_dffe21_wo <= round_bit_dffe21;
round_bit_dffe23_wi <= round_bit_dffe21_wo;
round_bit_dffe23_wo <= round_bit_dffe23;
round_bit_dffe26_wi <= round_bit_dffe23_wo;
round_bit_dffe26_wo <= round_bit_dffe26_wi;
round_bit_dffe31_wi <= round_bit_dffe26_wo;
round_bit_dffe31_wo <= round_bit_dffe31;
round_bit_dffe32_wi <= round_bit_dffe31_wo;
round_bit_dffe32_wo <= round_bit_dffe32_wi;
round_bit_dffe33_wi <= round_bit_dffe32_wo;
round_bit_dffe33_wo <= round_bit_dffe33_wi;
round_bit_dffe3_wi <= round_bit_dffe33_wo;
round_bit_dffe3_wo <= round_bit_dffe3;
round_bit_w <= ((((wire_w397w(0) AND man_add_sub_res_mag_dffe27_wo(0)) OR ((wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) AND man_add_sub_res_mag_dffe27_wo(25)) AND man_add_sub_res_mag_dffe27_wo(1))) OR (wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w391w(0) AND man_add_sub_res_mag_dffe27_wo(2))) OR ((man_add_sub_res_mag_dffe27_wo(26) AND man_add_sub_res_mag_dffe27_wo(25)) AND man_add_sub_res_mag_dffe27_wo(2)));
rounded_res_infinity_dffe4_wi <= exp_rounded_res_infinity_w;
rounded_res_infinity_dffe4_wo <= rounded_res_infinity_dffe4;
rshift_distance_dffe13_wi <= rshift_distance_w;
rshift_distance_dffe13_wo <= rshift_distance_dffe13;
rshift_distance_dffe14_wi <= rshift_distance_dffe13_wo;
rshift_distance_dffe14_wo <= rshift_distance_dffe14;
rshift_distance_dffe15_wi <= rshift_distance_dffe14_wo;
rshift_distance_dffe15_wo <= rshift_distance_dffe15;
rshift_distance_w <= (wire_w_lg_w_exp_diff_abs_exceed_max_w_range290w294w OR wire_w293w);
sign_dffe31_wi <= ((man_res_not_zero_dffe26_wo AND man_add_sub_res_sign_dffe26_wo) OR wire_w_lg_w_lg_man_res_not_zero_dffe26_wo503w504w(0));
sign_dffe31_wo <= sign_dffe31;
sign_dffe32_wi <= sign_dffe31_wo;
sign_dffe32_wo <= sign_dffe32_wi;
sign_dffe33_wi <= sign_dffe32_wo;
sign_dffe33_wo <= sign_dffe33_wi;
sign_out_dffe5_wi <= (wire_w_lg_force_nan_w630w(0) AND ((force_infinity_w AND infinite_output_sign_dffe4_wo) OR wire_w_lg_w_lg_force_infinity_w629w654w(0)));
sign_out_dffe5_wo <= sign_out_dffe5;
sign_res_dffe3_wi <= sign_dffe33_wo;
sign_res_dffe3_wo <= sign_res_dffe3;
sign_res_dffe41_wi <= sign_res_dffe42_wo;
sign_res_dffe41_wo <= sign_res_dffe41;
sign_res_dffe42_wi <= sign_res_dffe3_wo;
sign_res_dffe42_wo <= sign_res_dffe42_wi;
sign_res_dffe4_wi <= sign_res_dffe41_wo;
sign_res_dffe4_wo <= sign_res_dffe4;
sticky_bit_cnt_dataa_w <= ( "0" & rshift_distance_dffe15_wo);
sticky_bit_cnt_datab_w <= ( "0" & wire_trailing_zeros_cnt_q);
sticky_bit_cnt_res_w <= wire_add_sub3_result;
sticky_bit_dffe1_wi <= wire_trailing_zeros_limit_comparator_agb;
sticky_bit_dffe1_wo <= sticky_bit_dffe1;
sticky_bit_dffe21_wi <= sticky_bit_w;
sticky_bit_dffe21_wo <= sticky_bit_dffe21;
sticky_bit_dffe22_wi <= sticky_bit_dffe2_wo;
sticky_bit_dffe22_wo <= sticky_bit_dffe22_wi;
sticky_bit_dffe23_wi <= sticky_bit_dffe21_wo;
sticky_bit_dffe23_wo <= sticky_bit_dffe23;
sticky_bit_dffe25_wi <= sticky_bit_dffe1_wo;
sticky_bit_dffe25_wo <= sticky_bit_dffe25_wi;
sticky_bit_dffe26_wi <= sticky_bit_dffe23_wo;
sticky_bit_dffe26_wo <= sticky_bit_dffe26_wi;
sticky_bit_dffe27_wi <= sticky_bit_dffe22_wo;
sticky_bit_dffe27_wo <= sticky_bit_dffe27;
sticky_bit_dffe2_wi <= sticky_bit_dffe25_wo;
sticky_bit_dffe2_wo <= sticky_bit_dffe2;
sticky_bit_dffe31_wi <= sticky_bit_dffe26_wo;
sticky_bit_dffe31_wo <= sticky_bit_dffe31;
sticky_bit_dffe32_wi <= sticky_bit_dffe31_wo;
sticky_bit_dffe32_wo <= sticky_bit_dffe32_wi;
sticky_bit_dffe33_wi <= sticky_bit_dffe32_wo;
sticky_bit_dffe33_wo <= sticky_bit_dffe33_wi;
sticky_bit_dffe3_wi <= sticky_bit_dffe33_wo;
sticky_bit_dffe3_wo <= sticky_bit_dffe3;
sticky_bit_w <= (((wire_w_lg_w397w407w(0) OR ((wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) AND man_add_sub_res_mag_dffe27_wo(25)) AND wire_w_lg_sticky_bit_dffe27_wo402w(0))) OR (wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w391w(0) AND (wire_w_lg_sticky_bit_dffe27_wo402w(0) OR man_add_sub_res_mag_dffe27_wo(1)))) OR ((man_add_sub_res_mag_dffe27_wo(26) AND man_add_sub_res_mag_dffe27_wo(25)) AND (wire_w_lg_sticky_bit_dffe27_wo402w(0) OR man_add_sub_res_mag_dffe27_wo(1))));
trailing_zeros_limit_w <= "000010";
zero_man_sign_dffe21_wi <= zero_man_sign_dffe27_wo;
zero_man_sign_dffe21_wo <= zero_man_sign_dffe21;
zero_man_sign_dffe22_wi <= zero_man_sign_dffe2_wo;
zero_man_sign_dffe22_wo <= zero_man_sign_dffe22_wi;
zero_man_sign_dffe23_wi <= zero_man_sign_dffe21_wo;
zero_man_sign_dffe23_wo <= zero_man_sign_dffe23;
zero_man_sign_dffe26_wi <= zero_man_sign_dffe23_wo;
zero_man_sign_dffe26_wo <= zero_man_sign_dffe26_wi;
zero_man_sign_dffe27_wi <= zero_man_sign_dffe22_wo;
zero_man_sign_dffe27_wo <= zero_man_sign_dffe27;
zero_man_sign_dffe2_wi <= (dataa_sign_dffe25_wo AND add_sub_dffe25_wo);
zero_man_sign_dffe2_wo <= zero_man_sign_dffe2;
wire_w_aligned_dataa_exp_dffe15_wo_range315w <= aligned_dataa_exp_dffe15_wo(7 DOWNTO 0);
wire_w_aligned_datab_exp_dffe15_wo_range313w <= aligned_datab_exp_dffe15_wo(7 DOWNTO 0);
wire_w_dataa_range141w(0) <= dataa(10);
wire_w_dataa_range147w(0) <= dataa(11);
wire_w_dataa_range153w(0) <= dataa(12);
wire_w_dataa_range159w(0) <= dataa(13);
wire_w_dataa_range165w(0) <= dataa(14);
wire_w_dataa_range171w(0) <= dataa(15);
wire_w_dataa_range177w(0) <= dataa(16);
wire_w_dataa_range183w(0) <= dataa(17);
wire_w_dataa_range189w(0) <= dataa(18);
wire_w_dataa_range195w(0) <= dataa(19);
wire_w_dataa_range87w(0) <= dataa(1);
wire_w_dataa_range201w(0) <= dataa(20);
wire_w_dataa_range207w(0) <= dataa(21);
wire_w_dataa_range213w(0) <= dataa(22);
wire_w_dataa_range17w(0) <= dataa(24);
wire_w_dataa_range27w(0) <= dataa(25);
wire_w_dataa_range37w(0) <= dataa(26);
wire_w_dataa_range47w(0) <= dataa(27);
wire_w_dataa_range57w(0) <= dataa(28);
wire_w_dataa_range67w(0) <= dataa(29);
wire_w_dataa_range93w(0) <= dataa(2);
wire_w_dataa_range77w(0) <= dataa(30);
wire_w_dataa_range99w(0) <= dataa(3);
wire_w_dataa_range105w(0) <= dataa(4);
wire_w_dataa_range111w(0) <= dataa(5);
wire_w_dataa_range117w(0) <= dataa(6);
wire_w_dataa_range123w(0) <= dataa(7);
wire_w_dataa_range129w(0) <= dataa(8);
wire_w_dataa_range135w(0) <= dataa(9);
wire_w_dataa_dffe11_wo_range242w <= dataa_dffe11_wo(22 DOWNTO 0);
wire_w_dataa_dffe11_wo_range232w <= dataa_dffe11_wo(30 DOWNTO 23);
wire_w_datab_range144w(0) <= datab(10);
wire_w_datab_range150w(0) <= datab(11);
wire_w_datab_range156w(0) <= datab(12);
wire_w_datab_range162w(0) <= datab(13);
wire_w_datab_range168w(0) <= datab(14);
wire_w_datab_range174w(0) <= datab(15);
wire_w_datab_range180w(0) <= datab(16);
wire_w_datab_range186w(0) <= datab(17);
wire_w_datab_range192w(0) <= datab(18);
wire_w_datab_range198w(0) <= datab(19);
wire_w_datab_range90w(0) <= datab(1);
wire_w_datab_range204w(0) <= datab(20);
wire_w_datab_range210w(0) <= datab(21);
wire_w_datab_range216w(0) <= datab(22);
wire_w_datab_range20w(0) <= datab(24);
wire_w_datab_range30w(0) <= datab(25);
wire_w_datab_range40w(0) <= datab(26);
wire_w_datab_range50w(0) <= datab(27);
wire_w_datab_range60w(0) <= datab(28);
wire_w_datab_range70w(0) <= datab(29);
wire_w_datab_range96w(0) <= datab(2);
wire_w_datab_range80w(0) <= datab(30);
wire_w_datab_range102w(0) <= datab(3);
wire_w_datab_range108w(0) <= datab(4);
wire_w_datab_range114w(0) <= datab(5);
wire_w_datab_range120w(0) <= datab(6);
wire_w_datab_range126w(0) <= datab(7);
wire_w_datab_range132w(0) <= datab(8);
wire_w_datab_range138w(0) <= datab(9);
wire_w_datab_dffe11_wo_range261w <= datab_dffe11_wo(22 DOWNTO 0);
wire_w_datab_dffe11_wo_range251w <= datab_dffe11_wo(30 DOWNTO 23);
wire_w_exp_a_all_one_w_range7w(0) <= exp_a_all_one_w(0);
wire_w_exp_a_all_one_w_range24w(0) <= exp_a_all_one_w(1);
wire_w_exp_a_all_one_w_range34w(0) <= exp_a_all_one_w(2);
wire_w_exp_a_all_one_w_range44w(0) <= exp_a_all_one_w(3);
wire_w_exp_a_all_one_w_range54w(0) <= exp_a_all_one_w(4);
wire_w_exp_a_all_one_w_range64w(0) <= exp_a_all_one_w(5);
wire_w_exp_a_all_one_w_range74w(0) <= exp_a_all_one_w(6);
wire_w_exp_a_all_one_w_range84w(0) <= exp_a_all_one_w(7);
wire_w_exp_a_not_zero_w_range2w(0) <= exp_a_not_zero_w(0);
wire_w_exp_a_not_zero_w_range19w(0) <= exp_a_not_zero_w(1);
wire_w_exp_a_not_zero_w_range29w(0) <= exp_a_not_zero_w(2);
wire_w_exp_a_not_zero_w_range39w(0) <= exp_a_not_zero_w(3);
wire_w_exp_a_not_zero_w_range49w(0) <= exp_a_not_zero_w(4);
wire_w_exp_a_not_zero_w_range59w(0) <= exp_a_not_zero_w(5);
wire_w_exp_a_not_zero_w_range69w(0) <= exp_a_not_zero_w(6);
wire_w_exp_adjustment2_add_sub_w_range518w(0) <= exp_adjustment2_add_sub_w(1);
wire_w_exp_adjustment2_add_sub_w_range521w(0) <= exp_adjustment2_add_sub_w(2);
wire_w_exp_adjustment2_add_sub_w_range524w(0) <= exp_adjustment2_add_sub_w(3);
wire_w_exp_adjustment2_add_sub_w_range527w(0) <= exp_adjustment2_add_sub_w(4);
wire_w_exp_adjustment2_add_sub_w_range530w(0) <= exp_adjustment2_add_sub_w(5);
wire_w_exp_adjustment2_add_sub_w_range533w(0) <= exp_adjustment2_add_sub_w(6);
wire_w_exp_adjustment2_add_sub_w_range557w <= exp_adjustment2_add_sub_w(7 DOWNTO 0);
wire_w_exp_adjustment2_add_sub_w_range536w(0) <= exp_adjustment2_add_sub_w(7);
wire_w_exp_adjustment2_add_sub_w_range511w(0) <= exp_adjustment2_add_sub_w(8);
wire_w_exp_amb_w_range275w <= exp_amb_w(7 DOWNTO 0);
wire_w_exp_b_all_one_w_range9w(0) <= exp_b_all_one_w(0);
wire_w_exp_b_all_one_w_range26w(0) <= exp_b_all_one_w(1);
wire_w_exp_b_all_one_w_range36w(0) <= exp_b_all_one_w(2);
wire_w_exp_b_all_one_w_range46w(0) <= exp_b_all_one_w(3);
wire_w_exp_b_all_one_w_range56w(0) <= exp_b_all_one_w(4);
wire_w_exp_b_all_one_w_range66w(0) <= exp_b_all_one_w(5);
wire_w_exp_b_all_one_w_range76w(0) <= exp_b_all_one_w(6);
wire_w_exp_b_all_one_w_range86w(0) <= exp_b_all_one_w(7);
wire_w_exp_b_not_zero_w_range5w(0) <= exp_b_not_zero_w(0);
wire_w_exp_b_not_zero_w_range22w(0) <= exp_b_not_zero_w(1);
wire_w_exp_b_not_zero_w_range32w(0) <= exp_b_not_zero_w(2);
wire_w_exp_b_not_zero_w_range42w(0) <= exp_b_not_zero_w(3);
wire_w_exp_b_not_zero_w_range52w(0) <= exp_b_not_zero_w(4);
wire_w_exp_b_not_zero_w_range62w(0) <= exp_b_not_zero_w(5);
wire_w_exp_b_not_zero_w_range72w(0) <= exp_b_not_zero_w(6);
wire_w_exp_bma_w_range273w <= exp_bma_w(7 DOWNTO 0);
wire_w_exp_diff_abs_exceed_max_w_range283w(0) <= exp_diff_abs_exceed_max_w(0);
wire_w_exp_diff_abs_exceed_max_w_range287w(0) <= exp_diff_abs_exceed_max_w(1);
wire_w_exp_diff_abs_exceed_max_w_range290w(0) <= exp_diff_abs_exceed_max_w(2);
wire_w_exp_diff_abs_w_range291w <= exp_diff_abs_w(4 DOWNTO 0);
wire_w_exp_diff_abs_w_range285w(0) <= exp_diff_abs_w(6);
wire_w_exp_diff_abs_w_range288w(0) <= exp_diff_abs_w(7);
wire_w_exp_res_max_w_range540w(0) <= exp_res_max_w(0);
wire_w_exp_res_max_w_range543w(0) <= exp_res_max_w(1);
wire_w_exp_res_max_w_range545w(0) <= exp_res_max_w(2);
wire_w_exp_res_max_w_range547w(0) <= exp_res_max_w(3);
wire_w_exp_res_max_w_range549w(0) <= exp_res_max_w(4);
wire_w_exp_res_max_w_range551w(0) <= exp_res_max_w(5);
wire_w_exp_res_max_w_range553w(0) <= exp_res_max_w(6);
wire_w_exp_res_max_w_range555w(0) <= exp_res_max_w(7);
wire_w_exp_res_not_zero_w_range516w(0) <= exp_res_not_zero_w(0);
wire_w_exp_res_not_zero_w_range520w(0) <= exp_res_not_zero_w(1);
wire_w_exp_res_not_zero_w_range523w(0) <= exp_res_not_zero_w(2);
wire_w_exp_res_not_zero_w_range526w(0) <= exp_res_not_zero_w(3);
wire_w_exp_res_not_zero_w_range529w(0) <= exp_res_not_zero_w(4);
wire_w_exp_res_not_zero_w_range532w(0) <= exp_res_not_zero_w(5);
wire_w_exp_res_not_zero_w_range535w(0) <= exp_res_not_zero_w(6);
wire_w_exp_res_not_zero_w_range538w(0) <= exp_res_not_zero_w(7);
wire_w_exp_rounded_res_max_w_range601w(0) <= exp_rounded_res_max_w(0);
wire_w_exp_rounded_res_max_w_range605w(0) <= exp_rounded_res_max_w(1);
wire_w_exp_rounded_res_max_w_range608w(0) <= exp_rounded_res_max_w(2);
wire_w_exp_rounded_res_max_w_range611w(0) <= exp_rounded_res_max_w(3);
wire_w_exp_rounded_res_max_w_range614w(0) <= exp_rounded_res_max_w(4);
wire_w_exp_rounded_res_max_w_range617w(0) <= exp_rounded_res_max_w(5);
wire_w_exp_rounded_res_max_w_range620w(0) <= exp_rounded_res_max_w(6);
wire_w_exp_rounded_res_w_range603w(0) <= exp_rounded_res_w(1);
wire_w_exp_rounded_res_w_range606w(0) <= exp_rounded_res_w(2);
wire_w_exp_rounded_res_w_range609w(0) <= exp_rounded_res_w(3);
wire_w_exp_rounded_res_w_range612w(0) <= exp_rounded_res_w(4);
wire_w_exp_rounded_res_w_range615w(0) <= exp_rounded_res_w(5);
wire_w_exp_rounded_res_w_range618w(0) <= exp_rounded_res_w(6);
wire_w_exp_rounded_res_w_range621w(0) <= exp_rounded_res_w(7);
wire_w_man_a_not_zero_w_range12w(0) <= man_a_not_zero_w(0);
wire_w_man_a_not_zero_w_range143w(0) <= man_a_not_zero_w(10);
wire_w_man_a_not_zero_w_range149w(0) <= man_a_not_zero_w(11);
wire_w_man_a_not_zero_w_range155w(0) <= man_a_not_zero_w(12);
wire_w_man_a_not_zero_w_range161w(0) <= man_a_not_zero_w(13);
wire_w_man_a_not_zero_w_range167w(0) <= man_a_not_zero_w(14);
wire_w_man_a_not_zero_w_range173w(0) <= man_a_not_zero_w(15);
wire_w_man_a_not_zero_w_range179w(0) <= man_a_not_zero_w(16);
wire_w_man_a_not_zero_w_range185w(0) <= man_a_not_zero_w(17);
wire_w_man_a_not_zero_w_range191w(0) <= man_a_not_zero_w(18);
wire_w_man_a_not_zero_w_range197w(0) <= man_a_not_zero_w(19);
wire_w_man_a_not_zero_w_range89w(0) <= man_a_not_zero_w(1);
wire_w_man_a_not_zero_w_range203w(0) <= man_a_not_zero_w(20);
wire_w_man_a_not_zero_w_range209w(0) <= man_a_not_zero_w(21);
wire_w_man_a_not_zero_w_range215w(0) <= man_a_not_zero_w(22);
wire_w_man_a_not_zero_w_range95w(0) <= man_a_not_zero_w(2);
wire_w_man_a_not_zero_w_range101w(0) <= man_a_not_zero_w(3);
wire_w_man_a_not_zero_w_range107w(0) <= man_a_not_zero_w(4);
wire_w_man_a_not_zero_w_range113w(0) <= man_a_not_zero_w(5);
wire_w_man_a_not_zero_w_range119w(0) <= man_a_not_zero_w(6);
wire_w_man_a_not_zero_w_range125w(0) <= man_a_not_zero_w(7);
wire_w_man_a_not_zero_w_range131w(0) <= man_a_not_zero_w(8);
wire_w_man_a_not_zero_w_range137w(0) <= man_a_not_zero_w(9);
wire_w_man_add_sub_res_mag_dffe21_wo_range443w(0) <= man_add_sub_res_mag_dffe21_wo(10);
wire_w_man_add_sub_res_mag_dffe21_wo_range446w(0) <= man_add_sub_res_mag_dffe21_wo(11);
wire_w_man_add_sub_res_mag_dffe21_wo_range449w(0) <= man_add_sub_res_mag_dffe21_wo(12);
wire_w_man_add_sub_res_mag_dffe21_wo_range452w(0) <= man_add_sub_res_mag_dffe21_wo(13);
wire_w_man_add_sub_res_mag_dffe21_wo_range455w(0) <= man_add_sub_res_mag_dffe21_wo(14);
wire_w_man_add_sub_res_mag_dffe21_wo_range458w(0) <= man_add_sub_res_mag_dffe21_wo(15);
wire_w_man_add_sub_res_mag_dffe21_wo_range461w(0) <= man_add_sub_res_mag_dffe21_wo(16);
wire_w_man_add_sub_res_mag_dffe21_wo_range464w(0) <= man_add_sub_res_mag_dffe21_wo(17);
wire_w_man_add_sub_res_mag_dffe21_wo_range467w(0) <= man_add_sub_res_mag_dffe21_wo(18);
wire_w_man_add_sub_res_mag_dffe21_wo_range470w(0) <= man_add_sub_res_mag_dffe21_wo(19);
wire_w_man_add_sub_res_mag_dffe21_wo_range473w(0) <= man_add_sub_res_mag_dffe21_wo(20);
wire_w_man_add_sub_res_mag_dffe21_wo_range476w(0) <= man_add_sub_res_mag_dffe21_wo(21);
wire_w_man_add_sub_res_mag_dffe21_wo_range479w(0) <= man_add_sub_res_mag_dffe21_wo(22);
wire_w_man_add_sub_res_mag_dffe21_wo_range482w(0) <= man_add_sub_res_mag_dffe21_wo(23);
wire_w_man_add_sub_res_mag_dffe21_wo_range485w(0) <= man_add_sub_res_mag_dffe21_wo(24);
wire_w_man_add_sub_res_mag_dffe21_wo_range488w(0) <= man_add_sub_res_mag_dffe21_wo(25);
wire_w_man_add_sub_res_mag_dffe21_wo_range419w(0) <= man_add_sub_res_mag_dffe21_wo(2);
wire_w_man_add_sub_res_mag_dffe21_wo_range422w(0) <= man_add_sub_res_mag_dffe21_wo(3);
wire_w_man_add_sub_res_mag_dffe21_wo_range425w(0) <= man_add_sub_res_mag_dffe21_wo(4);
wire_w_man_add_sub_res_mag_dffe21_wo_range428w(0) <= man_add_sub_res_mag_dffe21_wo(5);
wire_w_man_add_sub_res_mag_dffe21_wo_range431w(0) <= man_add_sub_res_mag_dffe21_wo(6);
wire_w_man_add_sub_res_mag_dffe21_wo_range434w(0) <= man_add_sub_res_mag_dffe21_wo(7);
wire_w_man_add_sub_res_mag_dffe21_wo_range437w(0) <= man_add_sub_res_mag_dffe21_wo(8);
wire_w_man_add_sub_res_mag_dffe21_wo_range440w(0) <= man_add_sub_res_mag_dffe21_wo(9);
wire_w_man_add_sub_res_mag_dffe27_wo_range396w(0) <= man_add_sub_res_mag_dffe27_wo(0);
wire_w_man_add_sub_res_mag_dffe27_wo_range411w <= man_add_sub_res_mag_dffe27_wo(25 DOWNTO 0);
wire_w_man_add_sub_res_mag_dffe27_wo_range387w(0) <= man_add_sub_res_mag_dffe27_wo(25);
wire_w_man_add_sub_res_mag_dffe27_wo_range413w <= man_add_sub_res_mag_dffe27_wo(26 DOWNTO 1);
wire_w_man_add_sub_res_mag_dffe27_wo_range381w(0) <= man_add_sub_res_mag_dffe27_wo(26);
wire_w_man_add_sub_w_range372w(0) <= man_add_sub_w(27);
wire_w_man_b_not_zero_w_range15w(0) <= man_b_not_zero_w(0);
wire_w_man_b_not_zero_w_range146w(0) <= man_b_not_zero_w(10);
wire_w_man_b_not_zero_w_range152w(0) <= man_b_not_zero_w(11);
wire_w_man_b_not_zero_w_range158w(0) <= man_b_not_zero_w(12);
wire_w_man_b_not_zero_w_range164w(0) <= man_b_not_zero_w(13);
wire_w_man_b_not_zero_w_range170w(0) <= man_b_not_zero_w(14);
wire_w_man_b_not_zero_w_range176w(0) <= man_b_not_zero_w(15);
wire_w_man_b_not_zero_w_range182w(0) <= man_b_not_zero_w(16);
wire_w_man_b_not_zero_w_range188w(0) <= man_b_not_zero_w(17);
wire_w_man_b_not_zero_w_range194w(0) <= man_b_not_zero_w(18);
wire_w_man_b_not_zero_w_range200w(0) <= man_b_not_zero_w(19);
wire_w_man_b_not_zero_w_range92w(0) <= man_b_not_zero_w(1);
wire_w_man_b_not_zero_w_range206w(0) <= man_b_not_zero_w(20);
wire_w_man_b_not_zero_w_range212w(0) <= man_b_not_zero_w(21);
wire_w_man_b_not_zero_w_range218w(0) <= man_b_not_zero_w(22);
wire_w_man_b_not_zero_w_range98w(0) <= man_b_not_zero_w(2);
wire_w_man_b_not_zero_w_range104w(0) <= man_b_not_zero_w(3);
wire_w_man_b_not_zero_w_range110w(0) <= man_b_not_zero_w(4);
wire_w_man_b_not_zero_w_range116w(0) <= man_b_not_zero_w(5);
wire_w_man_b_not_zero_w_range122w(0) <= man_b_not_zero_w(6);
wire_w_man_b_not_zero_w_range128w(0) <= man_b_not_zero_w(7);
wire_w_man_b_not_zero_w_range134w(0) <= man_b_not_zero_w(8);
wire_w_man_b_not_zero_w_range140w(0) <= man_b_not_zero_w(9);
wire_w_man_res_not_zero_w2_range417w(0) <= man_res_not_zero_w2(0);
wire_w_man_res_not_zero_w2_range448w(0) <= man_res_not_zero_w2(10);
wire_w_man_res_not_zero_w2_range451w(0) <= man_res_not_zero_w2(11);
wire_w_man_res_not_zero_w2_range454w(0) <= man_res_not_zero_w2(12);
wire_w_man_res_not_zero_w2_range457w(0) <= man_res_not_zero_w2(13);
wire_w_man_res_not_zero_w2_range460w(0) <= man_res_not_zero_w2(14);
wire_w_man_res_not_zero_w2_range463w(0) <= man_res_not_zero_w2(15);
wire_w_man_res_not_zero_w2_range466w(0) <= man_res_not_zero_w2(16);
wire_w_man_res_not_zero_w2_range469w(0) <= man_res_not_zero_w2(17);
wire_w_man_res_not_zero_w2_range472w(0) <= man_res_not_zero_w2(18);
wire_w_man_res_not_zero_w2_range475w(0) <= man_res_not_zero_w2(19);
wire_w_man_res_not_zero_w2_range421w(0) <= man_res_not_zero_w2(1);
wire_w_man_res_not_zero_w2_range478w(0) <= man_res_not_zero_w2(20);
wire_w_man_res_not_zero_w2_range481w(0) <= man_res_not_zero_w2(21);
wire_w_man_res_not_zero_w2_range484w(0) <= man_res_not_zero_w2(22);
wire_w_man_res_not_zero_w2_range487w(0) <= man_res_not_zero_w2(23);
wire_w_man_res_not_zero_w2_range424w(0) <= man_res_not_zero_w2(2);
wire_w_man_res_not_zero_w2_range427w(0) <= man_res_not_zero_w2(3);
wire_w_man_res_not_zero_w2_range430w(0) <= man_res_not_zero_w2(4);
wire_w_man_res_not_zero_w2_range433w(0) <= man_res_not_zero_w2(5);
wire_w_man_res_not_zero_w2_range436w(0) <= man_res_not_zero_w2(6);
wire_w_man_res_not_zero_w2_range439w(0) <= man_res_not_zero_w2(7);
wire_w_man_res_not_zero_w2_range442w(0) <= man_res_not_zero_w2(8);
wire_w_man_res_not_zero_w2_range445w(0) <= man_res_not_zero_w2(9);
wire_w_man_res_rounding_add_sub_w_range584w <= man_res_rounding_add_sub_w(22 DOWNTO 0);
wire_w_man_res_rounding_add_sub_w_range588w <= man_res_rounding_add_sub_w(23 DOWNTO 1);
wire_w_man_res_rounding_add_sub_w_range585w(0) <= man_res_rounding_add_sub_w(24);
lbarrel_shift : add_flt_stratix5_speed_altbarrel_shift_nud
PORT MAP (
aclr => aclr,
clk_en => clk_en,
clock => clock,
data => man_dffe31_wo,
distance => man_leading_zeros_cnt_w,
result => wire_lbarrel_shift_result
);
wire_rbarrel_shift_data <= ( man_smaller_dffe13_wo & "00");
rbarrel_shift : add_flt_stratix5_speed_altbarrel_shift_u1g
PORT MAP (
aclr => aclr,
clk_en => clk_en,
clock => clock,
data => wire_rbarrel_shift_data,
distance => rshift_distance_dffe13_wo,
result => wire_rbarrel_shift_result
);
wire_leading_zeroes_cnt_data <= ( man_add_sub_res_mag_dffe21_wo(25 DOWNTO 1) & "1" & "000000");
leading_zeroes_cnt : add_flt_stratix5_speed_altpriority_encoder_ou8
PORT MAP (
aclr => aclr,
clk_en => clk_en,
clock => clock,
data => wire_leading_zeroes_cnt_data,
q => wire_leading_zeroes_cnt_q
);
wire_trailing_zeros_cnt_data <= ( "111111111" & man_smaller_dffe13_wo(22 DOWNTO 0));
trailing_zeros_cnt : add_flt_stratix5_speed_altpriority_encoder_dna
PORT MAP (
aclr => aclr,
clk_en => clk_en,
clock => clock,
data => wire_trailing_zeros_cnt_data,
q => wire_trailing_zeros_cnt_q
);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_exp_dffe12 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_exp_dffe12 <= aligned_dataa_exp_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_exp_dffe13 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_exp_dffe13 <= aligned_dataa_exp_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_exp_dffe14 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_exp_dffe14 <= aligned_dataa_exp_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_exp_dffe15 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_exp_dffe15 <= aligned_dataa_exp_dffe15_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_man_dffe12 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_man_dffe12 <= aligned_dataa_man_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_man_dffe13 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_man_dffe13 <= aligned_dataa_man_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_man_dffe14 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_man_dffe14 <= aligned_dataa_man_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_man_dffe15 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_man_dffe15 <= aligned_dataa_man_dffe15_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_sign_dffe12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_sign_dffe12 <= aligned_dataa_sign_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_sign_dffe13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_sign_dffe13 <= aligned_dataa_sign_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_sign_dffe14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_sign_dffe14 <= aligned_dataa_sign_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_sign_dffe15 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_sign_dffe15 <= aligned_dataa_sign_dffe15_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_exp_dffe12 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_exp_dffe12 <= aligned_datab_exp_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_exp_dffe13 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_exp_dffe13 <= aligned_datab_exp_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_exp_dffe14 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_exp_dffe14 <= aligned_datab_exp_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_exp_dffe15 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_exp_dffe15 <= aligned_datab_exp_dffe15_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_man_dffe12 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_man_dffe12 <= aligned_datab_man_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_man_dffe13 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_man_dffe13 <= aligned_datab_man_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_man_dffe14 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_man_dffe14 <= aligned_datab_man_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_man_dffe15 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_man_dffe15 <= aligned_datab_man_dffe15_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_sign_dffe12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_sign_dffe12 <= aligned_datab_sign_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_sign_dffe13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_sign_dffe13 <= aligned_datab_sign_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_sign_dffe14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_sign_dffe14 <= aligned_datab_sign_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_sign_dffe15 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_sign_dffe15 <= aligned_datab_sign_dffe15_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN both_inputs_are_infinite_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN both_inputs_are_infinite_dffe1 <= both_inputs_are_infinite_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN data_exp_dffe1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN data_exp_dffe1 <= data_exp_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN dataa_man_dffe1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN dataa_man_dffe1 <= dataa_man_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN dataa_sign_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN dataa_sign_dffe1 <= dataa_sign_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN datab_man_dffe1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN datab_man_dffe1 <= datab_man_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN datab_sign_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN datab_sign_dffe1 <= datab_sign_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN denormal_res_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN denormal_res_dffe3 <= denormal_res_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN denormal_res_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN denormal_res_dffe4 <= denormal_res_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN denormal_res_dffe41 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN denormal_res_dffe41 <= denormal_res_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_adj_dffe21 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_adj_dffe21 <= exp_adj_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_adj_dffe23 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_adj_dffe23 <= exp_adj_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_amb_mux_dffe13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_amb_mux_dffe13 <= exp_amb_mux_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_amb_mux_dffe14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_amb_mux_dffe14 <= exp_amb_mux_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_amb_mux_dffe15 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_amb_mux_dffe15 <= exp_amb_mux_dffe15_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_intermediate_res_dffe41 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_intermediate_res_dffe41 <= exp_intermediate_res_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_out_dffe5 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_out_dffe5 <= exp_out_dffe5_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe2 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe2 <= exp_res_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe21 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe21 <= exp_res_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe23 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe23 <= exp_res_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe27 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe27 <= exp_res_dffe27_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe3 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe3 <= exp_res_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe4 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe4 <= exp_res_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe1 <= infinite_output_sign_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe2 <= infinite_output_sign_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe21 <= infinite_output_sign_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe23 <= infinite_output_sign_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe27 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe27 <= infinite_output_sign_dffe27_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe3 <= infinite_output_sign_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe31 <= infinite_output_sign_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe4 <= infinite_output_sign_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe41 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe41 <= infinite_output_sign_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_res_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_res_dffe3 <= infinite_res_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_res_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_res_dffe4 <= infinite_res_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_res_dffe41 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_res_dffe41 <= infinite_res_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe2 <= infinity_magnitude_sub_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe21 <= infinity_magnitude_sub_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe23 <= infinity_magnitude_sub_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe27 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe27 <= infinity_magnitude_sub_dffe27_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe3 <= infinity_magnitude_sub_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe31 <= infinity_magnitude_sub_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe4 <= infinity_magnitude_sub_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe41 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe41 <= infinity_magnitude_sub_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_dataa_infinite_dffe12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_dataa_infinite_dffe12 <= input_dataa_infinite_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_dataa_infinite_dffe13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_dataa_infinite_dffe13 <= input_dataa_infinite_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_dataa_infinite_dffe14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_dataa_infinite_dffe14 <= input_dataa_infinite_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_dataa_infinite_dffe15 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_dataa_infinite_dffe15 <= input_dataa_infinite_dffe15_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_dataa_nan_dffe12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_dataa_nan_dffe12 <= input_dataa_nan_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_datab_infinite_dffe12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_datab_infinite_dffe12 <= input_datab_infinite_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_datab_infinite_dffe13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_datab_infinite_dffe13 <= input_datab_infinite_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_datab_infinite_dffe14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_datab_infinite_dffe14 <= input_datab_infinite_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_datab_infinite_dffe15 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_datab_infinite_dffe15 <= input_datab_infinite_dffe15_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_datab_nan_dffe12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_datab_nan_dffe12 <= input_datab_nan_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe1 <= input_is_infinite_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe2 <= input_is_infinite_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe21 <= input_is_infinite_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe23 <= input_is_infinite_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe27 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe27 <= input_is_infinite_dffe27_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe3 <= input_is_infinite_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe31 <= input_is_infinite_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe4 <= input_is_infinite_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe41 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe41 <= input_is_infinite_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe1 <= input_is_nan_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe13 <= input_is_nan_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe14 <= input_is_nan_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe15 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe15 <= input_is_nan_dffe15_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe2 <= input_is_nan_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe21 <= input_is_nan_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe23 <= input_is_nan_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe27 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe27 <= input_is_nan_dffe27_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe3 <= input_is_nan_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe31 <= input_is_nan_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe4 <= input_is_nan_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe41 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe41 <= input_is_nan_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_add_sub_res_mag_dffe21 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_add_sub_res_mag_dffe21 <= man_add_sub_res_mag_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_add_sub_res_mag_dffe23 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_add_sub_res_mag_dffe23 <= man_add_sub_res_mag_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_add_sub_res_mag_dffe27 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_add_sub_res_mag_dffe27 <= man_add_sub_res_mag_dffe27_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_add_sub_res_sign_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_add_sub_res_sign_dffe21 <= man_add_sub_res_sign_dffe27_wo;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_add_sub_res_sign_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_add_sub_res_sign_dffe23 <= man_add_sub_res_sign_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_add_sub_res_sign_dffe27 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_add_sub_res_sign_dffe27 <= man_add_sub_res_sign_dffe27_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_dffe31 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_dffe31 <= man_add_sub_res_mag_dffe26_wo;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_leading_zeros_dffe31 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_leading_zeros_dffe31 <= man_leading_zeros_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_out_dffe5 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_out_dffe5 <= man_out_dffe5_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_dffe4 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_dffe4 <= man_res_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_is_not_zero_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_is_not_zero_dffe3 <= man_res_is_not_zero_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_is_not_zero_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_is_not_zero_dffe31 <= man_res_is_not_zero_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_is_not_zero_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_is_not_zero_dffe4 <= man_res_is_not_zero_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_is_not_zero_dffe41 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_is_not_zero_dffe41 <= man_res_is_not_zero_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_not_zero_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_not_zero_dffe23 <= man_res_not_zero_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_rounding_add_sub_result_reg <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_rounding_add_sub_result_reg <= ( wire_man_res_rounding_add_sub_lower_w_lg_w_lg_w_lg_cout580w581w582w & wire_man_res_rounding_add_sub_lower_result);
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_smaller_dffe13 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_smaller_dffe13 <= man_smaller_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN need_complement_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN need_complement_dffe2 <= need_complement_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN round_bit_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN round_bit_dffe21 <= round_bit_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN round_bit_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN round_bit_dffe23 <= round_bit_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN round_bit_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN round_bit_dffe3 <= round_bit_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN round_bit_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN round_bit_dffe31 <= round_bit_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN rounded_res_infinity_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN rounded_res_infinity_dffe4 <= rounded_res_infinity_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN rshift_distance_dffe13 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN rshift_distance_dffe13 <= rshift_distance_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN rshift_distance_dffe14 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN rshift_distance_dffe14 <= rshift_distance_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN rshift_distance_dffe15 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN rshift_distance_dffe15 <= rshift_distance_dffe15_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe31 <= sign_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_out_dffe5 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_out_dffe5 <= sign_out_dffe5_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_res_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_res_dffe3 <= sign_res_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_res_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_res_dffe4 <= sign_res_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_res_dffe41 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_res_dffe41 <= sign_res_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe1 <= sticky_bit_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe2 <= sticky_bit_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe21 <= sticky_bit_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe23 <= sticky_bit_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe27 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe27 <= sticky_bit_dffe27_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe3 <= sticky_bit_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe31 <= sticky_bit_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN zero_man_sign_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN zero_man_sign_dffe2 <= zero_man_sign_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN zero_man_sign_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN zero_man_sign_dffe21 <= zero_man_sign_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN zero_man_sign_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN zero_man_sign_dffe23 <= zero_man_sign_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN zero_man_sign_dffe27 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN zero_man_sign_dffe27 <= zero_man_sign_dffe27_wi;
END IF;
END IF;
END PROCESS;
add_sub1 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => aligned_dataa_exp_w,
datab => aligned_datab_exp_w,
result => wire_add_sub1_result
);
add_sub2 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => aligned_datab_exp_w,
datab => aligned_dataa_exp_w,
result => wire_add_sub2_result
);
add_sub3 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 6
)
PORT MAP (
dataa => sticky_bit_cnt_dataa_w,
datab => sticky_bit_cnt_datab_w,
result => wire_add_sub3_result
);
add_sub4 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9
)
PORT MAP (
dataa => exp_adjustment_add_sub_dataa_w,
datab => exp_adjustment_add_sub_datab_w,
result => wire_add_sub4_result
);
add_sub5 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => exp_adjustment2_add_sub_dataa_w,
datab => exp_adjustment2_add_sub_datab_w,
result => wire_add_sub5_result
);
add_sub6 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9
)
PORT MAP (
dataa => exp_res_rounding_adder_dataa_w,
datab => exp_rounding_adjustment_w,
result => wire_add_sub6_result
);
loop124 : FOR i IN 0 TO 13 GENERATE
wire_man_2comp_res_lower_w_lg_w_lg_cout367w368w(i) <= wire_man_2comp_res_lower_w_lg_cout367w(0) AND wire_man_2comp_res_upper0_result(i);
END GENERATE loop124;
loop125 : FOR i IN 0 TO 13 GENERATE
wire_man_2comp_res_lower_w_lg_cout366w(i) <= wire_man_2comp_res_lower_cout AND wire_man_2comp_res_upper1_result(i);
END GENERATE loop125;
wire_man_2comp_res_lower_w_lg_cout367w(0) <= NOT wire_man_2comp_res_lower_cout;
loop126 : FOR i IN 0 TO 13 GENERATE
wire_man_2comp_res_lower_w_lg_w_lg_w_lg_cout367w368w369w(i) <= wire_man_2comp_res_lower_w_lg_w_lg_cout367w368w(i) OR wire_man_2comp_res_lower_w_lg_cout366w(i);
END GENERATE loop126;
man_2comp_res_lower : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => borrow_w,
clken => clk_en,
clock => clock,
cout => wire_man_2comp_res_lower_cout,
dataa => man_2comp_res_dataa_w(13 DOWNTO 0),
datab => man_2comp_res_datab_w(13 DOWNTO 0),
result => wire_man_2comp_res_lower_result
);
man_2comp_res_upper0 : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => wire_gnd,
clken => clk_en,
clock => clock,
dataa => man_2comp_res_dataa_w(27 DOWNTO 14),
datab => man_2comp_res_datab_w(27 DOWNTO 14),
result => wire_man_2comp_res_upper0_result
);
man_2comp_res_upper1 : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => wire_vcc,
clken => clk_en,
clock => clock,
dataa => man_2comp_res_dataa_w(27 DOWNTO 14),
datab => man_2comp_res_datab_w(27 DOWNTO 14),
result => wire_man_2comp_res_upper1_result
);
loop127 : FOR i IN 0 TO 13 GENERATE
wire_man_add_sub_lower_w_lg_w_lg_cout354w355w(i) <= wire_man_add_sub_lower_w_lg_cout354w(0) AND wire_man_add_sub_upper0_result(i);
END GENERATE loop127;
loop128 : FOR i IN 0 TO 13 GENERATE
wire_man_add_sub_lower_w_lg_cout353w(i) <= wire_man_add_sub_lower_cout AND wire_man_add_sub_upper1_result(i);
END GENERATE loop128;
wire_man_add_sub_lower_w_lg_cout354w(0) <= NOT wire_man_add_sub_lower_cout;
loop129 : FOR i IN 0 TO 13 GENERATE
wire_man_add_sub_lower_w_lg_w_lg_w_lg_cout354w355w356w(i) <= wire_man_add_sub_lower_w_lg_w_lg_cout354w355w(i) OR wire_man_add_sub_lower_w_lg_cout353w(i);
END GENERATE loop129;
man_add_sub_lower : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => borrow_w,
clken => clk_en,
clock => clock,
cout => wire_man_add_sub_lower_cout,
dataa => man_add_sub_dataa_w(13 DOWNTO 0),
datab => man_add_sub_datab_w(13 DOWNTO 0),
result => wire_man_add_sub_lower_result
);
man_add_sub_upper0 : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => wire_gnd,
clken => clk_en,
clock => clock,
dataa => man_add_sub_dataa_w(27 DOWNTO 14),
datab => man_add_sub_datab_w(27 DOWNTO 14),
result => wire_man_add_sub_upper0_result
);
man_add_sub_upper1 : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => wire_vcc,
clken => clk_en,
clock => clock,
dataa => man_add_sub_dataa_w(27 DOWNTO 14),
datab => man_add_sub_datab_w(27 DOWNTO 14),
result => wire_man_add_sub_upper1_result
);
loop130 : FOR i IN 0 TO 12 GENERATE
wire_man_res_rounding_add_sub_lower_w_lg_w_lg_cout580w581w(i) <= wire_man_res_rounding_add_sub_lower_w_lg_cout580w(0) AND adder_upper_w(i);
END GENERATE loop130;
loop131 : FOR i IN 0 TO 12 GENERATE
wire_man_res_rounding_add_sub_lower_w_lg_cout579w(i) <= wire_man_res_rounding_add_sub_lower_cout AND wire_man_res_rounding_add_sub_upper1_result(i);
END GENERATE loop131;
wire_man_res_rounding_add_sub_lower_w_lg_cout580w(0) <= NOT wire_man_res_rounding_add_sub_lower_cout;
loop132 : FOR i IN 0 TO 12 GENERATE
wire_man_res_rounding_add_sub_lower_w_lg_w_lg_w_lg_cout580w581w582w(i) <= wire_man_res_rounding_add_sub_lower_w_lg_w_lg_cout580w581w(i) OR wire_man_res_rounding_add_sub_lower_w_lg_cout579w(i);
END GENERATE loop132;
man_res_rounding_add_sub_lower : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 13
)
PORT MAP (
cout => wire_man_res_rounding_add_sub_lower_cout,
dataa => man_intermediate_res_w(12 DOWNTO 0),
datab => man_res_rounding_add_sub_datab_w(12 DOWNTO 0),
result => wire_man_res_rounding_add_sub_lower_result
);
man_res_rounding_add_sub_upper1 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 13
)
PORT MAP (
cin => wire_vcc,
dataa => man_intermediate_res_w(25 DOWNTO 13),
datab => man_res_rounding_add_sub_datab_w(25 DOWNTO 13),
result => wire_man_res_rounding_add_sub_upper1_result
);
trailing_zeros_limit_comparator : lpm_compare
GENERIC MAP (
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 6
)
PORT MAP (
agb => wire_trailing_zeros_limit_comparator_agb,
dataa => sticky_bit_cnt_res_w,
datab => trailing_zeros_limit_w
);
END RTL; --add_flt_stratix5_speed_altfp_add_sub_jkj
--VALID FILE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_speed IS
PORT
(
clk_en : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END add_flt_stratix5_speed;
ARCHITECTURE RTL OF add_flt_stratix5_speed IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT add_flt_stratix5_speed_altfp_add_sub_jkj
PORT (
clk_en : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(31 DOWNTO 0);
add_flt_stratix5_speed_altfp_add_sub_jkj_component : add_flt_stratix5_speed_altfp_add_sub_jkj
PORT MAP (
clk_en => clk_en,
clock => clock,
datab => datab,
dataa => dataa,
result => sub_wire0
);
END RTL;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: FPM_FORMAT NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix V"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: WIDTH_DATA NUMERIC "32"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: DENORMAL_SUPPORT STRING "NO"
-- Retrieval info: CONSTANT: DIRECTION STRING "ADD"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix V"
-- Retrieval info: CONSTANT: OPTIMIZE STRING "SPEED"
-- Retrieval info: CONSTANT: PIPELINE NUMERIC "14"
-- Retrieval info: CONSTANT: REDUCED_FUNCTIONALITY STRING "NO"
-- Retrieval info: CONSTANT: WIDTH_EXP NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_MAN NUMERIC "23"
-- Retrieval info: USED_PORT: clk_en 0 0 0 0 INPUT NODEFVAL "clk_en"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL "dataa[31..0]"
-- Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL "datab[31..0]"
-- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
-- Retrieval info: CONNECT: @clk_en 0 0 0 0 clk_en 0 0 0 0
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
-- Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0
-- Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL add_flt_stratix5_speed.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL add_flt_stratix5_speed.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL add_flt_stratix5_speed.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL add_flt_stratix5_speed.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL add_flt_stratix5_speed_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
| gpl-3.0 | 466f176679028c504f74e947e66ef603 | 0.697144 | 2.466673 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-xilinx-zc702/leon3mp.vhd | 1 | 23,813 | -----------------------------------------------------------------------------
-- LEON3 Zc702 Demonstration design
-- Copyright (C) 2012 Fredrik Ringhage, Aeroflex Gaisler
-- Modifed by Jiri Gaisler to provide working AXI interface, 2014-04-05
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.config.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.jtag.all;
-- pragma translate_off
use gaisler.sim.all;
-- pragma translate_on
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
processing_system7_0_MIO : inout std_logic_vector(53 downto 0);
processing_system7_0_PS_SRSTB : inout std_logic;
processing_system7_0_PS_CLK : inout std_logic;
processing_system7_0_PS_PORB : inout std_logic;
processing_system7_0_DDR_Clk : inout std_logic;
processing_system7_0_DDR_Clk_n : inout std_logic;
processing_system7_0_DDR_CKE : inout std_logic;
processing_system7_0_DDR_CS_n : inout std_logic;
processing_system7_0_DDR_RAS_n : inout std_logic;
processing_system7_0_DDR_CAS_n : inout std_logic;
processing_system7_0_DDR_WEB_pin : inout std_logic;
processing_system7_0_DDR_BankAddr : inout std_logic_vector(2 downto 0);
processing_system7_0_DDR_Addr : inout std_logic_vector(14 downto 0);
processing_system7_0_DDR_ODT : inout std_logic;
processing_system7_0_DDR_DRSTB : inout std_logic;
processing_system7_0_DDR_DQ : inout std_logic_vector(31 downto 0);
processing_system7_0_DDR_DM : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS_n : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_VRN : inout std_logic;
processing_system7_0_DDR_VRP : inout std_logic;
button : in std_logic_vector(3 downto 0);
switch : inout std_logic_vector(7 downto 0);
led : out std_logic_vector(7 downto 0)
);
end;
architecture rtl of leon3mp is
component leon3_zc702_stub
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FCLK_CLK0 : out STD_LOGIC;
FCLK_CLK1 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
S_AXI_GP0_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_arid : in STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); --
S_AXI_GP0_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); --
S_AXI_GP0_arready : out STD_LOGIC;
S_AXI_GP0_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_arvalid : in STD_LOGIC;
S_AXI_GP0_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_awid : in STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); --
S_AXI_GP0_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); --
S_AXI_GP0_awready : out STD_LOGIC;
S_AXI_GP0_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_awvalid : in STD_LOGIC;
S_AXI_GP0_bid : out STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_bready : in STD_LOGIC;
S_AXI_GP0_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_bvalid : out STD_LOGIC;
S_AXI_GP0_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_rid : out STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_rlast : out STD_LOGIC;
S_AXI_GP0_rready : in STD_LOGIC;
S_AXI_GP0_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_rvalid : out STD_LOGIC;
S_AXI_GP0_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_wid : in STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_wlast : in STD_LOGIC;
S_AXI_GP0_wready : out STD_LOGIC;
S_AXI_GP0_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_wvalid : in STD_LOGIC
);
end component;
constant maxahbm : integer := (CFG_LEON3*CFG_NCPU)+CFG_AHB_JTAG;
constant maxahbs : integer := 8;
constant maxapbs : integer := 16;
signal vcc, gnd : std_logic;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rsti, rst : std_ulogic;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal rxd1 : std_logic;
signal txd1 : std_logic;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
constant BOARD_FREQ : integer := 83333; -- CLK0 frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ;
signal stati : ahbstat_in_type;
constant CIDSZ : integer := 6;
constant CLENSZ : integer := 4;
signal S_AXI_GP0_araddr : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S_AXI_GP0_arburst : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S_AXI_GP0_arcache : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S_AXI_GP0_arid : STD_LOGIC_VECTOR ( CIDSZ-1 downto 0 );
signal S_AXI_GP0_arlen : STD_LOGIC_VECTOR ( CLENSZ-1 downto 0 );
signal S_AXI_GP0_arlock : STD_LOGIC_VECTOR ( 1 downto 0 ); --
signal S_AXI_GP0_arprot : STD_LOGIC_VECTOR ( 2 downto 0 );
signal S_AXI_GP0_arqos : STD_LOGIC_VECTOR ( 3 downto 0 ); --
signal S_AXI_GP0_awqos : STD_LOGIC_VECTOR ( 3 downto 0 ); --
signal S_AXI_GP0_arready : STD_LOGIC;
signal S_AXI_GP0_arsize : STD_LOGIC_VECTOR ( 2 downto 0 );
signal S_AXI_GP0_arvalid : STD_LOGIC;
signal S_AXI_GP0_awaddr : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S_AXI_GP0_awburst : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S_AXI_GP0_awcache : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S_AXI_GP0_awid : STD_LOGIC_VECTOR ( CIDSZ-1 downto 0 );
signal S_AXI_GP0_awlen : STD_LOGIC_VECTOR ( CLENSZ-1 downto 0 );
signal S_AXI_GP0_awlock : STD_LOGIC_VECTOR ( 1 downto 0 ); --
signal S_AXI_GP0_awprot : STD_LOGIC_VECTOR ( 2 downto 0 );
signal S_AXI_GP0_awready : STD_LOGIC;
signal S_AXI_GP0_awsize : STD_LOGIC_VECTOR ( 2 downto 0 );
signal S_AXI_GP0_awvalid : STD_LOGIC;
signal S_AXI_GP0_bid : STD_LOGIC_VECTOR ( CIDSZ-1 downto 0 );
signal S_AXI_GP0_bready : STD_LOGIC;
signal S_AXI_GP0_bresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S_AXI_GP0_bvalid : STD_LOGIC;
signal S_AXI_GP0_rdata : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S_AXI_GP0_rid : STD_LOGIC_VECTOR ( CIDSZ-1 downto 0 );
signal S_AXI_GP0_rlast : STD_LOGIC;
signal S_AXI_GP0_rready : STD_LOGIC;
signal S_AXI_GP0_rresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S_AXI_GP0_rvalid : STD_LOGIC;
signal S_AXI_GP0_wdata : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S_AXI_GP0_wlast : STD_LOGIC;
signal S_AXI_GP0_wready : STD_LOGIC;
signal S_AXI_GP0_wstrb : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S_AXI_GP0_wvalid : STD_LOGIC;
signal S_AXI_GP0_wid : STD_LOGIC_VECTOR ( 5 downto 0 ); --
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1'; gnd <= '0';
reset_pad : inpad generic map (level => cmos, voltage => x18v, tech => padtech)
port map (button(0), rsti);
rstn <= rst and not rsti;
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, fpnpen => CFG_FPNPEN,
nahbm => maxahbm, nahbs => maxahbs)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
leon3_0 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
end generate;
nocpu : if CFG_LEON3 = 0 generate dbgo(0) <= dbgo_none; end generate;
led1_pad : outpad generic map (tech => padtech, level => cmos, voltage => x33v) port map (led(1), dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsui.break <= gpioi.din(0);
end generate;
dsuact_pad : outpad generic map (tech => padtech, level => cmos, voltage => x33v) port map (led(0), dsuo.active);
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0'; ahbso(2) <= ahbs_none;
end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_LEON3*CFG_NCPU)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_LEON3*CFG_NCPU),
open, open, open, open, open, open, open, gnd);
end generate;
leon3_zc702_stub_i : leon3_zc702_stub
port map (
DDR_ck_p => processing_system7_0_DDR_Clk,
DDR_ck_n => processing_system7_0_DDR_Clk_n,
DDR_cke => processing_system7_0_DDR_CKE,
DDR_cs_n => processing_system7_0_DDR_CS_n,
DDR_ras_n => processing_system7_0_DDR_RAS_n,
DDR_cas_n => processing_system7_0_DDR_CAS_n,
DDR_we_n => processing_system7_0_DDR_WEB_pin,
DDR_ba => processing_system7_0_DDR_BankAddr,
DDR_addr => processing_system7_0_DDR_Addr,
DDR_odt => processing_system7_0_DDR_ODT,
DDR_reset_n => processing_system7_0_DDR_DRSTB,
DDR_dq => processing_system7_0_DDR_DQ,
DDR_dm => processing_system7_0_DDR_DM,
DDR_dqs_p => processing_system7_0_DDR_DQS,
DDR_dqs_n => processing_system7_0_DDR_DQS_n,
FCLK_CLK0 => clkm,
FCLK_RESET0_N => rst,
FIXED_IO_mio => processing_system7_0_MIO,
FIXED_IO_ps_srstb => processing_system7_0_PS_SRSTB,
FIXED_IO_ps_clk => processing_system7_0_PS_CLK,
FIXED_IO_ps_porb => processing_system7_0_PS_PORB,
FIXED_IO_ddr_vrn => processing_system7_0_DDR_VRN,
FIXED_IO_ddr_vrp => processing_system7_0_DDR_VRP,
S_AXI_GP0_araddr => S_AXI_GP0_araddr,
S_AXI_GP0_arburst(1 downto 0) => S_AXI_GP0_arburst(1 downto 0),
S_AXI_GP0_arcache(3 downto 0) => S_AXI_GP0_arcache(3 downto 0),
S_AXI_GP0_arid => S_AXI_GP0_arid,
S_AXI_GP0_arlen => S_AXI_GP0_arlen,
S_AXI_GP0_arlock => S_AXI_GP0_arlock,
S_AXI_GP0_arprot(2 downto 0) => S_AXI_GP0_arprot(2 downto 0),
S_AXI_GP0_arqos => S_AXI_GP0_arqos,
S_AXI_GP0_awqos => S_AXI_GP0_awqos,
S_AXI_GP0_arready => S_AXI_GP0_arready,
S_AXI_GP0_arsize(2 downto 0) => S_AXI_GP0_arsize(2 downto 0),
S_AXI_GP0_arvalid => S_AXI_GP0_arvalid,
S_AXI_GP0_awaddr => S_AXI_GP0_awaddr,
S_AXI_GP0_awburst(1 downto 0) => S_AXI_GP0_awburst(1 downto 0),
S_AXI_GP0_awcache(3 downto 0) => S_AXI_GP0_awcache(3 downto 0),
S_AXI_GP0_awid => S_AXI_GP0_awid,
S_AXI_GP0_awlen => S_AXI_GP0_awlen,
S_AXI_GP0_awlock => S_AXI_GP0_awlock,
S_AXI_GP0_awprot(2 downto 0) => S_AXI_GP0_awprot(2 downto 0),
S_AXI_GP0_awready => S_AXI_GP0_awready,
S_AXI_GP0_awsize(2 downto 0) => S_AXI_GP0_awsize(2 downto 0),
S_AXI_GP0_awvalid => S_AXI_GP0_awvalid,
S_AXI_GP0_bid => S_AXI_GP0_bid,
S_AXI_GP0_bready => S_AXI_GP0_bready,
S_AXI_GP0_bresp(1 downto 0) => S_AXI_GP0_bresp(1 downto 0),
S_AXI_GP0_bvalid => S_AXI_GP0_bvalid,
S_AXI_GP0_rdata(31 downto 0) => S_AXI_GP0_rdata(31 downto 0),
S_AXI_GP0_rid => S_AXI_GP0_rid,
S_AXI_GP0_rlast => S_AXI_GP0_rlast,
S_AXI_GP0_rready => S_AXI_GP0_rready,
S_AXI_GP0_rresp(1 downto 0) => S_AXI_GP0_rresp(1 downto 0),
S_AXI_GP0_rvalid => S_AXI_GP0_rvalid,
S_AXI_GP0_wdata(31 downto 0) => S_AXI_GP0_wdata(31 downto 0),
S_AXI_GP0_wid => S_AXI_GP0_wid,
S_AXI_GP0_wlast => S_AXI_GP0_wlast,
S_AXI_GP0_wready => S_AXI_GP0_wready,
S_AXI_GP0_wstrb(3 downto 0) => S_AXI_GP0_wstrb(3 downto 0),
S_AXI_GP0_wvalid => S_AXI_GP0_wvalid
);
ahb2axi0 : entity work.ahb2axi
generic map(
hindex => 3, haddr => 16#400#, hmask => 16#F00#,
pindex => 0, paddr => 0, cidsz => CIDSZ, clensz => CLENSZ)
port map(
rstn => rstn,
clk => clkm,
ahbsi => ahbsi,
ahbso => ahbso(3),
apbi => apbi,
apbo => apbo(0),
M_AXI_araddr => S_AXI_GP0_araddr,
M_AXI_arburst(1 downto 0) => S_AXI_GP0_arburst(1 downto 0),
M_AXI_arcache(3 downto 0) => S_AXI_GP0_arcache(3 downto 0),
M_AXI_arid => S_AXI_GP0_arid,
M_AXI_arlen => S_AXI_GP0_arlen,
M_AXI_arlock => S_AXI_GP0_arlock,
M_AXI_arprot(2 downto 0) => S_AXI_GP0_arprot(2 downto 0),
M_AXI_arqos => S_AXI_GP0_arqos,
M_AXI_arready => S_AXI_GP0_arready,
M_AXI_arsize(2 downto 0) => S_AXI_GP0_arsize(2 downto 0),
M_AXI_arvalid => S_AXI_GP0_arvalid,
M_AXI_awaddr => S_AXI_GP0_awaddr,
M_AXI_awburst(1 downto 0) => S_AXI_GP0_awburst(1 downto 0),
M_AXI_awcache(3 downto 0) => S_AXI_GP0_awcache(3 downto 0),
M_AXI_awid => S_AXI_GP0_awid,
M_AXI_awlen => S_AXI_GP0_awlen,
M_AXI_awlock => S_AXI_GP0_awlock,
M_AXI_awprot(2 downto 0) => S_AXI_GP0_awprot(2 downto 0),
M_AXI_awqos => S_AXI_GP0_awqos,
M_AXI_awready => S_AXI_GP0_awready,
M_AXI_awsize(2 downto 0) => S_AXI_GP0_awsize(2 downto 0),
M_AXI_awvalid => S_AXI_GP0_awvalid,
M_AXI_bid => S_AXI_GP0_bid,
M_AXI_bready => S_AXI_GP0_bready,
M_AXI_bresp(1 downto 0) => S_AXI_GP0_bresp(1 downto 0),
M_AXI_bvalid => S_AXI_GP0_bvalid,
M_AXI_rdata(31 downto 0) => S_AXI_GP0_rdata(31 downto 0),
M_AXI_rid => S_AXI_GP0_rid,
M_AXI_rlast => S_AXI_GP0_rlast,
M_AXI_rready => S_AXI_GP0_rready,
M_AXI_rresp(1 downto 0) => S_AXI_GP0_rresp(1 downto 0),
M_AXI_rvalid => S_AXI_GP0_rvalid,
M_AXI_wdata(31 downto 0) => S_AXI_GP0_wdata(31 downto 0),
M_AXI_wlast => S_AXI_GP0_wlast,
M_AXI_wready => S_AXI_GP0_wready,
M_AXI_wstrb(3 downto 0) => S_AXI_GP0_wstrb(3 downto 0),
M_AXI_wvalid => S_AXI_GP0_wvalid
);
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
irqgen : if CFG_LEON3 = 1 generate
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
end generate;
irqctrl : if (CFG_IRQ3_ENABLE + CFG_LEON3) /= 2 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW, wdog => 0)
port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
gpti <= gpti_dhalt_drive(dsuo.tstop);
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 8, paddr => 8, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(8), gpioi => gpioi, gpioo => gpioo);
pio_pads : for i in 0 to 7 generate
pio_pad : iopad generic map (tech => padtech, level => cmos, voltage => x18v)
port map (switch(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
pio_pads2 : for i in 8 to 10 generate
pio_pad : inpad generic map (tech => padtech, level => cmos, voltage => x18v)
port map (button(i-8+1), gpioi.din(i)); -- Use +1 because button(0) is used for reset
end generate;
pio_pads3 : for i in 11 to 14 generate
pio_pad : outpad generic map (tech => padtech, level => cmos, voltage => x33v)
port map (led(i-11+4), gpioo.dout(i));
end generate;
end generate;
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1;
u1i.ctsn <= '0';
u1i.extclk <= '0';
txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
hready_pad : outpad generic map (level => cmos, voltage => x33v, tech => padtech)
port map (led(2), ahbmi.hready);
rsti_pad : outpad generic map (level => cmos, voltage => x33v, tech => padtech)
port map (led(3), rsti);
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
stati <= ahbstat_in_none;
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 0, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(0));
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 5, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(5));
end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0 : ahbrep generic map (hindex => 6, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(6));
-- pragma translate_on
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (maxahbs+1) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Xilinx zc702 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-3.0 | 83deb2eeee2aad7b0dc6e77f1217d8ed | 0.569815 | 3.238983 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/maps/grgates.vhd | 1 | 6,924 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: Various
-- File: grgates.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Various gates with tech mapping
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use work.allclkgen.all;
entity grmux2 is generic( tech : integer := inferred; imp : integer := 0);
port( ip0, ip1, sel : in std_logic; op : out std_ulogic); end;
architecture rtl of grmux2 is
component ut130hbd_mux2
port(
i0 : in std_ulogic;
i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic);
end component;
component mux2_ut90nhbd
port(
i0 : in std_ulogic;
i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic);
end component;
component mux2_rhs65
port(
i0 : in std_ulogic;
i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic);
end component;
constant has_mux2 : tech_ability_type :=
( rhlib18t => 1, ut130 => 1, ut90 => 1, rhs65 => 1, others => 0);
begin
y0 : if has_mux2(tech) = 1 generate
rhlib : if tech = rhlib18t generate
x0 : clkmux_rhlib18t port map (i0 => ip0, i1 => ip1, sel => sel, o => op);
end generate;
ut13 : if tech = ut130 generate
x0 : ut130hbd_mux2 port map (i0 => ip0, i1 => ip1, sel => sel, o => op);
end generate;
ut90n : if tech = ut90 generate
x0 : mux2_ut90nhbd port map (i0 => ip0, i1 => ip1, sel => sel, o => op);
end generate;
rhs65n: if tech=rhs65 generate
x0 : mux2_rhs65 port map (i0 => ip0, i1 => ip1, sel => sel, o => op);
end generate;
end generate;
y1 : if has_mux2(tech) = 0 generate
op <= ip0 when sel = '0' else ip1;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity grmux2v is generic( tech : integer := inferred;
bits : integer := 2; imp : integer := 0);
port( ip0, ip1 : in std_logic_vector(bits-1 downto 0);
sel : in std_logic;
op : out std_logic_vector(bits-1 downto 0));
end;
architecture rtl of grmux2v is
begin
x0 : for i in bits-1 downto 0 generate
y0 : grmux2 generic map (tech, imp) port map (ip0(i), ip1(i), sel, op(i));
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity grdff is generic( tech : integer := inferred; imp : integer := 0);
port( clk, d : in std_ulogic; q : out std_ulogic); end;
architecture rtl of grdff is
component ut130hbd_dff
port(
clk : in std_ulogic;
d : in std_ulogic;
q : out std_ulogic);
end component;
component dff_ut90nhbd
port(
clk : in std_ulogic;
d : in std_ulogic;
q : out std_ulogic);
end component;
constant has_dff : tech_ability_type :=
( ut130 => 1, ut90 => 1, others => 0);
begin
y0 : if has_dff(tech) = 1 generate
ut13 : if tech = ut130 generate
x0 : ut130hbd_dff port map (clk => clk, d => d, q => q);
end generate;
ut90n : if tech = ut90 generate
x0 : dff_ut90nhbd port map (clk => clk, d => d, q => q);
end generate;
end generate;
y1 : if has_dff(tech) = 0 generate
x0 : process(clk)
begin if rising_edge(clk) then q <= d; end if; end process;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity gror2 is generic( tech : integer := inferred; imp : integer := 0);
port( i0, i1 : in std_ulogic; q : out std_ulogic); end;
architecture rtl of gror2 is
component ut130hbd_or2
port(
i0 : in std_ulogic;
i1 : in std_ulogic;
q : out std_ulogic);
end component;
component or2_ut90nhbd
port(
i0 : in std_ulogic;
i1 : in std_ulogic;
o : out std_ulogic);
end component;
constant has_or2 : tech_ability_type :=
( ut130 => 1, ut90 => 1, others => 0);
begin
y0 : if has_or2(tech) = 1 generate
ut13 : if tech = ut130 generate
x0 : ut130hbd_or2 port map (i0 => i0, i1 => i1, q => q);
end generate;
ut90n : if tech = ut90 generate
x0 : or2_ut90nhbd port map (i0 => i0, i1 => i1, o => q);
end generate;
end generate;
y1 : if has_or2(tech) = 0 generate
q <= i0 or i1;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity grand12 is generic( tech : integer := inferred; imp : integer := 0);
port( i0, i1 : in std_ulogic; q : out std_ulogic); end;
architecture rtl of grand12 is
component ut130hbd_and12
port(
i0 : in std_ulogic;
i1 : in std_ulogic;
q : out std_ulogic);
end component;
component and12_ut90nhbd
port(
i0 : in std_ulogic;
i1 : in std_ulogic;
o : out std_ulogic);
end component;
constant has_and12 : tech_ability_type :=
( ut130 => 1, ut90 => 1, others => 0);
begin
y0 : if has_and12(tech) = 1 generate
ut13 : if tech = ut130 generate
x0 : ut130hbd_and12 port map (i0 => i0, i1 => i1, q => q);
end generate;
ut90n : if tech = ut90 generate
x0 : and12_ut90nhbd port map (i0 => i0, i1 => i1, o => q);
end generate;
end generate;
y1 : if has_and12(tech) = 0 generate
q <= i0 and not i1;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity grnand2 is
generic (
tech: integer := 0;
imp: integer := 0
);
port (
i0: in std_ulogic;
i1: in std_ulogic;
q : out std_ulogic
);
end;
architecture rtl of grnand2 is
constant has_nand2: tech_ability_type := (others => 0);
begin
y0: if has_nand2(tech)=1 generate
end generate;
y1: if has_nand2(tech)=0 generate
q <= not (i0 and i1);
end generate;
end;
| gpl-3.0 | e66ed254e5d2cc7c3f40f5304af3f48a | 0.602109 | 3.102151 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3mp/testbench.vhd | 1 | 19,913 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
use gaisler.jtagtst.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 21; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
port (
pci_rst : inout std_logic; -- PCI bus
pci_clk : in std_ulogic;
pci_gnt : in std_ulogic;
pci_idsel : in std_ulogic;
pci_lock : inout std_ulogic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_ulogic;
pci_irdy : inout std_ulogic;
pci_trdy : inout std_ulogic;
pci_devsel : inout std_ulogic;
pci_stop : inout std_ulogic;
pci_perr : inout std_ulogic;
pci_par : inout std_ulogic;
pci_req : inout std_ulogic;
pci_serr : inout std_ulogic;
pci_host : in std_ulogic;
pci_66 : in std_ulogic
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
component leon3mp
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
pllref : in std_ulogic;
errorn : out std_ulogic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
sa : out std_logic_vector(14 downto 0);
sd : inout std_logic_vector(63 downto 0);
sdclk : out std_ulogic;
sdcke : out std_logic_vector (1 downto 0); -- sdram clock enable
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_ulogic; -- sdram write enable
sdrasn : out std_ulogic; -- sdram ras
sdcasn : out std_ulogic; -- sdram cas
sddqm : out std_logic_vector (7 downto 0); -- sdram dqm
dsutx : out std_ulogic; -- DSU tx data
dsurx : in std_ulogic; -- DSU rx data
dsuen : in std_ulogic;
dsubre : in std_ulogic;
dsuact : out std_ulogic;
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
txd2 : out std_ulogic; -- UART1 tx data
rxd2 : in std_ulogic; -- UART1 rx data
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_ulogic;
writen : out std_ulogic;
read : out std_ulogic;
iosn : out std_ulogic;
romsn : out std_logic_vector (1 downto 0);
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_logic;
erx_clk : in std_logic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_logic;
erx_er : in std_logic;
erx_col : in std_logic;
erx_crs : in std_logic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_logic;
etx_er : out std_logic;
emdc : out std_logic;
emddis : out std_logic;
epwrdwn : out std_logic;
ereset : out std_logic;
esleep : out std_logic;
epause : out std_logic;
pci_rst : inout std_logic; -- PCI bus
pci_clk : in std_ulogic;
pci_gnt : in std_ulogic;
pci_idsel : in std_ulogic;
pci_lock : inout std_ulogic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_ulogic;
pci_irdy : inout std_ulogic;
pci_trdy : inout std_ulogic;
pci_devsel : inout std_ulogic;
pci_stop : inout std_ulogic;
pci_perr : inout std_ulogic;
pci_par : inout std_ulogic;
pci_req : inout std_ulogic;
pci_serr : inout std_ulogic;
pci_host : in std_ulogic;
pci_66 : in std_ulogic;
pci_arb_req : in std_logic_vector(0 to 3);
pci_arb_gnt : out std_logic_vector(0 to 3);
can_txd : out std_ulogic;
can_rxd : in std_ulogic;
can_stb : out std_ulogic;
spw_clk : in std_ulogic;
spw_rxd : in std_logic_vector(0 to 2);
spw_rxdn : in std_logic_vector(0 to 2);
spw_rxs : in std_logic_vector(0 to 2);
spw_rxsn : in std_logic_vector(0 to 2);
spw_txd : out std_logic_vector(0 to 2);
spw_txdn : out std_logic_vector(0 to 2);
spw_txs : out std_logic_vector(0 to 2);
spw_txsn : out std_logic_vector(0 to 2);
tck, tms, tdi : in std_ulogic;
tdo : out std_ulogic
);
end component;
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(27 downto 0);
signal data : std_logic_vector(31 downto 0);
signal ramsn : std_logic_vector(4 downto 0);
signal ramoen : std_logic_vector(4 downto 0);
signal rwen : std_logic_vector(3 downto 0);
signal rwenx : std_logic_vector(3 downto 0);
signal romsn : std_logic_vector(1 downto 0);
signal iosn : std_ulogic;
signal oen : std_ulogic;
signal read : std_ulogic;
signal writen : std_ulogic;
signal brdyn : std_ulogic;
signal bexcn : std_ulogic;
signal wdog : std_ulogic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal error : std_logic;
signal gpio : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal sdcke : std_logic_vector ( 1 downto 0); -- clk en
signal sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
signal sdwen : std_ulogic; -- write en
signal sdrasn : std_ulogic; -- row addr stb
signal sdcasn : std_ulogic; -- col addr stb
signal sddqm : std_logic_vector ( 7 downto 0); -- data i/o mask
signal sdclk : std_ulogic;
signal plllock : std_ulogic;
signal txd1, rxd1 : std_ulogic;
signal txd2, rxd2 : std_ulogic;
signal etx_clk, erx_clk, erx_dv, erx_er, erx_col, erx_crs, etx_en, etx_er : std_logic:='0';
signal erxd, etxd: std_logic_vector(3 downto 0):=(others=>'0');
signal erxdt, etxdt: std_logic_vector(7 downto 0):=(others=>'0');
signal emdc, emdio: std_logic;
signal gtx_clk : std_ulogic;
signal emddis : std_logic;
signal epwrdwn : std_logic;
signal ereset : std_logic;
signal esleep : std_logic;
signal epause : std_logic;
constant lresp : boolean := false;
signal sa : std_logic_vector(14 downto 0);
signal sd : std_logic_vector(63 downto 0);
signal pci_arb_req, pci_arb_gnt : std_logic_vector(0 to 3);
signal can_txd : std_ulogic;
signal can_rxd : std_ulogic;
signal can_stb : std_ulogic;
signal spw_clk : std_ulogic := '0';
signal spw_rxd : std_logic_vector(0 to 2) := "000";
signal spw_rxdn : std_logic_vector(0 to 2) := "000";
signal spw_rxs : std_logic_vector(0 to 2) := "000";
signal spw_rxsn : std_logic_vector(0 to 2) := "000";
signal spw_txd : std_logic_vector(0 to 2);
signal spw_txdn : std_logic_vector(0 to 2);
signal spw_txs : std_logic_vector(0 to 2);
signal spw_txsn : std_logic_vector(0 to 2);
signal tck, tms, tdi, tdo : std_ulogic;
constant CFG_SDEN : integer := CFG_SDCTRL + CFG_MCTRL_SDEN ;
constant CFG_SD64 : integer := CFG_SDCTRL_SD64 + CFG_MCTRL_SD64;
begin
-- clock and reset
spw_clk <= not spw_clk after 20 ns;
spw_rxd(0) <= spw_txd(0); spw_rxdn(0) <= spw_txdn(0);
spw_rxs(0) <= spw_txs(0); spw_rxsn(0) <= spw_txsn(0);
spw_rxd(1) <= spw_txd(1); spw_rxdn(1) <= spw_txdn(1);
spw_rxs(1) <= spw_txs(1); spw_rxsn(1) <= spw_txsn(1);
spw_rxd(2) <= spw_txd(0); spw_rxdn(2) <= spw_txdn(2);
spw_rxs(2) <= spw_txs(0); spw_rxsn(2) <= spw_txsn(2);
clk <= not clk after ct * 1 ns;
rst <= dsurst;
dsuen <= '1'; dsubre <= '0'; rxd1 <= '1';
--## can_rxd <= '1';
can_rxd <= can_txd; -- CAN LOOP BACK ##
d3 : leon3mp
generic map ( fabtech, memtech, padtech, clktech,
disas, dbguart, pclow )
port map (rst, clk, sdclk, error, address(27 downto 0), data,
sa, sd, sdclk, sdcke, sdcsn, sdwen, sdrasn, sdcasn, sddqm,
dsutx, dsurx, dsuen, dsubre, dsuact, txd1, rxd1, txd2, rxd2,
ramsn, ramoen, rwen, oen, writen, read, iosn, romsn, gpio,
emdio, etx_clk, erx_clk, erxd, erx_dv, erx_er, erx_col, erx_crs,
etxd, etx_en, etx_er, emdc, emddis, epwrdwn, ereset, esleep, epause,
pci_rst, pci_clk, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr, pci_par,
pci_req, pci_serr, pci_host, pci_66, pci_arb_req, pci_arb_gnt,
can_txd, can_rxd, can_stb, spw_clk, spw_rxd, spw_rxdn, spw_rxs,
spw_rxsn, spw_txd, spw_txdn, spw_txs, spw_txsn, tck, tms, tdi, tdo);
-- optional sdram
sd0 : if (CFG_SDEN /= 0) and (CFG_MCTRL_SEPBUS = 0) generate
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => data(31 downto 16), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => data(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
u2: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => data(31 downto 16), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u3: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => data(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
end generate;
sd1 : if (CFG_SDEN /= 0) and (CFG_MCTRL_SEPBUS = 1) generate
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
u2: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u3: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
sd64 : if (CFG_SD64 /= 0) generate
u4: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(63 downto 48), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(7 downto 6));
u5: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(47 downto 32), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(5 downto 4));
u6: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(63 downto 48), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(7 downto 6));
u7: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(47 downto 32), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(5 downto 4));
end generate;
end generate;
prom0 : for i in 0 to (romwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => romdepth, fname => promfile)
port map (address(romdepth+1 downto 2), data(31-i*8 downto 24-i*8), romsn(0),
rwen(i), oen);
end generate;
sbanks : for k in 0 to srambanks-1 generate
sram0 : for i in 0 to (sramwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
port map (address(sramdepth+1 downto 2), data(31-i*8 downto 24-i*8),
ramsn(k), rwen(i), ramoen(k));
end generate;
end generate;
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
erxd <= erxdt(3 downto 0);
etxdt <= "0000" & etxd;
p0: phy
generic map(base1000_t_fd => 0, base1000_t_hd => 0)
port map(rst, emdio, etx_clk, erx_clk, erxdt, erx_dv,
erx_er, erx_col, erx_crs, etxdt, etx_en, etx_er, emdc, gtx_clk);
end generate;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= buskeep(data), (others => 'H') after 250 ns;
sd <= buskeep(sd), (others => 'H') after 250 ns;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, oen, writen, brdyn);
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
jtagproc : process
begin
wait;
jtagcom(tdo, tck, tms, tdi, 100, 20, 16#40000000#, true);
wait;
end process;
end;
| gpl-3.0 | 6260c653d5431c8b93d433b6a5a7af3c | 0.575453 | 3.04294 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-gr-xc3s-1500/testbench.vhd | 1 | 16,282 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 18; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
component leon3mp
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
clk3 : in std_ulogic;
pllref : in std_ulogic;
errorn : out std_ulogic;
wdogn : out std_ulogic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_ulogic;
writen : out std_ulogic;
read : out std_ulogic;
iosn : out std_ulogic;
bexcn : in std_ulogic; -- DSU rx data
brdyn : in std_ulogic; -- DSU rx data
romsn : out std_logic_vector (1 downto 0);
sdclk : out std_ulogic;
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_ulogic; -- sdram write enable
sdrasn : out std_ulogic; -- sdram ras
sdcasn : out std_ulogic; -- sdram cas
sddqm : out std_logic_vector (3 downto 0); -- sdram dqm
dsuen : in std_ulogic;
dsubre : in std_ulogic;
dsuact : out std_ulogic;
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
ctsn1 : in std_ulogic; -- UART1 rx data
rtsn1 : out std_ulogic; -- UART1 rx data
txd2 : out std_ulogic; -- UART2 tx data
rxd2 : in std_ulogic; -- UART2 rx data
ctsn2 : in std_ulogic; -- UART1 rx data
rtsn2 : out std_ulogic; -- UART1 rx data
pio : inout std_logic_vector(17 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
emdint : in std_ulogic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
emdc : out std_ulogic;
ps2clk : inout std_logic_vector(1 downto 0);
ps2data : inout std_logic_vector(1 downto 0);
vid_clock : out std_ulogic;
vid_blankn : out std_ulogic;
vid_syncn : out std_ulogic;
vid_hsync : out std_ulogic;
vid_vsync : out std_ulogic;
vid_r : out std_logic_vector(7 downto 0);
vid_g : out std_logic_vector(7 downto 0);
vid_b : out std_logic_vector(7 downto 0);
spw_clk : in std_ulogic;
spw_rxdp : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxdn : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxsp : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxsn : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txdp : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txdn : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txsp : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txsn : out std_logic_vector(0 to CFG_SPW_NUM-1);
usb_clkout : in std_ulogic;
usb_d : inout std_logic_vector(15 downto 0);
usb_linestate : in std_logic_vector(1 downto 0);
usb_opmode : out std_logic_vector(1 downto 0);
usb_reset : out std_ulogic;
usb_rxactive : in std_ulogic;
usb_rxerror : in std_ulogic;
usb_rxvalid : in std_ulogic;
usb_suspend : out std_ulogic;
usb_termsel : out std_ulogic;
usb_txready : in std_ulogic;
usb_txvalid : out std_ulogic;
usb_validh : inout std_ulogic;
usb_xcvrsel : out std_ulogic;
usb_vbus : in std_ulogic
);
end component;
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(27 downto 0);
signal data : std_logic_vector(31 downto 0);
signal pio : std_logic_vector(17 downto 0);
signal romsn : std_logic_vector(1 downto 0);
signal ramsn : std_logic_vector(4 downto 0);
signal ramoen : std_logic_vector(4 downto 0);
signal rwen : std_logic_vector(3 downto 0);
signal oen : std_ulogic;
signal writen : std_ulogic;
signal read : std_ulogic;
signal iosn : std_ulogic;
signal bexcn : std_ulogic;
signal brdyn : std_ulogic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal wdogn : std_logic;
signal sdcke : std_ulogic; -- clk en
signal sdcsn : std_logic_vector ( 1 downto 0);
signal sdwen : std_ulogic; -- write en
signal sdrasn : std_ulogic; -- row addr stb
signal sdcasn : std_ulogic; -- col addr stb
signal sddqm : std_logic_vector ( 3 downto 0); -- data i/o mask
signal sdclk : std_ulogic;
signal pllref : std_ulogic;
signal txd1, rxd1 : std_logic;
signal txd2, rxd2 : std_logic;
signal ctsn1, rtsn1 : std_ulogic;
signal ctsn2, rtsn2 : std_ulogic;
signal errorn : std_logic;
signal etx_clk, erx_clk, erx_dv, erx_er, erx_col, erx_crs, etx_en, etx_er : std_logic:='0';
signal erxd, etxd: std_logic_vector(3 downto 0):=(others=>'0');
signal erxdt, etxdt : std_logic_vector(7 downto 0);
signal emdc, emdio: std_logic; --dummy signal for the mdc,mdio in the phy which is not used
signal eth_macclk : std_ulogic := '0';
signal emdint : std_ulogic;
signal ps2clk : std_logic_vector(1 downto 0);
signal ps2data : std_logic_vector(1 downto 0);
signal vid_clock : std_ulogic;
signal vid_blankn : std_ulogic;
signal vid_syncn : std_ulogic;
signal vid_hsync : std_ulogic;
signal vid_vsync : std_ulogic;
signal vid_r : std_logic_vector(7 downto 0);
signal vid_g : std_logic_vector(7 downto 0);
signal vid_b : std_logic_vector(7 downto 0);
signal clk3 : std_ulogic := '0';
signal spw_clk : std_ulogic := '0';
signal spw_rxdp : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_rxdn : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_rxsp : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_rxsn : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_txdp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txdn : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txsp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txsn : std_logic_vector(0 to CFG_SPW_NUM-1);
signal usb_clkout : std_ulogic := '0';
signal usb_d : std_logic_vector(15 downto 0);
signal usb_linestate : std_logic_vector(1 downto 0);
signal usb_opmode : std_logic_vector(1 downto 0);
signal usb_reset : std_ulogic;
signal usb_rxactive : std_ulogic;
signal usb_rxerror : std_ulogic;
signal usb_rxvalid : std_ulogic;
signal usb_suspend : std_ulogic;
signal usb_termsel : std_ulogic;
signal usb_txready : std_ulogic;
signal usb_txvalid : std_ulogic;
signal usb_validh : std_logic;
signal usb_xcvrsel : std_ulogic;
signal usb_vbus : std_ulogic;
signal rhvalid : std_ulogic;
constant lresp : boolean := false;
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
clk3 <= not clk3 after 20 ns;
rst <= dsurst and wdogn;
dsuen <= '1'; dsubre <= '0';
rxd1 <= 'H'; ctsn1 <= '0';
rxd2 <= 'H'; ctsn2 <= '0'; pllref <= sdclk;
ps2clk <= "HH"; ps2data <= "HH";
pio(4) <= pio(5); pio(1) <= pio(2); pio <= (others => 'H');
wdogn <= 'H';
usb_clkout <= not usb_clkout after 8.33 ns; -- ~60MHz
spw_rxdp <= spw_txdp; spw_rxdn <= spw_txdn;
spw_rxsp <= spw_txsp; spw_rxsn <= spw_txsn;
cpu : leon3mp
generic map ( fabtech, memtech, padtech, clktech,
disas, dbguart, pclow )
port map (rst, clk, clk3, pllref, errorn, wdogn, address(27 downto 0), data,
ramsn, ramoen, rwen, oen, writen, read, iosn, bexcn, brdyn, romsn,
sdclk, sdcsn, sdwen, sdrasn, sdcasn, sddqm,
dsuen, dsubre, dsuact,
txd1, rxd1, ctsn1, rtsn1, txd2, rxd2, ctsn2, rtsn2, pio,
emdio, etx_clk, erx_clk, erxd, erx_dv, erx_er, erx_col, erx_crs, emdint,
etxd, etx_en, etx_er, emdc, ps2clk, ps2data, vid_clock, vid_blankn, vid_syncn,
vid_hsync, vid_vsync, vid_r, vid_g, vid_b, spw_clk, spw_rxdp, spw_rxdn,
spw_rxsp, spw_rxsn, spw_txdp, spw_txdn, spw_txsp, spw_txsn, usb_clkout,
usb_d, usb_linestate, usb_opmode, usb_reset, usb_rxactive, usb_rxerror,
usb_rxvalid, usb_suspend, usb_termsel, usb_txready, usb_txvalid, usb_validh,
usb_xcvrsel, usb_vbus
);
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => data(31 downto 16), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => vcc,
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => data(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => vcc,
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
prom0 : sram generic map (index => 6, abits => romdepth, fname => promfile)
port map (address(romdepth-1 downto 0), data(31 downto 24), romsn(0),
writen, oen);
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
erxd <= erxdt(3 downto 0);
etxdt <= "0000" & etxd;
p0: phy
generic map(base1000_t_fd => 0, base1000_t_hd => 0)
port map(rst, emdio, etx_clk, erx_clk, erxdt, erx_dv,
erx_er, erx_col, erx_crs, etxdt, etx_en, etx_er, emdc, eth_macclk);
end generate;
ps2devs: for i in 0 to 1 generate
ps2_device(ps2clk(i), ps2data(i));
end generate ps2devs;
errorn <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 5000 ns;
if to_x01(errorn) = '1' then wait on errorn; end if;
assert (to_x01(errorn) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
test0 : grtestmod
port map ( rst, clk, errorn, address(21 downto 2), data,
iosn, oen, writen, brdyn);
data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 320 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 2500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#2e#, txp);
wait for 25000 ns;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0D#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#70#, 16#11#, 16#78#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#0D#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#00#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
wait;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#aa#, txp);
txa(dsutx, 16#00#, 16#55#, 16#00#, 16#55#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#a0#, txp);
txa(dsutx, 16#01#, 16#02#, 16#09#, 16#33#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#80#, 16#00#, 16#02#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(txd2, rxd2);
wait;
end process;
end ;
| gpl-3.0 | 139c2e6691dab55946d4c222286f4141 | 0.587888 | 3.039955 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/pci/ptf/pt_pci_monitor.vhd | 1 | 14,814 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pcitb_monitor
-- File: pcitb_monitor.vhd
-- Author:
-- Description: PCI Monitor.
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.pt_pkg.all;
library grlib;
use grlib.stdlib.xorv;
entity pt_pci_monitor is
generic (dbglevel : integer := 1);
port (pciin : in pci_type);
end pt_pci_monitor;
architecture tb of pt_pci_monitor is
constant T_O : integer := 9;
type pci_array_type is array(0 to 2) of pci_type;
type reg_type is record
pci : pci_array_type;
frame_deass : boolean;
m_wait_data_phase : boolean;
t_wait_data_phase : boolean;
stop_asserted : boolean;
device_sel : boolean;
first : boolean;
current_master : integer;
master_cnt : integer;
irdy_cnt : integer;
trdy_cnt : integer;
end record;
signal r,rin : reg_type;
signal init_done : boolean := false;
begin
init : process
begin
if init_done = false then
wait until pciin.syst.rst = '0';
wait until pciin.syst.rst = '1';
init_done <= true;
else
wait until pciin.syst.rst = '0';
init_done <= false;
end if;
end process;
comb : process(pciin)
variable i : integer;
variable v : reg_type;
begin
v := r;
v.pci(0) := pciin; v.pci(1) := r.pci(0); v.pci(2) := r.pci(1);
if r.pci(0).ifc.frame = 'H' then v.frame_deass := false;
elsif (r.pci(0).ifc.frame and not r.pci(1).ifc.frame) = '1' then v.frame_deass := true; end if;
if ((r.pci(0).ifc.trdy and r.pci(0).ifc.stop) or r.pci(0).ifc.irdy) = '0' then v.m_wait_data_phase := false;
elsif r.pci(0).ifc.irdy = '0' then v.m_wait_data_phase := true; end if;
if ((r.pci(0).ifc.trdy and r.pci(0).ifc.stop) or r.pci(0).ifc.irdy) = '0' then v.t_wait_data_phase := false;
elsif (r.pci(0).ifc.trdy and r.pci(0).ifc.stop) = '0' then v.t_wait_data_phase := true; end if;
if r.pci(0).ifc.frame = '0' and r.pci(1).ifc.frame = 'H' then
for i in 0 to 20 loop
if r.pci(0).arb.gnt(i) = '0' then v.current_master := i; end if;
end loop;
end if;
if (r.pci(0).ifc.frame and r.pci(0).ifc.irdy) = '0' then
if (r.pci(0).ifc.trdy and r.pci(0).ifc.stop) = '1' then
v.master_cnt := r.master_cnt+1;
else v.master_cnt := 0; end if;
else v.master_cnt := 0; end if;
if (r.pci(0).ifc.irdy and not r.pci(0).ifc.frame) = '1' then
v.irdy_cnt := r.irdy_cnt+1;
else v.irdy_cnt := 0; end if;
if ((r.pci(0).ifc.trdy and r.pci(0).ifc.stop) and not (r.pci(0).ifc.frame and r.pci(0).ifc.irdy)) = '1' then
v.trdy_cnt := r.trdy_cnt+1;
else v.trdy_cnt := 0; end if;
if r.pci(0).ifc.devsel = '0' then v.device_sel := true;
elsif (to_x01(r.pci(1).ifc.devsel) and not (r.pci(0).ifc.frame and r.pci(0).ifc.irdy)) = '1' then v.device_sel := false; end if;
if r.pci(0).ifc.stop = '0' then v.stop_asserted := true;
elsif r.pci(0).ifc.frame = '0' then v.stop_asserted := false; end if;
if (r.pci(1).ifc.frame = 'H' and r.pci(0).ifc.frame = '0') then v.first := true;
elsif (r.pci(0).ifc.trdy and r.pci(0).ifc.stop) = '0' then v.first := false; end if;
rin <= v;
end process;
clkprc : process(pciin.syst)
begin
if rising_edge(pciin.syst.clk) then
r <= rin;
if init_done then
if (r.pci(0).ifc.frame = '0' and r.frame_deass = true) then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: FRAME# was reasserted during the same transaction.");
end if;
end if;
if (r.pci(0).ifc.frame and r.pci(0).ifc.irdy and not r.pci(1).ifc.frame) = '1' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: FRAME# was deasserted without IRDY# asserted.");
end if;
end if;
if (r.m_wait_data_phase and r.device_sel) then
if (r.pci(0).ifc.frame /= r.pci(1).ifc.frame) or (r.pci(0).ifc.irdy /= r.pci(1).ifc.irdy) then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Current master changed IRDY# or FRAME# before current data phase was completed.");
end if;
end if;
end if;
if ((r.pci(1).ifc.irdy and r.pci(1).ifc.frame and not r.pci(2).ifc.irdy) = '1' and r.stop_asserted = true) then
if not ((r.pci(1).arb.req(r.current_master) and (r.pci(0).arb.req(r.current_master) or r.pci(2).arb.req(r.current_master))) = '1') then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Current master at slot %d did not release its REQ# when the bus returned to idle state.",r.current_master);
end if;
end if;
end if;
if (r.pci(0).ifc.stop and not r.pci(1).ifc.stop and not r.pci(0).ifc.frame) = '1' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Target did not keep STOP# asserted until FRAME# was deasserted.");
end if;
end if;
if (r.pci(0).ifc.frame and r.pci(1).ifc.frame and not r.pci(0).ifc.stop and not r.pci(1).ifc.stop) = '1' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Target did not release STOP# after FRAME# was deasserted.");
end if;
end if;
if r.t_wait_data_phase = true then
if (r.pci(0).ifc.devsel /= r.pci(1).ifc.devsel) or (r.pci(0).ifc.trdy /= r.pci(1).ifc.trdy) or (r.pci(0).ifc.stop /= r.pci(1).ifc.stop) then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Current target changed DEVSEL#, STOP# or TRDY# before current data phase was completed.");
end if;
end if;
end if;
if (r.pci(0).ifc.frame and r.pci(0).ifc.stop and not r.pci(1).ifc.frame and not r.pci(1).ifc.stop) = '1' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Target did not keep STOP# asserted until the last data phase.");
end if;
end if;
if (r.pci(2).ifc.frame and not (r.pci(2).ifc.trdy and r.pci(2).ifc.stop)) = '1' then
if r.pci(1).ifc.irdy = '0' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Master kept IRDY# asserted after last data phase.");
end if;
end if;
if r.pci(1).ifc.trdy = '0' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Target kept TRDY# asserted after last data phase.");
end if;
end if;
if r.pci(1).ifc.stop = '0' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Target kept STOP# asserted after last data phase.");
end if;
end if;
if r.pci(1).ifc.frame /= 'H' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Master did not tri-state FRAME# after turn-around cycle.");
end if;
end if;
if r.pci(0).ifc.irdy /= 'H' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Master did not tri-state IRDY# after turn-around cycle.");
end if;
end if;
if r.pci(0).ifc.trdy /= 'H' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Target did not tri-state TRDY# after turn-around cycle.");
end if;
end if;
if r.pci(0).ifc.stop /= 'H' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Target did not tri-state STOP# after turn-around cycle.");
end if;
end if;
end if;
if (r.master_cnt > 16 and r.first = true) then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Target did not complete its initial data phase in 16 clkc.");
end if;
end if;
if r.irdy_cnt > 8 then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Master did not complete its initial data phase in 8 clkc.");
end if;
end if;
if (r.trdy_cnt > 8 and r.device_sel = true and r.first = false) then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Target did not complete a data phase in 8 clkc.");
end if;
end if;
if not r.device_sel then
if (r.pci(0).ifc.irdy and not r.pci(1).ifc.irdy) = '1' then
if dbglevel > 0 then
assert false
report "**"
severity note;
printf("PCI_MONITOR: Master abort detected.");
end if;
end if;
end if;
if ((r.pci(1).ifc.irdy = 'H' and r.pci(1).ifc.frame = '0')
or (r.pci(1).ifc.irdy or r.pci(1).ifc.trdy) = '0') then
if r.pci(0).ad.par = 'Z' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Current Master/Target is not generating parity during a data phase.");
end if;
elsif r.pci(0).ad.par /= xorv(r.pci(1).ad.ad & r.pci(1).ad.cbe) then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Parity error detected.");
end if;
end if;
end if;
end if;
end if;
end process;
adchk : process(pciin.ad)
begin
if init_done then
-- for i in 0 to 31 loop
-- if pciin.ad.ad(i) = 'X' then
-- if dbglevel > 0 then
-- assert false
-- report " **"
-- severity warning;
-- printf("PCI_MONITOR: AD lines have multiple drivers.");
-- end if;
-- end if;
-- end loop;
for i in 0 to 3 loop
if pciin.ad.cbe(i) = 'X' then
if dbglevel > 0 then
assert false
report " **"
severity warning;
printf("PCI_MONITOR: CBE# lines have multiple drivers.");
end if;
end if;
end loop;
-- if pciin.ad.par = 'X' then
-- if dbglevel > 0 then
-- assert false
-- report " **"
-- severity warning;
-- printf("PCI_MONITOR: PAR line has multiple drivers.");
-- end if;
-- end if;
end if;
end process;
ifcchk : process(pciin.ifc)
begin
if init_done then
if pciin.ifc.frame = 'X' then
if dbglevel > 0 then
assert false
report " **"
severity warning;
printf("PCI_MONITOR: FRAME# line has multiple drivers.");
end if;
end if;
if pciin.ifc.irdy = 'X' then
if dbglevel > 0 then
assert false
report " **"
severity warning;
printf("PCI_MONITOR: IRDY# line has multiple drivers.");
end if;
end if;
if pciin.ifc.trdy = 'X' then
if dbglevel > 0 then
assert false
report " **"
severity warning;
printf("PCI_MONITOR: TRDY# line has multiple drivers.");
end if;
end if;
if pciin.ifc.stop = 'X' then
if dbglevel > 0 then
assert false
report " **"
severity warning;
printf("PCI_MONITOR: STOP# line has multiple drivers.");
end if;
end if;
if pciin.ifc.devsel = 'X' then
if dbglevel > 0 then
assert false
report " **"
severity warning;
printf("PCI_MONITOR: DEVSEL# line has multiple drivers.");
end if;
end if;
end if;
end process;
arbchk : process(pciin.arb)
variable gnt_set : boolean;
begin
gnt_set := false;
if init_done then
for i in 0 to 20 loop
if pciin.arb.gnt(i) = '0' then
if gnt_set then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: GNT# is asserted for more than one PCI master.");
end if;
else gnt_set := true; end if;
end if;
end loop;
end if;
end process;
end;
-- pragma translate_on
| gpl-3.0 | a0ad3011d7ca6290f4f5f595c8cccf8d | 0.529567 | 3.755133 | false | false | false | false |
kdgwill/VHDL_Framer_Example | VHDL_Framer_Example/Example1/tb_ramIntro.vhd | 1 | 4,735 | ---------------------------------------------------------------------------------
--Project Test Bench------------------------------------------------------------
--By Kyle Williams, 04/07/2011--------------------------------------------------
--PROJECT DESCRIPTION------------------------------------------------------------
--1--Input Serial data stream----------------------------------------------------
--2--Detect a start of Frame whose pattern is 10101011----------------------------
--3--After frame detect take every 8 bits and store them in a ram----------------
--4--After 8 bytes have been written in the ram start reading the data from the ram
--5--check that data read from ram matches what was written in the ram-----------
---------------------------------------------------------------------------------
----------------Define Libraries to be used--------------------------------------
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_unsigned.all ;
-----------------ENTITY FOR TEST BENCH------------------------------------------
ENTITY tb_ramIntro IS
GENERIC ( bits : INTEGER := 8); -- # of bits per word
END tb_ramIntro;
-----------------BEHAVIOR OF TEST BENCH-----------------------------------------
ARCHITECTURE tb_ramIntro of tb_ramIntro IS
-----------------COMPONENT INITIALIZATIONS--------------------------------------
COMPONENT generator
Generic(N : Integer := 8);
PORT(
clock, reset, load: OUT std_logic;
D : OUT std_logic_vector(n-1 downto 0);
vec : OUT std_logic_vector(N-1 downto 0);
sin : OUT STD_Logic
);
END COMPONENT;
COMPONENT receiver
PORT ( reset : IN STD_Logic;
clock : IN STD_LOGIC;
rec_in : IN STD_LOGIC;
enable : OUT STD_LOGIC;
rec_out : OUT STD_LOGIC_VECTOR (bits -1 DOWNTO 0)
);
End COMPONENT;
COMPONENT ramController
PORT ( reset : IN STD_Logic;
clock : IN STD_LOGIC;
enable : IN STD_LOGIC;
ctrl_in : IN STD_LOGIC_VECTOR (bits - 1 DOWNTO 0);
addr : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
wr_ena : OUT STD_LOGIC; -- write enable
ctrl_out : OUT STD_LOGIC_VECTOR (bits -1 DOWNTO 0)
);
End COMPONENT;
COMPONENT ram
PORT ( wr_ena : IN STD_LOGIC; -- write enable
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
addr : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
ram_in : IN STD_LOGIC_VECTOR (bits - 1 DOWNTO 0);
ram_out : OUT STD_LOGIC_VECTOR (bits -1 DOWNTO 0)
);
End COMPONENT;
COMPONENT dataValidation
PORT ( reset : IN STD_Logic;
clock : IN STD_LOGIC;
wr_ena : IN STD_LOGIC; -- write enable
enable : IN STD_LOGIC;
ctrl_out : IN STD_LOGIC_VECTOR (bits -1 DOWNTO 0);
ram_out : IN STD_LOGIC_VECTOR (bits -1 DOWNTO 0);
data_Valid : OUT STD_LOGIC;
validOffset : OUT Integer
);
End COMPONENT;
-------------------VARIABLE DECLARATION----------------------------------------
Signal clock : STD_LOGIC;
Signal reset : STD_LOGIC;
Signal load : STD_LOGIC;
Signal sin : STD_LOGIC;
Signal wr_enable : STD_LOGIC;
Signal enable : STD_LOGIC;
Signal data_Valid : STD_LOGIC;
Signal address : STD_LOGIC_VECTOR(5 DOWNTO 0);--2^6 bit address 64 possible locations
Signal D : STD_LOGIC_VECTOR(bits-1 Downto 0);
Signal rec_out : STD_LOGIC_VECTOR(bits-1 DOWNTO 0);
Signal ctrl_out : STD_LOGIC_VECTOR(bits-1 DOWNTO 0);
Signal ram_out : STD_LOGIC_VECTOR(bits-1 DOWNTO 0);
Signal validOffset : Integer;
-------------------BEGINING OF INSTRUCTIONS-----------------------------------
BEGIN
-------------------VARIABLE DECLARATIONS--------------------------------------
Gen: generator
PORT Map (sin=>sin, clock => clock, reset => reset, load => load);
recMod:receiver
PORT MAP( reset => reset, clock => clock, enable=>enable,rec_in => sin, rec_out => rec_out);
ctrlMod:ramController
PORT MAP( reset=> reset,clock => clock,enable=>enable,ctrl_in => rec_out,addr=> address,wr_ena=>wr_enable,ctrl_out => ctrl_out);
SRAM:ram
PORT MAP( wr_ena=>wr_enable,clock=>clock,reset=>reset,addr=>address,ram_in=>ctrl_out,ram_out=>ram_out);
valid:dataValidation
PORT MAP(reset=>reset,clock=>clock,wr_ena=>wr_enable,enable=>enable,ctrl_out=>ctrl_out,
ram_out=>ram_out,data_Valid=>data_Valid,validOffset=>validOffset);
-------------------ADDITIONAL INSTRUCTIONS--------------------------------------
--look into tb_ram_demo so you can add a check
END tb_ramIntro;
| gpl-3.0 | 10b2513bc0515dd3fe600e5be0306171 | 0.50264 | 4.113814 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/ddr/ahb2mig_7series_ddr2_dq16_ad13_ba3.vhd | 1 | 25,583 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: ahb2mig_7series_ddr2_dq16_ad13_ba3
-- File: ahb2mig_7series_ddr2_dq16_ad13_ba3.vhd
-- Author: Pascal Trotta
--
-- This is a AHB-2.0 interface for the Xilinx Virtex-7 MIG. (adapted from
-- ahb2mig_7series to work with 16-bit ddr2 memories)
-- Notes: - works only with 32-bit bus
-- - does not replicate output data
-- - does not support MIG interface model
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library gaisler;
use gaisler.all;
use gaisler.ahb2mig_7series_pkg.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use grlib.config_types.all;
use grlib.config.all;
library std;
use std.textio.all;
entity ahb2mig_7series_ddr2_dq16_ad13_ba3 is
generic(
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
maxwriteburst : integer := 8;
maxreadburst : integer := 8;
SIM_BYPASS_INIT_CAL : string := "OFF";
SIMULATION : string := "FALSE";
USE_MIG_INTERFACE_MODEL : boolean := false
);
port(
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0);
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_reset_n : out std_logic;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
calib_done : out std_logic;
rst_n_syn : in std_logic;
rst_n_async : in std_logic;
clk_amba : in std_logic;
sys_clk_i : in std_logic;
clk_ref_i : in std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic
);
end ;
architecture rtl of ahb2mig_7series_ddr2_dq16_ad13_ba3 is
type bstate_type is (idle, start, read_cmd, read_data, read_wait, read_output, write_cmd, write_burst);
constant maxburst : integer := 8;
constant maxmigcmds : integer := 3;
constant wrsteps : integer := log2(32);
constant wrmask : integer := log2(32/8);
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
others => zero32);
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, 0, 0),
1 => apb_iobar(paddr, pmask));
type reg_type is record
bstate : bstate_type;
cmd : std_logic_vector(2 downto 0);
cmd_en : std_logic;
wr_en : std_logic;
wr_end : std_logic;
cmd_count : unsigned(31 downto 0);
wr_count : unsigned(31 downto 0);
rd_count : unsigned(31 downto 0);
hready : std_logic;
hwrite : std_logic;
hwdata_burst : std_logic_vector(128*maxmigcmds-1 downto 0);
mask_burst : std_logic_vector(16*maxmigcmds-1 downto 0);
htrans : std_logic_vector(1 downto 0);
hburst : std_logic_vector(2 downto 0);
hsize : std_logic_vector(2 downto 0);
hrdata : std_logic_vector(AHBDW-1 downto 0);
haddr : std_logic_vector(31 downto 0);
haddr_start : std_logic_vector(31 downto 0);
haddr_offset : std_logic_vector(31 downto 0);
hmaster : std_logic_vector(3 downto 0);
int_buffer : unsigned(128*maxmigcmds-1 downto 0);
rd_buffer : unsigned(128*maxmigcmds-1 downto 0);
wdf_data_buffer : std_logic_vector(127 downto 0);
wdf_mask_buffer : std_logic_vector(15 downto 0);
migcommands : integer;
nxt : std_logic;
maxrburst : integer;
end record;
type mig_in_type is record
app_addr : std_logic_vector(26 downto 0);
app_cmd : std_logic_vector(2 downto 0);
app_en : std_logic;
app_wdf_data : std_logic_vector(127 downto 0);
app_wdf_end : std_logic;
app_wdf_mask : std_logic_vector(15 downto 0);
app_wdf_wren : std_logic;
end record;
type mig_out_type is record
app_rd_data : std_logic_vector(127 downto 0);
app_rd_data_end : std_logic;
app_rd_data_valid : std_logic;
app_rdy : std_logic;
app_wdf_rdy : std_logic;
end record;
signal rin, r, rnxt, rnxtin : reg_type;
signal migin : mig_in_type;
signal migout,migoutraw : mig_out_type;
component mig is
port (
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_dqs_n : inout std_logic_vector(1 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
sys_clk_i : in std_logic;
clk_ref_i : in std_logic;
app_addr : in std_logic_vector(26 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
app_en : in std_logic;
app_wdf_data : in std_logic_vector(127 downto 0);
app_wdf_end : in std_logic;
app_wdf_mask : in std_logic_vector(15 downto 0);
app_wdf_wren : in std_logic;
app_rd_data : out std_logic_vector(127 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
app_sr_req : in std_logic;
app_ref_req : in std_logic;
app_zq_req : in std_logic;
app_sr_active : out std_logic;
app_ref_ack : out std_logic;
app_zq_ack : out std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic;
init_calib_complete : out std_logic;
sys_rst : in std_logic
);
end component mig;
begin
comb: process( rst_n_syn, r, rin, ahbsi, migout )
-- Design temp variables
variable v,vnxt : reg_type;
variable writedata : std_logic_vector(255 downto 0);
variable wmask : std_logic_vector(AHBDW/4-1 downto 0);
variable shift_steps : natural;
variable hrdata_shift_steps : natural;
variable steps_write : unsigned(31 downto 0);
variable shift_steps_write : natural;
variable shift_steps_write_mask : natural;
variable startaddress : unsigned(v.haddr'length-1 downto 0);
variable start_address : std_logic_vector(v.haddr'length-1 downto 0);
variable step_offset : unsigned(steps_write'length-1 downto 0);
variable haddr_offset : unsigned(steps_write'length-1 downto 0);
begin
-- Make all register visible for the statemachine
v := r; vnxt := rnxt;
-- workout the start address in AHB2MIG buffer based upon
startaddress := resize(unsigned(unsigned(ahbsi.haddr(ahbsi.haddr'left-5 downto 4)) & "000"),startaddress'length);
-- Adjust offset in memory buffer
start_address := std_logic_vector(startaddress);
-- Workout local offset to be able to adust for warp-around
haddr_offset := unsigned(r.haddr_start) - unsigned(unsigned(r.haddr_offset(r.haddr_offset'length-1 downto 4))&"0000");
step_offset := resize(unsigned(haddr_offset(5 downto 4)&"00"),step_offset'length);
-- Fetch AMBA Commands
if (( ahbsi.hsel(hindex) and ahbsi.htrans(1) and ahbsi.hready and not ahbsi.htrans(0)) = '1'
and (ahbsi.hwrite = '0' or ahbsi.hwrite = '1' )) then
vnxt.cmd_count:= (others => '0');
vnxt.wr_count := (others => '0');
vnxt.rd_count := (others => '0');
vnxt.hrdata := (others => '0');
-- Clear old pointers and MIG command signals
vnxt.cmd := (others => '0');
vnxt.cmd_en := '0';
vnxt.wr_en := '0';
vnxt.wr_end := '0';
vnxt.hwrite := '0';
vnxt.hwdata_burst := (others => '0');
vnxt.mask_burst := (others => '0');
-- Hold info regarding transaction and execute
vnxt.hburst := ahbsi.hburst;
vnxt.hwrite := ahbsi.hwrite;
vnxt.hsize := ahbsi.hsize;
vnxt.hmaster := ahbsi.hmaster;
vnxt.hready := '0';
vnxt.htrans := ahbsi.htrans;
vnxt.bstate := start;
vnxt.haddr := start_address;
vnxt.haddr_start := ahbsi.haddr;
vnxt.haddr_offset := ahbsi.haddr;
vnxt.cmd(2 downto 0) := (others => '0');
vnxt.cmd(0) := not ahbsi.hwrite;
if (r.bstate = idle) then vnxt.nxt := '0'; else vnxt.nxt := '1'; end if;
-- Clear some old stuff
vnxt.int_buffer := (others => '0');
vnxt.rd_buffer := (others => '0');
vnxt.wdf_data_buffer := (others => '0');
vnxt.wdf_mask_buffer := (others => '0');
end if;
case r.bstate is
when idle =>
-- Clear old pointers and MIG command signals
v.cmd := (others => '0');
v.cmd_en := '0';
v.wr_en := '0';
v.wr_end := '0';
v.hready := '1';
v.hwrite := '0';
v.hwdata_burst := (others => '0');
v.mask_burst := (others => '0');
v.rd_count := (others => '0');
vnxt.cmd := (others => '0');
vnxt.cmd_en := '0';
vnxt.wr_en := '0';
vnxt.wr_end := '0';
vnxt.hready := '1';
vnxt.hwrite := '0';
vnxt.hwdata_burst := (others => '0');
vnxt.mask_burst := (others => '0');
vnxt.rd_count := (others => '0');
vnxt.wr_count := (others => '0');
vnxt.cmd_count := (others => '0');
-- Check if this is a single or burst transfer (and not a BUSY transfer)
if (( ahbsi.hsel(hindex) and ahbsi.htrans(1) and ahbsi.hready) = '1'
and (ahbsi.hwrite = '0' or ahbsi.hwrite = '1' )) then
-- Hold info regarding transaction and execute
v.hburst := ahbsi.hburst;
v.hwrite := ahbsi.hwrite;
v.hsize := ahbsi.hsize;
v.hmaster := ahbsi.hmaster;
v.hready := '0';
v.htrans := ahbsi.htrans;
v.bstate := start;
v.haddr := start_address;
v.haddr_start := ahbsi.haddr;
v.haddr_offset := ahbsi.haddr;
v.cmd := (others => '0');
v.cmd(0) := not ahbsi.hwrite;
end if;
when start =>
v.migcommands := nbrmigcmds16(r.hwrite,r.hsize,ahbsi.htrans,step_offset,AHBDW);
-- Check if a write command shall be issued to the DDR3 memory
if r.hwrite = '1' then
wmask := (others => '0');
writedata := (others => '0');
if ((ahbsi.htrans /= HTRANS_SEQ) or ((ahbsi.htrans = HTRANS_SEQ) and (r.rd_count > 0) and (r.rd_count <= maxburst))) then
-- work out how many steps we need to shift the input
steps_write := ahbselectdatanoreplicastep16(r.haddr_start(7 downto 2),r.hsize(2 downto 0)) + step_offset;
shift_steps_write := to_integer(shift_left(steps_write,wrsteps));
shift_steps_write_mask := to_integer(shift_left(steps_write,wrmask));
-- generate mask for complete burst (only need to use addr[3:0])
wmask := ahbselectdatanoreplicamask(r.haddr_start(6 downto 0),r.hsize(2 downto 0));
v.mask_burst := r.mask_burst or std_logic_vector(shift_left(resize(unsigned(wmask), r.mask_burst'length),shift_steps_write_mask));
-- fetch all wdata before write to memory can begin (only supports upto 128bits i.e. addr[4:0]
writedata(AHBDW-1 downto 0) := ahbselectdatanoreplica(ahbsi.hwdata(AHBDW-1 downto 0),r.haddr_start(4 downto 0),r.hsize(2 downto 0));
v.hwdata_burst := r.hwdata_burst or std_logic_vector(shift_left(resize(unsigned(writedata),v.hwdata_burst'length),shift_steps_write));
v.haddr_start := ahbsi.haddr;
end if;
-- Check if this is a cont burst longer than internal buffer
if (ahbsi.htrans = HTRANS_SEQ) then
if (r.rd_count < maxburst-1) then
v.hready := '1';
else
v.hready := '0';
end if;
if (r.rd_count >= maxburst) then
if (r.htrans = HTRANS_SEQ) then
v.bstate := write_cmd;
end if;
v.htrans := ahbsi.htrans;
end if;
else
v.bstate := write_cmd;
v.htrans := ahbsi.htrans;
end if;
-- Else issue a read command when ready
else
if migout.app_rdy = '1' and migout.app_wdf_rdy = '1' then
v.cmd := "001";
v.bstate := read_cmd;
v.htrans := ahbsi.htrans;
v.cmd_count := to_unsigned(0,v.cmd_count'length);
end if;
end if;
when write_cmd =>
-- Check if burst has ended due to max size burst
if (ahbsi.htrans /= HTRANS_SEQ) then
v.htrans := (others => '0');
end if;
-- Stop when addr and write command is accepted by mig
if (r.wr_count >= r.migcommands) and (r.cmd_count >= r.migcommands) then
if (r.htrans /= HTRANS_SEQ) then
-- Check if we have a pending transaction
if (vnxt.nxt = '1') then
v := vnxt;
vnxt.nxt := '0';
else
v.bstate := idle;
end if;
else -- Cont burst and work out new offset for next write command
v.bstate := write_burst;
v.hready := '1';
end if;
end if;
when write_burst =>
v.bstate := start;
v.hready := '0';
v.hwdata_burst := (others => '0');
v.mask_burst := (others => '0');
v.haddr := start_address;
v.haddr_offset := ahbsi.haddr;
-- Check if we have a pending transaction
if (vnxt.nxt = '1') then
v := vnxt;
vnxt.nxt := '0';
end if;
when read_cmd =>
v.hready := '0';
v.rd_count := (others => '0');
-- stop when read command is accepted ny mig.
if (r.cmd_count >= r.migcommands) then
v.bstate := read_data;
--v.int_buffer := (others => '0');
end if;
when read_data =>
-- We are not ready yet so issue a read command to the memory controller
v.hready := '0';
-- If read data is valid store data in buffers
if (migout.app_rd_data_valid = '1') then
v.rd_count := r.rd_count + 1;
-- Viviado seems to misinterpet the following shift construct and
-- therefore changed to a if-else statement
--v.int_buffer := r.int_buffer or shift_left( resize(unsigned(migout.app_rd_data),r.int_buffer'length),
-- to_integer(shift_left(r.rd_count,9)));
if (r.rd_count = 0) then
v.int_buffer(127 downto 0) := unsigned(migout.app_rd_data);
elsif (r.rd_count = 1) then
v.int_buffer(255 downto 128) := unsigned(migout.app_rd_data);
end if;
end if;
if (r.rd_count >= r.migcommands) then
v.rd_buffer := r.int_buffer;
v.bstate := read_output;
v.rd_count := to_unsigned(0,v.rd_count'length);
end if;
when read_output =>
-- Data is fetched from memory and ready to be transfered
v.hready := '1';
-- uses the "wr_count" signal to keep track of number of bytes output'd to AHB
-- Select correct 32bit output
v.hrdata := ahbselectdatanoreplicaoutput16(r.haddr_start(7 downto 0),r.wr_count,r.hsize,r.rd_buffer,r.wr_count,false);
-- Count number of bytes send
v.wr_count := r.wr_count + 1;
-- Set maximum read burst depending on the starting address offset
case r.haddr_start(3 downto 2) is
when "01" => v.maxrburst := 7;
when "10" => v.maxrburst := 6;
when "11" => v.maxrburst := 5;
when others => v.maxrburst := 8;
end case;
-- Check if this was the last transaction
if (r.wr_count >= v.maxrburst-1) then
v.bstate := read_wait;
end if;
-- Check if transfer was interrupted or no burst
if (ahbsi.htrans = HTRANS_IDLE) or ((ahbsi.htrans = HTRANS_NONSEQ) and (r.wr_count < maxburst)) then
v.bstate := read_wait;
v.wr_count := (others => '0');
v.rd_count := (others => '0');
v.cmd_count := (others => '0');
-- Check if we have a pending transaction
if (vnxt.nxt = '1') then
v := vnxt;
vnxt.nxt := '0';
v.bstate := start;
end if;
end if;
when read_wait =>
if ((r.wr_count >= v.maxrburst) and (ahbsi.htrans = HTRANS_SEQ)) then
v.hready := '0';
v.bstate := start;
v.haddr_start := ahbsi.haddr;
v.haddr := start_address;
v.haddr_offset := ahbsi.haddr;
else
-- Check if we have a pending transaction
if (vnxt.nxt = '1') then
v := vnxt;
vnxt.nxt := '0';
v.bstate := start;
else
v.bstate := idle;
v.hready := '1';
end if;
end if;
when others =>
v.bstate := idle;
end case;
if ((ahbsi.htrans /= HTRANS_SEQ) and (r.bstate = start)) then
v.hready := '0';
end if;
if rst_n_syn = '0' then
v.bstate := idle; v.hready := '1'; v.cmd_en := '0'; v.wr_en := '0'; v.wr_end := '0'; v.maxrburst := maxburst;
end if;
rin <= v;
rnxtin <= vnxt;
end process;
ahbso.hready <= r.hready;
ahbso.hresp <= "00";
ahbso.hrdata <= ahbdrivedata(r.hrdata);
migin.app_addr <= r.haddr(26 downto 2) & "00";
migin.app_cmd <= r.cmd;
migin.app_en <= r.cmd_en;
migin.app_wdf_data <= r.wdf_data_buffer;
migin.app_wdf_end <= r.wr_end;
migin.app_wdf_mask <= r.wdf_mask_buffer;
migin.app_wdf_wren <= r.wr_en;
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
apbo.pirq <= (others => '0');
apbo.prdata <= (others => '0');
regs : process(clk_amba)
begin
if rising_edge(clk_amba) then
-- Copy variables into registers (Default values)
r <= rin;
rnxt <= rnxtin;
-- add extra pipe-stage for read data
migout <= migoutraw;
-- IDLE Clear
if ((r.bstate = idle) or (r.bstate = read_wait)) then
r.cmd_count <= (others => '0');
r.wr_count <= (others => '0');
r.rd_count <= (others => '0');
end if;
if (r.bstate = write_burst) then
r.cmd_count <= (others => '0');
r.wr_count <= (others => '0');
r.rd_count <= to_unsigned(1,r.rd_count'length);
end if;
-- Read AHB write data
if (r.bstate = start) and (r.hwrite = '1') then
r.rd_count <= r.rd_count + 1;
end if;
-- Write command repsonse
if r.bstate = write_cmd then
if (r.cmd_count < 1) then
r.cmd_en <= '1';
end if;
if (migoutraw.app_rdy = '1') and (r.cmd_en = '1' ) then
r.cmd_count <= r.cmd_count + 1;
if (r.cmd_count < r.migcommands-1 ) then
r.haddr <= r.haddr + 8;
end if;
if (r.cmd_count >= r.migcommands-1) then
r.cmd_en <= '0';
end if;
end if;
if (r.wr_count < 1 ) then
r.wr_en <= '1';
r.wr_end <= '1';
r.wdf_mask_buffer <= not r.mask_burst(15 downto 0);
r.wdf_data_buffer <= r.hwdata_burst(127 downto 0);
end if;
if (migoutraw.app_wdf_rdy = '1') and (r.wr_en = '1' ) then
if (r.wr_count = 0) then
r.wdf_mask_buffer <= not r.mask_burst(31 downto 16);
r.wdf_data_buffer <= r.hwdata_burst(255 downto 128);
elsif (r.wr_count = 1) then --to support 3 migcmds
r.wdf_mask_buffer <= not r.mask_burst(47 downto 32);
r.wdf_data_buffer <= r.hwdata_burst(383 downto 256);
else
r.wdf_mask_buffer <= not r.mask_burst(31 downto 16);
r.wdf_data_buffer <= r.hwdata_burst(255 downto 128);
end if;
r.wr_count <= r.wr_count + 1;
if (r.wr_count >= r.migcommands - 1) then
r.wr_en <= '0';
r.wr_end <= '0';
end if;
end if;
end if;
-- Burst Write Wait
if r.bstate = write_burst then
r.cmd_count <= (others => '0');
r.wr_count <= (others => '0');
r.rd_count <= (others => '0');
end if;
-- Read command repsonse
if r.bstate = read_cmd then
if (r.cmd_count < 1) then
r.cmd_en <= '1';
end if;
if (migoutraw.app_rdy = '1') and (r.cmd_en = '1' ) then
r.cmd_count <= r.cmd_count + 1;
if (r.cmd_count < r.migcommands-1 ) then
r.haddr <= r.haddr + 8;
end if;
if (r.cmd_count >= r.migcommands-1) then
r.cmd_en <= '0';
end if;
end if;
end if;
end if;
end process;
MCB_inst : mig
port map (
ddr2_dq => ddr2_dq,
ddr2_dqs_p => ddr2_dqs_p,
ddr2_dqs_n => ddr2_dqs_n,
ddr2_addr => ddr2_addr,
ddr2_ba => ddr2_ba,
ddr2_ras_n => ddr2_ras_n,
ddr2_cas_n => ddr2_cas_n,
ddr2_we_n => ddr2_we_n,
ddr2_ck_p => ddr2_ck_p,
ddr2_ck_n => ddr2_ck_n,
ddr2_cke => ddr2_cke,
ddr2_cs_n => ddr2_cs_n,
ddr2_dm => ddr2_dm,
ddr2_odt => ddr2_odt,
sys_clk_i => sys_clk_i,
clk_ref_i => clk_ref_i,
app_addr => migin.app_addr,
app_cmd => migin.app_cmd,
app_en => migin.app_en,
app_rdy => migoutraw.app_rdy,
app_wdf_data => migin.app_wdf_data,
app_wdf_end => migin.app_wdf_end,
app_wdf_mask => migin.app_wdf_mask,
app_wdf_wren => migin.app_wdf_wren,
app_wdf_rdy => migoutraw.app_wdf_rdy,
app_rd_data => migoutraw.app_rd_data,
app_rd_data_end => migoutraw.app_rd_data_end,
app_rd_data_valid => migoutraw.app_rd_data_valid,
app_sr_req => '0',
app_ref_req => '0',
app_zq_req => '0',
app_sr_active => open,
app_ref_ack => open,
app_zq_ack => open,
ui_clk => ui_clk,
ui_clk_sync_rst => ui_clk_sync_rst,
init_calib_complete => calib_done,
sys_rst => rst_n_async
);
end;
| gpl-3.0 | 5ae25942654ed53f6304f8e30a1b596d | 0.522339 | 3.44645 | false | false | false | false |
hoglet67/CoPro6502 | client/6809/102d/tuberom_6809.vhd | 1 | 86,728 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tuberom_6809 is
port (
CLK : in std_logic;
ADDR : in std_logic_vector(10 downto 0);
DATA : out std_logic_vector(7 downto 0)
);
end;
architecture RTL of tuberom_6809 is
signal rom_addr : std_logic_vector(11 downto 0);
begin
p_addr : process(ADDR)
begin
rom_addr <= (others => '0');
rom_addr(10 downto 0) <= ADDR;
end process;
p_rom : process
begin
wait until rising_edge(CLK);
DATA <= (others => '0');
case rom_addr is
when x"000" => DATA <= x"F8";
when x"001" => DATA <= x"2C";
when x"002" => DATA <= x"F8";
when x"003" => DATA <= x"71";
when x"004" => DATA <= x"FF";
when x"005" => DATA <= x"E0";
when x"006" => DATA <= x"F8";
when x"007" => DATA <= x"EA";
when x"008" => DATA <= x"F8";
when x"009" => DATA <= x"FE";
when x"00A" => DATA <= x"FF";
when x"00B" => DATA <= x"EE";
when x"00C" => DATA <= x"F8";
when x"00D" => DATA <= x"F3";
when x"00E" => DATA <= x"FF";
when x"00F" => DATA <= x"E7";
when x"010" => DATA <= x"F8";
when x"011" => DATA <= x"F0";
when x"012" => DATA <= x"F8";
when x"013" => DATA <= x"E9";
when x"014" => DATA <= x"20";
when x"015" => DATA <= x"5B";
when x"016" => DATA <= x"0D";
when x"017" => DATA <= x"36";
when x"018" => DATA <= x"38";
when x"019" => DATA <= x"30";
when x"01A" => DATA <= x"39";
when x"01B" => DATA <= x"20";
when x"01C" => DATA <= x"54";
when x"01D" => DATA <= x"55";
when x"01E" => DATA <= x"42";
when x"01F" => DATA <= x"45";
when x"020" => DATA <= x"20";
when x"021" => DATA <= x"36";
when x"022" => DATA <= x"34";
when x"023" => DATA <= x"4B";
when x"024" => DATA <= x"20";
when x"025" => DATA <= x"31";
when x"026" => DATA <= x"2E";
when x"027" => DATA <= x"30";
when x"028" => DATA <= x"32";
when x"029" => DATA <= x"64";
when x"02A" => DATA <= x"0D";
when x"02B" => DATA <= x"00";
when x"02C" => DATA <= x"1A";
when x"02D" => DATA <= x"50";
when x"02E" => DATA <= x"10";
when x"02F" => DATA <= x"CE";
when x"030" => DATA <= x"F8";
when x"031" => DATA <= x"00";
when x"032" => DATA <= x"1F";
when x"033" => DATA <= x"41";
when x"034" => DATA <= x"EC";
when x"035" => DATA <= x"84";
when x"036" => DATA <= x"ED";
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when x"23D" => DATA <= x"F5";
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when x"247" => DATA <= x"53";
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when x"24A" => DATA <= x"8C";
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when x"24E" => DATA <= x"12";
when x"24F" => DATA <= x"E6";
when x"250" => DATA <= x"07";
when x"251" => DATA <= x"3A";
when x"252" => DATA <= x"CE";
when x"253" => DATA <= x"FA";
when x"254" => DATA <= x"AA";
when x"255" => DATA <= x"C6";
when x"256" => DATA <= x"04";
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when x"258" => DATA <= x"80";
when x"259" => DATA <= x"A1";
when x"25A" => DATA <= x"C2";
when x"25B" => DATA <= x"26";
when x"25C" => DATA <= x"3F";
when x"25D" => DATA <= x"5A";
when x"25E" => DATA <= x"26";
when x"25F" => DATA <= x"F7";
when x"260" => DATA <= x"A6";
when x"261" => DATA <= x"26";
when x"262" => DATA <= x"48";
when x"263" => DATA <= x"2A";
when x"264" => DATA <= x"45";
when x"265" => DATA <= x"84";
when x"266" => DATA <= x"1E";
when x"267" => DATA <= x"81";
when x"268" => DATA <= x"06";
when x"269" => DATA <= x"26";
when x"26A" => DATA <= x"3F";
when x"26B" => DATA <= x"30";
when x"26C" => DATA <= x"1C";
when x"26D" => DATA <= x"BF";
when x"26E" => DATA <= x"FF";
when x"26F" => DATA <= x"82";
when x"270" => DATA <= x"FE";
when x"271" => DATA <= x"FF";
when x"272" => DATA <= x"90";
when x"273" => DATA <= x"BE";
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when x"276" => DATA <= x"35";
when x"277" => DATA <= x"02";
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when x"27A" => DATA <= x"10";
when x"27B" => DATA <= x"8C";
when x"27C" => DATA <= x"80";
when x"27D" => DATA <= x"00";
when x"27E" => DATA <= x"25";
when x"27F" => DATA <= x"04";
when x"280" => DATA <= x"10";
when x"281" => DATA <= x"BF";
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when x"283" => DATA <= x"8A";
when x"284" => DATA <= x"10";
when x"285" => DATA <= x"BF";
when x"286" => DATA <= x"FF";
when x"287" => DATA <= x"8E";
when x"288" => DATA <= x"BE";
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when x"28A" => DATA <= x"86";
when x"28B" => DATA <= x"EE";
when x"28C" => DATA <= x"66";
when x"28D" => DATA <= x"46";
when x"28E" => DATA <= x"86";
when x"28F" => DATA <= x"01";
when x"290" => DATA <= x"AD";
when x"291" => DATA <= x"A4";
when x"292" => DATA <= x"35";
when x"293" => DATA <= x"60";
when x"294" => DATA <= x"10";
when x"295" => DATA <= x"BF";
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when x"297" => DATA <= x"8A";
when x"298" => DATA <= x"FF";
when x"299" => DATA <= x"FF";
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when x"29B" => DATA <= x"39";
when x"29C" => DATA <= x"BE";
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when x"29F" => DATA <= x"EE";
when x"2A0" => DATA <= x"63";
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when x"2A2" => DATA <= x"35";
when x"2A3" => DATA <= x"01";
when x"2A4" => DATA <= x"6E";
when x"2A5" => DATA <= x"A4";
when x"2A6" => DATA <= x"29";
when x"2A7" => DATA <= x"43";
when x"2A8" => DATA <= x"28";
when x"2A9" => DATA <= x"00";
when x"2AA" => DATA <= x"35";
when x"2AB" => DATA <= x"01";
when x"2AC" => DATA <= x"10";
when x"2AD" => DATA <= x"24";
when x"2AE" => DATA <= x"05";
when x"2AF" => DATA <= x"09";
when x"2B0" => DATA <= x"BD";
when x"2B1" => DATA <= x"F8";
when x"2B2" => DATA <= x"CD";
when x"2B3" => DATA <= x"3F";
when x"2B4" => DATA <= x"F9";
when x"2B5" => DATA <= x"4E";
when x"2B6" => DATA <= x"6F";
when x"2B7" => DATA <= x"74";
when x"2B8" => DATA <= x"20";
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when x"2BA" => DATA <= x"38";
when x"2BB" => DATA <= x"30";
when x"2BC" => DATA <= x"39";
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when x"2BE" => DATA <= x"63";
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when x"2C0" => DATA <= x"64";
when x"2C1" => DATA <= x"65";
when x"2C2" => DATA <= x"00";
when x"2C3" => DATA <= x"4F";
when x"2C4" => DATA <= x"BD";
when x"2C5" => DATA <= x"FC";
when x"2C6" => DATA <= x"F5";
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when x"2C8" => DATA <= x"02";
when x"2C9" => DATA <= x"8B";
when x"2CA" => DATA <= x"80";
when x"2CB" => DATA <= x"B6";
when x"2CC" => DATA <= x"FE";
when x"2CD" => DATA <= x"E2";
when x"2CE" => DATA <= x"2A";
when x"2CF" => DATA <= x"FB";
when x"2D0" => DATA <= x"B6";
when x"2D1" => DATA <= x"FE";
when x"2D2" => DATA <= x"E3";
when x"2D3" => DATA <= x"39";
when x"2D4" => DATA <= x"34";
when x"2D5" => DATA <= x"06";
when x"2D6" => DATA <= x"4D";
when x"2D7" => DATA <= x"2B";
when x"2D8" => DATA <= x"23";
when x"2D9" => DATA <= x"86";
when x"2DA" => DATA <= x"04";
when x"2DB" => DATA <= x"BD";
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when x"2DD" => DATA <= x"F5";
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when x"2E0" => DATA <= x"BD";
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when x"2E2" => DATA <= x"F3";
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when x"2E4" => DATA <= x"06";
when x"2E5" => DATA <= x"34";
when x"2E6" => DATA <= x"06";
when x"2E7" => DATA <= x"BD";
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when x"2E9" => DATA <= x"F5";
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when x"2EB" => DATA <= x"DF";
when x"2EC" => DATA <= x"1F";
when x"2ED" => DATA <= x"89";
when x"2EE" => DATA <= x"4F";
when x"2EF" => DATA <= x"1F";
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when x"2F1" => DATA <= x"35";
when x"2F2" => DATA <= x"86";
when x"2F3" => DATA <= x"8E";
when x"2F4" => DATA <= x"F8";
when x"2F5" => DATA <= x"16";
when x"2F6" => DATA <= x"BF";
when x"2F7" => DATA <= x"FF";
when x"2F8" => DATA <= x"86";
when x"2F9" => DATA <= x"7E";
when x"2FA" => DATA <= x"FA";
when x"2FB" => DATA <= x"41";
when x"2FC" => DATA <= x"81";
when x"2FD" => DATA <= x"82";
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when x"2FF" => DATA <= x"39";
when x"300" => DATA <= x"81";
when x"301" => DATA <= x"83";
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when x"303" => DATA <= x"37";
when x"304" => DATA <= x"81";
when x"305" => DATA <= x"84";
when x"306" => DATA <= x"27";
when x"307" => DATA <= x"33";
when x"308" => DATA <= x"86";
when x"309" => DATA <= x"06";
when x"30A" => DATA <= x"BD";
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when x"30C" => DATA <= x"F5";
when x"30D" => DATA <= x"1F";
when x"30E" => DATA <= x"10";
when x"30F" => DATA <= x"BD";
when x"310" => DATA <= x"FC";
when x"311" => DATA <= x"F3";
when x"312" => DATA <= x"BD";
when x"313" => DATA <= x"FC";
when x"314" => DATA <= x"F1";
when x"315" => DATA <= x"35";
when x"316" => DATA <= x"06";
when x"317" => DATA <= x"BD";
when x"318" => DATA <= x"FC";
when x"319" => DATA <= x"F5";
when x"31A" => DATA <= x"81";
when x"31B" => DATA <= x"9D";
when x"31C" => DATA <= x"27";
when x"31D" => DATA <= x"B5";
when x"31E" => DATA <= x"81";
when x"31F" => DATA <= x"8E";
when x"320" => DATA <= x"27";
when x"321" => DATA <= x"D1";
when x"322" => DATA <= x"34";
when x"323" => DATA <= x"06";
when x"324" => DATA <= x"8D";
when x"325" => DATA <= x"A5";
when x"326" => DATA <= x"8B";
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when x"328" => DATA <= x"34";
when x"329" => DATA <= x"01";
when x"32A" => DATA <= x"8D";
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when x"32C" => DATA <= x"1F";
when x"32D" => DATA <= x"89";
when x"32E" => DATA <= x"4F";
when x"32F" => DATA <= x"1F";
when x"330" => DATA <= x"02";
when x"331" => DATA <= x"8D";
when x"332" => DATA <= x"98";
when x"333" => DATA <= x"1E";
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when x"335" => DATA <= x"1F";
when x"336" => DATA <= x"01";
when x"337" => DATA <= x"35";
when x"338" => DATA <= x"87";
when x"339" => DATA <= x"86";
when x"33A" => DATA <= x"88";
when x"33B" => DATA <= x"48";
when x"33C" => DATA <= x"8E";
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when x"33E" => DATA <= x"82";
when x"33F" => DATA <= x"EC";
when x"340" => DATA <= x"86";
when x"341" => DATA <= x"1F";
when x"342" => DATA <= x"01";
when x"343" => DATA <= x"1F";
when x"344" => DATA <= x"89";
when x"345" => DATA <= x"4F";
when x"346" => DATA <= x"1F";
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when x"348" => DATA <= x"35";
when x"349" => DATA <= x"86";
when x"34A" => DATA <= x"4D";
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when x"34C" => DATA <= x"5C";
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when x"34E" => DATA <= x"26";
when x"34F" => DATA <= x"34";
when x"350" => DATA <= x"10";
when x"351" => DATA <= x"1F";
when x"352" => DATA <= x"89";
when x"353" => DATA <= x"86";
when x"354" => DATA <= x"08";
when x"355" => DATA <= x"BD";
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when x"357" => DATA <= x"F5";
when x"358" => DATA <= x"BD";
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when x"35A" => DATA <= x"F3";
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when x"35C" => DATA <= x"2A";
when x"35D" => DATA <= x"04";
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when x"360" => DATA <= x"20";
when x"361" => DATA <= x"0C";
when x"362" => DATA <= x"86";
when x"363" => DATA <= x"10";
when x"364" => DATA <= x"C1";
when x"365" => DATA <= x"15";
when x"366" => DATA <= x"24";
when x"367" => DATA <= x"06";
when x"368" => DATA <= x"8E";
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when x"36A" => DATA <= x"D8";
when x"36B" => DATA <= x"3A";
when x"36C" => DATA <= x"A6";
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when x"36E" => DATA <= x"35";
when x"36F" => DATA <= x"10";
when x"370" => DATA <= x"BD";
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when x"372" => DATA <= x"F5";
when x"373" => DATA <= x"1F";
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when x"375" => DATA <= x"1E";
when x"376" => DATA <= x"89";
when x"377" => DATA <= x"4F";
when x"378" => DATA <= x"1E";
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when x"37A" => DATA <= x"4A";
when x"37B" => DATA <= x"2B";
when x"37C" => DATA <= x"03";
when x"37D" => DATA <= x"BD";
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when x"37F" => DATA <= x"C2";
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when x"381" => DATA <= x"10";
when x"382" => DATA <= x"5D";
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when x"384" => DATA <= x"04";
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when x"386" => DATA <= x"01";
when x"387" => DATA <= x"20";
when x"388" => DATA <= x"0C";
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when x"38A" => DATA <= x"10";
when x"38B" => DATA <= x"C1";
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when x"38D" => DATA <= x"24";
when x"38E" => DATA <= x"06";
when x"38F" => DATA <= x"8E";
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when x"391" => DATA <= x"EC";
when x"392" => DATA <= x"3A";
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when x"394" => DATA <= x"84";
when x"395" => DATA <= x"35";
when x"396" => DATA <= x"10";
when x"397" => DATA <= x"BD";
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when x"399" => DATA <= x"F5";
when x"39A" => DATA <= x"1F";
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when x"39C" => DATA <= x"1E";
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when x"39E" => DATA <= x"4F";
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when x"3A0" => DATA <= x"02";
when x"3A1" => DATA <= x"4A";
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when x"3A4" => DATA <= x"BD";
when x"3A5" => DATA <= x"FC";
when x"3A6" => DATA <= x"D2";
when x"3A7" => DATA <= x"35";
when x"3A8" => DATA <= x"A6";
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when x"3AA" => DATA <= x"0A";
when x"3AB" => DATA <= x"BD";
when x"3AC" => DATA <= x"FC";
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when x"3AE" => DATA <= x"30";
when x"3AF" => DATA <= x"02";
when x"3B0" => DATA <= x"10";
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when x"3B2" => DATA <= x"00";
when x"3B3" => DATA <= x"03";
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when x"3B5" => DATA <= x"FC";
when x"3B6" => DATA <= x"C2";
when x"3B7" => DATA <= x"30";
when x"3B8" => DATA <= x"1E";
when x"3B9" => DATA <= x"86";
when x"3BA" => DATA <= x"07";
when x"3BB" => DATA <= x"BD";
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when x"3BD" => DATA <= x"F5";
when x"3BE" => DATA <= x"4F";
when x"3BF" => DATA <= x"BD";
when x"3C0" => DATA <= x"FC";
when x"3C1" => DATA <= x"F5";
when x"3C2" => DATA <= x"BD";
when x"3C3" => DATA <= x"FA";
when x"3C4" => DATA <= x"CB";
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when x"3C7" => DATA <= x"25";
when x"3C8" => DATA <= x"0F";
when x"3C9" => DATA <= x"AE";
when x"3CA" => DATA <= x"84";
when x"3CB" => DATA <= x"BD";
when x"3CC" => DATA <= x"FA";
when x"3CD" => DATA <= x"CB";
when x"3CE" => DATA <= x"A7";
when x"3CF" => DATA <= x"80";
when x"3D0" => DATA <= x"31";
when x"3D1" => DATA <= x"21";
when x"3D2" => DATA <= x"81";
when x"3D3" => DATA <= x"0D";
when x"3D4" => DATA <= x"26";
when x"3D5" => DATA <= x"F5";
when x"3D6" => DATA <= x"31";
when x"3D7" => DATA <= x"3F";
when x"3D8" => DATA <= x"39";
when x"3D9" => DATA <= x"00";
when x"3DA" => DATA <= x"05";
when x"3DB" => DATA <= x"00";
when x"3DC" => DATA <= x"05";
when x"3DD" => DATA <= x"04";
when x"3DE" => DATA <= x"05";
when x"3DF" => DATA <= x"08";
when x"3E0" => DATA <= x"0E";
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when x"3E2" => DATA <= x"01";
when x"3E3" => DATA <= x"01";
when x"3E4" => DATA <= x"05";
when x"3E5" => DATA <= x"00";
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when x"3E7" => DATA <= x"20";
when x"3E8" => DATA <= x"10";
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when x"3EA" => DATA <= x"00";
when x"3EB" => DATA <= x"04";
when x"3EC" => DATA <= x"80";
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when x"3EE" => DATA <= x"00";
when x"3EF" => DATA <= x"05";
when x"3F0" => DATA <= x"00";
when x"3F1" => DATA <= x"05";
when x"3F2" => DATA <= x"00";
when x"3F3" => DATA <= x"00";
when x"3F4" => DATA <= x"00";
when x"3F5" => DATA <= x"05";
when x"3F6" => DATA <= x"09";
when x"3F7" => DATA <= x"05";
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when x"3F9" => DATA <= x"08";
when x"3FA" => DATA <= x"19";
when x"3FB" => DATA <= x"00";
when x"3FC" => DATA <= x"01";
when x"3FD" => DATA <= x"0D";
when x"3FE" => DATA <= x"80";
when x"3FF" => DATA <= x"04";
when x"400" => DATA <= x"80";
when x"401" => DATA <= x"34";
when x"402" => DATA <= x"26";
when x"403" => DATA <= x"86";
when x"404" => DATA <= x"0C";
when x"405" => DATA <= x"BD";
when x"406" => DATA <= x"FC";
when x"407" => DATA <= x"F5";
when x"408" => DATA <= x"BD";
when x"409" => DATA <= x"FC";
when x"40A" => DATA <= x"F1";
when x"40B" => DATA <= x"10";
when x"40C" => DATA <= x"8E";
when x"40D" => DATA <= x"00";
when x"40E" => DATA <= x"04";
when x"40F" => DATA <= x"BD";
when x"410" => DATA <= x"FC";
when x"411" => DATA <= x"C2";
when x"412" => DATA <= x"35";
when x"413" => DATA <= x"06";
when x"414" => DATA <= x"BD";
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when x"416" => DATA <= x"F5";
when x"417" => DATA <= x"BD";
when x"418" => DATA <= x"FA";
when x"419" => DATA <= x"CB";
when x"41A" => DATA <= x"34";
when x"41B" => DATA <= x"02";
when x"41C" => DATA <= x"10";
when x"41D" => DATA <= x"8E";
when x"41E" => DATA <= x"00";
when x"41F" => DATA <= x"04";
when x"420" => DATA <= x"BD";
when x"421" => DATA <= x"FC";
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when x"423" => DATA <= x"35";
when x"424" => DATA <= x"A2";
when x"425" => DATA <= x"34";
when x"426" => DATA <= x"04";
when x"427" => DATA <= x"86";
when x"428" => DATA <= x"0E";
when x"429" => DATA <= x"BD";
when x"42A" => DATA <= x"FC";
when x"42B" => DATA <= x"F5";
when x"42C" => DATA <= x"BD";
when x"42D" => DATA <= x"FC";
when x"42E" => DATA <= x"F1";
when x"42F" => DATA <= x"35";
when x"430" => DATA <= x"04";
when x"431" => DATA <= x"7E";
when x"432" => DATA <= x"FA";
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when x"434" => DATA <= x"34";
when x"435" => DATA <= x"06";
when x"436" => DATA <= x"86";
when x"437" => DATA <= x"10";
when x"438" => DATA <= x"BD";
when x"439" => DATA <= x"FC";
when x"43A" => DATA <= x"F5";
when x"43B" => DATA <= x"BD";
when x"43C" => DATA <= x"FC";
when x"43D" => DATA <= x"F1";
when x"43E" => DATA <= x"35";
when x"43F" => DATA <= x"06";
when x"440" => DATA <= x"34";
when x"441" => DATA <= x"06";
when x"442" => DATA <= x"BD";
when x"443" => DATA <= x"FC";
when x"444" => DATA <= x"F5";
when x"445" => DATA <= x"BD";
when x"446" => DATA <= x"FA";
when x"447" => DATA <= x"CB";
when x"448" => DATA <= x"35";
when x"449" => DATA <= x"86";
when x"44A" => DATA <= x"34";
when x"44B" => DATA <= x"06";
when x"44C" => DATA <= x"86";
when x"44D" => DATA <= x"12";
when x"44E" => DATA <= x"BD";
when x"44F" => DATA <= x"FC";
when x"450" => DATA <= x"F5";
when x"451" => DATA <= x"35";
when x"452" => DATA <= x"06";
when x"453" => DATA <= x"BD";
when x"454" => DATA <= x"FC";
when x"455" => DATA <= x"F5";
when x"456" => DATA <= x"4D";
when x"457" => DATA <= x"27";
when x"458" => DATA <= x"06";
when x"459" => DATA <= x"BD";
when x"45A" => DATA <= x"FC";
when x"45B" => DATA <= x"B9";
when x"45C" => DATA <= x"7E";
when x"45D" => DATA <= x"FA";
when x"45E" => DATA <= x"CB";
when x"45F" => DATA <= x"34";
when x"460" => DATA <= x"04";
when x"461" => DATA <= x"BD";
when x"462" => DATA <= x"FC";
when x"463" => DATA <= x"F1";
when x"464" => DATA <= x"BD";
when x"465" => DATA <= x"FA";
when x"466" => DATA <= x"CB";
when x"467" => DATA <= x"4F";
when x"468" => DATA <= x"35";
when x"469" => DATA <= x"84";
when x"46A" => DATA <= x"34";
when x"46B" => DATA <= x"32";
when x"46C" => DATA <= x"86";
when x"46D" => DATA <= x"14";
when x"46E" => DATA <= x"BD";
when x"46F" => DATA <= x"FC";
when x"470" => DATA <= x"F5";
when x"471" => DATA <= x"30";
when x"472" => DATA <= x"02";
when x"473" => DATA <= x"10";
when x"474" => DATA <= x"8E";
when x"475" => DATA <= x"00";
when x"476" => DATA <= x"10";
when x"477" => DATA <= x"BD";
when x"478" => DATA <= x"FC";
when x"479" => DATA <= x"C2";
when x"47A" => DATA <= x"30";
when x"47B" => DATA <= x"1E";
when x"47C" => DATA <= x"AE";
when x"47D" => DATA <= x"84";
when x"47E" => DATA <= x"BD";
when x"47F" => DATA <= x"FC";
when x"480" => DATA <= x"B9";
when x"481" => DATA <= x"35";
when x"482" => DATA <= x"02";
when x"483" => DATA <= x"BD";
when x"484" => DATA <= x"FC";
when x"485" => DATA <= x"F5";
when x"486" => DATA <= x"BD";
when x"487" => DATA <= x"FA";
when x"488" => DATA <= x"CB";
when x"489" => DATA <= x"35";
when x"48A" => DATA <= x"10";
when x"48B" => DATA <= x"34";
when x"48C" => DATA <= x"02";
when x"48D" => DATA <= x"30";
when x"48E" => DATA <= x"02";
when x"48F" => DATA <= x"10";
when x"490" => DATA <= x"8E";
when x"491" => DATA <= x"00";
when x"492" => DATA <= x"10";
when x"493" => DATA <= x"BD";
when x"494" => DATA <= x"FC";
when x"495" => DATA <= x"D2";
when x"496" => DATA <= x"30";
when x"497" => DATA <= x"1E";
when x"498" => DATA <= x"35";
when x"499" => DATA <= x"A2";
when x"49A" => DATA <= x"34";
when x"49B" => DATA <= x"22";
when x"49C" => DATA <= x"86";
when x"49D" => DATA <= x"16";
when x"49E" => DATA <= x"BD";
when x"49F" => DATA <= x"FC";
when x"4A0" => DATA <= x"F5";
when x"4A1" => DATA <= x"10";
when x"4A2" => DATA <= x"8E";
when x"4A3" => DATA <= x"00";
when x"4A4" => DATA <= x"0D";
when x"4A5" => DATA <= x"BD";
when x"4A6" => DATA <= x"FC";
when x"4A7" => DATA <= x"C2";
when x"4A8" => DATA <= x"35";
when x"4A9" => DATA <= x"02";
when x"4AA" => DATA <= x"BD";
when x"4AB" => DATA <= x"FC";
when x"4AC" => DATA <= x"F5";
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when x"4AE" => DATA <= x"8E";
when x"4AF" => DATA <= x"00";
when x"4B0" => DATA <= x"0D";
when x"4B1" => DATA <= x"BD";
when x"4B2" => DATA <= x"FC";
when x"4B3" => DATA <= x"D2";
when x"4B4" => DATA <= x"35";
when x"4B5" => DATA <= x"20";
when x"4B6" => DATA <= x"7E";
when x"4B7" => DATA <= x"FA";
when x"4B8" => DATA <= x"C7";
when x"4B9" => DATA <= x"A6";
when x"4BA" => DATA <= x"80";
when x"4BB" => DATA <= x"8D";
when x"4BC" => DATA <= x"38";
when x"4BD" => DATA <= x"81";
when x"4BE" => DATA <= x"0D";
when x"4BF" => DATA <= x"26";
when x"4C0" => DATA <= x"F8";
when x"4C1" => DATA <= x"39";
when x"4C2" => DATA <= x"34";
when x"4C3" => DATA <= x"04";
when x"4C4" => DATA <= x"1F";
when x"4C5" => DATA <= x"20";
when x"4C6" => DATA <= x"3A";
when x"4C7" => DATA <= x"35";
when x"4C8" => DATA <= x"04";
when x"4C9" => DATA <= x"A6";
when x"4CA" => DATA <= x"82";
when x"4CB" => DATA <= x"8D";
when x"4CC" => DATA <= x"28";
when x"4CD" => DATA <= x"31";
when x"4CE" => DATA <= x"3F";
when x"4CF" => DATA <= x"26";
when x"4D0" => DATA <= x"F8";
when x"4D1" => DATA <= x"39";
when x"4D2" => DATA <= x"34";
when x"4D3" => DATA <= x"04";
when x"4D4" => DATA <= x"1F";
when x"4D5" => DATA <= x"20";
when x"4D6" => DATA <= x"3A";
when x"4D7" => DATA <= x"35";
when x"4D8" => DATA <= x"04";
when x"4D9" => DATA <= x"BD";
when x"4DA" => DATA <= x"FA";
when x"4DB" => DATA <= x"CB";
when x"4DC" => DATA <= x"A7";
when x"4DD" => DATA <= x"82";
when x"4DE" => DATA <= x"31";
when x"4DF" => DATA <= x"3F";
when x"4E0" => DATA <= x"26";
when x"4E1" => DATA <= x"F7";
when x"4E2" => DATA <= x"39";
when x"4E3" => DATA <= x"34";
when x"4E4" => DATA <= x"02";
when x"4E5" => DATA <= x"B6";
when x"4E6" => DATA <= x"FE";
when x"4E7" => DATA <= x"E0";
when x"4E8" => DATA <= x"48";
when x"4E9" => DATA <= x"2A";
when x"4EA" => DATA <= x"FA";
when x"4EB" => DATA <= x"35";
when x"4EC" => DATA <= x"02";
when x"4ED" => DATA <= x"B7";
when x"4EE" => DATA <= x"FE";
when x"4EF" => DATA <= x"E1";
when x"4F0" => DATA <= x"39";
when x"4F1" => DATA <= x"1F";
when x"4F2" => DATA <= x"20";
when x"4F3" => DATA <= x"1F";
when x"4F4" => DATA <= x"98";
when x"4F5" => DATA <= x"34";
when x"4F6" => DATA <= x"02";
when x"4F7" => DATA <= x"B6";
when x"4F8" => DATA <= x"FE";
when x"4F9" => DATA <= x"E2";
when x"4FA" => DATA <= x"48";
when x"4FB" => DATA <= x"2A";
when x"4FC" => DATA <= x"FA";
when x"4FD" => DATA <= x"35";
when x"4FE" => DATA <= x"02";
when x"4FF" => DATA <= x"B7";
when x"500" => DATA <= x"FE";
when x"501" => DATA <= x"E3";
when x"502" => DATA <= x"39";
when x"503" => DATA <= x"34";
when x"504" => DATA <= x"02";
when x"505" => DATA <= x"B6";
when x"506" => DATA <= x"FE";
when x"507" => DATA <= x"E6";
when x"508" => DATA <= x"2B";
when x"509" => DATA <= x"51";
when x"50A" => DATA <= x"B6";
when x"50B" => DATA <= x"FE";
when x"50C" => DATA <= x"E0";
when x"50D" => DATA <= x"2B";
when x"50E" => DATA <= x"06";
when x"50F" => DATA <= x"35";
when x"510" => DATA <= x"02";
when x"511" => DATA <= x"6E";
when x"512" => DATA <= x"9F";
when x"513" => DATA <= x"FF";
when x"514" => DATA <= x"B1";
when x"515" => DATA <= x"B6";
when x"516" => DATA <= x"FE";
when x"517" => DATA <= x"E1";
when x"518" => DATA <= x"2B";
when x"519" => DATA <= x"1B";
when x"51A" => DATA <= x"35";
when x"51B" => DATA <= x"02";
when x"51C" => DATA <= x"34";
when x"51D" => DATA <= x"76";
when x"51E" => DATA <= x"8D";
when x"51F" => DATA <= x"1C";
when x"520" => DATA <= x"1F";
when x"521" => DATA <= x"89";
when x"522" => DATA <= x"4F";
when x"523" => DATA <= x"1F";
when x"524" => DATA <= x"02";
when x"525" => DATA <= x"8D";
when x"526" => DATA <= x"15";
when x"527" => DATA <= x"1F";
when x"528" => DATA <= x"89";
when x"529" => DATA <= x"4F";
when x"52A" => DATA <= x"1F";
when x"52B" => DATA <= x"01";
when x"52C" => DATA <= x"8D";
when x"52D" => DATA <= x"0E";
when x"52E" => DATA <= x"AD";
when x"52F" => DATA <= x"9F";
when x"530" => DATA <= x"FF";
when x"531" => DATA <= x"FC";
when x"532" => DATA <= x"35";
when x"533" => DATA <= x"76";
when x"534" => DATA <= x"3B";
when x"535" => DATA <= x"48";
when x"536" => DATA <= x"B7";
when x"537" => DATA <= x"FF";
when x"538" => DATA <= x"80";
when x"539" => DATA <= x"35";
when x"53A" => DATA <= x"02";
when x"53B" => DATA <= x"3B";
when x"53C" => DATA <= x"B6";
when x"53D" => DATA <= x"FE";
when x"53E" => DATA <= x"E6";
when x"53F" => DATA <= x"2A";
when x"540" => DATA <= x"02";
when x"541" => DATA <= x"8D";
when x"542" => DATA <= x"12";
when x"543" => DATA <= x"B6";
when x"544" => DATA <= x"FE";
when x"545" => DATA <= x"E0";
when x"546" => DATA <= x"2A";
when x"547" => DATA <= x"F4";
when x"548" => DATA <= x"B6";
when x"549" => DATA <= x"FE";
when x"54A" => DATA <= x"E1";
when x"54B" => DATA <= x"39";
when x"54C" => DATA <= x"B6";
when x"54D" => DATA <= x"FE";
when x"54E" => DATA <= x"E6";
when x"54F" => DATA <= x"2A";
when x"550" => DATA <= x"FB";
when x"551" => DATA <= x"B6";
when x"552" => DATA <= x"FE";
when x"553" => DATA <= x"E7";
when x"554" => DATA <= x"39";
when x"555" => DATA <= x"1C";
when x"556" => DATA <= x"7F";
when x"557" => DATA <= x"34";
when x"558" => DATA <= x"01";
when x"559" => DATA <= x"34";
when x"55A" => DATA <= x"02";
when x"55B" => DATA <= x"35";
when x"55C" => DATA <= x"02";
when x"55D" => DATA <= x"34";
when x"55E" => DATA <= x"16";
when x"55F" => DATA <= x"B6";
when x"560" => DATA <= x"FE";
when x"561" => DATA <= x"E7";
when x"562" => DATA <= x"2A";
when x"563" => DATA <= x"22";
when x"564" => DATA <= x"10";
when x"565" => DATA <= x"CE";
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when x"567" => DATA <= x"80";
when x"568" => DATA <= x"8E";
when x"569" => DATA <= x"FF";
when x"56A" => DATA <= x"00";
when x"56B" => DATA <= x"BD";
when x"56C" => DATA <= x"FA";
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when x"56E" => DATA <= x"86";
when x"56F" => DATA <= x"3F";
when x"570" => DATA <= x"A7";
when x"571" => DATA <= x"80";
when x"572" => DATA <= x"BD";
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when x"575" => DATA <= x"A7";
when x"576" => DATA <= x"80";
when x"577" => DATA <= x"BD";
when x"578" => DATA <= x"FA";
when x"579" => DATA <= x"CB";
when x"57A" => DATA <= x"A7";
when x"57B" => DATA <= x"80";
when x"57C" => DATA <= x"26";
when x"57D" => DATA <= x"F9";
when x"57E" => DATA <= x"8E";
when x"57F" => DATA <= x"FF";
when x"580" => DATA <= x"01";
when x"581" => DATA <= x"34";
when x"582" => DATA <= x"10";
when x"583" => DATA <= x"7E";
when x"584" => DATA <= x"FF";
when x"585" => DATA <= x"BC";
when x"586" => DATA <= x"34";
when x"587" => DATA <= x"02";
when x"588" => DATA <= x"8D";
when x"589" => DATA <= x"C2";
when x"58A" => DATA <= x"35";
when x"58B" => DATA <= x"02";
when x"58C" => DATA <= x"81";
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when x"58F" => DATA <= x"06";
when x"590" => DATA <= x"7F";
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when x"593" => DATA <= x"35";
when x"594" => DATA <= x"16";
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when x"598" => DATA <= x"8D";
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when x"59A" => DATA <= x"8D";
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when x"59C" => DATA <= x"8D";
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when x"5A0" => DATA <= x"8D";
when x"5A1" => DATA <= x"AA";
when x"5A2" => DATA <= x"1E";
when x"5A3" => DATA <= x"89";
when x"5A4" => DATA <= x"1F";
when x"5A5" => DATA <= x"01";
when x"5A6" => DATA <= x"86";
when x"5A7" => DATA <= x"FF";
when x"5A8" => DATA <= x"B7";
when x"5A9" => DATA <= x"FF";
when x"5AA" => DATA <= x"94";
when x"5AB" => DATA <= x"1C";
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when x"5AD" => DATA <= x"8D";
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when x"5AF" => DATA <= x"A6";
when x"5B0" => DATA <= x"E0";
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when x"5B2" => DATA <= x"66";
when x"5B3" => DATA <= x"81";
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when x"5B5" => DATA <= x"25";
when x"5B6" => DATA <= x"55";
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when x"5B8" => DATA <= x"43";
when x"5B9" => DATA <= x"81";
when x"5BA" => DATA <= x"04";
when x"5BB" => DATA <= x"25";
when x"5BC" => DATA <= x"2F";
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when x"5BE" => DATA <= x"69";
when x"5BF" => DATA <= x"5F";
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when x"5C1" => DATA <= x"07";
when x"5C2" => DATA <= x"25";
when x"5C3" => DATA <= x"11";
when x"5C4" => DATA <= x"26";
when x"5C5" => DATA <= x"65";
when x"5C6" => DATA <= x"B6";
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when x"5C8" => DATA <= x"E4";
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when x"5CA" => DATA <= x"FB";
when x"5CB" => DATA <= x"B6";
when x"5CC" => DATA <= x"FE";
when x"5CD" => DATA <= x"E5";
when x"5CE" => DATA <= x"A7";
when x"5CF" => DATA <= x"80";
when x"5D0" => DATA <= x"5A";
when x"5D1" => DATA <= x"26";
when x"5D2" => DATA <= x"F3";
when x"5D3" => DATA <= x"20";
when x"5D4" => DATA <= x"56";
when x"5D5" => DATA <= x"B6";
when x"5D6" => DATA <= x"FE";
when x"5D7" => DATA <= x"E4";
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when x"5D9" => DATA <= x"FB";
when x"5DA" => DATA <= x"A6";
when x"5DB" => DATA <= x"80";
when x"5DC" => DATA <= x"B7";
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when x"5DE" => DATA <= x"E5";
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when x"5E0" => DATA <= x"26";
when x"5E1" => DATA <= x"F3";
when x"5E2" => DATA <= x"B6";
when x"5E3" => DATA <= x"FE";
when x"5E4" => DATA <= x"E4";
when x"5E5" => DATA <= x"2A";
when x"5E6" => DATA <= x"FB";
when x"5E7" => DATA <= x"B7";
when x"5E8" => DATA <= x"FE";
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when x"5EA" => DATA <= x"20";
when x"5EB" => DATA <= x"3F";
when x"5EC" => DATA <= x"13";
when x"5ED" => DATA <= x"B6";
when x"5EE" => DATA <= x"FF";
when x"5EF" => DATA <= x"94";
when x"5F0" => DATA <= x"27";
when x"5F1" => DATA <= x"39";
when x"5F2" => DATA <= x"B6";
when x"5F3" => DATA <= x"FE";
when x"5F4" => DATA <= x"E5";
when x"5F5" => DATA <= x"F6";
when x"5F6" => DATA <= x"FE";
when x"5F7" => DATA <= x"E5";
when x"5F8" => DATA <= x"ED";
when x"5F9" => DATA <= x"81";
when x"5FA" => DATA <= x"20";
when x"5FB" => DATA <= x"F0";
when x"5FC" => DATA <= x"13";
when x"5FD" => DATA <= x"B6";
when x"5FE" => DATA <= x"FF";
when x"5FF" => DATA <= x"94";
when x"600" => DATA <= x"27";
when x"601" => DATA <= x"29";
when x"602" => DATA <= x"EC";
when x"603" => DATA <= x"81";
when x"604" => DATA <= x"B7";
when x"605" => DATA <= x"FE";
when x"606" => DATA <= x"E5";
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when x"608" => DATA <= x"FE";
when x"609" => DATA <= x"E5";
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when x"60B" => DATA <= x"F0";
when x"60C" => DATA <= x"13";
when x"60D" => DATA <= x"B6";
when x"60E" => DATA <= x"FF";
when x"60F" => DATA <= x"94";
when x"610" => DATA <= x"27";
when x"611" => DATA <= x"19";
when x"612" => DATA <= x"B6";
when x"613" => DATA <= x"FE";
when x"614" => DATA <= x"E5";
when x"615" => DATA <= x"A7";
when x"616" => DATA <= x"80";
when x"617" => DATA <= x"20";
when x"618" => DATA <= x"F3";
when x"619" => DATA <= x"13";
when x"61A" => DATA <= x"B6";
when x"61B" => DATA <= x"FF";
when x"61C" => DATA <= x"94";
when x"61D" => DATA <= x"27";
when x"61E" => DATA <= x"0C";
when x"61F" => DATA <= x"A6";
when x"620" => DATA <= x"80";
when x"621" => DATA <= x"B7";
when x"622" => DATA <= x"FE";
when x"623" => DATA <= x"E5";
when x"624" => DATA <= x"20";
when x"625" => DATA <= x"F3";
when x"626" => DATA <= x"20";
when x"627" => DATA <= x"03";
when x"628" => DATA <= x"BF";
when x"629" => DATA <= x"FF";
when x"62A" => DATA <= x"8C";
when x"62B" => DATA <= x"35";
when x"62C" => DATA <= x"16";
when x"62D" => DATA <= x"3B";
when x"62E" => DATA <= x"32";
when x"62F" => DATA <= x"6A";
when x"630" => DATA <= x"35";
when x"631" => DATA <= x"10";
when x"632" => DATA <= x"BF";
when x"633" => DATA <= x"FF";
when x"634" => DATA <= x"82";
when x"635" => DATA <= x"1C";
when x"636" => DATA <= x"00";
when x"637" => DATA <= x"6E";
when x"638" => DATA <= x"9F";
when x"639" => DATA <= x"FF";
when x"63A" => DATA <= x"FA";
when x"63B" => DATA <= x"FF";
when x"63C" => DATA <= x"FF";
when x"63D" => DATA <= x"FF";
when x"63E" => DATA <= x"FF";
when x"63F" => DATA <= x"FF";
when x"640" => DATA <= x"FF";
when x"641" => DATA <= x"FF";
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when x"643" => DATA <= x"FF";
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when x"646" => DATA <= x"FF";
when x"647" => DATA <= x"FF";
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when x"64A" => DATA <= x"FF";
when x"64B" => DATA <= x"FF";
when x"64C" => DATA <= x"FF";
when x"64D" => DATA <= x"FF";
when x"64E" => DATA <= x"FF";
when x"64F" => DATA <= x"FF";
when x"650" => DATA <= x"FF";
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when x"656" => DATA <= x"FF";
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when x"65A" => DATA <= x"FF";
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when x"65C" => DATA <= x"FF";
when x"65D" => DATA <= x"FF";
when x"65E" => DATA <= x"FF";
when x"65F" => DATA <= x"FF";
when x"660" => DATA <= x"FF";
when x"661" => DATA <= x"FF";
when x"662" => DATA <= x"FF";
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when x"665" => DATA <= x"FF";
when x"666" => DATA <= x"FF";
when x"667" => DATA <= x"FF";
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when x"66A" => DATA <= x"FF";
when x"66B" => DATA <= x"FF";
when x"66C" => DATA <= x"FF";
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when x"66E" => DATA <= x"FF";
when x"66F" => DATA <= x"FF";
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when x"671" => DATA <= x"FF";
when x"672" => DATA <= x"FF";
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when x"675" => DATA <= x"FF";
when x"676" => DATA <= x"FF";
when x"677" => DATA <= x"FF";
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when x"67A" => DATA <= x"FF";
when x"67B" => DATA <= x"FF";
when x"67C" => DATA <= x"FF";
when x"67D" => DATA <= x"FF";
when x"67E" => DATA <= x"FF";
when x"67F" => DATA <= x"FF";
when x"680" => DATA <= x"FF";
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when x"682" => DATA <= x"FF";
when x"683" => DATA <= x"FF";
when x"684" => DATA <= x"FF";
when x"685" => DATA <= x"FF";
when x"686" => DATA <= x"FF";
when x"687" => DATA <= x"FF";
when x"688" => DATA <= x"FF";
when x"689" => DATA <= x"FF";
when x"68A" => DATA <= x"FF";
when x"68B" => DATA <= x"FF";
when x"68C" => DATA <= x"FF";
when x"68D" => DATA <= x"FF";
when x"68E" => DATA <= x"FF";
when x"68F" => DATA <= x"FF";
when x"690" => DATA <= x"FF";
when x"691" => DATA <= x"FF";
when x"692" => DATA <= x"FF";
when x"693" => DATA <= x"FF";
when x"694" => DATA <= x"FF";
when x"695" => DATA <= x"FF";
when x"696" => DATA <= x"FF";
when x"697" => DATA <= x"FF";
when x"698" => DATA <= x"FF";
when x"699" => DATA <= x"FF";
when x"69A" => DATA <= x"FF";
when x"69B" => DATA <= x"FF";
when x"69C" => DATA <= x"FF";
when x"69D" => DATA <= x"FF";
when x"69E" => DATA <= x"FF";
when x"69F" => DATA <= x"FF";
when x"6A0" => DATA <= x"FF";
when x"6A1" => DATA <= x"FF";
when x"6A2" => DATA <= x"FF";
when x"6A3" => DATA <= x"FF";
when x"6A4" => DATA <= x"FF";
when x"6A5" => DATA <= x"FF";
when x"6A6" => DATA <= x"FF";
when x"6A7" => DATA <= x"FF";
when x"6A8" => DATA <= x"FF";
when x"6A9" => DATA <= x"FF";
when x"6AA" => DATA <= x"FF";
when x"6AB" => DATA <= x"FF";
when x"6AC" => DATA <= x"FF";
when x"6AD" => DATA <= x"FF";
when x"6AE" => DATA <= x"FF";
when x"6AF" => DATA <= x"FF";
when x"6B0" => DATA <= x"FF";
when x"6B1" => DATA <= x"FF";
when x"6B2" => DATA <= x"FF";
when x"6B3" => DATA <= x"FF";
when x"6B4" => DATA <= x"FF";
when x"6B5" => DATA <= x"FF";
when x"6B6" => DATA <= x"FF";
when x"6B7" => DATA <= x"FF";
when x"6B8" => DATA <= x"FF";
when x"6B9" => DATA <= x"FF";
when x"6BA" => DATA <= x"FF";
when x"6BB" => DATA <= x"FF";
when x"6BC" => DATA <= x"FF";
when x"6BD" => DATA <= x"FF";
when x"6BE" => DATA <= x"FF";
when x"6BF" => DATA <= x"FF";
when x"6C0" => DATA <= x"FF";
when x"6C1" => DATA <= x"FF";
when x"6C2" => DATA <= x"FF";
when x"6C3" => DATA <= x"FF";
when x"6C4" => DATA <= x"FF";
when x"6C5" => DATA <= x"FF";
when x"6C6" => DATA <= x"FF";
when x"6C7" => DATA <= x"FF";
when x"6C8" => DATA <= x"FF";
when x"6C9" => DATA <= x"FF";
when x"6CA" => DATA <= x"FF";
when x"6CB" => DATA <= x"FF";
when x"6CC" => DATA <= x"FF";
when x"6CD" => DATA <= x"FF";
when x"6CE" => DATA <= x"FF";
when x"6CF" => DATA <= x"FF";
when x"6D0" => DATA <= x"FF";
when x"6D1" => DATA <= x"FF";
when x"6D2" => DATA <= x"FF";
when x"6D3" => DATA <= x"FF";
when x"6D4" => DATA <= x"FF";
when x"6D5" => DATA <= x"FF";
when x"6D6" => DATA <= x"FF";
when x"6D7" => DATA <= x"FF";
when x"6D8" => DATA <= x"FF";
when x"6D9" => DATA <= x"FF";
when x"6DA" => DATA <= x"FF";
when x"6DB" => DATA <= x"FF";
when x"6DC" => DATA <= x"FF";
when x"6DD" => DATA <= x"FF";
when x"6DE" => DATA <= x"FF";
when x"6DF" => DATA <= x"FF";
when x"6E0" => DATA <= x"00";
when x"6E1" => DATA <= x"00";
when x"6E2" => DATA <= x"00";
when x"6E3" => DATA <= x"00";
when x"6E4" => DATA <= x"00";
when x"6E5" => DATA <= x"00";
when x"6E6" => DATA <= x"00";
when x"6E7" => DATA <= x"00";
when x"6E8" => DATA <= x"FF";
when x"6E9" => DATA <= x"FF";
when x"6EA" => DATA <= x"FF";
when x"6EB" => DATA <= x"FF";
when x"6EC" => DATA <= x"FF";
when x"6ED" => DATA <= x"FF";
when x"6EE" => DATA <= x"FF";
when x"6EF" => DATA <= x"FF";
when x"6F0" => DATA <= x"FE";
when x"6F1" => DATA <= x"2D";
when x"6F2" => DATA <= x"FE";
when x"6F3" => DATA <= x"2D";
when x"6F4" => DATA <= x"FE";
when x"6F5" => DATA <= x"2D";
when x"6F6" => DATA <= x"FD";
when x"6F7" => DATA <= x"03";
when x"6F8" => DATA <= x"FE";
when x"6F9" => DATA <= x"2D";
when x"6FA" => DATA <= x"FE";
when x"6FB" => DATA <= x"2E";
when x"6FC" => DATA <= x"FE";
when x"6FD" => DATA <= x"2D";
when x"6FE" => DATA <= x"F8";
when x"6FF" => DATA <= x"2C";
when x"700" => DATA <= x"00";
when x"701" => DATA <= x"00";
when x"702" => DATA <= x"00";
when x"703" => DATA <= x"00";
when x"704" => DATA <= x"00";
when x"705" => DATA <= x"00";
when x"706" => DATA <= x"00";
when x"707" => DATA <= x"00";
when x"708" => DATA <= x"00";
when x"709" => DATA <= x"00";
when x"70A" => DATA <= x"00";
when x"70B" => DATA <= x"00";
when x"70C" => DATA <= x"00";
when x"70D" => DATA <= x"00";
when x"70E" => DATA <= x"00";
when x"70F" => DATA <= x"00";
when x"710" => DATA <= x"00";
when x"711" => DATA <= x"00";
when x"712" => DATA <= x"00";
when x"713" => DATA <= x"00";
when x"714" => DATA <= x"00";
when x"715" => DATA <= x"00";
when x"716" => DATA <= x"00";
when x"717" => DATA <= x"00";
when x"718" => DATA <= x"00";
when x"719" => DATA <= x"00";
when x"71A" => DATA <= x"00";
when x"71B" => DATA <= x"00";
when x"71C" => DATA <= x"00";
when x"71D" => DATA <= x"00";
when x"71E" => DATA <= x"00";
when x"71F" => DATA <= x"00";
when x"720" => DATA <= x"00";
when x"721" => DATA <= x"00";
when x"722" => DATA <= x"00";
when x"723" => DATA <= x"00";
when x"724" => DATA <= x"00";
when x"725" => DATA <= x"00";
when x"726" => DATA <= x"00";
when x"727" => DATA <= x"00";
when x"728" => DATA <= x"00";
when x"729" => DATA <= x"00";
when x"72A" => DATA <= x"00";
when x"72B" => DATA <= x"00";
when x"72C" => DATA <= x"00";
when x"72D" => DATA <= x"00";
when x"72E" => DATA <= x"00";
when x"72F" => DATA <= x"00";
when x"730" => DATA <= x"00";
when x"731" => DATA <= x"00";
when x"732" => DATA <= x"00";
when x"733" => DATA <= x"00";
when x"734" => DATA <= x"00";
when x"735" => DATA <= x"00";
when x"736" => DATA <= x"00";
when x"737" => DATA <= x"00";
when x"738" => DATA <= x"00";
when x"739" => DATA <= x"00";
when x"73A" => DATA <= x"00";
when x"73B" => DATA <= x"00";
when x"73C" => DATA <= x"00";
when x"73D" => DATA <= x"00";
when x"73E" => DATA <= x"00";
when x"73F" => DATA <= x"00";
when x"740" => DATA <= x"00";
when x"741" => DATA <= x"00";
when x"742" => DATA <= x"00";
when x"743" => DATA <= x"00";
when x"744" => DATA <= x"00";
when x"745" => DATA <= x"00";
when x"746" => DATA <= x"00";
when x"747" => DATA <= x"00";
when x"748" => DATA <= x"00";
when x"749" => DATA <= x"00";
when x"74A" => DATA <= x"00";
when x"74B" => DATA <= x"00";
when x"74C" => DATA <= x"00";
when x"74D" => DATA <= x"00";
when x"74E" => DATA <= x"00";
when x"74F" => DATA <= x"00";
when x"750" => DATA <= x"00";
when x"751" => DATA <= x"00";
when x"752" => DATA <= x"00";
when x"753" => DATA <= x"00";
when x"754" => DATA <= x"00";
when x"755" => DATA <= x"00";
when x"756" => DATA <= x"00";
when x"757" => DATA <= x"00";
when x"758" => DATA <= x"00";
when x"759" => DATA <= x"00";
when x"75A" => DATA <= x"00";
when x"75B" => DATA <= x"00";
when x"75C" => DATA <= x"00";
when x"75D" => DATA <= x"00";
when x"75E" => DATA <= x"00";
when x"75F" => DATA <= x"00";
when x"760" => DATA <= x"00";
when x"761" => DATA <= x"00";
when x"762" => DATA <= x"00";
when x"763" => DATA <= x"00";
when x"764" => DATA <= x"00";
when x"765" => DATA <= x"00";
when x"766" => DATA <= x"00";
when x"767" => DATA <= x"00";
when x"768" => DATA <= x"00";
when x"769" => DATA <= x"00";
when x"76A" => DATA <= x"00";
when x"76B" => DATA <= x"00";
when x"76C" => DATA <= x"00";
when x"76D" => DATA <= x"00";
when x"76E" => DATA <= x"00";
when x"76F" => DATA <= x"00";
when x"770" => DATA <= x"00";
when x"771" => DATA <= x"00";
when x"772" => DATA <= x"00";
when x"773" => DATA <= x"00";
when x"774" => DATA <= x"00";
when x"775" => DATA <= x"00";
when x"776" => DATA <= x"00";
when x"777" => DATA <= x"00";
when x"778" => DATA <= x"00";
when x"779" => DATA <= x"00";
when x"77A" => DATA <= x"00";
when x"77B" => DATA <= x"00";
when x"77C" => DATA <= x"00";
when x"77D" => DATA <= x"00";
when x"77E" => DATA <= x"00";
when x"77F" => DATA <= x"00";
when x"780" => DATA <= x"00";
when x"781" => DATA <= x"00";
when x"782" => DATA <= x"F8";
when x"783" => DATA <= x"16";
when x"784" => DATA <= x"F8";
when x"785" => DATA <= x"B0";
when x"786" => DATA <= x"F8";
when x"787" => DATA <= x"16";
when x"788" => DATA <= x"00";
when x"789" => DATA <= x"00";
when x"78A" => DATA <= x"F8";
when x"78B" => DATA <= x"00";
when x"78C" => DATA <= x"FF";
when x"78D" => DATA <= x"B9";
when x"78E" => DATA <= x"FF";
when x"78F" => DATA <= x"B9";
when x"790" => DATA <= x"FF";
when x"791" => DATA <= x"B9";
when x"792" => DATA <= x"00";
when x"793" => DATA <= x"00";
when x"794" => DATA <= x"00";
when x"795" => DATA <= x"7E";
when x"796" => DATA <= x"FA";
when x"797" => DATA <= x"9B";
when x"798" => DATA <= x"7E";
when x"799" => DATA <= x"F8";
when x"79A" => DATA <= x"2C";
when x"79B" => DATA <= x"7E";
when x"79C" => DATA <= x"FA";
when x"79D" => DATA <= x"9B";
when x"79E" => DATA <= x"7E";
when x"79F" => DATA <= x"FA";
when x"7A0" => DATA <= x"9B";
when x"7A1" => DATA <= x"7E";
when x"7A2" => DATA <= x"F9";
when x"7A3" => DATA <= x"3E";
when x"7A4" => DATA <= x"7E";
when x"7A5" => DATA <= x"FA";
when x"7A6" => DATA <= x"9B";
when x"7A7" => DATA <= x"7E";
when x"7A8" => DATA <= x"F8";
when x"7A9" => DATA <= x"71";
when x"7AA" => DATA <= x"7E";
when x"7AB" => DATA <= x"F9";
when x"7AC" => DATA <= x"17";
when x"7AD" => DATA <= x"7E";
when x"7AE" => DATA <= x"F9";
when x"7AF" => DATA <= x"0F";
when x"7B0" => DATA <= x"7E";
when x"7B1" => DATA <= x"FE";
when x"7B2" => DATA <= x"2D";
when x"7B3" => DATA <= x"7E";
when x"7B4" => DATA <= x"F9";
when x"7B5" => DATA <= x"2E";
when x"7B6" => DATA <= x"7E";
when x"7B7" => DATA <= x"FA";
when x"7B8" => DATA <= x"9B";
when x"7B9" => DATA <= x"7E";
when x"7BA" => DATA <= x"F8";
when x"7BB" => DATA <= x"71";
when x"7BC" => DATA <= x"7E";
when x"7BD" => DATA <= x"FE";
when x"7BE" => DATA <= x"30";
when x"7BF" => DATA <= x"7E";
when x"7C0" => DATA <= x"F8";
when x"7C1" => DATA <= x"D3";
when x"7C2" => DATA <= x"7E";
when x"7C3" => DATA <= x"FA";
when x"7C4" => DATA <= x"9B";
when x"7C5" => DATA <= x"7E";
when x"7C6" => DATA <= x"F9";
when x"7C7" => DATA <= x"35";
when x"7C8" => DATA <= x"7E";
when x"7C9" => DATA <= x"FA";
when x"7CA" => DATA <= x"9B";
when x"7CB" => DATA <= x"7E";
when x"7CC" => DATA <= x"FA";
when x"7CD" => DATA <= x"9B";
when x"7CE" => DATA <= x"7E";
when x"7CF" => DATA <= x"FC";
when x"7D0" => DATA <= x"4A";
when x"7D1" => DATA <= x"7E";
when x"7D2" => DATA <= x"FC";
when x"7D3" => DATA <= x"9A";
when x"7D4" => DATA <= x"7E";
when x"7D5" => DATA <= x"FC";
when x"7D6" => DATA <= x"34";
when x"7D7" => DATA <= x"7E";
when x"7D8" => DATA <= x"FC";
when x"7D9" => DATA <= x"25";
when x"7DA" => DATA <= x"7E";
when x"7DB" => DATA <= x"FC";
when x"7DC" => DATA <= x"01";
when x"7DD" => DATA <= x"7E";
when x"7DE" => DATA <= x"FC";
when x"7DF" => DATA <= x"6A";
when x"7E0" => DATA <= x"7E";
when x"7E1" => DATA <= x"FA";
when x"7E2" => DATA <= x"C3";
when x"7E3" => DATA <= x"81";
when x"7E4" => DATA <= x"0D";
when x"7E5" => DATA <= x"26";
when x"7E6" => DATA <= x"07";
when x"7E7" => DATA <= x"86";
when x"7E8" => DATA <= x"0A";
when x"7E9" => DATA <= x"BD";
when x"7EA" => DATA <= x"FF";
when x"7EB" => DATA <= x"EE";
when x"7EC" => DATA <= x"86";
when x"7ED" => DATA <= x"0D";
when x"7EE" => DATA <= x"7E";
when x"7EF" => DATA <= x"FC";
when x"7F0" => DATA <= x"E3";
when x"7F1" => DATA <= x"7E";
when x"7F2" => DATA <= x"FB";
when x"7F3" => DATA <= x"4A";
when x"7F4" => DATA <= x"7E";
when x"7F5" => DATA <= x"FA";
when x"7F6" => DATA <= x"D4";
when x"7F7" => DATA <= x"7E";
when x"7F8" => DATA <= x"F9";
when x"7F9" => DATA <= x"80";
when x"7FA" => DATA <= x"F8";
when x"7FB" => DATA <= x"B0";
when x"7FC" => DATA <= x"FA";
when x"7FD" => DATA <= x"9B";
when x"7FE" => DATA <= x"F8";
when x"7FF" => DATA <= x"2C";
when others => DATA <= (others => '0');
end case;
end process;
end RTL;
| gpl-3.0 | b404f5f918be7f7cd156d14145909bfe | 0.358731 | 2.974415 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/gencomp/gencomp.vhd | 1 | 93,253 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: gencomp
-- File: gencomp.vhd
-- Author: Jiri Gaisler et al. - Aeroflex Gaisler
-- Description: Declaration of portable memory modules, pads, e.t.c.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config.grlib_config_array;
use grlib.config_types.grlib_techmap_testin_extra;
package gencomp is
---------------------------------------------------------------------------
-- BASIC DECLARATIONS
---------------------------------------------------------------------------
-- technologies and libraries
constant NTECH : integer := 57;
type tech_ability_type is array (0 to NTECH) of integer;
constant inferred : integer := 0;
constant virtex : integer := 1;
constant virtex2 : integer := 2;
constant memvirage : integer := 3;
constant axcel : integer := 4;
constant proasic : integer := 5;
constant atc18s : integer := 6;
constant altera : integer := 7;
constant umc : integer := 8;
constant rhumc : integer := 9;
constant apa3 : integer := 10;
constant spartan3 : integer := 11;
constant ihp25 : integer := 12;
constant rhlib18t : integer := 13;
constant virtex4 : integer := 14;
constant lattice : integer := 15;
constant ut25 : integer := 16;
constant spartan3e : integer := 17;
constant peregrine : integer := 18;
constant memartisan : integer := 19;
constant virtex5 : integer := 20;
constant custom1 : integer := 21;
constant ihp25rh : integer := 22;
constant stratix1 : integer := 23;
constant stratix2 : integer := 24;
constant eclipse : integer := 25;
constant stratix3 : integer := 26;
constant cyclone3 : integer := 27;
constant memvirage90 : integer := 28;
constant tsmc90 : integer := 29;
constant easic90 : integer := 30;
constant atc18rha : integer := 31;
constant smic013 : integer := 32;
constant tm65gplus : integer := 33;
constant axdsp : integer := 34;
constant spartan6 : integer := 35;
constant virtex6 : integer := 36;
constant actfus : integer := 37;
constant stratix4 : integer := 38;
constant st65lp : integer := 39;
constant st65gp : integer := 40;
constant easic45 : integer := 41;
constant cmos9sf : integer := 42;
constant apa3e : integer := 43;
constant apa3l : integer := 44;
constant ut130 : integer := 45;
constant ut90 : integer := 46;
constant gf65 : integer := 47;
constant virtex7 : integer := 48;
constant kintex7 : integer := 49;
constant artix7 : integer := 50;
constant zynq7000 : integer := 51;
constant rhlib13t : integer := 52;
constant saed32 : integer := 53;
constant dare : integer := 54;
constant igloo2 : integer := 55;
constant smartfusion2: integer := 55;
constant rhs65 : integer := 56;
constant rtg4 : integer := 57;
constant DEFMEMTECH : integer := inferred;
constant DEFPADTECH : integer := inferred;
constant DEFFABTECH : integer := inferred;
constant is_fpga : tech_ability_type :=
(inferred => 1, virtex => 1, virtex2 => 1, axcel => 1,
proasic => 1, altera => 1, apa3 => 1, spartan3 => 1,
virtex4 => 1, lattice => 1, spartan3e => 1, virtex5 => 1,
stratix1 => 1, stratix2 => 1, eclipse => 1,
stratix3 => 1, cyclone3 => 1, axdsp => 1,
spartan6 => 1, virtex6 => 1, actfus => 1,
stratix4 => 1, apa3e => 1, apa3l => 1, virtex7 => 1, kintex7 => 1,
artix7 => 1, zynq7000 => 1, igloo2 => 1, rtg4 => 1,
others => 0);
constant infer_mul : tech_ability_type := is_fpga;
-- The write_through and dest_rw_collision tables should be set up
-- depending on how the raw memory cells behave on simultaneous read
-- and write to the same address:
-- write_through rw_collision | read-result write-result
-- 0 0 | undefined success
-- 1 0 | new write-data success
-- 0 1 | undefined wrong data written
--
-- If the write-through behavior is required by the IP, then set wrfst
-- on the syncram_2p instantiation and the syncram wrapper will add logic to
-- implement this if needed. The wrapper will also avoid simulatneous
-- read/write if rw_collision is set but this can only be done when the
-- read/write ports are known to be in the same clock domain (sepclk=0),
-- otherwise this requirement has to be managed at higher level.
constant syncram_2p_write_through : tech_ability_type :=
(rhumc => 1, eclipse => 1, others => 0);
constant regfile_3p_write_through : tech_ability_type :=
(rhumc => 1, ihp25 => 1, ihp25rh => 1, eclipse => 1, others => 0);
constant regfile_3p_infer : tech_ability_type :=
(inferred => 1, rhumc => 1, ihp25 => 1, rhlib18t => 0, ut90 => 1,
peregrine => 1, ihp25rh => 1, umc => 1, custom1 => 0, rhs65 => 1, others => 0);
constant syncram_2p_dest_rw_collision : tech_ability_type :=
(memartisan => 1, smic013 => 1, easic45 => 1, ut130 => 1, rhs65 => 0,
igloo2 => 1, rtg4 => 1, others => 0);
constant syncram_dp_dest_rw_collision : tech_ability_type :=
(memartisan => 1, smic013 => 1, easic45 => 1, others => 0);
-- The readhold table should be set to 1 if the techology mapping's
-- memory blocks keep the read-data bus stable at it's current value
-- when enable/renable is clocked in low any number of cycles after
-- a read.
constant syncram_readhold : tech_ability_type :=
(rhs65 => 1, others => 0);
constant syncram_2p_readhold : tech_ability_type :=
(rhs65 => 1, others => 0);
constant syncram_dp_readhold : tech_ability_type :=
(others => 0);
constant regfile_3p_readhold : tech_ability_type :=
(others => 0);
constant syncram_has_customif : tech_ability_type := (rhs65 => 1, others => 0);
constant syncram_customif_maxwidth: integer := 64; -- Expand as needed
-- Set to 1 to add input-to-output bypass logic during scan mode in the syncram
-- wrappers.
constant syncram_add_scan_bypass : tech_ability_type := (others => 0);
constant has_sram : tech_ability_type :=
(atc18s => 0, others => 1);
constant has_2pram : tech_ability_type :=
( atc18s => 0, umc => 0, rhumc => 0, ihp25 => 0, others => 1);
constant has_dpram : tech_ability_type :=
(virtex => 1, virtex2 => 1, memvirage => 1, axcel => 0,
altera => 1, apa3 => 1, spartan3 => 1, virtex4 => 1,
lattice => 1, spartan3e => 1, memartisan => 1, virtex5 => 1,
custom1 => 1, stratix1 => 1, stratix2 => 1, stratix3 => 1,
cyclone3 => 1, memvirage90 => 1, atc18rha => 1, smic013 => 1,
tm65gplus => 1, axdsp => 0, spartan6 => 1, virtex6 => 1,
actfus => 1, stratix4 => 1, easic45 => 1, apa3e => 1,
apa3l => 1, ut90 => 1, virtex7 => 1, kintex7 => 1, artix7 => 1, zynq7000 => 1,
dare => 1, igloo2 => 1, rtg4 => 1, others => 0);
constant has_sram64 : tech_ability_type :=
(inferred => 0, virtex2 => 1, spartan3 => 1, virtex4 => 1,
spartan3e => 1, memartisan => 1, virtex5 => 1, smic013 => 1,
spartan6 => 1, virtex6 => 1, easic45 => 1, virtex7 => 1, kintex7 => 1,
artix7 => 1, zynq7000 => 1, others => 0);
constant has_sram128bw : tech_ability_type := (
virtex2 => 1, virtex4 => 1, virtex5 => 1, spartan3 => 1,
spartan3e => 1, spartan6 => 1, virtex6 => 1, virtex7 => 1, kintex7 => 1,
altera => 1, cyclone3 => 1, stratix2 => 1, stratix3 => 1, stratix4 => 1,
ut90 => 1, others => 0);
constant has_sram128 : tech_ability_type := (
virtex2 => 1, virtex4 => 1, virtex5 => 1, spartan3 => 1,
spartan3e => 1, spartan6 => 1, virtex6 => 1, virtex7 => 1, kintex7 => 1,
tm65gplus => 0, easic45 => 1, others => 0);
constant has_sram156bw : tech_ability_type := (
virtex2 => 0, virtex4 => 0, virtex5 => 0, spartan3 => 0,
spartan3e => 0, spartan6 => 0, virtex6 => 0, virtex7 => 0, kintex7 => 0,
altera => 0, cyclone3 => 0, stratix2 => 0, stratix3 => 0, stratix4 => 0,
tm65gplus => 0, custom1 => 1, ut90 => 1, rhs65 => 1, others => 0);
constant has_sram256bw : tech_ability_type := (
virtex2 => 1, virtex4 => 1, virtex5 => 1, spartan3 => 1,
spartan3e => 1, spartan6 => 1, virtex6 => 1, virtex7 => 1, kintex7 => 1,
altera => 1, cyclone3 => 1, stratix2 => 1, stratix3 => 1, stratix4 => 1,
tm65gplus => 0, cmos9sf => 1, others => 0);
constant has_sram_2pbw : tech_ability_type := (
easic45 => 1, others => 0);
constant has_srambw : tech_ability_type := (easic45 => 1, virtex => 0, virtex2 => 0,
virtex4 => 0, virtex5 => 1, spartan3 => 0, spartan3e => 0, spartan6 => 0,
virtex6 => 1, virtex7 => 1, kintex7 => 1, artix7 => 1, zynq7000 => 1, rtg4 => 1,
igloo2 => 1, others => 0);
constant has_2pfifo : tech_ability_type := (
altera => 1, stratix1 => 1, stratix2 => 1, stratix3 => 1,
stratix4 => 1, others => 0);
-- ram_raw_latency - describes how many edges on the write-port clock that
-- must pass before data is commited to memory. for example, if the write data
-- is commited to memory on the falling edge after a write cycle, and is
-- available to the read port after a short T_{raw} then ram_raw_latency
-- should be set to 1. If the data is available to the read port immediately
-- after the write-port clock rising edge that latches the write operation then
-- ram_raw_latency(tech) should return 0. If T_{raw} cannot be assumed to be
-- negligible (for instance, it is longer than a clock cycle on the read port)
-- then the ram_raw_latency value should be increased to cover also T_{raw}.
-- this value is important for cores that use DP or 2P memories in CDC.
constant ram_raw_latency : tech_ability_type := (easic45 => 1, others => 0);
-- Support for target (memory) technology FT features
-- has_sram_ecc(tech) = 1 -> target tech has SECDED capabilities for SRAM
constant has_sram_ecc : tech_ability_type :=
(rtg4 => 1, virtex5 => 1, virtex6 => 1,
artix7 => 1, kintex7 => 1, virtex7 => 1,
others => 0);
constant padoen_polarity : tech_ability_type :=
(axcel => 1, proasic => 1, umc => 1, rhumc => 1, saed32 => 1, rhs65 => 0, dare => 1, apa3 => 1,
ihp25 => 1, ut25 => 1, peregrine => 1, easic90 => 1, axdsp => 1,
actfus => 1, apa3e => 1, apa3l => 1, ut130 => 1, easic45 => 1,
ut90 => 1, igloo2 => 1, rtg4 => 1, others => 0);
constant has_pads : tech_ability_type :=
(inferred => 0, virtex => 1, virtex2 => 1, memvirage => 0,
axcel => 1, proasic => 1, atc18s => 1, altera => 0,
umc => 1, rhumc => 1, saed32 => 1, dare => 1, rhs65 => 1, apa3 => 1, spartan3 => 1,
ihp25 => 1, rhlib18t => 1, virtex4 => 1, lattice => 0,
ut25 => 1, spartan3e => 1, peregrine => 1, virtex5 => 1, axdsp => 1,
easic90 => 1, atc18rha => 1, spartan6 => 1, virtex6 => 1,
actfus => 1, apa3e => 1, apa3l => 1, ut130 => 1, easic45 => 1,
ut90 => 1, virtex7 => 1, kintex7 => 1,
artix7 => 1, zynq7000 => 1, igloo2 => 1, rtg4 => 1, others => 0);
constant has_ds_pads : tech_ability_type :=
(inferred => 0, virtex => 1, virtex2 => 1, memvirage => 0,
axcel => 1, proasic => 0, atc18s => 0, altera => 0,
umc => 0, rhumc => 0, saed32 => 0, dare => 0, rhs65 => 0, apa3 => 1, spartan3 => 1,
ihp25 => 0, rhlib18t => 1, virtex4 => 1, lattice => 0,
ut25 => 1, spartan3e => 1, virtex5 => 1, axdsp => 1,
spartan6 => 1, virtex6 => 1, actfus => 1,
apa3e => 1, apa3l => 1, ut130 => 0, easic45 => 1, virtex7 => 1, kintex7 => 1,
artix7 => 1, zynq7000 => 1, igloo2 => 1, rtg4 => 1, others => 0);
constant has_ds_combo : tech_ability_type :=
( rhumc => 1, ut25 => 1, ut130 => 1, others => 0);
constant has_tm_pads : tech_ability_type := (rhs65 => 1, others => 0);
constant has_clkand : tech_ability_type :=
( virtex => 1, virtex2 => 1, spartan3 => 1, spartan3e => 1, virtex4 => 1,
virtex5 => 1, ut25 => 1, rhlib18t => 1,
spartan6 => 1, virtex6 => 1, ut130 => 1, easic45 => 1,
ut90 => 1, virtex7 => 1, kintex7 => 1, artix7 => 1, zynq7000 => 1, saed32 => 1, dare => 1, rhs65 => 1, others => 0);
constant has_clkmux : tech_ability_type :=
( virtex => 1, virtex2 => 1, spartan3 => 1, spartan3e => 1,
virtex4 => 1, virtex5 => 1, rhlib18t => 1,
spartan6 => 1, virtex6 => 1, ut130 => 1, easic45 => 1,
ut90 => 1, virtex7 => 1, kintex7 => 1, artix7 => 1, zynq7000 => 1, saed32 => 1, dare => 1, rhumc => 1, rhs65 => 1, others => 0);
constant has_clkinv : tech_ability_type :=
( saed32 => 1, dare => 1, rhs65 => 1, others => 0);
constant has_techbuf : tech_ability_type :=
( virtex => 1, virtex2 => 1, virtex4 => 1, virtex5 => 1,
spartan3 => 1, spartan3e => 1, axcel => 1, ut25 => 1,
apa3 => 1, easic90 => 1, axdsp => 1, actfus => 1,
apa3e => 1, apa3l => 1, ut130 => 1, easic45 => 1,
ut90 => 1, spartan6 => 1, virtex6 => 1, virtex7 => 1, kintex7 => 1,
artix7 => 1, zynq7000 => 1, igloo2 => 1, rtg4 => 1, others => 0);
constant has_tapsel : tech_ability_type :=
( virtex => 1, virtex2 => 1, virtex4 => 1, virtex5 => 1,
spartan3 => 1, spartan3e => 1,
spartan6 => 1, virtex6 => 1, virtex7 => 1, kintex7 => 1,
artix7 => 1, zynq7000 => 1, others => 0);
constant tap_tck_gated : tech_ability_type :=
( virtex => 1, virtex2 => 1, virtex4 => 1, virtex5 => 1, spartan3 => 1, spartan3e => 1,
spartan6 => 0, others => 0);
constant need_extra_sync_reset : tech_ability_type :=
(axcel => 1, atc18s => 1, ut25 => 1, rhumc => 1, saed32 => 1, dare => 1, rhs65 => 1, tsmc90 => 1,
rhlib18t => 1, atc18rha => 1, easic90 => 1, tm65gplus => 1,
axdsp => 1, cmos9sf => 1, apa3 => 1, apa3e => 1, apa3l => 1,
ut130 => 1, easic45 => 1, ut90 => 1, others => 0);
constant is_unisim : tech_ability_type :=
( virtex => 1, virtex2 => 1, virtex4 => 1, virtex5 => 1,
spartan3 => 1, spartan3e => 1,
spartan6 => 1, virtex6 => 1, virtex7 => 1, kintex7 => 1, artix7 => 1, zynq7000 => 1, others => 0);
constant has_tap : tech_ability_type :=
(inferred => 0, virtex => 1, virtex2 => 1, axcel => 0,
proasic => 0, altera => 1, apa3 => 1, spartan3 => 1,
virtex4 => 1, lattice => 0, spartan3e => 1, virtex5 => 1,
stratix1 => 1, stratix2 => 1, eclipse => 0,
stratix3 => 1, cyclone3 => 1, axdsp => 0,
spartan6 => 1, virtex6 => 1, actfus => 1,
stratix4 => 1, easic45 => 0, apa3e => 1, apa3l => 1, virtex7 => 1, kintex7 => 1,
artix7 => 1, zynq7000 => 1, igloo2 => 1, rtg4 => 1,
others => 0);
constant has_clkgen : tech_ability_type :=
(inferred => 0, virtex => 1, virtex2 => 1, axcel => 1,
proasic => 1, altera => 1, apa3 => 1, spartan3 => 1,
virtex4 => 1, lattice => 0, spartan3e => 1, virtex5 => 1,
stratix1 => 1, stratix2 => 1, eclipse => 0, rhumc => 1, saed32 => 1, dare => 1, rhs65 => 1,
stratix3 => 1, cyclone3 => 1, axdsp => 1,
spartan6 => 1, virtex6 => 1, actfus => 1, easic90 => 1,
stratix4 => 1, easic45 => 1, apa3e => 1, apa3l => 1,
rhlib18t => 1, ut130 => 1, ut90 => 1, virtex7 => 1, kintex7 => 1, artix7 => 1, zynq7000 => 1, others => 0);
constant has_ddr2phy: tech_ability_type :=
(inferred => 0, stratix2 => 1, stratix3 => 1, stratix4 => 1, spartan3 => 1,
easic90 => 1, spartan6 => 1, easic45 => 1,
virtex4 => 1, virtex5 => 1, virtex6 => 1, virtex7 => 1, kintex7 => 1,
artix7 => 1, zynq7000 => 1, others => 0);
constant ddr2phy_builtin_pads: tech_ability_type := (
-- Wrapped DDR2 IP cores with builtin pads
easic45 => 1,
-- Below techs have builtin pads for legacy reasons, can be converted if needed
easic90 => 1, spartan3 => 1, stratix4 => 1, stratix3 => 1, stratix2 => 1,
others => 0);
constant ddr2phy_has_fbclk: tech_ability_type :=
(inferred => 1, others => 0);
constant ddrphy_has_fbclk: tech_ability_type :=
(others => 0);
constant ddr2phy_has_reg: tech_ability_type :=
(easic45 => 1, stratix4 => 1, others => 0);
constant ddr2phy_dis_caslat: tech_ability_type :=
(stratix4 => 1, others => 0);
constant ddr2phy_dis_init: tech_ability_type :=
(stratix4 => 1, others => 0);
constant ddr2phy_has_custom: tech_ability_type :=
(easic45 => 1, others => 0);
constant ddr2phy_refclk_type: tech_ability_type :=
(virtex4 => 1, virtex5 => 1, virtex6 => 1, -- 1: 200 MHz reference
virtex7 => 1, kintex7 => 1, artix7 => 1, zynq7000 => 1,
easic45 => 2, -- 2: 270 degree shifted clock
others => 0); -- 0: None
constant ddr2phy_has_datavalid: tech_ability_type :=
( stratix4 => 1,
easic45 => 1,
others => 0);
constant ddrphy_has_datavalid: tech_ability_type :=
(ut90 => 1, others => 0);
constant ddrphy_builtin_pads: tech_ability_type := (
inferred => 0,
-- Most techs have builtin pads for legacy reasons, can be converted if needed
others => 1);
constant ddrphy_latency: tech_ability_type := (
-- extra read latency, only used when not datavalid signal is available
inferred => 1,
others => 0
);
-- If the PHY passes through the control signals directly to the pads
-- and therefore needs them to be set asynchronously at reset
constant ddr2phy_ptctrl: tech_ability_type := (
inferred => 1, others => 0
);
constant ddrphy_ptctrl: tech_ability_type := (
inferred => 1, others => 0
);
constant has_syncreg: tech_ability_type := (
inferred => 0, others => 0);
constant has_transceivers : tech_ability_type := (
stratix3 => 1, stratix4 => 1,
virtex5 => 1, virtex6 => 1,
igloo2 => 1, rtg4 => 1,
others => 0
);
-- pragma translate_off
subtype tech_description is string(1 to 10);
type tech_table_type is array (0 to NTECH) of tech_description;
-------------------------------------------------------------------------------
constant tech_table : tech_table_type := (
inferred => "inferred ", virtex => "virtex ",
virtex2 => "virtex2 ", memvirage => "virage ",
axcel => "axcel ", proasic => "proasic ",
atc18s => "atc18s ", altera => "altera ",
umc => "umc18 ", rhumc => "rhumc ",
apa3 => "proasic3 ", spartan3 => "spartan3 ",
ihp25 => "ihp25 ", rhlib18t => "rhlib18t ",
virtex4 => "virtex4 ", lattice => "lattice ",
ut25 => "ut025crh ", spartan3e => "spartan3e ",
peregrine => "peregrine ", memartisan => "artisan ",
virtex5 => "virtex5 ", custom1 => "custom1 ",
ihp25rh => "ihp25rh ", stratix1 => "stratix ",
stratix2 => "stratixii ", eclipse => "eclipse ",
stratix3 => "stratixiii", cyclone3 => "cycloneiii",
memvirage90 => "virage90 ", tsmc90 => "tsmc90 ",
easic90 => "nextreme ", atc18rha => "atc18rha ",
smic013 => "smic13 ", tm65gplus => "tm65gplus ",
axdsp => "axdsp ", spartan6 => "spartan6 ",
virtex6 => "virtex6 ", actfus => "fusion ",
stratix4 => "stratix4 ", st65lp => "st65lp ",
st65gp => "st65gp ", easic45 => "nextreme2 ",
cmos9sf => "cmos9sf ", apa3e => "proasic3e ",
apa3l => "proasic3l ", ut130 => "ut130hbd ",
ut90 => "ut90nhbd ", gf65 => "gf65g ",
virtex7 => "virtex7 ", kintex7 => "kintex7 ",
artix7 => "artix7 ", zynq7000 => "zynq7000 ",
rhlib13t => "rhlib13t ", saed32 => "saed32 ",
dare => "dare ", igloo2 => "igloo2 ",
rhs65 => "rhs65 ", rtg4 => "rtg4 ");
-- pragma translate_on
-- input/output voltage
constant x12v : integer := 12;
constant x15v : integer := 15;
constant x18v : integer := 1;
constant x25v : integer := 2;
constant x33v : integer := 3;
constant x50v : integer := 5;
-- input/output levels
constant ttl : integer := 0;
constant cmos : integer := 1;
constant pci33 : integer := 2;
constant pci66 : integer := 3;
constant lvds : integer := 4;
constant sstl2_i : integer := 5;
constant sstl2_ii : integer := 6;
constant sstl3_i : integer := 7;
constant sstl3_ii : integer := 8;
constant sstl18_i : integer := 9;
constant sstl18_ii: integer := 10;
constant lvpecl : integer := 11;
constant sstl : integer := 12;
-- pad types
constant normal : integer := 0;
constant pullup : integer := 1;
constant pulldown : integer := 2;
constant opendrain: integer := 3;
constant schmitt : integer := 4;
constant dci : integer := 5;
-- transceivers types
-- Xilinx transceiver type and channel number
constant GTP0 : integer := 0;
constant GTP1 : integer := 1;
constant GTP2 : integer := 2;
constant GTP3 : integer := 3;
constant GTX0 : integer := 16;
constant GTX1 : integer := 17;
constant GTX2 : integer := 18;
constant GTX3 : integer := 19;
constant GTH0 : integer := 32;
constant GTH1 : integer := 33;
constant GTH2 : integer := 34;
constant GTH3 : integer := 35;
-- Microsemi transceiver type
constant m075 : integer := 14; -- values represent the length of the paddr field of serdes APB interface
constant m010 : integer := 13;
---------------------------------------------------------------------------
-- MEMORY
---------------------------------------------------------------------------
-- testin vector is testen & scanen & (tech-dependent...)
constant TESTIN_WIDTH : integer := 4 + GRLIB_CONFIG_ARRAY(grlib_techmap_testin_extra);
constant testin_none : std_logic_vector(TESTIN_WIDTH-1 downto 0) := (others => '0');
-- Used for mbist support via customin/out on cores that support it
constant memtest_vlen: integer := 16;
subtype memtest_vector is std_logic_vector(memtest_vlen-1 downto 0);
type memtest_vector_array is array(natural range <>) of memtest_vector;
-- synchronous single-port ram
component syncram
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
testen : integer := 0; custombits : integer := 1);
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic;
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0) := testin_none
);
end component;
-- synchronous two-port ram (1 read, 1 write port)
component syncram_2p
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
sepclk : integer := 0; wrfst : integer := 0; testen : integer := 0;
words : integer := 0; custombits : integer := 1);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0) := testin_none
);
end component;
-- synchronous dual-port ram (2 read/write ports)
component syncram_dp
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
testen : integer := 0; custombits : integer := 1; sepclk: integer := 1;
wrfst : integer := 0);
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic;
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0) := testin_none
);
end component;
-- synchronous 3-port regfile (2 read, 1 write port)
component regfile_3p
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
wrfst : integer := 0; numregs : integer := 64; testen : integer := 0;
custombits : integer := 1);
port (
wclk : in std_ulogic;
waddr : in std_logic_vector((abits -1) downto 0);
wdata : in std_logic_vector((dbits -1) downto 0);
we : in std_ulogic;
rclk : in std_ulogic;
raddr1 : in std_logic_vector((abits -1) downto 0);
re1 : in std_ulogic;
rdata1 : out std_logic_vector((dbits -1) downto 0);
raddr2 : in std_logic_vector((abits -1) downto 0);
re2 : in std_ulogic;
rdata2 : out std_logic_vector((dbits -1) downto 0);
ce1 : out std_ulogic;
ce2 : out std_ulogic;
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0) := testin_none
);
end component;
-- 64-bit synchronous single-port ram with 32-bit write strobe
component syncram64
generic (tech : integer := 0; abits : integer := 6; testen : integer := 0;
paren : integer := 0; custombits : integer := 1);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (63+8*paren downto 0);
dataout : out std_logic_vector (63+8*paren downto 0);
enable : in std_logic_vector (1 downto 0);
write : in std_logic_vector (1 downto 0);
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0) := testin_none
);
end component;
-- 128-bit synchronous single-port ram with 32-bit write strobe
component syncram128
generic (tech : integer := 0; abits : integer := 6; testen : integer := 0;
paren : integer := 0; custombits : integer := 1);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (127+16*paren downto 0);
dataout : out std_logic_vector (127+16*paren downto 0);
enable : in std_logic_vector (3 downto 0);
write : in std_logic_vector (3 downto 0);
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0) := testin_none
);
end component;
component syncramft
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
ft : integer range 0 to 5 := 0; testen : integer := 0; custombits : integer := 1 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
write : in std_ulogic;
enable : in std_ulogic;
error : out std_logic_vector((((dbits+7)/8)-1)*(1-ft/4)+ft/4 downto 0);
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0) := testin_none;
errinj : in std_logic_vector(((dbits + 7)/8)*2-1 downto 0) := (others => '0')
);
end component;
component syncram_2pft
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
sepclk : integer := 0; wrfst : integer := 0; ft : integer := 0;
testen : integer := 0; words : integer := 0; custombits : integer := 1);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
error : out std_logic_vector((((dbits+7)/8)-1)*(1-ft/4)+ft/4 downto 0);
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0) := testin_none;
errinj : in std_logic_vector((((dbits + 7)/8)*2-1)*(1-ft/4)+(6*(ft/4)) downto 0) := (others => '0')
);
end component;
component syncram128bw
generic (tech : integer := 0; abits : integer := 6; testen : integer := 0; custombits : integer := 1);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (127 downto 0);
dataout : out std_logic_vector (127 downto 0);
enable : in std_logic_vector (15 downto 0);
write : in std_logic_vector (15 downto 0);
testin : in std_logic_vector (TESTIN_WIDTH-1 downto 0) := testin_none
);
end component;
component syncram156bw
generic (tech : integer := 0; abits : integer := 6; testen : integer := 0; custombits : integer := 1);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (155 downto 0);
dataout : out std_logic_vector (155 downto 0);
enable : in std_logic_vector (15 downto 0);
write : in std_logic_vector (15 downto 0);
testin : in std_logic_vector (TESTIN_WIDTH-1 downto 0) := testin_none
);
end component;
component syncram256bw is
generic (tech : integer := 0; abits : integer := 6; testen : integer := 0; custombits : integer := 1);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (255 downto 0);
dataout : out std_logic_vector (255 downto 0);
enable : in std_logic_vector (31 downto 0);
write : in std_logic_vector (31 downto 0);
testin : in std_logic_vector (TESTIN_WIDTH-1 downto 0) := testin_none
);
end component;
component syncrambw
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
testen : integer := 0; custombits : integer := 1);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits-1 downto 0);
datain : in std_logic_vector (dbits-1 downto 0);
dataout : out std_logic_vector (dbits-1 downto 0);
enable : in std_logic_vector (dbits/8-1 downto 0);
write : in std_logic_vector (dbits/8-1 downto 0);
testin : in std_logic_vector (TESTIN_WIDTH-1 downto 0) := testin_none
);
end component;
component syncram_2pbw
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
sepclk : integer := 0; wrfst : integer := 0; testen : integer := 0;
words : integer := 0; custombits : integer := 1);
port (
rclk : in std_ulogic;
renable : in std_logic_vector((dbits/8-1) downto 0);
raddress : in std_logic_vector((abits-1) downto 0);
dataout : out std_logic_vector((dbits-1) downto 0);
wclk : in std_ulogic;
write : in std_logic_vector((dbits/8-1) downto 0);
waddress : in std_logic_vector((abits-1) downto 0);
datain : in std_logic_vector((dbits-1) downto 0);
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0) := testin_none
);
end component;
component syncrambwft is
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
ft : integer range 0 to 3 := 0; testen : integer := 0; custombits : integer := 1);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits-1 downto 0);
datain : in std_logic_vector (dbits-1 downto 0);
dataout : out std_logic_vector (dbits-1 downto 0);
enable : in std_logic_vector (dbits/8-1 downto 0);
write : in std_logic_vector (dbits/8-1 downto 0);
error : out std_logic_vector (dbits/8-1 downto 0);
testin : in std_logic_vector (TESTIN_WIDTH-1 downto 0) := testin_none;
errinj : in std_logic_vector((dbits/8)*2-1 downto 0) := (others => '0')
);
end component;
component from is
generic (
timingcheckson: boolean := True;
instancepath: string := "*";
xon: boolean := False;
msgon: boolean := True;
data_x: integer := 1;
memoryfile: string := "";
progfile: string := "");
port (
clk: in std_ulogic;
addr: in std_logic_vector(6 downto 0);
data: out std_logic_vector(7 downto 0));
end component;
component syncfifo_2p is
generic (
tech : integer := 0;
abits : integer := 6;
dbits : integer := 8;
sepclk : integer := 1; -- 1 = asynchronous, 0 = synchronous
pfull : integer := 100; -- almost full threshold
pempty : integer := 10; -- almost empty threshold
fwft : integer := 0 -- 0 = standard fifo mode, 1 = first word-fall through mode
);
port (
rclk : in std_logic;
rrstn : in std_logic; -- synchronous reset (read domain)
wrstn : in std_logic; -- synchronous reest (write domain)
renable : in std_logic;
rfull : out std_logic;
rempty : out std_logic;
aempty : out std_logic;
rusedw : out std_logic_vector(abits-1 downto 0);
dataout : out std_logic_vector(dbits-1 downto 0);
wclk : in std_logic;
write : in std_logic;
wfull : out std_logic;
afull : out std_logic;
wempty : out std_logic;
wusedw : out std_logic_vector(abits-1 downto 0);
datain : in std_logic_vector(dbits-1 downto 0));
end component;
---------------------------------------------------------------------------
-- PADS
---------------------------------------------------------------------------
component inpad
generic (tech : integer := 0; level : integer := 0;
voltage : integer := x33v; filter : integer := 0;
strength : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic);
end component;
component inpadv
generic (tech : integer := 0; level : integer := 0;
voltage : integer := x33v; width : integer := 1;
filter : integer := 0; strength : integer := 0);
port (
pad : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0));
end component;
component iopad
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0; filter : integer := 0);
port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic;
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end component;
component iopadv
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0; filter : integer := 0);
port (
pad : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_ulogic;
o : out std_logic_vector(width-1 downto 0);
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end component;
component iopadvv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0; filter : integer := 0);
port (
pad : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0);
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000"
);
end component;
component iodpad
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (pad : inout std_ulogic; i : in std_ulogic; o : out std_ulogic);
end component;
component iodpadv
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
pad : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0));
end component;
component outpad
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12);
port (pad : out std_ulogic; i : in std_ulogic;
cfgi : in std_logic_vector(19 downto 0) := "00000000000000000000");
end component;
component outpadv
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1);
port (
pad : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end component;
component odpad
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (pad : out std_ulogic; i : in std_ulogic;
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end component;
component odpadv
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
pad : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end component;
component toutpad
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (pad : out std_ulogic; i, en : in std_ulogic;
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end component;
component toutpadv
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
pad : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_ulogic;
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end component;
component toutpadvv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
pad : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0);
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end component;
component toutpad_ds
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (padp, padn : out std_ulogic; i, en : in std_ulogic);
end component;
component toutpad_dsv
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
padp : out std_logic_vector(width-1 downto 0);
padn : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_ulogic);
end component;
component toutpad_dsvv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
padp : out std_logic_vector(width-1 downto 0);
padn : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0));
end component;
component skew_outpad
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; skew : integer := 0);
port (pad : out std_ulogic; i : in std_ulogic; rst : in std_ulogic;
o : out std_ulogic);
end component;
component clkpad
generic (tech : integer := 0; level : integer := 0;
voltage : integer := x33v; arch : integer := 0;
hf : integer := 0; filter : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic; rstn : std_ulogic := '1'; lock : out std_ulogic);
end component;
component inpad_ds
generic (tech : integer := 0; level : integer := lvds; voltage : integer := x33v; term : integer := 0);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end component;
component clkpad_ds
generic (tech : integer := 0; level : integer := lvds; voltage : integer := x33v; term : integer := 0);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end component;
component inpad_dsv
generic (tech : integer := 0; level : integer := lvds;
voltage : integer := x33v; width : integer := 1; term : integer := 0);
port (
padp : in std_logic_vector(width-1 downto 0);
padn : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0));
end component;
component iopad_ds
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0; term : integer := 0);
port (padp, padn : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end component;
component iopad_dsv
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
padp, padn : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_ulogic;
o : out std_logic_vector(width-1 downto 0));
end component;
component iopad_dsvv
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
padp, padn : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0));
end component;
component outpad_ds
generic (tech : integer := 0; level : integer := lvds;
voltage : integer := x33v; oepol : integer := 0; slew : integer := 0);
port (padp, padn : out std_ulogic; i, en : in std_ulogic);
end component;
component outpad_dsv
generic (tech : integer := 0; level : integer := lvds;
voltage : integer := x33v; width : integer := 1; slew : integer := 0);
port (
padp : out std_logic_vector(width-1 downto 0);
padn : out std_logic_vector(width-1 downto 0);
i, en: in std_logic_vector(width-1 downto 0));
end component;
component lvds_combo is
generic (tech : integer := 0; voltage : integer := 0; width : integer := 1;
oepol : integer := 0; term : integer := 0);
port (odpadp, odpadn, ospadp, ospadn : out std_logic_vector(0 to width-1);
odval, osval, en : in std_logic_vector(0 to width-1);
idpadp, idpadn, ispadp, ispadn : in std_logic_vector(0 to width-1);
idval, isval : out std_logic_vector(0 to width-1);
powerdown : in std_logic_vector(0 to width-1) := (others => '0');
powerdownrx : in std_logic_vector(0 to width-1) := (others => '0');
lvdsref : in std_logic := '1'; lvdsrefo : out std_logic
);
end component;
component iopad_tm
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0; filter : integer := 0);
port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic;
test: in std_ulogic; ti, ten: in std_ulogic;
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end component;
component iopad_tmvv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0; filter : integer := 0);
port (
pad : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0);
test: in std_ulogic;
ti : in std_logic_vector(width-1 downto 0);
ten : in std_logic_vector(width-1 downto 0);
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000"
);
end component;
component toutpad_tm
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (pad : out std_ulogic; i, en : in std_ulogic;
test: in std_ulogic; ti, ten: in std_ulogic;
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end component;
component toutpad_tmvv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
pad : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0);
test: in std_ulogic;
ti : in std_logic_vector(width-1 downto 0);
ten : in std_logic_vector(width-1 downto 0);
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end component;
-------------------------------------------------------------------------------
-- DDR PADS (bundles PAD and DDR register(s))
-------------------------------------------------------------------------------
component inpad_ddr
generic (tech : integer := 0; level : integer := 0; voltage : integer := x33v;
filter : integer := 0; strength : integer := 0 );
port (pad : in std_ulogic; o1, o2 : out std_ulogic; c1, c2 : in std_ulogic;
ce : in std_ulogic; r : in std_ulogic; s : in std_ulogic);
end component;
component inpad_ddrv
generic (tech : integer := 0; level : integer := 0; voltage : integer := 0;
filter : integer := 0; strength : integer := 0; width : integer := 1);
port (pad : in std_logic_vector(width-1 downto 0);
o1, o2 : out std_logic_vector(width-1 downto 0); c1, c2 : in std_ulogic;
ce : in std_ulogic; r: in std_ulogic; s : in std_ulogic);
end component;
component outpad_ddr
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12);
port (pad : out std_ulogic; i1, i2 : in std_ulogic; c1, c2 : in std_ulogic;
ce : in std_ulogic; r : in std_ulogic; s : in std_ulogic);
end component;
component outpad_ddrv
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 12;
width : integer := 1);
port (pad : out std_logic_vector(width-1 downto 0);
i1, i2 : in std_logic_vector(width-1 downto 0);
c1, c2 : in std_ulogic; ce : in std_ulogic;
r : in std_ulogic; s : in std_ulogic);
end component;
component iopad_ddr
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (pad : inout std_ulogic; i1, i2 : in std_ulogic; en : in std_ulogic;
o1, o2 : out std_ulogic; c1, c2 : in std_ulogic; ce : in std_ulogic;
r : in std_ulogic; s : in std_ulogic);
end component;
component iopad_ddrv
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (pad : inout std_logic_vector(width-1 downto 0);
i1, i2 : in std_logic_vector(width-1 downto 0); en : in std_ulogic;
o1, o2 : out std_logic_vector(width-1 downto 0); c1, c2 : in std_ulogic;
ce : in std_ulogic; r : in std_ulogic; s : in std_ulogic);
end component;
component iopad_ddrvv
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (pad : inout std_logic_vector(width-1 downto 0);
i1, i2 : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0);
o1, o2 : out std_logic_vector(width-1 downto 0); c1, c2 : in std_ulogic;
ce : in std_ulogic; r : in std_ulogic; s : in std_ulogic);
end component;
---------------------------------------------------------------------------
-- BUFFERS
---------------------------------------------------------------------------
component techbuf is
generic(
buftype : integer range 0 to 6 := 0;
tech : integer range 0 to NTECH := inferred);
port(
i : in std_ulogic;
o : out std_ulogic
);
end component;
---------------------------------------------------------------------------
-- CLOCK GENERATION
---------------------------------------------------------------------------
type clkgen_in_type is record
pllref : std_logic; -- optional reference for PLL
pllrst : std_logic; -- optional reset for PLL
pllctrl : std_logic_vector(1 downto 0); -- optional control for PLL
clksel : std_logic_vector(1 downto 0); -- optional clock select
end record;
type clkgen_out_type is record
clklock : std_logic;
pcilock : std_logic;
end record;
component clkgen
generic (
tech : integer := DEFFABTECH;
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 1;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0;
clksel : integer := 0; -- enable clock select
clk_odiv : integer := 1; -- Proasic3/Fusion output divider clkA
clkb_odiv: integer := 0; -- Proasic3/Fusion output divider clkB
clkc_odiv: integer := 0); -- Proasic3/Fusion output divider clkC
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- 2x clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk4x : out std_logic; -- 4x clock
clk1xu : out std_logic; -- unscaled 1X clock
clk2xu : out std_logic; -- unscaled 2X clock
clkb : out std_logic; -- Proasic3/Fusion clkB
clkc : out std_logic; -- Proasic3/Fusion clkC
clk8x : out std_logic); -- 8x clock
end component;
component clkand
generic( tech : integer := 0;
ren : integer range 0 to 1 := 0); -- registered enable
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic;
tsten : in std_ulogic := '0'
);
end component;
component clkmux
generic( tech : integer := 0;
rsel : integer range 0 to 1 := 0); -- registered sel
port(
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic;
rst : in std_ulogic := '1'
);
end component;
component clkinv
generic( tech : integer := 0);
port(
i : in std_ulogic;
o : out std_ulogic
);
end component;
component clkrand is
generic( tech : integer := 0);
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic;
tsten : in std_ulogic := '0'
);
end component;
---------------------------------------------------------------------------
-- TAP controller and boundary scan
---------------------------------------------------------------------------
component tap
generic (
tech : integer := 0;
irlen : integer range 2 to 8 := 4;
idcode : integer range 0 to 255 := 9;
manf : integer range 0 to 2047 := 804;
part : integer range 0 to 65535 := 0;
ver : integer range 0 to 15 := 0;
trsten : integer range 0 to 1 := 1;
scantest : integer := 0;
oepol : integer := 1;
tcknen : integer := 0);
port (
trst : in std_ulogic;
tck : in std_ulogic;
tms : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_inst : out std_logic_vector(7 downto 0);
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic;
tapi_en1 : in std_ulogic;
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_ninst : out std_logic_vector(7 downto 0);
tapo_iupd : out std_ulogic;
tapo_tckn : out std_ulogic;
testen : in std_ulogic := '0';
testrst : in std_ulogic := '1';
testoen : in std_ulogic := '0';
tdoen : out std_ulogic;
tckn : in std_ulogic := '0'
);
end component;
component scanregi
generic (
tech : integer := 0;
intesten: integer := 1
);
port (
pad : in std_ulogic;
core : out std_ulogic;
tck : in std_ulogic;
tckn : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
bsshft : in std_ulogic;
bscapt : in std_ulogic; -- capture signal to scan reg on next tck edge
bsupd : in std_ulogic; -- update data reg from scan reg on next tck edge
bsdrive : in std_ulogic; -- drive data reg to core
bshighz : in std_ulogic
);
end component;
component scanrego
generic (
tech : integer := 0
);
port (
pad : out std_ulogic;
core : in std_ulogic;
samp : in std_ulogic; -- normally same as core unless outpad has feedback
tck : in std_ulogic;
tckn : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
bsshft : in std_ulogic;
bscapt : in std_ulogic; -- capture signal to scan reg on next tck edge
bsupd : in std_ulogic; -- update data reg from scan reg on next tck edge
bsdrive : in std_ulogic -- drive data reg to pad
);
end component;
component scanregto -- 2 scan registers: tdo<---output<--outputen<--tdi
generic (
tech : integer := 0;
hzsup: integer range 0 to 1 := 1;
oepol: integer range 0 to 1 := 1;
scantest: integer range 0 to 1 := 0
);
port (
pado : out std_ulogic;
padoen : out std_ulogic;
samp : in std_ulogic; -- normally same as core unless outpad has feedback
coreo : in std_ulogic;
coreoen : in std_ulogic;
tck : in std_ulogic;
tckn : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
bsshft : in std_ulogic;
bscapto : in std_ulogic; -- capture signal to scan reg on next tck edge
bscaptoe : in std_ulogic; -- capture signal to scan reg on next tck edge
bsupdo : in std_ulogic; -- update data reg from scan reg on next tck edge
bsdrive : in std_ulogic; -- drive data reg to pad
bshighz : in std_ulogic; -- tri-state output
testen : in std_ulogic := '0';
testoen : in std_ulogic := '0'
);
end component;
component scanregio -- 3 scan registers: tdo<--input<--output<--outputen<--tdi
generic (
tech : integer := 0;
hzsup: integer range 0 to 1 := 1;
oepol: integer range 0 to 1 := 1;
intesten: integer range 0 to 1 := 1;
scantest: integer range 0 to 1 := 0
);
port (
pado : out std_ulogic;
padoen : out std_ulogic;
padi : in std_ulogic;
coreo : in std_ulogic;
coreoen : in std_ulogic;
corei : out std_ulogic;
tck : in std_ulogic;
tckn : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
bsshft : in std_ulogic;
bscapti : in std_ulogic; -- capture signals to scan regs on next tck edge
bscapto : in std_ulogic; -- capture signals to scan regs on next tck edge
bscaptoe: in std_ulogic; -- capture signals to scan regs on next tck edge
bsupdi : in std_ulogic; -- update indata reg from scan reg on next tck edge
bsupdo : in std_ulogic; -- update outdata reg from scan reg on next tck edge
bsdrive : in std_ulogic; -- drive outdata regs to pad,
-- drive datareg(coreoen=0) or coreo(coreoen=1) to corei
bshighz : in std_ulogic; -- tri-state output
testen : in std_ulogic := '0';
testoen : in std_ulogic := '0'
);
end component;
---------------------------------------------------------------------------
-- DDR registers and PHY
---------------------------------------------------------------------------
component ddr_ireg is
generic ( tech : integer; arch : integer := 0; scantest: integer := 0);
port ( Q1 : out std_ulogic;
Q2 : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic;
testen : in std_ulogic := '0';
testrst : in std_ulogic := '1');
end component;
component ddr_oreg is generic (tech : integer; arch : integer := 0; scantest: integer := 0);
port
( Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic;
testen : in std_ulogic := '0';
testrst: in std_ulogic := '1');
end component;
component ddrphy
generic (tech : integer := virtex2; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16;
clk_mul : integer := 2 ; clk_div : integer := 2;
rskew : integer :=0; mobile : integer := 0;
abits: integer := 14; nclk: integer := 3; ncs: integer := 2;
scantest : integer := 0; phyiconf : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
clkread : out std_ulogic; -- read clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0);
ck : in std_logic_vector(2 downto 0);
moben : in std_logic;
dqvalid : out std_ulogic;
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end component;
component ddrphy_wo_pads
generic (tech : integer := virtex2; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16;
clk_mul : integer := 2; clk_div : integer := 2;
rskew : integer := 0; mobile: integer := 0;
abits : integer := 14; nclk: integer := 3; ncs: integer := 2;
scantest : integer := 0; phyiconf : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock returned
clkread : out std_ulogic;
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (abits-1 downto 0);
ba : in std_logic_vector (1 downto 0);
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr output data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
ck : in std_logic_vector(2 downto 0);
moben : in std_logic;
dqvalid : out std_ulogic;
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end component;
component ddr2phy
generic (
tech : integer := virtex5; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16;
clk_mul : integer := 2; clk_div : integer := 2;
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
ddelayb6 : integer := 0; ddelayb7 : integer := 0;
ddelayb8 : integer := 0;
ddelayb9 : integer := 0; ddelayb10: integer := 0; ddelayb11: integer := 0;
numidelctrl : integer := 4; norefclk : integer := 0; rskew : integer := 0;
eightbanks : integer range 0 to 1 := 0; dqsse : integer range 0 to 1 := 0;
abits : integer := 14; nclk: integer := 3; ncs: integer := 2;
ctrl2en: integer := 0; resync: integer := 0; custombits: integer := 8; extraio: integer := 0;
scantest : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref : in std_logic; -- input reference clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
clkresync : in std_ulogic; -- resync clock (if resync/=0)
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (extraio+dbits/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqsn
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
addr : in std_logic_vector (abits-1 downto 0);
ba : in std_logic_vector ( 2 downto 0);
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr output data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
noen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
cal_en : in std_logic_vector(dbits/8-1 downto 0);
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
cal_pll : in std_logic_vector(1 downto 0);
cal_rst : in std_logic;
odt : in std_logic_vector(ncs-1 downto 0);
oct : in std_logic;
read_pend : in std_logic_vector(7 downto 0);
regwdata : in std_logic_vector(63 downto 0);
regwrite : in std_logic_vector(1 downto 0);
regrdata : out std_logic_vector(63 downto 0);
dqin_valid : out std_ulogic;
customclk : in std_ulogic;
customdin : in std_logic_vector(custombits-1 downto 0);
customdout : out std_logic_vector(custombits-1 downto 0);
-- Copy of control signals for 2nd DIMM
ddr_web2 : out std_ulogic; -- ddr write enable
ddr_rasb2 : out std_ulogic; -- ddr ras
ddr_casb2 : out std_ulogic; -- ddr cas
ddr_ad2 : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba2 : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic;
oct_rdn : in std_logic := '0';
oct_rup : in std_logic := '0');
end component;
component ddr2phy_wo_pads
generic (tech : integer := virtex5; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16;
clk_mul : integer := 2; clk_div : integer := 2;
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
ddelayb6 : integer := 0; ddelayb7 : integer := 0;
ddelayb8: integer := 0;
ddelayb9: integer := 0; ddelayb10: integer := 0; ddelayb11: integer := 0;
numidelctrl : integer := 4; norefclk : integer := 0; rskew : integer := 0;
eightbanks : integer range 0 to 1 := 0; dqsse : integer range 0 to 1 := 0;
abits : integer := 14; nclk: integer := 3; ncs: integer := 2;
resync : integer := 0; custombits: integer := 8; scantest: integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock returned
clkresync : in std_ulogic;
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
addr : in std_logic_vector (abits-1 downto 0);
ba : in std_logic_vector ( 2 downto 0);
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr output data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
noen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
cal_en : in std_logic_vector(dbits/8-1 downto 0);
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
cal_pll : in std_logic_vector(1 downto 0);
cal_rst : in std_logic;
odt : in std_logic_vector(ncs-1 downto 0);
oct : in std_logic;
read_pend : in std_logic_vector(7 downto 0);
regwdata : in std_logic_vector(63 downto 0);
regwrite : in std_logic_vector(1 downto 0);
regrdata : out std_logic_vector(63 downto 0);
dqin_valid : out std_ulogic;
customclk : in std_ulogic;
customdin : in std_logic_vector(custombits-1 downto 0);
customdout : out std_logic_vector(custombits-1 downto 0);
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end component;
component lpddr2phy_wo_pads
generic (
tech : integer := virtex5;
dbits : integer := 16;
nclk: integer := 3;
ncs: integer := 2;
clkratio: integer := 1;
scantest: integer := 0);
port (
rst : in std_ulogic;
clkin : in std_ulogic;
clkin2 : in std_ulogic;
clkout : out std_ulogic;
clkoutret : in std_ulogic; -- ckkout returned
clkout2 : out std_ulogic;
lock : out std_ulogic;
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_ca : out std_logic_vector(9 downto 0);
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
ca : in std_logic_vector (10*2*clkratio-1 downto 0);
cke : in std_logic_vector (ncs*clkratio-1 downto 0);
csn : in std_logic_vector (ncs*clkratio-1 downto 0);
dqin : out std_logic_vector (dbits*2*clkratio-1 downto 0); -- ddr output data
dqout : in std_logic_vector (dbits*2*clkratio-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4*clkratio-1 downto 0); -- data mask
ckstop : in std_ulogic;
boot : in std_ulogic;
wrpend : in std_logic_vector(7 downto 0);
rdpend : in std_logic_vector(7 downto 0);
wrreq : out std_logic_vector(clkratio-1 downto 0);
rdvalid : out std_logic_vector(clkratio-1 downto 0);
refcal : in std_ulogic;
refcalwu : in std_ulogic;
refcaldone : out std_ulogic;
phycmd : in std_logic_vector(7 downto 0);
phycmden : in std_ulogic;
phycmdin : in std_logic_vector(31 downto 0);
phycmdout : out std_logic_vector(31 downto 0);
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end component;
component ddr2pads is
generic (tech: integer := virtex5;
dbits: integer := 16;
eightbanks: integer := 0;
dqsse: integer range 0 to 1 := 0;
abits: integer := 14;
nclk: integer := 3;
ncs: integer := 2;
ctrl2en: integer := 0);
port (
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqsn
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
-- Copy of control signals for 2nd DIMM (if ctrl2en /= 0)
ddr_web2 : out std_ulogic; -- ddr write enable
ddr_rasb2 : out std_ulogic; -- ddr ras
ddr_casb2 : out std_ulogic; -- ddr cas
ddr_ad2 : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba2 : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
lddr_clk : in std_logic_vector(nclk-1 downto 0);
lddr_clkb : in std_logic_vector(nclk-1 downto 0);
lddr_clk_fb_out : in std_logic;
lddr_clk_fb : out std_logic;
lddr_cke : in std_logic_vector(ncs-1 downto 0);
lddr_csb : in std_logic_vector(ncs-1 downto 0);
lddr_web : in std_ulogic; -- ddr write enable
lddr_rasb : in std_ulogic; -- ddr ras
lddr_casb : in std_ulogic; -- ddr cas
lddr_dm : in std_logic_vector (dbits/8-1 downto 0); -- ddr dm
lddr_dqs_in : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
lddr_dqs_out : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
lddr_dqs_oen : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
lddr_ad : in std_logic_vector (abits-1 downto 0); -- ddr address
lddr_ba : in std_logic_vector (1+eightbanks downto 0); -- ddr bank address
lddr_dq_in : out std_logic_vector (dbits-1 downto 0); -- ddr data
lddr_dq_out : in std_logic_vector (dbits-1 downto 0); -- ddr data
lddr_dq_oen : in std_logic_vector (dbits-1 downto 0); -- ddr data
lddr_odt : in std_logic_vector(ncs-1 downto 0)
);
end component;
component ddrpads is
generic (tech: integer := virtex5;
dbits: integer := 16;
abits: integer := 14;
nclk: integer := 3;
ncs: integer := 2;
ctrl2en: integer := 0);
port (
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
-- Copy of control signals for 2nd DIMM (if ctrl2en /= 0)
ddr_web2 : out std_ulogic; -- ddr write enable
ddr_rasb2 : out std_ulogic; -- ddr ras
ddr_casb2 : out std_ulogic; -- ddr cas
ddr_ad2 : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba2 : out std_logic_vector (1 downto 0); -- ddr bank address
lddr_clk : in std_logic_vector(nclk-1 downto 0);
lddr_clkb : in std_logic_vector(nclk-1 downto 0);
lddr_clk_fb_out : in std_logic;
lddr_clk_fb : out std_logic;
lddr_cke : in std_logic_vector(ncs-1 downto 0);
lddr_csb : in std_logic_vector(ncs-1 downto 0);
lddr_web : in std_ulogic; -- ddr write enable
lddr_rasb : in std_ulogic; -- ddr ras
lddr_casb : in std_ulogic; -- ddr cas
lddr_dm : in std_logic_vector (dbits/8-1 downto 0); -- ddr dm
lddr_dqs_in : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
lddr_dqs_out : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
lddr_dqs_oen : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
lddr_ad : in std_logic_vector (abits-1 downto 0); -- ddr address
lddr_ba : in std_logic_vector (1 downto 0); -- ddr bank address
lddr_dq_in : out std_logic_vector (dbits-1 downto 0); -- ddr data
lddr_dq_out : in std_logic_vector (dbits-1 downto 0); -- ddr data
lddr_dq_oen : in std_logic_vector (dbits-1 downto 0) -- ddr data
);
end component;
component ddrphy_datapath is
generic (
regtech: integer := 0;
dbits: integer;
abits: integer;
bankbits: integer range 2 to 3 := 2;
ncs: integer;
nclk: integer;
resync: integer range 0 to 2 := 0
);
port (
clk0: in std_ulogic;
clk90: in std_ulogic;
clk180: in std_ulogic;
clk270: in std_ulogic;
clkresync: in std_ulogic;
ddr_clk: out std_logic_vector(nclk-1 downto 0);
ddr_clkb: out std_logic_vector(nclk-1 downto 0);
ddr_dq_in: in std_logic_vector(dbits-1 downto 0);
ddr_dq_out: out std_logic_vector(dbits-1 downto 0);
ddr_dq_oen: out std_logic_vector(dbits-1 downto 0);
ddr_dqs_in90: in std_logic_vector(dbits/8-1 downto 0);
ddr_dqs_in90n: in std_logic_vector(dbits/8-1 downto 0);
ddr_dqs_out: out std_logic_vector(dbits/8-1 downto 0);
ddr_dqs_oen: out std_logic_vector(dbits/8-1 downto 0);
ddr_cke: out std_logic_vector(ncs-1 downto 0);
ddr_csb: out std_logic_vector(ncs-1 downto 0);
ddr_web: out std_ulogic;
ddr_rasb: out std_ulogic;
ddr_casb: out std_ulogic;
ddr_ad: out std_logic_vector(abits-1 downto 0);
ddr_ba: out std_logic_vector(bankbits-1 downto 0);
ddr_dm: out std_logic_vector(dbits/8-1 downto 0);
ddr_odt: out std_logic_vector(ncs-1 downto 0);
dqin: out std_logic_vector(dbits*2-1 downto 0);
dqout: in std_logic_vector(dbits*2-1 downto 0);
addr : in std_logic_vector (abits-1 downto 0);
ba : in std_logic_vector (bankbits-1 downto 0);
dm : in std_logic_vector (dbits/4-1 downto 0);
oen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
odt : in std_logic_vector(ncs-1 downto 0);
dqs_en : in std_ulogic;
dqs_oen : in std_ulogic;
ddrclk_en : in std_logic_vector(nclk-1 downto 0)
);
end component;
---------------------------------------------------------------------------
-- 61x61 Multiplier
---------------------------------------------------------------------------
component mul_61x61
generic (multech : integer := 0;
fabtech : integer := 0);
port(A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end component;
---------------------------------------------------------------------------
-- Ring oscillator
---------------------------------------------------------------------------
component ringosc
generic (tech : integer := 0);
port (
roen : in Std_ULogic;
roout : out Std_ULogic);
end component;
---------------------------------------------------------------------------
-- System monitor
---------------------------------------------------------------------------
component system_monitor
generic (
-- GRLIB generics
tech : integer := DEFFABTECH;
-- Virtex 5 SYSMON generics
INIT_40 : bit_vector := X"0000";
INIT_41 : bit_vector := X"0000";
INIT_42 : bit_vector := X"0800";
INIT_43 : bit_vector := X"0000";
INIT_44 : bit_vector := X"0000";
INIT_45 : bit_vector := X"0000";
INIT_46 : bit_vector := X"0000";
INIT_47 : bit_vector := X"0000";
INIT_48 : bit_vector := X"0000";
INIT_49 : bit_vector := X"0000";
INIT_4A : bit_vector := X"0000";
INIT_4B : bit_vector := X"0000";
INIT_4C : bit_vector := X"0000";
INIT_4D : bit_vector := X"0000";
INIT_4E : bit_vector := X"0000";
INIT_4F : bit_vector := X"0000";
INIT_50 : bit_vector := X"0000";
INIT_51 : bit_vector := X"0000";
INIT_52 : bit_vector := X"0000";
INIT_53 : bit_vector := X"0000";
INIT_54 : bit_vector := X"0000";
INIT_55 : bit_vector := X"0000";
INIT_56 : bit_vector := X"0000";
INIT_57 : bit_vector := X"0000";
SIM_MONITOR_FILE : string := "design.txt");
port (
alm : out std_logic_vector(2 downto 0);
busy : out std_ulogic;
channel : out std_logic_vector(4 downto 0);
do : out std_logic_vector(15 downto 0);
drdy : out std_ulogic;
eoc : out std_ulogic;
eos : out std_ulogic;
jtagbusy : out std_ulogic;
jtaglocked : out std_ulogic;
jtagmodified : out std_ulogic;
ot : out std_ulogic;
convst : in std_ulogic;
convstclk : in std_ulogic;
daddr : in std_logic_vector(6 downto 0);
dclk : in std_ulogic;
den : in std_ulogic;
di : in std_logic_vector(15 downto 0);
dwe : in std_ulogic;
reset : in std_ulogic;
vauxn : in std_logic_vector(15 downto 0);
vauxp : in std_logic_vector(15 downto 0);
vn : in std_ulogic;
vp : in std_ulogic);
end component;
component nandtree
generic(
tech : integer := inferred;
width : integer := 2;
imp : integer := 0 );
port( i : in std_logic_vector(width-1 downto 0);
o : out std_ulogic;
en : in std_ulogic
);
end component;
component grmux2 is generic( tech : integer := inferred; imp : integer := 0);
port( ip0, ip1, sel : in std_logic; op : out std_ulogic); end component;
component grmux2v is generic( tech : integer := inferred; bits : integer := 2; imp : integer := 0);
port( ip0, ip1 : in std_logic_vector(bits-1 downto 0);
sel : in std_logic; op : out std_logic_vector(bits-1 downto 0));
end component;
component grdff is generic( tech : integer := inferred; imp : integer := 0);
port( clk, d : in std_ulogic; q : out std_ulogic); end component;
component gror2 is generic( tech : integer := inferred; imp : integer := 0);
port( i0, i1 : in std_ulogic; q : out std_ulogic); end component;
component grand12 is generic( tech : integer := inferred; imp : integer := 0);
port( i0, i1 : in std_ulogic; q : out std_ulogic); end component;
component grnand2 is generic (tech: integer := inferred; imp: integer := 0);
port( i0, i1 : in std_ulogic; q : out std_ulogic); end component;
component techmult
generic (
tech : integer := 0;
arch : integer := 0;
a_width : positive := 2; -- multiplier word width
b_width : positive := 2; -- multiplicand word width
num_stages : positive := 2; -- number of pipeline stages
stall_mode : natural range 0 to 1 := 1 -- '0': non-stallable; '1': stallable
);
port(a : in std_logic_vector(a_width-1 downto 0);
b : in std_logic_vector(b_width-1 downto 0);
clk : in std_logic;
en : in std_logic;
sign : in std_logic;
product : out std_logic_vector(a_width+b_width-1 downto 0));
end component;
component syncreg
generic (
tech : integer := 0;
stages : integer range 1 to 5 := 2
);
port (
clk : in std_ulogic;
d : in std_ulogic;
q : out std_ulogic
);
end component;
-------------------------------------------------------------------------------
-- SDRAM PHY
-------------------------------------------------------------------------------
component sdram_phy
generic (
tech : integer := spartan3;
oepol : integer := 0;
level : integer := 0;
voltage : integer := x33v;
strength : integer := 12;
aw : integer := 15; -- # address bits
dw : integer := 32; -- # data bits
ncs : integer := 2;
reg : integer := 0); -- 1: include registers on all signals
port (
-- SDRAM interface
addr : out std_logic_vector(aw-1 downto 0);
dq : inout std_logic_vector(dw-1 downto 0);
cke : out std_logic_vector(ncs-1 downto 0);
sn : out std_logic_vector(ncs-1 downto 0);
wen : out std_ulogic;
rasn : out std_ulogic;
casn : out std_ulogic;
dqm : out std_logic_vector(dw/8-1 downto 0);
-- Interface toward memory controller
laddr : in std_logic_vector(aw-1 downto 0);
ldq_din : out std_logic_vector(dw-1 downto 0);
ldq_dout : in std_logic_vector(dw-1 downto 0);
ldq_oen : in std_logic_vector(dw-1 downto 0);
lcke : in std_logic_vector(ncs-1 downto 0);
lsn : in std_logic_vector(ncs-1 downto 0);
lwen : in std_ulogic;
lrasn : in std_ulogic;
lcasn : in std_ulogic;
ldqm : in std_logic_vector(dw/8-1 downto 0);
-- Only used when reg generic is non-zero
rstn : in std_ulogic; -- Registered pads reset
clk : in std_ulogic; -- SDRAM clock for registered pads
-- Optional pad configuration inputs
cfgi_cmd : in std_logic_vector(19 downto 0) := "00000000000000000000"; -- CMD pads
cfgi_dq : in std_logic_vector(19 downto 0) := "00000000000000000000" -- DQ pads
);
end component;
-------------------------------------------------------------------------------
-- GIGABIT ETHERNET SERDES
-------------------------------------------------------------------------------
-- Types for IGLOO2 serdes
type apb_in_serdes is record
paddr : std_logic_vector(14 downto 2);
pclk : std_logic;
penable : std_logic;
prstn : std_logic;
psel : std_logic;
pwdata : std_logic_vector(31 downto 0);
pwrite : std_logic;
end record;
constant apb_in_serdes_none : apb_in_serdes := ((others=>'0'), '0', '0', '0', '0', (others =>'0'), '0');
type apb_out_serdes is record
prdata : std_logic_vector(31 downto 0);
pready : std_logic;
pslverr : std_logic;
end record;
constant apb_out_serdes_none : apb_out_serdes := ((others=>'0'), '0', '0');
type pad_in_serdes is record
refclkp : std_logic;
refclkn : std_logic;
rx0p : std_logic;
rx0n : std_logic;
rx1p : std_logic;
rx1n : std_logic;
rx2p : std_logic;
rx2n : std_logic;
rx3p : std_logic;
rx3n : std_logic;
end record;
constant pad_in_serdes_none : pad_in_serdes := ('0', '0', '0', '0', '0', '0', '0', '0', '0', '0');
type pad_out_serdes is record
tx0p : std_logic;
tx0n : std_logic;
tx1p : std_logic;
tx1n : std_logic;
tx2p : std_logic;
tx2n : std_logic;
tx3p : std_logic;
tx3n : std_logic;
end record;
constant pad_out_serdes_none : pad_out_serdes := ('0', '0', '0', '0', '0', '0', '0', '0');
type sigin_serdes_type is record
rstn : std_logic;
tx_data : std_logic_vector(9 downto 0);
end record;
type sigout_serdes_type is record
ready : std_logic;
rx_clk : std_logic;
rx_data : std_logic_vector(9 downto 0);
rx_idle : std_logic;
rx_rstn : std_logic;
rx_val : std_logic;
tx_clk : std_logic;
tx_clk_lock : std_logic;
tx_rstn : std_logic;
refclk : std_logic;
end record;
component serdes is
generic (
fabtech : integer;
transtech : integer
);
port (
clk_125 : in std_logic;
rst_125 : in std_logic;
rx_in_p : in std_logic; -- SER IN
rx_in_n : in std_logic; -- SER IN
rx_out : out std_logic_vector(9 downto 0); -- PAR OUT
rx_clk : out std_logic;
rx_rstn : out std_logic;
rx_pll_clk : out std_logic;
rx_pll_rstn : out std_logic;
tx_pll_clk : out std_logic;
tx_pll_rstn : out std_logic;
tx_in : in std_logic_vector(9 downto 0) ; -- PAR IN
tx_out_p : out std_logic; -- SER OUT
tx_out_n : out std_logic; -- SER OUT
bitslip : in std_logic;
-- added for igloo2_serdes
apbin : in apb_in_serdes;
apbout : out apb_out_serdes;
m2gl_padin : in pad_in_serdes;
m2gl_padout : out pad_out_serdes;
serdes_clk125 : out std_logic;
serdes_ready: out std_logic);
end component;
end;
| gpl-3.0 | e4f30f13ea7e34a02b3073d5d63e6b93 | 0.565505 | 3.411238 | false | false | false | false |
ARC-Lab-UF/UAA | src/add_flt_stratix5_area.vhd | 1 | 286,316 | -- megafunction wizard: %ALTFP_ADD_SUB%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altfp_add_sub
-- ============================================================
-- File Name: add_flt_stratix5_area.vhd
-- Megafunction Name(s):
-- altfp_add_sub
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
--altfp_add_sub CBX_AUTO_BLACKBOX="ALL" DENORMAL_SUPPORT="NO" DEVICE_FAMILY="Stratix V" DIRECTION="ADD" OPTIMIZE="AREA" PIPELINE=14 REDUCED_FUNCTIONALITY="NO" WIDTH_EXP=8 WIDTH_MAN=23 clk_en clock dataa datab result
--VERSION_BEGIN 13.1 cbx_altbarrel_shift 2013:10:23:18:05:48:SJ cbx_altfp_add_sub 2013:10:23:18:05:48:SJ cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_cycloneii 2013:10:23:18:05:48:SJ cbx_lpm_add_sub 2013:10:23:18:05:48:SJ cbx_lpm_compare 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ cbx_stratix 2013:10:23:18:05:48:SJ cbx_stratixii 2013:10:23:18:05:48:SJ VERSION_END
--altbarrel_shift CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix V" PIPELINE=2 SHIFTDIR="LEFT" WIDTH=26 WIDTHDIST=5 aclr clk_en clock data distance result
--VERSION_BEGIN 13.1 cbx_altbarrel_shift 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--synthesis_resources = reg 56
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_area_altbarrel_shift_oud IS
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (25 DOWNTO 0);
distance : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (25 DOWNTO 0)
);
END add_flt_stratix5_area_altbarrel_shift_oud;
ARCHITECTURE RTL OF add_flt_stratix5_area_altbarrel_shift_oud IS
SIGNAL dir_pipe : STD_LOGIC_VECTOR(1 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL sbit_piper1d : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL sbit_piper2d : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL sel_pipec3r1d : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sel_pipec4r1d : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range635w648w649w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range635w644w645w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range656w669w670w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range656w665w666w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range678w691w692w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range678w687w688w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range701w713w714w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range701w709w710w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range720w732w733w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range720w728w729w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range635w640w641w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range656w661w662w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range678w683w684w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range701w705w706w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range720w724w725w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range635w648w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range635w644w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range656w669w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range656w665w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range678w691w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range678w687w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range701w713w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range701w709w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range720w732w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range720w728w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_dir_w_range632w647w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_dir_w_range654w668w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_dir_w_range675w690w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_dir_w_range699w712w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_dir_w_range718w731w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range635w640w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range656w661w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range678w683w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range701w705w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range720w724w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range635w648w649w650w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range656w669w670w671w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range678w691w692w693w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range701w713w714w715w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range720w732w733w734w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w651w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w672w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w694w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w716w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w735w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL dir_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL direction_w : STD_LOGIC;
SIGNAL pad_w : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sbit_w : STD_LOGIC_VECTOR (155 DOWNTO 0);
SIGNAL sel_w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL smux_w : STD_LOGIC_VECTOR (129 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w643w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w646w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w664w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w667w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w686w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w689w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w708w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w711w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w727w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w730w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_dir_w_range632w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_dir_w_range654w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_dir_w_range675w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_dir_w_range699w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_dir_w_range718w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sbit_w_range695w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sbit_w_range717w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sbit_w_range630w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sbit_w_range653w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sbit_w_range673w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sel_w_range635w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sel_w_range656w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sel_w_range678w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sel_w_range701w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sel_w_range720w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_smux_w_range723w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_smux_w_range682w : STD_LOGIC_VECTOR (25 DOWNTO 0);
BEGIN
loop0 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range635w648w649w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range635w648w(0) AND wire_lbarrel_shift_w646w(i);
END GENERATE loop0;
loop1 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range635w644w645w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range635w644w(0) AND wire_lbarrel_shift_w643w(i);
END GENERATE loop1;
loop2 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range656w669w670w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range656w669w(0) AND wire_lbarrel_shift_w667w(i);
END GENERATE loop2;
loop3 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range656w665w666w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range656w665w(0) AND wire_lbarrel_shift_w664w(i);
END GENERATE loop3;
loop4 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range678w691w692w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range678w691w(0) AND wire_lbarrel_shift_w689w(i);
END GENERATE loop4;
loop5 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range678w687w688w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range678w687w(0) AND wire_lbarrel_shift_w686w(i);
END GENERATE loop5;
loop6 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range701w713w714w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range701w713w(0) AND wire_lbarrel_shift_w711w(i);
END GENERATE loop6;
loop7 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range701w709w710w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range701w709w(0) AND wire_lbarrel_shift_w708w(i);
END GENERATE loop7;
loop8 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range720w732w733w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range720w732w(0) AND wire_lbarrel_shift_w730w(i);
END GENERATE loop8;
loop9 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range720w728w729w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range720w728w(0) AND wire_lbarrel_shift_w727w(i);
END GENERATE loop9;
loop10 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range635w640w641w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range635w640w(0) AND wire_lbarrel_shift_w_sbit_w_range630w(i);
END GENERATE loop10;
loop11 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range656w661w662w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range656w661w(0) AND wire_lbarrel_shift_w_sbit_w_range653w(i);
END GENERATE loop11;
loop12 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range678w683w684w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range678w683w(0) AND wire_lbarrel_shift_w_sbit_w_range673w(i);
END GENERATE loop12;
loop13 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range701w705w706w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range701w705w(0) AND wire_lbarrel_shift_w_sbit_w_range695w(i);
END GENERATE loop13;
loop14 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range720w724w725w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range720w724w(0) AND wire_lbarrel_shift_w_sbit_w_range717w(i);
END GENERATE loop14;
wire_lbarrel_shift_w_lg_w_sel_w_range635w648w(0) <= wire_lbarrel_shift_w_sel_w_range635w(0) AND wire_lbarrel_shift_w_lg_w_dir_w_range632w647w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range635w644w(0) <= wire_lbarrel_shift_w_sel_w_range635w(0) AND wire_lbarrel_shift_w_dir_w_range632w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range656w669w(0) <= wire_lbarrel_shift_w_sel_w_range656w(0) AND wire_lbarrel_shift_w_lg_w_dir_w_range654w668w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range656w665w(0) <= wire_lbarrel_shift_w_sel_w_range656w(0) AND wire_lbarrel_shift_w_dir_w_range654w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range678w691w(0) <= wire_lbarrel_shift_w_sel_w_range678w(0) AND wire_lbarrel_shift_w_lg_w_dir_w_range675w690w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range678w687w(0) <= wire_lbarrel_shift_w_sel_w_range678w(0) AND wire_lbarrel_shift_w_dir_w_range675w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range701w713w(0) <= wire_lbarrel_shift_w_sel_w_range701w(0) AND wire_lbarrel_shift_w_lg_w_dir_w_range699w712w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range701w709w(0) <= wire_lbarrel_shift_w_sel_w_range701w(0) AND wire_lbarrel_shift_w_dir_w_range699w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range720w732w(0) <= wire_lbarrel_shift_w_sel_w_range720w(0) AND wire_lbarrel_shift_w_lg_w_dir_w_range718w731w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range720w728w(0) <= wire_lbarrel_shift_w_sel_w_range720w(0) AND wire_lbarrel_shift_w_dir_w_range718w(0);
wire_lbarrel_shift_w_lg_w_dir_w_range632w647w(0) <= NOT wire_lbarrel_shift_w_dir_w_range632w(0);
wire_lbarrel_shift_w_lg_w_dir_w_range654w668w(0) <= NOT wire_lbarrel_shift_w_dir_w_range654w(0);
wire_lbarrel_shift_w_lg_w_dir_w_range675w690w(0) <= NOT wire_lbarrel_shift_w_dir_w_range675w(0);
wire_lbarrel_shift_w_lg_w_dir_w_range699w712w(0) <= NOT wire_lbarrel_shift_w_dir_w_range699w(0);
wire_lbarrel_shift_w_lg_w_dir_w_range718w731w(0) <= NOT wire_lbarrel_shift_w_dir_w_range718w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range635w640w(0) <= NOT wire_lbarrel_shift_w_sel_w_range635w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range656w661w(0) <= NOT wire_lbarrel_shift_w_sel_w_range656w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range678w683w(0) <= NOT wire_lbarrel_shift_w_sel_w_range678w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range701w705w(0) <= NOT wire_lbarrel_shift_w_sel_w_range701w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range720w724w(0) <= NOT wire_lbarrel_shift_w_sel_w_range720w(0);
loop15 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range635w648w649w650w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range635w648w649w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range635w644w645w(i);
END GENERATE loop15;
loop16 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range656w669w670w671w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range656w669w670w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range656w665w666w(i);
END GENERATE loop16;
loop17 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range678w691w692w693w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range678w691w692w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range678w687w688w(i);
END GENERATE loop17;
loop18 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range701w713w714w715w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range701w713w714w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range701w709w710w(i);
END GENERATE loop18;
loop19 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range720w732w733w734w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range720w732w733w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range720w728w729w(i);
END GENERATE loop19;
loop20 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w651w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range635w648w649w650w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range635w640w641w(i);
END GENERATE loop20;
loop21 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w672w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range656w669w670w671w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range656w661w662w(i);
END GENERATE loop21;
loop22 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w694w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range678w691w692w693w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range678w683w684w(i);
END GENERATE loop22;
loop23 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w716w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range701w713w714w715w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range701w705w706w(i);
END GENERATE loop23;
loop24 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w735w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range720w732w733w734w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range720w724w725w(i);
END GENERATE loop24;
dir_w <= ( dir_pipe(1) & dir_w(3) & dir_pipe(0) & dir_w(1 DOWNTO 0) & direction_w);
direction_w <= '0';
pad_w <= (OTHERS => '0');
result <= sbit_w(155 DOWNTO 130);
sbit_w <= ( sbit_piper2d & smux_w(103 DOWNTO 78) & sbit_piper1d & smux_w(51 DOWNTO 0) & data);
sel_w <= ( sel_pipec4r1d & sel_pipec3r1d & distance(2 DOWNTO 0));
smux_w <= ( wire_lbarrel_shift_w735w & wire_lbarrel_shift_w716w & wire_lbarrel_shift_w694w & wire_lbarrel_shift_w672w & wire_lbarrel_shift_w651w);
wire_lbarrel_shift_w643w <= ( pad_w(0) & sbit_w(25 DOWNTO 1));
wire_lbarrel_shift_w646w <= ( sbit_w(24 DOWNTO 0) & pad_w(0));
wire_lbarrel_shift_w664w <= ( pad_w(1 DOWNTO 0) & sbit_w(51 DOWNTO 28));
wire_lbarrel_shift_w667w <= ( sbit_w(49 DOWNTO 26) & pad_w(1 DOWNTO 0));
wire_lbarrel_shift_w686w <= ( pad_w(3 DOWNTO 0) & sbit_w(77 DOWNTO 56));
wire_lbarrel_shift_w689w <= ( sbit_w(73 DOWNTO 52) & pad_w(3 DOWNTO 0));
wire_lbarrel_shift_w708w <= ( pad_w(7 DOWNTO 0) & sbit_w(103 DOWNTO 86));
wire_lbarrel_shift_w711w <= ( sbit_w(95 DOWNTO 78) & pad_w(7 DOWNTO 0));
wire_lbarrel_shift_w727w <= ( pad_w(15 DOWNTO 0) & sbit_w(129 DOWNTO 120));
wire_lbarrel_shift_w730w <= ( sbit_w(113 DOWNTO 104) & pad_w(15 DOWNTO 0));
wire_lbarrel_shift_w_dir_w_range632w(0) <= dir_w(0);
wire_lbarrel_shift_w_dir_w_range654w(0) <= dir_w(1);
wire_lbarrel_shift_w_dir_w_range675w(0) <= dir_w(2);
wire_lbarrel_shift_w_dir_w_range699w(0) <= dir_w(3);
wire_lbarrel_shift_w_dir_w_range718w(0) <= dir_w(4);
wire_lbarrel_shift_w_sbit_w_range695w <= sbit_w(103 DOWNTO 78);
wire_lbarrel_shift_w_sbit_w_range717w <= sbit_w(129 DOWNTO 104);
wire_lbarrel_shift_w_sbit_w_range630w <= sbit_w(25 DOWNTO 0);
wire_lbarrel_shift_w_sbit_w_range653w <= sbit_w(51 DOWNTO 26);
wire_lbarrel_shift_w_sbit_w_range673w <= sbit_w(77 DOWNTO 52);
wire_lbarrel_shift_w_sel_w_range635w(0) <= sel_w(0);
wire_lbarrel_shift_w_sel_w_range656w(0) <= sel_w(1);
wire_lbarrel_shift_w_sel_w_range678w(0) <= sel_w(2);
wire_lbarrel_shift_w_sel_w_range701w(0) <= sel_w(3);
wire_lbarrel_shift_w_sel_w_range720w(0) <= sel_w(4);
wire_lbarrel_shift_w_smux_w_range723w <= smux_w(129 DOWNTO 104);
wire_lbarrel_shift_w_smux_w_range682w <= smux_w(77 DOWNTO 52);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN dir_pipe <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN dir_pipe <= ( dir_w(4) & dir_w(2));
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sbit_piper1d <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sbit_piper1d <= wire_lbarrel_shift_w_smux_w_range682w;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sbit_piper2d <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sbit_piper2d <= wire_lbarrel_shift_w_smux_w_range723w;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sel_pipec3r1d <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sel_pipec3r1d <= distance(3);
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sel_pipec4r1d <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sel_pipec4r1d <= distance(4);
END IF;
END IF;
END PROCESS;
END RTL; --add_flt_stratix5_area_altbarrel_shift_oud
--altbarrel_shift CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix V" PIPELINE=2 REGISTER_OUTPUT="NO" SHIFTDIR="RIGHT" WIDTH=26 WIDTHDIST=5 aclr clk_en clock data distance result
--VERSION_BEGIN 13.1 cbx_altbarrel_shift 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--synthesis_resources = reg 58
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_area_altbarrel_shift_u1g IS
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (25 DOWNTO 0);
distance : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (25 DOWNTO 0)
);
END add_flt_stratix5_area_altbarrel_shift_u1g;
ARCHITECTURE RTL OF add_flt_stratix5_area_altbarrel_shift_u1g IS
SIGNAL dir_pipe : STD_LOGIC_VECTOR(1 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL sbit_piper1d : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL sbit_piper2d : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL sel_pipec2r1d : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sel_pipec3r1d : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sel_pipec4r1d : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sel_pipec4r2d : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range746w759w760w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range746w755w756w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range767w780w781w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range767w776w777w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range790w802w803w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range790w798w799w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range809w821w822w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range809w817w818w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range830w842w843w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range830w838w839w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range746w751w752w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range767w772w773w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range790w794w795w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range809w813w814w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range830w834w835w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range746w759w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range746w755w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range767w780w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range767w776w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range790w802w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range790w798w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range809w821w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range809w817w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range830w842w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range830w838w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_dir_w_range743w758w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_dir_w_range765w779w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_dir_w_range788w801w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_dir_w_range807w820w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_dir_w_range828w841w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range746w751w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range767w772w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range790w794w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range809w813w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range830w834w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range746w759w760w761w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range767w780w781w782w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range790w802w803w804w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range809w821w822w823w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range830w842w843w844w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w762w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w783w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w805w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w824w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w845w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL dir_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL direction_w : STD_LOGIC;
SIGNAL pad_w : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sbit_w : STD_LOGIC_VECTOR (155 DOWNTO 0);
SIGNAL sel_w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL smux_w : STD_LOGIC_VECTOR (129 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w754w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w757w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w775w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w778w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w797w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w800w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w816w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w819w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w837w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w840w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_dir_w_range743w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_dir_w_range765w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_dir_w_range788w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_dir_w_range807w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_dir_w_range828w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sbit_w_range806w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sbit_w_range825w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sbit_w_range741w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sbit_w_range764w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sbit_w_range784w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sel_w_range746w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sel_w_range767w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sel_w_range790w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sel_w_range809w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sel_w_range830w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_smux_w_range812w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_smux_w_range771w : STD_LOGIC_VECTOR (25 DOWNTO 0);
BEGIN
loop25 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range746w759w760w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range746w759w(0) AND wire_rbarrel_shift_w757w(i);
END GENERATE loop25;
loop26 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range746w755w756w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range746w755w(0) AND wire_rbarrel_shift_w754w(i);
END GENERATE loop26;
loop27 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range767w780w781w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range767w780w(0) AND wire_rbarrel_shift_w778w(i);
END GENERATE loop27;
loop28 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range767w776w777w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range767w776w(0) AND wire_rbarrel_shift_w775w(i);
END GENERATE loop28;
loop29 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range790w802w803w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range790w802w(0) AND wire_rbarrel_shift_w800w(i);
END GENERATE loop29;
loop30 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range790w798w799w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range790w798w(0) AND wire_rbarrel_shift_w797w(i);
END GENERATE loop30;
loop31 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range809w821w822w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range809w821w(0) AND wire_rbarrel_shift_w819w(i);
END GENERATE loop31;
loop32 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range809w817w818w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range809w817w(0) AND wire_rbarrel_shift_w816w(i);
END GENERATE loop32;
loop33 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range830w842w843w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range830w842w(0) AND wire_rbarrel_shift_w840w(i);
END GENERATE loop33;
loop34 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range830w838w839w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range830w838w(0) AND wire_rbarrel_shift_w837w(i);
END GENERATE loop34;
loop35 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range746w751w752w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range746w751w(0) AND wire_rbarrel_shift_w_sbit_w_range741w(i);
END GENERATE loop35;
loop36 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range767w772w773w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range767w772w(0) AND wire_rbarrel_shift_w_sbit_w_range764w(i);
END GENERATE loop36;
loop37 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range790w794w795w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range790w794w(0) AND wire_rbarrel_shift_w_sbit_w_range784w(i);
END GENERATE loop37;
loop38 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range809w813w814w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range809w813w(0) AND wire_rbarrel_shift_w_sbit_w_range806w(i);
END GENERATE loop38;
loop39 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range830w834w835w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range830w834w(0) AND wire_rbarrel_shift_w_sbit_w_range825w(i);
END GENERATE loop39;
wire_rbarrel_shift_w_lg_w_sel_w_range746w759w(0) <= wire_rbarrel_shift_w_sel_w_range746w(0) AND wire_rbarrel_shift_w_lg_w_dir_w_range743w758w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range746w755w(0) <= wire_rbarrel_shift_w_sel_w_range746w(0) AND wire_rbarrel_shift_w_dir_w_range743w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range767w780w(0) <= wire_rbarrel_shift_w_sel_w_range767w(0) AND wire_rbarrel_shift_w_lg_w_dir_w_range765w779w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range767w776w(0) <= wire_rbarrel_shift_w_sel_w_range767w(0) AND wire_rbarrel_shift_w_dir_w_range765w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range790w802w(0) <= wire_rbarrel_shift_w_sel_w_range790w(0) AND wire_rbarrel_shift_w_lg_w_dir_w_range788w801w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range790w798w(0) <= wire_rbarrel_shift_w_sel_w_range790w(0) AND wire_rbarrel_shift_w_dir_w_range788w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range809w821w(0) <= wire_rbarrel_shift_w_sel_w_range809w(0) AND wire_rbarrel_shift_w_lg_w_dir_w_range807w820w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range809w817w(0) <= wire_rbarrel_shift_w_sel_w_range809w(0) AND wire_rbarrel_shift_w_dir_w_range807w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range830w842w(0) <= wire_rbarrel_shift_w_sel_w_range830w(0) AND wire_rbarrel_shift_w_lg_w_dir_w_range828w841w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range830w838w(0) <= wire_rbarrel_shift_w_sel_w_range830w(0) AND wire_rbarrel_shift_w_dir_w_range828w(0);
wire_rbarrel_shift_w_lg_w_dir_w_range743w758w(0) <= NOT wire_rbarrel_shift_w_dir_w_range743w(0);
wire_rbarrel_shift_w_lg_w_dir_w_range765w779w(0) <= NOT wire_rbarrel_shift_w_dir_w_range765w(0);
wire_rbarrel_shift_w_lg_w_dir_w_range788w801w(0) <= NOT wire_rbarrel_shift_w_dir_w_range788w(0);
wire_rbarrel_shift_w_lg_w_dir_w_range807w820w(0) <= NOT wire_rbarrel_shift_w_dir_w_range807w(0);
wire_rbarrel_shift_w_lg_w_dir_w_range828w841w(0) <= NOT wire_rbarrel_shift_w_dir_w_range828w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range746w751w(0) <= NOT wire_rbarrel_shift_w_sel_w_range746w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range767w772w(0) <= NOT wire_rbarrel_shift_w_sel_w_range767w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range790w794w(0) <= NOT wire_rbarrel_shift_w_sel_w_range790w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range809w813w(0) <= NOT wire_rbarrel_shift_w_sel_w_range809w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range830w834w(0) <= NOT wire_rbarrel_shift_w_sel_w_range830w(0);
loop40 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range746w759w760w761w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range746w759w760w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range746w755w756w(i);
END GENERATE loop40;
loop41 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range767w780w781w782w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range767w780w781w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range767w776w777w(i);
END GENERATE loop41;
loop42 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range790w802w803w804w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range790w802w803w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range790w798w799w(i);
END GENERATE loop42;
loop43 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range809w821w822w823w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range809w821w822w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range809w817w818w(i);
END GENERATE loop43;
loop44 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range830w842w843w844w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range830w842w843w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range830w838w839w(i);
END GENERATE loop44;
loop45 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w762w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range746w759w760w761w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range746w751w752w(i);
END GENERATE loop45;
loop46 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w783w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range767w780w781w782w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range767w772w773w(i);
END GENERATE loop46;
loop47 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w805w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range790w802w803w804w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range790w794w795w(i);
END GENERATE loop47;
loop48 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w824w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range809w821w822w823w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range809w813w814w(i);
END GENERATE loop48;
loop49 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w845w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range830w842w843w844w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range830w834w835w(i);
END GENERATE loop49;
dir_w <= ( dir_w(4) & dir_pipe(1) & dir_w(2) & dir_pipe(0) & dir_w(0) & direction_w);
direction_w <= '1';
pad_w <= (OTHERS => '0');
result <= sbit_w(155 DOWNTO 130);
sbit_w <= ( smux_w(129 DOWNTO 104) & sbit_piper2d & smux_w(77 DOWNTO 52) & sbit_piper1d & smux_w(25 DOWNTO 0) & data);
sel_w <= ( sel_pipec4r2d & sel_pipec3r1d & sel_pipec2r1d & distance(1 DOWNTO 0));
smux_w <= ( wire_rbarrel_shift_w845w & wire_rbarrel_shift_w824w & wire_rbarrel_shift_w805w & wire_rbarrel_shift_w783w & wire_rbarrel_shift_w762w);
wire_rbarrel_shift_w754w <= ( pad_w(0) & sbit_w(25 DOWNTO 1));
wire_rbarrel_shift_w757w <= ( sbit_w(24 DOWNTO 0) & pad_w(0));
wire_rbarrel_shift_w775w <= ( pad_w(1 DOWNTO 0) & sbit_w(51 DOWNTO 28));
wire_rbarrel_shift_w778w <= ( sbit_w(49 DOWNTO 26) & pad_w(1 DOWNTO 0));
wire_rbarrel_shift_w797w <= ( pad_w(3 DOWNTO 0) & sbit_w(77 DOWNTO 56));
wire_rbarrel_shift_w800w <= ( sbit_w(73 DOWNTO 52) & pad_w(3 DOWNTO 0));
wire_rbarrel_shift_w816w <= ( pad_w(7 DOWNTO 0) & sbit_w(103 DOWNTO 86));
wire_rbarrel_shift_w819w <= ( sbit_w(95 DOWNTO 78) & pad_w(7 DOWNTO 0));
wire_rbarrel_shift_w837w <= ( pad_w(15 DOWNTO 0) & sbit_w(129 DOWNTO 120));
wire_rbarrel_shift_w840w <= ( sbit_w(113 DOWNTO 104) & pad_w(15 DOWNTO 0));
wire_rbarrel_shift_w_dir_w_range743w(0) <= dir_w(0);
wire_rbarrel_shift_w_dir_w_range765w(0) <= dir_w(1);
wire_rbarrel_shift_w_dir_w_range788w(0) <= dir_w(2);
wire_rbarrel_shift_w_dir_w_range807w(0) <= dir_w(3);
wire_rbarrel_shift_w_dir_w_range828w(0) <= dir_w(4);
wire_rbarrel_shift_w_sbit_w_range806w <= sbit_w(103 DOWNTO 78);
wire_rbarrel_shift_w_sbit_w_range825w <= sbit_w(129 DOWNTO 104);
wire_rbarrel_shift_w_sbit_w_range741w <= sbit_w(25 DOWNTO 0);
wire_rbarrel_shift_w_sbit_w_range764w <= sbit_w(51 DOWNTO 26);
wire_rbarrel_shift_w_sbit_w_range784w <= sbit_w(77 DOWNTO 52);
wire_rbarrel_shift_w_sel_w_range746w(0) <= sel_w(0);
wire_rbarrel_shift_w_sel_w_range767w(0) <= sel_w(1);
wire_rbarrel_shift_w_sel_w_range790w(0) <= sel_w(2);
wire_rbarrel_shift_w_sel_w_range809w(0) <= sel_w(3);
wire_rbarrel_shift_w_sel_w_range830w(0) <= sel_w(4);
wire_rbarrel_shift_w_smux_w_range812w <= smux_w(103 DOWNTO 78);
wire_rbarrel_shift_w_smux_w_range771w <= smux_w(51 DOWNTO 26);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN dir_pipe <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN dir_pipe <= ( dir_w(3) & dir_w(1));
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sbit_piper1d <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sbit_piper1d <= wire_rbarrel_shift_w_smux_w_range771w;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sbit_piper2d <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sbit_piper2d <= wire_rbarrel_shift_w_smux_w_range812w;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sel_pipec2r1d <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sel_pipec2r1d <= distance(2);
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sel_pipec3r1d <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sel_pipec3r1d <= distance(3);
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sel_pipec4r1d <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sel_pipec4r1d <= distance(4);
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sel_pipec4r2d <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sel_pipec4r2d <= sel_pipec4r1d;
END IF;
END IF;
END PROCESS;
END RTL; --add_flt_stratix5_area_altbarrel_shift_u1g
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" PIPELINE=1 WIDTH=32 WIDTHAD=5 aclr clk_en clock data q
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" PIPELINE=0 WIDTH=16 WIDTHAD=4 data q
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=8 WIDTHAD=3 data q
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=4 WIDTHAD=2 data q
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=2 WIDTHAD=1 data q
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_area_altpriority_encoder_3v7 IS
PORT
(
data : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END add_flt_stratix5_area_altpriority_encoder_3v7;
ARCHITECTURE RTL OF add_flt_stratix5_area_altpriority_encoder_3v7 IS
BEGIN
q(0) <= ( data(1));
END RTL; --add_flt_stratix5_area_altpriority_encoder_3v7
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=2 WIDTHAD=1 data q zero
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_area_altpriority_encoder_3e8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END add_flt_stratix5_area_altpriority_encoder_3e8;
ARCHITECTURE RTL OF add_flt_stratix5_area_altpriority_encoder_3e8 IS
BEGIN
q(0) <= ( data(1));
zero <= (NOT (data(0) OR data(1)));
END RTL; --add_flt_stratix5_area_altpriority_encoder_3e8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_area_altpriority_encoder_6v7 IS
PORT
(
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END add_flt_stratix5_area_altpriority_encoder_6v7;
ARCHITECTURE RTL OF add_flt_stratix5_area_altpriority_encoder_6v7 IS
SIGNAL wire_altpriority_encoder16_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder17_w_lg_w_lg_zero878w879w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder17_w_lg_zero880w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder17_w_lg_zero878w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder17_w_lg_w_lg_zero880w881w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder17_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder17_zero : STD_LOGIC;
COMPONENT add_flt_stratix5_area_altpriority_encoder_3v7
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT;
COMPONENT add_flt_stratix5_area_altpriority_encoder_3e8
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder17_w_lg_zero878w & wire_altpriority_encoder17_w_lg_w_lg_zero880w881w);
altpriority_encoder16 : add_flt_stratix5_area_altpriority_encoder_3v7
PORT MAP (
data => data(1 DOWNTO 0),
q => wire_altpriority_encoder16_q
);
wire_altpriority_encoder17_w_lg_w_lg_zero878w879w(0) <= wire_altpriority_encoder17_w_lg_zero878w(0) AND wire_altpriority_encoder17_q(0);
wire_altpriority_encoder17_w_lg_zero880w(0) <= wire_altpriority_encoder17_zero AND wire_altpriority_encoder16_q(0);
wire_altpriority_encoder17_w_lg_zero878w(0) <= NOT wire_altpriority_encoder17_zero;
wire_altpriority_encoder17_w_lg_w_lg_zero880w881w(0) <= wire_altpriority_encoder17_w_lg_zero880w(0) OR wire_altpriority_encoder17_w_lg_w_lg_zero878w879w(0);
altpriority_encoder17 : add_flt_stratix5_area_altpriority_encoder_3e8
PORT MAP (
data => data(3 DOWNTO 2),
q => wire_altpriority_encoder17_q,
zero => wire_altpriority_encoder17_zero
);
END RTL; --add_flt_stratix5_area_altpriority_encoder_6v7
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=4 WIDTHAD=2 data q zero
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_area_altpriority_encoder_6e8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END add_flt_stratix5_area_altpriority_encoder_6e8;
ARCHITECTURE RTL OF add_flt_stratix5_area_altpriority_encoder_6e8 IS
SIGNAL wire_altpriority_encoder18_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder19_w_lg_w_lg_zero896w897w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder19_w_lg_zero898w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder19_w_lg_zero896w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder19_w_lg_w_lg_zero898w899w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder19_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder19_zero : STD_LOGIC;
COMPONENT add_flt_stratix5_area_altpriority_encoder_3e8
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder19_w_lg_zero896w & wire_altpriority_encoder19_w_lg_w_lg_zero898w899w);
zero <= (wire_altpriority_encoder18_zero AND wire_altpriority_encoder19_zero);
altpriority_encoder18 : add_flt_stratix5_area_altpriority_encoder_3e8
PORT MAP (
data => data(1 DOWNTO 0),
q => wire_altpriority_encoder18_q,
zero => wire_altpriority_encoder18_zero
);
wire_altpriority_encoder19_w_lg_w_lg_zero896w897w(0) <= wire_altpriority_encoder19_w_lg_zero896w(0) AND wire_altpriority_encoder19_q(0);
wire_altpriority_encoder19_w_lg_zero898w(0) <= wire_altpriority_encoder19_zero AND wire_altpriority_encoder18_q(0);
wire_altpriority_encoder19_w_lg_zero896w(0) <= NOT wire_altpriority_encoder19_zero;
wire_altpriority_encoder19_w_lg_w_lg_zero898w899w(0) <= wire_altpriority_encoder19_w_lg_zero898w(0) OR wire_altpriority_encoder19_w_lg_w_lg_zero896w897w(0);
altpriority_encoder19 : add_flt_stratix5_area_altpriority_encoder_3e8
PORT MAP (
data => data(3 DOWNTO 2),
q => wire_altpriority_encoder19_q,
zero => wire_altpriority_encoder19_zero
);
END RTL; --add_flt_stratix5_area_altpriority_encoder_6e8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_area_altpriority_encoder_bv7 IS
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
);
END add_flt_stratix5_area_altpriority_encoder_bv7;
ARCHITECTURE RTL OF add_flt_stratix5_area_altpriority_encoder_bv7 IS
SIGNAL wire_altpriority_encoder14_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder15_w_lg_w_lg_zero869w870w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder15_w_lg_zero871w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder15_w_lg_zero869w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder15_w_lg_w_lg_zero871w872w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder15_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder15_zero : STD_LOGIC;
COMPONENT add_flt_stratix5_area_altpriority_encoder_6v7
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END COMPONENT;
COMPONENT add_flt_stratix5_area_altpriority_encoder_6e8
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder15_w_lg_zero869w & wire_altpriority_encoder15_w_lg_w_lg_zero871w872w);
altpriority_encoder14 : add_flt_stratix5_area_altpriority_encoder_6v7
PORT MAP (
data => data(3 DOWNTO 0),
q => wire_altpriority_encoder14_q
);
loop50 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder15_w_lg_w_lg_zero869w870w(i) <= wire_altpriority_encoder15_w_lg_zero869w(0) AND wire_altpriority_encoder15_q(i);
END GENERATE loop50;
loop51 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder15_w_lg_zero871w(i) <= wire_altpriority_encoder15_zero AND wire_altpriority_encoder14_q(i);
END GENERATE loop51;
wire_altpriority_encoder15_w_lg_zero869w(0) <= NOT wire_altpriority_encoder15_zero;
loop52 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder15_w_lg_w_lg_zero871w872w(i) <= wire_altpriority_encoder15_w_lg_zero871w(i) OR wire_altpriority_encoder15_w_lg_w_lg_zero869w870w(i);
END GENERATE loop52;
altpriority_encoder15 : add_flt_stratix5_area_altpriority_encoder_6e8
PORT MAP (
data => data(7 DOWNTO 4),
q => wire_altpriority_encoder15_q,
zero => wire_altpriority_encoder15_zero
);
END RTL; --add_flt_stratix5_area_altpriority_encoder_bv7
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=8 WIDTHAD=3 data q zero
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_area_altpriority_encoder_be8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END add_flt_stratix5_area_altpriority_encoder_be8;
ARCHITECTURE RTL OF add_flt_stratix5_area_altpriority_encoder_be8 IS
SIGNAL wire_altpriority_encoder20_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder20_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder21_w_lg_w_lg_zero906w907w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_w_lg_zero908w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_w_lg_zero906w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_w_lg_w_lg_zero908w909w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_zero : STD_LOGIC;
COMPONENT add_flt_stratix5_area_altpriority_encoder_6e8
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder21_w_lg_zero906w & wire_altpriority_encoder21_w_lg_w_lg_zero908w909w);
zero <= (wire_altpriority_encoder20_zero AND wire_altpriority_encoder21_zero);
altpriority_encoder20 : add_flt_stratix5_area_altpriority_encoder_6e8
PORT MAP (
data => data(3 DOWNTO 0),
q => wire_altpriority_encoder20_q,
zero => wire_altpriority_encoder20_zero
);
loop53 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder21_w_lg_w_lg_zero906w907w(i) <= wire_altpriority_encoder21_w_lg_zero906w(0) AND wire_altpriority_encoder21_q(i);
END GENERATE loop53;
loop54 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder21_w_lg_zero908w(i) <= wire_altpriority_encoder21_zero AND wire_altpriority_encoder20_q(i);
END GENERATE loop54;
wire_altpriority_encoder21_w_lg_zero906w(0) <= NOT wire_altpriority_encoder21_zero;
loop55 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder21_w_lg_w_lg_zero908w909w(i) <= wire_altpriority_encoder21_w_lg_zero908w(i) OR wire_altpriority_encoder21_w_lg_w_lg_zero906w907w(i);
END GENERATE loop55;
altpriority_encoder21 : add_flt_stratix5_area_altpriority_encoder_6e8
PORT MAP (
data => data(7 DOWNTO 4),
q => wire_altpriority_encoder21_q,
zero => wire_altpriority_encoder21_zero
);
END RTL; --add_flt_stratix5_area_altpriority_encoder_be8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_area_altpriority_encoder_uv8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END add_flt_stratix5_area_altpriority_encoder_uv8;
ARCHITECTURE RTL OF add_flt_stratix5_area_altpriority_encoder_uv8 IS
SIGNAL wire_altpriority_encoder12_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder13_w_lg_w_lg_zero860w861w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder13_w_lg_zero862w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder13_w_lg_zero860w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder13_w_lg_w_lg_zero862w863w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder13_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder13_zero : STD_LOGIC;
COMPONENT add_flt_stratix5_area_altpriority_encoder_bv7
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
);
END COMPONENT;
COMPONENT add_flt_stratix5_area_altpriority_encoder_be8
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder13_w_lg_zero860w & wire_altpriority_encoder13_w_lg_w_lg_zero862w863w);
altpriority_encoder12 : add_flt_stratix5_area_altpriority_encoder_bv7
PORT MAP (
data => data(7 DOWNTO 0),
q => wire_altpriority_encoder12_q
);
loop56 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder13_w_lg_w_lg_zero860w861w(i) <= wire_altpriority_encoder13_w_lg_zero860w(0) AND wire_altpriority_encoder13_q(i);
END GENERATE loop56;
loop57 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder13_w_lg_zero862w(i) <= wire_altpriority_encoder13_zero AND wire_altpriority_encoder12_q(i);
END GENERATE loop57;
wire_altpriority_encoder13_w_lg_zero860w(0) <= NOT wire_altpriority_encoder13_zero;
loop58 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder13_w_lg_w_lg_zero862w863w(i) <= wire_altpriority_encoder13_w_lg_zero862w(i) OR wire_altpriority_encoder13_w_lg_w_lg_zero860w861w(i);
END GENERATE loop58;
altpriority_encoder13 : add_flt_stratix5_area_altpriority_encoder_be8
PORT MAP (
data => data(15 DOWNTO 8),
q => wire_altpriority_encoder13_q,
zero => wire_altpriority_encoder13_zero
);
END RTL; --add_flt_stratix5_area_altpriority_encoder_uv8
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" PIPELINE=0 WIDTH=16 WIDTHAD=4 data q zero
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_area_altpriority_encoder_ue9 IS
PORT
(
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
zero : OUT STD_LOGIC
);
END add_flt_stratix5_area_altpriority_encoder_ue9;
ARCHITECTURE RTL OF add_flt_stratix5_area_altpriority_encoder_ue9 IS
SIGNAL wire_altpriority_encoder22_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder22_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder23_w_lg_w_lg_zero916w917w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder23_w_lg_zero918w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder23_w_lg_zero916w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder23_w_lg_w_lg_zero918w919w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder23_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder23_zero : STD_LOGIC;
COMPONENT add_flt_stratix5_area_altpriority_encoder_be8
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder23_w_lg_zero916w & wire_altpriority_encoder23_w_lg_w_lg_zero918w919w);
zero <= (wire_altpriority_encoder22_zero AND wire_altpriority_encoder23_zero);
altpriority_encoder22 : add_flt_stratix5_area_altpriority_encoder_be8
PORT MAP (
data => data(7 DOWNTO 0),
q => wire_altpriority_encoder22_q,
zero => wire_altpriority_encoder22_zero
);
loop59 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder23_w_lg_w_lg_zero916w917w(i) <= wire_altpriority_encoder23_w_lg_zero916w(0) AND wire_altpriority_encoder23_q(i);
END GENERATE loop59;
loop60 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder23_w_lg_zero918w(i) <= wire_altpriority_encoder23_zero AND wire_altpriority_encoder22_q(i);
END GENERATE loop60;
wire_altpriority_encoder23_w_lg_zero916w(0) <= NOT wire_altpriority_encoder23_zero;
loop61 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder23_w_lg_w_lg_zero918w919w(i) <= wire_altpriority_encoder23_w_lg_zero918w(i) OR wire_altpriority_encoder23_w_lg_w_lg_zero916w917w(i);
END GENERATE loop61;
altpriority_encoder23 : add_flt_stratix5_area_altpriority_encoder_be8
PORT MAP (
data => data(15 DOWNTO 8),
q => wire_altpriority_encoder23_q,
zero => wire_altpriority_encoder23_zero
);
END RTL; --add_flt_stratix5_area_altpriority_encoder_ue9
--synthesis_resources = reg 5
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_area_altpriority_encoder_ou8 IS
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END add_flt_stratix5_area_altpriority_encoder_ou8;
ARCHITECTURE RTL OF add_flt_stratix5_area_altpriority_encoder_ou8 IS
SIGNAL wire_altpriority_encoder10_q : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder11_w_lg_w_lg_zero850w851w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder11_w_lg_zero852w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder11_w_lg_zero850w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder11_w_lg_w_lg_zero852w853w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder11_q : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder11_zero : STD_LOGIC;
SIGNAL pipeline_q_dffe : STD_LOGIC_VECTOR(4 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL tmp_q_wire : STD_LOGIC_VECTOR (4 DOWNTO 0);
COMPONENT add_flt_stratix5_area_altpriority_encoder_uv8
PORT
(
data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
COMPONENT add_flt_stratix5_area_altpriority_encoder_ue9
PORT
(
data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= pipeline_q_dffe;
tmp_q_wire <= ( wire_altpriority_encoder11_w_lg_zero850w & wire_altpriority_encoder11_w_lg_w_lg_zero852w853w);
altpriority_encoder10 : add_flt_stratix5_area_altpriority_encoder_uv8
PORT MAP (
data => data(15 DOWNTO 0),
q => wire_altpriority_encoder10_q
);
loop62 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder11_w_lg_w_lg_zero850w851w(i) <= wire_altpriority_encoder11_w_lg_zero850w(0) AND wire_altpriority_encoder11_q(i);
END GENERATE loop62;
loop63 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder11_w_lg_zero852w(i) <= wire_altpriority_encoder11_zero AND wire_altpriority_encoder10_q(i);
END GENERATE loop63;
wire_altpriority_encoder11_w_lg_zero850w(0) <= NOT wire_altpriority_encoder11_zero;
loop64 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder11_w_lg_w_lg_zero852w853w(i) <= wire_altpriority_encoder11_w_lg_zero852w(i) OR wire_altpriority_encoder11_w_lg_w_lg_zero850w851w(i);
END GENERATE loop64;
altpriority_encoder11 : add_flt_stratix5_area_altpriority_encoder_ue9
PORT MAP (
data => data(31 DOWNTO 16),
q => wire_altpriority_encoder11_q,
zero => wire_altpriority_encoder11_zero
);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN pipeline_q_dffe <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN pipeline_q_dffe <= tmp_q_wire;
END IF;
END IF;
END PROCESS;
END RTL; --add_flt_stratix5_area_altpriority_encoder_ou8
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" PIPELINE=2 WIDTH=32 WIDTHAD=5 aclr clk_en clock data q
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" PIPELINE=1 WIDTH=16 WIDTHAD=4 aclr clk_en clock data q zero
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" PIPELINE=0 WIDTH=8 WIDTHAD=3 data q zero
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=4 WIDTHAD=2 data q zero
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=2 WIDTHAD=1 data q zero
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_area_altpriority_encoder_nh8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END add_flt_stratix5_area_altpriority_encoder_nh8;
ARCHITECTURE RTL OF add_flt_stratix5_area_altpriority_encoder_nh8 IS
SIGNAL wire_altpriority_encoder30_w_lg_w_data_range971w973w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder30_w_data_range971w : STD_LOGIC_VECTOR (0 DOWNTO 0);
BEGIN
wire_altpriority_encoder30_w_lg_w_data_range971w973w(0) <= NOT wire_altpriority_encoder30_w_data_range971w(0);
q <= ( wire_altpriority_encoder30_w_lg_w_data_range971w973w);
zero <= (NOT (data(0) OR data(1)));
wire_altpriority_encoder30_w_data_range971w(0) <= data(0);
END RTL; --add_flt_stratix5_area_altpriority_encoder_nh8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_area_altpriority_encoder_qh8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END add_flt_stratix5_area_altpriority_encoder_qh8;
ARCHITECTURE RTL OF add_flt_stratix5_area_altpriority_encoder_qh8 IS
SIGNAL wire_altpriority_encoder30_w_lg_w_lg_zero963w964w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder30_w_lg_zero965w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder30_w_lg_zero963w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder30_w_lg_w_lg_zero965w966w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder30_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder30_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder31_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder31_zero : STD_LOGIC;
COMPONENT add_flt_stratix5_area_altpriority_encoder_nh8
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder30_zero & wire_altpriority_encoder30_w_lg_w_lg_zero965w966w);
zero <= (wire_altpriority_encoder30_zero AND wire_altpriority_encoder31_zero);
wire_altpriority_encoder30_w_lg_w_lg_zero963w964w(0) <= wire_altpriority_encoder30_w_lg_zero963w(0) AND wire_altpriority_encoder30_q(0);
wire_altpriority_encoder30_w_lg_zero965w(0) <= wire_altpriority_encoder30_zero AND wire_altpriority_encoder31_q(0);
wire_altpriority_encoder30_w_lg_zero963w(0) <= NOT wire_altpriority_encoder30_zero;
wire_altpriority_encoder30_w_lg_w_lg_zero965w966w(0) <= wire_altpriority_encoder30_w_lg_zero965w(0) OR wire_altpriority_encoder30_w_lg_w_lg_zero963w964w(0);
altpriority_encoder30 : add_flt_stratix5_area_altpriority_encoder_nh8
PORT MAP (
data => data(1 DOWNTO 0),
q => wire_altpriority_encoder30_q,
zero => wire_altpriority_encoder30_zero
);
altpriority_encoder31 : add_flt_stratix5_area_altpriority_encoder_nh8
PORT MAP (
data => data(3 DOWNTO 2),
q => wire_altpriority_encoder31_q,
zero => wire_altpriority_encoder31_zero
);
END RTL; --add_flt_stratix5_area_altpriority_encoder_qh8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_area_altpriority_encoder_2h9 IS
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END add_flt_stratix5_area_altpriority_encoder_2h9;
ARCHITECTURE RTL OF add_flt_stratix5_area_altpriority_encoder_2h9 IS
SIGNAL wire_altpriority_encoder28_w_lg_w_lg_zero953w954w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder28_w_lg_zero955w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder28_w_lg_zero953w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder28_w_lg_w_lg_zero955w956w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder28_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder28_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder29_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder29_zero : STD_LOGIC;
COMPONENT add_flt_stratix5_area_altpriority_encoder_qh8
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder28_zero & wire_altpriority_encoder28_w_lg_w_lg_zero955w956w);
zero <= (wire_altpriority_encoder28_zero AND wire_altpriority_encoder29_zero);
loop65 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder28_w_lg_w_lg_zero953w954w(i) <= wire_altpriority_encoder28_w_lg_zero953w(0) AND wire_altpriority_encoder28_q(i);
END GENERATE loop65;
loop66 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder28_w_lg_zero955w(i) <= wire_altpriority_encoder28_zero AND wire_altpriority_encoder29_q(i);
END GENERATE loop66;
wire_altpriority_encoder28_w_lg_zero953w(0) <= NOT wire_altpriority_encoder28_zero;
loop67 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder28_w_lg_w_lg_zero955w956w(i) <= wire_altpriority_encoder28_w_lg_zero955w(i) OR wire_altpriority_encoder28_w_lg_w_lg_zero953w954w(i);
END GENERATE loop67;
altpriority_encoder28 : add_flt_stratix5_area_altpriority_encoder_qh8
PORT MAP (
data => data(3 DOWNTO 0),
q => wire_altpriority_encoder28_q,
zero => wire_altpriority_encoder28_zero
);
altpriority_encoder29 : add_flt_stratix5_area_altpriority_encoder_qh8
PORT MAP (
data => data(7 DOWNTO 4),
q => wire_altpriority_encoder29_q,
zero => wire_altpriority_encoder29_zero
);
END RTL; --add_flt_stratix5_area_altpriority_encoder_2h9
--synthesis_resources = reg 5
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_area_altpriority_encoder_d6b IS
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
zero : OUT STD_LOGIC
);
END add_flt_stratix5_area_altpriority_encoder_d6b;
ARCHITECTURE RTL OF add_flt_stratix5_area_altpriority_encoder_d6b IS
SIGNAL wire_altpriority_encoder26_w_lg_w_lg_zero938w939w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder26_w_lg_zero940w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder26_w_lg_zero938w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder26_w_lg_w_lg_zero940w941w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder26_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder26_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder27_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_zero : STD_LOGIC;
SIGNAL pipeline_q_dffe : STD_LOGIC_VECTOR(3 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL pipeline_zero_n_dffe : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_pipeline_zero_n_dffe_w_lg_q950w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder24_w_lg_tmp_q_wire947w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder24_w_lg_tmp_zero_wire948w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL tmp_q_wire : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL tmp_zero_wire : STD_LOGIC;
COMPONENT add_flt_stratix5_area_altpriority_encoder_2h9
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
loop68 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder24_w_lg_tmp_q_wire947w(i) <= NOT tmp_q_wire(i);
END GENERATE loop68;
wire_altpriority_encoder24_w_lg_tmp_zero_wire948w(0) <= NOT tmp_zero_wire;
q <= (NOT pipeline_q_dffe);
tmp_q_wire <= ( wire_altpriority_encoder26_zero & wire_altpriority_encoder26_w_lg_w_lg_zero940w941w);
tmp_zero_wire <= (wire_altpriority_encoder26_zero AND wire_altpriority_encoder27_zero);
zero <= wire_pipeline_zero_n_dffe_w_lg_q950w(0);
loop69 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder26_w_lg_w_lg_zero938w939w(i) <= wire_altpriority_encoder26_w_lg_zero938w(0) AND wire_altpriority_encoder26_q(i);
END GENERATE loop69;
loop70 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder26_w_lg_zero940w(i) <= wire_altpriority_encoder26_zero AND wire_altpriority_encoder27_q(i);
END GENERATE loop70;
wire_altpriority_encoder26_w_lg_zero938w(0) <= NOT wire_altpriority_encoder26_zero;
loop71 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder26_w_lg_w_lg_zero940w941w(i) <= wire_altpriority_encoder26_w_lg_zero940w(i) OR wire_altpriority_encoder26_w_lg_w_lg_zero938w939w(i);
END GENERATE loop71;
altpriority_encoder26 : add_flt_stratix5_area_altpriority_encoder_2h9
PORT MAP (
data => data(7 DOWNTO 0),
q => wire_altpriority_encoder26_q,
zero => wire_altpriority_encoder26_zero
);
altpriority_encoder27 : add_flt_stratix5_area_altpriority_encoder_2h9
PORT MAP (
data => data(15 DOWNTO 8),
q => wire_altpriority_encoder27_q,
zero => wire_altpriority_encoder27_zero
);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN pipeline_q_dffe <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN pipeline_q_dffe <= wire_altpriority_encoder24_w_lg_tmp_q_wire947w;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN pipeline_zero_n_dffe <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN pipeline_zero_n_dffe <= wire_altpriority_encoder24_w_lg_tmp_zero_wire948w(0);
END IF;
END IF;
END PROCESS;
wire_pipeline_zero_n_dffe_w_lg_q950w(0) <= NOT pipeline_zero_n_dffe;
END RTL; --add_flt_stratix5_area_altpriority_encoder_d6b
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" PIPELINE=1 WIDTH=16 WIDTHAD=4 aclr clk_en clock data q
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" PIPELINE=0 WIDTH=8 WIDTHAD=3 data q
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=4 WIDTHAD=2 data q
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=2 WIDTHAD=1 data q
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_area_altpriority_encoder_n28 IS
PORT
(
data : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END add_flt_stratix5_area_altpriority_encoder_n28;
ARCHITECTURE RTL OF add_flt_stratix5_area_altpriority_encoder_n28 IS
SIGNAL wire_altpriority_encoder37_w_lg_w_data_range1008w1010w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder37_w_data_range1008w : STD_LOGIC_VECTOR (0 DOWNTO 0);
BEGIN
wire_altpriority_encoder37_w_lg_w_data_range1008w1010w(0) <= NOT wire_altpriority_encoder37_w_data_range1008w(0);
q <= ( wire_altpriority_encoder37_w_lg_w_data_range1008w1010w);
wire_altpriority_encoder37_w_data_range1008w(0) <= data(0);
END RTL; --add_flt_stratix5_area_altpriority_encoder_n28
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_area_altpriority_encoder_q28 IS
PORT
(
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END add_flt_stratix5_area_altpriority_encoder_q28;
ARCHITECTURE RTL OF add_flt_stratix5_area_altpriority_encoder_q28 IS
SIGNAL wire_altpriority_encoder36_w_lg_w_lg_zero1001w1002w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder36_w_lg_zero1003w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder36_w_lg_zero1001w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder36_w_lg_w_lg_zero1003w1004w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder36_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder36_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder37_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT add_flt_stratix5_area_altpriority_encoder_nh8
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT add_flt_stratix5_area_altpriority_encoder_n28
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder36_zero & wire_altpriority_encoder36_w_lg_w_lg_zero1003w1004w);
wire_altpriority_encoder36_w_lg_w_lg_zero1001w1002w(0) <= wire_altpriority_encoder36_w_lg_zero1001w(0) AND wire_altpriority_encoder36_q(0);
wire_altpriority_encoder36_w_lg_zero1003w(0) <= wire_altpriority_encoder36_zero AND wire_altpriority_encoder37_q(0);
wire_altpriority_encoder36_w_lg_zero1001w(0) <= NOT wire_altpriority_encoder36_zero;
wire_altpriority_encoder36_w_lg_w_lg_zero1003w1004w(0) <= wire_altpriority_encoder36_w_lg_zero1003w(0) OR wire_altpriority_encoder36_w_lg_w_lg_zero1001w1002w(0);
altpriority_encoder36 : add_flt_stratix5_area_altpriority_encoder_nh8
PORT MAP (
data => data(1 DOWNTO 0),
q => wire_altpriority_encoder36_q,
zero => wire_altpriority_encoder36_zero
);
altpriority_encoder37 : add_flt_stratix5_area_altpriority_encoder_n28
PORT MAP (
data => data(3 DOWNTO 2),
q => wire_altpriority_encoder37_q
);
END RTL; --add_flt_stratix5_area_altpriority_encoder_q28
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_area_altpriority_encoder_229 IS
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
);
END add_flt_stratix5_area_altpriority_encoder_229;
ARCHITECTURE RTL OF add_flt_stratix5_area_altpriority_encoder_229 IS
SIGNAL wire_altpriority_encoder34_w_lg_w_lg_zero992w993w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder34_w_lg_zero994w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder34_w_lg_zero992w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder34_w_lg_w_lg_zero994w995w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder34_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder34_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder35_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
COMPONENT add_flt_stratix5_area_altpriority_encoder_qh8
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT add_flt_stratix5_area_altpriority_encoder_q28
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder34_zero & wire_altpriority_encoder34_w_lg_w_lg_zero994w995w);
loop72 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder34_w_lg_w_lg_zero992w993w(i) <= wire_altpriority_encoder34_w_lg_zero992w(0) AND wire_altpriority_encoder34_q(i);
END GENERATE loop72;
loop73 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder34_w_lg_zero994w(i) <= wire_altpriority_encoder34_zero AND wire_altpriority_encoder35_q(i);
END GENERATE loop73;
wire_altpriority_encoder34_w_lg_zero992w(0) <= NOT wire_altpriority_encoder34_zero;
loop74 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder34_w_lg_w_lg_zero994w995w(i) <= wire_altpriority_encoder34_w_lg_zero994w(i) OR wire_altpriority_encoder34_w_lg_w_lg_zero992w993w(i);
END GENERATE loop74;
altpriority_encoder34 : add_flt_stratix5_area_altpriority_encoder_qh8
PORT MAP (
data => data(3 DOWNTO 0),
q => wire_altpriority_encoder34_q,
zero => wire_altpriority_encoder34_zero
);
altpriority_encoder35 : add_flt_stratix5_area_altpriority_encoder_q28
PORT MAP (
data => data(7 DOWNTO 4),
q => wire_altpriority_encoder35_q
);
END RTL; --add_flt_stratix5_area_altpriority_encoder_229
--synthesis_resources = reg 4
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_area_altpriority_encoder_ena IS
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END add_flt_stratix5_area_altpriority_encoder_ena;
ARCHITECTURE RTL OF add_flt_stratix5_area_altpriority_encoder_ena IS
SIGNAL wire_altpriority_encoder32_w_lg_w_lg_zero980w981w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder32_w_lg_zero982w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder32_w_lg_zero980w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder32_w_lg_w_lg_zero982w983w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder32_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder32_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder33_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL pipeline_q_dffe : STD_LOGIC_VECTOR(3 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_altpriority_encoder25_w_lg_tmp_q_wire988w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL tmp_q_wire : STD_LOGIC_VECTOR (3 DOWNTO 0);
COMPONENT add_flt_stratix5_area_altpriority_encoder_2h9
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT add_flt_stratix5_area_altpriority_encoder_229
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
);
END COMPONENT;
BEGIN
loop75 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder25_w_lg_tmp_q_wire988w(i) <= NOT tmp_q_wire(i);
END GENERATE loop75;
q <= (NOT pipeline_q_dffe);
tmp_q_wire <= ( wire_altpriority_encoder32_zero & wire_altpriority_encoder32_w_lg_w_lg_zero982w983w);
loop76 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder32_w_lg_w_lg_zero980w981w(i) <= wire_altpriority_encoder32_w_lg_zero980w(0) AND wire_altpriority_encoder32_q(i);
END GENERATE loop76;
loop77 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder32_w_lg_zero982w(i) <= wire_altpriority_encoder32_zero AND wire_altpriority_encoder33_q(i);
END GENERATE loop77;
wire_altpriority_encoder32_w_lg_zero980w(0) <= NOT wire_altpriority_encoder32_zero;
loop78 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder32_w_lg_w_lg_zero982w983w(i) <= wire_altpriority_encoder32_w_lg_zero982w(i) OR wire_altpriority_encoder32_w_lg_w_lg_zero980w981w(i);
END GENERATE loop78;
altpriority_encoder32 : add_flt_stratix5_area_altpriority_encoder_2h9
PORT MAP (
data => data(7 DOWNTO 0),
q => wire_altpriority_encoder32_q,
zero => wire_altpriority_encoder32_zero
);
altpriority_encoder33 : add_flt_stratix5_area_altpriority_encoder_229
PORT MAP (
data => data(15 DOWNTO 8),
q => wire_altpriority_encoder33_q
);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN pipeline_q_dffe <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN pipeline_q_dffe <= wire_altpriority_encoder25_w_lg_tmp_q_wire988w;
END IF;
END IF;
END PROCESS;
END RTL; --add_flt_stratix5_area_altpriority_encoder_ena
--synthesis_resources = reg 14
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_area_altpriority_encoder_dna IS
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END add_flt_stratix5_area_altpriority_encoder_dna;
ARCHITECTURE RTL OF add_flt_stratix5_area_altpriority_encoder_dna IS
SIGNAL wire_altpriority_encoder24_w_lg_w_lg_zero926w927w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder24_w_lg_zero928w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder24_w_lg_zero926w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder24_w_lg_w_lg_zero928w929w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder24_q : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder24_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder25_q : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL pipeline_q_dffe : STD_LOGIC_VECTOR(4 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_trailing_zeros_cnt_w_lg_tmp_q_wire934w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL tmp_q_wire : STD_LOGIC_VECTOR (4 DOWNTO 0);
COMPONENT add_flt_stratix5_area_altpriority_encoder_d6b
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT add_flt_stratix5_area_altpriority_encoder_ena
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
BEGIN
loop79 : FOR i IN 0 TO 4 GENERATE
wire_trailing_zeros_cnt_w_lg_tmp_q_wire934w(i) <= NOT tmp_q_wire(i);
END GENERATE loop79;
q <= (NOT pipeline_q_dffe);
tmp_q_wire <= ( wire_altpriority_encoder24_zero & wire_altpriority_encoder24_w_lg_w_lg_zero928w929w);
loop80 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder24_w_lg_w_lg_zero926w927w(i) <= wire_altpriority_encoder24_w_lg_zero926w(0) AND wire_altpriority_encoder24_q(i);
END GENERATE loop80;
loop81 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder24_w_lg_zero928w(i) <= wire_altpriority_encoder24_zero AND wire_altpriority_encoder25_q(i);
END GENERATE loop81;
wire_altpriority_encoder24_w_lg_zero926w(0) <= NOT wire_altpriority_encoder24_zero;
loop82 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder24_w_lg_w_lg_zero928w929w(i) <= wire_altpriority_encoder24_w_lg_zero928w(i) OR wire_altpriority_encoder24_w_lg_w_lg_zero926w927w(i);
END GENERATE loop82;
altpriority_encoder24 : add_flt_stratix5_area_altpriority_encoder_d6b
PORT MAP (
aclr => aclr,
clk_en => clk_en,
clock => clock,
data => data(15 DOWNTO 0),
q => wire_altpriority_encoder24_q,
zero => wire_altpriority_encoder24_zero
);
altpriority_encoder25 : add_flt_stratix5_area_altpriority_encoder_ena
PORT MAP (
aclr => aclr,
clk_en => clk_en,
clock => clock,
data => data(31 DOWNTO 16),
q => wire_altpriority_encoder25_q
);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN pipeline_q_dffe <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN pipeline_q_dffe <= wire_trailing_zeros_cnt_w_lg_tmp_q_wire934w;
END IF;
END IF;
END PROCESS;
END RTL; --add_flt_stratix5_area_altpriority_encoder_dna
LIBRARY lpm;
USE lpm.all;
--synthesis_resources = lpm_add_sub 9 lpm_compare 1 reg 794
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_area_altfp_add_sub_rgj IS
PORT
(
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END add_flt_stratix5_area_altfp_add_sub_rgj;
ARCHITECTURE RTL OF add_flt_stratix5_area_altfp_add_sub_rgj IS
SIGNAL wire_lbarrel_shift_result : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_data : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_result : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_leading_zeroes_cnt_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL wire_leading_zeroes_cnt_q : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_trailing_zeros_cnt_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL wire_trailing_zeros_cnt_q : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe12 : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_dataa_exp_dffe13 : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_dataa_exp_dffe14 : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_dataa_exp_dffe15 : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_dataa_man_dffe12 : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_dataa_man_dffe13 : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_dataa_man_dffe14 : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_dataa_man_dffe15 : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_dataa_sign_dffe12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL aligned_dataa_sign_dffe13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL aligned_dataa_sign_dffe14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL aligned_dataa_sign_dffe15 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL aligned_datab_exp_dffe12 : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_datab_exp_dffe13 : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_datab_exp_dffe14 : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_datab_exp_dffe15 : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_datab_man_dffe12 : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_datab_man_dffe13 : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_datab_man_dffe14 : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_datab_man_dffe15 : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_datab_sign_dffe12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL aligned_datab_sign_dffe13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL aligned_datab_sign_dffe14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL aligned_datab_sign_dffe15 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL both_inputs_are_infinite_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL data_exp_dffe1 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL dataa_man_dffe1 : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL dataa_sign_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL datab_man_dffe1 : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL datab_sign_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL denormal_res_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL denormal_res_dffe32 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL denormal_res_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL denormal_res_dffe41 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL exp_adj_dffe21 : STD_LOGIC_VECTOR(1 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_adj_dffe23 : STD_LOGIC_VECTOR(1 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_amb_mux_dffe13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL exp_amb_mux_dffe14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL exp_amb_mux_dffe15 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL exp_intermediate_res_dffe41 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_out_dffe5 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe2 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe21 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe23 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe3 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe32 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe4 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe32 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe41 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_res_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_res_dffe32 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_res_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_res_dffe41 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe32 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe41 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_dataa_infinite_dffe12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_dataa_infinite_dffe13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_dataa_infinite_dffe14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_dataa_infinite_dffe15 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_dataa_nan_dffe12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_datab_infinite_dffe12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_datab_infinite_dffe13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_datab_infinite_dffe14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_datab_infinite_dffe15 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_datab_nan_dffe12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe32 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe41 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe15 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe32 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe41 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_add_sub_res_mag_dffe21 : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_add_sub_res_mag_dffe23 : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_add_sub_res_sign_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_add_sub_res_sign_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_dffe31 : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_leading_zeros_dffe31 : STD_LOGIC_VECTOR(4 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_out_dffe5 : STD_LOGIC_VECTOR(22 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_res_dffe4 : STD_LOGIC_VECTOR(22 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_res_is_not_zero_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_res_is_not_zero_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_res_is_not_zero_dffe32 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_res_is_not_zero_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_res_is_not_zero_dffe41 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_res_not_zero_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_smaller_dffe13 : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL need_complement_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL round_bit_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL round_bit_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL round_bit_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL round_bit_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL round_bit_dffe32 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL rounded_res_infinity_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL rshift_distance_dffe13 : STD_LOGIC_VECTOR(4 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL rshift_distance_dffe14 : STD_LOGIC_VECTOR(4 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL rshift_distance_dffe15 : STD_LOGIC_VECTOR(4 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL sign_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_dffe32 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_out_dffe5 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_res_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_res_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_res_dffe41 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe32 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL zero_man_sign_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL zero_man_sign_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL zero_man_sign_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_add_sub1_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_add_sub2_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_add_sub3_result : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_add_sub4_result : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL wire_add_sub5_result : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL wire_add_sub6_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_add_sub7_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_add_sub8_result : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_add_sub9_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_trailing_zeros_limit_comparator_agb : STD_LOGIC;
SIGNAL wire_w248w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w267w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w375w385w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_force_zero_w601w602w603w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_force_zero_w601w602w612w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_denormal_result_w536w537w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w324w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w331w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w317w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_amb_mux_w276w279w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_amb_mux_w276w277w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_infinity_w596w606w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_infinity_w596w615w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_infinity_w596w621w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_nan_w597w609w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_nan_w597w618w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w243w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w234w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_dataa_infinite_dffe11_wo246w247w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w262w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w253w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_datab_infinite_dffe11_wo265w266w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_datab_infinite_dffe15_wo337w338w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_man_res_not_zero_dffe26_wo481w482w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w293w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_w375w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w361w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_w390w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_man_add_sub_w_range350w353w356w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL wire_w554w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_zero_w601w604w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_zero_w601w613w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_dffe15_wo330w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_dffe15_wo323w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_dffe15_wo314w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_w280w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_w274w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_force_infinity_w607w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_force_infinity_w616w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_force_nan_w610w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_force_nan_w619w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_need_complement_dffe22_wo354w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range17w23w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range27w33w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range37w43w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range47w53w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range57w63w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range67w73w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range77w83w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range20w25w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range30w35w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range40w45w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range50w55w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range60w65w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range70w75w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range80w85w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_a_all_one_w_range84w220w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_b_all_one_w_range86w226w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_diff_abs_exceed_max_w_range290w294w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range518w520w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range521w522w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range523w524w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range525w526w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range527w528w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range529w530w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range531w532w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range533w539w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range568w571w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range572w574w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range575w577w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range578w580w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range581w583w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range584w586w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range587w589w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range359w369w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range359w362w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range359w392w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_w_range350w357w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_rounding_add_sub_w_range552w556w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_zero_w601w602w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_add_sub_dffe25_wo469w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_add_sub_w2342w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_denormal_result_w536w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_dffe15_wo316w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_w276w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_force_infinity_w596w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_force_nan_w597w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_force_zero_w595w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_dataa_denormal_dffe11_wo233w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_dataa_infinite_dffe11_wo246w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_dataa_zero_dffe11_wo245w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_datab_denormal_dffe11_wo252w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_datab_infinite_dffe11_wo265w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_datab_infinite_dffe15_wo337w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_datab_zero_dffe11_wo264w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_man_res_is_not_zero_dffe4_wo594w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_man_res_not_zero_dffe26_wo481w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_need_complement_dffe22_wo351w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_sticky_bit_dffe1_wo343w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_adjustment2_add_sub_w_range489w538w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_diff_abs_exceed_max_w_range290w292w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_a_not_zero_w_range215w219w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range365w368w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range359w360w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_w_range350w353w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_b_not_zero_w_range218w225w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_rounding_add_sub_w_range552w553w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_force_zero_w601w604w605w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_force_zero_w601w613w614w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_infinity_w607w608w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_infinity_w616w617w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_force_zero_w601w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_sticky_bit_dffe27_wo380w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range141w142w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range147w148w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range153w154w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range159w160w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range165w166w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range171w172w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range177w178w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range183w184w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range189w190w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range195w196w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range87w88w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range201w202w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range207w208w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range213w214w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range17w18w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range27w28w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range37w38w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range47w48w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range57w58w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range67w68w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range93w94w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range77w78w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range99w100w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range105w106w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range111w112w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range117w118w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range123w124w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range129w130w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range135w136w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range144w145w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range150w151w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range156w157w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range162w163w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range168w169w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range174w175w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range180w181w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range186w187w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range192w193w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range198w199w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range90w91w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range204w205w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range210w211w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range216w217w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range20w21w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range30w31w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range40w41w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range50w51w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range60w61w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range70w71w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range96w97w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range80w81w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range102w103w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range108w109w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range114w115w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range120w121w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range126w127w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range132w133w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range138w139w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_diff_abs_exceed_max_w_range283w286w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_diff_abs_exceed_max_w_range287w289w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range494w497w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range498w500w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range501w503w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range504w506w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range507w509w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range510w512w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range513w515w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range516w517w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range395w398w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range426w428w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range429w431w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range432w434w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range435w437w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range438w440w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range441w443w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range444w446w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range447w449w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range450w452w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range453w455w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range399w401w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range456w458w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range459w461w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range462w464w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range465w467w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range402w404w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range405w407w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range408w410w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range411w413w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range414w416w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range417w419w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range420w422w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range423w425w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL aclr : STD_LOGIC;
SIGNAL add_sub_dffe25_wi : STD_LOGIC;
SIGNAL add_sub_dffe25_wo : STD_LOGIC;
SIGNAL add_sub_w2 : STD_LOGIC;
SIGNAL aligned_dataa_exp_dffe12_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe12_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe13_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe13_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe14_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe14_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe15_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe15_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe12_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe12_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe13_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe13_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe14_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe14_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe15_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe15_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe15_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL aligned_dataa_sign_dffe12_wi : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe12_wo : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe13_wi : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe13_wo : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe14_wi : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe14_wo : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe15_wi : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe15_wo : STD_LOGIC;
SIGNAL aligned_dataa_sign_w : STD_LOGIC;
SIGNAL aligned_datab_exp_dffe12_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe12_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe13_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe13_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe14_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe14_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe15_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe15_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_man_dffe12_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe12_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe13_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe13_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe14_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe14_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe15_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL aligned_datab_man_dffe15_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe15_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL aligned_datab_sign_dffe12_wi : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe12_wo : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe13_wi : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe13_wo : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe14_wi : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe14_wo : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe15_wi : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe15_wo : STD_LOGIC;
SIGNAL aligned_datab_sign_w : STD_LOGIC;
SIGNAL borrow_w : STD_LOGIC;
SIGNAL both_inputs_are_infinite_dffe1_wi : STD_LOGIC;
SIGNAL both_inputs_are_infinite_dffe1_wo : STD_LOGIC;
SIGNAL both_inputs_are_infinite_dffe25_wi : STD_LOGIC;
SIGNAL both_inputs_are_infinite_dffe25_wo : STD_LOGIC;
SIGNAL data_exp_dffe1_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL data_exp_dffe1_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL dataa_dffe11_wi : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL dataa_dffe11_wo : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL dataa_man_dffe1_wi : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL dataa_man_dffe1_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL dataa_sign_dffe1_wi : STD_LOGIC;
SIGNAL dataa_sign_dffe1_wo : STD_LOGIC;
SIGNAL dataa_sign_dffe25_wi : STD_LOGIC;
SIGNAL dataa_sign_dffe25_wo : STD_LOGIC;
SIGNAL datab_dffe11_wi : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL datab_dffe11_wo : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL datab_man_dffe1_wi : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL datab_man_dffe1_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL datab_sign_dffe1_wi : STD_LOGIC;
SIGNAL datab_sign_dffe1_wo : STD_LOGIC;
SIGNAL denormal_flag_w : STD_LOGIC;
SIGNAL denormal_res_dffe32_wi : STD_LOGIC;
SIGNAL denormal_res_dffe32_wo : STD_LOGIC;
SIGNAL denormal_res_dffe33_wi : STD_LOGIC;
SIGNAL denormal_res_dffe33_wo : STD_LOGIC;
SIGNAL denormal_res_dffe3_wi : STD_LOGIC;
SIGNAL denormal_res_dffe3_wo : STD_LOGIC;
SIGNAL denormal_res_dffe41_wi : STD_LOGIC;
SIGNAL denormal_res_dffe41_wo : STD_LOGIC;
SIGNAL denormal_res_dffe42_wi : STD_LOGIC;
SIGNAL denormal_res_dffe42_wo : STD_LOGIC;
SIGNAL denormal_res_dffe4_wi : STD_LOGIC;
SIGNAL denormal_res_dffe4_wo : STD_LOGIC;
SIGNAL denormal_result_w : STD_LOGIC;
SIGNAL exp_a_all_one_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_a_not_zero_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_adj_0pads : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL exp_adj_dffe21_wi : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adj_dffe21_wo : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adj_dffe23_wi : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adj_dffe23_wo : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adj_dffe26_wi : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adj_dffe26_wo : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adjust_by_add1 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adjust_by_add2 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adjustment2_add_sub_dataa_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adjustment2_add_sub_datab_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adjustment2_add_sub_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adjustment_add_sub_dataa_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adjustment_add_sub_datab_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adjustment_add_sub_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_all_ones_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_all_zeros_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_amb_mux_dffe13_wi : STD_LOGIC;
SIGNAL exp_amb_mux_dffe13_wo : STD_LOGIC;
SIGNAL exp_amb_mux_dffe14_wi : STD_LOGIC;
SIGNAL exp_amb_mux_dffe14_wo : STD_LOGIC;
SIGNAL exp_amb_mux_dffe15_wi : STD_LOGIC;
SIGNAL exp_amb_mux_dffe15_wo : STD_LOGIC;
SIGNAL exp_amb_mux_w : STD_LOGIC;
SIGNAL exp_amb_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_b_all_one_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_b_not_zero_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_bma_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_diff_abs_exceed_max_w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL exp_diff_abs_max_w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL exp_diff_abs_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_intermediate_res_dffe41_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_intermediate_res_dffe41_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_intermediate_res_dffe42_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_intermediate_res_dffe42_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_intermediate_res_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_out_dffe5_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_out_dffe5_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe21_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe21_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe22_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe22_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe23_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe23_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe25_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe25_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe26_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe26_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe27_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe27_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe2_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe2_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe32_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe32_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe33_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe33_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe3_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe3_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe4_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe4_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_max_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_not_zero_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_res_rounding_adder_dataa_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_res_rounding_adder_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_rounded_res_infinity_w : STD_LOGIC;
SIGNAL exp_rounded_res_max_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_rounded_res_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_rounding_adjustment_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_value : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL force_infinity_w : STD_LOGIC;
SIGNAL force_nan_w : STD_LOGIC;
SIGNAL force_zero_w : STD_LOGIC;
SIGNAL guard_bit_dffe3_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe1_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe1_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe21_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe21_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe22_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe22_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe23_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe23_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe25_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe25_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe26_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe26_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe27_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe27_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe2_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe2_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe31_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe31_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe32_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe32_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe33_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe33_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe3_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe3_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe41_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe41_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe42_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe42_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe4_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe4_wo : STD_LOGIC;
SIGNAL infinite_res_dff32_wi : STD_LOGIC;
SIGNAL infinite_res_dff32_wo : STD_LOGIC;
SIGNAL infinite_res_dff33_wi : STD_LOGIC;
SIGNAL infinite_res_dff33_wo : STD_LOGIC;
SIGNAL infinite_res_dffe3_wi : STD_LOGIC;
SIGNAL infinite_res_dffe3_wo : STD_LOGIC;
SIGNAL infinite_res_dffe41_wi : STD_LOGIC;
SIGNAL infinite_res_dffe41_wo : STD_LOGIC;
SIGNAL infinite_res_dffe42_wi : STD_LOGIC;
SIGNAL infinite_res_dffe42_wo : STD_LOGIC;
SIGNAL infinite_res_dffe4_wi : STD_LOGIC;
SIGNAL infinite_res_dffe4_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe21_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe21_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe22_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe22_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe23_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe23_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe26_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe26_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe27_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe27_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe2_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe2_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe31_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe31_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe32_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe32_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe33_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe33_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe3_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe3_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe41_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe41_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe42_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe42_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe4_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe4_wo : STD_LOGIC;
SIGNAL input_dataa_denormal_dffe11_wi : STD_LOGIC;
SIGNAL input_dataa_denormal_dffe11_wo : STD_LOGIC;
SIGNAL input_dataa_denormal_w : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe11_wi : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe11_wo : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe12_wi : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe12_wo : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe13_wi : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe13_wo : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe14_wi : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe14_wo : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe15_wi : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe15_wo : STD_LOGIC;
SIGNAL input_dataa_infinite_w : STD_LOGIC;
SIGNAL input_dataa_nan_dffe11_wi : STD_LOGIC;
SIGNAL input_dataa_nan_dffe11_wo : STD_LOGIC;
SIGNAL input_dataa_nan_dffe12_wi : STD_LOGIC;
SIGNAL input_dataa_nan_dffe12_wo : STD_LOGIC;
SIGNAL input_dataa_nan_w : STD_LOGIC;
SIGNAL input_dataa_zero_dffe11_wi : STD_LOGIC;
SIGNAL input_dataa_zero_dffe11_wo : STD_LOGIC;
SIGNAL input_dataa_zero_w : STD_LOGIC;
SIGNAL input_datab_denormal_dffe11_wi : STD_LOGIC;
SIGNAL input_datab_denormal_dffe11_wo : STD_LOGIC;
SIGNAL input_datab_denormal_w : STD_LOGIC;
SIGNAL input_datab_infinite_dffe11_wi : STD_LOGIC;
SIGNAL input_datab_infinite_dffe11_wo : STD_LOGIC;
SIGNAL input_datab_infinite_dffe12_wi : STD_LOGIC;
SIGNAL input_datab_infinite_dffe12_wo : STD_LOGIC;
SIGNAL input_datab_infinite_dffe13_wi : STD_LOGIC;
SIGNAL input_datab_infinite_dffe13_wo : STD_LOGIC;
SIGNAL input_datab_infinite_dffe14_wi : STD_LOGIC;
SIGNAL input_datab_infinite_dffe14_wo : STD_LOGIC;
SIGNAL input_datab_infinite_dffe15_wi : STD_LOGIC;
SIGNAL input_datab_infinite_dffe15_wo : STD_LOGIC;
SIGNAL input_datab_infinite_w : STD_LOGIC;
SIGNAL input_datab_nan_dffe11_wi : STD_LOGIC;
SIGNAL input_datab_nan_dffe11_wo : STD_LOGIC;
SIGNAL input_datab_nan_dffe12_wi : STD_LOGIC;
SIGNAL input_datab_nan_dffe12_wo : STD_LOGIC;
SIGNAL input_datab_nan_w : STD_LOGIC;
SIGNAL input_datab_zero_dffe11_wi : STD_LOGIC;
SIGNAL input_datab_zero_dffe11_wo : STD_LOGIC;
SIGNAL input_datab_zero_w : STD_LOGIC;
SIGNAL input_is_infinite_dffe1_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe1_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe21_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe21_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe22_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe22_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe23_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe23_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe25_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe25_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe26_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe26_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe27_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe27_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe2_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe2_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe31_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe31_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe32_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe32_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe33_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe33_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe3_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe3_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe41_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe41_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe42_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe42_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe4_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe4_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe13_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe13_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe14_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe14_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe15_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe15_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe1_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe1_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe21_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe21_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe22_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe22_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe23_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe23_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe25_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe25_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe26_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe26_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe27_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe27_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe2_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe2_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe31_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe31_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe32_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe32_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe33_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe33_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe3_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe3_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe41_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe41_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe42_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe42_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe4_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe4_wo : STD_LOGIC;
SIGNAL man_2comp_res_dataa_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_2comp_res_datab_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_2comp_res_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_a_not_zero_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_add_sub_dataa_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_add_sub_datab_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe21_wi : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe21_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe23_wi : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe23_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe26_wi : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe26_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe27_wi : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe27_wo : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_add_sub_res_mag_w2 : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_add_sub_res_sign_dffe21_wo : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe23_wi : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe23_wo : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe26_wi : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe26_wo : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe27_wi : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe27_wo : STD_LOGIC;
SIGNAL man_add_sub_res_sign_w2 : STD_LOGIC;
SIGNAL man_add_sub_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_all_zeros_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_b_not_zero_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_dffe31_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_intermediate_res_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_leading_zeros_cnt_w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL man_leading_zeros_dffe31_wi : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL man_leading_zeros_dffe31_wo : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL man_nan_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_out_dffe5_wi : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_out_dffe5_wo : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_res_dffe4_wi : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_res_dffe4_wo : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_res_is_not_zero_dffe31_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe31_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe32_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe32_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe33_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe33_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe3_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe3_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe41_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe41_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe42_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe42_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe4_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe4_wo : STD_LOGIC;
SIGNAL man_res_mag_w2 : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_res_not_zero_dffe23_wi : STD_LOGIC;
SIGNAL man_res_not_zero_dffe23_wo : STD_LOGIC;
SIGNAL man_res_not_zero_dffe26_wi : STD_LOGIC;
SIGNAL man_res_not_zero_dffe26_wo : STD_LOGIC;
SIGNAL man_res_not_zero_w2 : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL man_res_rounding_add_sub_datab_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_res_rounding_add_sub_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_res_w3 : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL man_rounded_res_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_rounding_add_value_w : STD_LOGIC;
SIGNAL man_smaller_dffe13_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL man_smaller_dffe13_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL man_smaller_w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL need_complement_dffe22_wi : STD_LOGIC;
SIGNAL need_complement_dffe22_wo : STD_LOGIC;
SIGNAL need_complement_dffe2_wi : STD_LOGIC;
SIGNAL need_complement_dffe2_wo : STD_LOGIC;
SIGNAL pos_sign_bit_ext : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL priority_encoder_1pads_w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL round_bit_dffe21_wi : STD_LOGIC;
SIGNAL round_bit_dffe21_wo : STD_LOGIC;
SIGNAL round_bit_dffe23_wi : STD_LOGIC;
SIGNAL round_bit_dffe23_wo : STD_LOGIC;
SIGNAL round_bit_dffe26_wi : STD_LOGIC;
SIGNAL round_bit_dffe26_wo : STD_LOGIC;
SIGNAL round_bit_dffe31_wi : STD_LOGIC;
SIGNAL round_bit_dffe31_wo : STD_LOGIC;
SIGNAL round_bit_dffe32_wi : STD_LOGIC;
SIGNAL round_bit_dffe32_wo : STD_LOGIC;
SIGNAL round_bit_dffe33_wi : STD_LOGIC;
SIGNAL round_bit_dffe33_wo : STD_LOGIC;
SIGNAL round_bit_dffe3_wi : STD_LOGIC;
SIGNAL round_bit_dffe3_wo : STD_LOGIC;
SIGNAL round_bit_w : STD_LOGIC;
SIGNAL rounded_res_infinity_dffe4_wi : STD_LOGIC;
SIGNAL rounded_res_infinity_dffe4_wo : STD_LOGIC;
SIGNAL rshift_distance_dffe13_wi : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_dffe13_wo : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_dffe14_wi : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_dffe14_wo : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_dffe15_wi : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_dffe15_wo : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sign_dffe31_wi : STD_LOGIC;
SIGNAL sign_dffe31_wo : STD_LOGIC;
SIGNAL sign_dffe32_wi : STD_LOGIC;
SIGNAL sign_dffe32_wo : STD_LOGIC;
SIGNAL sign_dffe33_wi : STD_LOGIC;
SIGNAL sign_dffe33_wo : STD_LOGIC;
SIGNAL sign_out_dffe5_wi : STD_LOGIC;
SIGNAL sign_out_dffe5_wo : STD_LOGIC;
SIGNAL sign_res_dffe3_wi : STD_LOGIC;
SIGNAL sign_res_dffe3_wo : STD_LOGIC;
SIGNAL sign_res_dffe41_wi : STD_LOGIC;
SIGNAL sign_res_dffe41_wo : STD_LOGIC;
SIGNAL sign_res_dffe42_wi : STD_LOGIC;
SIGNAL sign_res_dffe42_wo : STD_LOGIC;
SIGNAL sign_res_dffe4_wi : STD_LOGIC;
SIGNAL sign_res_dffe4_wo : STD_LOGIC;
SIGNAL sticky_bit_cnt_dataa_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sticky_bit_cnt_datab_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sticky_bit_cnt_res_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sticky_bit_dffe1_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe1_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe21_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe21_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe22_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe22_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe23_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe23_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe25_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe25_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe26_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe26_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe27_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe27_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe2_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe2_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe31_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe31_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe32_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe32_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe33_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe33_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe3_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe3_wo : STD_LOGIC;
SIGNAL sticky_bit_w : STD_LOGIC;
SIGNAL trailing_zeros_limit_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL zero_man_sign_dffe21_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe21_wo : STD_LOGIC;
SIGNAL zero_man_sign_dffe22_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe22_wo : STD_LOGIC;
SIGNAL zero_man_sign_dffe23_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe23_wo : STD_LOGIC;
SIGNAL zero_man_sign_dffe26_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe26_wo : STD_LOGIC;
SIGNAL zero_man_sign_dffe27_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe27_wo : STD_LOGIC;
SIGNAL zero_man_sign_dffe2_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe2_wo : STD_LOGIC;
SIGNAL wire_w_aligned_dataa_exp_dffe15_wo_range315w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_aligned_datab_exp_dffe15_wo_range313w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_dataa_range141w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range147w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range153w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range159w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range165w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range171w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range177w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range183w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range189w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range195w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range87w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range201w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range207w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range213w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range17w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range27w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range37w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range47w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range57w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range67w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range93w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range77w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range99w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range105w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range111w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range117w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range123w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range129w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range135w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_dffe11_wo_range242w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_dataa_dffe11_wo_range232w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_datab_range144w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range150w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range156w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range162w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range168w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range174w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range180w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range186w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range192w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range198w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range90w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range204w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range210w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range216w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range20w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range30w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range40w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range50w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range60w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range70w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range96w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range80w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range102w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range108w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range114w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range120w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range126w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range132w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range138w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_dffe11_wo_range261w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_datab_dffe11_wo_range251w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range7w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range24w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range34w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range44w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range54w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range64w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range74w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range84w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range2w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range19w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range29w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range39w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range49w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range59w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range69w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range496w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range499w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range502w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range505w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range508w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range511w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range535w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range514w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range489w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_amb_w_range275w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range9w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range26w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range36w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range46w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range56w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range66w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range76w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range86w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range5w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range22w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range32w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range42w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range52w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range62w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range72w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_bma_w_range273w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_exceed_max_w_range283w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_exceed_max_w_range287w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_exceed_max_w_range290w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_w_range291w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_w_range285w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_w_range288w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range518w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range521w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range523w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range525w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range527w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range529w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range531w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range533w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range494w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range498w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range501w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range504w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range507w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range510w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range513w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range516w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range568w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range572w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range575w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range578w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range581w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range584w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range587w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range570w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range573w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range576w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range579w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range582w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range585w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range588w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range12w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range143w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range149w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range155w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range161w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range167w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range173w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range179w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range185w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range191w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range197w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range89w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range203w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range209w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range215w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range95w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range101w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range107w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range113w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range119w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range125w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range131w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range137w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range421w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range424w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range427w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range430w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range433w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range436w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range439w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range442w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range445w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range448w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range451w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range454w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range457w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range460w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range463w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range466w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range397w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range400w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range403w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range406w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range409w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range412w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range415w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range418w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe27_wo_range374w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe27_wo_range389w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe27_wo_range365w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe27_wo_range391w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe27_wo_range359w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_w_range350w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range15w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range146w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range152w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range158w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range164w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range170w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range176w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range182w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range188w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range194w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range200w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range92w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range206w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range212w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range218w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range98w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range104w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range110w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range116w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range122w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range128w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range134w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range140w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range395w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range426w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range429w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range432w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range435w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range438w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range441w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range444w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range447w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range450w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range453w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range399w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range456w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range459w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range462w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range465w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range402w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range405w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range408w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range411w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range414w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range417w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range420w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range423w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_rounding_add_sub_w_range551w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_man_res_rounding_add_sub_w_range555w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_man_res_rounding_add_sub_w_range552w : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT add_flt_stratix5_area_altbarrel_shift_oud
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
distance : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR(25 DOWNTO 0)
);
END COMPONENT;
COMPONENT add_flt_stratix5_area_altbarrel_shift_u1g
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
distance : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR(25 DOWNTO 0)
);
END COMPONENT;
COMPONENT add_flt_stratix5_area_altpriority_encoder_ou8
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT;
COMPONENT add_flt_stratix5_area_altpriority_encoder_dna
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT;
COMPONENT lpm_add_sub
GENERIC
(
LPM_DIRECTION : STRING := "DEFAULT";
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "SIGNED";
LPM_WIDTH : NATURAL;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_add_sub"
);
PORT
(
aclr : IN STD_LOGIC := '0';
add_sub : IN STD_LOGIC := '1';
cin : IN STD_LOGIC := 'Z';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
cout : OUT STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
overflow : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT lpm_compare
GENERIC
(
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "UNSIGNED";
LPM_WIDTH : NATURAL;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_compare"
);
PORT
(
aclr : IN STD_LOGIC := '0';
aeb : OUT STD_LOGIC;
agb : OUT STD_LOGIC;
ageb : OUT STD_LOGIC;
alb : OUT STD_LOGIC;
aleb : OUT STD_LOGIC;
aneb : OUT STD_LOGIC;
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
BEGIN
wire_w248w(0) <= wire_w_lg_w_lg_input_dataa_infinite_dffe11_wo246w247w(0) AND wire_w_lg_input_dataa_zero_dffe11_wo245w(0);
wire_w267w(0) <= wire_w_lg_w_lg_input_datab_infinite_dffe11_wo265w266w(0) AND wire_w_lg_input_datab_zero_dffe11_wo264w(0);
wire_w_lg_w375w385w(0) <= wire_w375w(0) AND sticky_bit_dffe27_wo;
loop83 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_w_lg_force_zero_w601w602w603w(i) <= wire_w_lg_w_lg_force_zero_w601w602w(0) AND exp_res_dffe4_wo(i);
END GENERATE loop83;
loop84 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_w_lg_force_zero_w601w602w612w(i) <= wire_w_lg_w_lg_force_zero_w601w602w(0) AND man_res_dffe4_wo(i);
END GENERATE loop84;
loop85 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_denormal_result_w536w537w(i) <= wire_w_lg_denormal_result_w536w(0) AND wire_w_exp_adjustment2_add_sub_w_range535w(i);
END GENERATE loop85;
loop86 : FOR i IN 0 TO 25 GENERATE
wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w324w(i) <= wire_w_lg_exp_amb_mux_dffe15_wo316w(0) AND aligned_dataa_man_dffe15_w(i);
END GENERATE loop86;
loop87 : FOR i IN 0 TO 25 GENERATE
wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w331w(i) <= wire_w_lg_exp_amb_mux_dffe15_wo316w(0) AND wire_rbarrel_shift_result(i);
END GENERATE loop87;
loop88 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w317w(i) <= wire_w_lg_exp_amb_mux_dffe15_wo316w(0) AND wire_w_aligned_dataa_exp_dffe15_wo_range315w(i);
END GENERATE loop88;
loop89 : FOR i IN 0 TO 23 GENERATE
wire_w_lg_w_lg_exp_amb_mux_w276w279w(i) <= wire_w_lg_exp_amb_mux_w276w(0) AND aligned_datab_man_dffe12_wo(i);
END GENERATE loop89;
loop90 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_exp_amb_mux_w276w277w(i) <= wire_w_lg_exp_amb_mux_w276w(0) AND wire_w_exp_amb_w_range275w(i);
END GENERATE loop90;
loop91 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_force_infinity_w596w606w(i) <= wire_w_lg_force_infinity_w596w(0) AND wire_w_lg_w_lg_w_lg_force_zero_w601w604w605w(i);
END GENERATE loop91;
loop92 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_force_infinity_w596w615w(i) <= wire_w_lg_force_infinity_w596w(0) AND wire_w_lg_w_lg_w_lg_force_zero_w601w613w614w(i);
END GENERATE loop92;
wire_w_lg_w_lg_force_infinity_w596w621w(0) <= wire_w_lg_force_infinity_w596w(0) AND sign_res_dffe4_wo;
loop93 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_force_nan_w597w609w(i) <= wire_w_lg_force_nan_w597w(0) AND wire_w_lg_w_lg_force_infinity_w607w608w(i);
END GENERATE loop93;
loop94 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_force_nan_w597w618w(i) <= wire_w_lg_force_nan_w597w(0) AND wire_w_lg_w_lg_force_infinity_w616w617w(i);
END GENERATE loop94;
loop95 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w243w(i) <= wire_w_lg_input_dataa_denormal_dffe11_wo233w(0) AND wire_w_dataa_dffe11_wo_range242w(i);
END GENERATE loop95;
loop96 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w234w(i) <= wire_w_lg_input_dataa_denormal_dffe11_wo233w(0) AND wire_w_dataa_dffe11_wo_range232w(i);
END GENERATE loop96;
wire_w_lg_w_lg_input_dataa_infinite_dffe11_wo246w247w(0) <= wire_w_lg_input_dataa_infinite_dffe11_wo246w(0) AND wire_w_lg_input_dataa_denormal_dffe11_wo233w(0);
loop97 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w262w(i) <= wire_w_lg_input_datab_denormal_dffe11_wo252w(0) AND wire_w_datab_dffe11_wo_range261w(i);
END GENERATE loop97;
loop98 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w253w(i) <= wire_w_lg_input_datab_denormal_dffe11_wo252w(0) AND wire_w_datab_dffe11_wo_range251w(i);
END GENERATE loop98;
wire_w_lg_w_lg_input_datab_infinite_dffe11_wo265w266w(0) <= wire_w_lg_input_datab_infinite_dffe11_wo265w(0) AND wire_w_lg_input_datab_denormal_dffe11_wo252w(0);
wire_w_lg_w_lg_input_datab_infinite_dffe15_wo337w338w(0) <= wire_w_lg_input_datab_infinite_dffe15_wo337w(0) AND aligned_dataa_sign_dffe15_wo;
wire_w_lg_w_lg_man_res_not_zero_dffe26_wo481w482w(0) <= wire_w_lg_man_res_not_zero_dffe26_wo481w(0) AND zero_man_sign_dffe26_wo;
loop99 : FOR i IN 0 TO 4 GENERATE
wire_w293w(i) <= wire_w_lg_w_exp_diff_abs_exceed_max_w_range290w292w(0) AND wire_w_exp_diff_abs_w_range291w(i);
END GENERATE loop99;
wire_w375w(0) <= wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range359w360w(0) AND wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range365w368w(0);
loop100 : FOR i IN 0 TO 1 GENERATE
wire_w361w(i) <= wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range359w360w(0) AND exp_adjust_by_add1(i);
END GENERATE loop100;
loop101 : FOR i IN 0 TO 25 GENERATE
wire_w390w(i) <= wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range359w360w(0) AND wire_w_man_add_sub_res_mag_dffe27_wo_range389w(i);
END GENERATE loop101;
loop102 : FOR i IN 0 TO 27 GENERATE
wire_w_lg_w_lg_w_man_add_sub_w_range350w353w356w(i) <= wire_w_lg_w_man_add_sub_w_range350w353w(0) AND man_add_sub_w(i);
END GENERATE loop102;
loop103 : FOR i IN 0 TO 22 GENERATE
wire_w554w(i) <= wire_w_lg_w_man_res_rounding_add_sub_w_range552w553w(0) AND wire_w_man_res_rounding_add_sub_w_range551w(i);
END GENERATE loop103;
loop104 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_force_zero_w601w604w(i) <= wire_w_lg_force_zero_w601w(0) AND exp_all_zeros_w(i);
END GENERATE loop104;
loop105 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_force_zero_w601w613w(i) <= wire_w_lg_force_zero_w601w(0) AND man_all_zeros_w(i);
END GENERATE loop105;
loop106 : FOR i IN 0 TO 25 GENERATE
wire_w_lg_exp_amb_mux_dffe15_wo330w(i) <= exp_amb_mux_dffe15_wo AND aligned_datab_man_dffe15_w(i);
END GENERATE loop106;
loop107 : FOR i IN 0 TO 25 GENERATE
wire_w_lg_exp_amb_mux_dffe15_wo323w(i) <= exp_amb_mux_dffe15_wo AND wire_rbarrel_shift_result(i);
END GENERATE loop107;
loop108 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_exp_amb_mux_dffe15_wo314w(i) <= exp_amb_mux_dffe15_wo AND wire_w_aligned_datab_exp_dffe15_wo_range313w(i);
END GENERATE loop108;
loop109 : FOR i IN 0 TO 23 GENERATE
wire_w_lg_exp_amb_mux_w280w(i) <= exp_amb_mux_w AND aligned_dataa_man_dffe12_wo(i);
END GENERATE loop109;
loop110 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_exp_amb_mux_w274w(i) <= exp_amb_mux_w AND wire_w_exp_bma_w_range273w(i);
END GENERATE loop110;
loop111 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_force_infinity_w607w(i) <= force_infinity_w AND exp_all_ones_w(i);
END GENERATE loop111;
loop112 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_force_infinity_w616w(i) <= force_infinity_w AND man_all_zeros_w(i);
END GENERATE loop112;
loop113 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_force_nan_w610w(i) <= force_nan_w AND exp_all_ones_w(i);
END GENERATE loop113;
loop114 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_force_nan_w619w(i) <= force_nan_w AND man_nan_w(i);
END GENERATE loop114;
wire_w_lg_need_complement_dffe22_wo354w(0) <= need_complement_dffe22_wo AND wire_w_lg_w_man_add_sub_w_range350w353w(0);
wire_w_lg_w_dataa_range17w23w(0) <= wire_w_dataa_range17w(0) AND wire_w_exp_a_all_one_w_range7w(0);
wire_w_lg_w_dataa_range27w33w(0) <= wire_w_dataa_range27w(0) AND wire_w_exp_a_all_one_w_range24w(0);
wire_w_lg_w_dataa_range37w43w(0) <= wire_w_dataa_range37w(0) AND wire_w_exp_a_all_one_w_range34w(0);
wire_w_lg_w_dataa_range47w53w(0) <= wire_w_dataa_range47w(0) AND wire_w_exp_a_all_one_w_range44w(0);
wire_w_lg_w_dataa_range57w63w(0) <= wire_w_dataa_range57w(0) AND wire_w_exp_a_all_one_w_range54w(0);
wire_w_lg_w_dataa_range67w73w(0) <= wire_w_dataa_range67w(0) AND wire_w_exp_a_all_one_w_range64w(0);
wire_w_lg_w_dataa_range77w83w(0) <= wire_w_dataa_range77w(0) AND wire_w_exp_a_all_one_w_range74w(0);
wire_w_lg_w_datab_range20w25w(0) <= wire_w_datab_range20w(0) AND wire_w_exp_b_all_one_w_range9w(0);
wire_w_lg_w_datab_range30w35w(0) <= wire_w_datab_range30w(0) AND wire_w_exp_b_all_one_w_range26w(0);
wire_w_lg_w_datab_range40w45w(0) <= wire_w_datab_range40w(0) AND wire_w_exp_b_all_one_w_range36w(0);
wire_w_lg_w_datab_range50w55w(0) <= wire_w_datab_range50w(0) AND wire_w_exp_b_all_one_w_range46w(0);
wire_w_lg_w_datab_range60w65w(0) <= wire_w_datab_range60w(0) AND wire_w_exp_b_all_one_w_range56w(0);
wire_w_lg_w_datab_range70w75w(0) <= wire_w_datab_range70w(0) AND wire_w_exp_b_all_one_w_range66w(0);
wire_w_lg_w_datab_range80w85w(0) <= wire_w_datab_range80w(0) AND wire_w_exp_b_all_one_w_range76w(0);
wire_w_lg_w_exp_a_all_one_w_range84w220w(0) <= wire_w_exp_a_all_one_w_range84w(0) AND wire_w_lg_w_man_a_not_zero_w_range215w219w(0);
wire_w_lg_w_exp_b_all_one_w_range86w226w(0) <= wire_w_exp_b_all_one_w_range86w(0) AND wire_w_lg_w_man_b_not_zero_w_range218w225w(0);
loop115 : FOR i IN 0 TO 4 GENERATE
wire_w_lg_w_exp_diff_abs_exceed_max_w_range290w294w(i) <= wire_w_exp_diff_abs_exceed_max_w_range290w(0) AND exp_diff_abs_max_w(i);
END GENERATE loop115;
wire_w_lg_w_exp_res_max_w_range518w520w(0) <= wire_w_exp_res_max_w_range518w(0) AND wire_w_exp_adjustment2_add_sub_w_range496w(0);
wire_w_lg_w_exp_res_max_w_range521w522w(0) <= wire_w_exp_res_max_w_range521w(0) AND wire_w_exp_adjustment2_add_sub_w_range499w(0);
wire_w_lg_w_exp_res_max_w_range523w524w(0) <= wire_w_exp_res_max_w_range523w(0) AND wire_w_exp_adjustment2_add_sub_w_range502w(0);
wire_w_lg_w_exp_res_max_w_range525w526w(0) <= wire_w_exp_res_max_w_range525w(0) AND wire_w_exp_adjustment2_add_sub_w_range505w(0);
wire_w_lg_w_exp_res_max_w_range527w528w(0) <= wire_w_exp_res_max_w_range527w(0) AND wire_w_exp_adjustment2_add_sub_w_range508w(0);
wire_w_lg_w_exp_res_max_w_range529w530w(0) <= wire_w_exp_res_max_w_range529w(0) AND wire_w_exp_adjustment2_add_sub_w_range511w(0);
wire_w_lg_w_exp_res_max_w_range531w532w(0) <= wire_w_exp_res_max_w_range531w(0) AND wire_w_exp_adjustment2_add_sub_w_range514w(0);
wire_w_lg_w_exp_res_max_w_range533w539w(0) <= wire_w_exp_res_max_w_range533w(0) AND wire_w_lg_w_exp_adjustment2_add_sub_w_range489w538w(0);
wire_w_lg_w_exp_rounded_res_max_w_range568w571w(0) <= wire_w_exp_rounded_res_max_w_range568w(0) AND wire_w_exp_rounded_res_w_range570w(0);
wire_w_lg_w_exp_rounded_res_max_w_range572w574w(0) <= wire_w_exp_rounded_res_max_w_range572w(0) AND wire_w_exp_rounded_res_w_range573w(0);
wire_w_lg_w_exp_rounded_res_max_w_range575w577w(0) <= wire_w_exp_rounded_res_max_w_range575w(0) AND wire_w_exp_rounded_res_w_range576w(0);
wire_w_lg_w_exp_rounded_res_max_w_range578w580w(0) <= wire_w_exp_rounded_res_max_w_range578w(0) AND wire_w_exp_rounded_res_w_range579w(0);
wire_w_lg_w_exp_rounded_res_max_w_range581w583w(0) <= wire_w_exp_rounded_res_max_w_range581w(0) AND wire_w_exp_rounded_res_w_range582w(0);
wire_w_lg_w_exp_rounded_res_max_w_range584w586w(0) <= wire_w_exp_rounded_res_max_w_range584w(0) AND wire_w_exp_rounded_res_w_range585w(0);
wire_w_lg_w_exp_rounded_res_max_w_range587w589w(0) <= wire_w_exp_rounded_res_max_w_range587w(0) AND wire_w_exp_rounded_res_w_range588w(0);
wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range359w369w(0) <= wire_w_man_add_sub_res_mag_dffe27_wo_range359w(0) AND wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range365w368w(0);
loop116 : FOR i IN 0 TO 1 GENERATE
wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range359w362w(i) <= wire_w_man_add_sub_res_mag_dffe27_wo_range359w(0) AND exp_adjust_by_add2(i);
END GENERATE loop116;
loop117 : FOR i IN 0 TO 25 GENERATE
wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range359w392w(i) <= wire_w_man_add_sub_res_mag_dffe27_wo_range359w(0) AND wire_w_man_add_sub_res_mag_dffe27_wo_range391w(i);
END GENERATE loop117;
loop118 : FOR i IN 0 TO 27 GENERATE
wire_w_lg_w_man_add_sub_w_range350w357w(i) <= wire_w_man_add_sub_w_range350w(0) AND man_2comp_res_w(i);
END GENERATE loop118;
loop119 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_man_res_rounding_add_sub_w_range552w556w(i) <= wire_w_man_res_rounding_add_sub_w_range552w(0) AND wire_w_man_res_rounding_add_sub_w_range555w(i);
END GENERATE loop119;
wire_w_lg_w_lg_force_zero_w601w602w(0) <= NOT wire_w_lg_force_zero_w601w(0);
wire_w_lg_add_sub_dffe25_wo469w(0) <= NOT add_sub_dffe25_wo;
wire_w_lg_add_sub_w2342w(0) <= NOT add_sub_w2;
wire_w_lg_denormal_result_w536w(0) <= NOT denormal_result_w;
wire_w_lg_exp_amb_mux_dffe15_wo316w(0) <= NOT exp_amb_mux_dffe15_wo;
wire_w_lg_exp_amb_mux_w276w(0) <= NOT exp_amb_mux_w;
wire_w_lg_force_infinity_w596w(0) <= NOT force_infinity_w;
wire_w_lg_force_nan_w597w(0) <= NOT force_nan_w;
wire_w_lg_force_zero_w595w(0) <= NOT force_zero_w;
wire_w_lg_input_dataa_denormal_dffe11_wo233w(0) <= NOT input_dataa_denormal_dffe11_wo;
wire_w_lg_input_dataa_infinite_dffe11_wo246w(0) <= NOT input_dataa_infinite_dffe11_wo;
wire_w_lg_input_dataa_zero_dffe11_wo245w(0) <= NOT input_dataa_zero_dffe11_wo;
wire_w_lg_input_datab_denormal_dffe11_wo252w(0) <= NOT input_datab_denormal_dffe11_wo;
wire_w_lg_input_datab_infinite_dffe11_wo265w(0) <= NOT input_datab_infinite_dffe11_wo;
wire_w_lg_input_datab_infinite_dffe15_wo337w(0) <= NOT input_datab_infinite_dffe15_wo;
wire_w_lg_input_datab_zero_dffe11_wo264w(0) <= NOT input_datab_zero_dffe11_wo;
wire_w_lg_man_res_is_not_zero_dffe4_wo594w(0) <= NOT man_res_is_not_zero_dffe4_wo;
wire_w_lg_man_res_not_zero_dffe26_wo481w(0) <= NOT man_res_not_zero_dffe26_wo;
wire_w_lg_need_complement_dffe22_wo351w(0) <= NOT need_complement_dffe22_wo;
wire_w_lg_sticky_bit_dffe1_wo343w(0) <= NOT sticky_bit_dffe1_wo;
wire_w_lg_w_exp_adjustment2_add_sub_w_range489w538w(0) <= NOT wire_w_exp_adjustment2_add_sub_w_range489w(0);
wire_w_lg_w_exp_diff_abs_exceed_max_w_range290w292w(0) <= NOT wire_w_exp_diff_abs_exceed_max_w_range290w(0);
wire_w_lg_w_man_a_not_zero_w_range215w219w(0) <= NOT wire_w_man_a_not_zero_w_range215w(0);
wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range365w368w(0) <= NOT wire_w_man_add_sub_res_mag_dffe27_wo_range365w(0);
wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range359w360w(0) <= NOT wire_w_man_add_sub_res_mag_dffe27_wo_range359w(0);
wire_w_lg_w_man_add_sub_w_range350w353w(0) <= NOT wire_w_man_add_sub_w_range350w(0);
wire_w_lg_w_man_b_not_zero_w_range218w225w(0) <= NOT wire_w_man_b_not_zero_w_range218w(0);
wire_w_lg_w_man_res_rounding_add_sub_w_range552w553w(0) <= NOT wire_w_man_res_rounding_add_sub_w_range552w(0);
loop120 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_w_lg_force_zero_w601w604w605w(i) <= wire_w_lg_w_lg_force_zero_w601w604w(i) OR wire_w_lg_w_lg_w_lg_force_zero_w601w602w603w(i);
END GENERATE loop120;
loop121 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_w_lg_force_zero_w601w613w614w(i) <= wire_w_lg_w_lg_force_zero_w601w613w(i) OR wire_w_lg_w_lg_w_lg_force_zero_w601w602w612w(i);
END GENERATE loop121;
loop122 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_force_infinity_w607w608w(i) <= wire_w_lg_force_infinity_w607w(i) OR wire_w_lg_w_lg_force_infinity_w596w606w(i);
END GENERATE loop122;
loop123 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_force_infinity_w616w617w(i) <= wire_w_lg_force_infinity_w616w(i) OR wire_w_lg_w_lg_force_infinity_w596w615w(i);
END GENERATE loop123;
wire_w_lg_force_zero_w601w(0) <= force_zero_w OR denormal_flag_w;
wire_w_lg_sticky_bit_dffe27_wo380w(0) <= sticky_bit_dffe27_wo OR wire_w_man_add_sub_res_mag_dffe27_wo_range374w(0);
wire_w_lg_w_dataa_range141w142w(0) <= wire_w_dataa_range141w(0) OR wire_w_man_a_not_zero_w_range137w(0);
wire_w_lg_w_dataa_range147w148w(0) <= wire_w_dataa_range147w(0) OR wire_w_man_a_not_zero_w_range143w(0);
wire_w_lg_w_dataa_range153w154w(0) <= wire_w_dataa_range153w(0) OR wire_w_man_a_not_zero_w_range149w(0);
wire_w_lg_w_dataa_range159w160w(0) <= wire_w_dataa_range159w(0) OR wire_w_man_a_not_zero_w_range155w(0);
wire_w_lg_w_dataa_range165w166w(0) <= wire_w_dataa_range165w(0) OR wire_w_man_a_not_zero_w_range161w(0);
wire_w_lg_w_dataa_range171w172w(0) <= wire_w_dataa_range171w(0) OR wire_w_man_a_not_zero_w_range167w(0);
wire_w_lg_w_dataa_range177w178w(0) <= wire_w_dataa_range177w(0) OR wire_w_man_a_not_zero_w_range173w(0);
wire_w_lg_w_dataa_range183w184w(0) <= wire_w_dataa_range183w(0) OR wire_w_man_a_not_zero_w_range179w(0);
wire_w_lg_w_dataa_range189w190w(0) <= wire_w_dataa_range189w(0) OR wire_w_man_a_not_zero_w_range185w(0);
wire_w_lg_w_dataa_range195w196w(0) <= wire_w_dataa_range195w(0) OR wire_w_man_a_not_zero_w_range191w(0);
wire_w_lg_w_dataa_range87w88w(0) <= wire_w_dataa_range87w(0) OR wire_w_man_a_not_zero_w_range12w(0);
wire_w_lg_w_dataa_range201w202w(0) <= wire_w_dataa_range201w(0) OR wire_w_man_a_not_zero_w_range197w(0);
wire_w_lg_w_dataa_range207w208w(0) <= wire_w_dataa_range207w(0) OR wire_w_man_a_not_zero_w_range203w(0);
wire_w_lg_w_dataa_range213w214w(0) <= wire_w_dataa_range213w(0) OR wire_w_man_a_not_zero_w_range209w(0);
wire_w_lg_w_dataa_range17w18w(0) <= wire_w_dataa_range17w(0) OR wire_w_exp_a_not_zero_w_range2w(0);
wire_w_lg_w_dataa_range27w28w(0) <= wire_w_dataa_range27w(0) OR wire_w_exp_a_not_zero_w_range19w(0);
wire_w_lg_w_dataa_range37w38w(0) <= wire_w_dataa_range37w(0) OR wire_w_exp_a_not_zero_w_range29w(0);
wire_w_lg_w_dataa_range47w48w(0) <= wire_w_dataa_range47w(0) OR wire_w_exp_a_not_zero_w_range39w(0);
wire_w_lg_w_dataa_range57w58w(0) <= wire_w_dataa_range57w(0) OR wire_w_exp_a_not_zero_w_range49w(0);
wire_w_lg_w_dataa_range67w68w(0) <= wire_w_dataa_range67w(0) OR wire_w_exp_a_not_zero_w_range59w(0);
wire_w_lg_w_dataa_range93w94w(0) <= wire_w_dataa_range93w(0) OR wire_w_man_a_not_zero_w_range89w(0);
wire_w_lg_w_dataa_range77w78w(0) <= wire_w_dataa_range77w(0) OR wire_w_exp_a_not_zero_w_range69w(0);
wire_w_lg_w_dataa_range99w100w(0) <= wire_w_dataa_range99w(0) OR wire_w_man_a_not_zero_w_range95w(0);
wire_w_lg_w_dataa_range105w106w(0) <= wire_w_dataa_range105w(0) OR wire_w_man_a_not_zero_w_range101w(0);
wire_w_lg_w_dataa_range111w112w(0) <= wire_w_dataa_range111w(0) OR wire_w_man_a_not_zero_w_range107w(0);
wire_w_lg_w_dataa_range117w118w(0) <= wire_w_dataa_range117w(0) OR wire_w_man_a_not_zero_w_range113w(0);
wire_w_lg_w_dataa_range123w124w(0) <= wire_w_dataa_range123w(0) OR wire_w_man_a_not_zero_w_range119w(0);
wire_w_lg_w_dataa_range129w130w(0) <= wire_w_dataa_range129w(0) OR wire_w_man_a_not_zero_w_range125w(0);
wire_w_lg_w_dataa_range135w136w(0) <= wire_w_dataa_range135w(0) OR wire_w_man_a_not_zero_w_range131w(0);
wire_w_lg_w_datab_range144w145w(0) <= wire_w_datab_range144w(0) OR wire_w_man_b_not_zero_w_range140w(0);
wire_w_lg_w_datab_range150w151w(0) <= wire_w_datab_range150w(0) OR wire_w_man_b_not_zero_w_range146w(0);
wire_w_lg_w_datab_range156w157w(0) <= wire_w_datab_range156w(0) OR wire_w_man_b_not_zero_w_range152w(0);
wire_w_lg_w_datab_range162w163w(0) <= wire_w_datab_range162w(0) OR wire_w_man_b_not_zero_w_range158w(0);
wire_w_lg_w_datab_range168w169w(0) <= wire_w_datab_range168w(0) OR wire_w_man_b_not_zero_w_range164w(0);
wire_w_lg_w_datab_range174w175w(0) <= wire_w_datab_range174w(0) OR wire_w_man_b_not_zero_w_range170w(0);
wire_w_lg_w_datab_range180w181w(0) <= wire_w_datab_range180w(0) OR wire_w_man_b_not_zero_w_range176w(0);
wire_w_lg_w_datab_range186w187w(0) <= wire_w_datab_range186w(0) OR wire_w_man_b_not_zero_w_range182w(0);
wire_w_lg_w_datab_range192w193w(0) <= wire_w_datab_range192w(0) OR wire_w_man_b_not_zero_w_range188w(0);
wire_w_lg_w_datab_range198w199w(0) <= wire_w_datab_range198w(0) OR wire_w_man_b_not_zero_w_range194w(0);
wire_w_lg_w_datab_range90w91w(0) <= wire_w_datab_range90w(0) OR wire_w_man_b_not_zero_w_range15w(0);
wire_w_lg_w_datab_range204w205w(0) <= wire_w_datab_range204w(0) OR wire_w_man_b_not_zero_w_range200w(0);
wire_w_lg_w_datab_range210w211w(0) <= wire_w_datab_range210w(0) OR wire_w_man_b_not_zero_w_range206w(0);
wire_w_lg_w_datab_range216w217w(0) <= wire_w_datab_range216w(0) OR wire_w_man_b_not_zero_w_range212w(0);
wire_w_lg_w_datab_range20w21w(0) <= wire_w_datab_range20w(0) OR wire_w_exp_b_not_zero_w_range5w(0);
wire_w_lg_w_datab_range30w31w(0) <= wire_w_datab_range30w(0) OR wire_w_exp_b_not_zero_w_range22w(0);
wire_w_lg_w_datab_range40w41w(0) <= wire_w_datab_range40w(0) OR wire_w_exp_b_not_zero_w_range32w(0);
wire_w_lg_w_datab_range50w51w(0) <= wire_w_datab_range50w(0) OR wire_w_exp_b_not_zero_w_range42w(0);
wire_w_lg_w_datab_range60w61w(0) <= wire_w_datab_range60w(0) OR wire_w_exp_b_not_zero_w_range52w(0);
wire_w_lg_w_datab_range70w71w(0) <= wire_w_datab_range70w(0) OR wire_w_exp_b_not_zero_w_range62w(0);
wire_w_lg_w_datab_range96w97w(0) <= wire_w_datab_range96w(0) OR wire_w_man_b_not_zero_w_range92w(0);
wire_w_lg_w_datab_range80w81w(0) <= wire_w_datab_range80w(0) OR wire_w_exp_b_not_zero_w_range72w(0);
wire_w_lg_w_datab_range102w103w(0) <= wire_w_datab_range102w(0) OR wire_w_man_b_not_zero_w_range98w(0);
wire_w_lg_w_datab_range108w109w(0) <= wire_w_datab_range108w(0) OR wire_w_man_b_not_zero_w_range104w(0);
wire_w_lg_w_datab_range114w115w(0) <= wire_w_datab_range114w(0) OR wire_w_man_b_not_zero_w_range110w(0);
wire_w_lg_w_datab_range120w121w(0) <= wire_w_datab_range120w(0) OR wire_w_man_b_not_zero_w_range116w(0);
wire_w_lg_w_datab_range126w127w(0) <= wire_w_datab_range126w(0) OR wire_w_man_b_not_zero_w_range122w(0);
wire_w_lg_w_datab_range132w133w(0) <= wire_w_datab_range132w(0) OR wire_w_man_b_not_zero_w_range128w(0);
wire_w_lg_w_datab_range138w139w(0) <= wire_w_datab_range138w(0) OR wire_w_man_b_not_zero_w_range134w(0);
wire_w_lg_w_exp_diff_abs_exceed_max_w_range283w286w(0) <= wire_w_exp_diff_abs_exceed_max_w_range283w(0) OR wire_w_exp_diff_abs_w_range285w(0);
wire_w_lg_w_exp_diff_abs_exceed_max_w_range287w289w(0) <= wire_w_exp_diff_abs_exceed_max_w_range287w(0) OR wire_w_exp_diff_abs_w_range288w(0);
wire_w_lg_w_exp_res_not_zero_w_range494w497w(0) <= wire_w_exp_res_not_zero_w_range494w(0) OR wire_w_exp_adjustment2_add_sub_w_range496w(0);
wire_w_lg_w_exp_res_not_zero_w_range498w500w(0) <= wire_w_exp_res_not_zero_w_range498w(0) OR wire_w_exp_adjustment2_add_sub_w_range499w(0);
wire_w_lg_w_exp_res_not_zero_w_range501w503w(0) <= wire_w_exp_res_not_zero_w_range501w(0) OR wire_w_exp_adjustment2_add_sub_w_range502w(0);
wire_w_lg_w_exp_res_not_zero_w_range504w506w(0) <= wire_w_exp_res_not_zero_w_range504w(0) OR wire_w_exp_adjustment2_add_sub_w_range505w(0);
wire_w_lg_w_exp_res_not_zero_w_range507w509w(0) <= wire_w_exp_res_not_zero_w_range507w(0) OR wire_w_exp_adjustment2_add_sub_w_range508w(0);
wire_w_lg_w_exp_res_not_zero_w_range510w512w(0) <= wire_w_exp_res_not_zero_w_range510w(0) OR wire_w_exp_adjustment2_add_sub_w_range511w(0);
wire_w_lg_w_exp_res_not_zero_w_range513w515w(0) <= wire_w_exp_res_not_zero_w_range513w(0) OR wire_w_exp_adjustment2_add_sub_w_range514w(0);
wire_w_lg_w_exp_res_not_zero_w_range516w517w(0) <= wire_w_exp_res_not_zero_w_range516w(0) OR wire_w_exp_adjustment2_add_sub_w_range489w(0);
wire_w_lg_w_man_res_not_zero_w2_range395w398w(0) <= wire_w_man_res_not_zero_w2_range395w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range397w(0);
wire_w_lg_w_man_res_not_zero_w2_range426w428w(0) <= wire_w_man_res_not_zero_w2_range426w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range427w(0);
wire_w_lg_w_man_res_not_zero_w2_range429w431w(0) <= wire_w_man_res_not_zero_w2_range429w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range430w(0);
wire_w_lg_w_man_res_not_zero_w2_range432w434w(0) <= wire_w_man_res_not_zero_w2_range432w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range433w(0);
wire_w_lg_w_man_res_not_zero_w2_range435w437w(0) <= wire_w_man_res_not_zero_w2_range435w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range436w(0);
wire_w_lg_w_man_res_not_zero_w2_range438w440w(0) <= wire_w_man_res_not_zero_w2_range438w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range439w(0);
wire_w_lg_w_man_res_not_zero_w2_range441w443w(0) <= wire_w_man_res_not_zero_w2_range441w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range442w(0);
wire_w_lg_w_man_res_not_zero_w2_range444w446w(0) <= wire_w_man_res_not_zero_w2_range444w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range445w(0);
wire_w_lg_w_man_res_not_zero_w2_range447w449w(0) <= wire_w_man_res_not_zero_w2_range447w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range448w(0);
wire_w_lg_w_man_res_not_zero_w2_range450w452w(0) <= wire_w_man_res_not_zero_w2_range450w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range451w(0);
wire_w_lg_w_man_res_not_zero_w2_range453w455w(0) <= wire_w_man_res_not_zero_w2_range453w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range454w(0);
wire_w_lg_w_man_res_not_zero_w2_range399w401w(0) <= wire_w_man_res_not_zero_w2_range399w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range400w(0);
wire_w_lg_w_man_res_not_zero_w2_range456w458w(0) <= wire_w_man_res_not_zero_w2_range456w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range457w(0);
wire_w_lg_w_man_res_not_zero_w2_range459w461w(0) <= wire_w_man_res_not_zero_w2_range459w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range460w(0);
wire_w_lg_w_man_res_not_zero_w2_range462w464w(0) <= wire_w_man_res_not_zero_w2_range462w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range463w(0);
wire_w_lg_w_man_res_not_zero_w2_range465w467w(0) <= wire_w_man_res_not_zero_w2_range465w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range466w(0);
wire_w_lg_w_man_res_not_zero_w2_range402w404w(0) <= wire_w_man_res_not_zero_w2_range402w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range403w(0);
wire_w_lg_w_man_res_not_zero_w2_range405w407w(0) <= wire_w_man_res_not_zero_w2_range405w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range406w(0);
wire_w_lg_w_man_res_not_zero_w2_range408w410w(0) <= wire_w_man_res_not_zero_w2_range408w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range409w(0);
wire_w_lg_w_man_res_not_zero_w2_range411w413w(0) <= wire_w_man_res_not_zero_w2_range411w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range412w(0);
wire_w_lg_w_man_res_not_zero_w2_range414w416w(0) <= wire_w_man_res_not_zero_w2_range414w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range415w(0);
wire_w_lg_w_man_res_not_zero_w2_range417w419w(0) <= wire_w_man_res_not_zero_w2_range417w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range418w(0);
wire_w_lg_w_man_res_not_zero_w2_range420w422w(0) <= wire_w_man_res_not_zero_w2_range420w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range421w(0);
wire_w_lg_w_man_res_not_zero_w2_range423w425w(0) <= wire_w_man_res_not_zero_w2_range423w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range424w(0);
aclr <= '0';
add_sub_dffe25_wi <= add_sub_w2;
add_sub_dffe25_wo <= add_sub_dffe25_wi;
add_sub_w2 <= (NOT (dataa_sign_dffe1_wo XOR datab_sign_dffe1_wo));
aligned_dataa_exp_dffe12_wi <= aligned_dataa_exp_w;
aligned_dataa_exp_dffe12_wo <= aligned_dataa_exp_dffe12;
aligned_dataa_exp_dffe13_wi <= aligned_dataa_exp_dffe12_wo;
aligned_dataa_exp_dffe13_wo <= aligned_dataa_exp_dffe13;
aligned_dataa_exp_dffe14_wi <= aligned_dataa_exp_dffe13_wo;
aligned_dataa_exp_dffe14_wo <= aligned_dataa_exp_dffe14;
aligned_dataa_exp_dffe15_wi <= aligned_dataa_exp_dffe14_wo;
aligned_dataa_exp_dffe15_wo <= aligned_dataa_exp_dffe15;
aligned_dataa_exp_w <= ( "0" & wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w234w);
aligned_dataa_man_dffe12_wi <= aligned_dataa_man_w(25 DOWNTO 2);
aligned_dataa_man_dffe12_wo <= aligned_dataa_man_dffe12;
aligned_dataa_man_dffe13_wi <= aligned_dataa_man_dffe12_wo;
aligned_dataa_man_dffe13_wo <= aligned_dataa_man_dffe13;
aligned_dataa_man_dffe14_wi <= aligned_dataa_man_dffe13_wo;
aligned_dataa_man_dffe14_wo <= aligned_dataa_man_dffe14;
aligned_dataa_man_dffe15_w <= ( aligned_dataa_man_dffe15_wo & "00");
aligned_dataa_man_dffe15_wi <= aligned_dataa_man_dffe14_wo;
aligned_dataa_man_dffe15_wo <= aligned_dataa_man_dffe15;
aligned_dataa_man_w <= ( wire_w248w & wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w243w & "00");
aligned_dataa_sign_dffe12_wi <= aligned_dataa_sign_w;
aligned_dataa_sign_dffe12_wo <= aligned_dataa_sign_dffe12;
aligned_dataa_sign_dffe13_wi <= aligned_dataa_sign_dffe12_wo;
aligned_dataa_sign_dffe13_wo <= aligned_dataa_sign_dffe13;
aligned_dataa_sign_dffe14_wi <= aligned_dataa_sign_dffe13_wo;
aligned_dataa_sign_dffe14_wo <= aligned_dataa_sign_dffe14;
aligned_dataa_sign_dffe15_wi <= aligned_dataa_sign_dffe14_wo;
aligned_dataa_sign_dffe15_wo <= aligned_dataa_sign_dffe15;
aligned_dataa_sign_w <= dataa_dffe11_wo(31);
aligned_datab_exp_dffe12_wi <= aligned_datab_exp_w;
aligned_datab_exp_dffe12_wo <= aligned_datab_exp_dffe12;
aligned_datab_exp_dffe13_wi <= aligned_datab_exp_dffe12_wo;
aligned_datab_exp_dffe13_wo <= aligned_datab_exp_dffe13;
aligned_datab_exp_dffe14_wi <= aligned_datab_exp_dffe13_wo;
aligned_datab_exp_dffe14_wo <= aligned_datab_exp_dffe14;
aligned_datab_exp_dffe15_wi <= aligned_datab_exp_dffe14_wo;
aligned_datab_exp_dffe15_wo <= aligned_datab_exp_dffe15;
aligned_datab_exp_w <= ( "0" & wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w253w);
aligned_datab_man_dffe12_wi <= aligned_datab_man_w(25 DOWNTO 2);
aligned_datab_man_dffe12_wo <= aligned_datab_man_dffe12;
aligned_datab_man_dffe13_wi <= aligned_datab_man_dffe12_wo;
aligned_datab_man_dffe13_wo <= aligned_datab_man_dffe13;
aligned_datab_man_dffe14_wi <= aligned_datab_man_dffe13_wo;
aligned_datab_man_dffe14_wo <= aligned_datab_man_dffe14;
aligned_datab_man_dffe15_w <= ( aligned_datab_man_dffe15_wo & "00");
aligned_datab_man_dffe15_wi <= aligned_datab_man_dffe14_wo;
aligned_datab_man_dffe15_wo <= aligned_datab_man_dffe15;
aligned_datab_man_w <= ( wire_w267w & wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w262w & "00");
aligned_datab_sign_dffe12_wi <= aligned_datab_sign_w;
aligned_datab_sign_dffe12_wo <= aligned_datab_sign_dffe12;
aligned_datab_sign_dffe13_wi <= aligned_datab_sign_dffe12_wo;
aligned_datab_sign_dffe13_wo <= aligned_datab_sign_dffe13;
aligned_datab_sign_dffe14_wi <= aligned_datab_sign_dffe13_wo;
aligned_datab_sign_dffe14_wo <= aligned_datab_sign_dffe14;
aligned_datab_sign_dffe15_wi <= aligned_datab_sign_dffe14_wo;
aligned_datab_sign_dffe15_wo <= aligned_datab_sign_dffe15;
aligned_datab_sign_w <= datab_dffe11_wo(31);
borrow_w <= (wire_w_lg_sticky_bit_dffe1_wo343w(0) AND wire_w_lg_add_sub_w2342w(0));
both_inputs_are_infinite_dffe1_wi <= (input_dataa_infinite_dffe15_wo AND input_datab_infinite_dffe15_wo);
both_inputs_are_infinite_dffe1_wo <= both_inputs_are_infinite_dffe1;
both_inputs_are_infinite_dffe25_wi <= both_inputs_are_infinite_dffe1_wo;
both_inputs_are_infinite_dffe25_wo <= both_inputs_are_infinite_dffe25_wi;
data_exp_dffe1_wi <= (wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w317w OR wire_w_lg_exp_amb_mux_dffe15_wo314w);
data_exp_dffe1_wo <= data_exp_dffe1;
dataa_dffe11_wi <= dataa;
dataa_dffe11_wo <= dataa_dffe11_wi;
dataa_man_dffe1_wi <= (wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w324w OR wire_w_lg_exp_amb_mux_dffe15_wo323w);
dataa_man_dffe1_wo <= dataa_man_dffe1;
dataa_sign_dffe1_wi <= aligned_dataa_sign_dffe15_wo;
dataa_sign_dffe1_wo <= dataa_sign_dffe1;
dataa_sign_dffe25_wi <= dataa_sign_dffe1_wo;
dataa_sign_dffe25_wo <= dataa_sign_dffe25_wi;
datab_dffe11_wi <= datab;
datab_dffe11_wo <= datab_dffe11_wi;
datab_man_dffe1_wi <= (wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w331w OR wire_w_lg_exp_amb_mux_dffe15_wo330w);
datab_man_dffe1_wo <= datab_man_dffe1;
datab_sign_dffe1_wi <= aligned_datab_sign_dffe15_wo;
datab_sign_dffe1_wo <= datab_sign_dffe1;
denormal_flag_w <= (((wire_w_lg_force_nan_w597w(0) AND wire_w_lg_force_infinity_w596w(0)) AND wire_w_lg_force_zero_w595w(0)) AND denormal_res_dffe4_wo);
denormal_res_dffe32_wi <= denormal_result_w;
denormal_res_dffe32_wo <= denormal_res_dffe32;
denormal_res_dffe33_wi <= denormal_res_dffe32_wo;
denormal_res_dffe33_wo <= denormal_res_dffe33_wi;
denormal_res_dffe3_wi <= denormal_res_dffe33_wo;
denormal_res_dffe3_wo <= denormal_res_dffe3;
denormal_res_dffe41_wi <= denormal_res_dffe42_wo;
denormal_res_dffe41_wo <= denormal_res_dffe41;
denormal_res_dffe42_wi <= denormal_res_dffe3_wo;
denormal_res_dffe42_wo <= denormal_res_dffe42_wi;
denormal_res_dffe4_wi <= denormal_res_dffe41_wo;
denormal_res_dffe4_wo <= denormal_res_dffe4;
denormal_result_w <= ((NOT exp_res_not_zero_w(8)) OR exp_adjustment2_add_sub_w(8));
exp_a_all_one_w <= ( wire_w_lg_w_dataa_range77w83w & wire_w_lg_w_dataa_range67w73w & wire_w_lg_w_dataa_range57w63w & wire_w_lg_w_dataa_range47w53w & wire_w_lg_w_dataa_range37w43w & wire_w_lg_w_dataa_range27w33w & wire_w_lg_w_dataa_range17w23w & dataa(23));
exp_a_not_zero_w <= ( wire_w_lg_w_dataa_range77w78w & wire_w_lg_w_dataa_range67w68w & wire_w_lg_w_dataa_range57w58w & wire_w_lg_w_dataa_range47w48w & wire_w_lg_w_dataa_range37w38w & wire_w_lg_w_dataa_range27w28w & wire_w_lg_w_dataa_range17w18w & dataa(23));
exp_adj_0pads <= (OTHERS => '0');
exp_adj_dffe21_wi <= (wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range359w362w OR wire_w361w);
exp_adj_dffe21_wo <= exp_adj_dffe21;
exp_adj_dffe23_wi <= exp_adj_dffe21_wo;
exp_adj_dffe23_wo <= exp_adj_dffe23;
exp_adj_dffe26_wi <= exp_adj_dffe23_wo;
exp_adj_dffe26_wo <= exp_adj_dffe26_wi;
exp_adjust_by_add1 <= "01";
exp_adjust_by_add2 <= "10";
exp_adjustment2_add_sub_dataa_w <= exp_value;
exp_adjustment2_add_sub_datab_w <= exp_adjustment_add_sub_w;
exp_adjustment2_add_sub_w <= wire_add_sub7_result;
exp_adjustment_add_sub_dataa_w <= ( priority_encoder_1pads_w & wire_leading_zeroes_cnt_q);
exp_adjustment_add_sub_datab_w <= ( exp_adj_0pads & exp_adj_dffe26_wo);
exp_adjustment_add_sub_w <= wire_add_sub6_result;
exp_all_ones_w <= (OTHERS => '1');
exp_all_zeros_w <= (OTHERS => '0');
exp_amb_mux_dffe13_wi <= exp_amb_mux_w;
exp_amb_mux_dffe13_wo <= exp_amb_mux_dffe13;
exp_amb_mux_dffe14_wi <= exp_amb_mux_dffe13_wo;
exp_amb_mux_dffe14_wo <= exp_amb_mux_dffe14;
exp_amb_mux_dffe15_wi <= exp_amb_mux_dffe14_wo;
exp_amb_mux_dffe15_wo <= exp_amb_mux_dffe15;
exp_amb_mux_w <= exp_amb_w(8);
exp_amb_w <= wire_add_sub1_result;
exp_b_all_one_w <= ( wire_w_lg_w_datab_range80w85w & wire_w_lg_w_datab_range70w75w & wire_w_lg_w_datab_range60w65w & wire_w_lg_w_datab_range50w55w & wire_w_lg_w_datab_range40w45w & wire_w_lg_w_datab_range30w35w & wire_w_lg_w_datab_range20w25w & datab(23));
exp_b_not_zero_w <= ( wire_w_lg_w_datab_range80w81w & wire_w_lg_w_datab_range70w71w & wire_w_lg_w_datab_range60w61w & wire_w_lg_w_datab_range50w51w & wire_w_lg_w_datab_range40w41w & wire_w_lg_w_datab_range30w31w & wire_w_lg_w_datab_range20w21w & datab(23));
exp_bma_w <= wire_add_sub2_result;
exp_diff_abs_exceed_max_w <= ( wire_w_lg_w_exp_diff_abs_exceed_max_w_range287w289w & wire_w_lg_w_exp_diff_abs_exceed_max_w_range283w286w & exp_diff_abs_w(5));
exp_diff_abs_max_w <= (OTHERS => '1');
exp_diff_abs_w <= (wire_w_lg_w_lg_exp_amb_mux_w276w277w OR wire_w_lg_exp_amb_mux_w274w);
exp_intermediate_res_dffe41_wi <= exp_intermediate_res_dffe42_wo;
exp_intermediate_res_dffe41_wo <= exp_intermediate_res_dffe41;
exp_intermediate_res_dffe42_wi <= exp_intermediate_res_w;
exp_intermediate_res_dffe42_wo <= exp_intermediate_res_dffe42_wi;
exp_intermediate_res_w <= exp_res_dffe3_wo;
exp_out_dffe5_wi <= (wire_w_lg_force_nan_w610w OR wire_w_lg_w_lg_force_nan_w597w609w);
exp_out_dffe5_wo <= exp_out_dffe5;
exp_res_dffe21_wi <= exp_res_dffe27_wo;
exp_res_dffe21_wo <= exp_res_dffe21;
exp_res_dffe22_wi <= exp_res_dffe2_wo;
exp_res_dffe22_wo <= exp_res_dffe22_wi;
exp_res_dffe23_wi <= exp_res_dffe21_wo;
exp_res_dffe23_wo <= exp_res_dffe23;
exp_res_dffe25_wi <= data_exp_dffe1_wo;
exp_res_dffe25_wo <= exp_res_dffe25_wi;
exp_res_dffe26_wi <= exp_res_dffe23_wo;
exp_res_dffe26_wo <= exp_res_dffe26_wi;
exp_res_dffe27_wi <= exp_res_dffe22_wo;
exp_res_dffe27_wo <= exp_res_dffe27_wi;
exp_res_dffe2_wi <= exp_res_dffe25_wo;
exp_res_dffe2_wo <= exp_res_dffe2;
exp_res_dffe32_wi <= wire_w_lg_w_lg_denormal_result_w536w537w;
exp_res_dffe32_wo <= exp_res_dffe32;
exp_res_dffe33_wi <= exp_res_dffe32_wo;
exp_res_dffe33_wo <= exp_res_dffe33_wi;
exp_res_dffe3_wi <= exp_res_dffe33_wo;
exp_res_dffe3_wo <= exp_res_dffe3;
exp_res_dffe4_wi <= exp_rounded_res_w;
exp_res_dffe4_wo <= exp_res_dffe4;
exp_res_max_w <= ( wire_w_lg_w_exp_res_max_w_range531w532w & wire_w_lg_w_exp_res_max_w_range529w530w & wire_w_lg_w_exp_res_max_w_range527w528w & wire_w_lg_w_exp_res_max_w_range525w526w & wire_w_lg_w_exp_res_max_w_range523w524w & wire_w_lg_w_exp_res_max_w_range521w522w & wire_w_lg_w_exp_res_max_w_range518w520w & exp_adjustment2_add_sub_w(0));
exp_res_not_zero_w <= ( wire_w_lg_w_exp_res_not_zero_w_range516w517w & wire_w_lg_w_exp_res_not_zero_w_range513w515w & wire_w_lg_w_exp_res_not_zero_w_range510w512w & wire_w_lg_w_exp_res_not_zero_w_range507w509w & wire_w_lg_w_exp_res_not_zero_w_range504w506w & wire_w_lg_w_exp_res_not_zero_w_range501w503w & wire_w_lg_w_exp_res_not_zero_w_range498w500w & wire_w_lg_w_exp_res_not_zero_w_range494w497w & exp_adjustment2_add_sub_w(0));
exp_res_rounding_adder_dataa_w <= ( "0" & exp_intermediate_res_dffe41_wo);
exp_res_rounding_adder_w <= wire_add_sub9_result;
exp_rounded_res_infinity_w <= exp_rounded_res_max_w(7);
exp_rounded_res_max_w <= ( wire_w_lg_w_exp_rounded_res_max_w_range587w589w & wire_w_lg_w_exp_rounded_res_max_w_range584w586w & wire_w_lg_w_exp_rounded_res_max_w_range581w583w & wire_w_lg_w_exp_rounded_res_max_w_range578w580w & wire_w_lg_w_exp_rounded_res_max_w_range575w577w & wire_w_lg_w_exp_rounded_res_max_w_range572w574w & wire_w_lg_w_exp_rounded_res_max_w_range568w571w & exp_rounded_res_w(0));
exp_rounded_res_w <= exp_res_rounding_adder_w(7 DOWNTO 0);
exp_rounding_adjustment_w <= ( "00000000" & man_res_rounding_add_sub_w(24));
exp_value <= ( "0" & exp_res_dffe26_wo);
force_infinity_w <= ((input_is_infinite_dffe4_wo OR rounded_res_infinity_dffe4_wo) OR infinite_res_dffe4_wo);
force_nan_w <= (infinity_magnitude_sub_dffe4_wo OR input_is_nan_dffe4_wo);
force_zero_w <= wire_w_lg_man_res_is_not_zero_dffe4_wo594w(0);
guard_bit_dffe3_wo <= man_res_w3(0);
infinite_output_sign_dffe1_wi <= (wire_w_lg_w_lg_input_datab_infinite_dffe15_wo337w338w(0) OR (input_datab_infinite_dffe15_wo AND aligned_datab_sign_dffe15_wo));
infinite_output_sign_dffe1_wo <= infinite_output_sign_dffe1;
infinite_output_sign_dffe21_wi <= infinite_output_sign_dffe27_wo;
infinite_output_sign_dffe21_wo <= infinite_output_sign_dffe21;
infinite_output_sign_dffe22_wi <= infinite_output_sign_dffe2_wo;
infinite_output_sign_dffe22_wo <= infinite_output_sign_dffe22_wi;
infinite_output_sign_dffe23_wi <= infinite_output_sign_dffe21_wo;
infinite_output_sign_dffe23_wo <= infinite_output_sign_dffe23;
infinite_output_sign_dffe25_wi <= infinite_output_sign_dffe1_wo;
infinite_output_sign_dffe25_wo <= infinite_output_sign_dffe25_wi;
infinite_output_sign_dffe26_wi <= infinite_output_sign_dffe23_wo;
infinite_output_sign_dffe26_wo <= infinite_output_sign_dffe26_wi;
infinite_output_sign_dffe27_wi <= infinite_output_sign_dffe22_wo;
infinite_output_sign_dffe27_wo <= infinite_output_sign_dffe27_wi;
infinite_output_sign_dffe2_wi <= infinite_output_sign_dffe25_wo;
infinite_output_sign_dffe2_wo <= infinite_output_sign_dffe2;
infinite_output_sign_dffe31_wi <= infinite_output_sign_dffe26_wo;
infinite_output_sign_dffe31_wo <= infinite_output_sign_dffe31;
infinite_output_sign_dffe32_wi <= infinite_output_sign_dffe31_wo;
infinite_output_sign_dffe32_wo <= infinite_output_sign_dffe32;
infinite_output_sign_dffe33_wi <= infinite_output_sign_dffe32_wo;
infinite_output_sign_dffe33_wo <= infinite_output_sign_dffe33_wi;
infinite_output_sign_dffe3_wi <= infinite_output_sign_dffe33_wo;
infinite_output_sign_dffe3_wo <= infinite_output_sign_dffe3;
infinite_output_sign_dffe41_wi <= infinite_output_sign_dffe42_wo;
infinite_output_sign_dffe41_wo <= infinite_output_sign_dffe41;
infinite_output_sign_dffe42_wi <= infinite_output_sign_dffe3_wo;
infinite_output_sign_dffe42_wo <= infinite_output_sign_dffe42_wi;
infinite_output_sign_dffe4_wi <= infinite_output_sign_dffe41_wo;
infinite_output_sign_dffe4_wo <= infinite_output_sign_dffe4;
infinite_res_dff32_wi <= wire_w_lg_w_exp_res_max_w_range533w539w(0);
infinite_res_dff32_wo <= infinite_res_dffe32;
infinite_res_dff33_wi <= infinite_res_dff32_wo;
infinite_res_dff33_wo <= infinite_res_dff33_wi;
infinite_res_dffe3_wi <= infinite_res_dff33_wo;
infinite_res_dffe3_wo <= infinite_res_dffe3;
infinite_res_dffe41_wi <= infinite_res_dffe42_wo;
infinite_res_dffe41_wo <= infinite_res_dffe41;
infinite_res_dffe42_wi <= infinite_res_dffe3_wo;
infinite_res_dffe42_wo <= infinite_res_dffe42_wi;
infinite_res_dffe4_wi <= infinite_res_dffe41_wo;
infinite_res_dffe4_wo <= infinite_res_dffe4;
infinity_magnitude_sub_dffe21_wi <= infinity_magnitude_sub_dffe27_wo;
infinity_magnitude_sub_dffe21_wo <= infinity_magnitude_sub_dffe21;
infinity_magnitude_sub_dffe22_wi <= infinity_magnitude_sub_dffe2_wo;
infinity_magnitude_sub_dffe22_wo <= infinity_magnitude_sub_dffe22_wi;
infinity_magnitude_sub_dffe23_wi <= infinity_magnitude_sub_dffe21_wo;
infinity_magnitude_sub_dffe23_wo <= infinity_magnitude_sub_dffe23;
infinity_magnitude_sub_dffe26_wi <= infinity_magnitude_sub_dffe23_wo;
infinity_magnitude_sub_dffe26_wo <= infinity_magnitude_sub_dffe26_wi;
infinity_magnitude_sub_dffe27_wi <= infinity_magnitude_sub_dffe22_wo;
infinity_magnitude_sub_dffe27_wo <= infinity_magnitude_sub_dffe27_wi;
infinity_magnitude_sub_dffe2_wi <= (wire_w_lg_add_sub_dffe25_wo469w(0) AND both_inputs_are_infinite_dffe25_wo);
infinity_magnitude_sub_dffe2_wo <= infinity_magnitude_sub_dffe2;
infinity_magnitude_sub_dffe31_wi <= infinity_magnitude_sub_dffe26_wo;
infinity_magnitude_sub_dffe31_wo <= infinity_magnitude_sub_dffe31;
infinity_magnitude_sub_dffe32_wi <= infinity_magnitude_sub_dffe31_wo;
infinity_magnitude_sub_dffe32_wo <= infinity_magnitude_sub_dffe32;
infinity_magnitude_sub_dffe33_wi <= infinity_magnitude_sub_dffe32_wo;
infinity_magnitude_sub_dffe33_wo <= infinity_magnitude_sub_dffe33_wi;
infinity_magnitude_sub_dffe3_wi <= infinity_magnitude_sub_dffe33_wo;
infinity_magnitude_sub_dffe3_wo <= infinity_magnitude_sub_dffe3;
infinity_magnitude_sub_dffe41_wi <= infinity_magnitude_sub_dffe42_wo;
infinity_magnitude_sub_dffe41_wo <= infinity_magnitude_sub_dffe41;
infinity_magnitude_sub_dffe42_wi <= infinity_magnitude_sub_dffe3_wo;
infinity_magnitude_sub_dffe42_wo <= infinity_magnitude_sub_dffe42_wi;
infinity_magnitude_sub_dffe4_wi <= infinity_magnitude_sub_dffe41_wo;
infinity_magnitude_sub_dffe4_wo <= infinity_magnitude_sub_dffe4;
input_dataa_denormal_dffe11_wi <= input_dataa_denormal_w;
input_dataa_denormal_dffe11_wo <= input_dataa_denormal_dffe11_wi;
input_dataa_denormal_w <= ((NOT exp_a_not_zero_w(7)) AND man_a_not_zero_w(22));
input_dataa_infinite_dffe11_wi <= input_dataa_infinite_w;
input_dataa_infinite_dffe11_wo <= input_dataa_infinite_dffe11_wi;
input_dataa_infinite_dffe12_wi <= input_dataa_infinite_dffe11_wo;
input_dataa_infinite_dffe12_wo <= input_dataa_infinite_dffe12;
input_dataa_infinite_dffe13_wi <= input_dataa_infinite_dffe12_wo;
input_dataa_infinite_dffe13_wo <= input_dataa_infinite_dffe13;
input_dataa_infinite_dffe14_wi <= input_dataa_infinite_dffe13_wo;
input_dataa_infinite_dffe14_wo <= input_dataa_infinite_dffe14;
input_dataa_infinite_dffe15_wi <= input_dataa_infinite_dffe14_wo;
input_dataa_infinite_dffe15_wo <= input_dataa_infinite_dffe15;
input_dataa_infinite_w <= wire_w_lg_w_exp_a_all_one_w_range84w220w(0);
input_dataa_nan_dffe11_wi <= input_dataa_nan_w;
input_dataa_nan_dffe11_wo <= input_dataa_nan_dffe11_wi;
input_dataa_nan_dffe12_wi <= input_dataa_nan_dffe11_wo;
input_dataa_nan_dffe12_wo <= input_dataa_nan_dffe12;
input_dataa_nan_w <= (exp_a_all_one_w(7) AND man_a_not_zero_w(22));
input_dataa_zero_dffe11_wi <= input_dataa_zero_w;
input_dataa_zero_dffe11_wo <= input_dataa_zero_dffe11_wi;
input_dataa_zero_w <= ((NOT exp_a_not_zero_w(7)) AND wire_w_lg_w_man_a_not_zero_w_range215w219w(0));
input_datab_denormal_dffe11_wi <= input_datab_denormal_w;
input_datab_denormal_dffe11_wo <= input_datab_denormal_dffe11_wi;
input_datab_denormal_w <= ((NOT exp_b_not_zero_w(7)) AND man_b_not_zero_w(22));
input_datab_infinite_dffe11_wi <= input_datab_infinite_w;
input_datab_infinite_dffe11_wo <= input_datab_infinite_dffe11_wi;
input_datab_infinite_dffe12_wi <= input_datab_infinite_dffe11_wo;
input_datab_infinite_dffe12_wo <= input_datab_infinite_dffe12;
input_datab_infinite_dffe13_wi <= input_datab_infinite_dffe12_wo;
input_datab_infinite_dffe13_wo <= input_datab_infinite_dffe13;
input_datab_infinite_dffe14_wi <= input_datab_infinite_dffe13_wo;
input_datab_infinite_dffe14_wo <= input_datab_infinite_dffe14;
input_datab_infinite_dffe15_wi <= input_datab_infinite_dffe14_wo;
input_datab_infinite_dffe15_wo <= input_datab_infinite_dffe15;
input_datab_infinite_w <= wire_w_lg_w_exp_b_all_one_w_range86w226w(0);
input_datab_nan_dffe11_wi <= input_datab_nan_w;
input_datab_nan_dffe11_wo <= input_datab_nan_dffe11_wi;
input_datab_nan_dffe12_wi <= input_datab_nan_dffe11_wo;
input_datab_nan_dffe12_wo <= input_datab_nan_dffe12;
input_datab_nan_w <= (exp_b_all_one_w(7) AND man_b_not_zero_w(22));
input_datab_zero_dffe11_wi <= input_datab_zero_w;
input_datab_zero_dffe11_wo <= input_datab_zero_dffe11_wi;
input_datab_zero_w <= ((NOT exp_b_not_zero_w(7)) AND wire_w_lg_w_man_b_not_zero_w_range218w225w(0));
input_is_infinite_dffe1_wi <= (input_dataa_infinite_dffe15_wo OR input_datab_infinite_dffe15_wo);
input_is_infinite_dffe1_wo <= input_is_infinite_dffe1;
input_is_infinite_dffe21_wi <= input_is_infinite_dffe27_wo;
input_is_infinite_dffe21_wo <= input_is_infinite_dffe21;
input_is_infinite_dffe22_wi <= input_is_infinite_dffe2_wo;
input_is_infinite_dffe22_wo <= input_is_infinite_dffe22_wi;
input_is_infinite_dffe23_wi <= input_is_infinite_dffe21_wo;
input_is_infinite_dffe23_wo <= input_is_infinite_dffe23;
input_is_infinite_dffe25_wi <= input_is_infinite_dffe1_wo;
input_is_infinite_dffe25_wo <= input_is_infinite_dffe25_wi;
input_is_infinite_dffe26_wi <= input_is_infinite_dffe23_wo;
input_is_infinite_dffe26_wo <= input_is_infinite_dffe26_wi;
input_is_infinite_dffe27_wi <= input_is_infinite_dffe22_wo;
input_is_infinite_dffe27_wo <= input_is_infinite_dffe27_wi;
input_is_infinite_dffe2_wi <= input_is_infinite_dffe25_wo;
input_is_infinite_dffe2_wo <= input_is_infinite_dffe2;
input_is_infinite_dffe31_wi <= input_is_infinite_dffe26_wo;
input_is_infinite_dffe31_wo <= input_is_infinite_dffe31;
input_is_infinite_dffe32_wi <= input_is_infinite_dffe31_wo;
input_is_infinite_dffe32_wo <= input_is_infinite_dffe32;
input_is_infinite_dffe33_wi <= input_is_infinite_dffe32_wo;
input_is_infinite_dffe33_wo <= input_is_infinite_dffe33_wi;
input_is_infinite_dffe3_wi <= input_is_infinite_dffe33_wo;
input_is_infinite_dffe3_wo <= input_is_infinite_dffe3;
input_is_infinite_dffe41_wi <= input_is_infinite_dffe42_wo;
input_is_infinite_dffe41_wo <= input_is_infinite_dffe41;
input_is_infinite_dffe42_wi <= input_is_infinite_dffe3_wo;
input_is_infinite_dffe42_wo <= input_is_infinite_dffe42_wi;
input_is_infinite_dffe4_wi <= input_is_infinite_dffe41_wo;
input_is_infinite_dffe4_wo <= input_is_infinite_dffe4;
input_is_nan_dffe13_wi <= (input_dataa_nan_dffe12_wo OR input_datab_nan_dffe12_wo);
input_is_nan_dffe13_wo <= input_is_nan_dffe13;
input_is_nan_dffe14_wi <= input_is_nan_dffe13_wo;
input_is_nan_dffe14_wo <= input_is_nan_dffe14;
input_is_nan_dffe15_wi <= input_is_nan_dffe14_wo;
input_is_nan_dffe15_wo <= input_is_nan_dffe15;
input_is_nan_dffe1_wi <= input_is_nan_dffe15_wo;
input_is_nan_dffe1_wo <= input_is_nan_dffe1;
input_is_nan_dffe21_wi <= input_is_nan_dffe27_wo;
input_is_nan_dffe21_wo <= input_is_nan_dffe21;
input_is_nan_dffe22_wi <= input_is_nan_dffe2_wo;
input_is_nan_dffe22_wo <= input_is_nan_dffe22_wi;
input_is_nan_dffe23_wi <= input_is_nan_dffe21_wo;
input_is_nan_dffe23_wo <= input_is_nan_dffe23;
input_is_nan_dffe25_wi <= input_is_nan_dffe1_wo;
input_is_nan_dffe25_wo <= input_is_nan_dffe25_wi;
input_is_nan_dffe26_wi <= input_is_nan_dffe23_wo;
input_is_nan_dffe26_wo <= input_is_nan_dffe26_wi;
input_is_nan_dffe27_wi <= input_is_nan_dffe22_wo;
input_is_nan_dffe27_wo <= input_is_nan_dffe27_wi;
input_is_nan_dffe2_wi <= input_is_nan_dffe25_wo;
input_is_nan_dffe2_wo <= input_is_nan_dffe2;
input_is_nan_dffe31_wi <= input_is_nan_dffe26_wo;
input_is_nan_dffe31_wo <= input_is_nan_dffe31;
input_is_nan_dffe32_wi <= input_is_nan_dffe31_wo;
input_is_nan_dffe32_wo <= input_is_nan_dffe32;
input_is_nan_dffe33_wi <= input_is_nan_dffe32_wo;
input_is_nan_dffe33_wo <= input_is_nan_dffe33_wi;
input_is_nan_dffe3_wi <= input_is_nan_dffe33_wo;
input_is_nan_dffe3_wo <= input_is_nan_dffe3;
input_is_nan_dffe41_wi <= input_is_nan_dffe42_wo;
input_is_nan_dffe41_wo <= input_is_nan_dffe41;
input_is_nan_dffe42_wi <= input_is_nan_dffe3_wo;
input_is_nan_dffe42_wo <= input_is_nan_dffe42_wi;
input_is_nan_dffe4_wi <= input_is_nan_dffe41_wo;
input_is_nan_dffe4_wo <= input_is_nan_dffe4;
man_2comp_res_dataa_w <= ( pos_sign_bit_ext & datab_man_dffe1_wo);
man_2comp_res_datab_w <= ( pos_sign_bit_ext & dataa_man_dffe1_wo);
man_2comp_res_w <= wire_add_sub5_result;
man_a_not_zero_w <= ( wire_w_lg_w_dataa_range213w214w & wire_w_lg_w_dataa_range207w208w & wire_w_lg_w_dataa_range201w202w & wire_w_lg_w_dataa_range195w196w & wire_w_lg_w_dataa_range189w190w & wire_w_lg_w_dataa_range183w184w & wire_w_lg_w_dataa_range177w178w & wire_w_lg_w_dataa_range171w172w & wire_w_lg_w_dataa_range165w166w & wire_w_lg_w_dataa_range159w160w & wire_w_lg_w_dataa_range153w154w & wire_w_lg_w_dataa_range147w148w & wire_w_lg_w_dataa_range141w142w & wire_w_lg_w_dataa_range135w136w & wire_w_lg_w_dataa_range129w130w & wire_w_lg_w_dataa_range123w124w & wire_w_lg_w_dataa_range117w118w & wire_w_lg_w_dataa_range111w112w & wire_w_lg_w_dataa_range105w106w & wire_w_lg_w_dataa_range99w100w & wire_w_lg_w_dataa_range93w94w & wire_w_lg_w_dataa_range87w88w & dataa(0));
man_add_sub_dataa_w <= ( pos_sign_bit_ext & dataa_man_dffe1_wo);
man_add_sub_datab_w <= ( pos_sign_bit_ext & datab_man_dffe1_wo);
man_add_sub_res_mag_dffe21_wi <= man_res_mag_w2;
man_add_sub_res_mag_dffe21_wo <= man_add_sub_res_mag_dffe21;
man_add_sub_res_mag_dffe23_wi <= man_add_sub_res_mag_dffe21_wo;
man_add_sub_res_mag_dffe23_wo <= man_add_sub_res_mag_dffe23;
man_add_sub_res_mag_dffe26_wi <= man_add_sub_res_mag_dffe23_wo;
man_add_sub_res_mag_dffe26_wo <= man_add_sub_res_mag_dffe26_wi;
man_add_sub_res_mag_dffe27_wi <= man_add_sub_res_mag_w2;
man_add_sub_res_mag_dffe27_wo <= man_add_sub_res_mag_dffe27_wi;
man_add_sub_res_mag_w2 <= (wire_w_lg_w_man_add_sub_w_range350w357w OR wire_w_lg_w_lg_w_man_add_sub_w_range350w353w356w);
man_add_sub_res_sign_dffe21_wo <= man_add_sub_res_sign_dffe21;
man_add_sub_res_sign_dffe23_wi <= man_add_sub_res_sign_dffe21_wo;
man_add_sub_res_sign_dffe23_wo <= man_add_sub_res_sign_dffe23;
man_add_sub_res_sign_dffe26_wi <= man_add_sub_res_sign_dffe23_wo;
man_add_sub_res_sign_dffe26_wo <= man_add_sub_res_sign_dffe26_wi;
man_add_sub_res_sign_dffe27_wi <= man_add_sub_res_sign_w2;
man_add_sub_res_sign_dffe27_wo <= man_add_sub_res_sign_dffe27_wi;
man_add_sub_res_sign_w2 <= (wire_w_lg_need_complement_dffe22_wo354w(0) OR (wire_w_lg_need_complement_dffe22_wo351w(0) AND man_add_sub_w(27)));
man_add_sub_w <= wire_add_sub4_result;
man_all_zeros_w <= (OTHERS => '0');
man_b_not_zero_w <= ( wire_w_lg_w_datab_range216w217w & wire_w_lg_w_datab_range210w211w & wire_w_lg_w_datab_range204w205w & wire_w_lg_w_datab_range198w199w & wire_w_lg_w_datab_range192w193w & wire_w_lg_w_datab_range186w187w & wire_w_lg_w_datab_range180w181w & wire_w_lg_w_datab_range174w175w & wire_w_lg_w_datab_range168w169w & wire_w_lg_w_datab_range162w163w & wire_w_lg_w_datab_range156w157w & wire_w_lg_w_datab_range150w151w & wire_w_lg_w_datab_range144w145w & wire_w_lg_w_datab_range138w139w & wire_w_lg_w_datab_range132w133w & wire_w_lg_w_datab_range126w127w & wire_w_lg_w_datab_range120w121w & wire_w_lg_w_datab_range114w115w & wire_w_lg_w_datab_range108w109w & wire_w_lg_w_datab_range102w103w & wire_w_lg_w_datab_range96w97w & wire_w_lg_w_datab_range90w91w & datab(0));
man_dffe31_wo <= man_dffe31;
man_intermediate_res_w <= ( "00" & man_res_w3);
man_leading_zeros_cnt_w <= man_leading_zeros_dffe31_wo;
man_leading_zeros_dffe31_wi <= (NOT wire_leading_zeroes_cnt_q);
man_leading_zeros_dffe31_wo <= man_leading_zeros_dffe31;
man_nan_w <= "10000000000000000000000";
man_out_dffe5_wi <= (wire_w_lg_force_nan_w619w OR wire_w_lg_w_lg_force_nan_w597w618w);
man_out_dffe5_wo <= man_out_dffe5;
man_res_dffe4_wi <= man_rounded_res_w;
man_res_dffe4_wo <= man_res_dffe4;
man_res_is_not_zero_dffe31_wi <= man_res_not_zero_dffe26_wo;
man_res_is_not_zero_dffe31_wo <= man_res_is_not_zero_dffe31;
man_res_is_not_zero_dffe32_wi <= man_res_is_not_zero_dffe31_wo;
man_res_is_not_zero_dffe32_wo <= man_res_is_not_zero_dffe32;
man_res_is_not_zero_dffe33_wi <= man_res_is_not_zero_dffe32_wo;
man_res_is_not_zero_dffe33_wo <= man_res_is_not_zero_dffe33_wi;
man_res_is_not_zero_dffe3_wi <= man_res_is_not_zero_dffe33_wo;
man_res_is_not_zero_dffe3_wo <= man_res_is_not_zero_dffe3;
man_res_is_not_zero_dffe41_wi <= man_res_is_not_zero_dffe42_wo;
man_res_is_not_zero_dffe41_wo <= man_res_is_not_zero_dffe41;
man_res_is_not_zero_dffe42_wi <= man_res_is_not_zero_dffe3_wo;
man_res_is_not_zero_dffe42_wo <= man_res_is_not_zero_dffe42_wi;
man_res_is_not_zero_dffe4_wi <= man_res_is_not_zero_dffe41_wo;
man_res_is_not_zero_dffe4_wo <= man_res_is_not_zero_dffe4;
man_res_mag_w2 <= (wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range359w392w OR wire_w390w);
man_res_not_zero_dffe23_wi <= man_res_not_zero_w2(24);
man_res_not_zero_dffe23_wo <= man_res_not_zero_dffe23;
man_res_not_zero_dffe26_wi <= man_res_not_zero_dffe23_wo;
man_res_not_zero_dffe26_wo <= man_res_not_zero_dffe26_wi;
man_res_not_zero_w2 <= ( wire_w_lg_w_man_res_not_zero_w2_range465w467w & wire_w_lg_w_man_res_not_zero_w2_range462w464w & wire_w_lg_w_man_res_not_zero_w2_range459w461w & wire_w_lg_w_man_res_not_zero_w2_range456w458w & wire_w_lg_w_man_res_not_zero_w2_range453w455w & wire_w_lg_w_man_res_not_zero_w2_range450w452w & wire_w_lg_w_man_res_not_zero_w2_range447w449w & wire_w_lg_w_man_res_not_zero_w2_range444w446w & wire_w_lg_w_man_res_not_zero_w2_range441w443w & wire_w_lg_w_man_res_not_zero_w2_range438w440w & wire_w_lg_w_man_res_not_zero_w2_range435w437w & wire_w_lg_w_man_res_not_zero_w2_range432w434w & wire_w_lg_w_man_res_not_zero_w2_range429w431w & wire_w_lg_w_man_res_not_zero_w2_range426w428w & wire_w_lg_w_man_res_not_zero_w2_range423w425w & wire_w_lg_w_man_res_not_zero_w2_range420w422w & wire_w_lg_w_man_res_not_zero_w2_range417w419w & wire_w_lg_w_man_res_not_zero_w2_range414w416w & wire_w_lg_w_man_res_not_zero_w2_range411w413w & wire_w_lg_w_man_res_not_zero_w2_range408w410w & wire_w_lg_w_man_res_not_zero_w2_range405w407w & wire_w_lg_w_man_res_not_zero_w2_range402w404w & wire_w_lg_w_man_res_not_zero_w2_range399w401w & wire_w_lg_w_man_res_not_zero_w2_range395w398w & man_add_sub_res_mag_dffe21_wo(1));
man_res_rounding_add_sub_datab_w <= ( "0000000000000000000000000" & man_rounding_add_value_w);
man_res_rounding_add_sub_w <= wire_add_sub8_result;
man_res_w3 <= wire_lbarrel_shift_result(25 DOWNTO 2);
man_rounded_res_w <= (wire_w_lg_w_man_res_rounding_add_sub_w_range552w556w OR wire_w554w);
man_rounding_add_value_w <= (round_bit_dffe3_wo AND (sticky_bit_dffe3_wo OR guard_bit_dffe3_wo));
man_smaller_dffe13_wi <= man_smaller_w;
man_smaller_dffe13_wo <= man_smaller_dffe13;
man_smaller_w <= (wire_w_lg_exp_amb_mux_w280w OR wire_w_lg_w_lg_exp_amb_mux_w276w279w);
need_complement_dffe22_wi <= need_complement_dffe2_wo;
need_complement_dffe22_wo <= need_complement_dffe22_wi;
need_complement_dffe2_wi <= dataa_sign_dffe25_wo;
need_complement_dffe2_wo <= need_complement_dffe2;
pos_sign_bit_ext <= (OTHERS => '0');
priority_encoder_1pads_w <= (OTHERS => '1');
result <= ( sign_out_dffe5_wo & exp_out_dffe5_wo & man_out_dffe5_wo);
round_bit_dffe21_wi <= round_bit_w;
round_bit_dffe21_wo <= round_bit_dffe21;
round_bit_dffe23_wi <= round_bit_dffe21_wo;
round_bit_dffe23_wo <= round_bit_dffe23;
round_bit_dffe26_wi <= round_bit_dffe23_wo;
round_bit_dffe26_wo <= round_bit_dffe26_wi;
round_bit_dffe31_wi <= round_bit_dffe26_wo;
round_bit_dffe31_wo <= round_bit_dffe31;
round_bit_dffe32_wi <= round_bit_dffe31_wo;
round_bit_dffe32_wo <= round_bit_dffe32;
round_bit_dffe33_wi <= round_bit_dffe32_wo;
round_bit_dffe33_wo <= round_bit_dffe33_wi;
round_bit_dffe3_wi <= round_bit_dffe33_wo;
round_bit_dffe3_wo <= round_bit_dffe3;
round_bit_w <= ((((wire_w375w(0) AND man_add_sub_res_mag_dffe27_wo(0)) OR ((wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range359w360w(0) AND man_add_sub_res_mag_dffe27_wo(25)) AND man_add_sub_res_mag_dffe27_wo(1))) OR (wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range359w369w(0) AND man_add_sub_res_mag_dffe27_wo(2))) OR ((man_add_sub_res_mag_dffe27_wo(26) AND man_add_sub_res_mag_dffe27_wo(25)) AND man_add_sub_res_mag_dffe27_wo(2)));
rounded_res_infinity_dffe4_wi <= exp_rounded_res_infinity_w;
rounded_res_infinity_dffe4_wo <= rounded_res_infinity_dffe4;
rshift_distance_dffe13_wi <= rshift_distance_w;
rshift_distance_dffe13_wo <= rshift_distance_dffe13;
rshift_distance_dffe14_wi <= rshift_distance_dffe13_wo;
rshift_distance_dffe14_wo <= rshift_distance_dffe14;
rshift_distance_dffe15_wi <= rshift_distance_dffe14_wo;
rshift_distance_dffe15_wo <= rshift_distance_dffe15;
rshift_distance_w <= (wire_w_lg_w_exp_diff_abs_exceed_max_w_range290w294w OR wire_w293w);
sign_dffe31_wi <= ((man_res_not_zero_dffe26_wo AND man_add_sub_res_sign_dffe26_wo) OR wire_w_lg_w_lg_man_res_not_zero_dffe26_wo481w482w(0));
sign_dffe31_wo <= sign_dffe31;
sign_dffe32_wi <= sign_dffe31_wo;
sign_dffe32_wo <= sign_dffe32;
sign_dffe33_wi <= sign_dffe32_wo;
sign_dffe33_wo <= sign_dffe33_wi;
sign_out_dffe5_wi <= (wire_w_lg_force_nan_w597w(0) AND ((force_infinity_w AND infinite_output_sign_dffe4_wo) OR wire_w_lg_w_lg_force_infinity_w596w621w(0)));
sign_out_dffe5_wo <= sign_out_dffe5;
sign_res_dffe3_wi <= sign_dffe33_wo;
sign_res_dffe3_wo <= sign_res_dffe3;
sign_res_dffe41_wi <= sign_res_dffe42_wo;
sign_res_dffe41_wo <= sign_res_dffe41;
sign_res_dffe42_wi <= sign_res_dffe3_wo;
sign_res_dffe42_wo <= sign_res_dffe42_wi;
sign_res_dffe4_wi <= sign_res_dffe41_wo;
sign_res_dffe4_wo <= sign_res_dffe4;
sticky_bit_cnt_dataa_w <= ( "0" & rshift_distance_dffe15_wo);
sticky_bit_cnt_datab_w <= ( "0" & wire_trailing_zeros_cnt_q);
sticky_bit_cnt_res_w <= wire_add_sub3_result;
sticky_bit_dffe1_wi <= wire_trailing_zeros_limit_comparator_agb;
sticky_bit_dffe1_wo <= sticky_bit_dffe1;
sticky_bit_dffe21_wi <= sticky_bit_w;
sticky_bit_dffe21_wo <= sticky_bit_dffe21;
sticky_bit_dffe22_wi <= sticky_bit_dffe2_wo;
sticky_bit_dffe22_wo <= sticky_bit_dffe22_wi;
sticky_bit_dffe23_wi <= sticky_bit_dffe21_wo;
sticky_bit_dffe23_wo <= sticky_bit_dffe23;
sticky_bit_dffe25_wi <= sticky_bit_dffe1_wo;
sticky_bit_dffe25_wo <= sticky_bit_dffe25_wi;
sticky_bit_dffe26_wi <= sticky_bit_dffe23_wo;
sticky_bit_dffe26_wo <= sticky_bit_dffe26_wi;
sticky_bit_dffe27_wi <= sticky_bit_dffe22_wo;
sticky_bit_dffe27_wo <= sticky_bit_dffe27_wi;
sticky_bit_dffe2_wi <= sticky_bit_dffe25_wo;
sticky_bit_dffe2_wo <= sticky_bit_dffe2;
sticky_bit_dffe31_wi <= sticky_bit_dffe26_wo;
sticky_bit_dffe31_wo <= sticky_bit_dffe31;
sticky_bit_dffe32_wi <= sticky_bit_dffe31_wo;
sticky_bit_dffe32_wo <= sticky_bit_dffe32;
sticky_bit_dffe33_wi <= sticky_bit_dffe32_wo;
sticky_bit_dffe33_wo <= sticky_bit_dffe33_wi;
sticky_bit_dffe3_wi <= sticky_bit_dffe33_wo;
sticky_bit_dffe3_wo <= sticky_bit_dffe3;
sticky_bit_w <= (((wire_w_lg_w375w385w(0) OR ((wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range359w360w(0) AND man_add_sub_res_mag_dffe27_wo(25)) AND wire_w_lg_sticky_bit_dffe27_wo380w(0))) OR (wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range359w369w(0) AND (wire_w_lg_sticky_bit_dffe27_wo380w(0) OR man_add_sub_res_mag_dffe27_wo(1)))) OR ((man_add_sub_res_mag_dffe27_wo(26) AND man_add_sub_res_mag_dffe27_wo(25)) AND (wire_w_lg_sticky_bit_dffe27_wo380w(0) OR man_add_sub_res_mag_dffe27_wo(1))));
trailing_zeros_limit_w <= "000010";
zero_man_sign_dffe21_wi <= zero_man_sign_dffe27_wo;
zero_man_sign_dffe21_wo <= zero_man_sign_dffe21;
zero_man_sign_dffe22_wi <= zero_man_sign_dffe2_wo;
zero_man_sign_dffe22_wo <= zero_man_sign_dffe22_wi;
zero_man_sign_dffe23_wi <= zero_man_sign_dffe21_wo;
zero_man_sign_dffe23_wo <= zero_man_sign_dffe23;
zero_man_sign_dffe26_wi <= zero_man_sign_dffe23_wo;
zero_man_sign_dffe26_wo <= zero_man_sign_dffe26_wi;
zero_man_sign_dffe27_wi <= zero_man_sign_dffe22_wo;
zero_man_sign_dffe27_wo <= zero_man_sign_dffe27_wi;
zero_man_sign_dffe2_wi <= (dataa_sign_dffe25_wo AND add_sub_dffe25_wo);
zero_man_sign_dffe2_wo <= zero_man_sign_dffe2;
wire_w_aligned_dataa_exp_dffe15_wo_range315w <= aligned_dataa_exp_dffe15_wo(7 DOWNTO 0);
wire_w_aligned_datab_exp_dffe15_wo_range313w <= aligned_datab_exp_dffe15_wo(7 DOWNTO 0);
wire_w_dataa_range141w(0) <= dataa(10);
wire_w_dataa_range147w(0) <= dataa(11);
wire_w_dataa_range153w(0) <= dataa(12);
wire_w_dataa_range159w(0) <= dataa(13);
wire_w_dataa_range165w(0) <= dataa(14);
wire_w_dataa_range171w(0) <= dataa(15);
wire_w_dataa_range177w(0) <= dataa(16);
wire_w_dataa_range183w(0) <= dataa(17);
wire_w_dataa_range189w(0) <= dataa(18);
wire_w_dataa_range195w(0) <= dataa(19);
wire_w_dataa_range87w(0) <= dataa(1);
wire_w_dataa_range201w(0) <= dataa(20);
wire_w_dataa_range207w(0) <= dataa(21);
wire_w_dataa_range213w(0) <= dataa(22);
wire_w_dataa_range17w(0) <= dataa(24);
wire_w_dataa_range27w(0) <= dataa(25);
wire_w_dataa_range37w(0) <= dataa(26);
wire_w_dataa_range47w(0) <= dataa(27);
wire_w_dataa_range57w(0) <= dataa(28);
wire_w_dataa_range67w(0) <= dataa(29);
wire_w_dataa_range93w(0) <= dataa(2);
wire_w_dataa_range77w(0) <= dataa(30);
wire_w_dataa_range99w(0) <= dataa(3);
wire_w_dataa_range105w(0) <= dataa(4);
wire_w_dataa_range111w(0) <= dataa(5);
wire_w_dataa_range117w(0) <= dataa(6);
wire_w_dataa_range123w(0) <= dataa(7);
wire_w_dataa_range129w(0) <= dataa(8);
wire_w_dataa_range135w(0) <= dataa(9);
wire_w_dataa_dffe11_wo_range242w <= dataa_dffe11_wo(22 DOWNTO 0);
wire_w_dataa_dffe11_wo_range232w <= dataa_dffe11_wo(30 DOWNTO 23);
wire_w_datab_range144w(0) <= datab(10);
wire_w_datab_range150w(0) <= datab(11);
wire_w_datab_range156w(0) <= datab(12);
wire_w_datab_range162w(0) <= datab(13);
wire_w_datab_range168w(0) <= datab(14);
wire_w_datab_range174w(0) <= datab(15);
wire_w_datab_range180w(0) <= datab(16);
wire_w_datab_range186w(0) <= datab(17);
wire_w_datab_range192w(0) <= datab(18);
wire_w_datab_range198w(0) <= datab(19);
wire_w_datab_range90w(0) <= datab(1);
wire_w_datab_range204w(0) <= datab(20);
wire_w_datab_range210w(0) <= datab(21);
wire_w_datab_range216w(0) <= datab(22);
wire_w_datab_range20w(0) <= datab(24);
wire_w_datab_range30w(0) <= datab(25);
wire_w_datab_range40w(0) <= datab(26);
wire_w_datab_range50w(0) <= datab(27);
wire_w_datab_range60w(0) <= datab(28);
wire_w_datab_range70w(0) <= datab(29);
wire_w_datab_range96w(0) <= datab(2);
wire_w_datab_range80w(0) <= datab(30);
wire_w_datab_range102w(0) <= datab(3);
wire_w_datab_range108w(0) <= datab(4);
wire_w_datab_range114w(0) <= datab(5);
wire_w_datab_range120w(0) <= datab(6);
wire_w_datab_range126w(0) <= datab(7);
wire_w_datab_range132w(0) <= datab(8);
wire_w_datab_range138w(0) <= datab(9);
wire_w_datab_dffe11_wo_range261w <= datab_dffe11_wo(22 DOWNTO 0);
wire_w_datab_dffe11_wo_range251w <= datab_dffe11_wo(30 DOWNTO 23);
wire_w_exp_a_all_one_w_range7w(0) <= exp_a_all_one_w(0);
wire_w_exp_a_all_one_w_range24w(0) <= exp_a_all_one_w(1);
wire_w_exp_a_all_one_w_range34w(0) <= exp_a_all_one_w(2);
wire_w_exp_a_all_one_w_range44w(0) <= exp_a_all_one_w(3);
wire_w_exp_a_all_one_w_range54w(0) <= exp_a_all_one_w(4);
wire_w_exp_a_all_one_w_range64w(0) <= exp_a_all_one_w(5);
wire_w_exp_a_all_one_w_range74w(0) <= exp_a_all_one_w(6);
wire_w_exp_a_all_one_w_range84w(0) <= exp_a_all_one_w(7);
wire_w_exp_a_not_zero_w_range2w(0) <= exp_a_not_zero_w(0);
wire_w_exp_a_not_zero_w_range19w(0) <= exp_a_not_zero_w(1);
wire_w_exp_a_not_zero_w_range29w(0) <= exp_a_not_zero_w(2);
wire_w_exp_a_not_zero_w_range39w(0) <= exp_a_not_zero_w(3);
wire_w_exp_a_not_zero_w_range49w(0) <= exp_a_not_zero_w(4);
wire_w_exp_a_not_zero_w_range59w(0) <= exp_a_not_zero_w(5);
wire_w_exp_a_not_zero_w_range69w(0) <= exp_a_not_zero_w(6);
wire_w_exp_adjustment2_add_sub_w_range496w(0) <= exp_adjustment2_add_sub_w(1);
wire_w_exp_adjustment2_add_sub_w_range499w(0) <= exp_adjustment2_add_sub_w(2);
wire_w_exp_adjustment2_add_sub_w_range502w(0) <= exp_adjustment2_add_sub_w(3);
wire_w_exp_adjustment2_add_sub_w_range505w(0) <= exp_adjustment2_add_sub_w(4);
wire_w_exp_adjustment2_add_sub_w_range508w(0) <= exp_adjustment2_add_sub_w(5);
wire_w_exp_adjustment2_add_sub_w_range511w(0) <= exp_adjustment2_add_sub_w(6);
wire_w_exp_adjustment2_add_sub_w_range535w <= exp_adjustment2_add_sub_w(7 DOWNTO 0);
wire_w_exp_adjustment2_add_sub_w_range514w(0) <= exp_adjustment2_add_sub_w(7);
wire_w_exp_adjustment2_add_sub_w_range489w(0) <= exp_adjustment2_add_sub_w(8);
wire_w_exp_amb_w_range275w <= exp_amb_w(7 DOWNTO 0);
wire_w_exp_b_all_one_w_range9w(0) <= exp_b_all_one_w(0);
wire_w_exp_b_all_one_w_range26w(0) <= exp_b_all_one_w(1);
wire_w_exp_b_all_one_w_range36w(0) <= exp_b_all_one_w(2);
wire_w_exp_b_all_one_w_range46w(0) <= exp_b_all_one_w(3);
wire_w_exp_b_all_one_w_range56w(0) <= exp_b_all_one_w(4);
wire_w_exp_b_all_one_w_range66w(0) <= exp_b_all_one_w(5);
wire_w_exp_b_all_one_w_range76w(0) <= exp_b_all_one_w(6);
wire_w_exp_b_all_one_w_range86w(0) <= exp_b_all_one_w(7);
wire_w_exp_b_not_zero_w_range5w(0) <= exp_b_not_zero_w(0);
wire_w_exp_b_not_zero_w_range22w(0) <= exp_b_not_zero_w(1);
wire_w_exp_b_not_zero_w_range32w(0) <= exp_b_not_zero_w(2);
wire_w_exp_b_not_zero_w_range42w(0) <= exp_b_not_zero_w(3);
wire_w_exp_b_not_zero_w_range52w(0) <= exp_b_not_zero_w(4);
wire_w_exp_b_not_zero_w_range62w(0) <= exp_b_not_zero_w(5);
wire_w_exp_b_not_zero_w_range72w(0) <= exp_b_not_zero_w(6);
wire_w_exp_bma_w_range273w <= exp_bma_w(7 DOWNTO 0);
wire_w_exp_diff_abs_exceed_max_w_range283w(0) <= exp_diff_abs_exceed_max_w(0);
wire_w_exp_diff_abs_exceed_max_w_range287w(0) <= exp_diff_abs_exceed_max_w(1);
wire_w_exp_diff_abs_exceed_max_w_range290w(0) <= exp_diff_abs_exceed_max_w(2);
wire_w_exp_diff_abs_w_range291w <= exp_diff_abs_w(4 DOWNTO 0);
wire_w_exp_diff_abs_w_range285w(0) <= exp_diff_abs_w(6);
wire_w_exp_diff_abs_w_range288w(0) <= exp_diff_abs_w(7);
wire_w_exp_res_max_w_range518w(0) <= exp_res_max_w(0);
wire_w_exp_res_max_w_range521w(0) <= exp_res_max_w(1);
wire_w_exp_res_max_w_range523w(0) <= exp_res_max_w(2);
wire_w_exp_res_max_w_range525w(0) <= exp_res_max_w(3);
wire_w_exp_res_max_w_range527w(0) <= exp_res_max_w(4);
wire_w_exp_res_max_w_range529w(0) <= exp_res_max_w(5);
wire_w_exp_res_max_w_range531w(0) <= exp_res_max_w(6);
wire_w_exp_res_max_w_range533w(0) <= exp_res_max_w(7);
wire_w_exp_res_not_zero_w_range494w(0) <= exp_res_not_zero_w(0);
wire_w_exp_res_not_zero_w_range498w(0) <= exp_res_not_zero_w(1);
wire_w_exp_res_not_zero_w_range501w(0) <= exp_res_not_zero_w(2);
wire_w_exp_res_not_zero_w_range504w(0) <= exp_res_not_zero_w(3);
wire_w_exp_res_not_zero_w_range507w(0) <= exp_res_not_zero_w(4);
wire_w_exp_res_not_zero_w_range510w(0) <= exp_res_not_zero_w(5);
wire_w_exp_res_not_zero_w_range513w(0) <= exp_res_not_zero_w(6);
wire_w_exp_res_not_zero_w_range516w(0) <= exp_res_not_zero_w(7);
wire_w_exp_rounded_res_max_w_range568w(0) <= exp_rounded_res_max_w(0);
wire_w_exp_rounded_res_max_w_range572w(0) <= exp_rounded_res_max_w(1);
wire_w_exp_rounded_res_max_w_range575w(0) <= exp_rounded_res_max_w(2);
wire_w_exp_rounded_res_max_w_range578w(0) <= exp_rounded_res_max_w(3);
wire_w_exp_rounded_res_max_w_range581w(0) <= exp_rounded_res_max_w(4);
wire_w_exp_rounded_res_max_w_range584w(0) <= exp_rounded_res_max_w(5);
wire_w_exp_rounded_res_max_w_range587w(0) <= exp_rounded_res_max_w(6);
wire_w_exp_rounded_res_w_range570w(0) <= exp_rounded_res_w(1);
wire_w_exp_rounded_res_w_range573w(0) <= exp_rounded_res_w(2);
wire_w_exp_rounded_res_w_range576w(0) <= exp_rounded_res_w(3);
wire_w_exp_rounded_res_w_range579w(0) <= exp_rounded_res_w(4);
wire_w_exp_rounded_res_w_range582w(0) <= exp_rounded_res_w(5);
wire_w_exp_rounded_res_w_range585w(0) <= exp_rounded_res_w(6);
wire_w_exp_rounded_res_w_range588w(0) <= exp_rounded_res_w(7);
wire_w_man_a_not_zero_w_range12w(0) <= man_a_not_zero_w(0);
wire_w_man_a_not_zero_w_range143w(0) <= man_a_not_zero_w(10);
wire_w_man_a_not_zero_w_range149w(0) <= man_a_not_zero_w(11);
wire_w_man_a_not_zero_w_range155w(0) <= man_a_not_zero_w(12);
wire_w_man_a_not_zero_w_range161w(0) <= man_a_not_zero_w(13);
wire_w_man_a_not_zero_w_range167w(0) <= man_a_not_zero_w(14);
wire_w_man_a_not_zero_w_range173w(0) <= man_a_not_zero_w(15);
wire_w_man_a_not_zero_w_range179w(0) <= man_a_not_zero_w(16);
wire_w_man_a_not_zero_w_range185w(0) <= man_a_not_zero_w(17);
wire_w_man_a_not_zero_w_range191w(0) <= man_a_not_zero_w(18);
wire_w_man_a_not_zero_w_range197w(0) <= man_a_not_zero_w(19);
wire_w_man_a_not_zero_w_range89w(0) <= man_a_not_zero_w(1);
wire_w_man_a_not_zero_w_range203w(0) <= man_a_not_zero_w(20);
wire_w_man_a_not_zero_w_range209w(0) <= man_a_not_zero_w(21);
wire_w_man_a_not_zero_w_range215w(0) <= man_a_not_zero_w(22);
wire_w_man_a_not_zero_w_range95w(0) <= man_a_not_zero_w(2);
wire_w_man_a_not_zero_w_range101w(0) <= man_a_not_zero_w(3);
wire_w_man_a_not_zero_w_range107w(0) <= man_a_not_zero_w(4);
wire_w_man_a_not_zero_w_range113w(0) <= man_a_not_zero_w(5);
wire_w_man_a_not_zero_w_range119w(0) <= man_a_not_zero_w(6);
wire_w_man_a_not_zero_w_range125w(0) <= man_a_not_zero_w(7);
wire_w_man_a_not_zero_w_range131w(0) <= man_a_not_zero_w(8);
wire_w_man_a_not_zero_w_range137w(0) <= man_a_not_zero_w(9);
wire_w_man_add_sub_res_mag_dffe21_wo_range421w(0) <= man_add_sub_res_mag_dffe21_wo(10);
wire_w_man_add_sub_res_mag_dffe21_wo_range424w(0) <= man_add_sub_res_mag_dffe21_wo(11);
wire_w_man_add_sub_res_mag_dffe21_wo_range427w(0) <= man_add_sub_res_mag_dffe21_wo(12);
wire_w_man_add_sub_res_mag_dffe21_wo_range430w(0) <= man_add_sub_res_mag_dffe21_wo(13);
wire_w_man_add_sub_res_mag_dffe21_wo_range433w(0) <= man_add_sub_res_mag_dffe21_wo(14);
wire_w_man_add_sub_res_mag_dffe21_wo_range436w(0) <= man_add_sub_res_mag_dffe21_wo(15);
wire_w_man_add_sub_res_mag_dffe21_wo_range439w(0) <= man_add_sub_res_mag_dffe21_wo(16);
wire_w_man_add_sub_res_mag_dffe21_wo_range442w(0) <= man_add_sub_res_mag_dffe21_wo(17);
wire_w_man_add_sub_res_mag_dffe21_wo_range445w(0) <= man_add_sub_res_mag_dffe21_wo(18);
wire_w_man_add_sub_res_mag_dffe21_wo_range448w(0) <= man_add_sub_res_mag_dffe21_wo(19);
wire_w_man_add_sub_res_mag_dffe21_wo_range451w(0) <= man_add_sub_res_mag_dffe21_wo(20);
wire_w_man_add_sub_res_mag_dffe21_wo_range454w(0) <= man_add_sub_res_mag_dffe21_wo(21);
wire_w_man_add_sub_res_mag_dffe21_wo_range457w(0) <= man_add_sub_res_mag_dffe21_wo(22);
wire_w_man_add_sub_res_mag_dffe21_wo_range460w(0) <= man_add_sub_res_mag_dffe21_wo(23);
wire_w_man_add_sub_res_mag_dffe21_wo_range463w(0) <= man_add_sub_res_mag_dffe21_wo(24);
wire_w_man_add_sub_res_mag_dffe21_wo_range466w(0) <= man_add_sub_res_mag_dffe21_wo(25);
wire_w_man_add_sub_res_mag_dffe21_wo_range397w(0) <= man_add_sub_res_mag_dffe21_wo(2);
wire_w_man_add_sub_res_mag_dffe21_wo_range400w(0) <= man_add_sub_res_mag_dffe21_wo(3);
wire_w_man_add_sub_res_mag_dffe21_wo_range403w(0) <= man_add_sub_res_mag_dffe21_wo(4);
wire_w_man_add_sub_res_mag_dffe21_wo_range406w(0) <= man_add_sub_res_mag_dffe21_wo(5);
wire_w_man_add_sub_res_mag_dffe21_wo_range409w(0) <= man_add_sub_res_mag_dffe21_wo(6);
wire_w_man_add_sub_res_mag_dffe21_wo_range412w(0) <= man_add_sub_res_mag_dffe21_wo(7);
wire_w_man_add_sub_res_mag_dffe21_wo_range415w(0) <= man_add_sub_res_mag_dffe21_wo(8);
wire_w_man_add_sub_res_mag_dffe21_wo_range418w(0) <= man_add_sub_res_mag_dffe21_wo(9);
wire_w_man_add_sub_res_mag_dffe27_wo_range374w(0) <= man_add_sub_res_mag_dffe27_wo(0);
wire_w_man_add_sub_res_mag_dffe27_wo_range389w <= man_add_sub_res_mag_dffe27_wo(25 DOWNTO 0);
wire_w_man_add_sub_res_mag_dffe27_wo_range365w(0) <= man_add_sub_res_mag_dffe27_wo(25);
wire_w_man_add_sub_res_mag_dffe27_wo_range391w <= man_add_sub_res_mag_dffe27_wo(26 DOWNTO 1);
wire_w_man_add_sub_res_mag_dffe27_wo_range359w(0) <= man_add_sub_res_mag_dffe27_wo(26);
wire_w_man_add_sub_w_range350w(0) <= man_add_sub_w(27);
wire_w_man_b_not_zero_w_range15w(0) <= man_b_not_zero_w(0);
wire_w_man_b_not_zero_w_range146w(0) <= man_b_not_zero_w(10);
wire_w_man_b_not_zero_w_range152w(0) <= man_b_not_zero_w(11);
wire_w_man_b_not_zero_w_range158w(0) <= man_b_not_zero_w(12);
wire_w_man_b_not_zero_w_range164w(0) <= man_b_not_zero_w(13);
wire_w_man_b_not_zero_w_range170w(0) <= man_b_not_zero_w(14);
wire_w_man_b_not_zero_w_range176w(0) <= man_b_not_zero_w(15);
wire_w_man_b_not_zero_w_range182w(0) <= man_b_not_zero_w(16);
wire_w_man_b_not_zero_w_range188w(0) <= man_b_not_zero_w(17);
wire_w_man_b_not_zero_w_range194w(0) <= man_b_not_zero_w(18);
wire_w_man_b_not_zero_w_range200w(0) <= man_b_not_zero_w(19);
wire_w_man_b_not_zero_w_range92w(0) <= man_b_not_zero_w(1);
wire_w_man_b_not_zero_w_range206w(0) <= man_b_not_zero_w(20);
wire_w_man_b_not_zero_w_range212w(0) <= man_b_not_zero_w(21);
wire_w_man_b_not_zero_w_range218w(0) <= man_b_not_zero_w(22);
wire_w_man_b_not_zero_w_range98w(0) <= man_b_not_zero_w(2);
wire_w_man_b_not_zero_w_range104w(0) <= man_b_not_zero_w(3);
wire_w_man_b_not_zero_w_range110w(0) <= man_b_not_zero_w(4);
wire_w_man_b_not_zero_w_range116w(0) <= man_b_not_zero_w(5);
wire_w_man_b_not_zero_w_range122w(0) <= man_b_not_zero_w(6);
wire_w_man_b_not_zero_w_range128w(0) <= man_b_not_zero_w(7);
wire_w_man_b_not_zero_w_range134w(0) <= man_b_not_zero_w(8);
wire_w_man_b_not_zero_w_range140w(0) <= man_b_not_zero_w(9);
wire_w_man_res_not_zero_w2_range395w(0) <= man_res_not_zero_w2(0);
wire_w_man_res_not_zero_w2_range426w(0) <= man_res_not_zero_w2(10);
wire_w_man_res_not_zero_w2_range429w(0) <= man_res_not_zero_w2(11);
wire_w_man_res_not_zero_w2_range432w(0) <= man_res_not_zero_w2(12);
wire_w_man_res_not_zero_w2_range435w(0) <= man_res_not_zero_w2(13);
wire_w_man_res_not_zero_w2_range438w(0) <= man_res_not_zero_w2(14);
wire_w_man_res_not_zero_w2_range441w(0) <= man_res_not_zero_w2(15);
wire_w_man_res_not_zero_w2_range444w(0) <= man_res_not_zero_w2(16);
wire_w_man_res_not_zero_w2_range447w(0) <= man_res_not_zero_w2(17);
wire_w_man_res_not_zero_w2_range450w(0) <= man_res_not_zero_w2(18);
wire_w_man_res_not_zero_w2_range453w(0) <= man_res_not_zero_w2(19);
wire_w_man_res_not_zero_w2_range399w(0) <= man_res_not_zero_w2(1);
wire_w_man_res_not_zero_w2_range456w(0) <= man_res_not_zero_w2(20);
wire_w_man_res_not_zero_w2_range459w(0) <= man_res_not_zero_w2(21);
wire_w_man_res_not_zero_w2_range462w(0) <= man_res_not_zero_w2(22);
wire_w_man_res_not_zero_w2_range465w(0) <= man_res_not_zero_w2(23);
wire_w_man_res_not_zero_w2_range402w(0) <= man_res_not_zero_w2(2);
wire_w_man_res_not_zero_w2_range405w(0) <= man_res_not_zero_w2(3);
wire_w_man_res_not_zero_w2_range408w(0) <= man_res_not_zero_w2(4);
wire_w_man_res_not_zero_w2_range411w(0) <= man_res_not_zero_w2(5);
wire_w_man_res_not_zero_w2_range414w(0) <= man_res_not_zero_w2(6);
wire_w_man_res_not_zero_w2_range417w(0) <= man_res_not_zero_w2(7);
wire_w_man_res_not_zero_w2_range420w(0) <= man_res_not_zero_w2(8);
wire_w_man_res_not_zero_w2_range423w(0) <= man_res_not_zero_w2(9);
wire_w_man_res_rounding_add_sub_w_range551w <= man_res_rounding_add_sub_w(22 DOWNTO 0);
wire_w_man_res_rounding_add_sub_w_range555w <= man_res_rounding_add_sub_w(23 DOWNTO 1);
wire_w_man_res_rounding_add_sub_w_range552w(0) <= man_res_rounding_add_sub_w(24);
lbarrel_shift : add_flt_stratix5_area_altbarrel_shift_oud
PORT MAP (
aclr => aclr,
clk_en => clk_en,
clock => clock,
data => man_dffe31_wo,
distance => man_leading_zeros_cnt_w,
result => wire_lbarrel_shift_result
);
wire_rbarrel_shift_data <= ( man_smaller_dffe13_wo & "00");
rbarrel_shift : add_flt_stratix5_area_altbarrel_shift_u1g
PORT MAP (
aclr => aclr,
clk_en => clk_en,
clock => clock,
data => wire_rbarrel_shift_data,
distance => rshift_distance_dffe13_wo,
result => wire_rbarrel_shift_result
);
wire_leading_zeroes_cnt_data <= ( man_add_sub_res_mag_dffe21_wo(25 DOWNTO 1) & "1" & "000000");
leading_zeroes_cnt : add_flt_stratix5_area_altpriority_encoder_ou8
PORT MAP (
aclr => aclr,
clk_en => clk_en,
clock => clock,
data => wire_leading_zeroes_cnt_data,
q => wire_leading_zeroes_cnt_q
);
wire_trailing_zeros_cnt_data <= ( "111111111" & man_smaller_dffe13_wo(22 DOWNTO 0));
trailing_zeros_cnt : add_flt_stratix5_area_altpriority_encoder_dna
PORT MAP (
aclr => aclr,
clk_en => clk_en,
clock => clock,
data => wire_trailing_zeros_cnt_data,
q => wire_trailing_zeros_cnt_q
);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_exp_dffe12 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_exp_dffe12 <= aligned_dataa_exp_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_exp_dffe13 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_exp_dffe13 <= aligned_dataa_exp_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_exp_dffe14 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_exp_dffe14 <= aligned_dataa_exp_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_exp_dffe15 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_exp_dffe15 <= aligned_dataa_exp_dffe15_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_man_dffe12 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_man_dffe12 <= aligned_dataa_man_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_man_dffe13 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_man_dffe13 <= aligned_dataa_man_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_man_dffe14 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_man_dffe14 <= aligned_dataa_man_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_man_dffe15 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_man_dffe15 <= aligned_dataa_man_dffe15_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_sign_dffe12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_sign_dffe12 <= aligned_dataa_sign_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_sign_dffe13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_sign_dffe13 <= aligned_dataa_sign_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_sign_dffe14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_sign_dffe14 <= aligned_dataa_sign_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_sign_dffe15 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_sign_dffe15 <= aligned_dataa_sign_dffe15_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_exp_dffe12 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_exp_dffe12 <= aligned_datab_exp_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_exp_dffe13 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_exp_dffe13 <= aligned_datab_exp_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_exp_dffe14 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_exp_dffe14 <= aligned_datab_exp_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_exp_dffe15 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_exp_dffe15 <= aligned_datab_exp_dffe15_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_man_dffe12 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_man_dffe12 <= aligned_datab_man_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_man_dffe13 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_man_dffe13 <= aligned_datab_man_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_man_dffe14 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_man_dffe14 <= aligned_datab_man_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_man_dffe15 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_man_dffe15 <= aligned_datab_man_dffe15_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_sign_dffe12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_sign_dffe12 <= aligned_datab_sign_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_sign_dffe13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_sign_dffe13 <= aligned_datab_sign_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_sign_dffe14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_sign_dffe14 <= aligned_datab_sign_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_sign_dffe15 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_sign_dffe15 <= aligned_datab_sign_dffe15_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN both_inputs_are_infinite_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN both_inputs_are_infinite_dffe1 <= both_inputs_are_infinite_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN data_exp_dffe1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN data_exp_dffe1 <= data_exp_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN dataa_man_dffe1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN dataa_man_dffe1 <= dataa_man_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN dataa_sign_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN dataa_sign_dffe1 <= dataa_sign_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN datab_man_dffe1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN datab_man_dffe1 <= datab_man_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN datab_sign_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN datab_sign_dffe1 <= datab_sign_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN denormal_res_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN denormal_res_dffe3 <= denormal_res_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN denormal_res_dffe32 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN denormal_res_dffe32 <= denormal_res_dffe32_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN denormal_res_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN denormal_res_dffe4 <= denormal_res_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN denormal_res_dffe41 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN denormal_res_dffe41 <= denormal_res_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_adj_dffe21 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_adj_dffe21 <= exp_adj_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_adj_dffe23 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_adj_dffe23 <= exp_adj_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_amb_mux_dffe13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_amb_mux_dffe13 <= exp_amb_mux_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_amb_mux_dffe14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_amb_mux_dffe14 <= exp_amb_mux_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_amb_mux_dffe15 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_amb_mux_dffe15 <= exp_amb_mux_dffe15_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_intermediate_res_dffe41 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_intermediate_res_dffe41 <= exp_intermediate_res_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_out_dffe5 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_out_dffe5 <= exp_out_dffe5_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe2 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe2 <= exp_res_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe21 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe21 <= exp_res_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe23 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe23 <= exp_res_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe3 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe3 <= exp_res_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe32 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe32 <= exp_res_dffe32_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe4 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe4 <= exp_res_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe1 <= infinite_output_sign_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe2 <= infinite_output_sign_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe21 <= infinite_output_sign_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe23 <= infinite_output_sign_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe3 <= infinite_output_sign_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe31 <= infinite_output_sign_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe32 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe32 <= infinite_output_sign_dffe32_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe4 <= infinite_output_sign_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe41 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe41 <= infinite_output_sign_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_res_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_res_dffe3 <= infinite_res_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_res_dffe32 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_res_dffe32 <= infinite_res_dff32_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_res_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_res_dffe4 <= infinite_res_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_res_dffe41 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_res_dffe41 <= infinite_res_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe2 <= infinity_magnitude_sub_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe21 <= infinity_magnitude_sub_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe23 <= infinity_magnitude_sub_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe3 <= infinity_magnitude_sub_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe31 <= infinity_magnitude_sub_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe32 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe32 <= infinity_magnitude_sub_dffe32_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe4 <= infinity_magnitude_sub_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe41 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe41 <= infinity_magnitude_sub_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_dataa_infinite_dffe12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_dataa_infinite_dffe12 <= input_dataa_infinite_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_dataa_infinite_dffe13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_dataa_infinite_dffe13 <= input_dataa_infinite_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_dataa_infinite_dffe14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_dataa_infinite_dffe14 <= input_dataa_infinite_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_dataa_infinite_dffe15 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_dataa_infinite_dffe15 <= input_dataa_infinite_dffe15_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_dataa_nan_dffe12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_dataa_nan_dffe12 <= input_dataa_nan_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_datab_infinite_dffe12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_datab_infinite_dffe12 <= input_datab_infinite_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_datab_infinite_dffe13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_datab_infinite_dffe13 <= input_datab_infinite_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_datab_infinite_dffe14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_datab_infinite_dffe14 <= input_datab_infinite_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_datab_infinite_dffe15 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_datab_infinite_dffe15 <= input_datab_infinite_dffe15_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_datab_nan_dffe12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_datab_nan_dffe12 <= input_datab_nan_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe1 <= input_is_infinite_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe2 <= input_is_infinite_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe21 <= input_is_infinite_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe23 <= input_is_infinite_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe3 <= input_is_infinite_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe31 <= input_is_infinite_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe32 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe32 <= input_is_infinite_dffe32_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe4 <= input_is_infinite_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe41 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe41 <= input_is_infinite_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe1 <= input_is_nan_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe13 <= input_is_nan_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe14 <= input_is_nan_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe15 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe15 <= input_is_nan_dffe15_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe2 <= input_is_nan_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe21 <= input_is_nan_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe23 <= input_is_nan_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe3 <= input_is_nan_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe31 <= input_is_nan_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe32 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe32 <= input_is_nan_dffe32_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe4 <= input_is_nan_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe41 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe41 <= input_is_nan_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_add_sub_res_mag_dffe21 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_add_sub_res_mag_dffe21 <= man_add_sub_res_mag_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_add_sub_res_mag_dffe23 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_add_sub_res_mag_dffe23 <= man_add_sub_res_mag_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_add_sub_res_sign_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_add_sub_res_sign_dffe21 <= man_add_sub_res_sign_dffe27_wo;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_add_sub_res_sign_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_add_sub_res_sign_dffe23 <= man_add_sub_res_sign_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_dffe31 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_dffe31 <= man_add_sub_res_mag_dffe26_wo;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_leading_zeros_dffe31 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_leading_zeros_dffe31 <= man_leading_zeros_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_out_dffe5 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_out_dffe5 <= man_out_dffe5_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_dffe4 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_dffe4 <= man_res_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_is_not_zero_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_is_not_zero_dffe3 <= man_res_is_not_zero_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_is_not_zero_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_is_not_zero_dffe31 <= man_res_is_not_zero_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_is_not_zero_dffe32 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_is_not_zero_dffe32 <= man_res_is_not_zero_dffe32_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_is_not_zero_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_is_not_zero_dffe4 <= man_res_is_not_zero_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_is_not_zero_dffe41 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_is_not_zero_dffe41 <= man_res_is_not_zero_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_not_zero_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_not_zero_dffe23 <= man_res_not_zero_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_smaller_dffe13 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_smaller_dffe13 <= man_smaller_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN need_complement_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN need_complement_dffe2 <= need_complement_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN round_bit_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN round_bit_dffe21 <= round_bit_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN round_bit_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN round_bit_dffe23 <= round_bit_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN round_bit_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN round_bit_dffe3 <= round_bit_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN round_bit_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN round_bit_dffe31 <= round_bit_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN round_bit_dffe32 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN round_bit_dffe32 <= round_bit_dffe32_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN rounded_res_infinity_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN rounded_res_infinity_dffe4 <= rounded_res_infinity_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN rshift_distance_dffe13 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN rshift_distance_dffe13 <= rshift_distance_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN rshift_distance_dffe14 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN rshift_distance_dffe14 <= rshift_distance_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN rshift_distance_dffe15 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN rshift_distance_dffe15 <= rshift_distance_dffe15_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe31 <= sign_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe32 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe32 <= sign_dffe32_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_out_dffe5 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_out_dffe5 <= sign_out_dffe5_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_res_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_res_dffe3 <= sign_res_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_res_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_res_dffe4 <= sign_res_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_res_dffe41 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_res_dffe41 <= sign_res_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe1 <= sticky_bit_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe2 <= sticky_bit_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe21 <= sticky_bit_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe23 <= sticky_bit_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe3 <= sticky_bit_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe31 <= sticky_bit_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe32 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe32 <= sticky_bit_dffe32_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN zero_man_sign_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN zero_man_sign_dffe2 <= zero_man_sign_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN zero_man_sign_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN zero_man_sign_dffe21 <= zero_man_sign_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN zero_man_sign_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN zero_man_sign_dffe23 <= zero_man_sign_dffe23_wi;
END IF;
END IF;
END PROCESS;
add_sub1 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => aligned_dataa_exp_w,
datab => aligned_datab_exp_w,
result => wire_add_sub1_result
);
add_sub2 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => aligned_datab_exp_w,
datab => aligned_dataa_exp_w,
result => wire_add_sub2_result
);
add_sub3 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 6
)
PORT MAP (
dataa => sticky_bit_cnt_dataa_w,
datab => sticky_bit_cnt_datab_w,
result => wire_add_sub3_result
);
add_sub4 : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 28
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => borrow_w,
clken => clk_en,
clock => clock,
dataa => man_add_sub_dataa_w,
datab => man_add_sub_datab_w,
result => wire_add_sub4_result
);
add_sub5 : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 28
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => borrow_w,
clken => clk_en,
clock => clock,
dataa => man_2comp_res_dataa_w,
datab => man_2comp_res_datab_w,
result => wire_add_sub5_result
);
add_sub6 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9
)
PORT MAP (
dataa => exp_adjustment_add_sub_dataa_w,
datab => exp_adjustment_add_sub_datab_w,
result => wire_add_sub6_result
);
add_sub7 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => exp_adjustment2_add_sub_dataa_w,
datab => exp_adjustment2_add_sub_datab_w,
result => wire_add_sub7_result
);
add_sub8 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 26
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => man_intermediate_res_w,
datab => man_res_rounding_add_sub_datab_w,
result => wire_add_sub8_result
);
add_sub9 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9
)
PORT MAP (
dataa => exp_res_rounding_adder_dataa_w,
datab => exp_rounding_adjustment_w,
result => wire_add_sub9_result
);
trailing_zeros_limit_comparator : lpm_compare
GENERIC MAP (
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 6
)
PORT MAP (
agb => wire_trailing_zeros_limit_comparator_agb,
dataa => sticky_bit_cnt_res_w,
datab => trailing_zeros_limit_w
);
END RTL; --add_flt_stratix5_area_altfp_add_sub_rgj
--VALID FILE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_area IS
PORT
(
clk_en : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END add_flt_stratix5_area;
ARCHITECTURE RTL OF add_flt_stratix5_area IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT add_flt_stratix5_area_altfp_add_sub_rgj
PORT (
clk_en : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(31 DOWNTO 0);
add_flt_stratix5_area_altfp_add_sub_rgj_component : add_flt_stratix5_area_altfp_add_sub_rgj
PORT MAP (
clk_en => clk_en,
clock => clock,
datab => datab,
dataa => dataa,
result => sub_wire0
);
END RTL;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: FPM_FORMAT NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix V"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: WIDTH_DATA NUMERIC "32"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: DENORMAL_SUPPORT STRING "NO"
-- Retrieval info: CONSTANT: DIRECTION STRING "ADD"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix V"
-- Retrieval info: CONSTANT: OPTIMIZE STRING "AREA"
-- Retrieval info: CONSTANT: PIPELINE NUMERIC "14"
-- Retrieval info: CONSTANT: REDUCED_FUNCTIONALITY STRING "NO"
-- Retrieval info: CONSTANT: WIDTH_EXP NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_MAN NUMERIC "23"
-- Retrieval info: USED_PORT: clk_en 0 0 0 0 INPUT NODEFVAL "clk_en"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL "dataa[31..0]"
-- Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL "datab[31..0]"
-- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
-- Retrieval info: CONNECT: @clk_en 0 0 0 0 clk_en 0 0 0 0
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
-- Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0
-- Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL add_flt_stratix5_area.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL add_flt_stratix5_area.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL add_flt_stratix5_area.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL add_flt_stratix5_area.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL add_flt_stratix5_area_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
| gpl-3.0 | 7983eee81c609a51f411a45fd80ba4c2 | 0.696632 | 2.465839 | false | false | false | false |
pwsoft/fpga_examples | rtl/general/gen_usart.vhd | 1 | 4,422 | -- -----------------------------------------------------------------------
--
-- Syntiac's generic VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2010 by Peter Wendrich ([email protected])
-- http://www.syntiac.com/?.html
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
--
-- gen_usart.vhd
--
-- -----------------------------------------------------------------------
--
-- USART - Synchronous serial receiver/transmitter
--
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- -----------------------------------------------------------------------
entity gen_usart is
generic (
bits : integer := 8
);
port (
clk : in std_logic;
d : in unsigned(bits-1 downto 0) := (others => '0');
d_trigger : in std_logic := '0';
d_empty : out std_logic;
q : out unsigned(bits-1 downto 0);
q_trigger : out std_logic;
serial_clk : in std_logic;
serial_rxd : in std_logic := '1';
serial_txd : out std_logic;
serial_cts_n : in std_logic := '0'
);
end entity;
-- -----------------------------------------------------------------------
architecture rtl of gen_usart is
type state_t is (
STATE_IDLE,
STATE_BITS,
STATE_STOP);
signal serial_clk_reg : std_logic := '0';
signal serial_clk_dly : std_logic := '0';
signal receive_state : state_t := STATE_IDLE;
signal receive_shift : unsigned(bits-1 downto 0) := (others => '0');
signal receive_cnt : integer range 0 to bits-1 := 0;
signal transmit_state : state_t := STATE_IDLE;
signal transmit_empty : std_logic := '1';
signal transmit_buffer : unsigned(bits-1 downto 0) := (others => '0');
signal transmit_shift : unsigned(bits-1 downto 0) := (others => '0');
signal transmit_cnt : integer range 0 to bits-1 := 0;
begin
d_empty <= transmit_empty and (not d_trigger);
process(clk)
begin
if rising_edge(clk) then
serial_clk_reg <= serial_clk;
serial_clk_dly <= serial_clk_reg;
end if;
end process;
receive_process: process(clk)
begin
if rising_edge(clk) then
q_trigger <= '0';
-- Detect rising edge
if (serial_clk_reg = '1') and (serial_clk_dly = '0') then
case receive_state is
when STATE_IDLE =>
receive_cnt <= 0;
if serial_rxd = '0' then
receive_state <= STATE_BITS;
end if;
when STATE_BITS =>
receive_shift <= serial_rxd & receive_shift(receive_shift'high downto 1);
if receive_cnt = bits-1 then
receive_state <= STATE_STOP;
else
receive_cnt <= receive_cnt + 1;
end if;
when STATE_STOP =>
receive_state <= STATE_IDLE;
if serial_rxd = '1' then
q <= receive_shift;
q_trigger <= '1';
end if;
end case;
end if;
end if;
end process;
transmit_process: process(clk)
begin
if rising_edge(clk) then
-- Detect falling edge
if (serial_clk_reg = '0') and (serial_clk_dly = '1') then
case transmit_state is
when STATE_IDLE =>
transmit_cnt <= 0;
if (transmit_empty = '0') and (serial_cts_n = '0') then
transmit_shift <= transmit_buffer;
transmit_empty <= '1';
transmit_state <= STATE_BITS;
serial_txd <= '0';
else
serial_txd <= '1';
end if;
when STATE_BITS =>
serial_txd <= transmit_shift(transmit_cnt);
if transmit_cnt = bits-1 then
transmit_state <= STATE_STOP;
else
transmit_cnt <= transmit_cnt + 1;
end if;
when STATE_STOP =>
serial_txd <= '1';
transmit_state <= STATE_IDLE;
end case;
end if;
if d_trigger = '1' then
transmit_buffer <= d;
transmit_empty <= '0';
end if;
end if;
end process;
end architecture;
| lgpl-2.1 | 29e42c29df5c311ec0bec64863fce7da | 0.560606 | 3.451991 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/grlib/stdlib/stdio_tb.vhd | 1 | 4,766 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--------------------------------------------------------------------------------
-- Package: StdIO
-- File: stdio.vhd
-- Author: Gaisler Research
-- Description: Package for common I/O functions
--------------------------------------------------------------------------------
library Std;
use Std.Standard.all;
use Std.TextIO.all;
library IEEE;
use IEEE.Std_Logic_1164.all;
library GRLIB;
use GRLIB.StdIO.all;
entity StdIO_TB is
end entity StdIO_TB;
architecture Behavioural of StdIO_TB is
begin
process
variable LW: Line;
variable LR: Line;
file WFile: Text;
file RFile: Text;
constant SUL: Std_ULogic := 'H';
constant SL: Std_Logic := 'L';
constant SULV1: Std_ULogic_Vector := "1";
constant SULV2: Std_ULogic_Vector := "10";
constant SULV3: Std_ULogic_Vector := "011";
constant SULV4: Std_ULogic_Vector := "0100";
constant SULV5: Std_ULogic_Vector := "00101";
constant SULV6: Std_ULogic_Vector := "000110";
constant SULV7: Std_ULogic_Vector := "0000111";
constant SULV8: Std_ULogic_Vector := "00001000";
constant SULV9: Std_ULogic_Vector := "000001001";
constant SULVA: Std_ULogic_Vector := "00000001001000110100010101100111";
constant SULVB: Std_ULogic_Vector := "10001001101010111100110111101111";
variable SULVC: Std_ULogic_Vector(0 to 3);
variable SULVD: Std_ULogic_Vector(0 to 7);
variable SULVE: Std_ULogic_Vector(0 to 15);
variable SULVF: Std_ULogic_Vector(0 to 16);
constant SLVA: Std_Logic_Vector := "00000001001000110100010101100111";
constant SLVB: Std_Logic_Vector := "10001001101010111100110111101111";
variable SLVC: Std_Logic_Vector(0 to 7);
variable SLVD: Std_Logic_Vector(0 to 15);
begin
Write(LW, SUL);
WriteLine(Output, LW);
Write(LW, SL);
WriteLine(Output, LW);
HWrite(LW, SULV1);
WriteLine(Output, LW);
HWrite(LW, SULV2);
WriteLine(Output, LW);
HWrite(LW, SULV3);
WriteLine(Output, LW);
HWrite(LW, SULV4);
WriteLine(Output, LW);
HWrite(LW, SULV5);
WriteLine(Output, LW);
HWrite(LW, SULV6);
WriteLine(Output, LW);
HWrite(LW, SULV7);
WriteLine(Output, LW);
HWrite(LW, SULV8);
WriteLine(Output, LW);
HWrite(LW, SULV9);
WriteLine(Output, LW);
HWrite(LW, SULVA);
WriteLine(Output, LW);
HWrite(LW, SULVB);
WriteLine(Output, LW);
File_Open(WFile, "file.txt", Write_Mode);
HWrite(LW, SULVA);
WriteLine(WFile, LW);
HWrite(LW, SULVB);
WriteLine(WFile, LW);
HWrite(LW, SULVA);
WriteLine(WFile, LW);
HWrite(LW, SULVB);
WriteLine(WFile, LW);
HWrite(LW, SLVA);
WriteLine(WFile, LW);
HWrite(LW, SLVB);
WriteLine(WFile, LW);
File_Close(WFile);
File_Open(RFile, "file.txt", Read_Mode);
ReadLine(RFile, LR);
HRead(LR, SULVC);
HWrite(LW, SULVC);
WriteLine(Output, LW);
ReadLine(RFile, LR);
HRead(LR, SULVD);
HWrite(LW, SULVD);
WriteLine(Output, LW);
ReadLine(RFile, LR);
HRead(LR, SULVE);
HWrite(LW, SULVE);
WriteLine(Output, LW);
ReadLine(RFile, LR);
HRead(LR, SULVF);
HWrite(LW, SULVF);
WriteLine(Output, LW);
ReadLine(RFile, LR);
HRead(LR, SLVC);
HWrite(LW, SLVC);
WriteLine(Output, LW);
ReadLine(RFile, LR);
HRead(LR, SLVD);
HWrite(LW, SLVD);
WriteLine(Output, LW);
File_Close(RFile);
wait;
end process;
end architecture Behavioural;
| gpl-3.0 | 30cd1d535a8c4c8b5fec75823d83589c | 0.582669 | 3.843548 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-avnet-eval-xc4vlx60/leon3mp.vhd | 1 | 27,385 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2006 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.net.all;
use gaisler.jtag.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
use work.avnet_eval.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
ddrfreq : integer := 100000 -- frequency of ddr clock in kHz
);
port (
resetn : in std_ulogic;
resoutn : out std_logic;
clk_100mhz : in std_ulogic;
clk_50mhz : in std_ulogic;
clk_200p : in std_ulogic;
clk_200n : in std_ulogic;
errorn : out std_ulogic;
-- prom interface
address : out std_logic_vector(21 downto 0);
data : inout std_logic_vector(15 downto 0);
romsn : out std_ulogic;
oen : out std_ulogic;
writen : out std_ulogic;
romrstn : out std_ulogic;
-- pragma translate_off
iosn : out std_ulogic;
testdata : inout std_logic_vector(15 downto 0);
-- pragma translate_on
-- ddr memory
ddr_clk0 : out std_logic;
ddr_clk0b : out std_logic;
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke0 : out std_logic;
ddr_cs0b : out std_logic;
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (12 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (15 downto 0); -- ddr data
-- debug support unit
dsuen : in std_ulogic;
dsubre : in std_ulogic;
dsuact : out std_ulogic;
-- UART for serial DCL/console I/O
serrx : in std_ulogic;
sertx : out std_ulogic;
rtsn : out std_ulogic;
ctsn : in std_ulogic;
led_rx : out std_ulogic;
led_tx : out std_ulogic;
-- ethernet signals
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
emdc : out std_ulogic;
erstn : out std_ulogic;
-- OLED display signals
disp_dcn : out std_ulogic;
disp_csn : out std_ulogic;
disp_rdn : out std_ulogic;
disp_wrn : out std_ulogic;
disp_d : inout std_logic_vector(7 downto 0);
phy_done : out std_ulogic;
rst_done : out std_ulogic
);
end;
architecture rtl of leon3mp is
component mig_36_1
port(
cntrl0_ddr_dq : inout std_logic_vector(15 downto 0);
cntrl0_ddr_a : out std_logic_vector(12 downto 0);
cntrl0_ddr_ba : out std_logic_vector(1 downto 0);
cntrl0_ddr_cke : out std_logic;
cntrl0_ddr_cs_n : out std_logic;
cntrl0_ddr_ras_n : out std_logic;
cntrl0_ddr_cas_n : out std_logic;
cntrl0_ddr_we_n : out std_logic;
cntrl0_ddr_dm : out std_logic_vector(1 downto 0);
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
clk200_p : in std_logic;
clk200_n : in std_logic;
init_done : out std_logic;
sys_reset_in_n : in std_logic;
cntrl0_clk_tb : out std_logic;
cntrl0_reset_tb : out std_logic;
cntrl0_wdf_almost_full : out std_logic;
cntrl0_af_almost_full : out std_logic;
cntrl0_read_data_valid : out std_logic;
cntrl0_app_wdf_wren : in std_logic;
cntrl0_app_af_wren : in std_logic;
cntrl0_burst_length_div2 : out std_logic_vector(2 downto 0);
cntrl0_app_af_addr : in std_logic_vector(35 downto 0);
cntrl0_app_wdf_data : in std_logic_vector(31 downto 0);
cntrl0_read_data_fifo_out : out std_logic_vector(31 downto 0);
cntrl0_app_mask_data : in std_logic_vector(3 downto 0);
cntrl0_ddr_dqs : inout std_logic_vector(1 downto 0);
cntrl0_ddr_ck : out std_logic_vector(0 downto 0);
cntrl0_ddr_ck_n : out std_logic_vector(0 downto 0)
);
end component;
constant blength : integer := 12;
constant fifodepth : integer := 8;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdctrl_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal lclk : std_ulogic;
signal ddrclk, ddrrst, ddrclkfb : std_ulogic;
signal clkm, rstn, clkml, clk2x : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal tck, tms, tdi, tdo : std_ulogic;
signal fpi : grfpu_in_vector_type;
signal fpo : grfpu_out_vector_type;
-- signal dsubre : std_logic;
signal duart, ldsuen : std_logic;
signal rsertx, rserrx, rdsuen : std_logic;
signal rstraw : std_logic;
signal rstneg : std_logic;
signal rxd1 : std_logic;
signal txd1 : std_logic;
signal lock : std_logic;
signal lclk50 : std_logic;
signal rst0_tb, rst0_tbn, clk0_tb : std_logic;
signal migi : mig_app_in_type;
signal migo : mig_app_out_type;
signal init_done : std_ulogic;
signal migrst : std_ulogic;
signal ddr_clk : std_logic_vector(2 downto 0);
signal ddr_clkb : std_logic_vector(2 downto 0);
signal ddr_cke : std_logic_vector(1 downto 0);
signal ddr_csb : std_logic_vector(1 downto 0);
signal ddr_adl : std_logic_vector(13 downto 0); -- ddr address
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of lock : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute keep of lock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
constant BOARD_FREQ : integer := 50000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
begin
romrstn <= rstn;
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstneg;
rstneg <= not resetn;
rst0 : rstgen port map (rstneg, clkm, lock, rstn, rstraw);
clk50_pad : clkpad generic map (tech => padtech) port map (clk_50mhz, lclk50);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, 0, 1, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk50, gnd(0), clkm, open, open, open, open, cgi, cgo);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+1,
nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
leon3gen : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
nosh : if CFG_GRFPUSH = 0 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR,
CFG_NCPU-1, CFG_DFIXED, 0, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
sh : if CFG_GRFPUSH = 1 generate
u0 : leon3sh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR,
CFG_NCPU-1, CFG_DFIXED, 0, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), fpi(i), fpo(i));
end generate;
end generate;
sh : if CFG_GRFPUSH = 1 generate
grfpush0 : grfpushwx generic map ((CFG_FPU-1), CFG_NCPU, fabtech)
port map (clkm, rstn, fpi, fpo);
end generate;
error_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
-- dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 5, pindex => 0,
paddr => 0, srbanks => 1, ramaddr => 16#600#, rammask => 16#F00#, ram16 => 1 )
port map (rstn, clkm, memi, memo, ahbsi, ahbso(5), apbi, apbo(0), wpo, open);
end generate;
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
mg0 : if (CFG_MCTRL_LEON2 = 0) generate
apbo(0) <= apb_none; ahbso(5) <= ahbs_none;
roms_pad : outpad generic map (tech => padtech)
port map (romsn, vcc(0));
end generate;
mgpads : if (CFG_MCTRL_LEON2 /= 0) generate
addr_pad : outpadv generic map (width => 22, tech => padtech)
port map (address, memo.address(22 downto 1));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
-- pragma translate_off
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
tbdr : for i in 0 to 1 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (testdata(15-i*8 downto 8-i*8), memo.data(15-i*8 downto 8-i*8),
memo.bdrive(i+2), memi.data(15-i*8 downto 8-i*8));
end generate;
-- pragma translate_on
bdr : for i in 0 to 1 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (data(15-i*8 downto 8-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
end generate;
end generate;
----------------------------------------------------------------------
--- DDR memory controller -------------------------------------------
----------------------------------------------------------------------
ddrsp0 : if (CFG_DDRSP /= 0) generate
clk_pad : clkpad generic map (tech => padtech) port map (clk_100mhz, lclk);
ddrc : ddrspa generic map ( fabtech => virtex4, memtech => memtech,
hindex => 4, haddr => 16#400#, hmask => 16#F00#, ioaddr => 1,
pwron => CFG_DDRSP_INIT, MHz => 100, rskew => -95
-- pragma translate_off
* 0 -- disable clock skew during simulation
-- pragma translate_on
, clkmul => CFG_DDRSP_FREQ/5, clkdiv => 20, col => CFG_DDRSP_COL,
Mbyte => CFG_DDRSP_SIZE, ahbfreq => CPU_FREQ/1000, ddrbits => 16)
port map (
rstneg, rstn, lclk, clkm, lock, clkml, clkml, ahbsi, ahbso(4),
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_adl, ddr_ba, ddr_dq);
ddr_clk0 <= ddr_clk(0); ddr_clk0b <= ddr_clkb(0);
ddr_cke0 <= ddr_cke(0); ddr_cs0b <= ddr_csb(0);
ddr_ad <= ddr_adl(12 downto 0);
end generate;
migsp0 : if (CFG_MIG_DDR2 = 1) generate
ahb2mig0 : entity work.ahb2mig_avnet_eval
generic map ( hindex => 0, haddr => 16#400#, hmask => 16#FE0#,
MHz => 100, Mbyte => 32)
port map (
rst_ahb => rstn, rst_ddr => rst0_tbn, rst_50 => rstneg,
clk_ahb => clkm, clk_ddr => clk0_tb, clk_50 => lclk50,
init_done => init_done, ahbsi => ahbsi, ahbso => ahbso(0), migi => migi, migo => migo);
migv5 : mig_36_1
port map(
cntrl0_ddr_dq => ddr_dq,
cntrl0_ddr_a => ddr_ad(12 downto 0),
cntrl0_ddr_ba => ddr_ba,
cntrl0_ddr_cke => ddr_cke0,
cntrl0_ddr_cs_n => ddr_cs0b,
cntrl0_ddr_ras_n => ddr_rasb,
cntrl0_ddr_cas_n => ddr_casb,
cntrl0_ddr_we_n => ddr_web,
cntrl0_ddr_dm => ddr_dm,
sys_clk_p => clk_100mhz, clk200_p => clk_200p,
sys_clk_n => clk_100mhz, clk200_n => clk_200n,
init_done => init_done,
sys_reset_in_n => migi.mig_rst,
cntrl0_reset_tb => rst0_tb, cntrl0_clk_tb => clk0_tb,
cntrl0_wdf_almost_full => migo.app_wdf_afull,
cntrl0_af_almost_full => migo.app_af_afull,
cntrl0_read_data_valid => migo.app_rd_data_valid,
cntrl0_app_wdf_wren => migi.app_wdf_wren,
cntrl0_app_af_wren => migi.app_en,
cntrl0_app_af_addr => migi.app_addr,
cntrl0_app_wdf_data => migi.app_wdf_data,
cntrl0_read_data_fifo_out => migo.app_rd_data,
cntrl0_app_mask_data => migi.app_wdf_mask,
cntrl0_ddr_dqs => ddr_dqs,
cntrl0_ddr_ck => ddr_clk(0 downto 0),
cntrl0_ddr_ck_n => ddr_clkb(0 downto 0)
);
ddr_clk0 <= ddr_clk(0); ddr_clk0b <= ddr_clkb(0);
rst0_tbn <= not rst0_tb;
-- lock <= cgo.clklock;
lock <= init_done and rst0_tbn;
-- led(7) <= init_done;
end generate;
phy_done <= init_done;
rst_done <= migi.mig_rst;
noddr : if (CFG_DDRSP + CFG_MIG_DDR2) = 0 generate lock <= '1'; end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti <= gpti_dhalt_drive(dsuo.tstop);
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
grgpio0: grgpio
generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK,
nbits => 12 --CFG_GRGPIO_WIDTH
)
port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo);
disp_csn_pad : outpad generic map (tech => padtech)
port map (disp_csn, gpioo.dout(8));
disp_dcn_pad : outpad generic map (tech => padtech)
port map (disp_dcn, gpioo.dout(9));
disp_rdn_pad : outpad generic map (tech => padtech)
port map (disp_rdn, gpioo.dout(10));
disp_wrn_pad : outpad generic map (tech => padtech)
port map (disp_wrn, gpioo.dout(11));
disp_d_pads : for i in 0 to 7 generate
pio_pad : iopad generic map (tech => padtech)
port map (disp_d(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 15, paddr => 15, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL,
phyrstadr => 3, giga => CFG_GRETH1G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), apbi => apbi,
apbo => apbo(15), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
erstn_pad : outpad generic map (tech => padtech)
port map (erstn, rstn);
end generate;
-----------------------------------------------------------------------
--- AHB DMA ----------------------------------------------------------
-----------------------------------------------------------------------
-- dma0 : ahbdma
-- generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH,
-- pindex => 12, paddr => 12, dbuf => 32)
-- port map (rstn, clkm, apbi, apbo(12), ahbmi,
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH));
--
-- at0 : ahbtrace
-- generic map ( hindex => 7, ioaddr => 16#200#, iomask => 16#E00#,
-- tech => memtech, irq => 0, kbytes => 8)
-- port map ( rstn, clkm, ahbmi, ahbsi, ahbso(7));
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 3, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ,
pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+1) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-- nap0 : for i in 9 to NAPBSLV-1-CFG_GRETH generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
resoutn <= rstn;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 MP Demonstration design for Avnet Virtex4 Eval board",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
-- use switch 1 to multiplex DSU UART and UART1
dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, ldsuen);
duart <= rdsuen when CFG_AHB_UART /= 0 else '0';
rxd1 <= txd1 when duart = '1' else rserrx;
rsertx <= duo.txd when duart = '1' else txd1;
dui.rxd <= rserrx when duart = '1' else '1';
led_rx <= not rserrx;
p1 : process(clkm)
begin
if rising_edge(clkm) then
sertx <= rsertx; rserrx <= serrx; rdsuen <= ldsuen;
rtsn <= '0';
led_tx <= not rsertx;
end if;
end process;
end rtl;
| gpl-3.0 | 83d93c2303d6ad27e7f3a6c31a152dfc | 0.541318 | 3.568078 | false | false | false | false |
kdgwill/VHDL_Framer_Example | VHDL_Framer_Example/Example2/tb_FramerTop.vhd | 1 | 4,139 | LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_unsigned.all ;
ENTITY tb_FramerTop IS
--port (
--);
END;
ARCHITECTURE structure of tb_FramerTop IS
Signal bits: integer:= 32;
Signal clk : STD_LOGIC;
Signal resetb : STD_LOGIC;
Signal sin : STD_LOGIC;
Signal sout : STD_ULOGIC;
Signal clk_div_8 : std_ulogic;
Signal decode_F628_out : std_ulogic;
Signal ram_wren : STD_LOGIC ;
Signal ram_address : STD_LOGIC_VECTOR (4 DOWNTO 0);
Signal ram_data : STD_LOGIC_VECTOR (bits-1 DOWNTO 0);
Signal ram_q : STD_LOGIC_VECTOR (bits-1 DOWNTO 0);
Signal add_data0x : STD_LOGIC_VECTOR (bits-1 DOWNTO 0);
Signal add_data1x : STD_LOGIC_VECTOR (bits-1 DOWNTO 0);
Signal add_result : STD_LOGIC_VECTOR (bits-1 DOWNTO 0);
Signal divide_denom : STD_LOGIC_VECTOR (bits-1 DOWNTO 0);
Signal divide_numer : STD_LOGIC_VECTOR (bits-1 DOWNTO 0);
Signal divide_quotient : STD_LOGIC_VECTOR (bits-1 DOWNTO 0);
Signal divide_remain : STD_LOGIC_VECTOR (bits-1 DOWNTO 0);
COMPONENT tb_Framer_generator
PORT (
clk : OUT STD_LOGIC;
ser_in : OUT STD_LOGIC;
resetb : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT Framer
PORT (
clk : in std_ulogic;
sin : in std_ulogic;
resetb : in std_ulogic;
SOUT : out std_ulogic;
clk_div_8 : out std_ulogic;
decode_F628_out : out std_ulogic
);
END COMPONENT;
Component Average
generic (
bits: integer
);
PORT (clk : in std_logic;
resetb : in std_logic;
data_sig_in : in std_ulogic;
clk_div_8 : in std_ulogic;
decode_F628_out : in std_ulogic;
ram_wren : out STD_LOGIC ;
ram_address : out STD_LOGIC_VECTOR (4 DOWNTO 0);
ram_data : out STD_LOGIC_VECTOR (bits-1 DOWNTO 0);
ram_q : in STD_LOGIC_VECTOR (bits-1 DOWNTO 0);
add_value0x : Out STD_LOGIC_VECTOR (bits-1 DOWNTO 0);
add_value1x : Out STD_LOGIC_VECTOR (bits-1 DOWNTO 0);
add_sum : In STD_LOGIC_VECTOR (bits-1 DOWNTO 0);
div_denom : Out STD_LOGIC_VECTOR (bits-1 DOWNTO 0);
div_numer : Out STD_LOGIC_VECTOR (bits-1 DOWNTO 0)
);
end Component;
Component Ram IS
PORT
(
address : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (bits-1 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (bits-1 DOWNTO 0)
);
END Component;
Component Add IS
PORT
(
data0x : IN STD_LOGIC_VECTOR (bits-1 DOWNTO 0);
data1x : IN STD_LOGIC_VECTOR (bits-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (bits-1 DOWNTO 0)
);
END Component;
Component Divider IS
PORT
(
denom : IN STD_LOGIC_VECTOR (bits-1 DOWNTO 0);
numer : IN STD_LOGIC_VECTOR (bits-1 DOWNTO 0);
quotient : OUT STD_LOGIC_VECTOR (bits-1 DOWNTO 0);
remain : OUT STD_LOGIC_VECTOR (bits-1 DOWNTO 0)
);
END Component;
------------------PORT MAP
BEGIN
Gen: tb_Framer_generator
PORT Map (
clk => clk,
ser_in => sin,
resetb => resetb
);
UUT: Framer
PORT Map (
clk => clk,
sin => sin,
resetb => resetb,
sout => sout,
clk_div_8 => clk_div_8,
decode_F628_out => decode_F628_out
);
Avg: Average
generic map (
bits => bits
)
Port Map(
clk => clk,
resetb => resetb,
data_sig_in => sout,
clk_div_8 => clk_div_8,
decode_F628_out => decode_F628_out,
ram_wren => ram_wren,
ram_address => ram_address,
ram_data => ram_data,
ram_q => ram_q,
add_value0x => add_data0x,
add_value1x => add_data1x,
add_sum => add_result,
div_denom => divide_denom,
div_numer => divide_numer
);
RAM1: RAM
PORT map
(
address => ram_address,
clock => clk,
data => ram_data,
wren => ram_wren,
q => ram_q
);
Add1: Add
PORT map
(
data0x => add_data0x,
data1x => add_data1x,
result => add_result
);
Div1: Divider
PORT map
(
denom =>divide_denom,
numer => divide_numer,
quotient => divide_quotient,
remain => divide_remain
);
END ; | gpl-3.0 | 6f12b4aa76bf922fabd0228caefa4d86 | 0.592172 | 2.925088 | false | false | false | false |
yishinli/emc2 | src/hal/drivers/m5i20/hostmot5_src/fcounter.vhd | 1 | 1,692 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fcounter is
port (
obus: out STD_LOGIC_VECTOR (31 downto 0);
startgate: in STD_LOGIC;
readcmd: in STD_LOGIC;
ref: in STD_LOGIC; -- local bus clock
clk: in STD_LOGIC; -- reference clock
gateout: out STD_LOGIC
);
end fcounter;
architecture behavioral of fcounter is
signal count: STD_LOGIC_VECTOR (23 downto 0);
signal gate : STD_LOGIC;
signal pregate : STD_LOGIC;
signal gatereq : STD_LOGIC;
signal gatecounter : STD_LOGIC_VECTOR (23 downto 0);
begin
acounter: process (ref, clk, readcmd, count, gate)
begin
if ref'event and ref = '1' then
if gatecounter /= 0 then
gatecounter <= gatecounter -1;
end if;
if pregate = '1' and gate = '0' then
gatecounter <= x"4C4640"; -- 5 million = .1 second gate
end if;
if gate = '1' then
pregate <= '0';
elsif gatereq = '1' and gate = '0' then
pregate <= '1';
end if;
if gatecounter /= 0 then
gate <= '1';
else
gate <= '0';
end if;
end if; --(reference clock edge)
if clk'event and clk = '1' then
if startgate = '1' then
count <= x"000000";
gatereq <= '1';
end if;
if gate = '1' then
count <= count +1;
gatereq <= '0';
end if;
end if; -- local bus clock edge
obus <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
if readcmd = '1' then
obus(23 downto 0) <= count;
obus(30 downto 24) <= "0000000";
obus(31) <= gate;
end if;
gateout <= gate;
end process;
end behavioral;
| lgpl-2.1 | a9cb47eda74883d3c0f24d30a27f8b3c | 0.573286 | 3.076364 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/i2c/i2c2ahb_gen.vhd | 1 | 4,208 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: i2c2ahb_gen
-- File: i2c2ahb_gen.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- Contact: [email protected]
-- Description: Generic wrapper for I2C-slave, see i2c2ahb.vhd
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library gaisler;
use gaisler.i2c.all;
entity i2c2ahb_gen is
generic (
ahbaddrh : integer := 0;
ahbaddrl : integer := 0;
ahbmaskh : integer := 0;
ahbmaskl : integer := 0;
-- I2C configuration
i2cslvaddr : integer range 0 to 127 := 0;
i2ccfgaddr : integer range 0 to 127 := 0;
oepol : integer range 0 to 1 := 0;
--
filter : integer range 2 to 512 := 2
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi_hgrant : in std_ulogic;
ahbi_hready : in std_ulogic;
ahbi_hresp : in std_logic_vector(1 downto 0);
ahbi_hrdata : in std_logic_vector(AHBDW-1 downto 0);
--ahbo : out ahb_mst_out_type;
ahbo_hbusreq : out std_ulogic;
ahbo_hlock : out std_ulogic;
ahbo_htrans : out std_logic_vector(1 downto 0);
ahbo_haddr : out std_logic_vector(31 downto 0);
ahbo_hwrite : out std_ulogic;
ahbo_hsize : out std_logic_vector(2 downto 0);
ahbo_hburst : out std_logic_vector(2 downto 0);
ahbo_hprot : out std_logic_vector(3 downto 0);
ahbo_hwdata : out std_logic_vector(AHBDW-1 downto 0);
-- I2C signals
--i2ci : in i2c_in_type;
i2ci_scl : in std_ulogic;
i2ci_sda : in std_ulogic;
--i2co : out i2c_out_type
i2co_scl : out std_ulogic;
i2co_scloen : out std_ulogic;
i2co_sda : out std_ulogic;
i2co_sdaoen : out std_ulogic;
i2co_enable : out std_ulogic
);
end entity i2c2ahb_gen;
architecture rtl of i2c2ahb_gen is
-- AHB signals
signal ahbi : ahb_mst_in_type;
signal ahbo : ahb_mst_out_type;
-- I2C signals
signal i2ci : i2c_in_type;
signal i2co : i2c_out_type;
begin
ahbi.hgrant(0) <= ahbi_hgrant;
ahbi.hgrant(1 to NAHBMST-1) <= (others => '0');
ahbi.hready <= ahbi_hready;
ahbi.hresp <= ahbi_hresp;
ahbi.hrdata <= ahbi_hrdata;
ahbo_hbusreq <= ahbo.hbusreq;
ahbo_hlock <= ahbo.hlock;
ahbo_htrans <= ahbo.htrans;
ahbo_haddr <= ahbo.haddr;
ahbo_hwrite <= ahbo.hwrite;
ahbo_hsize <= ahbo.hsize;
ahbo_hburst <= ahbo.hburst;
ahbo_hprot <= ahbo.hprot;
ahbo_hwdata <= ahbo.hwdata;
i2ci.scl <= i2ci_scl;
i2ci.sda <= i2ci_sda;
i2co_scl <= i2co.scl;
i2co_scloen <= i2co.scloen;
i2co_sda <= i2co.sda;
i2co_sdaoen <= i2co.sdaoen;
i2co_enable <= i2co.enable;
i2c0 : i2c2ahb
generic map (
hindex => 0,
ahbaddrh => ahbaddrh, ahbaddrl => ahbaddrl,
ahbmaskh => ahbmaskh, ahbmaskl => ahbmaskl,
i2cslvaddr => i2cslvaddr, i2ccfgaddr => i2ccfgaddr,
oepol => oepol, filter => filter)
port map (rstn, clk, ahbi, ahbo, i2ci, i2co);
end architecture rtl;
| gpl-3.0 | a9562cc05e0ee9d43ae61206fee4fc2c | 0.597909 | 3.318612 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-digilent-xc3s1600e/testbench.vhd | 1 | 9,746 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- modified by Thomas Ameseder, Gleichmann Electronics 2004, 2005 to
-- support the use of an external AHB slave and different HPE board versions
------------------------------------------------------------------------------
-- further adapted from Hpe_compact to Hpe_mini (Feb. 2005)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.config.all; -- configuration
use work.debug.all;
use std.textio.all;
library grlib;
use grlib.stdlib.all;
use grlib.stdio.all;
use grlib.devices.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 16; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 18; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(23 downto 0);
signal data : std_logic_vector(31 downto 0);
signal romsn : std_logic_vector(1 downto 0);
signal oen : std_ulogic;
signal writen : std_ulogic;
signal iosn : std_ulogic;
-- ddr memory
signal ddr_clk : std_logic;
signal ddr_clkb : std_logic;
signal ddr_clk_fb : std_logic;
signal ddr_cke : std_logic;
signal ddr_csb : std_logic;
signal ddr_web : std_ulogic; -- ddr write enable
signal ddr_rasb : std_ulogic; -- ddr ras
signal ddr_casb : std_ulogic; -- ddr cas
signal ddr_dm : std_logic_vector (1 downto 0); -- ddr dm
signal ddr_dqs : std_logic_vector (1 downto 0); -- ddr dqs
signal ddr_ad : std_logic_vector (12 downto 0); -- ddr address
signal ddr_ba : std_logic_vector (1 downto 0); -- ddr bank address
signal ddr_dq : std_logic_vector (15 downto 0); -- ddr data
signal brdyn : std_ulogic;
signal bexcn : std_ulogic;
signal wdog : std_ulogic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal rtsn, ctsn : std_ulogic;
signal error : std_logic;
signal pio : std_logic_vector(15 downto 0);
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal plllock : std_ulogic;
-- pulled up high, therefore std_logic
signal txd, rxd1 : std_logic;
signal etx_clk, erx_clk, erx_dv, erx_er, erx_col, erx_crs, etx_en, etx_er : std_logic := '0';
signal erxd, etxd : std_logic_vector(3 downto 0) := (others => '0');
signal emdc, emdio : std_logic; --dummy signal for the mdc,mdio in the phy which is not used
constant lresp : boolean := false;
signal resoutn : std_logic;
signal dsubren : std_ulogic;
signal dsuactn : std_ulogic;
begin
dsubren <= not dsubre;
-- clock and reset
clk <= not clk after ct * 1 ns;
rst <= '1', '0' after 100 ns;
dsuen <= '0'; dsubre <= '0'; rxd1 <= 'H';
address(0) <= '0';
ddr_dqs <= (others => 'L');
d3 : entity work.leon3mp
port map (
reset => rst,
clk_50mhz => clk,
errorn => error,
address => address(23 downto 0),
data => data(31 downto 16),
testdata => data(15 downto 0),
ddr_clk0 => ddr_clk,
ddr_clk0b => ddr_clkb,
ddr_clk_fb => ddr_clk_fb,
ddr_cke0 => ddr_cke,
ddr_cs0b => ddr_csb,
ddr_web => ddr_web,
ddr_rasb => ddr_rasb,
ddr_casb => ddr_casb,
ddr_dm => ddr_dm,
ddr_dqs => ddr_dqs,
ddr_ad => ddr_ad,
ddr_ba => ddr_ba,
ddr_dq => ddr_dq,
dsuen => dsuen,
dsubre => dsubre,
-- dsuact => dsuactn,
dsutx => dsutx,
dsurx => dsurx,
oen => oen,
writen => writen,
iosn => iosn,
romsn => romsn(0),
utxd1 => txd,
urxd1 => txd,
emdio => emdio,
etx_clk => etx_clk,
erx_clk => erx_clk,
erxd => erxd,
erx_dv => erx_dv,
erx_er => erx_er,
erx_col => erx_col,
erx_crs => erx_crs,
etxd => etxd,
etx_en => etx_en,
etx_er => etx_er,
emdc => emdc
);
ddr_clk_fb <= ddr_clk;
-- u1 : mt46v16m16
-- generic map (index => -1, fname => sdramfile)
-- port map(
-- Dq => ddr_dq(15 downto 0), Dqs => ddr_dqs(1 downto 0), Addr => ddr_ad,
-- Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke,
-- Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
-- Dm => ddr_dm(1 downto 0));
ddr0 : ddrram
generic map(width => 16, abits => 13, colbits => 9, rowbits => 13,
implbanks => 1, fname => sdramfile, speedbin => 1, density => 2)
port map (ck => ddr_clk, cke => ddr_cke, csn => ddr_csb,
rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web,
dm => ddr_dm, ba => ddr_ba, a => ddr_ad, dq => ddr_dq,
dqs => ddr_dqs);
prom0 : for i in 0 to (romwidth/8)-1 generate
sr0 : sram generic map (index => i+4, abits => romdepth, fname => promfile)
port map (address(romdepth downto 1), data(31-i*8 downto 24-i*8), romsn(0),
writen, oen);
end generate;
-- phy0 : if CFG_GRETH > 0 generate
-- p0 : phy
-- port map(rst, led_cfg, open, etx_clk, erx_clk, erxd, erx_dv,
-- erx_er, erx_col, erx_crs, etxd, etx_en, etx_er, emdc);
-- end generate;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 5 us;
assert (to_X01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure;
end process;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, oen, writen, brdyn);
data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#ef#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
--
-- txc(dsutx, 16#80#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end;
| gpl-3.0 | 6b5cd9e9874a87a15977cdd8f1e5f723 | 0.527088 | 3.52988 | false | false | false | false |
firecake/IRIS | FPGA/VHDL/ipcore_dir/RAM/simulation/RAM_tb.vhd | 1 | 4,629 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: RAM_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY RAM_tb IS
END ENTITY;
ARCHITECTURE RAM_tb_ARCH OF RAM_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL CLKB : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
CLKB_GEN: PROCESS BEGIN
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
RAM_synth_inst:ENTITY work.RAM_synth
PORT MAP(
CLK_IN => CLK,
CLKB_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
| gpl-3.0 | c0d6d3f321fd4f18f11d9d7d5d01be68 | 0.595161 | 4.416985 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/maps/clkgen.vhd | 1 | 9,993 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: clkgen
-- File: clkgen.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: Clock generator with tech selection
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
entity clkgen is
generic (
tech : integer := DEFFABTECH;
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 1;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000; -- clock frequency in KHz
clk2xen : integer := 0;
clksel : integer := 0; -- enable clock select
clk_odiv : integer := 1; -- Proasic3/Fusion output divider clkA
clkb_odiv: integer := 0; -- Proasic3/Fusion output divider clkB
clkc_odiv: integer := 0); -- Proasic3/Fusion output divider clkC
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- 2x clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk4x : out std_logic; -- 4x clock
clk1xu : out std_logic; -- unscaled 1X clock
clk2xu : out std_logic; -- unscaled 2X clock
clkb : out std_logic; -- Proasic3/Fusion clkB
clkc : out std_logic; -- Proasic3/Fusion clkC
clk8x : out std_logic); -- 8x clock
end;
architecture struct of clkgen is
signal intclk, sdintclk : std_ulogic;
signal lock : std_ulogic;
begin
gen : if (has_clkgen(tech) = 0) generate
sdintclk <= pciclkin when (PCISYSCLK = 1 and PCIEN /= 0) else clkin;
sdclk <= sdintclk; intclk <= sdintclk
-- pragma translate_off
after 1 ns -- create 1 ns skew between clk and sdclk
-- pragma translate_on
;
clk1xu <= intclk; pciclk <= pciclkin; clk <= intclk; clkn <= not intclk;
cgo.clklock <= '1'; cgo.pcilock <= '1'; clk2x <= '0'; clk4x <= '0';
clkb <= '0'; clkc <= '0'; clk8x <= '0';
end generate;
xc2v : if (tech = virtex2) or (tech = virtex4) generate
v : clkgen_virtex2
generic map (clk_mul, clk_div, sdramen, noclkfb, pcien, pcidll, pcisysclk, freq, clk2xen, clksel)
port map (clkin, pciclkin, clk, clkn, clk2x, sdclk, pciclk, cgi, cgo, clk1xu, clk2xu);
end generate;
xc5l : if (tech = virtex5) or (tech = virtex6) generate
v : clkgen_virtex5
generic map (clk_mul, clk_div, sdramen, noclkfb, pcien, pcidll, pcisysclk, freq, clk2xen, clksel)
port map (clkin, pciclkin, clk, clkn, clk2x, sdclk, pciclk, cgi, cgo, clk1xu, clk2xu);
end generate;
xc7l : if (tech =virtex7) or (tech =kintex7) or (tech =artix7) or (tech =zynq7000) generate
v : clkgen_virtex7
generic map (clk_mul, clk_div, freq)
port map (clkin, clk, clkn, clk2x ,cgi, cgo);
end generate;
xc3s : if (tech = spartan3) or (tech = spartan3e) or (tech = spartan6) generate
v : clkgen_spartan3
generic map (clk_mul, clk_div, sdramen, noclkfb, pcien, pcidll, pcisysclk, freq, clk2xen, clksel)
port map (clkin, pciclkin, clk, clkn, clk2x, sdclk, pciclk, cgi, cgo, clk1xu, clk2xu);
end generate;
alt : if (tech = altera) or (tech = stratix1) generate
v : clkgen_altera_mf
generic map (clk_mul, clk_div, sdramen, noclkfb, pcien, pcidll, pcisysclk, freq, clk2xen)
port map (clkin, pciclkin, clk, clkn, clk2x, sdclk, pciclk, cgi, cgo);
end generate;
strat2 : if (tech = stratix2) generate
v : clkgen_stratixii
generic map (clk_mul, clk_div, sdramen, noclkfb, pcien, pcidll, pcisysclk, freq, clk2xen)
port map (clkin, pciclkin, clk, clkn, clk2x, sdclk, pciclk, cgi, cgo);
end generate;
cyc3 : if (tech = cyclone3) generate
v : clkgen_cycloneiii
generic map (clk_mul, clk_div, sdramen, noclkfb, pcien, pcidll, pcisysclk, freq, clk2xen)
port map (clkin, pciclkin, clk, clkn, clk2x, sdclk, pciclk, cgi, cgo);
end generate;
stra3 : if (tech = stratix3) or (tech = stratix4) generate
v : clkgen_stratixiii
generic map (clk_mul, clk_div, sdramen, noclkfb, pcien, pcidll, pcisysclk, freq, clk2xen)
port map (clkin, pciclkin, clk, clkn, clk2x, sdclk, pciclk, cgi, cgo);
end generate;
act : if (tech = axdsp) or (tech = proasic) generate
intclk <= pciclkin when (PCISYSCLK = 1 and PCIEN /= 0) else clkin;
sdclk <= '0'; pciclk <= pciclkin; clk <= intclk; clkn <= '0';
cgo.clklock <= '1'; cgo.pcilock <= '1'; clk2x <= '0';
end generate;
axc : if (tech = axcel) generate
pll_disabled : if (clk_mul = clk_div) generate
intclk <= pciclkin when (PCISYSCLK = 1 and PCIEN /= 0) else clkin;
sdclk <= '0'; pciclk <= pciclkin; clk <= intclk; clkn <= '0';
cgo.clklock <= '1'; cgo.pcilock <= '1'; clk2x <= '0';
end generate;
pll_enabled : if (clk_mul /= clk_div) generate
clk2x <= '0';
pll : clkgen_axcelerator
generic map (
clk_mul => clk_mul,
clk_div => clk_div,
sdramen => sdramen,
sdinvclk => 0,
pcien => pcien,
pcidll => pcidll,
pcisysclk => pcisysclk,
freq => freq)
port map(
clkin => clkin,
pciclkin => pciclkin,
clk => clk,
clkn => clkn,
sdclk => sdclk,
pciclk => pciclk,
cgi => cgi,
cgo => cgo);
end generate;
end generate;
lib18t : if (tech = rhlib18t) generate
v : clkgen_rh_lib18t
generic map (clk_mul, clk_div)
port map (cgi.pllrst, intclk, clk, sdclk, clk2x, clk4x);
intclk <= pciclkin when (PCISYSCLK = 1 and PCIEN /= 0) else clkin;
pciclk <= pciclkin; clkn <= '0';
cgo.clklock <= '1'; cgo.pcilock <= '1';
end generate;
ap3 : if tech = apa3 generate
v : clkgen_proasic3
generic map (clk_mul, clk_div, clk_odiv, pcien, pcisysclk, freq, clkb_odiv, clkc_odiv)
port map (clkin, pciclkin, clk, sdclk, pciclk, cgi, cgo, clkb, clkc);
clk2x <= '0';
end generate;
ap3e : if tech = apa3e generate
v : clkgen_proasic3e
generic map (clk_mul, clk_div, clk_odiv, pcien, pcisysclk, freq, clkb_odiv, clkc_odiv)
port map (clkin, pciclkin, clk, sdclk, pciclk, cgi, cgo, clkb, clkc);
clk2x <= '0';
end generate;
ap3l : if tech = apa3l generate
v : clkgen_proasic3l
generic map (clk_mul, clk_div, clk_odiv, pcien, pcisysclk, freq, clkb_odiv, clkc_odiv)
port map (clkin, pciclkin, clk, sdclk, pciclk, cgi, cgo, clkb, clkc);
clk2x <= '0';
end generate;
fus : if tech = actfus generate
v : clkgen_fusion
generic map (clk_mul, clk_div, clk_odiv, pcien, pcisysclk, freq, clkb_odiv, clkc_odiv)
port map (clkin, pciclkin, clk, sdclk, pciclk, cgi, cgo, clkb, clkc);
clk2x <= '0';
end generate;
dr : if (tech = rhumc) generate
v : clkgen_rhumc
port map (clkin, clk, clk2x, sdclk, pciclk,
cgi, cgo, clk4x, clk1xu, clk2xu);
clk8x <= '0';
end generate;
saed : if (tech = saed32) generate
v : clkgen_saed32
port map (clkin, clk, clk2x, sdclk, pciclk,
cgi, cgo, clk4x, clk1xu, clk2xu);
end generate;
rhs : if (tech = rhs65) generate
v : clkgen_rhs65
port map (clkin, clk, clk2x, sdclk, pciclk,
cgi, cgo, clk4x, clk1xu, clk2xu);
end generate;
dar : if (tech = dare) generate
v : clkgen_dare
generic map (noclkfb)
port map (clkin, clk, clk2x, sdclk, pciclk,
cgi, cgo, clk4x, clk1xu, clk2xu, clk8x);
end generate;
nextreme90 : if tech = easic90 generate
pll0 : clkgen_easic90
generic map (
clk_mul => clk_mul,
clk_div => clk_div,
freq => freq,
pcisysclk => pcisysclk,
pcien => pcien)
port map (clkin, pciclkin, clk, clk2x, clk4x, clkn, lock);
cgo.clklock <= lock;
cgo.pcilock <= lock;
end generate;
n2x : if tech = easic45 generate
v : clkgen_n2x
generic map (clk_mul, clk_div, sdramen, noclkfb, pcien, pcidll,
pcisysclk, freq, clk2xen, clksel, 0)
port map (clkin, pciclkin, clk, clkn, clk2x, sdclk, pciclk, cgi,
cgo, clk1xu, clk2xu, open);
end generate;
ut13 : if (tech = ut130) generate
v : clkgen_ut130hbd
generic map (clk_mul, clk_div, sdramen, noclkfb, pcien, pcidll, pcisysclk, freq, clk2xen, clksel)
port map (clkin, pciclkin, clk, clkn, clk2x, clk4x, clk8x, sdclk, pciclk, cgi, cgo, clk1xu, clk2xu);
end generate;
ut90nhbd : if (tech = ut90) generate
v : clkgen_ut90nhbd
generic map (clk_mul, clk_div, sdramen, noclkfb, pcien, pcidll, pcisysclk, freq, clk2xen, clksel)
port map (clkin, pciclkin, clk, clkn, clk2x, sdclk, pciclk, cgi, cgo, clk1xu, clk2xu);
end generate;
end;
| gpl-3.0 | 800b487f8f7b44f5d0ed4a7c8e8f23ce | 0.608326 | 3.434021 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/jtag/jtag.vhd | 1 | 6,818 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- package: jtag
-- File: jtag.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: JTAG components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
package jtag is
-- JTAG manufacturer IDs
constant JTAG_MANF_ID_GR : integer range 0 to 2047 := 804;
-- JTAG part numbers
-- Do NOT select an existing part number for your custom design!
--
-- For your design, please select a JTAG ID that starts with 16#a--#
-- and notify Aeroflex Gaisler (in case do not change the manufacturer
-- ID to your own ID).
constant JTAG_EXAMPLE_PART : integer range 0 to 65535 := 16#300#;
component ahbjtag
generic (
tech : integer range 0 to NTECH := 0;
hindex : integer := 0;
nsync : integer range 1 to 2 := 1;
idcode : integer range 0 to 255 := 9;
manf : integer range 0 to 2047 := 804;
part : integer range 0 to 65535 := 0;
ver : integer range 0 to 15 := 0;
ainst : integer range 0 to 255 := 2;
dinst : integer range 0 to 255 := 3;
scantest : integer := 0;
oepol : integer := 1;
tcknen : integer := 0;
versel : integer range 0 to 1 := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
tck : in std_ulogic;
tms : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_inst : out std_logic_vector(7 downto 0);
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapi_tdo : in std_ulogic;
trst : in std_ulogic := '1';
tdoen : out std_ulogic;
tckn : in std_ulogic := '0';
tapo_tckn : out std_ulogic;
tapo_ninst : out std_logic_vector(7 downto 0);
tapo_iupd : out std_ulogic
);
end component;
component ahbjtag_bsd
generic (
tech : integer range 0 to NTECH := 0;
hindex : integer := 0;
nsync : integer range 1 to 2 := 1;
ainst : integer range 0 to 255 := 2;
dinst : integer range 0 to 255 := 3);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
asel : in std_ulogic;
dsel : in std_ulogic;
tck : in std_ulogic;
regi : in std_ulogic;
shift : in std_ulogic;
rego : out std_ulogic
);
end component;
component bscanctrl
generic (
spinst: integer := 5; -- sample/preload
etinst: integer := 6; -- extest
itinst: integer := 7; --intest
hzinst: integer := 8; -- highz
clinst: integer := 10; -- clamp
mbist : integer := 11; -- mbist
testx1: integer := 12; -- generic test command
scantest : integer := 0
);
port (
trst : in std_ulogic;
tapo_tck : in std_ulogic;
tapo_tckn : in std_ulogic;
tapo_tdi : in std_ulogic;
tapo_ninst : in std_logic_vector(7 downto 0);
tapo_iupd : in std_ulogic;
tapo_rst : in std_ulogic;
tapo_capt : in std_ulogic;
tapo_shft : in std_ulogic;
tapo_upd : in std_ulogic;
tapi_tdo : out std_ulogic;
chain_tdi : out std_ulogic;
chain_tdo : in std_ulogic;
bsshft : out std_ulogic;
bscapt : out std_ulogic;
bsupdi : out std_ulogic;
bsupdo : out std_ulogic;
bsdrive : out std_ulogic;
bshighz : out std_ulogic;
bsmbist : out std_ulogic;
bstestx1 : out std_ulogic;
testen : in std_ulogic;
testrst : in std_ulogic;
bypass_tdo : out std_ulogic;
mbist_tdo : in std_ulogic := '0'
);
end component;
component bscanregs
generic (
tech: integer := 0;
nsigs: integer range 1 to 30 := 8;
dirmask: integer := 2#00000000#;
enable: integer range 0 to 1 := 1
);
port (
sigi: in std_logic_vector(nsigs-1 downto 0);
sigo: out std_logic_vector(nsigs-1 downto 0);
tck: in std_ulogic;
tckn:in std_ulogic;
tdi: in std_ulogic;
tdo: out std_ulogic;
bsshft: in std_ulogic;
bscapt: in std_ulogic;
bsupdi: in std_ulogic;
bsupdo: in std_ulogic;
bsdrive: in std_ulogic;
bshighz: in std_ulogic
);
end component;
component bscanregsbd
generic (
tech: integer:= 0;
nsigs: integer := 8;
enable: integer range 0 to 1 := 1;
hzsup: integer range 0 to 1 := 1
);
port (
pado : out std_logic_vector(nsigs-1 downto 0);
padoen : out std_logic_vector(nsigs-1 downto 0);
padi : in std_logic_vector(nsigs-1 downto 0);
coreo : in std_logic_vector(nsigs-1 downto 0);
coreoen : in std_logic_vector(nsigs-1 downto 0);
corei : out std_logic_vector(nsigs-1 downto 0);
tck : in std_ulogic;
tckn : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
bsshft : in std_ulogic;
bscapt : in std_ulogic; -- capture signals to scan regs on next tck edge
bsupdi : in std_ulogic; -- update indata reg from scan reg on next tck edge
bsupdo : in std_ulogic; -- update outdata reg from scan reg on next tck edge
bsdrive : in std_ulogic; -- drive outdata regs to pad,
-- drive datareg(coreoen=0) or coreo(coreoen=1) to corei
bshighz : in std_ulogic -- tri-state output if hzsup, sample 1 on input
);
end component;
end;
| gpl-3.0 | 8dae35a490f89a7a7af78d77ace2758a | 0.576269 | 3.638207 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-altera-c5ekit/config.vhd | 1 | 5,501 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := altera;
constant CFG_MEMTECH : integer := altera;
constant CFG_PADTECH : integer := altera;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (0);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 1;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 1 + 64*0;
constant CFG_ATBSZ : integer := 1;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000000#;
-- SSRAM controller
constant CFG_SSCTRL : integer := 0;
constant CFG_SSCTRLP16 : integer := 0;
-- I2C master
constant CFG_I2C_ENABLE : integer := 1;
-- AHB ROM
constant CFG_AHBROMEN : integer := 1;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#100#;
constant CFG_ROMMASK : integer := 16#E00# + 16#100#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 8;
-- Gaisler Ethernet core
constant CFG_GRETH2 : integer := 1;
constant CFG_GRETH21G : integer := 0;
constant CFG_ETH2_FIFO : integer := 8;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#000F#;
constant CFG_GRGPIO_WIDTH : integer := (2);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-3.0 | 7eaf85d97843fa4e8143e68d646e9d67 | 0.639702 | 3.604849 | false | false | false | false |
ggaray/nicsim-vhd | nicctrl.vhd | 1 | 41,074 | -- NICSim-vhd: A VHDL-based modelling and simulation of NIC's buffers
-- Copyright (C) 2013 Godofredo R. Garay <godofredo.garay (-at-) gmail.com>
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
use std.textio.all;
library ieee;
use ieee.numeric_std.all;
use ieee.math_real.all;
use ieee.std_logic_1164.all;
entity nicctrl is
port (
transfer_start_req : in bit;
transfer_end : out bit := '0';
req : out bit := '1';
gnt : in bit;
frame : inout std_logic := 'Z';
irdy : out bit := '1';
trdy : in bit;
AD : out bit := '0';
payload_size_in_data_blocks : in integer;
payload_transfer_req : out bit := '1';
descriptor_transfer_req : out bit := '1';
payload_transfer_end : in bit;
descriptor_transfer_end : in bit;
payload_transfer_aborted : in bit;
resume_aborted_payload_transfer : out bit := '1';
descriptor_transfer_aborted : in bit;
resume_aborted_descriptor_transfer : out bit := '1';
acq_latency_cycles_counter_out : out integer := 0;
nic_proc_latency_cycles_counter_out : out integer := 0;
nicclk : in bit;
pciclk : in bit
);
end nicctrl;
architecture V1 of nicctrl is
--------------- NIC processing latency configuration ---------------
constant packet_identification_latency : time := 4.72631578947368 us;
constant crc_computation_latency : time := 0 us;
--constant packet_identification_latency : time := 0.3 us;
--constant crc_computation_latency : time := 0.2 us;
-- Baseline for NIC latency used in all the experiment (burst size = 256 bytes, jumbo pkts, 10-GigE, NIC latency = 5 us )
--constant protocol_offload_latency : time := 0 us;
--------------------------------------------------------------------------------------
-- Extra overhead for Jumbo packets, 10 Gigabit Ethernet, PCI-X 133/64 bus
--------------------------------------------------------------------------------------
--constant protocol_offload_latency : time := 2.199248123 us; -- Extra overhead for burst size = 512 bytes, jumbo pkts
--constant protocol_offload_latency : time := 3.310150379 us; -- Extra overhead for burst size = 1024 bytes, jumbo pkts
--constant protocol_offload_latency : time := 3.800751884 us; -- Extra overhead for burst size = 2048 bytes, jumbo pkts
--constant protocol_offload_latency : time := 4.043233087 us; -- Extra overhead for burst size = 4096 bytes, jumbo pkts
--------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------
-- Extra overhead for max Ethernet packet size, PCI-X 133/64 bus, Gigabit Ethernet
--------------------------------------------------------------------------------------
--constant protocol_offload_latency : time := 3.696992484 us; -- Extra overhead for burst size = 256 bytes, max size pkts
--constant protocol_offload_latency : time := 4.136842109 us; -- Extra overhead for burst size = 512 bytes, max size pkts
--------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------
-- Extra overhead for max Ethernet packet size, PCI-X 133/64 bus, 10 Gigabit Ethernet
--------------------------------------------------------------------------------------
--constant protocol_offload_latency : time := 3.619924815 us; -- Extra overhead for burst size = 256 bytes, max size pkts
--constant protocol_offload_latency : time := 4.010902259 us; -- Extra overhead for burst size = 512 bytes, max size pkts
--constant protocol_offload_latency : time := 4.131203011 us; -- Extra overhead for burst size = 1024 bytes, max size pkts
--constant protocol_offload_latency : time := 4.260902259 us; -- Extra overhead for burst size = 4096 bytes, max size pkts
--------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------
-- Extra overhead for min Ethernet packet size, PCI-X 133/64 bus, burst size = 256 bytes
--------------------------------------------------------------------------------------
--constant protocol_offload_latency : time := 4.046992485 us; -- Extra overhead for Ethernet, min size pkts
--constant protocol_offload_latency : time := 4.289473688 us; -- Extra overhead for Fast Ethernet, min size pkts
--constant protocol_offload_latency : time := 4.161654139 us; -- Extra overhead for Gigabit Ethernet, min size pkts
--constant protocol_offload_latency : time := 3.48120301 us; -- Extra overhead for 10 Gigabit Ethernet, min size pkts
--------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------
-- Extra overhead for min Ethernet packet size, line speed = 100 Mbps, PCI-X 133/64 bus, burst size = 256 bytes
--------------------------------------------------------------------------------------
--constant protocol_offload_latency : time := 19.105263177 us; -- Extra overhead for NIC latency = 20 us
--constant protocol_offload_latency : time := 14.016917292 us; -- Extra overhead for NIC latency = 15 us
--constant protocol_offload_latency : time := 9.992481218 us; -- Extra overhead for NIC latency = 10 us
--constant protocol_offload_latency : time := 4.289473688 us; -- Extra overhead for NIC latency = 5.2 us
constant protocol_offload_latency : time := 0 us; -- Extra overhead for NIC latency = 0.9 us
--------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------
-- Extra overhead for min Ethernet packet size, line speed = 100 Mbps, NIC latency = 5.2 us, burst size = 256 bytes
--------------------------------------------------------------------------------------
--constant protocol_offload_latency : time := us; -- Extra overhead for NIC latency = 20 us
--constant protocol_offload_latency : time := us; -- Extra overhead for NIC latency = 15 us
--constant protocol_offload_latency : time := 3.805303096 us; -- Extra overhead for PCI 66/64
--constant protocol_offload_latency : time := 2.98787881 us; -- Extra overhead for PCI 33/32
--------------------------------------------------------------------------------------
-- ***To be removed
--constant min_acquisition_latency : positive := 1;
--constant max_acquisition_latency : positive := 80;
--constant min_acquisition_latency : positive := 1;
--constant max_acquisition_latency : positive := 80;
--------------- Random number generator configuration ---------------
-- ***To be removed
--Run 1
--constant seed1_value : positive := 34;
--constant seed2_value : positive := 45;
--Run 2
--constant seed1_value : positive := 329;
--constant seed2_value : positive := 6;
--Run 3
--constant seed1_value : positive := 105;
--constant seed2_value : positive := 134;
--Run 4
--constant seed1_value : positive := 4;
--constant seed2_value : positive := 3;
--Run 5
--constant seed1_value : positive := 8;
--constant seed2_value : positive := 4;
-- ****** In the future, constant pcilck_period should be removed a function based on the pciclk signal should be implemented
--constant pciclk_period : time := 0.03030303 us; -- PCI 33
--constant pciclk_period : time := 0.015151515 us; -- PCI 66
constant pciclk_period : time := 0.007518797 us; -- PCI-X 133
--constant pciclk_period : time := 0.003759398 us; -- PCI-X 266
--constant pciclk_period : time := 0.001876173 us; -- PCI-X 533
--constant tpd : time := 1 ns; ****** To be removed
--------------- Variables Declarations ---------------
shared variable random_cycles_count : integer := 0;
shared variable acq_latency_cycles_count : integer := 0;
shared variable nic_processing_latency_cycles_count : integer := 0;
-- A variable is declared for each output signal.
shared variable transfer_end_value : bit := '0' ;
shared variable req_value : bit := '1';
shared variable irdy_value : bit := '1';
signal AD_value : bit := '1';
--shared variable AD_value : bit := '1';
--shared variable frame_value : bit := '1';
shared variable payload_transfer_req_value : bit := '1';
shared variable descriptor_transfer_req_value : bit := '1';
shared variable resume_aborted_payload_transfer_value : bit := '1';
shared variable resume_aborted_descriptor_transfer_value : bit := '1';
-- Variables needed for printing out simulation statistics
shared variable total_transmission_cycles_count : natural := 0;
shared variable total_acquisition_cycles_count : natural := 0;
shared variable transmission_cycles_count : natural := 0;
shared variable non_transmission_cycles_count : natural := 0;
shared variable max_non_transmission_period : natural := 0;
-- These signals are used to handle frame bidirectional port
signal dir : std_logic := '0'; -- '0' reading, '1' driving
signal frame_value : std_logic := 'Z';
-- FSM initial state: idle
type nicctrl_state is (idle,
processing_packet,
waiting_arbitration_latency_for_payload_transfer,
waiting_acquisition_latency_for_payload_transfer,
waiting_initial_target_latency_for_payload_transfer,
transferring_payload,
waiting_arbitration_latency_for_descriptor_transfer,
waiting_acquisition_latency_for_descriptor_transfer,
waiting_initial_target_latency_for_descriptor_transfer,
transferring_descriptor,
waiting_arbitration_latency_for_resuming_payload_transfer,
waiting_acquisition_latency_for_resuming_payload_transfer,
waiting_initial_target_latency_for_resuming_payload_transfer,
resuming_aborted_payload_transfer,
waiting_arbitration_latency_for_resuming_descriptor_transfer,
waiting_acquisition_latency_for_resuming_descriptor_transfer,
waiting_initial_target_latency_for_resuming_descriptor_transfer,
resuming_aborted_descriptor_transfer,
ending_transaction);
shared variable state : nicctrl_state := idle;
shared variable next_state : nicctrl_state := idle;
--------------- Auxiliary Functions ---------------
function compute_crc_latency (eth_frame_size : in integer) return time is
variable result : time := crc_computation_latency; -- In this version, it is a fixed value.
-- In future version, it should be replace for a formula.
--So crc latency should be computed as a function of eth_frame_size
begin
return result;
end function compute_crc_latency;
function compute_offload_latency (eth_frame_size : in integer) return time is
variable result : time := protocol_offload_latency; -- In this version, it is a fixed value
-- In future version, it should be replace for a formula.
--So offload latency should be computed as a function of eth_frame_size
begin
return result;
end function compute_offload_latency;
function acquisition_latency return time is
variable result : time;
begin
result := pciclk_period * 2;
return result;
end function acquisition_latency;
--------------- Architecture Begin ---------------
begin
frame <= frame_value when (dir = '1') else 'Z';
AD <= AD_value;
nicctrl_fsm: process
variable my_line : line;
begin
--wait until pciclk'event and pciclk = '1';
wait until nicclk'event and nicclk = '1';
case state is
when idle =>
transfer_end_value := '0';
req_value := '1';
irdy_value := '1';
--dir <= '0';
--frame_value := '1';
payload_transfer_req_value := '1';
descriptor_transfer_req_value := '1';
resume_aborted_payload_transfer_value := '1';
resume_aborted_descriptor_transfer_value := '1';
--wait for pciclk_period * 2;
-- wait until (transfer_start_req'event
-- and transfer_start_req = '0');
--wait until transfer_start_req = '0';
if transfer_start_req = '1'
and payload_transfer_end = '0'
and payload_transfer_aborted = '0'
and descriptor_transfer_end = '0'
and descriptor_transfer_aborted = '0'
then next_state := idle;
elsif transfer_start_req = '0'
and payload_transfer_end = '0'
and descriptor_transfer_end = '0'
and payload_transfer_aborted = '0'
and descriptor_transfer_aborted = '0'
then assert false
report "nicctrl_fsm: processing_packet"
severity note;
next_state := processing_packet;
elsif transfer_start_req = '0'
and gnt = '1'
and payload_transfer_end = '1'
and descriptor_transfer_end = '0'
and payload_transfer_aborted = '0'
and descriptor_transfer_aborted = '0'
then assert false
report "nicctrl_fsm: waiting_arbitration_latency_for_descriptor_transfer"
severity note;
next_state := waiting_arbitration_latency_for_descriptor_transfer;
elsif transfer_start_req = '0'
and gnt = '1'
and payload_transfer_aborted = '1'
and payload_transfer_req_value = '1'
and payload_transfer_end = '0'
and descriptor_transfer_end = '0'
and descriptor_transfer_aborted = '0'
-- Duda aqui
then req_value := '0';
--resume_aborted_payload_transfer_value := '0';
assert false
report "nicctrl_fsm: waiting_arbitration_latency_for_resuming_payload_transfer"
severity note;
--next_state := resuming_aborted_payload_transfer;
next_state := waiting_arbitration_latency_for_resuming_payload_transfer;
elsif transfer_start_req = '0'
and descriptor_transfer_aborted = '1'
and payload_transfer_end = '0'
and descriptor_transfer_end = '0'
and payload_transfer_aborted = '0'
then assert false
report "nicctrl_fsm: resuming_aborted_descriptor_transfer"
severity note;
next_state := resuming_aborted_descriptor_transfer;
elsif descriptor_transfer_end = '1'
and transfer_start_req = '0'
then assert false
report "nicctrl_fsm: ending_transaction"
severity note;
next_state := ending_transaction;
else assert false
report "An illegal state has occurred in nicctrl_fsm:. "
severity note;
end if;
when processing_packet =>
if transfer_start_req = '0'
then --wait for nic_service_time;
wait for packet_identification_latency;
wait for compute_crc_latency (payload_size_in_data_blocks);
wait for compute_offload_latency (payload_size_in_data_blocks);
-- Once the processing for a single packet is completed, the variable nic_processing_latency_cycles_count is reset.
-- This variable will be increased again for the next packet. See process nic_processing_latency_cycles_counter.
nic_processing_latency_cycles_count := 0;
assert false
report "nicctrl_fsm: waiting_arbitration_latency_for_payload_transfer"
severity note;
next_state := waiting_arbitration_latency_for_payload_transfer;
elsif transfer_start_req = '1'
then next_state := idle;
end if;
when waiting_arbitration_latency_for_payload_transfer =>
--wait for pciclk_period * 2;
-- Wait for arbitration latency
if transfer_start_req = '1'
then next_state := idle;
-- If gnt = '0' due to a current transaction has not been complete yet, we keep waiting in this state until gnt = '0'
elsif gnt = '0'
then next_state := waiting_arbitration_latency_for_payload_transfer;
-- Bus is requested only if gnt = '1'
elsif gnt = '1'
then req_value := '0';
wait until gnt = '0';
assert false
report "nicctrl_fsm: waiting_acquisition_latency_for_payload_transfer"
severity note;
next_state := waiting_acquisition_latency_for_payload_transfer;
end if;
when waiting_acquisition_latency_for_payload_transfer =>
--wait for pciclk_period * 2;
-- If PCI/PCI-X bus is not idle due to the current transaction has not being completed, we keep waiting until the bus is idle
if transfer_start_req = '1'
then next_state := idle;
elsif frame = '0'
then dir <= '0';
next_state := waiting_acquisition_latency_for_payload_transfer;
elsif frame = 'Z'
then dir <= '1';
frame_value <= '0';
--AD_value := '0';
AD_value <= '0';
assert false
report "nicctrl_fsm: waiting_initial_target_latency_for_payload_transfer"
severity note;
next_state := waiting_initial_target_latency_for_payload_transfer;
elsif frame = '1'
then dir <= '0';
wait for pciclk_period;
dir <= '1';
frame_value <= '0';
--AD_value := '0';
AD_value <= '0';
assert false
report "nicctrl_fsm: waiting_initial_target_latency_for_payload_transfer"
severity note;
next_state := waiting_initial_target_latency_for_payload_transfer;
end if;
when waiting_initial_target_latency_for_payload_transfer =>
if trdy = '1'
then next_state := waiting_initial_target_latency_for_payload_transfer;
elsif trdy = '0'
then payload_transfer_req_value := '0';
irdy_value := '0';
assert false
report "nicctrl_fsm: transferring_payload"
severity note;
next_state := transferring_payload;
end if;
when transferring_payload =>
--if transfer_start_req = '0'
--then payload_transfer_req_value := '0';
--wait until (payload_transfer_end'event
--or payload_transfer_aborted'event);
if transfer_start_req = '1'
then next_state := idle;
elsif gnt = '1'
or (gnt = '0'
and payload_transfer_end = '1')
or (gnt = '0'
and payload_transfer_aborted = '1')
then assert false
report "nicctrl_fsm: idle"
severity note;
--aqui
--ad_value := '1';
AD_value <= '1';
--dir <= '0';
dir <= '1';
frame_value <= '1';
wait for pciclk_period;
dir <= '0';
next_state := idle;
-- In the normal scenario, we keep waiting in this stage until the rising edge of payload_transfer_end
elsif gnt = '0'
and payload_transfer_end = '0'
then next_state := transferring_payload;
end if;
when waiting_arbitration_latency_for_descriptor_transfer =>
-- This delay is required for syncronization
--wait for pciclk_period * 2;
-- Wait for arbitration latency
if transfer_start_req = '1'
then assert false
report "nicctrl_fsm: idle"
severity note;
next_state := idle;
-- If gnt = '0' due to a current transaction not complete yet, we keep waiting in this state until gnt = '0'
elsif gnt = '0'
then next_state := waiting_arbitration_latency_for_descriptor_transfer;
-- Bus is requested only if gnt = '1'
elsif gnt = '1'
then req_value := '0';
wait until gnt = '0';
assert false
report "nicctrl_fsm: waiting_acquisition_latency_for_descriptor_transfer"
severity note;
next_state := waiting_acquisition_latency_for_descriptor_transfer;
end if;
when waiting_acquisition_latency_for_descriptor_transfer =>
--if transfer_start_req = '1'
--then next_state := idle;
--elsif frame = '0'
--then dir <= '0';
-- next_state := waiting_acquisition_latency_for_descriptor_transfer;
--elsif frame = '1'
--then dir <= '1';
-- frame_value <= '0';
-- assert false
-- report "nicctrl_fsm: waiting_initial_target_latency_for_descriptor_transfer"
-- severity note;
-- next_state := waiting_initial_target_latency_for_descriptor_transfer;
--end if;
-- If PCI/PCI-X bus is not idle due to the current transaction has not being completed, we keep waiting until the bus is idle
if transfer_start_req = '1'
then assert false
report "nicctrl_fsm: waiting_acquisition_latency_for_descriptor_transfer"
severity note;
next_state := idle;
elsif frame = '0'
then dir <= '0';
next_state := waiting_acquisition_latency_for_descriptor_transfer;
elsif frame = 'Z'
then dir <= '1';
frame_value <= '0';
--AD_value := '0';
AD_value <= '0';
assert false
report "nicctrl_fsm: waiting_initial_target_latency_for_descriptor_transfer"
severity note;
next_state := waiting_initial_target_latency_for_descriptor_transfer;
elsif frame = '1'
then dir <= '0';
wait for pciclk_period;
dir <= '1';
frame_value <= '0';
--AD_value := '0';
AD_value <= '0';
assert false
report "nicctrl_fsm: waiting_initial_target_latency_for_descriptor_transfer"
severity note;
next_state := waiting_initial_target_latency_for_descriptor_transfer;
end if;
when waiting_initial_target_latency_for_descriptor_transfer =>
if transfer_start_req = '1'
then assert false
report "nicctrl_fsm: transferring_descriptor"
severity note;
next_state := idle;
-- We keep waiting in this state until trdy is asserted.
elsif trdy = '1'
then next_state := waiting_initial_target_latency_for_descriptor_transfer;
-- Here trdy is asserted.
elsif trdy = '0'
then descriptor_transfer_req_value := '0';
irdy_value := '0';
assert false
report "nicctrl_fsm: transferring_descriptor"
severity note;
next_state := transferring_descriptor;
end if;
when transferring_descriptor =>
-- If signal transfer_end is received we leave this stage.
if transfer_start_req = '1'
then next_state := idle;
-- If grant is de-asserted or descriptor transfer is aborted or descriptor transfer end we leave this stage.
elsif gnt = '1'
or (gnt = '0'
and descriptor_transfer_end = '1')
or (gnt = '0'
and descriptor_transfer_aborted = '1')
then
--aqui
--ad_value := '1';
AD_value <= '1';
--dir <= '0';
dir <= '1';
frame_value <= '1';
wait for pciclk_period;
dir <= '0';
assert false
report "nicctrl_fsm: idle"
severity note;
next_state := idle;
-- Keep waiting in this stage until the rising edge of descriptor_transfer_end
elsif gnt = '0'
and descriptor_transfer_end = '0'
then next_state := transferring_descriptor;
end if;
when waiting_arbitration_latency_for_resuming_payload_transfer =>
--wait for pciclk_period * 2;
-- Wait for arbitration latency
if transfer_start_req = '1'
then assert false
report "nicctrl_fsm: idle"
severity note;
next_state := idle;
-- If gnt = '0' due to a current transaction not complete yet, we keep waiting in this state until gnt = '0'
elsif gnt = '0'
then next_state := waiting_arbitration_latency_for_resuming_payload_transfer;
-- Bus is requested only if gnt = '1'
elsif gnt = '1'
then req_value := '0';
wait until gnt = '0';
assert false
report "nicctrl_fsm: waiting_acquisition_latency_for_resuming_payload_transfer"
severity note;
next_state := waiting_acquisition_latency_for_resuming_payload_transfer;
end if;
when waiting_acquisition_latency_for_resuming_payload_transfer =>
--if transfer_start_req = '1'
--then next_state := idle;
--elsif frame = '0'
--then dir <= '0';
-- next_state := waiting_acquisition_latency_for_resuming_payload_transfer;
--elsif frame = '1'
--then dir <= '1';
-- frame_value <= '0';
-- assert false
-- report "nicctrl_fsm: waiting_initial_target_latency_for_resuming_payload_transfer"
-- severity note;
-- next_state := waiting_initial_target_latency_for_resuming_payload_transfer;
--end if;
-- If PCI/PCI-X bus is not idle due to the current transaction has not being completed, we keep waiting until the bus is idle
if transfer_start_req = '1'
then assert false
report "nicctrl_fsm: idle"
severity note;
next_state := idle;
elsif frame = '0' -- Bus is busy
then dir <= '0';
next_state := waiting_acquisition_latency_for_resuming_payload_transfer;
elsif frame = 'Z'
then dir <= '1';
frame_value <= '0';
--AD_value := '0';
AD_value <= '0';
assert false
report "nicctrl_fsm: waiting_initial_target_latency_for_resuming_payload_transfer"
severity note;
next_state := waiting_initial_target_latency_for_resuming_payload_transfer;
elsif frame = '1'
then dir <= '0';
wait for pciclk_period;
dir <= '1';
frame_value <= '0';
--AD_value := '0';
AD_value <= '0';
assert false
report "nicctrl_fsm: waiting_initial_target_latency_for_resuming_payload_transfer"
severity note;
next_state := waiting_initial_target_latency_for_resuming_payload_transfer;
end if;
when waiting_initial_target_latency_for_resuming_payload_transfer =>
if trdy = '1'
then next_state := waiting_initial_target_latency_for_resuming_payload_transfer;
elsif trdy = '0'
then --payload_transfer_req_value := '0';
-- Here, resume_aborted_payload_transfer is asserted
irdy_value := '0';
resume_aborted_payload_transfer_value := '0';
assert false
report "nicctrl_fsm: resuming_aborted_payload_transfer"
severity note;
next_state := resuming_aborted_payload_transfer;
end if;
when resuming_aborted_payload_transfer =>
if transfer_start_req = '1'
then next_state := idle;
elsif gnt = '1'
or (gnt = '0'
and payload_transfer_end = '1')
or (gnt = '0'
and payload_transfer_aborted = '1')
-- *** Duda aqui ***
then AD_value <= '1';
--dir <= '0';
dir <= '1';
frame_value <= '1';
wait for pciclk_period;
dir <= '0';
assert false
report "nicctrl_fsm: idle"
severity note;
next_state := idle;
-- Keep waiting in this stage until the rising edge of payload_transfer_end
elsif gnt = '0'
and payload_transfer_end = '0'
then next_state := resuming_aborted_payload_transfer;
end if;
when waiting_arbitration_latency_for_resuming_descriptor_transfer =>
if transfer_start_req = '1'
then next_state := idle;
elsif transfer_start_req = '1'
then next_state := idle;
-- Keep waiting if conditions are not ok
elsif gnt = '0'
--and irdy_value = '1'
--and payload_transfer_end = '0'
--and descriptor_transfer_end = '0'
--and descriptor_transfer_aborted = '1')
then next_state := waiting_arbitration_latency_for_resuming_descriptor_transfer;
-- req is asserted if conditions are ok
elsif gnt = '1'
--and irdy_value = '1'
--and payload_transfer_end = '0'
--and descriptor_transfer_end = '0'
--and descriptor_transfer_aborted = '1'
then req_value := '0';
wait until gnt = '0';
-- Wait for acquisition latency
wait for acquisition_latency;
-- NIC is ready for data-phase transfers
--irdy_value := '0';
--next_state := resuming_aborted_descriptor_transfer;
next_state := waiting_acquisition_latency_for_resuming_descriptor_transfer;
end if;
when waiting_acquisition_latency_for_resuming_descriptor_transfer =>
--if transfer_start_req = '1'
--then next_state := idle;
--elsif frame = '0'
--then dir <= '0';
-- next_state := waiting_acquisition_latency_for_resuming_descriptor_transfer;
--elsif frame = '1'
--then dir <= '1';
-- frame_value <= '0';
-- assert false
-- report "nicctrl_fsm: waiting_initial_target_latency_for_resuming_descriptor_transfer"
-- severity note;
-- next_state := waiting_initial_target_latency_for_resuming_descriptor_transfer;
--end if;
if transfer_start_req = '1'
then next_state := idle;
elsif frame = '0'
then dir <= '0';
next_state := waiting_acquisition_latency_for_resuming_descriptor_transfer;
elsif frame = 'Z'
then dir <= '1';
frame_value <= '0';
--AD_value := '0';
AD_value <= '0';
assert false
report "nicctrl_fsm: waiting_initial_target_latency_for_resuming_descriptor_transfer"
severity note;
next_state := waiting_initial_target_latency_for_resuming_descriptor_transfer;
elsif frame = '1'
then dir <= '0';
wait for pciclk_period;
dir <= '1';
frame_value <= '0';
--AD_value := '0';
AD_value <= '0';
assert false
report "nicctrl_fsm: waiting_initial_target_latency_for_resuming_descriptor_transfer"
severity note;
next_state := waiting_initial_target_latency_for_resuming_descriptor_transfer;
end if;
when waiting_initial_target_latency_for_resuming_descriptor_transfer =>
if trdy = '1'
then next_state := waiting_initial_target_latency_for_resuming_descriptor_transfer;
elsif trdy = '0'
then resume_aborted_descriptor_transfer_value := '0';
irdy_value := '0';
-- Signal resume_aborted_payload_transfer_value is asserted
resume_aborted_descriptor_transfer_value := '0';
assert false
report "nicctrl_fsm: resuming_aborted_descriptor_transfer"
severity note;
next_state := resuming_aborted_descriptor_transfer;
end if;
when resuming_aborted_descriptor_transfer =>
--resume_aborted_descriptor_transfer_value := '0';
if transfer_start_req = '1'
then next_state := idle;
elsif gnt = '1'
or (gnt = '0'
and descriptor_transfer_end = '1')
or (gnt = '0'
and descriptor_transfer_aborted = '1')
then
--aqui
--ad_value := '1';
AD_value <= '1';
--dir <= '0';
dir <= '1';
frame_value <= '1';
wait for pciclk_period;
dir <= '0';
next_state := idle;
-- Keep waiting in this stage until the rising edge of payload_transfer_end
elsif gnt = '0'
and descriptor_transfer_end = '0'
then next_state := resuming_aborted_descriptor_transfer;
end if;
when ending_transaction =>
-- Signal transfer_end is generated if all conditions are ok
if transfer_start_req = '0'
--transfer_start_req = '1'
--or (gnt = '1'
--and descriptor_transfer_end = '0')
--and payload_transfer_end = '0'
--and payload_transfer_aborted = '0'
--and descriptor_transfer_aborted = '0'
then transfer_end_value := '1';
--wait for pciclk_period * 8;
--assert false
--report "nicctrl_fsm: idle"
--severity note;
--next_state := idle;
next_state := ending_transaction;
-- Keep waiting in this stage if all condition are not ok
elsif gnt = '1'
and descriptor_transfer_end = '1'
--and payload_transfer_end = '0'
--and payload_transfer_aborted = '0'
--and descriptor_transfer_aborted = '0')
then next_state := ending_transaction;
elsif transfer_start_req = '1'
then assert false
report "nicctrl_fsm: idle"
severity note;
next_state := idle;
end if;
end case;
state := next_state;
end process nicctrl_fsm;
-- FSM of Latecy Cycles Generator
-- random_number_generator_fsm: process
-- type generator_state is (idle, generating_random_number, waiting);
-- variable state : generator_state := idle;
-- variable next_state : generator_state := idle;
-- variable random_number : integer := 1;
-- variable seed1 : positive := seed1_value;
-- variable seed2 : positive := seed2_value;
-- variable rand: real;
-- file random_acquisition_cycles_file : text open write_mode is "random_acquisition_cycles.out";
-- variable output_line : line;
-- begin
-- case state is
-- when idle =>
-- wait until gnt'event and gnt = '0';
-- assert false
-- report "generating random acquisition latency"
-- severity note;
-- next_state := generating_random_number;
-- when generating_random_number =>
-- Since rand values are in the interval 0..1, the values are multiplicated by 1000 and rounded.
-- This way, an integer random value in the interval 1..1000 is obtained
-- uniform(seed1, seed2, rand);
-- random_number := integer(round(rand*1000.0));
--random_number := 5;
-- if random_number >= min_acquisition_latency
-- and random_number <= max_acquisition_latency
-- then random_cycles_count := random_number;
-- write(output_line, random_cycles_count);
-- writeline(random_acquisition_cycles_file, output_line);
-- next_state := waiting;
-- else next_state := generating_random_number;
-- end if;
-- when waiting =>
-- wait until gnt'event and gnt = '0';
-- next_state := generating_random_number;
-- end case;
-- state := next_state;
-- end process random_number_generator_fsm;
output_signals_driver: process
begin
--wait until pciclk'event and pciclk = '1';
wait until nicclk'event and nicclk = '1';
transfer_end <= transfer_end_value;
req <= req_value;
irdy <= irdy_value;
--AD <= AD_value;
--frame <= frame_value;
payload_transfer_req <= payload_transfer_req_value;
descriptor_transfer_req <= descriptor_transfer_req_value;
resume_aborted_payload_transfer <= resume_aborted_payload_transfer_value;
resume_aborted_descriptor_transfer <= resume_aborted_descriptor_transfer_value;
end process output_signals_driver;
-- transmission_and_non_transmission_cycles_counter : process
-- begin
-- wait until pciclk'event and pciclk = '1';
-- if state = processing_packet
-- or state = waiting_arbitration_latency_for_payload_transfer
-- or state = requesting_bus_access_for_descriptor_transfer
-- then non_transmission_cycles_count := non_transmission_cycles_count + 1;
-- elsif state = transferring_payload
-- or state = transferring_descriptor
-- then transmission_cycles_count := transmission_cycles_count + 1;
-- if non_transmission_cycles_count > max_non_transmission_period
-- then max_non_transmission_period := non_transmission_cycles_count;
-- end if;
-- end if;
-- end process transmission_and_non_transmission_cycles_counter;
total_transmission_cycles_counter : process
begin
wait until pciclk'event and pciclk = '1' and transfer_start_req = '0';
total_transmission_cycles_count := total_transmission_cycles_count + 1;
end process total_transmission_cycles_counter;
-- total_acquisition_cycles_counter : process
-- begin
-- wait until pciclk'event and pciclk = '1' and acq_latency_cycles_count > 0;
-- total_acquisition_cycles_count := total_acquisition_cycles_count + 1;
-- end process total_acquisition_cycles_counter;
-- print_out_nicctrl_statistics: process
-- file nicctrl_output_file : text open write_mode is "nicctrl.out";
-- variable output_line : line;
-- variable clock_counter : natural := 1;
-- begin
-- wait until pciclk'event and pciclk = '0';
-- write(output_line, string'("clock "));
-- write(output_line, clock_counter);
-- write(output_line, string'(": "));
-- write(output_line, string'("total transmission cycles count = "));
-- write(output_line, total_transmission_cycles_count);
-- write(output_line, string'(": "));
-- write(output_line, string'("total acquisition cycles count = "));
-- write(output_line, total_acquisition_cycles_count);
-- writeline(nicctrl_output_file, output_line);
-- clock_counter := clock_counter + 1;
-- end process print_out_nicctrl_statistics;
acquisition_latency_cycles_counter_out_driver: process
begin
wait until pciclk'event and pciclk = '0';
acq_latency_cycles_counter_out <= acq_latency_cycles_count;
end process acquisition_latency_cycles_counter_out_driver;
nic_processing_latency_cycles_counter : process
begin
wait until pciclk'event and pciclk = '1' and state = processing_packet; --transfer_start_req = '0' and req_value = '1';
nic_processing_latency_cycles_count := nic_processing_latency_cycles_count + 1;
end process nic_processing_latency_cycles_counter;
nic_processing_latency_cycles_counter_out_driver: process
begin
wait until pciclk'event and pciclk = '0';
nic_proc_latency_cycles_counter_out <= nic_processing_latency_cycles_count;
end process nic_processing_latency_cycles_counter_out_driver;
acq_latency_cycles_counter_fsm: process
-- Variables needed for acq_latency_cycles_counter_fsm
type acq_latency_cycles_counter_fsm_state is (idle,
incrementing_acq_latency_cycles_count,
waiting_transaction_end);
variable state : acq_latency_cycles_counter_fsm_state := idle;
variable next_state : acq_latency_cycles_counter_fsm_state := idle;
begin
wait until pciclk'event and pciclk = '1';
case state is
when idle =>
acq_latency_cycles_count := 0;
if gnt = '1'
then next_state := idle;
elsif gnt = '0'
then acq_latency_cycles_count := acq_latency_cycles_count + 1;
assert false
report "acq_latency_cycles_counter_fsm: incrementing_acq_latency_cycles_count"
severity note;
next_state := incrementing_acq_latency_cycles_count;
end if;
when incrementing_acq_latency_cycles_count =>
if gnt = '0'
and not (frame = '0'
and AD_value = '0')
then acq_latency_cycles_count := acq_latency_cycles_count + 1;
next_state := incrementing_acq_latency_cycles_count;
elsif gnt = '0'
and frame = '0'
and AD_value = '0'
then acq_latency_cycles_count := 0;
assert false
report "acq_latency_cycles_counter_fsm: waiting_transaction_end"
severity note;
next_state := waiting_transaction_end;
end if;
when waiting_transaction_end =>
if gnt = '0'
then next_state := waiting_transaction_end;
elsif gnt = '1'
then assert false
report "acq_latency_cycles_counter_fsm: idle"
severity note;
next_state := idle;
end if;
end case;
state := next_state;
end process acq_latency_cycles_counter_fsm;
-- print_out_nicctrl_statistics: process
-- file nicctrl_output_file : text open write_mode is "nicctrl.out";
-- variable output_line : line;
-- variable clock_counter : natural := 1;
-- variable average : real;
-- begin
-- wait until pciclk'event and pciclk = '0';
-- write(output_line, string'("clock "));
-- write(output_line, clock_counter);
-- write(output_line, string'(": "));
-- write(output_line, string'("non trans. cycles count = "));
-- write(output_line, non_transmission_cycles_count);
-- write(output_line, string'(": "));
-- write(output_line, string'("trans. cycles count = "));
-- write(output_line, transmission_cycles_count);
-- write(output_line, string'(": "));
-- write(output_line, string'("max. non trans. period = "));
-- write(output_line, max_non_transmission_period);
-- write(output_line, string'(": "));
-- write(output_line, string'("total cycles count = "));
-- write(output_line, transmission_cycles_count + non_transmission_cycles_count);
-- write(output_line, string'(": "));
-- write(output_line, string'("average rate = "));
--write(output_line, real(transmission_cycles_count)/real(transmission_cycles_count + non_transmission_cycles_count));
-- writeline(nicctrl_output_file, output_line);
-- clock_counter := clock_counter + 1;
-- end process print_out_nicctrl_statistics;
end V1;
| gpl-3.0 | a2d0163c66ac895b5f3a169e40aeefb0 | 0.611555 | 3.387267 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/greth/grethm.vhd | 1 | 6,489 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grethm
-- File: grethm.vhd
-- Author: Jiri Gaisler
-- Description: Module to select between greth and greth1g
------------------------------------------------------------------------------
library ieee;
library grlib;
library gaisler;
use ieee.std_logic_1164.all;
use grlib.stdlib.all;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
use gaisler.net.all;
entity grethm is
generic(
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 64 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
burstlength : integer range 4 to 128 := 32;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
rmii : integer range 0 to 1 := 0;
sim : integer range 0 to 1 := 0;
giga : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 2 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
maxsize : integer := 1500;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ethi : in eth_in_type;
etho : out eth_out_type
);
end entity;
architecture rtl of grethm is
begin
m100 : if giga = 0 generate
u0 : greth
generic map (
hindex => hindex,
pindex => pindex,
paddr => paddr,
pmask => pmask,
pirq => pirq,
memtech => memtech,
ifg_gap => ifg_gap,
attempt_limit => attempt_limit,
backoff_limit => backoff_limit,
slot_time => slot_time,
mdcscaler => mdcscaler,
enable_mdio => enable_mdio,
fifosize => fifosize,
nsync => nsync,
edcl => edcl,
edclbufsz => edclbufsz,
macaddrh => macaddrh,
macaddrl => macaddrl,
ipaddrh => ipaddrh,
ipaddrl => ipaddrl,
phyrstadr => phyrstadr,
rmii => rmii,
oepol => oepol,
scanen => scanen,
ft => ft,
edclft => edclft,
mdint_pol => mdint_pol,
enable_mdint => enable_mdint,
multicast => multicast,
ramdebug => ramdebug,
mdiohold => mdiohold,
maxsize => maxsize,
gmiimode => gmiimode
)
port map (
rst => rst,
clk => clk,
ahbmi => ahbmi,
ahbmo => ahbmo,
apbi => apbi,
apbo => apbo,
ethi => ethi,
etho => etho);
end generate;
m1000 : if giga = 1 generate
u0 : greth_gbit
generic map (
hindex => hindex,
pindex => pindex,
paddr => paddr,
pmask => pmask,
pirq => pirq,
memtech => memtech,
ifg_gap => ifg_gap,
attempt_limit => attempt_limit,
backoff_limit => backoff_limit,
slot_time => slot_time,
mdcscaler => mdcscaler,
nsync => nsync,
edcl => edcl,
edclbufsz => edclbufsz,
burstlength => burstlength,
macaddrh => macaddrh,
macaddrl => macaddrl,
ipaddrh => ipaddrh,
ipaddrl => ipaddrl,
phyrstadr => phyrstadr,
sim => sim,
oepol => oepol,
scanen => scanen,
ft => ft,
edclft => edclft,
mdint_pol => mdint_pol,
enable_mdint => enable_mdint,
multicast => multicast,
ramdebug => ramdebug,
mdiohold => mdiohold,
gmiimode => gmiimode
)
port map (
rst => rst,
clk => clk,
ahbmi => ahbmi,
ahbmo => ahbmo,
apbi => apbi,
apbo => apbo,
ethi => ethi,
etho => etho);
end generate;
end architecture;
| gpl-3.0 | e70ce0bd89b0e7f1f71bf1b6c75580d1 | 0.469564 | 4.453672 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/leon3v3/mmu_cache.vhd | 1 | 6,540 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mmu_cache
-- File: mmu_cache.vhd
-- Author: Jiri Gaisler
-- Description: Cache controllers and AHB interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.libleon3.all;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
use gaisler.libmmu.all;
entity mmu_cache is
generic (
hindex : integer := 0;
fabtech : integer := 0;
memtech : integer := 0;
dsu : integer range 0 to 1 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 0;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 0;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 7 := 0;
ilram : integer range 0 to 2 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 2 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
cached : integer := 0;
clk2x : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
smp : integer := 0;
mmuen : integer range 0 to 1 := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ici : in icache_in_type;
ico : out icache_out_type;
dci : in dcache_in_type;
dco : out dcache_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
crami : out cram_in_type;
cramo : in cram_out_type;
fpuholdn : in std_ulogic;
hclk, sclk : in std_ulogic;
hclken : in std_ulogic
);
end;
architecture rtl of mmu_cache is
constant MEMTECH_MOD : integer := memtech mod 65536;
constant MEMTECH_VEC : std_logic_vector(31 downto 0) := conv_std_logic_vector(memtech, 32);
constant TLB_INFER : integer := conv_integer(MEMTECH_VEC(16));
signal icol : icache_out_type;
signal dcol : dcache_out_type;
signal mcii : memory_ic_in_type;
signal mcio : memory_ic_out_type;
signal mcdi : memory_dc_in_type;
signal mcdo : memory_dc_out_type;
signal mcmmi : memory_mm_in_type;
signal mcmmo : memory_mm_out_type;
signal mmudci : mmudc_in_type;
signal mmudco : mmudc_out_type;
signal mmuici : mmuic_in_type;
signal mmuico : mmuic_out_type;
signal ahbsi2 : ahb_slv_in_type;
signal ahbi2 : ahb_mst_in_type;
signal ahbo2 : ahb_mst_out_type;
signal gndv: std_logic_vector(1 downto 0);
begin
gndv <= (others => '0');
icache0 : mmu_icache
generic map (fabtech, icen, irepl, isets, ilinesize, isetsize, isetlock, ilram,
ilramsize, ilramstart,
mmuen)
port map (rst, clk, ici, icol, dci, dcol, mcii, mcio,
crami.icramin, cramo.icramo, fpuholdn, mmudci, mmuici, mmuico);
dcache0 : mmu_dcache
generic map (dsu, dcen, drepl, dsets, dlinesize, dsetsize, dsetlock, dsnoop,
dlram, dlramsize, dlramstart, ilram, ilramstart,
itlbnum, dtlbnum, tlb_type,
MEMTECH_MOD, cached, mmupgsz, smp, mmuen, icen)
port map (rst, clk, dci, dcol, icol, mcdi, mcdo, ahbsi2,
crami.dcramin, cramo.dcramo, fpuholdn, mmudci, mmudco, sclk, ahbso);
-- AMBA AHB interface
a0 : mmu_acache
generic map (hindex, ilinesize, cached, clk2x, scantest
)
port map (rst, sclk, mcii, mcio, mcdi, mcdo, mcmmi, mcmmo, ahbi2, ahbo2, ahbso, hclken);
-- MMU
mmugen : if mmuen = 1 generate
m0 : mmu
generic map (MEMTECH_MOD*(1-TLB_INFER), itlbnum, dtlbnum, tlb_type, tlb_rep, mmupgsz, memtest_vlen)
port map (rst, clk, mmudci, mmudco, mmuici, mmuico, mcmmo, mcmmi, ahbi.testin
);
end generate;
nommu : if mmuen = 0 generate
mcmmi <= mci_zero; mmudco <= mmudco_zero; mmuico <= mmuico_zero;
end generate;
ico <= icol;
dco <= dcol;
clk2xgen: if clk2x /= 0 generate
sync0 : clk2xsync generic map (hindex, clk2x)
port map (rst, hclk, clk, ahbi, ahbi2, ahbo2, ahbo, ahbsi, ahbsi2,
mcii, mcdi, mcdo, mcmmi.req, mcmmo.grant, hclken);
end generate;
noclk2x : if clk2x = 0 generate
ahbsi2 <= ahbsi;
ahbi2 <= ahbi;
ahbo <= ahbo2;
end generate;
end;
| gpl-3.0 | 2e206da5441bc64e6b6e21dce1e41aab | 0.563761 | 3.726496 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-digilent-xc3s1600e/config.vhd | 1 | 6,446 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := spartan3e;
constant CFG_MEMTECH : integer := spartan3e;
constant CFG_PADTECH : integer := spartan3e;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := spartan3e;
constant CFG_CLKMUL : integer := (4);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 1;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 2;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 2;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 4 + 64*0;
constant CFG_ATBSZ : integer := 4;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000018#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDRSP : integer := 1;
constant CFG_DDRSP_INIT : integer := 1;
constant CFG_DDRSP_FREQ : integer := (90);
constant CFG_DDRSP_COL : integer := (10);
constant CFG_DDRSP_SIZE : integer := (64);
constant CFG_DDRSP_RSKEW : integer := (40);
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 1;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 1;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-3.0 | 12608ec91b0f596e93a6029d7de641c4 | 0.64412 | 3.601117 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/grdmac/apbmem.vhd | 1 | 3,745 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: apbmem
-- File: apbmem.vhd
-- Author: Andrea Gianarro - Aeroflex Gaisler AB
-- Description: AMBA APB memory
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity apbmem is
generic (
pindex : integer := 0; -- APB configuration slave index
paddr : integer := 1;
pmask : integer := 16#FFF#;
size : integer range 4 to 1024 := 1024); -- size in Bytes
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type);
end;
architecture rtl of apbmem is
constant MEM_BITS : integer := log2ext(size);
constant apbmax : integer := 19;
constant VERSION : amba_version_type := 0;
-- TODO: move this constant with other amba constants and change value
constant GAISLER_APBMEM : integer := 0;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant pconfig: apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_APBMEM, 0, VERSION, 0 ),
1 => apb_iobar(paddr, pmask)
);
type memory_vector_type is array (0 to size/4) of std_logic_vector(31 downto 0);
type reg_type is record
memarr : memory_vector_type;
end record;
constant RES : reg_type := (
memarr => (others => zero32));
signal r, rin : reg_type;
begin
reg : process(clk)
begin
if rising_edge(clk) then
r <= rin;
if RESET_ALL and rst = '0' then
r <= RES;
end if;
end if;
end process;
comb : process(r, rst, apbi)
variable vprdata : std_logic_vector(31 downto 0);
variable v : reg_type;
begin
v := r;
-- APB slave
-- write
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
v.memarr(conv_integer(apbi.paddr(MEM_BITS-1 downto 2))) := apbi.pwdata;
end if;
--read
vprdata := r.memarr(conv_integer(apbi.paddr(MEM_BITS-1 downto 2)));
if (not RESET_ALL) and (rst = '0') then
v := RES;
end if;
rin <= v;
apbo <= ( prdata => vprdata,
pirq => (others => '0'),
pconfig => pconfig,
pindex => pindex);
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("apbmem" & tost(pindex) &
": APB memory size " & tost(size) & "Bytes");
-- pragma translate_on
end architecture;
| gpl-3.0 | f310b09e20d806ffbc5efccb169ecc5c | 0.595995 | 3.798174 | false | true | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-digilent-xc3s1000/leon3mp.vhd | 1 | 16,978 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.jtag.all;
-- pragma translate_off
use gaisler.sim.all;
-- pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
reset : in std_ulogic;
clk : in std_ulogic; -- 50 MHz main clock
error : out std_ulogic;
address : out std_logic_vector(19 downto 2);
data : inout std_logic_vector(31 downto 0);
ramsn : out std_logic_vector (1 downto 0);
mben : out std_logic_vector (3 downto 0);
oen : out std_ulogic;
writen : out std_ulogic;
dsubre : in std_ulogic;
dsuact : out std_ulogic;
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
pio : inout std_logic_vector(17 downto 0); -- I/O port
-- switch : in std_logic_vector(7 downto 0); -- switches
-- button : in std_logic_vector(2 downto 0); -- buttons
ps2clk : inout std_logic;
ps2data : inout std_logic;
vid_hsync : out std_ulogic;
vid_vsync : out std_ulogic;
vid_r : out std_logic;
vid_g : out std_logic;
vid_b : out std_logic
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := CFG_NCPU+
CFG_AHB_JTAG+CFG_SVGA_ENABLE;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, nerror : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal lclk, rst : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal kbdi : ps2_in_type;
signal kbdo : ps2_out_type;
signal vgao : apbvga_out_type;
signal clkval : std_logic_vector(1 downto 0);
constant BOARD_FREQ : integer := 50000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := 0;
signal dac_clk, clk1x, vid_clock, video_clk, clkvga : std_logic; -- signals to vga_clkgen.
signal clk_sel : std_logic_vector(1 downto 0);
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of video_clk : signal is true;
attribute syn_preserve of video_clk : signal is true;
attribute keep of video_clk : signal is true;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
CFG_CLK_NOFB, 0, 0, 0, BOARD_FREQ)
port map (lclk, lclk, clkm, open, open, open, open, cgi, cgo, open, clk1x);
resetn_pad : inpad generic map (tech => padtech) port map (reset, rst);
rst0 : rstgen -- reset generator
generic map (acthigh => 1)
port map (rst, clkm, cgo.clklock, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
nerror <= not dbgo(0).error;
error_pad : outpad generic map (tech => padtech) port map (error, nerror);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
-- dcomgen : if CFG_AHB_UART = 1 generate
-- dcom0: ahbuart -- Debug UART
-- generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
-- port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
-- dsurx_pad : inpad generic map (tech => padtech) port map (rxd2, dui.rxd);
-- dsutx_pad : outpad generic map (tech => padtech) port map (txd2, duo.txd);
-- end generate;
-- nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "00";
mctrl0 : mctrl generic map (hindex => 0, pindex => 0,
rommask => 16#000#, iomask => 16#000#,
paddr => 0, srbanks => 1, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN,
invclk => CFG_CLK_NOFB, sepbus => CFG_MCTRL_SEPBUS)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
addr_pad : outpadv generic map (width => 18, tech => padtech)
port map (address, memo.address(19 downto 2));
ramsa_pad : outpad generic map (tech => padtech)
port map (ramsn(0), memo.ramsn(0));
ramsb_pad : outpad generic map (tech => padtech)
port map (ramsn(1), memo.ramsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
mben_pads : outpadv generic map (tech => padtech, width => 4)
port map (mben, memo.mben);
data_pads : iopadvv generic map (tech => padtech, width => 32)
port map (data, memo.data(31 downto 0),
memo.vbdrive(31 downto 0), memi.data(31 downto 0));
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0';
rxd1_pad : inpad generic map (tech => padtech) port map (rxd1, u1i.rxd);
txd1_pad : outpad generic map (tech => padtech) port map (txd1, u1o.txd);
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti <= gpti_dhalt_drive(dsuo.tstop);
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
kbd : if CFG_KBD_ENABLE /= 0 generate
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
end generate;
nokbd : if CFG_KBD_ENABLE = 0 generate
apbo(5) <= apb_none; kbdo <= ps2o_none;
end generate;
kbdclk_pad : iopad generic map (tech => padtech)
port map (ps2clk,kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
kbdata_pad : iopad generic map (tech => padtech)
port map (ps2data, kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
clkdiv : process(clk1x, rstn)
begin
if rstn = '0' then clkval <= "00";
elsif rising_edge(clk1x) then
clkval <= clkval + 1;
end if;
end process;
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, video_clk, apbi, apbo(6), vgao);
video_clock_pad : outpad generic map ( tech => padtech)
port map (vid_clock, dac_clk);
dac_clk <= not video_clk;
b1 : techbuf generic map (2, virtex2) port map (clkval(0), video_clk);
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
clkvga <= clkval(1) when clk_sel = "00" else clkval(0) when clk_sel = "01" else clkm;
b1 : techbuf generic map (2, virtex2) port map (clkvga, video_clk);
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_JTAG,
clk0 => 40000, clk1 => 20000, clk2 => 25000)
port map(rstn, clkm, video_clk, apbi, apbo(6), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_JTAG), clk_sel);
dac_clk <= not video_clk;
video_clock_pad : outpad generic map ( tech => padtech)
port map (vid_clock, dac_clk);
end generate;
novga : if (CFG_VGA_ENABLE = 0 and CFG_SVGA_ENABLE = 0) generate
apbo(6) <= apb_none; vgao <= vgao_none;
end generate;
vert_sync_pad : outpad generic map (tech => padtech)
port map (vid_vsync, vgao.vsync);
horiz_sync_pad : outpad generic map (tech => padtech)
port map (vid_hsync, vgao.hsync);
video_out_r_pad : outpad generic map (tech => padtech)
port map (vid_r, vgao.video_out_r(7));
video_out_g_pad : outpad generic map (tech => padtech)
port map (vid_g, vgao.video_out_g(7));
video_out_b_pad : outpad generic map (tech => padtech)
port map (vid_b, vgao.video_out_b(7));
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 8, paddr => 8, imask => CFG_GRGPIO_IMASK, nbits => 18)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(8),
gpioi => gpioi, gpioo => gpioo);
pio_pads : iopadvv generic map (width => 18, tech => padtech)
port map (pio, gpioo.dout(17 downto 0), gpioo.oen(17 downto 0),
gpioi.din(17 downto 0));
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (CFG_NCPU+FG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0 : ahbrep generic map (hindex => 4, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(4));
-- pragma translate_on
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Digilent XC3S1000 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-3.0 | 275789a294f509613ecf9c1efacf1d05 | 0.558782 | 3.658263 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-gr-cpci-xc4v/leon3mp.vhd | 1 | 45,906 | -----------------------------------------------------------------------------
-- LEON Demonstration design
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.can.all;
use gaisler.pci.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.spacewire.all;
use gaisler.l2cache.all;
use gaisler.subsys.all;
library testgrouppolito;
use testgrouppolito.dprc_pkg.all;
library esa;
use esa.memoryctrl.all;
use esa.pcicomp.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_logic;
clk : in std_logic;
pllref : in std_logic;
errorn : out std_logic;
wdogn : out std_logic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
cb : inout std_logic_vector(7 downto 0);
sa : out std_logic_vector(14 downto 0);
sd : inout std_logic_vector(63 downto 0);
-- scb : inout std_logic_vector(7 downto 0);
sdclk : out std_logic;
sdcke : out std_logic_vector (1 downto 0); -- sdram clock enable
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_logic; -- sdram write enable
sdrasn : out std_logic; -- sdram ras
sdcasn : out std_logic; -- sdram cas
sddqm : out std_logic_vector (7 downto 0); -- sdram dqm
dsutx : out std_logic; -- DSU tx data
dsurx : in std_logic; -- DSU rx data
dsuen : in std_logic;
dsubre : in std_logic;
dsuact : out std_logic;
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
rts1 : out std_ulogic;
cts1 : in std_ulogic;
txd2 : out std_ulogic; -- UART2 tx data
rxd2 : in std_ulogic; -- UART2 rx data
rts2 : out std_ulogic;
cts2 : in std_ulogic;
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_logic;
writen : out std_logic;
read : out std_logic;
iosn : out std_logic;
romsn : out std_logic_vector (1 downto 0);
brdyn : in std_logic; -- bus ready
bexcn : in std_logic; -- bus exception
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_logic;
erx_clk : in std_logic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_logic;
erx_er : in std_logic;
erx_col : in std_logic;
erx_crs : in std_logic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_logic;
etx_er : out std_logic;
emdc : out std_logic;
emdintn : in std_logic;
pci_rst : inout std_logic; -- PCI bus
pci_clk : in std_logic;
pci_gnt : in std_logic;
pci_idsel : in std_logic;
pci_lock : inout std_logic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_logic;
pci_irdy : inout std_logic;
pci_trdy : inout std_logic;
pci_devsel : inout std_logic;
pci_stop : inout std_logic;
pci_perr : inout std_logic;
pci_par : inout std_logic;
pci_req : inout std_logic;
pci_serr : inout std_logic;
pci_host : in std_logic;
pci_int : inout std_logic_vector(3 downto 0);
pci_66 : in std_logic;
pci_arb_req : in std_logic_vector(0 to 3);
pci_arb_gnt : out std_logic_vector(0 to 3);
can_txd : out std_logic_vector(0 to CFG_CAN_NUM-1);
can_rxd : in std_logic_vector(0 to CFG_CAN_NUM-1);
-- can_stb : out std_logic_vector(0 to CFG_CAN_NUM-1)
spw_clk : in std_logic;
spw_rxdp : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxdn : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxsp : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxsn : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txdp : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txdn : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txsp : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txsn : out std_logic_vector(0 to CFG_SPW_NUM-1)
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, pciclk, sdclkl : std_logic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal sysi : leon_dsu_stat_base_in_type;
signal syso : leon_dsu_stat_base_out_type;
signal perf : l3stat_in_type;
signal pcii : pci_in_type;
signal pcio : pci_out_type;
signal spwi : grspw_in_type_vector(0 to CFG_SPW_NUM-1);
signal spwo : grspw_out_type_vector(0 to CFG_SPW_NUM-1);
signal spw_rxclk : std_logic_vector(0 to CFG_SPW_NUM-1);
signal dtmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal stmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_rxtxclk : std_ulogic;
signal spw_rxclkn : std_ulogic;
signal spw_clkl : std_logic;
signal stati : ahbstat_in_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal wdog : std_logic;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal can_lrx, can_ltx : std_logic_vector(0 to 7);
signal lclk, pci_lclk : std_logic;
signal pci_arb_req_n, pci_arb_gnt_n : std_logic_vector(0 to 3);
signal pci_dirq : std_logic_vector(3 downto 0);
signal tck, tms, tdi, tdo : std_logic;
signal fpi : grfpu_in_vector_type;
signal fpo : grfpu_out_vector_type;
constant BOARD_FREQ : integer := 50000; -- Board frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := CFG_CAN + CFG_PCI + CFG_GRPCI2_MASTER + CFG_SDCTRL;
constant CFG_SDEN : integer := CFG_MCTRL_SDEN + CFG_SDCTRL;
constant CFG_INVCLK : integer := CFG_MCTRL_INVCLK;
constant OEPOL : integer := padoen_polarity(padtech);
----------------------------------------------------------------------
--- FIR component declaration --------------------------------------
----------------------------------------------------------------------
component fir_ahb_dma_apb is
generic (
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
technology : integer := virtex4);
port (
clk : in std_logic;
rstn : in std_logic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbin : in ahb_mst_in_type;
ahbout : out ahb_mst_out_type;
rm_reset: in std_logic
);
end component;
signal rm_reset : std_logic_vector(31 downto 0);
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
pllref_pad : clkpad generic map (tech => padtech) port map (pllref, cgi.pllref);
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
pci_clk_pad : clkpad generic map (tech => padtech, level => pci33)
port map (pci_clk, pci_lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_SDEN,
CFG_INVCLK, CFG_PCI+CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET, CFG_PCIDLL, CFG_PCISYSCLK, BOARD_FREQ)
port map (lclk, pci_lclk, clkm, open, open, sdclkl, pciclk, cgi, cgo);
sdclk_pad : outpad generic map (tech => padtech)
port map (sdclk, sdclkl);
rst0 : rstgen -- reset generator
port map (resetn, clkm, cgo.clklock, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => IOAEN,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_NUM+2*CFG_PRC, -- CFG_PRC if FIR core not included,
nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON processor and DSU -----------------------------------------
----------------------------------------------------------------------
leon : leon_dsu_stat_base
generic map (
leon => CFG_LEON, ncpu => CFG_NCPU, fabtech => fabtech, memtech => memtech,
nwindows => CFG_NWIN, dsu => CFG_DSU, fpu => CFG_FPU, v8 => CFG_V8, cp => 0,
mac => CFG_MAC, pclow => pclow, notag => 0, nwp => CFG_NWP, icen => CFG_ICEN,
irepl => CFG_IREPL, isets => CFG_ISETS, ilinesize => CFG_ILINE,
isetsize => CFG_ISETSZ, isetlock => CFG_ILOCK, dcen => CFG_DCEN,
drepl => CFG_DREPL, dsets => CFG_DSETS, dlinesize => CFG_DLINE,
dsetsize => CFG_DSETSZ, dsetlock => CFG_DLOCK, dsnoop => CFG_DSNOOP,
ilram => CFG_ILRAMEN, ilramsize => CFG_ILRAMSZ, ilramstart => CFG_ILRAMADDR,
dlram => CFG_DLRAMEN, dlramsize => CFG_DLRAMSZ, dlramstart => CFG_DLRAMADDR,
mmuen => CFG_MMUEN, itlbnum => CFG_ITLBNUM, dtlbnum => CFG_DTLBNUM,
tlb_type => CFG_TLB_TYPE, tlb_rep => CFG_TLB_REP, lddel => CFG_LDDEL,
disas => disas, tbuf => CFG_ITBSZ, pwd => CFG_PWD, svt => CFG_SVT,
rstaddr => CFG_RSTADDR, smp => CFG_NCPU-1, cached => CFG_DFIXED,
wbmask => CFG_BWMASK, busw => CFG_CACHEBW, netlist => CFG_LEON_NETLIST,
ft => CFG_LEONFT_EN, npasi => CFG_NP_ASI, pwrpsr => CFG_WRPSR,
rex => CFG_REX, altwin => CFG_ALTWIN, grfpush => CFG_GRFPUSH,
dsu_hindex => 2, dsu_haddr => 16#900#, dsu_hmask => 16#F00#, atbsz => CFG_ATBSZ,
stat => CFG_STAT_ENABLE, stat_pindex => 12, stat_paddr => 16#100#,
stat_pmask => 16#ffc#, stat_ncnt => CFG_STAT_CNT, stat_nmax => CFG_STAT_NMAX)
port map (
rstn => rstn, ahbclk => clkm, cpuclk => clkm, hclken => vcc(0),
leon_ahbmi => ahbmi, leon_ahbmo => ahbmo(CFG_NCPU-1 downto 0),
leon_ahbsi => ahbsi, leon_ahbso => ahbso,
irqi => irqi, irqo => irqo,
stat_apbi => apbi, stat_apbo => apbo(12), stat_ahbsi => ahbsi,
stati => perf,
dsu_ahbsi => ahbsi, dsu_ahbso => ahbso(2),
dsu_tahbmi => ahbmi, dsu_tahbsi => ahbsi,
sysi => sysi, syso => syso);
perf <= l3stat_in_none;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, syso.proc_error);
dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, sysi.dsu_enable);
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, sysi.dsu_break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, syso.dsu_active);
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
end generate;
-- nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.edac <= gpioo.val(2); memi.bwidth <= gpioo.val(1 downto 0);
mctrl0 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
srbanks => 4, sden => CFG_MCTRL_SDEN, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, invclk => CFG_MCTRL_INVCLK,
sepbus => CFG_MCTRL_SEPBUS, oepol => OEPOL,
sdbits => 32 + 32*CFG_MCTRL_SD64, pageburst => CFG_MCTRL_PAGE)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
addr_pad : outpadv generic map (width => 28, tech => padtech)
port map (address, memo.address(27 downto 0));
rams_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramsn, memo.ramsn(4 downto 0));
roms_pad : outpadv generic map (width => 2, tech => padtech)
port map (romsn, memo.romsn(1 downto 0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
rwen_pad : outpadv generic map (width => 4, tech => padtech)
port map (rwen, memo.wrn);
roen_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramoen, memo.ramoen(4 downto 0));
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
read_pad : outpad generic map (tech => padtech)
port map (read, memo.read);
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
data_pad : iopadvv generic map (tech => padtech, width => 32, oepol => OEPOL)
port map (data, memo.data, memo.vbdrive, memi.data);
brdyn_pad : inpad generic map (tech => padtech) port map (brdyn, memi.brdyn);
bexcn_pad : inpad generic map (tech => padtech) port map (bexcn, memi.bexcn);
memi.writen <= '1'; memi.wrn <= "1111";
sdpads : if CFG_MCTRL_SDEN = 1 generate -- SDRAM controller
sd2 : if CFG_MCTRL_SEPBUS = 1 generate
sa_pad : outpadv generic map (width => 15) port map (sa, memo.sa);
sd_pad : iopadvv generic map (tech => padtech, width => 32, oepol => OEPOL)
port map (sd(31 downto 0), memo.sddata(31 downto 0),
memo.svbdrive(31 downto 0), memi.sd(31 downto 0));
sd2 : if CFG_MCTRL_SD64 = 1 generate
sd_pad2 : iopadvv generic map (tech => padtech, width => 32)
port map (sd(63 downto 32), memo.data(31 downto 0),
memo.svbdrive(63 downto 32), memi.sd(63 downto 32));
end generate;
end generate;
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo.sdwen);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo.casn);
sddqm_pad : outpadv generic map (width => 8, tech => padtech)
port map (sddqm, sdo.dqm);
sdcke_pad : outpadv generic map (width => 2, tech => padtech)
port map (sdcke, sdo.sdcke);
sdcsn_pad : outpadv generic map (width => 2, tech => padtech)
port map (sdcsn, sdo.sdcsn);
end generate;
end generate;
ftmctrl0 : if CFG_MCTRLFT = 1 generate -- LEON2 memory controller
sr1 : ftmctrl generic map (hindex => 0, pindex => 0,
paddr => 0, srbanks => 4, sden => CFG_MCTRLFT_SDEN, ram8 => CFG_MCTRLFT_RAM8BIT,
ram16 => CFG_MCTRLFT_RAM16BIT, invclk => CFG_MCTRLFT_INVCLK,
sepbus => CFG_MCTRLFT_SEPBUS, oepol => OEPOL, edac => CFG_MCTRLFT_EDAC)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
addr_pad : outpadv generic map (width => 28, tech => padtech)
port map (address, memo.address(27 downto 0));
rams_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramsn, memo.ramsn(4 downto 0));
roms_pad : outpadv generic map (width => 2, tech => padtech)
port map (romsn, memo.romsn(1 downto 0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
rwen_pad : outpadv generic map (width => 4, tech => padtech)
port map (rwen, memo.wrn);
roen_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramoen, memo.ramoen(4 downto 0));
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
read_pad : outpad generic map (tech => padtech)
port map (read, memo.read);
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
data_pad : iopadvv generic map (tech => padtech, width => 32, oepol => OEPOL)
port map (data, memo.data, memo.vbdrive, memi.data);
cb_pad : iopadvv generic map (tech => padtech, width => 8, oepol => OEPOL)
port map (cb, memo.cb(7 downto 0), memo.vcdrive(7 downto 0), memi.cb(7 downto 0));
brdyn_pad : inpad generic map (tech => padtech) port map (brdyn, memi.brdyn);
bexcn_pad : inpad generic map (tech => padtech) port map (bexcn, memi.bexcn);
memi.writen <= '1'; memi.wrn <= "1111";
sdpads : if CFG_MCTRLFT_SDEN = 1 generate -- SDRAM controller
sd2 : if CFG_MCTRLFT_SEPBUS = 1 generate
sa_pad : outpadv generic map (width => 15) port map (sa, memo.sa);
sd_pad : iopadvv generic map (tech => padtech, width => 32, oepol => OEPOL)
port map (sd(31 downto 0), memo.sddata(31 downto 0),
memo.svbdrive(31 downto 0), memi.sd(31 downto 0));
scb_pad : iopadvv generic map (tech => padtech, width => 8, oepol => OEPOL)
-- port map (scb, memo.scb(7 downto 0), memo.svcdrive(7 downto 0), memi.scb(7 downto 0));
port map (sd(39 downto 32), memo.scb(7 downto 0), memo.svcdrive(7 downto 0), memi.scb(7 downto 0));
end generate;
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo.sdwen);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo.casn);
sddqm_pad : outpadv generic map (width =>8, tech => padtech)
port map (sddqm, sdo.dqm);
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, sdo.sdcke);
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, sdo.sdcsn);
end generate;
end generate;
nosd0 : if (CFG_SDEN = 0) generate -- no SDRAM controller
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, vcc(1 downto 0));
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, vcc(1 downto 0));
end generate;
mg0 : if CFG_MCTRL_LEON2 + CFG_MCTRLFT = 0 generate -- No PROM/SRAM controller
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
rams_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramsn, vcc);
roms_pad : outpadv generic map (width => 2, tech => padtech)
port map (romsn, vcc(1 downto 0));
end generate;
-- sdc : if CFG_SDCTRL = 1 generate
-- sdc : sdctrl64 generic map (hindex => 3, haddr => 16#400#, hmask => 16#C00#,
-- ioaddr => 1, fast => 0, pwron => 0, invclk => CFG_SDCTRL_INVCLK
---- , sdbits => 32 + 32*CFG_SDCTRL_SD64
-- )
-- port map (rstn, clkm, ahbsi2, ahbso2(3), sdi, sdo2);
-- sa_pad : outpadv generic map (width => 15, tech => padtech)
-- port map (sa, sdo2.address);
-- sd_pad : iopadv generic map (width => 32, tech => padtech)
-- port map (sd(31 downto 0), sdo2.data(31 downto 0), sdo2.bdrive, sdi.data(31 downto 0));
-- sd2 : if CFG_SDCTRL_SD64 = 1 generate
-- sd_pad2 : iopadv generic map (width => 32)
-- port map (sd(63 downto 32), sdo2.data(63 downto 32), sdo2.bdrive, sdi.data(63 downto 32));
-- end generate;
-- sdcke_pad : outpadv generic map (width =>2, tech => padtech)
-- port map (sdcke, sdo2.sdcke);
-- sdwen_pad : outpad generic map (tech => padtech)
-- port map (sdwen, sdo2.sdwen);
-- sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
-- port map (sdcsn, sdo2.sdcsn);
-- sdras_pad : outpad generic map (tech => padtech)
-- port map (sdrasn, sdo2.rasn);
-- sdcas_pad : outpad generic map (tech => padtech)
-- port map (sdcasn, sdo2.casn);
-- sddqm_pad : outpadv generic map (width =>8, tech => padtech)
-- port map (sddqm, sdo2.dqm(7 downto 0));
-- end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0';
rxd1_pad : inpad generic map (tech => padtech) port map (rxd1, u1i.rxd);
cts1_pad : inpad generic map (tech => padtech) port map (cts1, u1i.ctsn);
txd1_pad : outpad generic map (tech => padtech) port map (txd1, u1o.txd);
rts1_pad : outpad generic map (tech => padtech) port map (rts1, u1o.rtsn);
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
ua2 : if CFG_UART2_ENABLE /= 0 generate
uart2 : apbuart -- UART 2
generic map (pindex => 9, paddr => 9, pirq => 3, fifosize => CFG_UART2_FIFO)
port map (rstn, clkm, apbi, apbo(9), u2i, u2o);
u2i.extclk <= '0';
rxd2_pad : inpad generic map (tech => padtech) port map (rxd2, u2i.rxd);
cts2_pad : inpad generic map (tech => padtech) port map (cts2, u2i.ctsn);
txd2_pad : outpad generic map (tech => padtech) port map (txd2, u2o.txd);
rts2_pad : outpad generic map (tech => padtech) port map (rts2, u2o.rtsn);
end generate;
noua1 : if CFG_UART2_ENABLE = 0 generate apbo(9) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
-- apbo(2) <= apb_none;
end generate;
pci_dirq(3 downto 1) <= (others => '0');
pci_dirq(0) <= orv(irqi(0).irl);
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW, wdog => CFG_GPT_WDOG)
port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
gpti <= gpti_dhalt_drive(syso.dsu_tstop);
wdog <= gpto.wdogn when OEPOL = 0 else gpto.wdog;
wdogn_pad : odpad generic map (tech => padtech, oepol => OEPOL) port map (wdogn, wdog);
end generate;
-- notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
grgpio0: grgpio
generic map( pindex => 6, paddr => 6, imask => CFG_GRGPIO_IMASK,
nbits => CFG_GRGPIO_WIDTH)
port map( rstn, clkm, apbi, apbo(6), gpioi, gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
stati.cerror(0) <= memo.ce;
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 1,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
nop2 : if CFG_AHBSTAT = 0 generate apbo(15) <= apb_none; end generate;
-----------------------------------------------------------------------
--- PCI ------------------------------------------------------------
-----------------------------------------------------------------------
pci : if (CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET) /= 0 or CFG_PCI /= 0 generate
grpci2x : if (CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET) /= 0 and (CFG_PCI+CFG_GRPCI2_DMA) = 0 generate
pci0 : grpci2
generic map (
memtech => memtech,
oepol => OEPOL,
hmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
hdmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1,
hsindex => 4,
haddr => 16#C00#,
hmask => 16#E00#,
ioaddr => 16#000#,
pindex => 4,
paddr => 4,
irq => 4,
irqmode => 0,
master => CFG_GRPCI2_MASTER,
target => CFG_GRPCI2_TARGET,
dma => CFG_GRPCI2_DMA,
tracebuffer => CFG_GRPCI2_TRACE,
vendorid => CFG_GRPCI2_VID,
deviceid => CFG_GRPCI2_DID,
classcode => CFG_GRPCI2_CLASS,
revisionid => CFG_GRPCI2_RID,
cap_pointer => CFG_GRPCI2_CAP,
ext_cap_pointer => CFG_GRPCI2_NCAP,
iobase => CFG_AHBIO,
extcfg => CFG_GRPCI2_EXTCFG,
bar0 => CFG_GRPCI2_BAR0,
bar1 => CFG_GRPCI2_BAR1,
bar2 => CFG_GRPCI2_BAR2,
bar3 => CFG_GRPCI2_BAR3,
bar4 => CFG_GRPCI2_BAR4,
bar5 => CFG_GRPCI2_BAR5,
fifo_depth => CFG_GRPCI2_FDEPTH,
fifo_count => CFG_GRPCI2_FCOUNT,
conv_endian => CFG_GRPCI2_ENDIAN,
deviceirq => CFG_GRPCI2_DEVINT,
deviceirqmask => CFG_GRPCI2_DEVINTMSK,
hostirq => CFG_GRPCI2_HOSTINT,
hostirqmask => CFG_GRPCI2_HOSTINTMSK,
nsync => 2,
hostrst => 1,
bypass => CFG_GRPCI2_BYPASS,
debug => 0,
tbapben => 0,
tbpindex => 5,
tbpaddr => 16#400#,
tbpmask => 16#C00#
)
port map (
rstn, clkm, pciclk, pci_dirq, pcii, pcio, apbi, apbo(4), ahbsi, ahbso(4), ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbmi,
open, open, open, open, open);
end generate;
grpci2xd : if (CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET) /= 0 and CFG_PCI = 0 and
CFG_GRPCI2_DMA /= 0 generate
pci0 : grpci2
generic map (
memtech => memtech,
oepol => OEPOL,
hmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
hdmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1,
hsindex => 4,
haddr => 16#C00#,
hmask => 16#E00#,
ioaddr => 16#000#,
pindex => 4,
paddr => 4,
irq => 4,
irqmode => 0,
master => CFG_GRPCI2_MASTER,
target => CFG_GRPCI2_TARGET,
dma => CFG_GRPCI2_DMA,
tracebuffer => CFG_GRPCI2_TRACE,
vendorid => CFG_GRPCI2_VID,
deviceid => CFG_GRPCI2_DID,
classcode => CFG_GRPCI2_CLASS,
revisionid => CFG_GRPCI2_RID,
cap_pointer => CFG_GRPCI2_CAP,
ext_cap_pointer => CFG_GRPCI2_NCAP,
iobase => CFG_AHBIO,
extcfg => CFG_GRPCI2_EXTCFG,
bar0 => CFG_GRPCI2_BAR0,
bar1 => CFG_GRPCI2_BAR1,
bar2 => CFG_GRPCI2_BAR2,
bar3 => CFG_GRPCI2_BAR3,
bar4 => CFG_GRPCI2_BAR4,
bar5 => CFG_GRPCI2_BAR5,
fifo_depth => CFG_GRPCI2_FDEPTH,
fifo_count => CFG_GRPCI2_FCOUNT,
conv_endian => CFG_GRPCI2_ENDIAN,
deviceirq => CFG_GRPCI2_DEVINT,
deviceirqmask => CFG_GRPCI2_DEVINTMSK,
hostirq => CFG_GRPCI2_HOSTINT,
hostirqmask => CFG_GRPCI2_HOSTINTMSK,
nsync => 2,
hostrst => 1,
bypass => CFG_GRPCI2_BYPASS,
debug => 0,
tbapben => 0,
tbpindex => 5,
tbpaddr => 16#400#,
tbpmask => 16#C00#
)
port map (
rstn, clkm, pciclk, pci_dirq, pcii, pcio, apbi, apbo(4), ahbsi, ahbso(4), ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1),
open, open, open, open);
end generate;
grpci1x : if (CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET) = 0 and CFG_PCI /= 0 generate
pci_gr0 : if CFG_PCI = 1 generate -- simple target-only
pci0 : pci_target generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
device_id => CFG_PCIDID, vendor_id => CFG_PCIVID)
port map (rstn, clkm, pciclk, pcii, pcio, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG));
end generate;
pci_mtf0 : if CFG_PCI = 2 generate -- master/target with fifo
pci0 : pci_mtf generic map (memtech => memtech, hmstndx => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
fifodepth => log2(CFG_PCIDEPTH), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
hslvndx => 4, pindex => 4, paddr => 4, haddr => 16#E00#,
ioaddr => 16#400#, nsync => 2, hostrst => 1)
port map (rstn, clkm, pciclk, pcii, pcio, apbi, apbo(4),
ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4));
end generate;
pci_mtf1 : if CFG_PCI = 3 generate -- master/target with fifo and DMA
dma : pcidma generic map (memtech => memtech, dmstndx => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1,
dapbndx => 5, dapbaddr => 5, blength => blength, mstndx => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
fifodepth => log2(fifodepth), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
slvndx => 4, apbndx => 4, apbaddr => 4, haddr => 16#E00#, ioaddr => 16#800#,
nsync => 2, hostrst => 1)
port map (rstn, clkm, pciclk, pcii, pcio, apbo(5), ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1),
apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4));
end generate;
end generate;
pci_trc0 : if CFG_PCITBUFEN /= 0 generate -- PCI trace buffer
pt0 : pcitrace generic map (depth => (6 + log2(CFG_PCITBUF/256)),
memtech => memtech, pindex => 13, paddr => 16#100#, pmask => 16#f00#)
port map ( rstn, clkm, pciclk, pcii, apbi, apbo(13));
end generate;
pcia0 : if CFG_PCI_ARB = 1 generate -- PCI arbiter
pciarb0 : pciarb generic map (pindex => 8, paddr => 8,
apb_en => CFG_PCI_ARBAPB)
port map ( clk => pciclk, rst_n => pcii.rst,
req_n => pci_arb_req_n, frame_n => pcii.frame,
gnt_n => pci_arb_gnt_n, pclk => clkm,
prst_n => rstn, apbi => apbi, apbo => apbo(8)
);
pgnt_pad : outpadv generic map (tech => padtech, width => 4)
port map (pci_arb_gnt, pci_arb_gnt_n);
preq_pad : inpadv generic map (tech => padtech, width => 4)
port map (pci_arb_req, pci_arb_req_n);
end generate;
pcipads0 : pcipads generic map (padtech => padtech, host => 1, oepol => OEPOL,
noreset => 0, drivereset => 0, int => 10) -- PCI pads
port map ( pci_rst, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr,
pci_par, pci_req, pci_serr, pci_host, pci_66, pcii, pcio, pci_int);
end generate;
-- nop1 : if CFG_PCI <= 1 generate apbo(4) <= apb_none; end generate;
-- nop2 : if CFG_PCI <= 2 generate apbo(5) <= apb_none; end generate;
-- nop3 : if CFG_PCI <= 1 generate ahbso(4) <= ahbs_none; end generate;
-- notrc : if CFG_PCITBUFEN = 0 generate apbo(8) <= apb_none; end generate;
-- noarb : if CFG_PCI_ARB = 0 generate apbo(10) <= apb_none; end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : greth generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+log2x(CFG_PCI)+CFG_AHB_JTAG,
pindex => 14, paddr => 14, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+log2x(CFG_PCI)+CFG_AHB_JTAG), apbi => apbi,
apbo => apbo(14), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : inpad generic map (tech => padtech)
port map (etx_clk, ethi.tx_clk);
erxc_pad : inpad generic map (tech => padtech)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
emdintn_pad : inpad generic map (tech => padtech)
port map (emdintn, ethi.mdint);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
-- emdis_pad : outpad generic map (tech => padtech)
-- port map (emddis, vcc(0));
-- eepwrdwn_pad : outpad generic map (tech => padtech)
-- port map (epwrdwn, gnd(0));
-- esleep_pad : outpad generic map (tech => padtech)
-- port map (esleep, gnd(0));
-- epause_pad : outpad generic map (tech => padtech)
-- port map (epause, gnd(0));
-- ereset_pad : outpad generic map (tech => padtech)
-- port map (ereset, gnd(0));
end generate;
-----------------------------------------------------------------------
--- CAN --------------------------------------------------------------
-----------------------------------------------------------------------
can0 : if CFG_CAN = 1 generate
can0 : can_mc generic map (slvndx => 6, ioaddr => CFG_CANIO,
iomask => 16#FF0#, irq => CFG_CANIRQ, memtech => memtech,
ncores => CFG_CAN_NUM, sepirq => CFG_CANSEPIRQ)
port map (rstn, clkm, ahbsi, ahbso(6), can_lrx, can_ltx );
can_pads : for i in 0 to CFG_CAN_NUM-1 generate
can_tx_pad : outpad generic map (tech => padtech)
port map (can_txd(i), can_ltx(i));
can_rx_pad : inpad generic map (tech => padtech)
port map (can_rxd(i), can_lrx(i));
end generate;
end generate;
-- can_stb <= '0'; -- no standby
ncan : if CFG_CAN = 0 generate ahbso(6) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
-- ocram : if CFG_AHBRAMEN = 1 generate
-- ahbram0 : ftahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
-- tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pindex => 6,
-- paddr => 6, edacen => CFG_AHBRAEDAC, autoscrub => CFG_AHBRASCRU,
-- errcnten => CFG_AHBRAECNT, cntbits => CFG_AHBRAEBIT)
-- port map ( rstn, clkm, ahbsi, ahbso(7), apbi, apbo(6), open);
-- end generate;
--
-- nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- SPACEWIRE -------------------------------------------------------
-----------------------------------------------------------------------
spw : if CFG_SPW_EN > 0 generate
spw_clk_pad : clkpad generic map (tech => padtech) port map (spw_clk, spw_clkl);
-- spw_clkl <= pciclk;
spw_rxtxclk <= spw_clkl;
spw_rxclkn <= not spw_rxtxclk;
swloop : for i in 0 to CFG_SPW_NUM-1 generate
-- GRSPW2 PHY
spw2_input : if CFG_SPW_GRSPW = 2 generate
spw_phy0 : grspw2_phy
generic map(
scantest => 0,
tech => fabtech,
input_type => CFG_SPW_INPUT,
rxclkbuftype => 1)
port map(
rstn => rstn,
rxclki => spw_rxtxclk,
rxclkin => spw_rxclkn,
nrxclki => spw_rxtxclk,
di => dtmp(i),
si => stmp(i),
do => spwi(i).d(1 downto 0),
dov => spwi(i).dv(1 downto 0),
dconnect => spwi(i).dconnect(1 downto 0),
rxclko => spw_rxclk(i));
spwi(i).nd <= (others => '0'); -- Only used in GRSPW
spwi(i).dv(3 downto 2) <= "00"; -- For second port
end generate spw2_input;
-- GRSPW PHY
spw1_input: if CFG_SPW_GRSPW = 1 generate
spw_phy0 : grspw_phy
generic map(
tech => fabtech,
rxclkbuftype => 1,
scantest => 0)
port map(
rxrst => spwo(i).rxrst,
di => dtmp(i),
si => stmp(i),
rxclko => spw_rxclk(i),
do => spwi(i).d(0),
ndo => spwi(i).nd(4 downto 0),
dconnect => spwi(i).dconnect(1 downto 0));
spwi(i).d(1) <= '0';
spwi(i).dv <= (others => '0'); -- Only used in GRSPW2
spwi(i).nd(9 downto 5) <= "00000"; -- For second port
end generate spw1_input;
spwi(i).d(3 downto 2) <= "00"; -- For second port
spwi(i).dconnect(3 downto 2) <= "00"; -- For second port
spwi(i).s(1 downto 0) <= "00"; -- Only used in PHY
sw0 : grspwm generic map(tech => fabtech,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+i,
pindex => 10+i, paddr => 10+i, pirq => 5+i,
sysfreq => CPU_FREQ, nsync => 1, rmap => CFG_SPW_RMAP,
rmapcrc => CFG_SPW_RMAPCRC, fifosize1 => CFG_SPW_AHBFIFO,
fifosize2 => CFG_SPW_RXFIFO, rxclkbuftype => 1, memtech => memtech,
rmapbufs => CFG_SPW_RMAPBUF,ft => CFG_SPW_FT, ports => 1,
dmachan => CFG_SPW_DMACHAN, netlist => CFG_SPW_NETLIST, spwcore => CFG_SPW_GRSPW,
input_type => CFG_SPW_INPUT, output_type => CFG_SPW_OUTPUT,
rxtx_sameclk => CFG_SPW_RTSAME, rxunaligned => CFG_SPW_RXUNAL)
port map(rstn, clkm, spw_rxclk(i), spw_rxclk(i), spw_rxtxclk, spw_rxtxclk,
ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+i),
apbi, apbo(10+i), spwi(i), spwo(i));
spwi(i).tickin <= '0'; spwi(i).rmapen <= '0';
spwi(i).clkdiv10 <= conv_std_logic_vector(CPU_FREQ/10000-1, 8);
spwi(i).dcrstval <= (others => '0');
spwi(i).timerrstval <= (others => '0');
spw_rxd_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxdp(i), spw_rxdn(i), dtmp(i));
spw_rxs_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxsp(i), spw_rxsn(i), stmp(i));
spw_txd_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txdp(i), spw_txdn(i), spwo(i).d(0), gnd(0));
spw_txs_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txsp(i), spw_txsn(i), spwo(i).s(0), gnd(0));
end generate;
end generate;
-----------------------------------------------------------------------
--- DYNAMIC PARTIAL RECONFIGURATION ---------------------------------
-----------------------------------------------------------------------
prc : if CFG_PRC = 1 generate
p1 : dprc generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_NUM, pindex => 10+CFG_SPW_NUM, paddr => 10+CFG_SPW_NUM, edac_en => CFG_EDAC_EN,
pirq => 10+CFG_SPW_NUM, technology => CFG_FABTECH, crc_en => CFG_CRC_EN, words_block => CFG_WORDS_BLOCK, fifo_dcm_inst => CFG_DCM_FIFO, fifo_depth => CFG_DPR_FIFO)
port map(rstn => rstn, clkm => clkm, clkraw => lclk, clk100 => '0', ahbmi => ahbmi, ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH
+CFG_SPW_NUM), apbi => apbi, apbo => apbo(10+CFG_SPW_NUM), rm_reset => rm_reset);
--------------------------------------------------------------------
-- FIR component instantiation (for dprc demo) -------------------
--------------------------------------------------------------------
fir_ex : FIR_AHB_DMA_APB
generic map (hindex=>CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_NUM+CFG_PRC, pindex=>10+CFG_SPW_NUM+1, paddr=>10+CFG_SPW_NUM+1,
pmask=>16#fff#, technology =>CFG_FABTECH)
port map (rstn=>rstn, clk=>clkm, apbi=>apbi, apbo=>apbo(10+CFG_SPW_NUM+1), ahbin=>ahbmi, ahbout=>ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH
+CFG_SPW_NUM+CFG_PRC), rm_reset => rm_reset(0));
end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nam2 : if CFG_PCI > 1 generate
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+log2x(CFG_PCI)-1) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- apbo(6) <= apb_none;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 GR-CPCI-XC4V Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-3.0 | ffb0df1744c35c83b554844c53641122 | 0.545245 | 3.570506 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/grlib/amba/ahbmst.vhd | 1 | 5,778 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbmst
-- File: ahbmst.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Generic AHB master interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbmst is
generic (
hindex : integer := 0;
hirq : integer := 0;
venid : integer := VENDOR_GAISLER;
devid : integer := 0;
version : integer := 0;
chprot : integer := 3;
incaddr : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
dmai : in ahb_dma_in_type;
dmao : out ahb_dma_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type
);
end;
architecture rtl of ahbmst is
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( venid, devid, 0, version, 0),
others => zero32);
type reg_type is record
start : std_ulogic;
retry : std_ulogic;
grant : std_ulogic;
active : std_ulogic;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RES : reg_type := ('0', '0', '0', '0');
signal r, rin : reg_type;
begin
comb : process(ahbi, dmai, rst, r)
variable v : reg_type;
variable ready : std_ulogic;
variable retry : std_ulogic;
variable mexc : std_ulogic;
variable inc : std_logic_vector(5 downto 0); -- address increment
variable haddr : std_logic_vector(31 downto 0); -- AHB address
variable hwdata : std_logic_vector(AHBDW-1 downto 0); -- AHB write data
variable htrans : std_logic_vector(1 downto 0); -- transfer type
variable hwrite : std_ulogic; -- read/write
variable hburst : std_logic_vector(2 downto 0); -- burst type
variable newaddr : std_logic_vector(9 downto 0); -- next sequential address
variable hbusreq : std_ulogic; -- bus request
variable hprot : std_logic_vector(3 downto 0); -- transfer type
variable xhirq : std_logic_vector(NAHBIRQ-1 downto 0);
begin
v := r; ready := '0'; mexc := '0'; retry := '0'; inc := (others => '0');
hprot := conv_std_logic_vector(chprot, 4); -- non-cached supervisor data
xhirq := (others => '0'); xhirq(hirq) := dmai.irq;
haddr := dmai.address; hbusreq := dmai.start;
hwdata := dmai.wdata;
newaddr := dmai.address(9 downto 0);
if INCADDR > 0 then
inc(conv_integer(dmai.size)) := '1';
newaddr := haddr(9 downto 0) + inc;
end if;
if dmai.burst = '0' then hburst := HBURST_SINGLE;
else hburst := HBURST_INCR; end if;
if dmai.start = '1' then
if (r.active and dmai.burst and not r.retry) = '1' then
haddr(9 downto 0) := newaddr;
if dmai.busy = '1' then htrans := HTRANS_BUSY;
else htrans := HTRANS_SEQ; end if;
hburst := HBURST_INCR;
else htrans := HTRANS_NONSEQ; end if;
else htrans := HTRANS_IDLE; end if;
if r.active = '1' then
if ahbi.hready = '1' then
case ahbi.hresp is
when HRESP_OKAY => ready := '1';
when HRESP_RETRY | HRESP_SPLIT=> retry := '1';
when others => ready := '1'; mexc := '1';
end case;
end if;
if ((ahbi.hresp = HRESP_RETRY) or (ahbi.hresp = HRESP_SPLIT)) then
v.retry := not ahbi.hready;
else v.retry := '0'; end if;
end if;
if r.retry = '1' then htrans := HTRANS_IDLE; end if;
v.start := '0';
if ahbi.hready = '1' then
v.grant := ahbi.hgrant(hindex);
if (htrans = HTRANS_NONSEQ) or (htrans = HTRANS_SEQ) or (htrans = HTRANS_BUSY) then
v.active := r.grant; v.start := r.grant;
else
v.active := '0';
end if;
end if;
if (not RESET_ALL) and (rst = '0') then
v.retry := RES.retry; v.active := RES.active;
end if;
rin <= v;
ahbo.haddr <= haddr;
ahbo.htrans <= htrans;
ahbo.hbusreq <= hbusreq;
ahbo.hwdata <= hwdata;
ahbo.hconfig <= hconfig;
ahbo.hlock <= '0';
ahbo.hwrite <= dmai.write;
ahbo.hsize <= dmai.size;
ahbo.hburst <= hburst;
ahbo.hprot <= hprot;
ahbo.hirq <= xhirq;
ahbo.hindex <= hindex;
dmao.start <= r.start;
dmao.active <= r.active;
dmao.ready <= ready;
dmao.mexc <= mexc;
dmao.retry <= retry;
dmao.haddr <= newaddr;
dmao.rdata <= ahbi.hrdata;
end process;
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
if RESET_ALL and rst = '0' then
r <= RES;
end if;
end if;
end process;
end;
| gpl-3.0 | 8126b31b7c26145010c0eed92d9a1c41 | 0.580305 | 3.6 | false | false | false | false |
hoglet67/CoPro6502 | src/RAM/RAM_64K.vhd | 1 | 1,036 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity RAM_64K is
port (
clk : in std_logic;
we_uP : in std_logic;
ce : in std_logic;
addr_uP : in std_logic_vector (15 downto 0);
D_uP : in std_logic_vector (7 downto 0);
Q_uP : out std_logic_vector (7 downto 0));
end RAM_64K;
architecture BEHAVIORAL of RAM_64K is
type ram_type is array (65535 downto 0) of std_logic_vector (7 downto 0);
signal RAM : ram_type := (65535 downto 0 => X"ff");
attribute RAM_STYLE : string;
attribute RAM_STYLE of RAM : signal is "BLOCK";
begin
process (clk)
begin
if rising_edge(clk) then
if ce = '1' then
if we_UP = '1' then
RAM(conv_integer(addr_uP(15 downto 0))) <= D_up;
end if;
Q_up <= RAM(conv_integer(addr_uP(15 downto 0)));
end if;
end if;
end process;
end BEHAVIORAL;
| gpl-3.0 | e1dafe4a386b55b85038fcfc6d863ab1 | 0.527992 | 3.453333 | false | false | false | false |
hoglet67/CoPro6502 | src/LX9Co_CoPro6502fast.vhd | 1 | 16,300 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity LX9CoPro6502fast is
generic (
UseAlanDCore : boolean := false;
UseArletCore : boolean := true
);
port (
-- GOP Signals
fastclk : in std_logic;
test : inout std_logic_vector(8 downto 1);
sw : in std_logic_vector(3 downto 0);
-- Tube signals
h_phi2 : in std_logic;
h_addr : in std_logic_vector(2 downto 0);
h_data : inout std_logic_vector(7 downto 0);
h_rdnw : in std_logic;
h_cs_b : in std_logic;
h_rst_b : in std_logic;
h_irq_b : inout std_logic;
-- Ram Signals
ram_ub_b : out std_logic;
ram_lb_b : out std_logic;
ram_cs : out std_logic;
ram_oe : out std_logic;
ram_wr : out std_logic;
ram_addr : out std_logic_vector (18 downto 0);
ram_data : inout std_logic_vector (15 downto 0)
);
end LX9CoPro6502fast;
architecture BEHAVIORAL of LX9CoPro6502fast is
-------------------------------------------------
-- clock and reset signals
-------------------------------------------------
signal clk_cpu : std_logic;
signal cpu_clken : std_logic;
signal bootmode : std_logic;
signal RSTn : std_logic;
signal RSTn_sync : std_logic;
signal clken_counter : std_logic_vector (4 downto 0);
signal reset_counter : std_logic_vector (8 downto 0);
-------------------------------------------------
-- parasite signals
-------------------------------------------------
signal p_cs_b : std_logic;
signal bank_cs_b : std_logic;
signal p_data_out : std_logic_vector (7 downto 0);
-------------------------------------------------
-- ram/rom signals
-------------------------------------------------
signal ram_cs_b : std_logic;
signal rom_cs_b : std_logic;
signal rom_data_out : std_logic_vector (7 downto 0);
signal int_ram_data_out : std_logic_vector (7 downto 0);
signal ext_ram_data_out : std_logic_vector (7 downto 0);
-------------------------------------------------
-- bank registers and physical address bus
-------------------------------------------------
signal ext_ram : std_logic;
signal ext_ram_next : std_logic;
signal ext_ram_we : std_logic;
signal ext_ram_we_next : std_logic;
signal int_ram : std_logic;
signal int_ram_next : std_logic;
signal int_ram_we_next : std_logic;
signal physical_addr : std_logic_vector (20 downto 0);
signal physical_addr_next : std_logic_vector (20 downto 0);
-- bit 7 = 0 for internal RAM, 1 for external RAM
type bank_reg_type is array (0 to 7) of std_logic_vector (7 downto 0);
signal bank_reg : bank_reg_type;
-------------------------------------------------
-- cpu signals
-------------------------------------------------
signal debug_clk : std_logic;
signal cpu_R_W_n : std_logic;
signal cpu_addr : std_logic_vector (15 downto 0);
signal cpu_addr_us: unsigned (15 downto 0);
signal cpu_din : std_logic_vector (7 downto 0);
signal cpu_dout : std_logic_vector (7 downto 0);
signal cpu_dout_us: unsigned (7 downto 0);
signal cpu_IRQ_n : std_logic;
signal cpu_NMI_n : std_logic;
signal cpu_IRQ_n_sync : std_logic;
signal cpu_NMI_n_sync : std_logic;
signal sync : std_logic;
-- Lookahead (unregistered) signals
signal p_cs_b_next : std_logic;
signal bank_cs_b_next : std_logic;
signal ram_cs_b_next : std_logic;
signal rom_cs_b_next : std_logic;
signal cpu_dout_next : std_logic_vector (7 downto 0);
signal cpu_dout_next_us : unsigned (7 downto 0);
signal cpu_addr_next : std_logic_vector (15 downto 0);
signal cpu_addr_next_us : unsigned (15 downto 0);
signal cpu_we_next : std_logic;
signal cpu_R_W_n_next : std_logic;
signal digit1_cs_b : std_logic;
signal digit2_cs_b : std_logic;
signal digit1 : std_logic_vector (7 downto 0);
signal digit2 : std_logic_vector (7 downto 0);
signal sw_out : std_logic_vector (3 downto 0);
begin
---------------------------------------------------------------------
-- instantiated components
---------------------------------------------------------------------
inst_ICAP_config : entity work.ICAP_config port map (
fastclk => fastclk,
sw_in => sw,
sw_out => sw_out,
h_addr => h_addr,
h_cs_b => h_cs_b,
h_data => h_data,
h_phi2 => h_phi2,
h_rdnw => h_rdnw,
h_rst_b => h_rst_b
);
inst_dcm_cpu_clk : entity work.dcm_32_64 port map (
CLKIN_IN => fastclk,
CLK0_OUT => clk_cpu,
CLK0_OUT1 => open,
CLK2X_OUT => open
);
inst_tuberom : entity work.tuberom_65c102_banner port map (
CLK => clk_cpu,
ADDR => cpu_addr(10 downto 0),
DATA => rom_data_out
);
GenAlanDCore: if UseAlanDCore generate
inst_r65c02: entity work.r65c02 port map(
reset => RSTn_sync,
clk => clk_cpu,
enable => cpu_clken,
nmi_n => cpu_NMI_n_sync,
irq_n => cpu_IRQ_n_sync,
di => unsigned(cpu_din),
do_next => cpu_dout_next_us,
do => cpu_dout_us,
addr_next => cpu_addr_next_us,
addr => cpu_addr_us,
nwe_next => cpu_R_W_n_next,
nwe => cpu_R_W_n,
sync => sync,
sync_irq => open
);
cpu_dout <= std_logic_vector(cpu_dout_us);
cpu_addr <= std_logic_vector(cpu_addr_us);
cpu_dout_next <= std_logic_vector(cpu_dout_next_us);
cpu_addr_next <= std_logic_vector(cpu_addr_next_us);
end generate;
GenArletCore: if UseArletCore generate
inst_arlet_6502: entity work.cpu_65c02 port map(
clk => clk_cpu,
reset => not RSTn_sync,
AB => cpu_addr_next,
DI => cpu_din,
DO => cpu_dout_next,
WE => cpu_we_next,
IRQ => not cpu_IRQ_n_sync,
NMI => not cpu_NMI_n_sync,
RDY => cpu_clken
);
cpu_R_W_n_next <= not cpu_we_next;
process(clk_cpu)
begin
if rising_edge(clk_cpu) then
if cpu_clken = '1' then
cpu_addr <= cpu_addr_next;
cpu_dout <= cpu_dout_next;
cpu_R_W_n <= cpu_R_W_n_next;
end if;
end if;
end process;
end generate;
inst_tube: entity work.tube port map (
h_addr => h_addr,
h_cs_b => h_cs_b,
h_data => h_data,
h_phi2 => h_phi2,
h_rdnw => h_rdnw,
h_rst_b => h_rst_b,
h_irq_b => h_irq_b,
p_addr => cpu_addr(2 downto 0),
p_cs_b => not((not p_cs_b) and cpu_clken),
p_data_in => cpu_dout,
p_data_out => p_data_out,
p_rdnw => cpu_R_W_n,
p_phi2 => clk_cpu,
p_rst_b => RSTn,
p_nmi_b => cpu_NMI_n,
p_irq_b => cpu_IRQ_n
);
Inst_RAM_64K: entity work.RAM_64K PORT MAP(
clk => clk_cpu,
we_uP => int_ram_we_next,
ce => cpu_clken,
addr_uP => physical_addr_next(15 downto 0),
D_uP => cpu_dout_next,
Q_uP => int_ram_data_out
);
p_cs_b <= '0' when cpu_addr(15 downto 3) = 2#1111_1110_1111_1# else '1';
bank_cs_b <= '0' when cpu_addr(15 downto 3) = 2#1111_1110_1110_0# else '1';
rom_cs_b <= '0' when cpu_addr(15 downto 11) = "11111" and cpu_R_W_n = '1' and bootmode = '1' else '1';
digit1_cs_b <= '0' when rom_cs_b = '0' and cpu_addr(11 downto 0) = x"86F" else '1';
digit2_cs_b <= '0' when rom_cs_b = '0' and cpu_addr(11 downto 0) = x"870" else '1';
-- Original: Acorn TUBE 65C102 Co-Processor
-- Updated: Acorn TUBE 64MHz 65C102 Co-Pro
digit1 <= x"36" when sw_out(1 downto 0) = "11" else
x"31" when sw_out(1 downto 0) = "10" else
x"30";
digit2 <= x"33" when sw_out(1 downto 0) = "00" else
x"36" when sw_out(1 downto 0) = "10" else
x"34";
ram_cs_b <= '0' when bank_cs_b = '1' and p_cs_b = '1' and rom_cs_b = '1' else '1';
-- Look ahead versions of the chip selects
p_cs_b_next <= '0' when cpu_addr_next(15 downto 3) = 2#1111_1110_1111_1# else '1';
bank_cs_b_next <= '0' when cpu_addr_next(15 downto 3) = 2#1111_1110_1110_0# else '1';
rom_cs_b_next <= '0' when cpu_addr_next(15 downto 11) = "11111" and cpu_R_W_n_next = '1' and bootmode = '1' else '1';
ram_cs_b_next <= '0' when p_cs_b_next = '1' and bank_cs_b_next = '1' and rom_cs_b_next = '1' else '1';
cpu_din <=
p_data_out when p_cs_b = '0' else
digit1 when digit1_cs_b = '0' else
digit2 when digit2_cs_b = '0' else
rom_data_out when rom_cs_b = '0' else
int_ram_data_out when int_ram = '1' else
ext_ram_data_out when ext_ram = '1' else
x"f1";
--------------------------------------------------------
-- bank registers
--------------------------------------------------------
process (clk_cpu, RSTn_sync)
begin
if RSTn_sync = '0' then
bank_reg(0) <= x"00";
bank_reg(1) <= x"01";
bank_reg(2) <= x"02";
bank_reg(3) <= x"03";
bank_reg(4) <= x"04";
bank_reg(5) <= x"05";
bank_reg(6) <= x"06";
bank_reg(7) <= x"07";
elsif rising_edge(clk_cpu) then
if cpu_clken = '1' then
int_ram <= int_ram_next;
ext_ram <= ext_ram_next;
if bank_cs_b = '0' and cpu_R_W_n = '0' and bootmode = '0' then
bank_reg(conv_integer(cpu_addr(2 downto 0))) <= cpu_dout;
end if;
end if;
end if;
end process;
physical_addr_next <= bank_reg(conv_integer(cpu_addr_next(15 downto 13))) & cpu_addr_next(12 downto 0);
int_ram_next <= '1' when ram_cs_b_next = '0' and physical_addr_next(20) = '0' else
'0';
ext_ram_next <= '1' when ram_cs_b_next = '0' and physical_addr_next(20) = '1' else
'0';
int_ram_we_next <= '1' when int_ram_next = '1' and cpu_R_W_n_next = '0' else
'0';
ext_ram_we_next <= '1' when ext_ram_next = '1' and cpu_R_W_n_next = '0' else
'0';
--------------------------------------------------------
-- external Ram
--
-- note: dispite the naming, all control signals are active low
--------------------------------------------------------
process (clk_cpu)
begin
if rising_edge(clk_cpu) then
if cpu_clken = '1' then
ext_ram_we <= ext_ram_we_next;
physical_addr <= physical_addr_next;
end if;
end if;
end process;
-- With 4 wait states, an external RAM cycle lasts ~80ns
-- To provide some address setup/hold margin we generate
-- a gated write signal off the falling edge of the clock
-- which gives half a cycle of setup/hold margin
process (clk_cpu)
begin
if falling_edge(clk_cpu) then
if ext_ram_we = '1' and clken_counter > 0 then
ram_wr <= '0';
else
ram_wr <= '1';
end if;
end if;
end process;
ram_ub_b <= not physical_addr(19);
ram_lb_b <= physical_addr(19);
ram_cs <= not ext_ram;
ram_oe <= ext_ram_we;
ram_addr <= physical_addr(18 downto 0);
ram_data <= (cpu_dout & cpu_dout) when ext_ram_we = '1' else (others => 'Z');
ext_ram_data_out <= ram_data(15 downto 8) when physical_addr(19) = '1' else ram_data(7 downto 0);
--------------------------------------------------------
-- test signals
--------------------------------------------------------
-- default to hi-impedence, to avoid conflicts with
-- a Raspberry Pi connected to the test connector
test <= (others => 'Z');
--------------------------------------------------------
-- boot mode generator
--------------------------------------------------------
boot_gen : process(clk_cpu, RSTn_sync)
begin
if RSTn_sync = '0' then
bootmode <= '1';
elsif rising_edge(clk_cpu) then
if p_cs_b = '0' then
bootmode <= '0';
end if;
end if;
end process;
--------------------------------------------------------
-- power up reset
--------------------------------------------------------
reset_gen : process(clk_cpu)
begin
if rising_edge(clk_cpu) then
if (reset_counter(8) = '0') then
reset_counter <= reset_counter + 1;
end if;
RSTn_sync <= RSTn AND reset_counter(8);
end if;
end process;
--------------------------------------------------------
-- interrupt synchronization
--------------------------------------------------------
sync_gen : process(clk_cpu, RSTn_sync)
begin
if RSTn_sync = '0' then
cpu_NMI_n_sync <= '1';
cpu_IRQ_n_sync <= '1';
elsif rising_edge(clk_cpu) then
if (cpu_clken = '1') then
cpu_NMI_n_sync <= cpu_NMI_n;
cpu_IRQ_n_sync <= cpu_IRQ_n;
end if;
end if;
end process;
--------------------------------------------------------
-- clock enable generator
--------------------------------------------------------
clk_gen : process(clk_cpu)
begin
if rising_edge(clk_cpu) then
if clken_counter = 0 then
case sw_out(1 downto 0) is
when "11" =>
-- 64MHz
if rom_cs_b_next = '0' then
-- Add one wait state for ROM accesses
clken_counter <= "0" & x"1";
elsif ext_ram_next = '1' then
-- Add four wait states for external RAM accesses
clken_counter <= "0" & x"4";
else
-- Full speed ahead!
clken_counter <= "0" & x"0";
end if;
when "10" =>
-- 16MHz
if ext_ram_next = '1' then
-- Add four wait states for external RAM accesses
clken_counter <= "0" & x"4";
else
-- Quarter speed ahead!
clken_counter <= "0" & x"3";
end if;
when "01" =>
-- 4MHz
-- Running so slowly there is need to special case external RAM accesses
clken_counter <= "0" & x"F";
when "00" =>
-- 2.91MHz
-- Running so slowly there is need to special case external RAM accesses
clken_counter <= "1" & x"5";
when others =>
-- there are no others
end case;
else
clken_counter <= clken_counter - 1;
end if;
end if;
end process;
cpu_clken <= '1' when clken_counter = 0 else '0';
end BEHAVIORAL;
| gpl-3.0 | a2671e5b844f5b86d1498929cbf3ec27 | 0.439755 | 3.687783 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-digilent-atlys/config.vhd | 1 | 7,593 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := spartan6;
constant CFG_MEMTECH : integer := spartan6;
constant CFG_PADTECH : integer := spartan6;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := spartan6;
constant CFG_CLKMUL : integer := (2);
constant CFG_CLKDIV : integer := (4);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 1;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 4 + 64*0;
constant CFG_ATBSZ : integer := 4;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020765#;
constant CFG_ETH_ENL : integer := 16#003456#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 0;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDR2SP : integer := 1;
constant CFG_DDR2SP_INIT : integer := 1;
constant CFG_DDR2SP_FREQ : integer := 100;
constant CFG_DDR2SP_TRFC : integer := (130);
constant CFG_DDR2SP_DATAWIDTH : integer := (16);
constant CFG_DDR2SP_FTEN : integer := 0;
constant CFG_DDR2SP_FTWIDTH : integer := 0;
constant CFG_DDR2SP_COL : integer := (10);
constant CFG_DDR2SP_SIZE : integer := (128);
constant CFG_DDR2SP_DELAY0 : integer := (0);
constant CFG_DDR2SP_DELAY1 : integer := (0);
constant CFG_DDR2SP_DELAY2 : integer := (0);
constant CFG_DDR2SP_DELAY3 : integer := (0);
constant CFG_DDR2SP_DELAY4 : integer := (0);
constant CFG_DDR2SP_DELAY5 : integer := (0);
constant CFG_DDR2SP_DELAY6 : integer := (0);
constant CFG_DDR2SP_DELAY7 : integer := (0);
constant CFG_DDR2SP_NOSYNC : integer := 1;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 1;
constant CFG_AHBRSZ : integer := 16;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (32);
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 1;
constant CFG_VGA_ENABLE : integer := 1;
constant CFG_SVGA_ENABLE : integer := 0;
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 1;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#03#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 0;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := (1);
constant CFG_SPIMCTRL_ASCALER : integer := (8);
constant CFG_SPIMCTRL_PWRUPCNT : integer := (30000);
constant CFG_SPIMCTRL_OFFSET : integer := 16#0#;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-3.0 | 2afe80d6c8725078e902d5a53b3998d0 | 0.650072 | 3.561445 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/i2c/i2c2ahb_apb_gen.vhd | 1 | 5,376 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: i2c2ahb_apb_gen
-- File: i2c2ahb_apb_gen.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- Contact: [email protected]
-- Description: Generic wrapper for I2C-slave, see i2c2ahb_apb.vhd
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library gaisler;
use gaisler.i2c.all;
entity i2c2ahb_apb_gen is
generic (
ahbaddrh : integer := 0;
ahbaddrl : integer := 0;
ahbmaskh : integer := 0;
ahbmaskl : integer := 0;
resen : integer := 0;
-- APB configuration
pindex : integer := 0; -- slave bus index
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
-- I2C configuration
i2cslvaddr : integer range 0 to 127 := 0;
i2ccfgaddr : integer range 0 to 127 := 0;
oepol : integer range 0 to 1 := 0;
--
filter : integer range 2 to 512 := 2
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
--ahbi : in ahb_mst_in_type;
ahbi_hgrant : in std_ulogic;
ahbi_hready : in std_ulogic;
ahbi_hresp : in std_logic_vector(1 downto 0);
ahbi_hrdata : in std_logic_vector(AHBDW-1 downto 0);
--ahbo : out ahb_mst_out_type;
ahbo_hbusreq : out std_ulogic;
ahbo_hlock : out std_ulogic;
ahbo_htrans : out std_logic_vector(1 downto 0);
ahbo_haddr : out std_logic_vector(31 downto 0);
ahbo_hwrite : out std_ulogic;
ahbo_hsize : out std_logic_vector(2 downto 0);
ahbo_hburst : out std_logic_vector(2 downto 0);
ahbo_hprot : out std_logic_vector(3 downto 0);
ahbo_hwdata : out std_logic_vector(AHBDW-1 downto 0);
-- APB slave interface
apbi_psel : in std_ulogic;
apbi_penable : in std_ulogic;
apbi_paddr : in std_logic_vector(31 downto 0);
apbi_pwrite : in std_ulogic;
apbi_pwdata : in std_logic_vector(31 downto 0);
apbo_prdata : out std_logic_vector(31 downto 0);
apbo_irq : out std_logic;
-- I2C signals
--i2ci : in i2c_in_type;
i2ci_scl : in std_ulogic;
i2ci_sda : in std_ulogic;
--i2co : out i2c_out_type
i2co_scl : out std_ulogic;
i2co_scloen : out std_ulogic;
i2co_sda : out std_ulogic;
i2co_sdaoen : out std_ulogic;
i2co_enable : out std_ulogic
);
end entity i2c2ahb_apb_gen;
architecture rtl of i2c2ahb_apb_gen is
-- AHB signals
signal ahbi : ahb_mst_in_type;
signal ahbo : ahb_mst_out_type;
-- APB signals
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_type;
-- I2C signals
signal i2ci : i2c_in_type;
signal i2co : i2c_out_type;
begin
ahbi.hgrant(0) <= ahbi_hgrant;
ahbi.hgrant(1 to NAHBMST-1) <= (others => '0');
ahbi.hready <= ahbi_hready;
ahbi.hresp <= ahbi_hresp;
ahbi.hrdata <= ahbi_hrdata;
ahbo_hbusreq <= ahbo.hbusreq;
ahbo_hlock <= ahbo.hlock;
ahbo_htrans <= ahbo.htrans;
ahbo_haddr <= ahbo.haddr;
ahbo_hwrite <= ahbo.hwrite;
ahbo_hsize <= ahbo.hsize;
ahbo_hburst <= ahbo.hburst;
ahbo_hprot <= ahbo.hprot;
ahbo_hwdata <= ahbo.hwdata;
apbi.psel(0) <= apbi_psel;
apbi.psel(1 to NAPBSLV-1) <= (others => '0');
apbi.penable <= apbi_penable;
apbi.paddr <= apbi_paddr;
apbi.pwrite <= apbi_pwrite;
apbi.pwdata <= apbi_pwdata;
apbi.pirq <= (others => '0');
apbi.testen <= '0';
apbi.testrst <= '0';
apbi.scanen <= '0';
apbi.testoen <= '0';
apbo_prdata <= apbo.prdata;
apbo_irq <= apbo.pirq(0);
i2ci.scl <= i2ci_scl;
i2ci.sda <= i2ci_sda;
i2co_scl <= i2co.scl;
i2co_scloen <= i2co.scloen;
i2co_sda <= i2co.sda;
i2co_sdaoen <= i2co.sdaoen;
i2co_enable <= i2co.enable;
i2c0 : i2c2ahb_apb
generic map (
hindex => 0,
ahbaddrh => ahbaddrh, ahbaddrl => ahbaddrl,
ahbmaskh => ahbmaskh, ahbmaskl => ahbmaskl,
resen => resen,
pindex => 0, paddr => 0, pmask => 0, pirq => 0,
i2cslvaddr => i2cslvaddr, i2ccfgaddr => i2ccfgaddr,
oepol => oepol, filter => filter)
port map (rstn, clk, ahbi, ahbo, apbi, apbo, i2ci, i2co);
end architecture rtl;
| gpl-3.0 | 5aebb75843d238e6d08abf827fad31bd | 0.59003 | 3.264117 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-xilinx-ml605/testbench.vhd | 1 | 12,395 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
use work.debug.all;
use work.config.all;
use work.ml605.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 37
);
end;
architecture behav of testbench is
-- DDR3 Simulation parameters
constant SIM_BYPASS_INIT_CAL : string := "FAST";
-- # = "OFF" - Complete memory init &
-- calibration sequence
-- # = "SKIP" - Not supported
-- # = "FAST" - Complete memory init & use
-- abbreviated calib sequence
constant promfile : string := "prom.srec"; -- rom contents
constant ramfile : string := "ram.srec"; -- sdram contents
constant lresp : boolean := false;
constant ct : integer := clkperiod/2;
signal clk : std_logic := '0';
signal clk200p : std_logic := '1';
signal clk200n : std_logic := '0';
signal rst : std_logic := '0';
signal rstn1 : std_logic;
signal rstn2 : std_logic;
signal error : std_logic;
-- PROM flash
signal address : std_logic_vector(24 downto 0);
signal data : std_logic_vector(15 downto 0);
signal romsn : std_logic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal iosn : std_ulogic;
-- DDR3 memory
signal ddr3_dq : std_logic_vector(DQ_WIDTH-1 downto 0);
signal ddr3_dm : std_logic_vector(DM_WIDTH-1 downto 0);
signal ddr3_addr : std_logic_vector(ROW_WIDTH-1 downto 0);
signal ddr3_ba : std_logic_vector(BANK_WIDTH-1 downto 0);
signal ddr3_ras_n : std_logic;
signal ddr3_cas_n : std_logic;
signal ddr3_we_n : std_logic;
signal ddr3_reset_n : std_logic;
signal ddr3_cs_n : std_logic_vector((CS_WIDTH*nCS_PER_RANK)-1 downto 0);
signal ddr3_odt : std_logic_vector((CS_WIDTH*nCS_PER_RANK)-1 downto 0);
signal ddr3_cke : std_logic_vector(CKE_WIDTH-1 downto 0);
signal ddr3_dqs_p : std_logic_vector(DQS_WIDTH-1 downto 0);
signal ddr3_dqs_n : std_logic_vector(DQS_WIDTH-1 downto 0);
signal ddr3_tdqs_n : std_logic_vector(DQS_WIDTH-1 downto 0);
signal ddr3_ck_p : std_logic_vector(CK_WIDTH-1 downto 0);
signal ddr3_ck_n : std_logic_vector(CK_WIDTH-1 downto 0);
-- Debug support unit
signal dsubre : std_ulogic;
-- AHB Uart
signal dsurx : std_ulogic;
signal dsutx : std_ulogic;
-- APB Uart
signal urxd : std_ulogic;
signal utxd : std_ulogic;
-- Ethernet signals
signal etx_clk : std_ulogic;
signal erx_clk : std_ulogic;
signal erxdt : std_logic_vector(7 downto 0);
signal erx_dv : std_ulogic;
signal erx_er : std_ulogic;
signal erx_col : std_ulogic;
signal erx_crs : std_ulogic;
signal etxdt : std_logic_vector(7 downto 0);
signal etx_en : std_ulogic;
signal etx_er : std_ulogic;
signal emdc : std_ulogic;
signal emdio : std_logic;
signal emdint : std_logic;
signal egtx_clk : std_logic;
signal gmiiclk_p : std_logic := '1';
signal gmiiclk_n : std_logic := '0';
-- Output signals for LEDs
signal led : std_logic_vector(6 downto 0);
signal iic_scl_main, iic_sda_main : std_logic;
signal iic_scl_dvi, iic_sda_dvi : std_logic;
signal tft_lcd_data : std_logic_vector(11 downto 0);
signal tft_lcd_clk_p : std_logic;
signal tft_lcd_clk_n : std_logic;
signal tft_lcd_hsync : std_logic;
signal tft_lcd_vsync : std_logic;
signal tft_lcd_de : std_logic;
signal tft_lcd_reset_b : std_logic;
signal sysace_mpa : std_logic_vector(6 downto 0);
signal sysace_mpce : std_ulogic;
signal sysace_mpirq : std_ulogic;
signal sysace_mpoe : std_ulogic;
signal sysace_mpwe : std_ulogic;
signal sysace_d : std_logic_vector(7 downto 0);
signal clk_33 : std_ulogic := '0';
signal brdyn : std_ulogic;
---------------------pcie----------------------------------------------
signal cor_sys_reset_n : std_logic := '1';
signal ep_sys_clk_p : std_logic;
signal ep_sys_clk_n : std_logic;
signal rp_sys_clk : std_logic;
signal cor_pci_exp_txn : std_logic_vector(CFG_NO_OF_LANES-1 downto 0);
signal cor_pci_exp_txp : std_logic_vector(CFG_NO_OF_LANES-1 downto 0);
signal cor_pci_exp_rxn : std_logic_vector(CFG_NO_OF_LANES-1 downto 0);
signal cor_pci_exp_rxp : std_logic_vector(CFG_NO_OF_LANES-1 downto 0);
---------------------pcie end---------------------------------------------
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
clk200p <= not clk200p after 2.5 ns;
clk200n <= not clk200n after 2.5 ns;
gmiiclk_p <= not gmiiclk_p after 4 ns;
gmiiclk_n <= not gmiiclk_n after 4 ns;
clk_33 <= not clk_33 after 15 ns;
rst <= '1', '0' after 200 us;
rstn1 <= not rst;
dsubre <= '0';
urxd <= 'H';
d3 : entity work.leon3mp
generic map (fabtech, memtech, padtech, disas, dbguart, pclow,
SIM_BYPASS_INIT_CAL)
port map (
reset => rst,
errorn => error,
clk_ref_p => clk200p,
clk_ref_n => clk200n,
-- PROM
address => address(24 downto 1),
data => data(15 downto 0),
romsn => romsn,
oen => oen,
writen => writen,
-- DDR3
ddr3_dq => ddr3_dq,
ddr3_dm => ddr3_dm,
ddr3_addr => ddr3_addr,
ddr3_ba => ddr3_ba,
ddr3_ras_n => ddr3_ras_n,
ddr3_cas_n => ddr3_cas_n,
ddr3_we_n => ddr3_we_n,
ddr3_reset_n => ddr3_reset_n,
ddr3_cs_n => ddr3_cs_n,
ddr3_odt => ddr3_odt,
ddr3_cke => ddr3_cke,
ddr3_dqs_p => ddr3_dqs_p,
ddr3_dqs_n => ddr3_dqs_n,
ddr3_ck_p => ddr3_ck_p,
ddr3_ck_n => ddr3_ck_n,
-- Debug Unit
dsubre => dsubre,
-- AHB Uart
dsutx => dsutx,
dsurx => dsurx,
-- PHY
gmiiclk_p => gmiiclk_p,
gmiiclk_n => gmiiclk_n,
egtx_clk => egtx_clk,
etx_clk => etx_clk,
erx_clk => erx_clk,
erxd => erxdt(7 downto 0),
erx_dv => erx_dv,
erx_er => erx_er,
erx_col => erx_col,
erx_crs => erx_crs,
emdint => emdint,
etxd => etxdt(7 downto 0),
etx_en => etx_en,
etx_er => etx_er,
emdc => emdc,
emdio => emdio,
-- Output signals for LEDs
iic_scl_main => iic_scl_main,
iic_sda_main => iic_sda_main,
dvi_iic_scl => iic_scl_dvi,
dvi_iic_sda => iic_sda_dvi,
tft_lcd_data => tft_lcd_data,
tft_lcd_clk_p => tft_lcd_clk_p,
tft_lcd_clk_n => tft_lcd_clk_n,
tft_lcd_hsync => tft_lcd_hsync,
tft_lcd_vsync => tft_lcd_vsync,
tft_lcd_de => tft_lcd_de,
tft_lcd_reset_b => tft_lcd_reset_b,
clk_33 => clk_33,
sysace_mpa => sysace_mpa,
sysace_mpce => sysace_mpce,
sysace_mpirq => sysace_mpirq,
sysace_mpoe => sysace_mpoe,
sysace_mpwe => sysace_mpwe,
sysace_d => sysace_d,
pci_exp_txp=> cor_pci_exp_txp,
pci_exp_txn=> cor_pci_exp_txn,
pci_exp_rxp=> cor_pci_exp_rxp,
pci_exp_rxn=> cor_pci_exp_rxn,
sys_clk_p=> ep_sys_clk_p,
sys_clk_n=> ep_sys_clk_n,
sys_reset_n=> cor_sys_reset_n,
led => led
);
u1 : ddr3ram
generic map (
width => 64,
abits => 13,
colbits => 10,
rowbits => 13,
implbanks => 1,
fname => ramfile,
lddelay => (0 ns),
ldguard => 1,
speedbin => 9, --DDR3-1600K
density => 3,
pagesize => 1,
changeendian => 32)
port map (
ck => ddr3_ck_p(0),
ckn => ddr3_ck_n(0),
cke => ddr3_cke(0),
csn => ddr3_cs_n(0),
odt => ddr3_odt(0),
rasn => ddr3_ras_n,
casn => ddr3_cas_n,
wen => ddr3_we_n,
dm => ddr3_dm,
ba => ddr3_ba,
a => ddr3_addr,
resetn => ddr3_reset_n,
dq => ddr3_dq,
dqs => ddr3_dqs_p,
dqsn => ddr3_dqs_n,
doload => led(3)
);
address(0) <= '0';
prom0 : for i in 0 to 1 generate
sr0 : sram generic map (index => i+4, abits => 24, fname => promfile)
port map (address(24 downto 1), data(15-i*8 downto 8-i*8), romsn,
writen, oen);
end generate;
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
p0: phy
generic map (address => 7)
port map(rstn1, emdio, etx_clk, erx_clk, erxdt, erx_dv, erx_er,
erx_col, erx_crs, etxdt, etx_en, etx_er, emdc, egtx_clk);
end generate;
-- spimem0: if CFG_SPIMCTRL = 1 generate
-- s0 : spi_flash generic map (ftype => 4, debug => 0, fname => promfile,
-- readcmd => CFG_SPIMCTRL_READCMD,
-- dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
-- dualoutput => 0) -- Dual output is not supported in this design
-- port map (spi_clk, spi_mosi, data(24), spi_sel_n);
-- end generate spimem0;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 210 us; -- This is for proper DDR3 behaviour durign init phase not needed durin simulation
wait on led(3); -- DDR3 Memory Init ready
wait for 5000 ns;
assert (to_X01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure;
end process;
data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#ef#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
--
-- txc(dsutx, 16#80#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end;
| gpl-3.0 | 16a0a429ccceaae9d703c1bdb929379c | 0.551835 | 3.221154 | false | false | false | false |
pwsoft/fpga_examples | rtl/ttl/ttl_74590.vhd | 1 | 4,417 | -- -----------------------------------------------------------------------
--
-- Syntiac VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2020 by Peter Wendrich ([email protected])
-- http://www.syntiac.com
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
-- 8-bit binary counter with output register; 3-state
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.ttl_pkg.all;
-- -----------------------------------------------------------------------
entity ttl_74590 is
generic (
latency : integer := 3
);
port (
emuclk : in std_logic;
p1 : out ttl_t; -- Q1
p2 : out ttl_t; -- Q2
p3 : out ttl_t; -- Q3
p4 : out ttl_t; -- Q4
p5 : out ttl_t; -- Q5
p6 : out ttl_t; -- Q6
p7 : out ttl_t; -- Q7
p9 : out ttl_t; -- RCOn
p10 : in ttl_t; -- MRCn (counter reset)
p11 : in ttl_t; -- CPC (counter clock)
p12 : in ttl_t; -- CEn (clock enable of CPC)
p13 : in ttl_t; -- CPR (output register clock)
p14 : in ttl_t; -- OEn
p15 : out ttl_t -- Q0
);
end entity;
architecture rtl of ttl_74590 is
signal cpc_ena : std_logic;
signal cpr_ena : std_logic;
signal p1_loc : ttl_t;
signal p2_loc : ttl_t;
signal p3_loc : ttl_t;
signal p4_loc : ttl_t;
signal p5_loc : ttl_t;
signal p6_loc : ttl_t;
signal p7_loc : ttl_t;
signal p9_loc : ttl_t;
signal p15_loc : ttl_t;
signal counter_reg : unsigned(7 downto 0) := (others => '0');
signal output_reg : unsigned(7 downto 0) := (others => '0');
begin
cpc_edge_inst : entity work.ttl_edge
port map (emuclk => emuclk, edge => '1', d => p11, ena => cpc_ena);
cpr_edge_inst : entity work.ttl_edge
port map (emuclk=> emuclk, edge => '1', d => p13, ena => cpr_ena);
p1_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p1_loc, q => p1);
p2_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p2_loc, q => p2);
p3_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p3_loc, q => p3);
p4_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p4_loc, q => p4);
p5_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p5_loc, q => p5);
p6_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p6_loc, q => p6);
p7_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p7_loc, q => p7);
p9_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p9_loc, q => p9);
p15_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p15_loc, q => p15);
p1_loc <= std2ttl(output_reg(1));
p2_loc <= std2ttl(output_reg(2));
p3_loc <= std2ttl(output_reg(3));
p4_loc <= std2ttl(output_reg(4));
p5_loc <= std2ttl(output_reg(5));
p6_loc <= std2ttl(output_reg(6));
p7_loc <= std2ttl(output_reg(7));
p9_loc <= ZERO when counter_reg = X"FF" else ONE;
p15_loc <= std2ttl(output_reg(0));
process(emuclk)
begin
if rising_edge(emuclk) then
if (cpc_ena = '1') and is_low(p12) then
counter_reg <= counter_reg + 1;
end if;
if cpr_ena = '1' then
output_reg <= counter_reg;
end if;
if is_low(p10) then
-- Asynchronous reset, clears counter but not the output register
counter_reg <= (others => '0');
end if;
end if;
end process;
end architecture;
| lgpl-2.1 | d427943b854cc73b0cf962470916a81c | 0.587956 | 2.925166 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/maps/outpad.vhd | 1 | 5,981 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: outpad
-- File: outpad.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: output pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity outpad is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12);
port (pad : out std_ulogic; i : in std_ulogic;
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end;
architecture rtl of outpad is
signal padx, gnd, vcc : std_ulogic;
begin
gnd <= '0'; vcc <= '1';
gen0 : if has_pads(tech) = 0 generate
pad <= i
-- pragma translate_off
after 2 ns
-- pragma translate_on
when slew = 0 else i;
end generate;
xcv : if (is_unisim(tech) = 1) generate
x0 : unisim_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
axc : if (tech = axcel) or (tech = axdsp) generate
x0 : axcel_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
pa3 : if (tech = proasic) or (tech = apa3) generate
x0 : apa3_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
pa3e : if (tech = apa3e) generate
x0 : apa3e_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
igl2 : if (tech = igloo2) or (tech = rtg4) generate
x0 : igloo2_outpad port map (pad, i);
end generate;
pa3l : if (tech = apa3l) generate
x0 : apa3l_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
fus : if (tech = actfus) generate
x0 : fusion_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
atc : if (tech = atc18s) generate
x0 : atc18_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
atcrh : if (tech = atc18rha) generate
x0 : atc18rha_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
um : if (tech = umc) generate
x0 : umc_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
rhu : if (tech = rhumc) generate
x0 : rhumc_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
saed : if (tech = saed32) generate
x0 : saed32_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
rhs : if (tech = rhs65) generate
x0 : rhs65_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
dar : if (tech = dare) generate
x0 : dare_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
ihp : if (tech = ihp25) generate
x0 : ihp25_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
ihprh : if (tech = ihp25rh) generate
x0 : ihp25rh_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
rh18t : if (tech = rhlib18t) generate
x0 : rh_lib18t_iopad generic map (strength) port map (padx, i, gnd, open);
pad <= padx;
end generate;
ut025 : if (tech = ut25) generate
x0 : ut025crh_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
ut13 : if (tech = ut130) generate
x0 : ut130hbd_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
pere : if (tech = peregrine) generate
x0 : peregrine_toutpad generic map (level, slew, voltage, strength)
port map(pad, i, vcc);
end generate;
nex : if (tech = easic90) generate
x0 : nextreme_toutpad generic map (level, slew, voltage, strength)
port map(pad, i, vcc);
end generate;
n2x : if (tech = easic45) generate
x0 : n2x_outpad generic map (level, slew, voltage, strength)
port map(pad, i, cfgi(0), cfgi(1),
cfgi(19 downto 15), cfgi(14 downto 10), cfgi(9 downto 6), cfgi(5 downto 2));
end generate;
ut90nhbd : if (tech = ut90) generate
x0 : ut90nhbd_outpad generic map (level, slew, voltage, strength)
port map(pad, i, cfgi(0));
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity outpadv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 12; width : integer := 1);
port (
pad : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end;
architecture rtl of outpadv is
begin
v : for j in width-1 downto 0 generate
x0 : outpad generic map (tech, level, slew, voltage, strength)
port map (pad(j), i(j), cfgi);
end generate;
end;
| gpl-3.0 | f40e7dc7789628b9961df289e87f2c15 | 0.643371 | 3.530697 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/ddr/ddr2spax_ahb.vhd | 1 | 16,851 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr2spa_ahb
-- File: ddr2spa_ahb.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Asynch AHB interface for DDR memory controller
-- Based on ddr2sp(16/32/64)a, generalized and expanded
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
library gaisler;
use gaisler.ddrpkg.all;
use gaisler.ddrintpkg.all;
entity ddr2spax_ahb is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
burstlen : integer := 8;
nosync : integer := 0;
ahbbits : integer := ahbdw;
revision : integer := 0;
devid : integer := GAISLER_DDR2SP;
ddrbits : integer := 32;
regarea : integer := 0
);
port (
rst : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
request : out ddr_request_type;
start_tog: out std_logic;
response : in ddr_response_type;
wbwaddr : out std_logic_vector(log2(burstlen) downto 0);
wbwdata : out std_logic_vector(ahbbits-1 downto 0);
wbwrite : out std_logic;
wbwritebig: out std_logic;
rbraddr : out std_logic_vector(log2(burstlen*32/ahbbits)-1 downto 0);
rbrdata : in std_logic_vector(ahbbits-1 downto 0);
hwidth : in std_logic;
beid : in std_logic_vector(3 downto 0)
);
end ddr2spax_ahb;
architecture rtl of ddr2spax_ahb is
constant CMD_PRE : std_logic_vector(2 downto 0) := "010";
constant CMD_REF : std_logic_vector(2 downto 0) := "100";
constant CMD_LMR : std_logic_vector(2 downto 0) := "110";
constant CMD_EMR : std_logic_vector(2 downto 0) := "111";
constant ramwt: integer := 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, DEVID, 0, REVISION, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
5 => ahb_iobar(ioaddr, iomask),
others => zero32);
function zerov(w: integer) return std_logic_vector is
constant r: std_logic_vector(w-1 downto 0) := (others => '0');
begin
return r;
end zerov;
constant l2blen: integer := log2(burstlen)+log2(32);
constant l2ahbw: integer := log2(ahbbits);
constant l2ddrw: integer := log2(2*ddrbits);
-- Write buffer dimensions
-- Write buffer is addressable down to 32-bit level on write (AHB) side.
constant wbuf_wabits: integer := 1+l2blen-5; -- log2(burstlen);
constant wbuf_wdbits: integer := ahbbits;
-- Read buffer dimensions
constant rbuf_rabits: integer := l2blen-l2ahbw; -- log2(burstlen*32/ahbbits);
constant rbuf_rdbits: integer := ahbbits;
type ahbstate is (asnormal,asw1,asw2,asww1,asww2,aswr,aswwx);
type ahb_reg_type is record
s : ahbstate;
start_tog : std_logic;
ramaddr : std_logic_vector(l2blen-4 downto 2);
-- These are sent to the DDR layer
req : ddr_request_type;
-- Posted write following current request
nreq : ddr_request_type;
-- Read flow control
rctr_lin : std_logic_vector(3 downto 0);
endpos : std_logic_vector(7 downto log2(ddrbits/4));
block_read: std_logic_vector(1 downto 0);
-- Current AHB control signals
haddr : std_logic_vector(31 downto 0);
haddr_nonseq: std_logic_vector(9 downto 0);
hio : std_logic;
hsize : std_logic_vector(2 downto 0);
hwrite : std_logic;
hburst0 : std_logic;
-- AHB slave outputs
so_hready : std_logic;
-- From DDR layer
resp1,resp2: ddr_response_type;
end record;
signal ar,nar : ahb_reg_type;
begin
ahbcomb : process(ahbsi,rst,ar,response,rbrdata,hwidth,beid)
variable av: ahb_reg_type;
variable va2d: ddr_request_type;
variable so: ahb_slv_out_type;
variable vdone: std_logic;
variable vresp: ddr_response_type;
variable bigsize,midsize,canburst: std_logic;
variable inc_ramaddr: std_logic;
variable row: std_logic_vector(14 downto 0);
variable wbwa: std_logic_vector(wbuf_wabits-1 downto 0);
variable wbwd: std_logic_vector(wbuf_wdbits-1 downto 0);
variable wbw,wbwb: std_logic;
variable rbra: std_logic_vector(rbuf_rabits-1 downto 0);
variable ha0: std_logic_vector(31 downto 0);
variable rend,nrend: std_logic_vector(7 downto log2(ddrbits/4));
variable datavalid, writedone: std_logic;
variable rctr_gray: std_logic_vector(3 downto 0);
variable tog_start: std_logic;
variable regdata: std_logic_vector(31 downto 0);
begin
ha0 := ahbsi.haddr;
ha0(31 downto 20) := ha0(31 downto 20) and not std_logic_vector(to_unsigned(hmask,12));
av := ar;
so := (hready => ar.so_hready, hresp => HRESP_OKAY, hrdata => (others => '0'),
hsplit => (others => '0'), hirq => (others => '0'),
hconfig => hconfig, hindex => hindex);
wbw := '0';
wbwb := '0';
wbwa := ar.start_tog & ar.ramaddr;
wbwd := ahbreaddata(ahbsi.hwdata,ar.haddr(4 downto 2),
std_logic_vector(to_unsigned(log2(ahbbits/8),3)));
rbra := ar.ramaddr(l2blen-4 downto l2ahbw-3);
-- Determine whether the current hsize is a big (ahbbits-width) access
bigsize := '0';
if (ahbbits = 256 and ar.hsize(2)='1' and ar.hsize(0)='1') or
(ahbbits = 128 and ar.hsize(2)='1') or
(ahbbits = 64 and ar.hsize="011") then
bigsize := '1';
end if;
midsize := '0';
if ( (ahbbits = 256 and ((ar.hsize(2)='1' and ar.hsize(0)='0') or (ar.hsize(1 downto 0)="11"))) or
(ahbbits = 128 and ar.hsize="011") ) then
midsize := '1';
end if;
-- Determine whether sequential burst is allowed after current access
canburst := '0';
if (bigsize='1' and ar.haddr(l2blen-4 downto l2ahbw-3)/=(not zerov(l2blen-l2ahbw))) or
(ar.hsize="010" and ar.haddr(l2blen-4 downto 2)/=(not zerov(l2blen-5))) then
canburst := '1';
end if;
-- if canburst='1' then
-- print("ar.hsize=" & tost(ar.hsize) & "ar.haddr: " & tost(ar.haddr(l2blen-4 downto 2)) & " /= " & tost(not zerov(l2blen-5)));
-- end if;
if ar.hio='1' then
canburst := '0';
end if;
if ahbsi.hready='1' and ahbsi.hsel(hindex)='1' and ahbsi.htrans(1)='1' then
av.haddr := ha0;
av.ramaddr := ha0(log2(4*burstlen)-1 downto 2);
av.hio := ahbsi.hmbsel(1);
av.hsize := ahbsi.hsize;
av.hwrite := ahbsi.hwrite;
av.hburst0 := ahbsi.hburst(0);
if ahbsi.htrans(0)='0' or canburst='0' then
av.haddr_nonseq := ha0(9 downto 0);
end if;
end if;
-- Synchronize from DDR domain
av.resp1:=response; av.resp2:=ar.resp1;
vresp := ar.resp2;
if nosync /= 0 then vresp := response; end if;
vdone := vresp.done_tog;
-- Determine whether we can read more data in burst
datavalid := '0';
writedone := '0';
if ar.start_tog=vdone then
datavalid := '1';
writedone := '1';
end if;
if ar.rctr_lin="0000" then rend:=ar.haddr(7 downto l2ddrw-3); else rend:=ar.endpos; end if;
nrend := std_logic_vector(unsigned(rend)+1);
rctr_gray := lin2gray(ar.rctr_lin);
if ar.start_tog/=vdone and rctr_gray /= vresp.rctr_gray and ar.block_read(0)='0' then
av.rctr_lin := std_logic_vector(unsigned(ar.rctr_lin)+1);
av.endpos := nrend;
rend := nrend;
end if;
if 2*ddrbits > ahbbits then
if rend /= ar.haddr(7 downto log2(ddrbits/4)) then
datavalid := '1';
end if;
else
if rend(7 downto log2(ahbbits/8)) /= ar.haddr(7 downto log2(ahbbits/8)) then
datavalid := '1';
end if;
if 2*ddrbits < ahbbits and ahbbits > 32 then
if ar.hsize="010" or ar.hsize="001" or ar.hsize="000" then
if rend(log2(ahbbits/8)-1 downto log2(ddrbits/4)) /=
ar.haddr(log2(ahbbits/8)-1 downto log2(ddrbits/4)) then
datavalid := '1';
end if;
end if;
end if;
end if;
if ar.block_read(1)='1' or (ar.start_tog/=vdone and ar.block_read(0)='1') then
datavalid := '0';
writedone := '0';
end if;
if ar.block_read(1)='1' and ar.start_tog/=vdone then
av.block_read(1) := '0';
end if;
if ar.block_read(1)='0' and vresp.rctr_gray="0000" then
av.block_read(0) := '0';
end if;
-- FSM
inc_ramaddr := '0';
tog_start := '0';
case ar.s is
when asnormal =>
-- Idle and memory read state
if ahbsi.hready='1' and ahbsi.hsel(hindex)='1' and ahbsi.htrans(1)='1' then
-- Pass on address immediately to request for read case
av.req := (startaddr => ha0,
endaddr => ha0(9 downto 0),
hsize => ahbsi.hsize,
hwrite => ahbsi.hwrite,
hio => ahbsi.hmbsel(1),
burst => ahbsi.hburst(0),
maskdata => '0', maskcb => '0');
if ahbsi.hwrite='0' then
if ahbsi.htrans(0)='0' or canburst='0' then
av.so_hready := '0';
tog_start := '1';
elsif datavalid='1' then
inc_ramaddr := '1';
else
av.so_hready := '0';
-- grlib.testlib.print("Going to waitstate!");
end if;
else
av.s := asw1;
end if;
end if;
if ar.so_hready='0' and datavalid='1' then
av.so_hready := '1';
inc_ramaddr := '1';
end if;
when asw1 =>
-- Transfer data for write request
wbw := '1';
if bigsize='1' or midsize='1' then wbwb:='1'; end if;
av.so_hready := '1';
av.req.endaddr := ar.haddr(9 downto 0);
if ahbsi.hready='1' and ahbsi.hsel(hindex)='1' and ahbsi.htrans(1)='1' then
if ahbsi.htrans(0)='0' or canburst='0' then
if ahbsi.hwrite='1' then
av.s := asww1;
else
av.so_hready := '0';
av.s := aswr;
end if;
tog_start := '1';
end if;
else
av.s := asw2;
tog_start := '1';
end if;
when asw2 =>
-- Write request ongoing
av.so_hready := '1';
if ahbsi.hready='1' and ahbsi.hsel(hindex)='1' and ahbsi.htrans(1)='1' then
if ahbsi.hwrite='1' then
av.s := asww1;
else
av.so_hready := '0';
av.s := aswr;
end if;
elsif writedone='1' then
av.s := asnormal;
end if;
when asww1 =>
-- Transfer data for second write while write request ongoing
wbw := '1';
if bigsize='1' or midsize='1' then wbwb:='1'; end if;
av.so_hready := '1';
av.nreq := (startaddr => ar.haddr(31 downto 10) & ar.haddr_nonseq(9 downto 0),
endaddr => ar.haddr(9 downto 0),
hsize => ar.hsize,
hwrite => ar.hwrite,
hio => ar.hio,
burst => ar.hburst0,
maskdata => '0', maskcb => '0');
if ahbsi.hready='1' and ahbsi.hsel(hindex)='1' and ahbsi.htrans(1)='1' then
if ahbsi.htrans(0)='0' or canburst='0' then
av.so_hready := '0';
av.s := aswwx;
end if;
else
av.s := asww2;
end if;
when asww2 =>
-- Second write enqueued, wait for first write to finish
-- Any new request here will cause HREADY to go low
av.so_hready := '1';
if ahbsi.hready='1' and ahbsi.hsel(hindex)='1' and ahbsi.htrans(1)='1' then
av.so_hready := '0';
av.s := aswwx;
elsif writedone='1' then
av.req := ar.nreq;
tog_start := '1';
av.s := asw2;
end if;
when aswr =>
-- Read request following ongoing write request
-- HREADY is low in this state
av.so_hready := '0';
if writedone='1' then
av.req := (startaddr => ar.haddr(31 downto 10) & ar.haddr_nonseq(9 downto 0),
endaddr => ar.haddr(9 downto 0),
hsize => ar.hsize,
hwrite => ar.hwrite,
hio => ar.hio,
burst => ar.hburst0,
maskdata => '0', maskcb => '0');
av.hwrite := '0';
tog_start := '1';
av.s := asnormal;
end if;
when aswwx =>
-- Write ongoing + write posted + another AHB request (read or write)
-- Keep HREADY low
av.so_hready := '0';
if writedone='1' then
tog_start := '1';
av.req := ar.nreq;
if ar.hwrite='1' then
av.nreq := (startaddr => ar.haddr(31 downto 10) & ar.haddr_nonseq(9 downto 0),
endaddr => ar.haddr(9 downto 0),
hsize => ar.hsize,
hwrite => ar.hwrite,
hio => ar.hio,
burst => ar.hburst0,
maskdata => '0', maskcb => '0');
av.so_hready := '1';
av.s := asww1;
else
av.s := aswr;
end if;
end if;
end case;
if tog_start='1' and (regarea=0 or av.req.hio='0' or av.req.startaddr(5)='0') then
av.start_tog := not ar.start_tog;
av.rctr_lin := "0000";
if ar.start_tog /= vdone then
av.block_read(1) := '1';
end if;
av.block_read(0) := '1';
end if;
if inc_ramaddr='1' then
if bigsize='1' then
av.ramaddr(log2(4*burstlen)-1 downto log2(ahbbits/8)) :=
std_logic_vector(unsigned(ar.ramaddr(log2(4*burstlen)-1 downto log2(ahbbits/8)))+1);
else
av.ramaddr(log2(4*burstlen)-1 downto 2) :=
std_logic_vector(unsigned(ar.ramaddr(log2(4*burstlen)-1 downto 2))+1);
end if;
end if;
-- Used only if regarea /= 0
regdata := (others => '0');
regdata(18 downto 16) := std_logic_vector(to_unsigned(log2(ddrbits/8),3));
if hwidth/='0' then
regdata(18 downto 16) := std_logic_vector(to_unsigned(log2(ddrbits/16),3));
end if;
regdata(15 downto 12) := beid;
-- If we are using AMBA-compliant data muxing, nothing needs to be done to
-- the hrdata vector. Otherwise, we need to duplicate 32-bit lanes
if regarea/=0 and ar.req.hio='1' and ar.req.startaddr(5)='1' then
so.hrdata := ahbdrivedata(regdata);
elsif CORE_ACDM /= 0 then
so.hrdata := ahbdrivedata(rbrdata);
else
so.hrdata := ahbselectdata(ahbdrivedata(rbrdata),ar.haddr(4 downto 2),ar.hsize);
end if;
if rst='0' then
av.s := asnormal;
av.block_read := "00";
av.start_tog := '0';
av.so_hready := '1';
so.hready := '1';
so.hresp := HRESP_OKAY;
end if;
if l2blen-l2ddrw < 4 then
av.rctr_lin(3 downto l2blen-l2ddrw) := (others => '0');
end if;
nar <= av;
request <= ar.req;
start_tog <= ar.start_tog;
ahbso <= so;
wbwrite <= wbw;
wbwritebig <= wbwb;
wbwaddr <= wbwa;
wbwdata <= wbwd;
rbraddr <= rbra;
end process;
ahbregs : process(clk_ahb)
begin
if rising_edge(clk_ahb) then
ar <= nar;
end if;
end process;
end;
| gpl-3.0 | e9f3aa4d245bd9f908d3f7e41702a3a7 | 0.54246 | 3.515752 | false | false | false | false |
tec499-20142/t02-warmup | rtl/uart_tb.vhd | 1 | 2,852 | ----------------------------------------------------------------------------------
-- Creation Date: 13:07:48 27/03/2011
-- Module Name: RS232/UART Interface - Testbench
-- Used TAB of 4 Spaces
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity uart_tb is
end uart_tb;
architecture Behavioral of uart_tb is
----------------------------------------------
-- Constants
----------------------------------------------
constant MAIN_CLK_PER : time := 20 ns; -- 50 MHz
constant MAIN_CLK : integer := 50;
constant BAUD_RATE : integer := 9600; -- Bits per Second
constant RST_LVL : std_logic := '1'; -- Active Level of Reset
----------------------------------------------
-- Signal Declaration
----------------------------------------------
-- Clock and reset Signals
signal clk_50m : std_logic := '0';
signal rst : std_logic;
-- Transceiver Interface
signal data_from_transceiver : std_logic;
signal data_to_transceiver : std_logic;
-- Configuration signals
signal par_en : std_logic;
-- uPC Interface
signal tx_req : std_logic;
signal tx_end : std_logic;
signal tx_data : std_logic_vector(7 downto 0) := x"5A";
signal rx_ready : std_logic;
signal rx_data : std_logic_vector(7 downto 0);
-- Testbench Signals
signal uart_clk : std_logic := '0';
begin
----------------------------------------------
-- Components Instantiation
----------------------------------------------
uut:entity work.uart
generic map(
CLK_FREQ => MAIN_CLK, -- Main frequency (MHz)
SER_FREQ => BAUD_RATE -- Baud rate (bps)
)
port map(
-- Control
clk => clk_50m, -- Main clock
rst => rst, -- Main reset
-- External Interface
rx => data_from_transceiver, -- RS232 received serial data
tx => data_to_transceiver, -- RS232 transmitted serial data
-- RS232/UART Configuration
par_en => par_en, -- Parity bit enable
-- uPC Interface
tx_req => '1', -- Request SEND of data
tx_end => tx_end, -- Data SENDED
tx_data => tx_data, -- Data to transmit
rx_ready => rx_ready, -- Received data ready to uPC read
rx_data => rx_data -- Received data
);
----------------------------------------------
-- Main Signals Generation
----------------------------------------------
-- Main Clock generation
main_clock_generation:process
begin
wait for MAIN_CLK_PER/2;
clk_50m <= not clk_50m;
end process;
-- UART Clock generation
uart_clock_generation:process
begin
wait for (MAIN_CLK_PER*5208)/2;
uart_clk <= not uart_clk;
end process;
-- Reset generation
rst <= RST_LVL, not RST_LVL after MAIN_CLK_PER*5;
data_from_transceiver <= data_to_transceiver;
end Behavioral;
| gpl-2.0 | f0339e91309a1ea2c20998f38b75a6e2 | 0.52805 | 3.419664 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/usb/grusb.vhd | 1 | 24,363 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Package: grusb
-- File: grusb.vhd
-- Author: Marko Isomaki, Jonas Ekergarn
-- Description: Package for GRUSBHC, GRUSBDC, and GRUSB_DCL
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
package grusb is
-----------------------------------------------------------------------------
-- USB in/out types
-----------------------------------------------------------------------------
type grusb_in_type is record
datain : std_logic_vector(15 downto 0);
rxactive : std_ulogic;
rxvalid : std_ulogic;
rxvalidh : std_ulogic;
rxerror : std_ulogic;
txready : std_ulogic;
linestate : std_logic_vector(1 downto 0);
nxt : std_ulogic;
dir : std_ulogic;
vbusvalid : std_ulogic;
hostdisconnect : std_ulogic;
functesten : std_ulogic;
urstdrive : std_ulogic;
end record;
constant grusb_in_none : grusb_in_type :=
((others => '0'), '0', '0', '0', '0', '0', (others => '0'),
'0', '0', '0', '0', '0', '0');
type grusb_out_type is record
dataout : std_logic_vector(15 downto 0);
txvalid : std_ulogic;
txvalidh : std_ulogic;
opmode : std_logic_vector(1 downto 0);
xcvrselect : std_logic_vector(1 downto 0);
termselect : std_ulogic;
suspendm : std_ulogic;
reset : std_ulogic;
stp : std_ulogic;
oen : std_ulogic;
databus16_8 : std_ulogic;
dppulldown : std_ulogic;
dmpulldown : std_ulogic;
idpullup : std_ulogic;
drvvbus : std_ulogic;
dischrgvbus : std_ulogic;
chrgvbus : std_ulogic;
txbitstuffenable : std_ulogic;
txbitstuffenableh : std_ulogic;
fslsserialmode : std_ulogic;
tx_enable_n : std_ulogic;
tx_dat : std_ulogic;
tx_se0 : std_ulogic;
end record;
constant grusb_out_none : grusb_out_type :=
((others => '0'), '0', '0', (others => '0'), (others => '0'),
'0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0',
'0', '0', '0', '0', '0', '0');
type grusb_in_vector is array (natural range <>) of grusb_in_type;
type grusb_out_vector is array (natural range <>) of grusb_out_type;
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
component grusbhc is
generic (
ehchindex : integer range 0 to NAHBMST-1 := 0;
ehcpindex : integer range 0 to NAPBSLV-1 := 0;
ehcpaddr : integer range 0 to 16#FFF# := 0;
ehcpirq : integer range 0 to NAHBIRQ-1 := 0;
ehcpmask : integer range 0 to 16#FFF# := 16#FFF#;
uhchindex : integer range 0 to NAHBMST-1 := 0;
uhchsindex : integer range 0 to NAHBSLV-1 := 0;
uhchaddr : integer range 0 to 16#FFF# := 0;
uhchmask : integer range 0 to 16#FFF# := 16#FFF#;
uhchirq : integer range 0 to NAHBIRQ-1 := 0;
tech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nports : integer range 1 to 15 := 1;
ehcgen : integer range 0 to 1 := 1;
uhcgen : integer range 0 to 1 := 1;
n_cc : integer range 1 to 15 := 1;
n_pcc : integer range 1 to 15 := 1;
prr : integer range 0 to 1 := 0;
portroute1 : integer := 0;
portroute2 : integer := 0;
endian_conv : integer range 0 to 1 := 1;
be_regs : integer range 0 to 1 := 0;
be_desc : integer range 0 to 1 := 0;
uhcblo : integer range 0 to 255 := 2;
bwrd : integer range 1 to 256 := 16;
utm_type : integer range 0 to 2 := 2;
vbusconf : integer := 3;
netlist : integer range 0 to 1 := 0;
ramtest : integer range 0 to 1 := 0;
urst_time : integer := 0;
oepol : integer range 0 to 1 := 0;
scantest : integer range 0 to 1 := 0;
memsel : integer := 0;
syncprst : integer range 0 to 1 := 0;
sysfreq : integer := 65000;
pcidev : integer range 0 to 1 := 0;
debug : integer := 0;
debugsize : integer := 8192);
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
apbi : in apb_slv_in_type;
ehc_apbo : out apb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ehc_ahbmo : out ahb_mst_out_type;
uhc_ahbmo : out ahb_mst_out_vector_type(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbso : out ahb_slv_out_vector_type(n_cc*uhcgen downto 1*uhcgen);
o : out grusb_out_vector((nports-1) downto 0);
i : in grusb_in_vector((nports-1) downto 0));
end component;
component grusbdc is
generic (
hsindex : integer range 0 to NAHBSLV-1 := 0;
hirq : integer range 0 to NAHBIRQ-1 := 0;
haddr : integer := 0;
hmask : integer := 16#FFF#;
hmindex : integer range 0 to NAHBMST-1 := 0;
aiface : integer range 0 to 1 := 0;
memtech : integer range 0 to NTECH := DEFMEMTECH;
uiface : integer range 0 to 1 := 0;
dwidth : integer range 8 to 16 := 8;
blen : integer range 4 to 128 := 16;
nepi : integer range 1 to 16 := 1;
nepo : integer range 1 to 16 := 1;
i0 : integer range 8 to 3072 := 1024;
i1 : integer range 8 to 3072 := 1024;
i2 : integer range 8 to 3072 := 1024;
i3 : integer range 8 to 3072 := 1024;
i4 : integer range 8 to 3072 := 1024;
i5 : integer range 8 to 3072 := 1024;
i6 : integer range 8 to 3072 := 1024;
i7 : integer range 8 to 3072 := 1024;
i8 : integer range 8 to 3072 := 1024;
i9 : integer range 8 to 3072 := 1024;
i10 : integer range 8 to 3072 := 1024;
i11 : integer range 8 to 3072 := 1024;
i12 : integer range 8 to 3072 := 1024;
i13 : integer range 8 to 3072 := 1024;
i14 : integer range 8 to 3072 := 1024;
i15 : integer range 8 to 3072 := 1024;
o0 : integer range 8 to 3072 := 1024;
o1 : integer range 8 to 3072 := 1024;
o2 : integer range 8 to 3072 := 1024;
o3 : integer range 8 to 3072 := 1024;
o4 : integer range 8 to 3072 := 1024;
o5 : integer range 8 to 3072 := 1024;
o6 : integer range 8 to 3072 := 1024;
o7 : integer range 8 to 3072 := 1024;
o8 : integer range 8 to 3072 := 1024;
o9 : integer range 8 to 3072 := 1024;
o10 : integer range 8 to 3072 := 1024;
o11 : integer range 8 to 3072 := 1024;
o12 : integer range 8 to 3072 := 1024;
o13 : integer range 8 to 3072 := 1024;
o14 : integer range 8 to 3072 := 1024;
o15 : integer range 8 to 3072 := 1024;
oepol : integer range 0 to 1 := 0;
syncprst : integer range 0 to 1 := 0;
prsttime : integer range 0 to 512 := 0;
sysfreq : integer := 50000;
keepclk : integer range 0 to 1 := 0;
sepirq : integer range 0 to 1 := 0;
irqi : integer range 0 to NAHBIRQ-1 := 1;
irqo : integer range 0 to NAHBIRQ-1 := 2;
functesten : integer range 0 to 1 := 0;
scantest : integer range 0 to 1 := 0;
nsync : integer range 1 to 2 := 1);
port (
uclk : in std_ulogic;
usbi : in grusb_in_type;
usbo : out grusb_out_type;
hclk : in std_ulogic;
hrst : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end component;
component grusb_dcl is
generic (
hindex : integer := 0;
memtech : integer := DEFMEMTECH;
uiface : integer range 0 to 1 := 0;
dwidth : integer range 8 to 16 := 8;
oepol : integer range 0 to 1 := 0;
syncprst : integer range 0 to 1 := 0;
prsttime : integer range 0 to 512 := 0;
sysfreq : integer := 50000;
keepclk : integer range 0 to 1 := 0;
functesten : integer range 0 to 1 := 0;
burstlength: integer range 1 to 512 := 8;
scantest : integer range 0 to 1 := 0;
nsync : integer range 1 to 2 := 1
);
port (
uclk : in std_ulogic;
usbi : in grusb_in_type;
usbo : out grusb_out_type;
hclk : in std_ulogic;
hrst : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type
);
end component grusb_dcl;
component grusbhc_gen is
generic (
tech : integer := 0;
memtech : integer := 0;
nports : integer range 1 to 15 := 1;
ehcgen : integer range 0 to 1 := 1;
uhcgen : integer range 0 to 1 := 1;
n_cc : integer range 1 to 15 := 1;
n_pcc : integer range 1 to 15 := 1;
prr : integer range 0 to 1 := 0;
portroute1 : integer := 0;
portroute2 : integer := 0;
endian_conv : integer range 0 to 1 := 1;
be_regs : integer range 0 to 1 := 0;
be_desc : integer range 0 to 1 := 0;
uhcblo : integer range 0 to 255 := 2;
bwrd : integer range 1 to 256 := 16;
utm_type : integer range 0 to 2 := 2;
vbusconf : integer := 3;
netlist : integer range 0 to 1 := 0;
ramtest : integer range 0 to 1 := 0;
urst_time : integer := 0;
oepol : integer range 0 to 1 := 0;
scantest : integer range 0 to 1 := 0;
memsel : integer := 0;
syncprst : integer range 0 to 1 := 0;
sysfreq : integer := 65000;
pcidev : integer range 0 to 1 := 0;
debug : integer := 0;
debugsize : integer := 8192);
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
-- EHC APB slave input signals
ehc_apbsi_psel : in std_ulogic;
ehc_apbsi_penable : in std_ulogic;
ehc_apbsi_paddr : in std_logic_vector(31 downto 0);
ehc_apbsi_pwrite : in std_ulogic;
ehc_apbsi_pwdata : in std_logic_vector(31 downto 0);
-- EHC APB slave output signals
ehc_apbso_prdata : out std_logic_vector(31 downto 0);
ehc_irq : out std_ulogic;
-- EHC/UHC(s) AHB master input signals
ahbmi_hgrant : in std_logic_vector(n_cc*uhcgen downto 0);
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
-- UHC(s) AHB slave input signals
uhc_ahbsi_hsel : in std_logic_vector((n_cc-1)*uhcgen downto 0);
uhc_ahbsi_haddr : in std_logic_vector(31 downto 0);
uhc_ahbsi_hwrite : in std_ulogic;
uhc_ahbsi_htrans : in std_logic_vector(1 downto 0);
uhc_ahbsi_hsize : in std_logic_vector(2 downto 0);
uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0);
uhc_ahbsi_hready : in std_ulogic;
-- EHC AHB master output signals
ehc_ahbmo_hbusreq : out std_ulogic;
ehc_ahbmo_hlock : out std_ulogic;
ehc_ahbmo_htrans : out std_logic_vector(1 downto 0);
ehc_ahbmo_haddr : out std_logic_vector(31 downto 0);
ehc_ahbmo_hwrite : out std_ulogic;
ehc_ahbmo_hsize : out std_logic_vector(2 downto 0);
ehc_ahbmo_hburst : out std_logic_vector(2 downto 0);
ehc_ahbmo_hprot : out std_logic_vector(3 downto 0);
ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0);
-- UHC(s) AHB master output signals
uhc_ahbmo_hbusreq : out std_logic_vector((n_cc-1)*uhcgen downto 0);
uhc_ahbmo_hlock : out std_logic_vector((n_cc-1)*uhcgen downto 0);
uhc_ahbmo_htrans : out std_logic_vector(((n_cc*2)-1)*uhcgen downto 0);
uhc_ahbmo_haddr : out std_logic_vector(((n_cc*32)-1)*uhcgen downto 0);
uhc_ahbmo_hwrite : out std_logic_vector((n_cc-1)*uhcgen downto 0);
uhc_ahbmo_hsize : out std_logic_vector(((n_cc*3)-1)*uhcgen downto 0);
uhc_ahbmo_hburst : out std_logic_vector(((n_cc*3)-1)*uhcgen downto 0);
uhc_ahbmo_hprot : out std_logic_vector(((n_cc*4)-1)*uhcgen downto 0);
uhc_ahbmo_hwdata : out std_logic_vector(((n_cc*32)-1)*uhcgen downto 0);
-- UHC(s) AHB slave output signals
uhc_ahbso_hready : out std_logic_vector((n_cc-1)*uhcgen downto 0);
uhc_ahbso_hresp : out std_logic_vector(((n_cc*2)-1)*uhcgen downto 0);
uhc_ahbso_hrdata : out std_logic_vector(((n_cc*32)-1)*uhcgen downto 0);
uhc_ahbso_hsplit : out std_logic_vector(((n_cc*NAHBMST)-1)*uhcgen downto 0);
uhc_irq : out std_logic_vector((n_cc-1)*uhcgen downto 0);
-- ULPI/UTMI+ output signals
xcvrselect : out std_logic_vector(((nports*2)-1) downto 0);
termselect : out std_logic_vector((nports-1) downto 0);
opmode : out std_logic_vector(((nports*2)-1) downto 0);
txvalid : out std_logic_vector((nports-1) downto 0);
drvvbus : out std_logic_vector((nports-1) downto 0);
dataout : out std_logic_vector(((nports*16)-1) downto 0);
txvalidh : out std_logic_vector((nports-1) downto 0);
stp : out std_logic_vector((nports-1) downto 0);
reset : out std_logic_vector((nports-1) downto 0);
oen : out std_logic_vector((nports-1) downto 0);
suspendm : out std_ulogic;
databus16_8 : out std_ulogic;
dppulldown : out std_ulogic;
dmpulldown : out std_ulogic;
idpullup : out std_ulogic;
dischrgvbus : out std_ulogic;
chrgvbus : out std_ulogic;
txbitstuffenable : out std_ulogic;
txbitstuffenableh : out std_ulogic;
fslsserialmode : out std_ulogic;
tx_enable_n : out std_ulogic;
tx_dat : out std_ulogic;
tx_se0 : out std_ulogic;
-- ULPI/UTMI+ input signals
linestate : in std_logic_vector(((nports*2)-1) downto 0);
txready : in std_logic_vector((nports-1) downto 0);
rxvalid : in std_logic_vector((nports-1) downto 0);
rxactive : in std_logic_vector((nports-1) downto 0);
rxerror : in std_logic_vector((nports-1) downto 0);
vbusvalid : in std_logic_vector((nports-1) downto 0);
datain : in std_logic_vector(((nports*16)-1) downto 0);
rxvalidh : in std_logic_vector((nports-1) downto 0);
hostdisconnect : in std_logic_vector((nports-1) downto 0);
nxt : in std_logic_vector((nports-1) downto 0);
dir : in std_logic_vector((nports-1) downto 0);
urstdrive : in std_logic_vector((nports-1) downto 0);
-- scan signals
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end component;
component grusbdc_gen is
generic (
aiface : integer range 0 to 1 := 0;
memtech : integer range 0 to NTECH := DEFMEMTECH;
uiface : integer range 0 to 1 := 0;
dwidth : integer range 8 to 16 := 8;
blen : integer range 4 to 128 := 16;
nepi : integer range 1 to 16 := 1;
nepo : integer range 1 to 16 := 1;
i0 : integer range 8 to 3072 := 1024;
i1 : integer range 8 to 3072 := 1024;
i2 : integer range 8 to 3072 := 1024;
i3 : integer range 8 to 3072 := 1024;
i4 : integer range 8 to 3072 := 1024;
i5 : integer range 8 to 3072 := 1024;
i6 : integer range 8 to 3072 := 1024;
i7 : integer range 8 to 3072 := 1024;
i8 : integer range 8 to 3072 := 1024;
i9 : integer range 8 to 3072 := 1024;
i10 : integer range 8 to 3072 := 1024;
i11 : integer range 8 to 3072 := 1024;
i12 : integer range 8 to 3072 := 1024;
i13 : integer range 8 to 3072 := 1024;
i14 : integer range 8 to 3072 := 1024;
i15 : integer range 8 to 3072 := 1024;
o0 : integer range 8 to 3072 := 1024;
o1 : integer range 8 to 3072 := 1024;
o2 : integer range 8 to 3072 := 1024;
o3 : integer range 8 to 3072 := 1024;
o4 : integer range 8 to 3072 := 1024;
o5 : integer range 8 to 3072 := 1024;
o6 : integer range 8 to 3072 := 1024;
o7 : integer range 8 to 3072 := 1024;
o8 : integer range 8 to 3072 := 1024;
o9 : integer range 8 to 3072 := 1024;
o10 : integer range 8 to 3072 := 1024;
o11 : integer range 8 to 3072 := 1024;
o12 : integer range 8 to 3072 := 1024;
o13 : integer range 8 to 3072 := 1024;
o14 : integer range 8 to 3072 := 1024;
o15 : integer range 8 to 3072 := 1024;
oepol : integer range 0 to 1 := 0;
syncprst : integer range 0 to 1 := 0;
prsttime : integer range 0 to 512 := 0;
sysfreq : integer := 50000;
keepclk : integer range 0 to 1 := 0;
sepirq : integer range 0 to 1 := 0;
functesten : integer range 0 to 1 := 0;
scantest : integer range 0 to 1 := 0;
nsync : integer range 1 to 2 := 1);
port (
-- usb clock
uclk : in std_ulogic;
--usb in signals
datain : in std_logic_vector(15 downto 0);
rxactive : in std_ulogic;
rxvalid : in std_ulogic;
rxvalidh : in std_ulogic;
rxerror : in std_ulogic;
txready : in std_ulogic;
linestate : in std_logic_vector(1 downto 0);
nxt : in std_ulogic;
dir : in std_ulogic;
vbusvalid : in std_ulogic;
urstdrive : in std_ulogic;
--usb out signals
dataout : out std_logic_vector(15 downto 0);
txvalid : out std_ulogic;
txvalidh : out std_ulogic;
opmode : out std_logic_vector(1 downto 0);
xcvrselect : out std_logic_vector(1 downto 0);
termselect : out std_ulogic;
suspendm : out std_ulogic;
reset : out std_ulogic;
stp : out std_ulogic;
oen : out std_ulogic;
databus16_8 : out std_ulogic;
dppulldown : out std_ulogic;
dmpulldown : out std_ulogic;
idpullup : out std_ulogic;
drvvbus : out std_ulogic;
dischrgvbus : out std_ulogic;
chrgvbus : out std_ulogic;
txbitstuffenable : out std_ulogic;
txbitstuffenableh : out std_ulogic;
fslsserialmode : out std_ulogic;
tx_enable_n : out std_ulogic;
tx_dat : out std_ulogic;
tx_se0 : out std_ulogic;
-- amba clock/rst
hclk : in std_ulogic;
hrst : in std_ulogic;
--ahb master in signals
ahbmi_hgrant : in std_ulogic;
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
--ahb master out signals
ahbmo_hbusreq : out std_ulogic;
ahbmo_hlock : out std_ulogic;
ahbmo_htrans : out std_logic_vector(1 downto 0);
ahbmo_haddr : out std_logic_vector(31 downto 0);
ahbmo_hwrite : out std_ulogic;
ahbmo_hsize : out std_logic_vector(2 downto 0);
ahbmo_hburst : out std_logic_vector(2 downto 0);
ahbmo_hprot : out std_logic_vector(3 downto 0);
ahbmo_hwdata : out std_logic_vector(31 downto 0);
--ahb slave in signals
ahbsi_hsel : in std_ulogic;
ahbsi_haddr : in std_logic_vector(31 downto 0);
ahbsi_hwrite : in std_ulogic;
ahbsi_htrans : in std_logic_vector(1 downto 0);
ahbsi_hsize : in std_logic_vector(2 downto 0);
ahbsi_hburst : in std_logic_vector(2 downto 0);
ahbsi_hwdata : in std_logic_vector(31 downto 0);
ahbsi_hprot : in std_logic_vector(3 downto 0);
ahbsi_hready : in std_ulogic;
ahbsi_hmaster : in std_logic_vector(3 downto 0);
ahbsi_hmastlock : in std_ulogic;
--ahb slave out signals
ahbso_hready : out std_ulogic;
ahbso_hresp : out std_logic_vector(1 downto 0);
ahbso_hrdata : out std_logic_vector(31 downto 0);
ahbso_hsplit : out std_logic_vector(NAHBMST-1 downto 0);
-- misc
irq : out std_logic_vector(2*sepirq downto 0);
-- scan signals
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic
);
end component;
end grusb;
| gpl-3.0 | 9352f9cad1c7f2341ee4a213c7602663 | 0.495629 | 3.828253 | false | false | false | false |
pwsoft/fpga_examples | rtl/ttl/ttl_74283.vhd | 1 | 3,310 | -- -----------------------------------------------------------------------
--
-- Syntiac VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2018 by Peter Wendrich ([email protected])
-- http://www.syntiac.com
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
-- 4-bit binary full adder with fast carry
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.ttl_pkg.all;
-- -----------------------------------------------------------------------
entity ttl_74283 is
generic (
latency : integer := 2
);
port (
emuclk : in std_logic;
p1 : out ttl_t; -- Sum 2
p2 : in ttl_t; -- B2
p3 : in ttl_t; -- A2
p4 : out ttl_t; -- Sum 1
p5 : in ttl_t; -- A1
p6 : in ttl_t; -- B1
p7 : in ttl_t; -- C0
p9 : out ttl_t; -- C4
p10 : out ttl_t; -- Sum 4
p11 : in ttl_t; -- B4
p12 : in ttl_t; -- A4
p13 : out ttl_t; -- Sum 3
p14 : in ttl_t; -- A3
p15 : in ttl_t -- B3
);
end entity;
architecture rtl of ttl_74283 is
signal p1_loc : ttl_t;
signal p4_loc : ttl_t;
signal p9_loc : ttl_t;
signal p10_loc : ttl_t;
signal p13_loc : ttl_t;
signal a : unsigned(3 downto 0);
signal b : unsigned(3 downto 0);
signal c : unsigned(0 downto 0);
signal adder_reg : unsigned(4 downto 0) := (others => '0');
begin
p1_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p1_loc, q => p1);
p4_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p4_loc, q => p4);
p9_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p9_loc, q => p9);
p10_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p10_loc, q => p10);
p13_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p13_loc, q => p13);
-- Adder inputs
a(0) <= ttl2std(p5);
a(1) <= ttl2std(p3);
a(2) <= ttl2std(p14);
a(3) <= ttl2std(p12);
b(0) <= ttl2std(p6);
b(1) <= ttl2std(p2);
b(2) <= ttl2std(p15);
b(3) <= ttl2std(p11);
c(0) <= ttl2std(p7);
-- Adder results
p1_loc <= std2ttl(adder_reg(1));
p4_loc <= std2ttl(adder_reg(0));
p9_loc <= std2ttl(adder_reg(4));
p10_loc <= std2ttl(adder_reg(3));
p13_loc <= std2ttl(adder_reg(2));
process(emuclk)
begin
if rising_edge(emuclk) then
adder_reg <= ("0" & a) + ("0" & b) + ("0000" & c);
end if;
end process;
end architecture;
| lgpl-2.1 | 8a9b390f7a550934c44209edba200696 | 0.563142 | 2.900964 | false | false | false | false |
hoglet67/CoPro6502 | src/T80/SSRAM2.vhd | 1 | 3,034 | --
-- Inferrable Synchronous SRAM for Leonardo synthesis, no write through!
--
-- Version : 0236
--
-- Copyright (c) 2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
--
-- File history :
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity SSRAM is
generic(
AddrWidth : integer := 16;
DataWidth : integer := 8
);
port(
Clk : in std_logic;
CE_n : in std_logic;
WE_n : in std_logic;
A : in std_logic_vector(AddrWidth - 1 downto 0);
DIn : in std_logic_vector(DataWidth - 1 downto 0);
DOut : out std_logic_vector(DataWidth - 1 downto 0)
);
end SSRAM;
architecture behaviour of SSRAM is
type Memory_Image is array (natural range <>) of std_logic_vector(DataWidth - 1 downto 0);
signal RAM : Memory_Image(0 to 2 ** AddrWidth - 1);
-- signal A_r : std_logic_vector(AddrWidth - 1 downto 0);
begin
process (Clk)
begin
if Clk'event and Clk = '1' then
-- pragma translate_off
if not is_x(A) then
-- pragma translate_on
DOut <= RAM(to_integer(unsigned(A(AddrWidth - 1 downto 0))));
-- pragma translate_off
end if;
-- pragma translate_on
if CE_n = '0' and WE_n = '0' then
RAM(to_integer(unsigned(A))) <= DIn;
end if;
-- A_r <= A;
end if;
end process;
end;
| gpl-3.0 | f5e37f9de930ab913271175affceda64 | 0.720171 | 3.682039 | false | false | false | false |
ARC-Lab-UF/UAA | src/fifo2.vhd | 1 | 7,524 | -- Copyright (c) 2015 University of Florida
--
-- This file is part of uaa.
--
-- uaa is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- uaa is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with uaa. If not, see <http://www.gnu.org/licenses/>.
-- David Wilson
-- University of Florida
-- Description:
-- This file implements a fifo2 entity. Due to the nature of the FCBT, two elements
-- need to be read out during the same cycle. This is achieved with the fifo2 entity
-- by instantiating two fifo entities that take turns being written to and read from
-- as the first element of the fifo.
-- Notes:
-- The fifo protects against invalid writes (i.e. when full) and invalid reads
-- (i.e. when empty)
--
-- (use_bram = true and same_cycle_output = true) is not supported by
-- all FPGAs.
--
-- To simplify control logic, the depth is rounded up to an even number so that
-- both fifos have the same depth.
-- Used entities:
-- fifo
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.math_custom.all;
use work.flt_pkg.all;
-------------------------------------------------------------------------------
-- Generics Description
-- width : the width of the FIFO in bits (required)
-- depth : the depth of the FIFO in words (required)
-- use_bram : uses bram when true, uses LUTs/FFs when false
-- same_cycle_output : output appears in same cycle as read when true, one
-- cycle later when false
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Port Description:
-- clk : clock input
-- rst : reset input (asynchronous)
-- rd : read input (active high)
-- wr : write input (active high)
-- single : read only one input (active high)
-- empty : empty output (active high)
-- full : full output (active high)
-- overflow : fifo2 has overflowed (active high)
-- underflow : fifo2 has underflowed (active high)
-- input : fifo2 input
-- output0 : fifo2 output, first element
-- output1 : fifo2 output, second element
-- count : fifo2 count
-------------------------------------------------------------------------------
entity fifo2 is
generic(
width : positive;
depth : positive;
use_bram : boolean := true;
same_cycle_output : boolean := false);
port(
clk : in std_logic;
rst : in std_logic;
rd : in std_logic;
wr : in std_logic;
single : in std_logic;
empty : out std_logic;
full : out std_logic;
overflow : out std_logic;
underflow : out std_logic;
input : in std_logic_vector(width-1 downto 0);
output0 : out std_logic_vector(width-1 downto 0);
output1 : out std_logic_vector(width-1 downto 0);
count : out std_logic_vector(clog2(depth+1)-1 downto 0)
);
end fifo2;
architecture RTL of fifo2 is
-- round buffer depth to a number divisible by two so that both fifos gets the
-- same depth
constant BUFFER_DEPTH : positive := (depth+1)/2;
-- fifo signals
type data_array is array (natural range<>) of std_logic_vector(width-1 downto 0);
signal buf_rd : std_logic_vector(1 downto 0);
signal buf_wr : std_logic_vector(1 downto 0);
signal buf_empty : std_logic_vector(1 downto 0);
signal buf_full : std_logic_vector(1 downto 0);
signal buf_out : data_array(1 downto 0);
-- control signals
signal count_s : std_logic_vector(clog2(depth+1)-1 downto 0);
signal wr_sel : std_logic;
signal front_input_sel : std_logic;
begin
-- determine which fifo has first element of fifo2
output0 <= buf_out(0) when front_input_sel = '0' else buf_out(1);
output1 <= buf_out(1) when front_input_sel = '0' else buf_out(0);
-- update empty and full flags
empty <= '1' when buf_empty = "11" else '0';
full <= '1' when buf_full = "11" else '0';
-- fifo2 counter
process(clk, rst)
variable buf_count : integer;
begin
if (rst = '1') then
count_s <= (others => '0');
overflow <= '0';
underflow <= '0';
elsif (rising_edge(clk)) then
buf_count := to_integer(unsigned(count_s));
if (wr = '1') then
-- add to the buffer count if its not full
-- otherwise, the buffer has overflowed
if (to_integer(unsigned(count_s)) < depth) then
buf_count := buf_count + 1;
else
overflow <= '1';
end if;
end if;
if (rd = '1') then
-- read only one element from the fifo2
if (single = '1') then
-- subtract from buffer count if its not empty
-- otherwise, the buffer has underflowed
if (to_integer(unsigned(count_s)) > 0) then
buf_count := buf_count - 1;
else
underflow <= '1';
end if;
-- read two elements from the fifo2
else
-- subtract from buffer count if it doesn't have at least two elements
-- otherwise, the buffer has underflowed
if (to_integer(unsigned(count_s)) > 1) then
buf_count := buf_count - 2;
else
underflow <= '1';
end if;
end if;
end if;
count_s <= std_logic_vector(to_unsigned(buf_count,count_s'length));
end if;
end process;
count <= count_s;
-- alternate writes between the two buffers
process(clk, rst)
begin
if (rst = '1') then
wr_sel <= '0';
elsif (rising_edge(clk)) then
if (wr = '1') then
wr_sel <= not wr_sel;
end if;
end if;
end process;
-- only write to the fifo pointed to by wr_sel
buf_wr(0) <= '1' when wr = '1' and wr_sel = '0' else '0';
buf_wr(1) <= '1' when wr = '1' and wr_sel = '1' else '0';
-- both buffers are read from when there is a non-singleton read.
-- only front buffer is read from when there is a singleton read.
buf_rd(0) <= '1' when rd = '1' and single = '0' else
'1' when rd = '1' and single = '1' and front_input_sel = '0' else '0';
buf_rd(1) <= '1' when rd = '1' and single = '0' else
'1' when rd = '1' and single = '1' and front_input_sel = '1' else '0';
-- determine which fifo has the first element of fifo2
process(clk, rst)
begin
if (rst = '1') then
front_input_sel <= '0';
elsif (rising_edge(clk)) then
-- the front fifo only changes when a singleton read occurs
if (rd = '1' and single = '1') then
front_input_sel <= not front_input_sel;
end if;
end if;
end process;
U_BUF : for i in 0 to 1 generate
U_IBUF0 : entity work.fifo
generic map (
width => width,
depth => BUFFER_DEPTH,
use_bram => use_bram,
use_distributed_ram => false,
same_cycle_output => same_cycle_output)
port map (
clk => clk,
rst => rst,
rd => buf_rd(i),
wr => buf_wr(i),
empty => buf_empty(i),
full => buf_full(i),
input => input,
output => buf_out(i)
);
end generate;
end RTL;
| gpl-3.0 | 1c1081e2c5e3b0c39df00a2723eac0a2 | 0.585991 | 3.336585 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-xilinx-ml501/config.vhd | 1 | 7,629 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex5;
constant CFG_MEMTECH : integer := virtex5;
constant CFG_PADTECH : integer := virtex5;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex5;
constant CFG_CLKMUL : integer := (8);
constant CFG_CLKDIV : integer := (10);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 2;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 4;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 2;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 1*2 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 8;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000030#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- Xilinx MIG
constant CFG_MIG_DDR2 : integer := 0;
constant CFG_MIG_RANKS : integer := 1;
constant CFG_MIG_COLBITS : integer := 10;
constant CFG_MIG_ROWBITS : integer := 13;
constant CFG_MIG_BANKBITS: integer := 2;
constant CFG_MIG_HMASK : integer := 16#F00#;
-- DDR controller
constant CFG_DDR2SP : integer := 1;
constant CFG_DDR2SP_INIT : integer := 1;
constant CFG_DDR2SP_FREQ : integer := (140);
constant CFG_DDR2SP_TRFC : integer := (130);
constant CFG_DDR2SP_DATAWIDTH : integer := (64);
constant CFG_DDR2SP_FTEN : integer := 0;
constant CFG_DDR2SP_FTWIDTH : integer := 0;
constant CFG_DDR2SP_COL : integer := (10);
constant CFG_DDR2SP_SIZE : integer := (256);
constant CFG_DDR2SP_DELAY0 : integer := (15);
constant CFG_DDR2SP_DELAY1 : integer := (15);
constant CFG_DDR2SP_DELAY2 : integer := (15);
constant CFG_DDR2SP_DELAY3 : integer := (15);
constant CFG_DDR2SP_DELAY4 : integer := (15);
constant CFG_DDR2SP_DELAY5 : integer := (15);
constant CFG_DDR2SP_DELAY6 : integer := (15);
constant CFG_DDR2SP_DELAY7 : integer := (15);
constant CFG_DDR2SP_NOSYNC : integer := 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 1;
constant CFG_GPT_WDOG : integer := 16#FFFFF#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0FFFE#;
constant CFG_GRGPIO_WIDTH : integer := (14);
-- I2C master
constant CFG_I2C_ENABLE : integer := 1;
-- AMBA Wrapper for Xilinx System Monitor
constant CFG_GRSYSMON : integer := 1;
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 1;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 1;
-- AMBA System ACE Interface Controller
constant CFG_GRACECTRL : integer := 1;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-3.0 | b9c9aeebb953411a8c914c48e00ff2a9 | 0.649495 | 3.543428 | false | false | false | false |
pwsoft/fpga_examples | rtl/chameleon/chameleon_led.vhd | 1 | 2,288 | -- -----------------------------------------------------------------------
--
-- Turbo Chameleon
--
-- Multi purpose FPGA expansion for the Commodore 64 computer
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2011 by Peter Wendrich ([email protected])
-- http://www.syntiac.com/chameleon.html
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
--
-- LED blinker. Blink frequency 2 Hz
--
-- -----------------------------------------------------------------------
-- clk - system clock input
-- clk_1khz - 1 Khz clock input
-- led_on - if high the LED is on
-- led_blink - if high the LED is blinking
-- led - led output (high is on) 2hz
-- led_1hz - led output 1 hz
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
-- -----------------------------------------------------------------------
entity chameleon_led is
port (
clk : in std_logic;
clk_1khz : in std_logic;
led_on : in std_logic;
led_blink : in std_logic;
led : out std_logic;
led_1hz : out std_logic
);
end entity;
-- -----------------------------------------------------------------------
architecture rtl of chameleon_led is
signal count : unsigned(9 downto 0);
begin
led <= count(8);
led_1hz <= count(9);
process(clk)
begin
if rising_edge(clk) then
if clk_1khz = '1' then
count <= count + 1;
end if;
if led_blink = '0' then
count(8) <= led_on;
count(9) <= led_on;
end if;
end if;
end process;
end architecture;
| lgpl-2.1 | 64f881a72516b0926272782aba6e2148 | 0.524038 | 4 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/maps/iopad.vhd | 1 | 7,641 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iopad
-- File: iopad.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: io pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity iopad is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0; filter : integer := 0);
port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic;
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end;
architecture rtl of iopad is
signal oen : std_ulogic;
begin
oen <= not en when oepol /= padoen_polarity(tech) else en;
gen0 : if has_pads(tech) = 0 generate
pad <= transport i
-- pragma translate_off
after 2 ns
-- pragma translate_on
when oen = '0' and slew = 0 else i when oen = '0'
-- pragma translate_off
else 'X' after 2 ns when is_x(oen) and slew = 0
else 'X' when is_x(oen)
-- pragma translate_on
else 'Z'
-- pragma translate_off
after 2 ns
-- pragma translate_on
when slew = 0 else 'Z';
o <= transport to_X01(pad)
-- pragma translate_off
after 1 ns
-- pragma translate_on
;
end generate;
xcv : if (is_unisim(tech) = 1) generate
x0 : unisim_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
axc : if (tech = axcel) or (tech = axdsp) generate
x0 : axcel_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
pa3 : if (tech = proasic) or (tech = apa3) generate
x0 : apa3_iopad generic map (level, slew, voltage, strength, filter)
port map (pad, i, oen, o);
end generate;
pa3e : if (tech = apa3e) generate
x0 : apa3e_iopad generic map (level, slew, voltage, strength, filter)
port map (pad, i, oen, o);
end generate;
igl2 : if (tech = igloo2) or (tech = rtg4) generate
x0 : igloo2_iopad port map (pad, i, oen, o);
end generate;
pa3l : if (tech = apa3l) generate
x0 : apa3l_iopad generic map (level, slew, voltage, strength, filter)
port map (pad, i, oen, o);
end generate;
fus : if (tech = actfus) generate
x0 : fusion_iopad generic map (level, slew, voltage, strength, filter)
port map (pad, i, oen, o);
end generate;
atc : if (tech = atc18s) generate
x0 : atc18_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
atcrh : if (tech = atc18rha) generate
x0 : atc18rha_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
um : if (tech = umc) generate
x0 : umc_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
rhu : if (tech = rhumc) generate
x0 : rhumc_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
saed : if (tech = saed32) generate
x0 : saed32_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
rhs : if (tech = rhs65) generate
x0 : rhs65_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o, cfgi(0), cfgi(2), cfgi(1));
end generate;
dar : if (tech = dare) generate
x0 : dare_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
ihp : if (tech = ihp25) generate
x0 : ihp25_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
ihprh : if (tech = ihp25rh) generate
x0 : ihp25rh_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
rh18t : if (tech = rhlib18t) generate
x0 : rh_lib18t_iopad generic map (strength)
port map (pad, i, oen, o);
end generate;
ut025 : if (tech = ut25) generate
x0 : ut025crh_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
ut13 : if (tech = ut130) generate
x0 : ut130hbd_iopad generic map (level, slew, voltage, strength, filter)
port map (pad, i, oen, o);
end generate;
pere : if (tech = peregrine) generate
x0 : peregrine_iopad generic map (level, slew, voltage, strength)
port map(pad, i, oen, o);
end generate;
nex : if (tech = easic90) generate
x0 : nextreme_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
n2x : if (tech = easic45) generate
x0 : n2x_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o, cfgi(0), cfgi(1),
cfgi(19 downto 15), cfgi(14 downto 10), cfgi(9 downto 6), cfgi(5 downto 2));
end generate;
ut90nhbd : if (tech = ut90) generate
x0 : ut90nhbd_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o, cfgi(0));
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity iopadv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0; filter : integer := 0);
port (
pad : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_ulogic;
o : out std_logic_vector(width-1 downto 0);
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end;
architecture rtl of iopadv is
begin
v : for j in width-1 downto 0 generate
x0 : iopad generic map (tech, level, slew, voltage, strength, oepol, filter)
port map (pad(j), i(j), en, o(j), cfgi);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity iopadvv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0; filter : integer := 0);
port (
pad : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0);
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end;
architecture rtl of iopadvv is
begin
v : for j in width-1 downto 0 generate
x0 : iopad generic map (tech, level, slew, voltage, strength, oepol, filter)
port map (pad(j), i(j), en(j), o(j), cfgi);
end generate;
end;
| gpl-3.0 | f4cee2e95ebf67f38a9a15de0aff2da7 | 0.635126 | 3.376491 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/grlib/amba/dma2ahb.vhd | 1 | 25,162 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--============================================================================--
-- Design unit : DMA2AHB (Entity & architecture declarations)
--
-- File name : dma2ahb.vhd
--
-- Purpose : AMBA AHB master interface with DMA input
--
-- Reference : AMBA(TM) Specification (Rev 2.0), ARM IHI 0011A,
-- 13th May 1999, issue A, first release, ARM Limited
-- The document can be retrieved from http://www.arm.com
-- AMBA is a trademark of ARM Limited.
-- ARM is a registered trademark of ARM Limited.
--
-- Note : Naming convention according to AMBA(TM) Specification:
-- Signal names are in upper case, except for the following:
-- A lower case 'n' in the name indicates that the signal
-- is active low.
-- Constant names are in upper case.
-- The least significant bit of an array is located to the right,
-- carrying the index number zero.
--
-- Limitations : The AMBA AHB interface has been reduced in function to support
-- only what is required. The following features are constrained:
-- Optionally generates HSIZE=BYTE, HWORD and WORD
-- Only generates HPROT="0011"
-- Allways generates HBURST=HBURST_SINGLE, HBURST_INCR
-- Optionally generates HBURST_INCR4, HBURST_INCR8, HBURST_INCR16
--
-- Generates the following on reponses on DMA interface:
-- HRESP=HRESP_OKAY => DMAOut.Ready
-- HRESP=HRESP_ERROR => DMAOut.Fault
-- HRESP=HRESP_RETRY => DMAOut.Retry (normally not used)
-- HRESP=HRESP_SPLIT => DMAOut.Retry (normally not used)
--
-- Assumes pipelined data input (after OKAY asserted).
--
-- Only big-endianness is supported.
--
-- Supports Early Bus Termination with automatic restart.
-- Supports Retry/Split with automatic restart.
--
-- Library : gaisler
--
-- Authors : Aeroflex Gaisler AB
--
-- Contact : mailto:[email protected]
-- http://www.gaisler.com
--
-- Disclaimer : All information is provided "as is", there is no warranty that
-- the information is correct or suitable for any purpose,
-- neither implicit nor explicit.
--
--------------------------------------------------------------------------------
-- Version Author Date Changes
--
-- 0.1 SH 1 Jul 2003 New version
-- 0.2 SH 21 Jul 2003 Combinatorial response introduced
-- 0.3 SH 25 Jan 2004 Support for interrupted bursts introduced
-- (early burst termination)
-- Optimised coding
-- Idle transfer initiated in 1st error phase
-- 1.3 SH 1 Oct 2004 Ported to GRLIB
-- 1.4 SH 1 Jul 2005 Support for fixed length incrementing bursts
-- Support for record types
-- 1.5 SH 1 Sep 2005 New library gaisler
-- 1.6 SH 20 Sep 2005 Added transparent HSIZE support
-- 1.6 SH 1 Nov 2005 DMAOut.Grant asserted only while HREADY high
-- 1.8 SH 10 Nov 2005 Re-ported to GRLIB
-- 1.8.1 SH 12 Dec 2005 Ensured no HTRANS=seq occurs after idle
-- 1.9 SH 1 Jan 2006 Resolve retry/early burst termination
-- 1.9.2 SH 3 Jan 2006 DelDataPhase dealyed with HREADY signal
-- 1.9.3 SH 24 Feb 2006 Added syncrst generic
-- 1.9.4 MI 27 Mar 2007 Driving HSIZE with address
-- 1.9.5 SH 14 Dec 2007 Automatic 1kbyte boundary crossing (merged)
-- 1.9.6 JA 14 Dec 2007 Support for halfword and byte bursts
-- 1.9.7 MI 4 Aug 2008 Support for Lock
-- 1.9.8 SH 16 Apr 2009 Address recovery after SPLIT/RETRY moved
-- 1.9.9 SH 9 Oct 2009 HPROT defult to 0x3
-- 2.0 SH 4 Mar 2011 DMAOut.Grant masked while ReAddrPhase set
--------------------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
library GRLIB;
use GRLIB.AMBA.all;
use GRLIB.STDLIB.all;
use GRLIB.DMA2AHB_Package.all;
entity DMA2AHB is
generic(
hindex: in Integer := 0;
vendorid: in Integer := 0;
deviceid: in Integer := 0;
version: in Integer := 0;
syncrst: in Integer := 1;
boundary: in Integer := 1);
port(
-- AMBA AHB system signals
HCLK: in Std_ULogic; -- system clock
HRESETn: in Std_ULogic; -- asynchronous reset
-- Direct Memory Access Interface
DMAIn: in DMA_In_Type;
DMAOut: out DMA_OUt_Type;
-- AMBA AHB Master Interface
AHBIn: in AHB_Mst_In_Type;
AHBOut: out AHB_Mst_Out_Type);
end entity DMA2AHB;
--============================== Architecture ================================--
architecture RTL of DMA2AHB is
--=========================================================================--
-- Configuration GRLIB
-----------------------------------------------------------------------------
constant HConfig: AHB_Config_Type := (
0 => ahb_device_reg(vendorid, deviceid, 0, version, 0),
others => (others => '0'));
--=========================================================================--
-----------------------------------------------------------------------------
-- Local signals
-----------------------------------------------------------------------------
signal Address: Std_Logic_Vector(31 downto 0);
signal AddressSave: Std_Logic_Vector(31 downto 0);
signal ActivePhase: Std_ULogic; -- ongoing access
signal AddressPhase: Std_ULogic; -- address phase
signal DataPhase: Std_ULogic; -- data phase
signal ReDataPhase: Std_ULogic; -- restart first
signal ReAddrPhase: Std_ULogic; -- restart second
signal IdlePhase: Std_ULogic; -- idle phase
signal EarlyPhase: Std_ULogic; -- early termination
signal BoundaryPhase: Std_ULogic; -- boundary crossing
signal SingleAcc: Std_ULogic; -- single access
signal WriteAcc: Std_ULogic; -- write access
signal DelDataPhase: Std_ULogic; -- restart first
signal DelAddrPhase: Std_ULogic; -- restart second
signal AHBInHGRANTx: Std_ULogic; -- decoded grant
begin
--=========================================================================--
-- AMBA AHB master interface
-----------------------------------------------------------------------------
AHBOut.HIRQ <= (others => '0');
AHBOut.HCONFIG <= HConfig;
AHBOut.HINDEX <= hindex;
AHBInHGRANTx <= AHBIn.HGRANT(hindex);
--=========================================================================--
-----------------------------------------------------------------------------
-- AMBA AHB Master interface with fast issuing of accesses
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Fixed AMBA AHB signals
-----------------------------------------------------------------------------
AHBOut.HPROT <= "0011";
-----------------------------------------------------------------------------
-- Combinatorial paths
-----------------------------------------------------------------------------
AHBOut.HADDR <= Address; -- internal to external
AHBOut.HWDATA <= ahbdrivedata(DMAIn.Data); -- combinatorial path
DMAOut.OKAY <= '1' when AHBIn.HREADY='1' and
DataPhase ='1' and
AHBIN.HRESP=HRESP_OKAY else
'0';
DMAOut.Retry <= '1' when AHBIn.HREADY='0' and
DataPhase ='1' and
(AHBIN.HRESP=HRESP_RETRY or
AHBIN.HRESP=HRESP_SPLIT) else
'0';
DMAOut.Fault <= '1' when AHBIn.HREADY='0' and
DataPhase ='1' and
AHBIN.HRESP=HRESP_ERROR else
'0';
DMAOut.Grant <= '0' when ReDataPhase='1' or ReAddrPhase='1' else
'1' when AHBIn.HREADY='1' and
AHBInHGRANTx='1' and
DMAIn.Request='1' else
'0';
AHBOut.HBUSREQ <= '0' when IdlePhase='1' else
'1' when DMAIn.Request='1' else
'1' when DMAIn.Burst='1' else
'1' when ReDataPhase='1' else
'1' when ReAddrPhase='1' else
'0';
AHBOut.HLOCK <= '0' when IdlePhase='1' else
'1' when (DMAIn.Lock and
(DMAIn.Request or ReDataPhase)) = '1'else
'0';
-----------------------------------------------------------------------------
-- The AMBA AHB interfacing is done in this process
-----------------------------------------------------------------------------
AHBMaster: process(HCLK, HRESETn)
variable BoundaryCrossing: Std_ULogic;
variable AddressInc: Std_Logic_Vector(3 downto 0);
--------------------------------------------------------------------------
-- This procedure is used to define all reset values for the
-- asynchronous or synchronous reset statements in this process. This
-- is done to avoid source code duplication.
--------------------------------------------------------------------------
procedure Reset is
begin
ActivePhase <= '0';
EarlyPhase <= '0';
AddressPhase <= '0';
DataPhase <= '0';
ReDataPhase <= '0';
ReAddrPhase <= '0';
DelDataPhase <= '0';
DelAddrPhase <= '0';
BoundaryPhase <= '0';
IdlePhase <= '0';
EarlyPhase <= '0';
SingleAcc <= '0';
WriteAcc <= '0';
Address <= (others => '0');
AddressSave <= (others => '0');
DMAOut.Ready <= '0';
DMAOut.Data <= (others => '0');
AHBOut.HSIZE <= HSIZE_BYTE;
AHBOut.HBURST <= HBURST_SINGLE;
AHBOut.HTRANS <= HTRANS_IDLE;
AHBOut.HWRITE <= '0';
end Reset; ---------------------------------------------------------------
begin
if HRESETn='0' and syncrst=0 then -- asynchronous reset
Reset;
elsif Rising_Edge(HCLK) then
if DMAIn.Reset='1' or -- functional reset
(syncrst/=0 and HRESETn='0') then -- synchronous reset
Reset;
else -- no reset
--------------------------------------------------------------------
-- Temporary variables
--------------------------------------------------------------------
BoundaryCrossing := '0';
AddressInc := (others => '0');
--------------------------------------------------------------------
-- AMBA AHB interface - data phase handling
--------------------------------------------------------------------
-- indicate when no more activies are pending
if AddressPhase='0' and DataPhase='0' and
ReDataPhase='0' and ReAddrPhase='0' and
DMAIn.Burst='0' then
ActivePhase <= '0';
end if;
if AHBIn.HREADY='0' and DataPhase='1' then
-- error check
if AHBIN.HRESP=HRESP_ERROR then
DataPhase <= '0'; -- data phase aborted
end if;
-- split or retry check
if AHBIN.HRESP=HRESP_SPLIT or
AHBIN.HRESP=HRESP_RETRY then
ReDataPhase <= DataPhase; -- restart phases
ReAddrPhase <= AddressPhase or ReAddrPhase;
AddressPhase <= '0'; -- addr phase aborted
DataPhase <= '0'; -- data phase aborted
end if;
end if;
if AHBIn.HREADY='1' and DataPhase='1' then
-- sample AHB input data at end of data phase
DMAOut.Data <= ahbreadword(AHBIn.HRDATA);
DataPhase <= '0'; -- data phase ends
DMAOut.Ready <= '1';
else
-- remove acknowledgement after one cycle
DMAOut.Ready <= '0';
end if;
--------------------------------------------------------------------
-- AMBA AHB interface - address phase handling
--------------------------------------------------------------------
-- initialize data phase on AHB after previous address phase
if AddressPhase='1' and AHBIn.HREADY='1' then
DataPhase <= '1'; -- data phase start
end if;
-- address generation on AHB
if AHBIn.HREADY='1' then
if AddressPhase='1' then
-- burst continuation, sequential transfer
AddressInc(conv_integer(DMAIn.Size)) := '1';
if boundary=1 then -- automatic boundary
Address <= Address + AddressInc;
AddressSave <= Address;
if Address(9 downto 2)="11111111" then
BoundaryCrossing := '1';
BoundaryPhase <= '1';
end if;
else
Address(31 downto 10) <= DMAIn.Address(31 downto 10);
Address( 9 downto 0) <= Address(9 downto 0) + AddressInc;
AddressSave(9 downto 0) <= Address(9 downto 0);
end if;
if DMAIn.Size=HSIZE8 then
AHBOut.HSIZE <= HSIZE_BYTE;
elsif DMAIn.Size=HSIZE16 then
AHBOut.HSIZE <= HSIZE_HWORD;
else
AHBOut.HSIZE <= HSIZE_WORD;
end if;
elsif AHBInHGRANTx='1' and ActivePhase='0' and DMAIn.Request='1' then
-- start of burst, non-sequential transfer
-- start of single, non-sequential transfer
if boundary=1 then -- automatic boundary
Address <= DMAIn.Address;
AddressSave <= DMAIn.Address;
BoundaryCrossing := '0';
BoundaryPhase <= '0';
else
Address <= DMAIn.Address;
AddressSave(9 downto 0) <= DMAIn.Address(9 downto 0);
end if;
if DMAIn.Size=HSIZE8 then
AHBOut.HSIZE <= HSIZE_BYTE;
elsif DMAIn.Size=HSIZE16 then
AHBOut.HSIZE <= HSIZE_HWORD;
else
AHBOut.HSIZE <= HSIZE_WORD;
end if;
end if;
end if;
-- address generation on AHB
if AHBIn.HREADY='1' then
IdlePhase <= '0'; -- one clock cycle only
end if;
-- initialize address phase on AHB
if AHBIn.HREADY='1' then
-- granted the AHB bus
if AHBInHGRANTx='1' then
if ReDataPhase='1' then
ReDataPhase <= '0';
AddressPhase <= '1'; -- address phase start
EarlyPhase <= '0';
AHBOut.HTRANS <= HTRANS_NONSEQ;
if SingleAcc='1' then
AHBOut.HBURST <= HBURST_SINGLE;
else
AHBOut.HBURST <= HBURST_INCR;
end if;
AHBOut.HWRITE <= WriteAcc;
-- go back with address
if boundary=1 then
Address <= AddressSave;
else
Address(9 downto 0) <= AddressSave(9 downto 0);
end if;
elsif ReAddrPhase='1' then
AddressPhase <= '1'; -- address phase start
ReAddrPhase <= '0';
if AddressPhase='1' then
if boundary=1 and (BoundaryCrossing='1' or BoundaryPhase='1') then
-- new bursts, non-sequential transfer
AHBOut.HTRANS <= HTRANS_NONSEQ;
BoundaryPhase <= '0';
else
-- burst continuation, sequential transfer
AHBOut.HTRANS <= HTRANS_SEQ;
end if;
else
AHBOut.HTRANS <= HTRANS_NONSEQ;
end if;
EarlyPhase <= '0';
if SingleAcc='1' then
AHBOut.HBURST <= HBURST_SINGLE;
else
AHBOut.HBURST <= HBURST_INCR;
end if;
AHBOut.HWRITE <= WriteAcc;
elsif EarlyPhase='1' then
-- early terminated burst resumed
AddressPhase <= '1'; -- address phase start
EarlyPhase <= '0';
AHBOut.HTRANS <= HTRANS_NONSEQ;
AHBOut.HBURST <= HBURST_INCR;
AHBOut.HWRITE <= WriteAcc;
elsif DMAIn.Request='1' and DMAIn.Burst='1' then
AddressPhase <= '1'; -- address phase start
if ActivePhase='1' then
-- burst continuation, sequential transfer
if boundary=1 and (BoundaryCrossing='1' or BoundaryPhase='1') then
-- new bursts, non-sequential transfer
AHBOut.HTRANS <= HTRANS_NONSEQ;
BoundaryPhase <= '0';
else
-- burst continuation, sequential transfer
AHBOut.HTRANS <= HTRANS_SEQ;
end if;
else
-- start of burst, non-sequential transfer
AHBOut.HTRANS <= HTRANS_NONSEQ;
if DMAIn.Beat ="00" then
AHBOut.HBURST <= HBURST_INCR;
elsif DMAIn.Beat ="01" then
AHBOut.HBURST <= HBURST_INCR4;
elsif DMAIn.Beat ="10" then
AHBOut.HBURST <= HBURST_INCR8;
else
AHBOut.HBURST <= HBURST_INCR16;
end if;
AHBOut.HWRITE <= DMAIn.Store;
ActivePhase <= '1';
SingleAcc <= '0';
WriteAcc <= DMAIn.Store;
end if;
elsif DMAIn.Request='0' and DMAIn.Burst='1' and ActivePhase='1' then
-- burst in wait state
AddressPhase <= '0'; -- no address phase
AHBOut.HTRANS <= HTRANS_BUSY;
elsif DMAIn.Request='1' and DMAIn.Burst='0' then
-- start of single, non-sequential transfer
AddressPhase <= '1'; -- address phase start
ActivePhase <= '1';
SingleAcc <= '1';
WriteAcc <= DMAIn.Store;
AHBOut.HTRANS <= HTRANS_NONSEQ;
AHBOut.HBURST <= HBURST_SINGLE;
AHBOut.HWRITE <= DMAIn.Store;
else
-- drive idle transfer as default master
-- the next cycle will start the address phase
AddressPhase <= '0'; -- no useful address
AHBOut.HTRANS <= HTRANS_IDLE;
AHBOut.HBURST <= HBURST_SINGLE;
AHBOut.HWRITE <= '0';
end if;
-- not granted the AHB bus, but early burst termination
elsif (DMAIn.Request='1' or DMAIn.Burst='1') and ActivePhase='1'then
-- must restart a burst transfer since grant removed
AddressPhase <= '0'; -- no address phase
EarlyPhase <= '1';
AHBOut.HTRANS <= HTRANS_IDLE;
AHBOut.HBURST <= HBURST_SINGLE;
AHBOut.HWRITE <= '0';
-- not granted the AHB bus
else
-- drive idle transfer as default master
-- the next cycle will start the address phase
AddressPhase <= '0'; -- no useful address
AHBOut.HTRANS <= HTRANS_IDLE;
AHBOut.HBURST <= HBURST_SINGLE;
AHBOut.HWRITE <= '0';
end if;
elsif AHBIn.HREADY='0' and DataPhase='1' then
if AHBIN.HRESP=HRESP_ERROR or
AHBIN.HRESP=HRESP_SPLIT or
AHBIN.HRESP=HRESP_RETRY then
-- drive idle transfer due to error, retry or split
-- the next cycle will start the address phase
AddressPhase <= '0'; -- no useful address
IdlePhase <= '1';
AHBOut.HTRANS <= HTRANS_IDLE;
AHBOut.HBURST <= HBURST_SINGLE;
AHBOut.HWRITE <= '0';
end if;
end if;
end if;
if AHBIn.HREADY='1' then -- delay one phase
DelDataPhase <= ReDataPhase;
DelAddrPhase <= ReAddrPhase;
end if;
-- temporary variables cleared
BoundaryCrossing := '0';
AddressInc := (others => '0');
else
null;
end if;
end process AHBMaster;
end architecture RTL; --======================================================--
| gpl-3.0 | a2384859ee9229db1104a4fdd365d222 | 0.414673 | 5.664566 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/maps/ddrphy.vhd | 1 | 56,380 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddrphy
-- File: ddrphy.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: DDR PHY with tech mapping
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
use techmap.allddr.all;
------------------------------------------------------------------
-- DDR PHY with tech mapping ------------------------------------
------------------------------------------------------------------
entity ddrphy is
generic (tech : integer := virtex2; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16;
clk_mul : integer := 2 ; clk_div : integer := 2;
rskew : integer :=0; mobile : integer := 0;
abits: integer := 14; nclk: integer := 3; ncs: integer := 2;
scantest: integer := 0; phyiconf : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- return clock
clkread : out std_ulogic; -- read clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (abits-1 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
ck : in std_logic_vector(nclk-1 downto 0);
moben : in std_logic;
dqvalid : out std_ulogic;
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end;
architecture rtl of ddrphy is
signal lddr_clk,lddr_clkb: std_logic_vector(nclk-1 downto 0);
signal lddr_clk_fb_out,lddr_clk_fb: std_logic;
signal lddr_cke, lddr_csb: std_logic_vector(ncs-1 downto 0);
signal lddr_web,lddr_rasb,lddr_casb: std_logic;
signal lddr_dm, lddr_dqs_in,lddr_dqs_out,lddr_dqs_oen: std_logic_vector(dbits/8-1 downto 0);
signal lddr_ad: std_logic_vector(abits-1 downto 0);
signal lddr_ba: std_logic_vector(1 downto 0);
signal lddr_dq_in,lddr_dq_out,lddr_dq_oen: std_logic_vector(dbits-1 downto 0);
begin
strat2 : if (tech = stratix2) generate
ddr_phy0 : stratixii_ddr_phy
generic map (MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, clk_mul => clk_mul, clk_div => clk_div, dbits => dbits
)
port map (
rst, clk, clkout, lock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke);
clkread <= '0';
dqvalid <= '1';
end generate;
cyc3 : if (tech = cyclone3) generate
ddr_phy0 : cycloneiii_ddr_phy
generic map (MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, clk_mul => clk_mul, clk_div => clk_div, dbits => dbits, rskew => rskew
)
port map (
rst, clk, clkout, lock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke);
clkread <= '0';
dqvalid <= '1';
end generate;
xc2v : if (tech = virtex2) or (tech = spartan3) generate
ddr_phy0 : virtex2_ddr_phy
generic map (MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, clk_mul => clk_mul, clk_div => clk_div, dbits => dbits, rskew => rskew
)
port map (
rst, clk, clkout, lock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke);
clkread <= '0';
dqvalid <= '1';
end generate;
xc4v : if (tech = virtex4) or (tech = virtex5) or (tech = virtex6) generate
ddr_phy0 : virtex4_ddr_phy
generic map (MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, clk_mul => clk_mul, clk_div => clk_div, dbits => dbits, rskew => rskew,
phyiconf => phyiconf
)
port map (
rst, clk, clkout, lock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke, ck);
clkread <= '0';
dqvalid <= '1';
end generate;
xc3se : if (tech = spartan3e) or (tech = spartan6) generate
ddr_phy0 : spartan3e_ddr_phy
generic map (MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, clk_mul => clk_mul, clk_div => clk_div, dbits => dbits, rskew => rskew
)
port map (
rst, clk, clkout, clkread, lock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke);
dqvalid <= '1';
end generate;
-----------------------------------------------------------------------------
-- For technologies where the PHY does not have pads,
-- instantiate ddrphy_wo_pads + pads
-----------------------------------------------------------------------------
seppads: if ddrphy_builtin_pads(tech)=0 generate
phywop: ddrphy_wo_pads
generic map (tech,MHz,rstdelay,dbits,clk_mul,clk_div,
rskew,mobile,abits,nclk,ncs,scantest,phyiconf)
port map (
rst,clk,clkout,clkoutret,clkread,lock,
lddr_clk,lddr_clkb,lddr_clk_fb_out,lddr_clk_fb,lddr_cke,lddr_csb,
lddr_web,lddr_rasb,lddr_casb,lddr_dm,
lddr_dqs_in,lddr_dqs_out,lddr_dqs_oen,
lddr_ad,lddr_ba,
lddr_dq_in,lddr_dq_out,lddr_dq_oen,
addr,ba,dqin,dqout,dm,oen,dqs,dqsoen,rasn,casn,wen,csn,cke,ck,
moben,dqvalid,testen,testrst,scanen,testoen);
pads: ddrpads
generic map (tech,dbits,abits,nclk,ncs,0)
port map (ddr_clk,ddr_clkb,ddr_clk_fb_out,ddr_clk_fb,
ddr_cke,ddr_csb,ddr_web,ddr_rasb,ddr_casb,ddr_dm,ddr_dqs,
ddr_ad,ddr_ba,ddr_dq,
open,open,open,open,open,
lddr_clk,lddr_clkb,lddr_clk_fb_out,lddr_clk_fb,
lddr_cke,lddr_csb,lddr_web,lddr_rasb,lddr_casb,lddr_dm,
lddr_dqs_in,lddr_dqs_out,lddr_dqs_oen,
lddr_ad,lddr_ba,lddr_dq_in,lddr_dq_out,lddr_dq_oen);
end generate;
nseppads: if ddrphy_builtin_pads(tech)/=0 generate
lddr_clk <= (others => '0');
lddr_clkb <= (others => '0');
lddr_clk_fb_out <= '0';
lddr_clk_fb <= '0';
lddr_cke <= (others => '0');
lddr_csb <= (others => '0');
lddr_web <= '0';
lddr_rasb <= '0';
lddr_casb <= '0';
lddr_dm <= (others => '0');
lddr_dqs_in <= (others => '0');
lddr_dqs_out <= (others => '0');
lddr_dqs_oen <= (others => '0');
lddr_ad <= (others => '0');
lddr_ba <= (others => '0');
lddr_dq_in <= (others => '0');
lddr_dq_out <= (others => '0');
lddr_dq_oen <= (others => '0');
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.allddr.all;
entity ddrphy_wo_pads is
generic (tech : integer := virtex2; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16;
clk_mul : integer := 2; clk_div : integer := 2;
rskew : integer := 0; mobile: integer := 0;
abits : integer := 14; nclk: integer := 3; ncs: integer := 2;
scantest : integer := 0; phyiconf : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock returned
clkread : out std_ulogic;
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (abits-1 downto 0);
ba : in std_logic_vector (1 downto 0);
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr output data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
ck : in std_logic_vector(nclk-1 downto 0);
moben : in std_logic;
dqvalid : out std_ulogic;
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end;
architecture rtl of ddrphy_wo_pads is
begin
gut90: if (tech = ut90) generate
ddr_phy0: ut90nhbd_ddr_phy_wo_pads
generic map (
MHz => MHz, abits => abits, dbits => dbits,
nclk => nclk, ncs => ncs)
port map (
rst, clk, clkout, clkoutret, lock,
ddr_clk, ddr_clkb, ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs_in, ddr_dqs_out, ddr_dqs_oen, ddr_ad, ddr_ba, ddr_dq_in, ddr_dq_out, ddr_dq_oen,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen, rasn, casn, wen, csn, cke, ck,
moben, dqvalid, testen, testrst, scanen, testoen
);
ddr_clk_fb_out <= '0';
clkread <= '0';
end generate;
inf : if (tech = inferred) generate
ddr_phy0 : generic_ddr_phy_wo_pads
generic map (MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, clk_mul => clk_mul, clk_div => clk_div, dbits => dbits, rskew => rskew, mobile => mobile,
abits => abits, nclk => nclk, ncs => ncs
)
port map (
rst, clk, clkout, clkoutret, lock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs_in, ddr_dqs_out, ddr_dqs_oen, ddr_ad, ddr_ba, ddr_dq_in, ddr_dq_out, ddr_dq_oen,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke, ck, moben);
clkread <= '0';
dqvalid <= '1';
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
use techmap.allddr.all;
entity ddrpads is
generic (tech: integer := virtex5;
dbits: integer := 16;
abits: integer := 14;
nclk: integer := 3;
ncs: integer := 2;
ctrl2en: integer := 0);
port (
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
-- Copy of control signals for 2nd DIMM (if ctrl2en /= 0)
ddr_web2 : out std_ulogic; -- ddr write enable
ddr_rasb2 : out std_ulogic; -- ddr ras
ddr_casb2 : out std_ulogic; -- ddr cas
ddr_ad2 : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba2 : out std_logic_vector (1 downto 0); -- ddr bank address
lddr_clk : in std_logic_vector(nclk-1 downto 0);
lddr_clkb : in std_logic_vector(nclk-1 downto 0);
lddr_clk_fb_out : in std_logic;
lddr_clk_fb : out std_logic;
lddr_cke : in std_logic_vector(ncs-1 downto 0);
lddr_csb : in std_logic_vector(ncs-1 downto 0);
lddr_web : in std_ulogic; -- ddr write enable
lddr_rasb : in std_ulogic; -- ddr ras
lddr_casb : in std_ulogic; -- ddr cas
lddr_dm : in std_logic_vector (dbits/8-1 downto 0); -- ddr dm
lddr_dqs_in : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
lddr_dqs_out : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
lddr_dqs_oen : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
lddr_ad : in std_logic_vector (abits-1 downto 0); -- ddr address
lddr_ba : in std_logic_vector (1 downto 0); -- ddr bank address
lddr_dq_in : out std_logic_vector (dbits-1 downto 0); -- ddr data
lddr_dq_out : in std_logic_vector (dbits-1 downto 0); -- ddr data
lddr_dq_oen : in std_logic_vector (dbits-1 downto 0) -- ddr data
);
end;
architecture rtl of ddrpads is
signal vcc : std_ulogic;
begin
vcc <= '1';
-- DDR clock feedback
fbclkpadgen: if ddrphy_has_fbclk(tech)/=0 generate
fbclk_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_clk_fb_out, lddr_clk_fb_out);
fbclk_in_pad : inpad generic map (tech => tech)
port map (ddr_clk_fb, lddr_clk_fb);
end generate;
nfbclkpadgen: if ddrphy_has_fbclk(tech)=0 generate
ddr_clk_fb_out <= '0';
lddr_clk_fb <= '0';
end generate;
-- External DDR clock
ddrclocks : for i in 0 to nclk-1 generate
-- DDR_CLK/B
xc456v : if (tech = virtex4) or (tech = virtex5) or (tech = virtex6) generate
ddrclk_pad : outpad_ds generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_clk(i), ddr_clkb(i), lddr_clk(i), vcc);
end generate;
noxc456v : if not ((tech = virtex4) or (tech = virtex5) or (tech = virtex6)) generate
-- DDR_CLK
ddrclk_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_clk(i), lddr_clk(i));
-- DDR_CLKB
ddrclkb_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_clkb(i), lddr_clkb(i));
end generate;
end generate;
-- DDR single-edge control signals
-- RAS
rasn_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_rasb, lddr_rasb);
-- CAS
casn_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_casb, lddr_casb);
-- WEN
wen_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_web, lddr_web);
-- BA
bagen : for i in 0 to 1 generate
ddr_ba_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_ba(i), lddr_ba(i));
end generate;
-- ADDRESS
dagen : for i in 0 to abits-1 generate
ddr_ad_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_ad(i), lddr_ad(i));
end generate;
-- CSN and CKE
ddrbanks : for i in 0 to ncs-1 generate
csn_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_csb(i), lddr_csb(i));
cke_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_cke(i), lddr_cke(i));
end generate;
-- DQS pads
dqsgen : for i in 0 to dbits/8-1 generate
dqspn_pad : iopad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (pad => ddr_dqs(i), i=> lddr_dqs_out(i), en => lddr_dqs_oen(i),
o => lddr_dqs_in(i));
end generate;
-- DQM pads
dmgen : for i in 0 to dbits/8-1 generate
ddr_bm_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_dm(i), lddr_dm(i));
end generate;
-- Data bus pads
ddgen : for i in 0 to dbits-1 generate
dq_pad : iopad generic map (tech => tech, slew => 1, level => sstl18_ii)
port map (pad => ddr_dq(i), i => lddr_dq_out(i), en => lddr_dq_oen(i),
o => lddr_dq_in(i));
end generate;
-- Second copy of address/data lines
ctrl2gen: if ctrl2en/=0 generate
rasn2_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_rasb2, lddr_rasb);
casn2_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_casb2, lddr_casb);
wen2_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_web2, lddr_web);
ba2gen : for i in 0 to 1 generate
ddr_ba_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_ba2(i), lddr_ba(i));
da2gen : for i in 0 to abits-1 generate
ddr_ad_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_ad2(i), lddr_ad(i));
end generate;
end generate;
end generate;
ctrl2ngen: if ctrl2en=0 generate
ddr_rasb2 <= '0';
ddr_casb2 <= '0';
ddr_web2 <= '0';
ddr_ba2 <= (others => '0');
ddr_ad2 <= (others => '0');
end generate;
end;
------------------------------------------------------------------
-- DDR2 PHY with tech mapping ------------------------------------
------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
use techmap.allddr.all;
entity ddr2pads is
generic (tech: integer := virtex5;
dbits: integer := 16;
eightbanks: integer := 0;
dqsse: integer range 0 to 1 := 0;
abits: integer := 14;
nclk: integer := 3;
ncs: integer := 2;
ctrl2en: integer := 0);
port (
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqsn
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
-- Copy of control signals for 2nd DIMM (if ctrl2en /= 0)
ddr_web2 : out std_ulogic; -- ddr write enable
ddr_rasb2 : out std_ulogic; -- ddr ras
ddr_casb2 : out std_ulogic; -- ddr cas
ddr_ad2 : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba2 : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
lddr_clk : in std_logic_vector(nclk-1 downto 0);
lddr_clkb : in std_logic_vector(nclk-1 downto 0);
lddr_clk_fb_out : in std_logic;
lddr_clk_fb : out std_logic;
lddr_cke : in std_logic_vector(ncs-1 downto 0);
lddr_csb : in std_logic_vector(ncs-1 downto 0);
lddr_web : in std_ulogic; -- ddr write enable
lddr_rasb : in std_ulogic; -- ddr ras
lddr_casb : in std_ulogic; -- ddr cas
lddr_dm : in std_logic_vector (dbits/8-1 downto 0); -- ddr dm
lddr_dqs_in : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
lddr_dqs_out : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
lddr_dqs_oen : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
lddr_ad : in std_logic_vector (abits-1 downto 0); -- ddr address
lddr_ba : in std_logic_vector (1+eightbanks downto 0); -- ddr bank address
lddr_dq_in : out std_logic_vector (dbits-1 downto 0); -- ddr data
lddr_dq_out : in std_logic_vector (dbits-1 downto 0); -- ddr data
lddr_dq_oen : in std_logic_vector (dbits-1 downto 0); -- ddr data
lddr_odt : in std_logic_vector(ncs-1 downto 0)
);
end;
architecture rtl of ddr2pads is
signal vcc : std_ulogic;
begin
vcc <= '1';
-- DDR clock feedback
fbclkpadgen: if ddr2phy_has_fbclk(tech)/=0 generate
fbclk_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_clk_fb_out, lddr_clk_fb_out);
fbclk_in_pad : inpad generic map (tech => tech)
port map (ddr_clk_fb, lddr_clk_fb);
end generate;
nfbclkpadgen: if ddr2phy_has_fbclk(tech)=0 generate
ddr_clk_fb_out <= '0';
lddr_clk_fb <= '0';
end generate;
-- External DDR clock
ddrclocks : for i in 0 to nclk-1 generate
-- DDR_CLK/B
xc456v : if (tech = virtex4) or (tech = virtex5) or (tech = virtex6) or (tech = spartan6)
or (tech = virtex7) or (tech = kintex7) or (tech = artix7) or (tech = zynq7000) generate
ddrclk_pad : outpad_ds generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_clk(i), ddr_clkb(i), lddr_clk(i), vcc);
end generate;
noxc456v : if not ((tech = virtex4) or (tech = virtex5) or (tech = virtex6) or (tech = spartan6)
or (tech = virtex7) or (tech = kintex7) or (tech = artix7) or (tech = zynq7000)) generate
-- DDR_CLK
ddrclk_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_clk(i), lddr_clk(i));
-- DDR_CLKB
ddrclkb_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_clkb(i), lddr_clkb(i));
end generate;
end generate;
-- DDR single-edge control signals
-- RAS
rasn_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_rasb, lddr_rasb);
-- CAS
casn_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_casb, lddr_casb);
-- WEN
wen_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_web, lddr_web);
-- BA
bagen : for i in 0 to 1+eightbanks generate
ddr_ba_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_ba(i), lddr_ba(i));
end generate;
-- ODT
odtgen : for i in 0 to ncs-1 generate
ddr_ba_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_odt(i), lddr_odt(i));
end generate;
-- ADDRESS
dagen : for i in 0 to abits-1 generate
ddr_ad_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_ad(i), lddr_ad(i));
end generate;
-- CSN and CKE
ddrbanks : for i in 0 to ncs-1 generate
csn_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_csb(i), lddr_csb(i));
cke_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_cke(i), lddr_cke(i));
end generate;
-- DQS pads
dqsse0 : if dqsse = 0 generate
dqsgen : for i in 0 to dbits/8-1 generate
dqspn_pad : iopad_ds generic map (tech => tech, slew => 1, level => sstl18_ii)
port map (padp => ddr_dqs(i), padn => ddr_dqsn(i), i=> lddr_dqs_out(i), en => lddr_dqs_oen(i),
o => lddr_dqs_in(i));
end generate;
end generate;
dqsse1 : if dqsse = 1 generate
dqsgen : for i in 0 to dbits/8-1 generate
dqspn_pad : iopad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (pad => ddr_dqs(i), i=> lddr_dqs_out(i), en => lddr_dqs_oen(i),
o => lddr_dqs_in(i));
end generate;
end generate;
-- DQM pads
dmgen : for i in 0 to dbits/8-1 generate
ddr_bm_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_dm(i), lddr_dm(i));
end generate;
-- Data bus pads
ddgen : for i in 0 to dbits-1 generate
dq_pad : iopad generic map (tech => tech, slew => 1, level => sstl18_ii)
port map (pad => ddr_dq(i), i => lddr_dq_out(i), en => lddr_dq_oen(i),
o => lddr_dq_in(i));
end generate;
-- Second copy of address/data lines
ctrl2gen: if ctrl2en/=0 generate
rasn2_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_rasb2, lddr_rasb);
casn2_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_casb2, lddr_casb);
wen2_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_web2, lddr_web);
ba2gen : for i in 0 to 1+eightbanks generate
ddr_ba_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_ba2(i), lddr_ba(i));
da2gen : for i in 0 to abits-1 generate
ddr_ad_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_ad2(i), lddr_ad(i));
end generate;
end generate;
end generate;
ctrl2ngen: if ctrl2en=0 generate
ddr_rasb2 <= '0';
ddr_casb2 <= '0';
ddr_web2 <= '0';
ddr_ba2 <= (others => '0');
ddr_ad2 <= (others => '0');
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
use techmap.allddr.all;
use techmap.allpads.n2x_padcontrol_none;
-- With built-in pads
entity ddr2phy is
generic (tech : integer := virtex5; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16;
clk_mul : integer := 2; clk_div : integer := 2;
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
ddelayb6 : integer := 0; ddelayb7 : integer := 0;
ddelayb8: integer := 0;
ddelayb9: integer := 0; ddelayb10: integer := 0; ddelayb11: integer := 0;
numidelctrl : integer := 4; norefclk : integer := 0; rskew : integer := 0;
eightbanks : integer range 0 to 1 := 0; dqsse : integer range 0 to 1 := 0;
abits : integer := 14; nclk: integer := 3; ncs: integer := 2;
ctrl2en: integer := 0;
resync: integer := 0; custombits: integer := 8; extraio: integer := 0;
scantest: integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock returned
clkresync : in std_ulogic; -- resync clock (if resync/=0)
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (extraio+dbits/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqsn
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
addr : in std_logic_vector (abits-1 downto 0);
ba : in std_logic_vector ( 2 downto 0);
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr output data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
noen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
cal_en : in std_logic_vector(dbits/8-1 downto 0);
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
cal_pll : in std_logic_vector(1 downto 0);
cal_rst : in std_logic;
odt : in std_logic_vector(ncs-1 downto 0);
oct : in std_logic;
read_pend : in std_logic_vector(7 downto 0);
regwdata : in std_logic_vector(63 downto 0);
regwrite : in std_logic_vector(1 downto 0);
regrdata : out std_logic_vector(63 downto 0);
dqin_valid : out std_ulogic;
customclk : in std_ulogic;
customdin : in std_logic_vector(custombits-1 downto 0);
customdout : out std_logic_vector(custombits-1 downto 0);
-- Copy of control signals for 2nd DIMM
ddr_web2 : out std_ulogic; -- ddr write enable
ddr_rasb2 : out std_ulogic; -- ddr ras
ddr_casb2 : out std_ulogic; -- ddr cas
ddr_ad2 : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba2 : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic;
oct_rdn : in std_logic := '0';
oct_rup : in std_logic := '0'
);
end;
architecture rtl of ddr2phy is
signal lddr_clk,lddr_clkb: std_logic_vector(nclk-1 downto 0);
signal lddr_clk_fb_out,lddr_clk_fb: std_logic;
signal lddr_cke, lddr_csb: std_logic_vector(ncs-1 downto 0);
signal lddr_web,lddr_rasb,lddr_casb: std_logic;
signal lddr_dm, lddr_dqs_in,lddr_dqs_out,lddr_dqs_oen: std_logic_vector(dbits/8-1 downto 0);
signal lddr_dqsn_in,lddr_dqsn_out,lddr_dqsn_oen: std_logic_vector(dbits/8-1 downto 0);
signal lddr_ad: std_logic_vector(abits-1 downto 0);
signal lddr_ba: std_logic_vector(1+eightbanks downto 0);
signal lddr_dq_in,lddr_dq_out,lddr_dq_oen: std_logic_vector(dbits-1 downto 0);
signal lddr_odt: std_logic_vector(ncs-1 downto 0);
signal customdin_exp: std_logic_vector(132 downto 0);
begin
customdin_exp(custombits-1 downto 0) <= customdin;
customdin_exp(customdin_exp'high downto custombits) <= (others => '0');
-- For technologies without PHY-specific registers
nreggen: if ddr2phy_has_reg(tech)=0 and ddr2phy_builtin_pads(tech)/=0 generate
regrdata <= x"0000000000000000";
end generate;
ncustgen: if ddr2phy_has_custom(tech)=0 and ddr2phy_builtin_pads(tech)/=0 generate
customdout <= (others => '0');
end generate;
stra2 : if (tech = stratix2) generate
ddr_phy0 : stratixii_ddr2_phy
generic map (MHz => MHz, rstdelay => rstdelay,
clk_mul => clk_mul, clk_div => clk_div, dbits => dbits
)
port map (
rst, clk, clkout, lock, ddr_clk, ddr_clkb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq, ddr_odt,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke, cal_en, cal_inc, cal_rst, odt);
dqin_valid <= '1';
end generate;
stra3 : if (tech = stratix3) generate
ddr_phy0 : stratixiii_ddr2_phy
generic map (MHz => MHz, rstdelay => rstdelay,
clk_mul => clk_mul, clk_div => clk_div, dbits => dbits,
ddelayb0 => ddelayb0, ddelayb1 => ddelayb1, ddelayb2 => ddelayb2,
ddelayb3 => ddelayb3, ddelayb4 => ddelayb4, ddelayb5 => ddelayb5,
ddelayb6 => ddelayb6, ddelayb7 => ddelayb7,
numidelctrl => numidelctrl, norefclk => norefclk,
tech => tech, rskew => rskew, eightbanks => eightbanks
)
port map (
rst, clk, clkref, clkout, lock,
ddr_clk, ddr_clkb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_dqsn, ddr_ad, ddr_ba, ddr_dq, ddr_odt,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke, cal_en, cal_inc, cal_pll, cal_rst, odt, oct);
dqin_valid <= '1';
end generate;
uniphy : if (tech = stratix4) generate
ddr_phy0 : uniphy_ddr2_phy
generic map (
MHz => MHz, rstdelay => rstdelay,
dbits => dbits, clk_mul => clk_mul, clk_div => clk_div,
eightbanks => eightbanks, abits => abits,
nclk => nclk, ncs => ncs)
port map (
rst => rst, clk => clk,
clkout => clkout, clkoutret => clkoutret, lock => lock,
ddr_clk => ddr_clk, ddr_clkb => ddr_clkb, ddr_cke => ddr_cke,
ddr_csb => ddr_csb, ddr_web => ddr_web, ddr_rasb => ddr_rasb, ddr_casb => ddr_casb,
ddr_dm => ddr_dm, ddr_dqs => ddr_dqs, ddr_dqsn => ddr_dqsn, ddr_ad => ddr_ad, ddr_ba => ddr_ba,
ddr_dq => ddr_dq, ddr_odt => ddr_odt,
addr => addr, ba => ba, dqin => dqin, dqout => dqout, dm => dm,
oen => oen,
rasn => rasn, casn => casn, wen => wen, csn => csn, cke => cke,
odt => odt, read_pend => read_pend, dqin_valid => dqin_valid,
regwdata => regwdata, regwrite => regwrite, regrdata => regrdata,
oct_rdn => oct_rdn, oct_rup => oct_rup);
ddr_clk_fb_out <= '0';
customdout <= (others => '0');
end generate;
sp3a : if (tech = spartan3) generate
ddr_phy0 : spartan3a_ddr2_phy
generic map (MHz => MHz, rstdelay => rstdelay,
clk_mul => clk_mul, clk_div => clk_div, dbits => dbits, tech => tech, rskew => rskew,
eightbanks => eightbanks)
port map ( rst, clk, clkout, lock, ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_dqsn, ddr_ad, ddr_ba, ddr_dq, ddr_odt,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke, cal_pll, odt);
dqin_valid <= '1';
end generate;
nextreme : if (tech = easic90) generate
ddr_phy0 : easic90_ddr2_phy
generic map (
tech => tech,
MHz => MHz,
clk_mul => clk_mul,
clk_div => clk_div,
dbits => dbits,
rstdelay => rstdelay,
eightbanks => eightbanks)
port map (
rst, clk, clkout, lock, ddr_clk, ddr_clkb, ddr_clk_fb_out,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_dqsn, ddr_ad, ddr_ba, ddr_dq, ddr_odt,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke, odt, '1');
dqin_valid <= '1';
end generate;
nextreme2 : if (tech = easic45) generate
-- This requires dbits/8 extra bidir I/O that are suppliedd on the ddr_dqs port
ddr_phy0 : n2x_ddr2_phy
generic map (
MHz => MHz, rstdelay => rstdelay,
dbits => dbits, clk_mul => clk_mul, clk_div => clk_div, norefclk => norefclk,
eightbanks => eightbanks, dqsse => dqsse, abits => abits,
nclk => nclk, ncs => ncs, ctrl2en => ctrl2en)
port map (
rst => rst, clk => clk, clk270d => clkref,
clkout => clkout, clkoutret => clkoutret, lock => lock,
ddr_clk => ddr_clk, ddr_clkb => ddr_clkb, ddr_cke => ddr_cke,
ddr_csb => ddr_csb, ddr_web => ddr_web, ddr_rasb => ddr_rasb, ddr_casb => ddr_casb,
ddr_dm => ddr_dm, ddr_dqs => ddr_dqs(dbits/8-1 downto 0), ddr_dqsn => ddr_dqsn, ddr_ad => ddr_ad, ddr_ba => ddr_ba,
ddr_dq => ddr_dq, ddr_odt => ddr_odt, rden_pad => ddr_dqs(dbits/4-1 downto dbits/8),
addr => addr, ba => ba, dqin => dqin, dqout => dqout, dm => dm,
noen => noen,
rasn => rasn, casn => casn, wen => wen, csn => csn, cke => cke,
odt => odt, read_pend => read_pend, dqin_valid => dqin_valid,
regwdata => regwdata, regwrite => regwrite, regrdata => regrdata,
ddr_web2 => ddr_web2, ddr_rasb2 => ddr_rasb2, ddr_casb2 => ddr_casb2,
ddr_ad2 => ddr_ad2, ddr_ba2 => ddr_ba2,
dq_control => customdin_exp(73 downto 56),
dqs_control => customdin_exp(55 downto 38),
ck_control => customdin_exp(37 downto 20),
cmd_control => customdin_exp(19 downto 2),
compen => customdin_exp(0),
compupd => customdin_exp(1)
);
ddr_clk_fb_out <= '0';
customdout <= (others => '0');
end generate;
-----------------------------------------------------------------------------
-- For technologies where the PHY does not have pads,
-- instantiate ddr2phy_wo_pads + pads
-----------------------------------------------------------------------------
seppads: if ddr2phy_builtin_pads(tech)=0 generate
phywop: ddr2phy_wo_pads
generic map (tech,MHz,rstdelay,dbits,clk_mul,clk_div,
ddelayb0,ddelayb1,ddelayb2,ddelayb3,
ddelayb4,ddelayb5,ddelayb6,ddelayb7,
ddelayb8,ddelayb9,ddelayb10,ddelayb11,
numidelctrl,norefclk,rskew,eightbanks,dqsse,abits,nclk,ncs,
resync,custombits,scantest)
port map (
rst,clk,clkref,clkout,clkoutret,clkresync,lock,
lddr_clk,lddr_clkb,lddr_clk_fb_out,lddr_clk_fb,lddr_cke,lddr_csb,
lddr_web,lddr_rasb,lddr_casb,lddr_dm,
lddr_dqs_in,lddr_dqs_out,lddr_dqs_oen,
lddr_ad,lddr_ba,
lddr_dq_in,lddr_dq_out,lddr_dq_oen,lddr_odt,
addr,ba,dqin,dqout,dm,oen,noen,dqs,dqsoen,rasn,casn,wen,csn,cke,
cal_en,cal_inc,cal_pll,cal_rst,odt,oct,
read_pend,regwdata,regwrite,regrdata,dqin_valid,customclk,customdin,customdout,
testen,testrst,scanen,testoen);
pads: ddr2pads
generic map (tech,dbits,eightbanks,dqsse,abits,nclk,ncs,ctrl2en)
port map (ddr_clk,ddr_clkb,ddr_clk_fb_out,ddr_clk_fb,
ddr_cke,ddr_csb,ddr_web,ddr_rasb,ddr_casb,ddr_dm,ddr_dqs,ddr_dqsn,
ddr_ad,ddr_ba,ddr_dq,ddr_odt,
ddr_web2,ddr_rasb2,ddr_casb2,ddr_ad2,ddr_ba2,
lddr_clk,lddr_clkb,lddr_clk_fb_out,lddr_clk_fb,
lddr_cke,lddr_csb,lddr_web,lddr_rasb,lddr_casb,lddr_dm,
lddr_dqs_in,lddr_dqs_out,lddr_dqs_oen,
lddr_ad,lddr_ba,lddr_dq_in,lddr_dq_out,lddr_dq_oen,lddr_odt);
end generate;
nseppads: if ddr2phy_builtin_pads(tech)/=0 generate
lddr_clk <= (others => '0');
lddr_clkb <= (others => '0');
lddr_clk_fb_out <= '0';
lddr_clk_fb <= '0';
lddr_cke <= (others => '0');
lddr_csb <= (others => '0');
lddr_web <= '0';
lddr_rasb <= '0';
lddr_casb <= '0';
lddr_dm <= (others => '0');
lddr_dqs_in <= (others => '0');
lddr_dqs_out <= (others => '0');
lddr_dqs_oen <= (others => '0');
lddr_dqsn_in <= (others => '0');
lddr_dqsn_out <= (others => '0');
lddr_dqsn_oen <= (others => '0');
lddr_ad <= (others => '0');
lddr_ba <= (others => '0');
lddr_dq_in <= (others => '0');
lddr_dq_out <= (others => '0');
lddr_dq_oen <= (others => '0');
lddr_odt <= (others => '0');
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
use techmap.allddr.all;
-- without pads (typically used for ASIC technologies)
entity ddr2phy_wo_pads is
generic (tech : integer := virtex5; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16;
clk_mul : integer := 2; clk_div : integer := 2;
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
ddelayb6 : integer := 0; ddelayb7 : integer := 0;
ddelayb8: integer := 0;
ddelayb9: integer := 0; ddelayb10: integer := 0; ddelayb11: integer := 0;
numidelctrl : integer := 4; norefclk : integer := 0; rskew : integer := 0;
eightbanks : integer range 0 to 1 := 0; dqsse : integer range 0 to 1 := 0;
abits : integer := 14; nclk: integer := 3; ncs: integer := 2;
resync : integer := 0; custombits: integer := 8; scantest: integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock returned
clkresync : in std_ulogic; -- resync clock (if resync/=0)
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
addr : in std_logic_vector (abits-1 downto 0);
ba : in std_logic_vector ( 2 downto 0);
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr output data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
noen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
cal_en : in std_logic_vector(dbits/8-1 downto 0);
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
cal_pll : in std_logic_vector(1 downto 0);
cal_rst : in std_logic;
odt : in std_logic_vector(ncs-1 downto 0);
oct : in std_logic;
read_pend : in std_logic_vector(7 downto 0);
regwdata : in std_logic_vector(63 downto 0);
regwrite : in std_logic_vector(1 downto 0);
regrdata : out std_logic_vector(63 downto 0);
dqin_valid : out std_ulogic;
customclk : in std_ulogic;
customdin : in std_logic_vector(custombits-1 downto 0);
customdout : out std_logic_vector(custombits-1 downto 0);
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end;
architecture rtl of ddr2phy_wo_pads is
begin
-- For technologies without PHY-specific registers
nreggen: if ddr2phy_has_reg(tech)=0 generate
regrdata <= x"0000000000000000";
end generate;
ncustgen: if ddr2phy_has_custom(tech)=0 generate
customdout <= (others => '0');
end generate;
xc4v : if (tech = virtex4) or (tech = virtex5) or (tech = virtex6)
or (tech = artix7) or (tech = kintex7) or (tech = virtex7) or (tech=zynq7000) generate
ddr_phy0 : virtex5_ddr2_phy_wo_pads
generic map (MHz => MHz, rstdelay => rstdelay,
clk_mul => clk_mul, clk_div => clk_div, dbits => dbits,
ddelayb0 => ddelayb0, ddelayb1 => ddelayb1, ddelayb2 => ddelayb2,
ddelayb3 => ddelayb3, ddelayb4 => ddelayb4, ddelayb5 => ddelayb5,
ddelayb6 => ddelayb6, ddelayb7 => ddelayb7, ddelayb8 => ddelayb8,
ddelayb9 => ddelayb9, ddelayb10 => ddelayb10, ddelayb11 => ddelayb11,
numidelctrl => numidelctrl, norefclk => norefclk,
tech => tech, eightbanks => eightbanks, dqsse => dqsse,
abits => abits, nclk => nclk, ncs => ncs
)
port map (
rst, clk, clkref, clkout, clkoutret, lock,
ddr_clk, ddr_clkb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs_in, ddr_dqs_out, ddr_dqs_oen,
ddr_ad, ddr_ba,
ddr_dq_in, ddr_dq_out, ddr_dq_oen,ddr_odt,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke, cal_en, cal_inc, cal_rst, odt);
ddr_clk_fb_out <= '0';
dqin_valid <= '1';
end generate;
sp6 : if (tech = spartan6) generate
ddr_phy0 : spartan6_ddr2_phy_wo_pads
generic map (
MHz => MHz, rstdelay => rstdelay,
clk_mul => clk_mul, clk_div => clk_div, dbits => dbits,
tech => tech, rskew => rskew,
eightbanks => eightbanks,
abits => abits, nclk => nclk, ncs => ncs)
port map (
rst, clk, clkout, lock,
ddr_clk, ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs_in, ddr_dqs_out, ddr_dqs_oen,
ddr_ad, ddr_ba, ddr_dq_in, ddr_dq_out, ddr_dq_oen, ddr_odt,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke, cal_en, cal_inc, cal_rst, odt);
ddr_clkb <= (others => '0');
ddr_clk_fb_out <= '0';
dqin_valid <= '1';
end generate;
inf : if (has_ddr2phy(tech) = 0) generate
ddr_phy0 : generic_ddr2_phy_wo_pads
generic map (MHz => MHz, rstdelay => rstdelay,
clk_mul => clk_mul, clk_div => clk_div, dbits => dbits, rskew => rskew,
eightbanks => eightbanks, abits => abits, nclk => nclk, ncs => ncs
)
port map (
rst, clk, clkout, clkoutret, lock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs_in, ddr_dqs_out, ddr_dqs_oen,
ddr_ad, ddr_ba,
ddr_dq_in, ddr_dq_out, ddr_dq_oen, ddr_odt,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke, "111", odt
);
dqin_valid <= '1';
end generate;
end;
-------------------------------------------------------------------------------
-- LPDDR2 phy
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.allddr.all;
entity lpddr2phy_wo_pads is
generic (
tech : integer := virtex5;
dbits : integer := 16;
nclk: integer := 3;
ncs: integer := 2;
clkratio: integer := 1;
scantest: integer := 0);
port (
rst : in std_ulogic;
clkin : in std_ulogic;
clkin2 : in std_ulogic;
clkout : out std_ulogic;
clkoutret : in std_ulogic; -- ckkout returned
clkout2 : out std_ulogic;
lock : out std_ulogic;
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_ca : out std_logic_vector(9 downto 0);
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
ca : in std_logic_vector (10*2*clkratio-1 downto 0);
cke : in std_logic_vector (ncs*clkratio-1 downto 0);
csn : in std_logic_vector (ncs*clkratio-1 downto 0);
dqin : out std_logic_vector (dbits*2*clkratio-1 downto 0); -- ddr output data
dqout : in std_logic_vector (dbits*2*clkratio-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4*clkratio-1 downto 0); -- data mask
ckstop : in std_ulogic;
boot : in std_ulogic;
wrpend : in std_logic_vector(7 downto 0);
rdpend : in std_logic_vector(7 downto 0);
wrreq : out std_logic_vector(clkratio-1 downto 0);
rdvalid : out std_logic_vector(clkratio-1 downto 0);
refcal : in std_ulogic;
refcalwu : in std_ulogic;
refcaldone : out std_ulogic;
phycmd : in std_logic_vector(7 downto 0);
phycmden : in std_ulogic;
phycmdin : in std_logic_vector(31 downto 0);
phycmdout : out std_logic_vector(31 downto 0);
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end;
architecture tmap of lpddr2phy_wo_pads is
begin
inf: if true generate
phy0: generic_lpddr2phy_wo_pads
generic map (
tech => tech,
dbits => dbits,
nclk => nclk,
ncs => ncs,
clkratio => clkratio,
scantest => scantest)
port map (
rst => rst,
clkin => clkin,
clkin2 => clkin2,
clkout => clkout,
clkoutret => clkoutret,
clkout2 => clkout2,
lock => lock,
ddr_clk => ddr_clk,
ddr_clkb => ddr_clkb,
ddr_cke => ddr_cke,
ddr_csb => ddr_csb,
ddr_ca => ddr_ca,
ddr_dm => ddr_dm,
ddr_dqs_in => ddr_dqs_in,
ddr_dqs_out => ddr_dqs_out,
ddr_dqs_oen => ddr_dqs_oen,
ddr_dq_in => ddr_dq_in,
ddr_dq_out => ddr_dq_out,
ddr_dq_oen => ddr_dq_oen,
ca => ca,
cke => cke,
csn => csn,
dqin => dqin,
dqout => dqout,
dm => dm,
ckstop => ckstop,
boot => boot,
wrpend => wrpend,
rdpend => rdpend,
wrreq => wrreq,
rdvalid => rdvalid,
refcal => refcal,
refcalwu => refcalwu,
refcaldone => refcaldone,
phycmd => phycmd,
phycmden => phycmden,
phycmdin => phycmdin,
phycmdout => phycmdout,
testen => testen,
testrst => testrst,
scanen => scanen,
testoen => testoen);
end generate;
end;
| gpl-3.0 | dc9c20e203d9e5504962c028b7fdd539 | 0.555853 | 3.286314 | false | false | false | false |
Gizeta/bjuedc | uart-fpga/uart_send.vhd | 1 | 3,646 | --------------------------------------------
-- 串口发送模块
--------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity uart_send is
generic(framelen : integer := 7); -- 数据位为 framelen + 1 位
port(
-- bclk - 发送时钟
-- reset - 复位信号
-- xmit_cmd_p - 新一轮发送启动信号
bclk_t, reset_t, xmit_cmd_p : in std_logic;
-- 待发送数据寄存器
tbuf : in std_logic_vector(7 downto 0);
-- 串行数据输出
txd : out std_logic;
-- 一帧数据(8bits)发送完毕标志
t_done : out std_logic
);
end uart_send;
architecture arch of uart_send is
-- 状态机状态
type states is (t_idle, t_start_bit, t_data_bit, t_stop_bit);
-- 初始状态为t_idle
signal state : states := t_idle;
begin
process(bclk_t, reset_t, xmit_cmd_p, tbuf)
-- 发送1bit所要保持的时钟计数器
-- (因为现在的bclk_t是baud频率的16倍)
variable count : std_logic_vector(4 downto 0) := "00000";
-- 已经发送的数据位 计数器
variable tcnt : integer range 0 to framelen := 0;
-- 串行输出数据暂存变量
variable txd_tmp : std_logic;
begin
if reset_t = '1' then
state <= t_idle;
t_done <= '0';
txd_tmp := '1';
tcnt := 0;
count := "00000";
elsif rising_edge(bclk_t) then
case state is
when t_idle =>
if xmit_cmd_p = '1' then -- 判断是否启动新一轮发送
state <= t_start_bit; -- 准备发送起始位
-- 直到有这个发送脉冲后, t_done才复位
-- 从这儿开始, 发送数据不能改变了
t_done <= '0';
txd_tmp := '0';
count := "00000";
else
state <= t_idle;
txd_tmp := '1';
end if;
when t_start_bit => -- 发送起始位
if count <= "01110" then -- 需要保持16个时钟
count := count + 1;
txd_tmp := '0';
state <= t_start_bit; -- 继续发送起始位
else
state <= t_data_bit; -- 准备开始发送数据位
count := "00000"; -- 重置为0
txd_tmp := tbuf(0); -- 发送第0位
tcnt := 0;
end if;
when t_data_bit => -- 发送数据位
if count <= "01110" then
count := count + 1;
state <= t_data_bit;
else
if tcnt = framelen then -- 判断是否已经发送完一帧(8bits)数据
state <= t_stop_bit;
tcnt := 0;
count := "00000";
txd_tmp := '1';
else
tcnt := tcnt + 1;
txd_tmp := tbuf(tcnt);
state <= t_data_bit;
count := "00000"; -- 重新计数一bit所要保持的时间
end if;
end if;
when t_stop_bit => -- 停止位也是16位
if count <= "01110" then
count := count + 1;
txd_tmp := '1';
state <= t_stop_bit;
else
state <= t_idle;
count := "00000";
txd_tmp := '1';
t_done <= '1';
end if;
when others => -- 回到t_idle状态
state <= t_idle;
end case;
end if;
txd <= txd_tmp ; -- 当txd_tmp变化时, txd就立即变化, 功能仿真时无延时
end process;
end arch;
| mit | b4bddbfc90438967f2a5aa6d7e96b746 | 0.439279 | 2.686491 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/pci/grpci2/grpci2_ahb_mst.vhd | 1 | 7,127 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: grpci2_ahb_mst
-- File: grpci2_ahb_mst.vhd
-- Author: Nils-Johan Wessman - Aeroflex Gaisler
-- Description: GRPCI2 AHB master interface
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
use work.pcilib2.all;
entity grpci2_ahb_mst is
generic(
hindex : integer := 0;
venid : integer := VENDOR_GAISLER;
devid : integer := 0;
version : integer := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
dmai0 : in dma_ahb_in_type;
dmao0 : out dma_ahb_out_type;
dmai1 : in dma_ahb_in_type;
dmao1 : out dma_ahb_out_type
);
end entity;
architecture rtl of grpci2_ahb_mst is
type reg_type is record
bg : std_ulogic; --bus granted
bo : std_ulogic; --bus owner, 0=dma0, 1=dma1
ba : std_ulogic; --bus active
bb : std_ulogic; --1kB burst boundary detected
retry : std_ulogic;
end record;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( venid, devid, 0, version, 0),
others => zero32);
signal r, rin : reg_type;
begin
comb : process(rst, r, dmai1, dmai0, ahbmi) is
variable v : reg_type;
variable htrans : std_logic_vector(1 downto 0);
variable hbusreq : std_ulogic;
variable hwrite : std_ulogic;
variable haddr : std_logic_vector(31 downto 0);
variable hwdata : std_logic_vector(31 downto 0);
variable nbo : std_ulogic;
variable retry1 : std_ulogic;
variable retry0 : std_ulogic;
variable ready0 : std_ulogic;
variable ready1 : std_ulogic;
variable error0 : std_ulogic;
variable error1 : std_ulogic;
variable grant1 : std_ulogic;
variable grant0 : std_ulogic;
variable hsize : std_logic_vector(2 downto 0);
variable hburst : std_logic_vector(2 downto 0);
begin
v := r; htrans := HTRANS_IDLE; ready0 := '0'; ready1 := '0'; retry1 := '0';
retry0 := '0'; error0 := '0'; error1 := '0'; grant1 := '0'; grant0 := '0';
hsize := HSIZE_WORD;
hburst := HBURST_INCR;
if r.bo = '0' then hwdata := dmai0.data;
else hwdata := dmai1.data; end if;
hbusreq := dmai1.req or dmai0.req;
if hbusreq = '1' then htrans := HTRANS_NONSEQ; end if;
if r.retry = '0' then
nbo := dmai1.req and not (dmai0.req and not r.bo);
else
nbo := r.bo;
end if;
if nbo = '0' then
haddr := dmai0.addr; hwrite := dmai0.write; hsize := '0' & dmai0.size;
if dmai0.burst = '0' then hburst := HBURST_SINGLE; end if;
if (dmai0.req and r.ba
and not r.bo and not r.retry and dmai0.size(1)) = '1' and dmai0.burst = '1' then
htrans := HTRANS_SEQ;
end if;
if (dmai0.req and r.bg and ahbmi.hready and not r.retry) = '1'
then grant0 := '1'; end if;
else
haddr := dmai1.addr; hwrite := dmai1.write; hsize := '0' & dmai1.size;
if dmai1.burst = '0' then hburst := HBURST_SINGLE; end if;
if (dmai1.req and r.ba
and r.bo and not r.retry and dmai1.size(1)) = '1' and dmai1.burst = '1' then
htrans := HTRANS_SEQ;
end if;
if (dmai1.req and r.bg and ahbmi.hready and not r.retry) = '1'
then grant1 := '1'; end if;
end if;
--1 kB burst boundary
if ahbmi.hready = '1' then
if haddr(9 downto 2) = "11111111"
then
v.bb := '1';
if htrans = HTRANS_SEQ then hbusreq := '0'; end if;
elsif ((dmai0.noreq and grant0) or (dmai1.noreq and grant1)) = '1' then
v.bb := '1';
hbusreq := '0';
else
v.bb := '0';
end if;
end if;
if (r.bb = '1') and (htrans /= HTRANS_IDLE) then
htrans := HTRANS_NONSEQ;
end if;
if r.bo = '0' then
if r.ba = '1' then
if ahbmi.hready = '1' then
case ahbmi.hresp is
when HRESP_OKAY => ready0 := '1';
when HRESP_SPLIT | HRESP_RETRY => retry0 := '1';
when HRESP_ERROR => error0 := '1';
when others => null;
end case;
end if;
end if;
else
if r.ba = '1' then
if ahbmi.hready = '1' then
case ahbmi.hresp is
when HRESP_OKAY => ready1 := '1';
when HRESP_SPLIT | HRESP_RETRY => retry1 := '1';
when HRESP_ERROR => error1 := '1';
when others => null;
end case;
end if;
end if;
end if;
if (r.ba = '1') and
((ahbmi.hresp = HRESP_RETRY) or (ahbmi.hresp = HRESP_SPLIT) or (ahbmi.hresp = HRESP_ERROR))
then v.retry := not ahbmi.hready; else v.retry := '0'; end if;
if r.retry = '1' then htrans := HTRANS_IDLE; end if;
if ahbmi.hready = '1' then
v.bo := nbo; v.bg := ahbmi.hgrant(hindex);
if (htrans = HTRANS_NONSEQ) or (htrans = HTRANS_SEQ) then
v.ba := r.bg;
else
v.ba := '0';
end if;
end if;
if rst = '0' then
v.bg := '0'; v.ba := '0'; v.bo := '0'; v.bb := '0';
end if;
rin <= v;
dmao1.data <= ahbreadword(ahbmi.hrdata);
dmao0.data <= ahbreadword(ahbmi.hrdata);
dmao1.error <= error1;
dmao1.retry <= retry1;
dmao1.ready <= ready1;
dmao0.error <= error0;
dmao0.retry <= retry0;
dmao0.ready <= ready0;
dmao1.grant <= grant1;
dmao0.grant <= grant0;
ahbmo.htrans <= htrans;
ahbmo.hsize <= hsize;
ahbmo.hbusreq <= hbusreq;
ahbmo.haddr <= haddr;
ahbmo.hwrite <= hwrite;
ahbmo.hwdata <= ahbdrivedata(hwdata);
ahbmo.hburst <= hburst;
ahbmo.hconfig <= hconfig;
ahbmo.hindex <= hindex;
end process;
regs : process(clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process;
ahbmo.hlock <= '0';
ahbmo.hprot <= "0011";
ahbmo.hirq <= (others => '0');
end architecture;
| gpl-3.0 | 9bd9a0c6e8ca609468cdca2792cc4120 | 0.558019 | 3.42809 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/maps/inpad_ds.vhd | 1 | 3,890 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: inpad_ds
-- File: inpad_ds.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: input pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity inpad_ds is
generic (tech : integer := 0; level : integer := lvds; voltage : integer := x33v; term : integer := 0);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of inpad_ds is
signal gnd : std_ulogic;
begin
gnd <= '0';
gen0 : if has_ds_pads(tech) = 0 generate
o <= to_X01(padp)
-- pragma translate_off
after 1 ns
-- pragma translate_on
;
end generate;
xcv : if (tech = virtex2) or (tech = spartan3) generate
u0 : unisim_inpad_ds generic map (level, voltage, term) port map (padp, padn, o);
end generate;
xc4v : if (tech = virtex4) or (tech = spartan3e) or (tech = virtex5) or (tech = spartan6)
or (tech = virtex6) or (tech = virtex7) or (tech = kintex7) or (tech =artix7) or (tech =zynq7000) generate
u0 : virtex4_inpad_ds generic map (level, voltage) port map (padp, padn, o);
end generate;
axc : if (tech = axcel) or (tech = axdsp) generate
u0 : axcel_inpad_ds generic map (level, voltage) port map (padp, padn, o);
end generate;
pa3 : if (tech = apa3) generate
u0 : apa3_inpad_ds generic map (level) port map (padp, padn, o);
end generate;
igl2 : if (tech = igloo2) or (tech = rtg4) generate
u0 : igloo2_inpad_ds port map (padp, padn, o);
end generate;
pa3e : if (tech = apa3e) generate
u0 : apa3e_inpad_ds generic map (level) port map (padp, padn, o);
end generate;
pa3l : if (tech = apa3l) generate
u0 : apa3l_inpad_ds generic map (level) port map (padp, padn, o);
end generate;
fus : if (tech = actfus) generate
u0 : fusion_inpad_ds generic map (level) port map (padp, padn, o);
end generate;
rht : if (tech = rhlib18t) generate
u0 : rh_lib18t_inpad_ds port map (padp, padn, o, gnd);
end generate;
n2x : if (tech = easic45) generate
u0 : n2x_inpad_ds generic map (level, voltage) port map (padp, padn, o);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity inpad_dsv is
generic (tech : integer := 0; level : integer := lvds;
voltage : integer := x33v; width : integer := 1; term : integer := 0);
port (
padp : in std_logic_vector(width-1 downto 0);
padn : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0));
end;
architecture rtl of inpad_dsv is
begin
v : for i in width-1 downto 0 generate
u0 : inpad_ds generic map (tech, level, voltage, term) port map (padp(i), padn(i), o(i));
end generate;
end;
| gpl-3.0 | 488b35f796da45ca7d533328fe384789 | 0.634704 | 3.457778 | false | false | false | false |
hoglet67/CoPro6502 | src/DCM/dcm_32_16.vhd | 1 | 2,067 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity dcm_32_16 is
port (CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic);
end dcm_32_16;
architecture BEHAVIORAL of dcm_32_16 is
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKFX_BUFG_INST : BUFG
port map (I => CLKFX_BUF, O => CLK0_OUT);
DCM_INST : DCM
generic map(CLK_FEEDBACK => "NONE",
CLKDV_DIVIDE => 4.0, -- 16.000 = 32.000 * 10/20
CLKFX_DIVIDE => 20,
CLKFX_MULTIPLY => 10,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => 31.25,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => true,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => false)
port map (CLKFB => GND_BIT,
CLKIN => CLKIN_IN,
DSSEN => GND_BIT,
PSCLK => GND_BIT,
PSEN => GND_BIT,
PSINCDEC => GND_BIT,
RST => GND_BIT,
CLKDV => open,
CLKFX => CLKFX_BUF,
CLKFX180 => open,
CLK0 => open,
CLK2X => open,
CLK2X180 => open,
CLK90 => open,
CLK180 => open,
CLK270 => open,
LOCKED => open,
PSDONE => open,
STATUS => open);
end BEHAVIORAL;
| gpl-3.0 | eb7d8151b7d9b09f36824ff979803f86 | 0.405418 | 4.235656 | false | false | false | false |
pwsoft/fpga_examples | rtl/designs/gigatron/gigatron_sdram_ctrl.vhd | 1 | 7,585 | -- -----------------------------------------------------------------------
--
-- Turbo Chameleon
--
-- Multi purpose FPGA expansion for the Commodore 64 computer
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2021 by Peter Wendrich ([email protected])
-- http://www.syntiac.com/chameleon.html
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
--
-- Part of the Gigatron emulator.
-- A SDRAM controller to emulate the 16-bit wide code ROM.
--
-- -----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- -----------------------------------------------------------------------
entity gigatron_sdram_ctrl is
generic (
clk_ticks_per_usec : integer;
refresh_period_us : integer := 64000;
colbits : integer := 9;
rowbits : integer := 13;
setup_cycles : integer := 2
);
port (
clk : in std_logic;
reset : in std_logic;
-- Parameters
cas_latency : in unsigned(1 downto 0) := "10";
ras_nops : in unsigned(3 downto 0) := "0001";
write_nops : in unsigned(3 downto 0) := "0000";
precharge_nops : in unsigned(3 downto 0) := "0001";
refresh_nops : in unsigned(3 downto 0) := "0110";
-- Initial ROM image load from spi-flash
romload_req : in std_logic;
romload_ack : out std_logic;
romload_a : in unsigned((rowbits+colbits+2) downto 0);
romload_d : in unsigned(7 downto 0);
-- Reading of 16-bit ROM data from emulation
rom_req : in std_logic;
rom_ack : out std_logic;
rom_a : in unsigned(15 downto 0);
rom_q : out unsigned(15 downto 0);
-- SDRAM interface
ram_data : inout unsigned(15 downto 0);
ram_addr : out unsigned((rowbits-1) downto 0);
ram_ba : out unsigned(1 downto 0);
ram_we : out std_logic;
ram_ras : out std_logic;
ram_cas : out std_logic;
ram_ldqm : out std_logic;
ram_udqm : out std_logic
);
end entity;
architecture rtl of gigatron_sdram_ctrl is
constant refresh_interval : integer := (refresh_period_us * clk_ticks_per_usec) / (2**rowbits);
constant refresh_timer_range : integer := refresh_interval*3;
type state_t is (
ST_RESET,
ST_INIT_PRECHARGE, ST_SETMODE, ST_IDLE,
ST_LOADROM_CAS, ST_ROM_CAS, ST_ROM_DATA,
ST_REFRESH);
signal state_reg : state_t := ST_RESET;
signal refresh_timer_reg : integer range 0 to refresh_timer_range := 0;
signal timer_reg : unsigned(3 downto 0) := (others => '0');
signal ram_oe_reg : std_logic := '0';
signal ram_ras_reg : std_logic := '1';
signal ram_cas_reg : std_logic := '1';
signal ram_we_reg : std_logic := '1';
signal ram_ba_reg : unsigned(ram_ba'range) := (others => '0');
signal ram_data_reg : unsigned(ram_data'range) := (others => '0');
signal ram_addr_reg : unsigned(ram_addr'range) := (others => '0');
signal ram_ldqm_reg : std_logic := '1';
signal ram_udqm_reg : std_logic := '1';
signal romload_req_reg : std_logic := '0';
signal romload_ack_reg : std_logic := '0';
signal romload_bank : unsigned(ram_ba'range);
signal romload_row : unsigned(ram_addr'range);
signal romload_col : unsigned(colbits-1 downto 0);
signal rom_req_reg : std_logic := '0';
signal rom_ack_reg : std_logic := '0';
signal rom_q_reg : unsigned(rom_q'range) := (others => '0');
signal rom_bank : unsigned(ram_ba'range);
signal rom_row : unsigned(ram_addr'range);
signal rom_col : unsigned(colbits-1 downto 0);
begin
romload_ack <= romload_ack_reg;
rom_ack <= rom_ack_reg;
rom_q <= rom_q_reg;
ram_ras <= ram_ras_reg;
ram_cas <= ram_cas_reg;
ram_we <= ram_we_reg;
ram_ba <= ram_ba_reg;
ram_data <= ram_data_reg when ram_oe_reg = '1' else (others => 'Z');
ram_addr <= ram_addr_reg;
ram_ldqm <= ram_ldqm_reg;
ram_udqm <= ram_udqm_reg;
romload_bank <= romload_a(rowbits+colbits+2 downto rowbits+colbits+1);
romload_row <= romload_a(rowbits+colbits downto colbits+1);
romload_col <= romload_a(colbits downto 1);
rom_bank <= "00";
rom_row <= "000000" & rom_a(15 downto 9);
rom_col <= rom_a(8 downto 0);
process(clk)
begin
if rising_edge(clk) then
ram_addr_reg <= (others => '0');
ram_data_reg <= (others => '0');
ram_oe_reg <= '0';
ram_ras_reg <= '1';
ram_cas_reg <= '1';
ram_we_reg <= '1';
ram_ldqm_reg <= '0';
ram_udqm_reg <= '0';
refresh_timer_reg <= refresh_timer_reg + 1;
if timer_reg /= 0 then
timer_reg <= timer_reg - 1;
else
case state_reg is
when ST_RESET =>
state_reg <= ST_INIT_PRECHARGE;
timer_reg <= (others => '1');
when ST_INIT_PRECHARGE =>
ram_ras_reg <= '0';
ram_we_reg <= '0';
-- Precharge all banks
ram_addr_reg(10) <= '1';
timer_reg <= precharge_nops;
state_reg <= ST_SETMODE;
when ST_SETMODE =>
ram_ras_reg <= '0';
ram_cas_reg <= '0';
ram_we_reg <= '0';
ram_ba_reg <= "00";
-- A2-A0=111 burst length, A3=0 sequential, A6-A4 cas-latency, rest reserved or default 0
ram_addr_reg <= "0000000" & cas_latency & "0000";
timer_reg <= to_unsigned(setup_cycles - 1, timer_reg'length);
state_reg <= ST_IDLE;
when ST_IDLE =>
if romload_req /= romload_req_reg then
romload_req_reg <= romload_req;
ram_ras_reg <= '0';
ram_ba_reg <= romload_bank;
ram_addr_reg <= romload_row;
timer_reg <= ras_nops;
state_reg <= ST_LOADROM_CAS;
elsif rom_req /= rom_req_reg then
rom_req_reg <= rom_req;
ram_ras_reg <= '0';
ram_ba_reg <= rom_bank;
ram_addr_reg <= rom_row;
timer_reg <= ras_nops;
state_reg <= ST_ROM_CAS;
elsif refresh_timer_reg > refresh_interval then
state_reg <= ST_REFRESH;
end if;
when ST_LOADROM_CAS =>
ram_cas_reg <= '0';
ram_we_reg <= '0';
ram_ba_reg <= romload_bank;
ram_addr_reg(romload_col'range) <= romload_col;
ram_addr_reg(10) <= '1';
ram_data_reg <= romload_d & romload_d;
ram_oe_reg <= '1';
ram_ldqm_reg <= romload_a(0);
ram_udqm_reg <= not romload_a(0);
timer_reg <= precharge_nops;
romload_ack_reg <= romload_req_reg;
state_reg <= ST_IDLE;
when ST_ROM_CAS =>
ram_cas_reg <= '0';
ram_ba_reg <= rom_bank;
ram_addr_reg(romload_col'range) <= rom_col;
ram_addr_reg(10) <= '1';
timer_reg <= "0010";
if cas_latency = 3 then
timer_reg <= "0011";
end if;
state_reg <= ST_ROM_DATA;
when ST_ROM_DATA =>
rom_q_reg <= ram_data;
rom_ack_reg <= rom_req_reg;
state_reg <= ST_IDLE;
when ST_REFRESH =>
refresh_timer_reg <= refresh_timer_reg - refresh_interval;
timer_reg <= refresh_nops;
ram_ras_reg <= '0';
ram_cas_reg <= '0';
state_reg <= ST_IDLE;
end case;
end if;
if reset = '1' then
state_reg <= ST_RESET;
romload_req_reg <= romload_req;
romload_ack_reg <= romload_req;
rom_req_reg <= rom_req;
rom_ack_reg <= rom_req;
end if;
end if;
end process;
end architecture;
| lgpl-2.1 | a0a36a921b5f6bd2ba9b87c9c9bc40f4 | 0.592617 | 2.935372 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/l2cache/pkg/l2cache.vhd | 1 | 3,160 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: l2cache
-- File: libcache.vhd
-- Author: Nils-Johan Wessman - Gaisler Research
-- Description: L2-Cache component declaration
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
package l2cache is
component l2c is
generic (
hslvidx : integer := 0;
hmstidx : integer := 0;
haddr : integer := 16#F00#;
hmask : integer := 16#F00#;
ioaddr : integer := 16#000#;
cached : integer := 16#0000#;
hirq : integer := 0;
cen : integer range 0 to 1 := 0;
hproten : integer range 0 to 1 := 0;
wp : integer range 0 to 1 := 0;
repl : integer range 0 to 1 := 0;
ways : integer range 1 to 4 := 1;
linesize : integer range 16 to 64 := 32;
waysize : integer range 1 to 512 := 1;
memtech : integer range 0 to NTECH := 0;
bbuswidth : integer := 128;
bioaddr : integer := 16#000#;
biomask : integer := 16#000#;
sbus : integer := 0;
mbus : integer := 1;
stat : integer range 0 to 2 := 0;
scantest : integer := 0;
arch : integer := 0;
mtrr : integer := 0;
edacen : integer range 0 to 1 := 0;
rmw : integer range 0 to 1 := 0;
ft : integer range 0 to 1 := 0;
fttiming : integer range 0 to 1 := 0;
wbmask : integer range 0 to 16#FFFF# := 16#FFFF#;
debug : integer range 0 to 1 := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbsov: in ahb_slv_out_vector;
sto : out std_logic_vector(10 downto 0);
debugo: out std_logic_vector(255*debug downto 0)
);
end component;
end;
package body l2cache is
end;
| gpl-3.0 | 59bde760835d4575755e933783fa7092 | 0.563608 | 3.82104 | false | false | false | false |
yishinli/emc2 | src/hal/drivers/m5i20/hostmot5_src/pwmgenh.vhd | 1 | 4,664 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity pwmgenh is
port (
clk: in STD_LOGIC;
hclk: in STD_LOGIC;
refcount: in STD_LOGIC_VECTOR (9 downto 0);
ibus: in STD_LOGIC_VECTOR (15 downto 0);
obus: out STD_LOGIC_VECTOR (15 downto 0);
loadpwmval: in STD_LOGIC;
readpwmval: in STD_LOGIC;
clearpwmval: in STD_LOGIC;
pcrloadcmd: STD_LOGIC;
pcrreadcmd: STD_LOGIC;
pwmout: out STD_LOGIC;
dirio: inout STD_LOGIC;
enablein: in STD_LOGIC;
enableout: out STD_LOGIC
);
end pwmgenh;
architecture behavioral of pwmgenh is
signal pwmval: STD_LOGIC_VECTOR (9 downto 0);
signal prepwmval: STD_LOGIC_VECTOR (9 downto 0);
signal fixedpwmval: STD_LOGIC_VECTOR (9 downto 0);
signal fixedrefcount: STD_LOGIC_VECTOR (9 downto 0);
signal pwm: STD_LOGIC;
signal dir: STD_LOGIC;
signal unsignedmode: STD_LOGIC;
signal localenable: STD_LOGIC;
signal lacedpwm: STD_LOGIC;
signal predir: STD_LOGIC;
signal preunsignedmode: STD_LOGIC;
signal prelocalenable: STD_LOGIC;
signal prelacedpwm: STD_LOGIC;
signal loadpwmreq: STD_LOGIC;
signal oldloadpwmreq: STD_LOGIC;
signal olderloadpwmreq: STD_LOGIC;
signal loadpcrreq: STD_LOGIC;
signal oldloadpcrreq: STD_LOGIC;
signal olderloadpcrreq: STD_LOGIC;
begin
apwmgen: process (clk,
hclk,
refcount,
ibus,
loadpwmval,
readpwmval,
clearpwmval,
enablein,
localenable,
lacedpwm,
pwmval,
dir,
pcrreadcmd,
pwm
)
begin
if hclk'event and hclk = '1' then
if oldloadpwmreq = '1' and olderloadpwmreq = '1'then
pwmval <= prepwmval;
dir <= predir;
end if;
if oldloadpcrreq = '1' and olderloadpcrreq ='1' then
unsignedmode <= preunsignedmode;
lacedpwm <= prelacedpwm;
localenable <= prelocalenable;
end if;
olderloadpwmreq <= oldloadpwmreq;
olderloadpcrreq <= oldloadpcrreq;
oldloadpwmreq <= loadpwmreq;
oldloadpcrreq <= loadpcrreq;
if unsignedmode = '0' then
if dir = '1' then
-- fixedpwmval <= (not pwmval) +1; -- convert from 2s comp to magnitude
-- suffers from overflow problem
fixedpwmval <= (not pwmval); -- convert from 2s comp to magnitude
-- suffers from discontinuity at 0 but thats more palatable than overflow
else
fixedpwmval <= pwmval;
end if;
dirio <= dir;
else -- unsigned mode
fixedpwmval <= pwmval;
dirio <= 'Z';
end if;
if lacedpwm = '1' then -- interlaced (600 kc) output for analog
fixedrefcount(9) <= refcount(4);
fixedrefcount(8) <= refcount(5);
fixedrefcount(7) <= refcount(6);
fixedrefcount(6) <= refcount(7);
fixedrefcount(5) <= refcount(8);
fixedrefcount(4) <= refcount(9);
fixedrefcount(3 downto 0) <= refcount(3 downto 0);
else
fixedrefcount <= refcount;
end if;
if (UNSIGNED(fixedrefcount) < UNSIGNED(fixedpwmval)) and (enablein = '1') and (localenable = '1') then
pwm <= '1';
else
pwm <= '0';
end if;
pwmout <= pwm;
end if; -- hclk
if clk'event and clk = '1' then -- 33 mhz local bus clock
if loadpwmval = '1' then
if unsignedmode = '0' then -- signed mode
prepwmval <= ibus(14 downto 5);
predir <= ibus(15);
else -- unsigned mode
prepwmval <= ibus(15 downto 6);
end if;
loadpwmreq <= '1';
end if;
if pcrloadcmd = '1' then
preunsignedmode <= ibus(2);
prelacedpwm <= ibus(1);
prelocalenable <= ibus(0);
loadpcrreq <= '1';
end if;
end if; -- clk
if olderloadpwmreq = '1' then -- asyncronous request clear
loadpwmreq <= '0';
end if;
if olderloadpcrreq = '1' then -- asyncronous request clear
loadpcrreq <= '0';
end if;
if clearpwmval = '1' then -- asynchronous reset
pwmval <= "0000000000";
localenable <= '0';
end if;
if readpwmval = '1' and pcrreadcmd = '0' then
if unsignedmode = '0' then
obus(14 downto 5) <= pwmval;
obus(15) <= dir;
obus(4 downto 0) <= "00000";
else
obus(15 downto 6) <= pwmval;
obus(5 downto 0) <= "000000";
end if;
elsif readpwmval = '0' and pcrreadcmd = '1' then
obus(5) <= clearpwmval;
obus(4) <= dirio;
obus(3) <= pwm;
obus(2) <= unsignedmode;
obus(1) <= lacedpwm;
obus(0) <= localenable;
obus(15 downto 5) <="00000000000";
else
obus <= "ZZZZZZZZZZZZZZZZ";
end if;
enableout <= not localenable;
end process;
end behavioral;
| lgpl-2.1 | 1543591d987d9c962f9fec6a29a55ab0 | 0.610849 | 2.97449 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-ztex-ufm-111/testbench.vhd | 1 | 7,169 | -------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2011 Aeroflex Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.debug.all;
use work.config.all;
library micron;
use micron.components.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sdramfile : string := "ram.srec"; -- sdram contents
constant lresp : boolean := false;
signal reset : std_ulogic := '1';
signal clk48 : std_ulogic := '0';
signal errorn : std_logic;
signal mcb3_dram_dq : std_logic_vector(15 downto 0);
signal mcb3_rzq : std_logic;
signal mcb3_dram_dqs : std_logic_vector(1 downto 0);
signal mcb3_dram_a : std_logic_vector(12 downto 0);
signal mcb3_dram_ba : std_logic_vector(1 downto 0);
signal mcb3_dram_cke : std_logic;
signal mcb3_dram_ras_n : std_logic;
signal mcb3_dram_cas_n : std_logic;
signal mcb3_dram_we_n : std_logic;
signal mcb3_dram_dm : std_logic_vector(1 downto 0);
signal mcb3_dram_ck : std_logic;
signal mcb3_dram_ck_n : std_logic;
signal dsubre : std_ulogic; -- Debug Unit break (connect to button)
signal dsuact : std_ulogic; -- Debug Unit break (connect to button)
signal dsurx : std_ulogic;
signal dsutx : std_ulogic;
signal rxd1 : std_ulogic;
signal txd1 : std_ulogic;
signal sd_dat : std_logic;
signal sd_cmd : std_logic;
signal sd_sck : std_logic;
signal sd_dat3 : std_logic;
signal csb : std_logic := '0'; -- dummy
begin
-- clock and reset
clk48 <= not clk48 after 10.417 ns;
reset <= '1', '0' after 300 ns;
dsubre <= '0';
sd_dat <= 'H';
sd_cmd <= 'H';
sd_sck <= 'H';
d3 : entity work.leon3mp
generic map (fabtech, memtech, padtech, clktech, disas, dbguart, pclow)
port map (
reset => reset,
clk48 => clk48,
-- Processor error output
errorn => errorn,
-- DDR SDRAM
mcb3_dram_dq => mcb3_dram_dq,
mcb3_rzq => mcb3_rzq,
mcb3_dram_udqs => mcb3_dram_dqs(1),
mcb3_dram_dqs => mcb3_dram_dqs(0),
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_dm => mcb3_dram_dm(0),
mcb3_dram_udm => mcb3_dram_dm(1),
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
-- Debug support unit
dsubre => dsubre,
dsuact => dsuact,
-- AHB UART (debug link)
dsurx => dsurx,
dsutx => dsutx,
-- UART
rxd1 => rxd1,
txd1 => txd1,
-- SD card
sd_dat => sd_dat,
sd_cmd => sd_cmd,
sd_sck => sd_sck,
sd_dat3 => sd_dat3
);
migddr2mem : if (CFG_MIG_DDR2 = 1) generate
ddr0 : ddrram
generic map(width => 16, abits => 13, colbits => 10, rowbits => 13,
implbanks => 1, fname => sdramfile, speedbin=>4, lddelay => 15 us)
port map (ck => mcb3_dram_ck, cke => mcb3_dram_cke, csn => csb,
rasn => mcb3_dram_ras_n, casn => mcb3_dram_cas_n, wen => mcb3_dram_we_n,
dm => mcb3_dram_dm, ba => mcb3_dram_ba, a => mcb3_dram_a,
dq => mcb3_dram_dq, dqs => mcb3_dram_dqs);
end generate;
--spimem0: if CFG_SPIMCTRL = 1 generate
-- s0 : spi_flash generic map (ftype => 4, debug => 0, fname => promfile,
-- readcmd => CFG_SPIMCTRL_READCMD,
-- dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
-- dualoutput => 0) -- Dual output is not supported in this design
-- port map (spi_clk, spi_mosi, data(24), spi_sel_n);
--end generate spimem0;
iuerr : process
begin
wait for 5 us;
assert (to_X01(errorn) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure;
end process;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#ef#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
--
-- txc(dsutx, 16#80#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end;
| gpl-3.0 | 8ec51a45bf26e9f707e8ef08a242e270 | 0.552239 | 3.360994 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/uart/apbuart.vhd | 1 | 21,003 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: uart
-- File: uart.vhd
-- Authors: Jiri Gaisler - Gaisler Research
-- Marko Isomaki - Gaisler Research
-- Description: Asynchronous UART. Implements 8-bit data frame with one stop-bit.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--use ieee.numeric_std.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.uart.all;
--pragma translate_off
use std.textio.all;
--pragma translate_on
entity apbuart is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
console : integer := 0;
pirq : integer := 0;
parity : integer := 1;
flow : integer := 1;
fifosize : integer range 1 to 32 := 1;
abits : integer := 8;
sbits : integer range 12 to 32 := 12);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
uarti : in uart_in_type;
uarto : out uart_out_type);
end;
architecture rtl of apbuart is
constant REVISION : integer := 1;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_APBUART, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
type rxfsmtype is (idle, startbit, data, cparity, stopbit);
type txfsmtype is (idle, data, cparity, stopbit);
type fifo is array (0 to fifosize - 1) of std_logic_vector(7 downto 0);
type uartregs is record
rxen : std_ulogic; -- receiver enabled
txen : std_ulogic; -- transmitter enabled
rirqen : std_ulogic; -- receiver irq enable
tirqen : std_ulogic; -- transmitter irq enable
parsel : std_ulogic; -- parity select
paren : std_ulogic; -- parity select
flow : std_ulogic; -- flow control enable
loopb : std_ulogic; -- loop back mode enable
debug : std_ulogic; -- debug mode enable
rsempty : std_ulogic; -- receiver shift register empty (internal)
tsempty : std_ulogic; -- transmitter shift register empty
stop : std_ulogic; -- 0: one stop bit, 1: two stop bits
tsemptyirqen : std_ulogic; -- generate irq when tx shift register is empty
break : std_ulogic; -- break detected
breakirqen : std_ulogic; -- generate irq when break has been received
ovf : std_ulogic; -- receiver overflow
parerr : std_ulogic; -- parity error
frame : std_ulogic; -- framing error
ctsn : std_logic_vector(1 downto 0); -- clear to send
rtsn : std_ulogic; -- request to send
extclken : std_ulogic; -- use external baud rate clock
extclk : std_ulogic; -- rising edge detect register
rhold : fifo;
rshift : std_logic_vector(7 downto 0);
tshift : std_logic_vector(9 downto 0);
thold : fifo;
irq : std_ulogic; -- tx/rx interrupt (internal)
irqpend : std_ulogic; -- pending irq for delayed rx irq
delayirqen : std_ulogic; -- enable delayed rx irq
tpar : std_ulogic; -- tx data parity (internal)
txstate : txfsmtype;
txclk : std_logic_vector(2 downto 0); -- tx clock divider
txtick : std_ulogic; -- tx clock (internal)
rxstate : rxfsmtype;
rxclk : std_logic_vector(2 downto 0); -- rx clock divider
rxdb : std_logic_vector(1 downto 0); -- rx delay
dpar : std_ulogic; -- rx data parity (internal)
rxtick : std_ulogic; -- rx clock (internal)
tick : std_ulogic; -- rx clock (internal)
scaler : std_logic_vector(sbits-1 downto 0);
brate : std_logic_vector(sbits-1 downto 0);
rxf : std_logic_vector(4 downto 0); -- rx data filtering buffer
txd : std_ulogic; -- transmitter data
rfifoirqen : std_ulogic; -- receiver fifo interrupt enable
tfifoirqen : std_ulogic; -- transmitter fifo interrupt enable
irqcnt : std_logic_vector(5 downto 0); -- delay counter for rx irq
--fifo counters
rwaddr : std_logic_vector(log2x(fifosize) - 1 downto 0);
rraddr : std_logic_vector(log2x(fifosize) - 1 downto 0);
traddr : std_logic_vector(log2x(fifosize) - 1 downto 0);
twaddr : std_logic_vector(log2x(fifosize) - 1 downto 0);
rcnt : std_logic_vector(log2x(fifosize) downto 0);
tcnt : std_logic_vector(log2x(fifosize) downto 0);
end record;
constant rcntzero : std_logic_vector(log2x(fifosize) downto 0) := (others => '0');
constant addrzero : std_logic_vector(log2x(fifosize)-1 downto 0) := (others => '0');
constant sbitszero : std_logic_vector(sbits-1 downto 0) := (others => '0');
constant fifozero : fifo := (others => (others => '0'));
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RES : uartregs :=
(rxen => '0', txen => '0', rirqen => '0', tirqen => '0', parsel => '0',
paren => '0', flow => '0', loopb => '0', debug => '0', rsempty => '1',
tsempty => '1', stop => '0', tsemptyirqen => '0', break => '0', breakirqen => '0',
ovf => '0', parerr => '0', frame => '0', ctsn => (others => '0'),
rtsn => '1', extclken => '0', extclk => '0', rhold => fifozero,
rshift => (others => '0'), tshift => (others => '1'), thold => fifozero,
irq => '0', irqpend => '0', delayirqen => '0', tpar => '0', txstate => idle,
txclk => (others => '0'), txtick => '0', rxstate => idle,
rxclk => (others => '0'), rxdb => (others => '0'), dpar => '0',rxtick => '0',
tick => '0', scaler => sbitszero, brate => sbitszero, rxf => (others => '0'),
txd => '1', rfifoirqen => '0', tfifoirqen => '0', irqcnt => (others => '0'),
rwaddr => addrzero, rraddr => addrzero, traddr => addrzero, twaddr => addrzero,
rcnt => rcntzero, tcnt => rcntzero);
signal r, rin : uartregs;
begin
uartop : process(rst, r, apbi, uarti )
variable rdata : std_logic_vector(31 downto 0);
variable scaler : std_logic_vector(sbits-1 downto 0);
variable rxclk, txclk : std_logic_vector(2 downto 0);
variable rxd, ctsn : std_ulogic;
variable irq : std_logic_vector(NAHBIRQ-1 downto 0);
variable paddress : std_logic_vector(7 downto 2);
variable v : uartregs;
variable thalffull : std_ulogic;
variable rhalffull : std_ulogic;
variable rfull : std_ulogic;
variable tfull : std_ulogic;
variable dready : std_ulogic;
variable thempty : std_ulogic;
--pragma translate_off
variable L1 : line;
variable CH : character;
variable FIRST : boolean := true;
variable pt : time := 0 ns;
--pragma translate_on
begin
v := r; irq := (others => '0'); irq(pirq) := r.irq;
v.irq := '0'; v.txtick := '0'; v.rxtick := '0'; v.tick := '0';
rdata := (others => '0'); v.rxdb(1) := r.rxdb(0);
dready := '0'; thempty := '1'; thalffull := '1'; rhalffull := '0';
v.ctsn := r.ctsn(0) & uarti.ctsn;
paddress := (others => '0');
paddress(abits-1 downto 2) := apbi.paddr(abits-1 downto 2);
if fifosize = 1 then
dready := r.rcnt(0); rfull := dready; tfull := r.tcnt(0);
thempty := not tfull;
else
tfull := r.tcnt(log2x(fifosize)); rfull := r.rcnt(log2x(fifosize));
if (r.rcnt(log2x(fifosize)) or r.rcnt(log2x(fifosize) - 1)) = '1' then
rhalffull := '1';
end if;
if ((r.tcnt(log2x(fifosize)) or r.tcnt(log2x(fifosize) - 1))) = '1' then
thalffull := '0';
end if;
if r.rcnt /= rcntzero then dready := '1'; end if;
if r.tcnt /= rcntzero then thempty := '0'; end if;
end if;
-- scaler
scaler := r.scaler - 1;
if (r.rxen or r.txen) = '1' then
v.scaler := scaler;
v.tick := scaler(sbits-1) and not r.scaler(sbits-1);
if v.tick = '1' then v.scaler := r.brate; end if;
end if;
-- optional external uart clock
v.extclk := uarti.extclk;
if r.extclken = '1' then v.tick := r.extclk and not uarti.extclk; end if;
-- read/write registers
if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
case paddress(7 downto 2) is
when "000000" =>
rdata(7 downto 0) := r.rhold(conv_integer(r.rraddr));
if fifosize = 1 then v.rcnt(0) := '0';
else
if r.rcnt /= rcntzero then
v.rraddr := r.rraddr + 1; v.rcnt := r.rcnt - 1;
end if;
end if;
when "000001" =>
if fifosize /= 1 then
rdata (26 + log2x(fifosize) downto 26) := r.rcnt;
rdata (20 + log2x(fifosize) downto 20) := r.tcnt;
rdata (10 downto 7) := rfull & tfull & rhalffull & thalffull;
end if;
rdata(6 downto 0) := r.frame & r.parerr & r.ovf &
r.break & thempty & r.tsempty & dready;
--pragma translate_off
if CONSOLE = 1 then rdata(2 downto 1) := "11"; end if;
--pragma translate_on
when "000010" =>
if fifosize > 1 then
rdata(31) := '1';
end if;
rdata(15) := r.stop;
rdata(14) := r.tsemptyirqen;
rdata(13) := r.delayirqen;
rdata(12) := r.breakirqen;
rdata(11) := r.debug;
if fifosize /= 1 then
rdata(10 downto 9) := r.rfifoirqen & r.tfifoirqen;
end if;
rdata(8 downto 0) := r.extclken & r.loopb &
r.flow & r.paren & r.parsel & r.tirqen & r.rirqen & r.txen & r.rxen;
when "000011" =>
rdata(sbits-1 downto 0) := r.brate;
when "000100" =>
-- Read TX FIFO.
if r.debug = '1' and r.tcnt /= rcntzero then
rdata(7 downto 0) := r.thold(conv_integer(r.traddr));
if fifosize = 1 then
v.tcnt(0) := '0';
else
v.traddr := r.traddr + 1;
v.tcnt := r.tcnt - 1;
end if;
end if;
when others =>
null;
end case;
end if;
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case paddress(7 downto 2) is
when "000000" =>
when "000001" =>
v.frame := apbi.pwdata(6);
v.parerr := apbi.pwdata(5);
v.ovf := apbi.pwdata(4);
v.break := apbi.pwdata(3);
when "000010" =>
v.stop := apbi.pwdata(15);
v.tsemptyirqen := apbi.pwdata(14);
v.delayirqen := apbi.pwdata(13);
v.breakirqen := apbi.pwdata(12);
v.debug := apbi.pwdata(11);
if fifosize /= 1 then
v.rfifoirqen := apbi.pwdata(10);
v.tfifoirqen := apbi.pwdata(9);
end if;
v.extclken := apbi.pwdata(8);
v.loopb := apbi.pwdata(7);
v.flow := apbi.pwdata(6);
v.paren := apbi.pwdata(5);
v.parsel := apbi.pwdata(4);
v.tirqen := apbi.pwdata(3);
v.rirqen := apbi.pwdata(2);
v.txen := apbi.pwdata(1);
v.rxen := apbi.pwdata(0);
when "000011" =>
v.brate := apbi.pwdata(sbits-1 downto 0);
v.scaler := apbi.pwdata(sbits-1 downto 0);
when "000100" =>
-- Write RX fifo and generate irq
if flow /= 0 then
v.rhold(conv_integer(r.rwaddr)) := apbi.pwdata(7 downto 0);
if fifosize = 1 then v.rcnt(0) := '1';
else v.rwaddr := r.rwaddr + 1; v.rcnt := v.rcnt + 1; end if;
if r.debug = '1' then
v.irq := v.irq or r.rirqen;
end if;
end if;
when others =>
null;
end case;
end if;
-- tx clock
txclk := r.txclk + 1;
if r.tick = '1' then
v.txclk := txclk;
v.txtick := r.txclk(2) and not txclk(2);
end if;
-- rx clock
rxclk := r.rxclk + 1;
if r.tick = '1' then
v.rxclk := rxclk;
v.rxtick := r.rxclk(2) and not rxclk(2);
end if;
if (r.rxtick and r.delayirqen) = '1' then
v.irqcnt := v.irqcnt + 1;
end if;
if r.irqcnt(5 downto 4) = "11" then
v.irq := v.irq or (r.delayirqen and r.irqpend); -- make sure no tx irqs are lost !
v.irqpend := '0';
end if;
-- filter rx data
-- v.rxf := r.rxf(6 downto 0) & uarti.rxd;
-- if ((r.rxf(7) & r.rxf(7) & r.rxf(7) & r.rxf(7) & r.rxf(7) & r.rxf(7) &
-- r.rxf(7)) = r.rxf(6 downto 0))
-- then v.rxdb(0) := r.rxf(7); end if;
v.rxf(1 downto 0) := r.rxf(0) & uarti.rxd; -- meta-stability filter
if r.tick = '1' then
v.rxf(4 downto 2) := r.rxf(3 downto 1);
end if;
v.rxdb(0) := (r.rxf(4) and r.rxf(3)) or (r.rxf(4) and r.rxf(2)) or
(r.rxf(3) and r.rxf(2));
-- loop-back mode
if r.loopb = '1' then
v.rxdb(0) := r.tshift(0); ctsn := dready and not r.rsempty;
elsif (flow = 1) then ctsn := r.ctsn(1); else ctsn := '0'; end if;
rxd := r.rxdb(0);
-- transmitter operation
case r.txstate is
when idle => -- idle and stopbit state
if (r.txtick = '1') then v.tsempty := '1'; end if;
if ((not r.debug and r.txen and (not thempty) and r.txtick) and
((not ctsn) or not r.flow)) = '1' then
v.txstate := data;
v.tpar := r.parsel; v.tsempty := '0';
v.txclk := "00" & r.tick; v.txtick := '0';
v.tshift := '0' & r.thold(conv_integer(r.traddr)) & '0';
if fifosize = 1 then
v.irq := r.irq or r.tirqen; v.tcnt(0) := '0';
else
v.traddr := r.traddr + 1;
v.tcnt := r.tcnt - 1;
end if;
end if;
when data => -- transmit data frame
if r.txtick = '1' then
v.tpar := r.tpar xor r.tshift(1);
v.tshift := '1' & r.tshift(9 downto 1);
if r.tshift(9 downto 1) = "111111110" then
if r.paren = '1' then
v.tshift(0) := r.tpar; v.txstate := cparity;
else
v.tshift(0) := '1'; v.txstate := idle;
end if;
end if;
end if;
when cparity => -- transmit parity bit
if r.txtick = '1' then
v.tshift := '1' & r.tshift(9 downto 1);
if r.stop = '1' then
v.txstate := stopbit;
else
v.txstate := idle;
end if;
end if;
when stopbit =>
if r.txtick = '1' then
v.txstate := idle;
end if;
end case;
-- writing of tx data register must be done after tx fsm to get correct
-- operation of thempty flag
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case paddress(4 downto 2) is
when "000" =>
if fifosize = 1 then
v.thold(0) := apbi.pwdata(7 downto 0); v.tcnt(0) := '1';
else
v.thold(conv_integer(r.twaddr)) := apbi.pwdata(7 downto 0);
if not (tfull = '1') then
v.twaddr := r.twaddr + 1; v.tcnt := v.tcnt + 1;
end if;
end if;
--pragma translate_off
if CONSOLE = 1 then
if first then L1:= new string'(""); first := false; end if; --'
if apbi.penable'event then --'
CH := character'val(conv_integer(apbi.pwdata(7 downto 0))); --'
if CH = CR then
std.textio.writeline(OUTPUT, L1);
elsif CH /= LF then
std.textio.write(L1,CH);
end if;
pt := now;
end if;
end if;
--pragma translate_on
when others => null;
end case;
end if;
-- receiver operation
case r.rxstate is
when idle => -- wait for start bit
if ((r.rsempty = '0') and not (rfull = '1')) then
v.rsempty := '1';
v.rhold(conv_integer(r.rwaddr)) := r.rshift;
if fifosize = 1 then v.rcnt(0) := '1';
else v.rwaddr := r.rwaddr + 1; v.rcnt := v.rcnt + 1; end if;
end if;
if (r.rxen and r.rxdb(1) and (not rxd)) = '1' then
v.rxstate := startbit; v.rshift := (others => '1'); v.rxclk := "100";
if v.rsempty = '0' then v.ovf := '1'; end if;
v.rsempty := '0'; v.rxtick := '0';
end if;
when startbit => -- check validity of start bit
if r.rxtick = '1' then
if rxd = '0' then
v.rshift := rxd & r.rshift(7 downto 1); v.rxstate := data;
v.dpar := r.parsel;
else
v.rxstate := idle;
end if;
end if;
when data => -- receive data frame
if r.rxtick = '1' then
v.dpar := r.dpar xor rxd;
v.rshift := rxd & r.rshift(7 downto 1);
if r.rshift(0) = '0' then
if r.paren = '1' then v.rxstate := cparity;
else v.rxstate := stopbit; v.dpar := '0'; end if;
end if;
end if;
when cparity => -- receive parity bit
if r.rxtick = '1' then
v.dpar := r.dpar xor rxd; v.rxstate := stopbit;
end if;
when stopbit => -- receive stop bit
if r.rxtick = '1' then
if r.delayirqen = '0' then
v.irq := v.irq or r.rirqen; -- make sure no tx irqs are lost !
end if;
if rxd = '1' then
if r.delayirqen = '1' then
v.irqpend := r.rirqen; v.irqcnt := (others => '0');
end if;
v.parerr := r.parerr or r.dpar; v.rsempty := r.dpar;
if not (rfull = '1') and (r.dpar = '0') then
v.rsempty := '1';
v.rhold(conv_integer(r.rwaddr)) := r.rshift;
if fifosize = 1 then v.rcnt(0) := '1';
else v.rwaddr := r.rwaddr + 1; v.rcnt := v.rcnt + 1; end if;
end if;
else
if r.rshift = "00000000" then
v.break := '1';
v.irq := v.irq or r.breakirqen;
else v.frame := '1'; end if;
v.rsempty := '1';
end if;
v.rxstate := idle;
end if;
end case;
if r.rxtick = '1' then
v.rtsn := (rfull and not r.rsempty) or r.loopb;
end if;
v.txd := r.tshift(0) or r.loopb or r.debug;
if fifosize /= 1 then
if thempty = '0' and v.tcnt = rcntzero then
v.irq := v.irq or r.tirqen;
end if;
v.irq := v.irq or (r.tfifoirqen and r.txen and thalffull);
v.irq := v.irq or (r.rfifoirqen and r.rxen and rhalffull);
if (r.rfifoirqen and r.rxen and rhalffull) = '1' then
v.irqpend := '0';
end if;
end if;
v.irq := v.irq or (r.tsemptyirqen and v.tsempty and not r.tsempty);
-- reset operation
if (not RESET_ALL) and (rst = '0') then
v.frame := RES.frame; v.rsempty := RES.rsempty;
v.parerr := RES.parerr; v.ovf := RES.ovf; v.break := RES.break;
v.tsempty := RES.tsempty; v.stop := RES.stop; v.txen := RES.txen; v.rxen := RES.rxen;
v.txstate := RES.txstate; v.rxstate := RES.rxstate; v.tshift(0) := RES.tshift(0);
v.extclken := RES.extclken; v.rtsn := RES.rtsn; v.flow := RES.flow;
v.txclk := RES.txclk; v.rxclk := RES.rxclk;
v.rcnt := RES.rcnt; v.tcnt := RES.tcnt;
v.rwaddr := RES.rwaddr; v.twaddr := RES.twaddr;
v.rraddr := RES.rraddr; v.traddr := RES.traddr;
v.irqcnt := RES.irqcnt; v.irqpend := RES.irqpend;
end if;
-- update registers
rin <= v;
-- drive outputs
uarto.txd <= r.txd; uarto.rtsn <= r.rtsn;
uarto.scaler <= (others => '0');
uarto.scaler(sbits-1 downto 0) <= r.scaler;
apbo.prdata <= rdata; apbo.pirq <= irq;
apbo.pindex <= pindex;
uarto.txen <= r.txen; uarto.rxen <= r.rxen;
uarto.flow <= '0';
end process;
apbo.pconfig <= pconfig;
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
if RESET_ALL and rst = '0' then
r <= RES;
-- Sync. registers not reset
r.ctsn <= rin.ctsn;
r.rxf <= rin.rxf;
end if;
end if;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("apbuart" & tost(pindex) &
": Generic UART rev " & tost(REVISION) & ", fifo " & tost(fifosize) &
", irq " & tost(pirq) & ", scaler bits " & tost(sbits));
-- pragma translate_on
end;
| gpl-3.0 | dfda3f4069dfe96261417bd2ae027436 | 0.542113 | 3.334868 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-asic/pads.vhd | 1 | 26,685 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2013 Aeroflex Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.config.all;
library techmap;
use techmap.gencomp.all;
entity pads is
generic (
padtech : integer := 0;
padlevel : integer := 0;
padvoltage : integer := 0;
padfilter : integer := 0;
padstrength : integer := 0;
padslew : integer := 0;
padclkarch : integer := 0;
padhf : integer := 0;
spw_input_type : integer := 0;
jtag_padfilter : integer := 0;
testen_padfilter : integer := 0;
resetn_padfilter : integer := 0;
clk_padfilter : integer := 0;
spw_padstrength : integer := 0;
jtag_padstrength : integer := 0;
uart_padstrength : integer := 0;
dsu_padstrength : integer := 0;
oepol : integer := 0
);
port (
----------------------------------------------------------------------------
--to chip boundary
----------------------------------------------------------------------------
resetn : in std_ulogic;
clksel : in std_logic_vector (1 downto 0);
clk : in std_ulogic;
lock : out std_ulogic;
errorn : inout std_ulogic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
cb : inout std_logic_vector(7 downto 0);
sdclk : out std_ulogic;
sdcsn : out std_logic_vector (1 downto 0);
sdwen : out std_ulogic;
sdrasn : out std_ulogic;
sdcasn : out std_ulogic;
sddqm : out std_logic_vector (3 downto 0);
dsutx : out std_ulogic;
dsurx : in std_ulogic;
dsuen : in std_ulogic;
dsubre : in std_ulogic;
dsuact : out std_ulogic;
txd1 : out std_ulogic;
rxd1 : in std_ulogic;
txd2 : out std_ulogic;
rxd2 : in std_ulogic;
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_ulogic;
writen : out std_ulogic;
read : out std_ulogic;
iosn : out std_ulogic;
romsn : out std_logic_vector (1 downto 0);
brdyn : in std_ulogic;
bexcn : in std_ulogic;
wdogn : inout std_ulogic;
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
i2c_scl : inout std_ulogic;
i2c_sda : inout std_ulogic;
spi_miso : in std_ulogic;
spi_mosi : out std_ulogic;
spi_sck : out std_ulogic;
spi_slvsel : out std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
prom32 : in std_ulogic;
spw_clksel : in std_logic_vector (1 downto 0);
spw_clk : in std_ulogic;
spw_rxd : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxs : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txd : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txs : out std_logic_vector(0 to CFG_SPW_NUM-1);
gtx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(7 downto 0);
erx_dv : in std_ulogic;
etx_clk : in std_ulogic;
etxd : out std_logic_vector(7 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
emdint : in std_ulogic;
emdio : inout std_logic;
emdc : out std_ulogic;
testen : in std_ulogic;
trst : in std_ulogic;
tck : in std_ulogic;
tms : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
---------------------------------------------------------------------------
--to core
---------------------------------------------------------------------------
lresetn : out std_ulogic;
lclksel : out std_logic_vector (1 downto 0);
lclk : out std_ulogic;
llock : in std_ulogic;
lerrorn : in std_ulogic;
laddress : in std_logic_vector(27 downto 0);
ldatain : out std_logic_vector(31 downto 0);
ldataout : in std_logic_vector(31 downto 0);
ldataen : in std_logic_vector(31 downto 0);
lcbin : out std_logic_vector(7 downto 0);
lcbout : in std_logic_vector(7 downto 0);
lcben : in std_logic_vector(7 downto 0);
lsdclk : in std_ulogic;
lsdcsn : in std_logic_vector (1 downto 0);
lsdwen : in std_ulogic;
lsdrasn : in std_ulogic;
lsdcasn : in std_ulogic;
lsddqm : in std_logic_vector (3 downto 0);
ldsutx : in std_ulogic;
ldsurx : out std_ulogic;
ldsuen : out std_ulogic;
ldsubre : out std_ulogic;
ldsuact : in std_ulogic;
ltxd1 : in std_ulogic;
lrxd1 : out std_ulogic;
ltxd2 : in std_ulogic;
lrxd2 : out std_ulogic;
lramsn : in std_logic_vector (4 downto 0);
lramoen : in std_logic_vector (4 downto 0);
lrwen : in std_logic_vector (3 downto 0);
loen : in std_ulogic;
lwriten : in std_ulogic;
lread : in std_ulogic;
liosn : in std_ulogic;
lromsn : in std_logic_vector (1 downto 0);
lbrdyn : out std_ulogic;
lbexcn : out std_ulogic;
lwdogn : in std_ulogic;
lgpioin : out std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
lgpioout : in std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
lgpioen : in std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
li2c_sclout : in std_ulogic;
li2c_sclen : in std_ulogic;
li2c_sclin : out std_ulogic;
li2c_sdaout : in std_ulogic;
li2c_sdaen : in std_ulogic;
li2c_sdain : out std_ulogic;
lspi_miso : out std_ulogic;
lspi_mosi : in std_ulogic;
lspi_sck : in std_ulogic;
lspi_slvsel : in std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
lprom32 : out std_ulogic;
lspw_clksel : out std_logic_vector (1 downto 0);
lspw_clk : out std_ulogic;
lspw_rxd : out std_logic_vector(0 to CFG_SPW_NUM-1);
lspw_rxs : out std_logic_vector(0 to CFG_SPW_NUM-1);
lspw_txd : in std_logic_vector(0 to CFG_SPW_NUM-1);
lspw_txs : in std_logic_vector(0 to CFG_SPW_NUM-1);
lgtx_clk : out std_ulogic;
lerx_clk : out std_ulogic;
lerxd : out std_logic_vector(7 downto 0);
lerx_dv : out std_ulogic;
letx_clk : out std_ulogic;
letxd : in std_logic_vector(7 downto 0);
letx_en : in std_ulogic;
letx_er : in std_ulogic;
lerx_er : out std_ulogic;
lerx_col : out std_ulogic;
lerx_crs : out std_ulogic;
lemdint : out std_ulogic;
lemdioin : out std_logic;
lemdioout : in std_logic;
lemdioen : in std_logic;
lemdc : in std_ulogic;
ltesten : out std_ulogic;
ltrst : out std_ulogic;
ltck : out std_ulogic;
ltms : out std_ulogic;
ltdi : out std_ulogic;
ltdo : in std_ulogic;
ltdoen : in std_ulogic
);
end;
architecture rtl of pads is
signal vcc,gnd : std_logic;
begin
vcc <= '1';
gnd <= '0';
------------------------------------------------------------------------------
-- Clocking and clock pads
------------------------------------------------------------------------------
reset_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => resetn_padfilter,
strength => padstrength)
port map (
pad => resetn,
o => lresetn);
clk_pad : clkpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
arch => padclkarch,
hf => padhf,
filter => clk_padfilter)
port map (
pad => clk,
o => lclk);
clksel_pad : inpadv
generic map(
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter,
strength => padstrength,
width => 2)
port map(
pad => clksel,
o => lclksel);
spwclk_pad : clkpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
arch => padclkarch,
hf => padhf,
filter => clk_padfilter)
port map (
pad => spw_clk,
o => lspw_clk);
spwclksel_pad : inpadv
generic map(
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter,
strength => padstrength,
width => 2)
port map(
pad => spw_clksel,
o => lspw_clksel);
------------------------------------------------------------------------------
-- Test / Misc pads
------------------------------------------------------------------------------
wdogn_pad : toutpad
generic map (
tech => padtech,
level => padlevel,
slew => padslew,
voltage => padvoltage,
strength => padstrength,
oepol => oepol)
port map(
pad => wdogn,
en => lwdogn,
i => gnd);
testen_pad : inpad
generic map(
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => testen_padfilter,
strength => padstrength)
port map(
pad => testen,
o => ltesten);
lockpad : outpad
generic map (
tech => padtech,
level => padlevel,
slew => padslew,
voltage => padvoltage,
strength => padstrength)
port map (
pad => lock,
i => llock);
errorn_pad : toutpad
generic map (
tech => padtech,
level => padlevel,
slew => padslew,
voltage => padvoltage,
strength => padstrength,
oepol => oepol)
port map(
pad => errorn,
en => lerrorn,
i => gnd);
------------------------------------------------------------------------------
-- JTAG pads
------------------------------------------------------------------------------
trst_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => jtag_padfilter)
port map (
pad => trst,
o => ltrst);
tck_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => jtag_padfilter)
port map (
pad => tck,
o => ltck);
tms_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => jtag_padfilter)
port map (
pad => tms,
o => ltms);
tdi_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => jtag_padfilter)
port map (
pad => tdi,
o => ltdi);
tdo_pad : outpad
generic map (
tech => padtech,
level => padlevel,
slew => padslew,
voltage => padvoltage,
strength => jtag_padstrength)
port map (
pad => tdo,
i => ltdo);
------------------------------------------------------------------------------
-- DSU pads
------------------------------------------------------------------------------
dsuen_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter)
port map (
pad => dsuen,
o => ldsuen);
dsubre_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter)
port map (
pad => dsubre,
o => ldsubre);
dsuact_pad : outpad
generic map (
tech => padtech,
level => padlevel,
slew => padslew,
voltage => padvoltage,
strength => dsu_padstrength)
port map (
pad => dsuact,
i => ldsuact);
dsurx_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter)
port map (
pad => dsurx,
o => ldsurx);
dsutx_pad : outpad
generic map (
tech => padtech,
level => padlevel,
slew => padslew,
voltage => padvoltage,
strength => dsu_padstrength)
port map (
pad => dsutx,
i => ldsutx);
------------------------------------------------------------------------------
-- UART pads
------------------------------------------------------------------------------
rxd1_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter,
strength => padstrength)
port map (
pad => rxd1,
o => lrxd1);
txd1_pad : outpad
generic map (
tech => padtech,
level => padlevel,
slew => padslew,
voltage => padvoltage,
strength => uart_padstrength)
port map (
pad => txd1,
i => ltxd1);
rxd2_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter,
strength => padstrength)
port map (
pad => rxd2,
o => lrxd2);
txd2_pad : outpad
generic map (
tech => padtech,
level => padlevel,
slew => padslew,
voltage => padvoltage,
strength => uart_padstrength)
port map (
pad => txd2,
i => ltxd2);
------------------------------------------------------------------------------
-- SPI pads
------------------------------------------------------------------------------
miso_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter,
strength => padstrength)
port map(
pad => spi_miso,
o => lspi_miso);
mosi_pad : outpad
generic map (
tech => padtech,
level => padlevel,
slew => padslew,
voltage => padvoltage,
strength => padstrength)
port map(
pad => spi_mosi,
i => lspi_mosi);
sck_pad : outpad
generic map (
tech => padtech,
level => padlevel,
slew => padslew,
voltage => padvoltage,
strength => padstrength)
port map(
pad => spi_sck,
i => lspi_sck);
slvsel_pad : outpadv
generic map (
width => CFG_SPICTRL_SLVS,
tech => padtech,
level => padlevel,
slew => padslew,
voltage => padvoltage,
strength => padstrength)
port map (
pad => spi_slvsel,
i => lspi_slvsel);
------------------------------------------------------------------------------
-- I2C pads
------------------------------------------------------------------------------
scl_pad : iopad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
oepol => oepol,
strength => padstrength)
port map (
pad => i2c_scl,
i => li2c_sclout,
en => li2c_sclen,
o => li2c_sclin);
sda_pad : iopad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
oepol => oepol,
strength => padstrength)
port map (
pad => i2c_sda,
i => li2c_sdaout,
en => li2c_sdaen,
o => li2c_sdain);
------------------------------------------------------------------------------
-- Memory Interface pads
------------------------------------------------------------------------------
addr_pad : outpadv generic map (width => 28, tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (address, laddress);
data_pad : iopadvv generic map (width => 32, tech => padtech, level => padlevel, voltage => padvoltage, oepol => oepol, strength => padstrength) port map (pad => data, i => ldataout, en => ldataen, o => ldatain);
rams_pad : outpadv generic map (width => 5, tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (ramsn, lramsn);
roms_pad : outpadv generic map (width => 2, tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (romsn, lromsn);
ramoen_pad : outpadv generic map (width => 5, tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (ramoen, lramoen);
rwen_pad : outpadv generic map (width => 4, tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (rwen, lrwen);
oen_pad : outpad generic map (tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (oen, loen);
wri_pad : outpad generic map (tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (writen, lwriten);
read_pad : outpad generic map (tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (read, lread);
iosn_pad : outpad generic map (tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (iosn, liosn);
cb_pad : iopadvv generic map (width => 8, tech => padtech, level => padlevel, voltage => padvoltage, oepol => oepol, strength => padstrength) port map (pad => cb, i => lcbout, en => lcben, o => lcbin);
sdpads : if CFG_MCTRL_SDEN = 1 generate
sdclk_pad : outpad generic map (tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (sdclk, lsdclk);
sdwen_pad : outpad generic map (tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (sdwen, lsdwen);
sdras_pad : outpad generic map (tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (sdrasn, lsdrasn);
sdcas_pad : outpad generic map (tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (sdcasn, lsdcasn);
sddqm_pad : outpadv generic map (width => 4, tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (sddqm, lsddqm);
sdcsn_pad : outpadv generic map (width => 2, tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (sdcsn, lsdcsn);
end generate;
brdyn_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => pullup)
port map (
pad => brdyn,
o => lbrdyn);
bexcn_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => pullup)
port map (
pad => bexcn,
o => lbexcn);
prom32_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => pullup)
port map (
pad => prom32,
o => lprom32);
------------------------------------------------------------------------------
-- GPIO pads
------------------------------------------------------------------------------
gpio_pads : iopadvv
generic map (
width => CFG_GRGPIO_WIDTH,
tech => padtech,
level => padlevel,
voltage => padvoltage,
oepol => oepol,
strength => padstrength)
port map (
pad => gpio,
i => lgpioout,
en => lgpioen,
o => lgpioin);
------------------------------------------------------------------------------
-- SpW pads
------------------------------------------------------------------------------
spwpads0 : if CFG_SPW_EN > 0 generate
spwlvttl_pads : entity work.spw_lvttl_pads
generic map(
padtech => padtech,
strength => spw_padstrength,
input_type => spw_input_type,
voltage => padvoltage,
level => padlevel)
port map(
spw_rxd => spw_rxd,
spw_rxs => spw_rxs,
spw_txd => spw_txd,
spw_txs => spw_txs,
lspw_rxd => lspw_rxd,
lspw_rxs => lspw_rxs,
lspw_txd => lspw_txd,
lspw_txs => lspw_txs);
end generate;
nospwpads0 : if CFG_SPW_EN = 0 generate
spw_txd <= (others => '0');
spw_txs <= (others => '0');
lspw_rxd <= (others => '0');
lspw_rxs <= (others => '0');
end generate;
------------------------------------------------------------------------------
-- ETHERNET
------------------------------------------------------------------------------
greth1g: if CFG_GRETH1G = 1 generate
gtx_pad : clkpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
arch => padclkarch,
hf => padhf,
filter => clk_padfilter)
port map (
pad => gtx_clk,
o => lgtx_clk);
end generate;
nogreth1g: if CFG_GRETH1G = 0 generate
lgtx_clk <= '0';
end generate;
ethpads : if (CFG_GRETH = 1) generate
etxc_pad : clkpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
arch => padclkarch,
hf => padhf,
filter => clk_padfilter)
port map (etx_clk, letx_clk);
erxc_pad : clkpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
arch => padclkarch,
hf => padhf,
filter => clk_padfilter)
port map (erx_clk, lerx_clk);
erxd_pad : inpadv
generic map(
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter,
strength => padstrength,
width => 8)
port map (erxd, lerxd);
erxdv_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter,
strength => padstrength)
port map (erx_dv, lerx_dv);
erxer_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter,
strength => padstrength)
port map (erx_er, lerx_er);
erxco_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter,
strength => padstrength)
port map (erx_col, lerx_col);
erxcr_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter,
strength => padstrength)
port map (erx_crs, lerx_crs);
etxd_pad : outpadv
generic map(
width => 8,
tech => padtech,
level => padlevel,
slew => padslew,
voltage => padvoltage,
strength => padstrength)
port map (etxd, letxd);
etxen_pad : outpad generic map (tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength)
port map (etx_en, letx_en);
etxer_pad : outpad generic map (tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength)
port map (etx_er, letx_er);
emdc_pad : outpad generic map (tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength)
port map (emdc, lemdc);
emdio_pad : iopad generic map (tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength)
port map (emdio, lemdioout, lemdioen, lemdioin);
emdint_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter,
strength => padstrength)
port map (emdint, lemdint);
end generate;
end;
| gpl-3.0 | 2406dea63dc5b814994d06f5f9ea16d6 | 0.480195 | 4.205674 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/leon3v3/libfpu.vhd | 1 | 4,767 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: libfpu
-- File: libfpu.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: LEON3 FPU interface types and components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.leon3.all;
library techmap;
use techmap.gencomp.all;
package libfpu is
type fp_rf_in_type is record
rd1addr : std_logic_vector(3 downto 0); -- read address 1
rd2addr : std_logic_vector(3 downto 0); -- read address 2
wraddr : std_logic_vector(3 downto 0); -- write address
wrdata : std_logic_vector(31 downto 0); -- write data
ren1 : std_ulogic; -- read 1 enable
ren2 : std_ulogic; -- read 2 enable
wren : std_ulogic; -- write enable
end record;
type fp_rf_out_type is record
data1 : std_logic_vector(31 downto 0); -- read data 1
data2 : std_logic_vector(31 downto 0); -- read data 2
end record;
type fpc_pipeline_control_type is record
pc : std_logic_vector(31 downto 0);
inst : std_logic_vector(31 downto 0);
cnt : std_logic_vector(1 downto 0);
trap : std_ulogic;
annul : std_ulogic;
pv : std_ulogic;
end record;
type fpc_debug_in_type is record
enable : std_ulogic;
write : std_ulogic;
fsr : std_ulogic; -- FSR access
addr : std_logic_vector(4 downto 0);
data : std_logic_vector(31 downto 0);
end record;
type fpc_debug_out_type is record
data : std_logic_vector(31 downto 0);
end record;
constant fpc_debug_none : fpc_debug_out_type := (data => X"00000000"
);
type fpc_in_type is record
flush : std_ulogic; -- pipeline flush
exack : std_ulogic; -- FP exception acknowledge
a_rs1 : std_logic_vector(4 downto 0);
d : fpc_pipeline_control_type;
a : fpc_pipeline_control_type;
e : fpc_pipeline_control_type;
m : fpc_pipeline_control_type;
x : fpc_pipeline_control_type;
lddata : std_logic_vector(31 downto 0); -- load data
dbg : fpc_debug_in_type; -- debug signals
end record;
type fpc_out_type is record
data : std_logic_vector(31 downto 0); -- store data
exc : std_logic; -- FP exception
cc : std_logic_vector(1 downto 0); -- FP condition codes
ccv : std_ulogic; -- FP condition codes valid
ldlock : std_logic; -- FP pipeline hold
holdn : std_ulogic;
dbg : fpc_debug_out_type; -- FP debug signals
end record;
constant fpc_out_none : fpc_out_type := (X"00000000", '0', "00", '1', '0', '1',
fpc_debug_none);
component grfpwxsh
generic (
tech : integer range 0 to NTECH := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
id : integer range 0 to 7 := 0;
scantest : integer := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi : in fpc_in_type;
cpo : out fpc_out_type;
fpui : out grfpu_in_type;
fpuo : in grfpu_out_type;
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0)
);
end component;
end;
| gpl-3.0 | debd603c60a0c34c2eddf87c5f547d01 | 0.543948 | 3.959302 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/misc/ahbstat.vhd | 1 | 4,363 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
library grlib;
library gaisler;
use ieee.std_logic_1164.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use gaisler.misc.all;
entity ahbstat is
generic(
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
nftslv : integer range 1 to NAHBSLV - 1 := 3);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
stati : in ahbstat_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end entity;
architecture rtl of ahbstat is
type reg_type is record
addr : std_logic_vector(31 downto 0); --failing address
hsize : std_logic_vector(2 downto 0); --ahb signals for failing op.
hmaster : std_logic_vector(3 downto 0);
hwrite : std_ulogic;
hresp : std_logic_vector(1 downto 0);
newerr : std_ulogic; --new error detected
cerror : std_ulogic; --correctable error detected
pirq : std_ulogic;
end record;
signal r, rin : reg_type;
constant VERSION : integer := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg (VENDOR_GAISLER, GAISLER_AHBSTAT, 0, VERSION, pirq),
1 => apb_iobar(paddr, pmask));
begin
comb : process(rst, ahbmi, ahbsi, stati, apbi, r) is
variable v : reg_type;
variable prdata : std_logic_vector(31 downto 0);
variable vpirq : std_logic_vector(NAHBIRQ - 1 downto 0);
variable ce : std_ulogic; --correctable error
begin
v := r; vpirq := (others => '0'); prdata := (others => '0'); v.pirq := '0';
ce := orv(stati.cerror(0 to nftslv-1));
case apbi.paddr(2) is
when '0' => --status values
prdata(2 downto 0) := r.hsize;
prdata(6 downto 3) := r.hmaster;
prdata(7) := r.hwrite;
prdata(8) := r.newerr;
prdata(9) := r.cerror;
when others => --failing address
prdata := r.addr;
end case;
--writes. data is written in setup cycle so that r.newerr is updated
--when hready = '1'
if (apbi.psel(pindex) and not apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(2) is
when '0' =>
v.newerr := apbi.pwdata(8);
v.cerror := apbi.pwdata(9);
when others => null;
end case;
end if;
v.hresp := ahbmi.hresp;
if (ahbsi.hready = '1') and (r.newerr = '0') then
if (r.hresp = HRESP_ERROR) or (ce = '1') then v.newerr := '1';
v.cerror := ce;
else
v.addr := ahbsi.haddr;
v.hsize := ahbsi.hsize;
v.hmaster := ahbsi.hmaster;
v.hwrite := ahbsi.hwrite;
end if;
end if;
--irq generation
v.pirq := v.newerr and not r.newerr;
vpirq(pirq) := r.pirq;
--reset
if rst = '0' then
v.newerr := '0'; v.cerror := '0';
end if;
rin <= v;
apbo.prdata <= prdata;
apbo.pirq <= vpirq;
end process;
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
regs : process(clk) is
begin
if rising_edge(clk) then r <= rin; end if;
end process;
-- boot message
-- pragma translate_off
bootmsg : report_version
generic map ("ahbstat" & tost(pindex) &
": AHB status unit rev " & tost(VERSION) &
", irq " & tost(pirq));
-- pragma translate_on
end architecture;
| gpl-3.0 | e2bfed5375c1c072f4fe1bf20aaff9de | 0.599358 | 3.524233 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/jtag/jtagtst.vhd | 1 | 30,199 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: sim
-- File: sim.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: JTAG debug link communication test
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
library grlib;
use grlib.stdlib.all;
use grlib.stdio.all;
use grlib.amba.all;
package jtagtst is
procedure clkj(tmsi, tdii : in std_ulogic; tdoo : out std_ulogic;
signal tck, tms, tdi : out std_ulogic;
signal tdo : in std_ulogic;
cp : in integer);
procedure shift(dr : in boolean; len : in integer;
din : in std_logic_vector; dout : out std_logic_vector;
signal tck, tms, tdi : out std_ulogic;
signal tdo : in std_ulogic;
cp : in integer);
procedure jtagcom(signal tdo : in std_ulogic;
signal tck, tms, tdi : out std_ulogic;
cp, start, addr : in integer;
-- cp - TCK clock period in ns
-- start - time in us when JTAG test
-- is started
-- addr - read/write operation destination address
haltcpu : in boolean;
justinit : in boolean := false; -- Only perform initialization
reread : in boolean := false; -- Re-read on slow AHB response
assertions : in boolean := false -- Allow output from assertions
);
subtype jword_type is std_logic_vector(31 downto 0);
type jdata_vector_type is array (integer range <>) of jword_type;
procedure jwritem(addr : in std_logic_vector;
data : in jdata_vector_type;
signal tck, tms, tdi : out std_ulogic;
signal tdo : in std_ulogic;
cp : in integer);
procedure jwritem(addr : in std_logic_vector;
data : in jdata_vector_type;
hsize : in std_logic_vector(1 downto 0);
signal tck, tms, tdi : out std_ulogic;
signal tdo : in std_ulogic;
cp : in integer);
procedure jreadm(addr : in std_logic_vector;
data : out jdata_vector_type;
signal tck, tms, tdi : out std_ulogic;
signal tdo : in std_ulogic;
cp : in integer;
reread : in boolean := false;
assertions : in boolean := false);
procedure jreadm(addr : in std_logic_vector;
hsize : in std_logic_vector(1 downto 0);
data : out jdata_vector_type;
signal tck, tms, tdi : out std_ulogic;
signal tdo : in std_ulogic;
cp : in integer;
reread : in boolean := false;
assertions : in boolean := false);
procedure jwrite(addr, data : in std_logic_vector;
signal tck, tms, tdi : out std_ulogic;
signal tdo : in std_ulogic;
cp : in integer);
procedure jwrite(addr, hsize, data : in std_logic_vector;
signal tck, tms, tdi : out std_ulogic;
signal tdo : in std_ulogic;
cp : in integer;
ainst : in integer := 2;
dinst : in integer := 3;
isize : in integer := 6);
procedure jread(addr : in std_logic_vector;
data : out std_logic_vector;
signal tck, tms, tdi : out std_ulogic;
signal tdo : in std_ulogic;
cp : in integer;
reread : in boolean := false;
assertions : in boolean := false);
procedure jread(addr : in std_logic_vector;
hsize : in std_logic_vector;
data : out std_logic_vector;
signal tck, tms, tdi : out std_ulogic;
signal tdo : in std_ulogic;
cp : in integer;
reread : in boolean := false;
assertions : in boolean := false);
procedure bscantest(signal tdo : in std_ulogic;
signal tck, tms, tdi : out std_ulogic;
cp: in integer;
inst_samp: integer := 5;
inst_extest: integer := 6;
inst_intest: integer := 7;
inst_mbist: integer := 11;
fastmode: boolean := false);
procedure bscansampre(signal tdo : in std_ulogic;
signal tck, tms, tdi : out std_ulogic;
nsigs: in integer;
sigpre: in std_logic_vector; sigsamp: out std_logic_vector;
cp: in integer; inst_samp: integer);
end;
package body jtagtst is
procedure clkj(tmsi, tdii : in std_ulogic; tdoo : out std_ulogic;
signal tck, tms, tdi : out std_ulogic;
signal tdo : in std_ulogic;
cp : in integer) is
begin
tdi <= tdii;
tck <= '0'; tms <= tmsi;
wait for 2 * cp * 1 ns;
tck <= '1'; tdoo := tdo;
wait for 2 * cp * 1 ns;
end;
procedure shift(dr : in boolean; len : in integer;
din : in std_logic_vector; dout : out std_logic_vector;
signal tck, tms, tdi : out std_ulogic;
signal tdo : in std_ulogic;
cp : in integer) is
variable dc : std_ulogic;
begin
clkj('0', '0', dc, tck, tms, tdi, tdo, cp);
clkj('1', '0', dc, tck, tms, tdi, tdo, cp);
if (not dr) then clkj('1', '0', dc, tck, tms, tdi, tdo, cp); end if;
clkj('0', '0', dc, tck, tms, tdi, tdo, cp); -- capture
clkj('0', '0', dc, tck, tms, tdi, tdo, cp); -- shift (state)
for i in 0 to len-2 loop
clkj('0', din(i), dout(i), tck, tms, tdi, tdo, cp);
end loop;
clkj('1', din(len-1), dout(len-1), tck, tms, tdi, tdo, cp); -- end shift, goto exit1
clkj('1', '0', dc, tck, tms, tdi, tdo, cp); -- update ir/dr
clkj('0', '0', dc, tck, tms, tdi, tdo, cp); -- run_test/idle
end;
procedure jwrite(addr, data : in std_logic_vector;
signal tck, tms, tdi : out std_ulogic;
signal tdo : in std_ulogic;
cp : in integer) is
variable tmp : std_logic_vector(32 downto 0);
variable tmp2 : std_logic_vector(34 downto 0);
variable dr : std_logic_vector(32 downto 0);
variable dr2 : std_logic_vector(34 downto 0);
variable hsize : std_logic_vector(1 downto 0);
begin
hsize := "10";
wait for 10 * cp * 1 ns;
shift(false, 6, B"010000", dr, tck, tms, tdi, tdo, cp); -- inst = addrreg
wait for 5 * cp * 1 ns;
tmp2 := '1' & hsize & addr;
shift(true, 35, tmp2, dr2, tck, tms, tdi, tdo, cp); -- write add reg
wait for 5 * cp * 1 ns;
shift(false, 6, B"110000", dr, tck, tms, tdi, tdo, cp); -- inst = datareg
wait for 5 * cp * 1 ns;
tmp := '0' & data;
shift(true, 33, tmp, dr, tck, tms, tdi, tdo, cp); -- write data reg
end;
procedure jwrite(addr, hsize, data : in std_logic_vector;
signal tck, tms, tdi : out std_ulogic;
signal tdo : in std_ulogic;
cp : in integer;
ainst : in integer := 2;
dinst : in integer := 3;
isize : in integer := 6) is
variable tmp : std_logic_vector(32 downto 0);
variable tmp2 : std_logic_vector(34 downto 0);
variable dr : std_logic_vector(32 downto 0);
variable dr2 : std_logic_vector(34 downto 0);
variable v_ainst : std_logic_vector(0 to 7);
variable v_dinst : std_logic_vector(0 to 7);
variable tmp3 : std_logic_vector(7 downto 0);
variable tmp4 : std_logic_vector(7 downto 0);
begin
tmp3 := conv_std_logic_vector(ainst,8);
tmp4 := conv_std_logic_vector(dinst,8);
for i in 0 to 7 loop
v_ainst(i) := tmp3(i);
v_dinst(i) := tmp4(i);
end loop;
wait for 10 * cp * 1 ns;
shift(false, isize, v_ainst(0 to isize-1), dr, tck, tms, tdi, tdo, cp); -- inst = addrreg
wait for 5 * cp * 1 ns;
tmp2 := '1' & hsize & addr;
shift(true, 35, tmp2, dr2, tck, tms, tdi, tdo, cp); -- write add reg
wait for 5 * cp * 1 ns;
shift(false, isize, v_dinst(0 to isize-1), dr, tck, tms, tdi, tdo, cp); -- inst = datareg
wait for 5 * cp * 1 ns;
tmp := '0' & data;
shift(true, 33, tmp, dr, tck, tms, tdi, tdo, cp); -- write data reg
end;
procedure jread(addr : in std_logic_vector;
data : out std_logic_vector;
signal tck, tms, tdi : out std_ulogic;
signal tdo : in std_ulogic;
cp : in integer;
reread : in boolean := false;
assertions : in boolean := false) is
variable tmp : std_logic_vector(32 downto 0);
variable tmp2 : std_logic_vector(34 downto 0);
variable dr : std_logic_vector(32 downto 0);
variable dr2 : std_logic_vector(34 downto 0);
variable hsize : std_logic_vector(1 downto 0);
begin
hsize := "10";
wait for 10 * cp * 1 ns;
shift(false, 6, B"010000", dr, tck, tms, tdi, tdo, cp); -- inst = addrreg
wait for 5 * cp * 1 ns;
tmp2 := '0' & hsize & addr;
shift(true, 35, tmp2, dr2, tck, tms, tdi, tdo, cp); -- write add reg
wait for 5 * cp * 1 ns;
shift(false, 6, B"110000", dr, tck, tms, tdi, tdo, cp); -- inst = datareg
wait for 5 * cp * 1 ns;
tmp := (others => '0'); --tmp(32) := '1';
shift(true, 33, tmp, dr, tck, tms, tdi, tdo, cp); -- read data reg
assert dr(32) = '1' or not assertions
report "JTAG READ: data read out before AHB access completed"
severity warning;
while dr(32) /= '1' and reread loop
assert not assertions report "Re-reading JTAG data register" severity note;
tmp := (others => '0');
shift(true, 33, tmp, dr, tck, tms, tdi, tdo, cp); -- read data reg
end loop;
data := dr(31 downto 0);
end;
procedure jread(addr : in std_logic_vector;
hsize : in std_logic_vector;
data : out std_logic_vector;
signal tck, tms, tdi : out std_ulogic;
signal tdo : in std_ulogic;
cp : in integer;
reread : in boolean := false;
assertions : in boolean := false) is
variable tmp : std_logic_vector(32 downto 0);
variable tmp2 : std_logic_vector(34 downto 0);
variable dr : std_logic_vector(32 downto 0);
variable dr2 : std_logic_vector(34 downto 0);
begin
wait for 10 * cp * 1 ns;
shift(false, 6, B"010000", dr, tck, tms, tdi, tdo, cp); -- inst = addrreg
wait for 5 * cp * 1 ns;
tmp2 := '0' & hsize & addr;
shift(true, 35, tmp2, dr2, tck, tms, tdi, tdo, cp); -- write add reg
wait for 5 * cp * 1 ns;
shift(false, 6, B"110000", dr, tck, tms, tdi, tdo, cp); -- inst = datareg
wait for 5 * cp * 1 ns;
tmp := (others => '0'); --tmp(32) := '1';
shift(true, 33, tmp, dr, tck, tms, tdi, tdo, cp); -- read data reg
assert dr(32) = '1' or not assertions
report "JTAG READ: data read out before AHB access completed"
severity warning;
while dr(32) /= '1' and reread loop
assert not assertions report "Re-reading JTAG data register" severity note;
wait for 5 * cp * 1 ns;
tmp := (others => '0');
shift(true, 33, tmp, dr, tck, tms, tdi, tdo, cp); -- read data reg
end loop;
data := dr(31 downto 0);
end;
procedure jwritem(addr : in std_logic_vector;
data : in jdata_vector_type;
signal tck, tms, tdi : out std_ulogic;
signal tdo : in std_ulogic;
cp : in integer) is
variable tmp : std_logic_vector(32 downto 0);
variable tmp2 : std_logic_vector(34 downto 0);
variable dr : std_logic_vector(32 downto 0);
variable dr2 : std_logic_vector(34 downto 0);
variable hsize : std_logic_vector(1 downto 0);
begin
hsize := "10";
wait for 10 * cp * 1 ns;
shift(false, 6, B"010000", dr, tck, tms, tdi, tdo, cp); -- inst = addrreg
wait for 5 * cp * 1 ns;
tmp2 := '1' & hsize & addr;
shift(true, 35, tmp2, dr2, tck, tms, tdi, tdo, cp); -- write add reg
wait for 5 * cp * 1 ns;
shift(false, 6, B"110000", dr, tck, tms, tdi, tdo, cp); -- inst = datareg
wait for 5 * cp * 1 ns;
for i in data'left to data'right-1 loop
tmp := '1' & data(i);
shift(true, 33, tmp, dr, tck, tms, tdi, tdo, cp); -- write data reg
end loop;
tmp := '0' & data(data'right);
shift(true, 33, tmp, dr, tck, tms, tdi, tdo, cp); -- write data reg
end;
procedure jwritem(addr : in std_logic_vector;
data : in jdata_vector_type;
hsize : in std_logic_vector(1 downto 0);
signal tck, tms, tdi : out std_ulogic;
signal tdo : in std_ulogic;
cp : in integer) is
variable tmp : std_logic_vector(32 downto 0);
variable tmp2 : std_logic_vector(34 downto 0);
variable dr : std_logic_vector(32 downto 0);
variable dr2 : std_logic_vector(34 downto 0);
begin
wait for 10 * cp * 1 ns;
shift(false, 6, B"010000", dr, tck, tms, tdi, tdo, cp); -- inst = addrreg
wait for 5 * cp * 1 ns;
tmp2 := '1' & hsize & addr;
shift(true, 35, tmp2, dr2, tck, tms, tdi, tdo, cp); -- write add reg
wait for 5 * cp * 1 ns;
shift(false, 6, B"110000", dr, tck, tms, tdi, tdo, cp); -- inst = datareg
wait for 5 * cp * 1 ns;
for i in data'left to data'right-1 loop
tmp := '1' & data(i);
shift(true, 33, tmp, dr, tck, tms, tdi, tdo, cp); -- write data reg
end loop;
tmp := '0' & data(data'right);
shift(true, 33, tmp, dr, tck, tms, tdi, tdo, cp); -- write data reg
end;
procedure jreadm(addr : in std_logic_vector;
data : out jdata_vector_type;
signal tck, tms, tdi : out std_ulogic;
signal tdo : in std_ulogic;
cp : in integer;
reread : in boolean := false;
assertions : in boolean := false) is
variable tmp : std_logic_vector(32 downto 0);
variable tmp2 : std_logic_vector(34 downto 0);
variable dr : std_logic_vector(32 downto 0);
variable dr2 : std_logic_vector(34 downto 0);
variable hsize : std_logic_vector(1 downto 0);
begin
hsize := "10";
wait for 10 * cp * 1 ns;
shift(false, 6, B"010000", dr, tck, tms, tdi, tdo, cp); -- inst = addrreg
wait for 5 * cp * 1 ns;
tmp2 := '0' & hsize & addr;
shift(true, 35, tmp2, dr2, tck, tms, tdi, tdo, cp); -- write add reg
wait for 5 * cp * 1 ns;
shift(false, 6, B"110000", dr, tck, tms, tdi, tdo, cp); -- inst = datareg
wait for 5 * cp * 1 ns;
for i in data'left to data'right-1 loop
tmp := (others => '0'); tmp(32) := '1';
shift(true, 33, tmp, dr, tck, tms, tdi, tdo, cp); -- read data reg
assert dr(32) = '1' or not assertions
report "JTAG READ: data read out before AHB access completed"
severity warning;
while dr(32) /= '1' and reread loop
assert not assertions report "Re-reading JTAG data register" severity note;
tmp := (others => '0'); tmp(32) := '1';
shift(true, 33, tmp, dr, tck, tms, tdi, tdo, cp); -- read data reg
end loop;
data(i) := dr(31 downto 0);
end loop;
tmp := (others => '0');
shift(true, 33, tmp, dr, tck, tms, tdi, tdo, cp); -- read data reg
assert dr(32) = '1' or not assertions
report "JTAG READ: data read out before AHB access completed"
severity warning;
while dr(32) /= '1' and reread loop
assert not assertions report "Re-reading JTAG data register" severity note;
tmp := (others => '0');
shift(true, 33, tmp, dr, tck, tms, tdi, tdo, cp); -- read data reg
end loop;
data(data'right) := dr(31 downto 0);
end;
procedure jreadm(addr : in std_logic_vector;
hsize : in std_logic_vector(1 downto 0);
data : out jdata_vector_type;
signal tck, tms, tdi : out std_ulogic;
signal tdo : in std_ulogic;
cp : in integer;
reread : in boolean := false;
assertions : in boolean := false) is
variable tmp : std_logic_vector(32 downto 0);
variable tmp2 : std_logic_vector(34 downto 0);
variable dr : std_logic_vector(32 downto 0);
variable dr2 : std_logic_vector(34 downto 0);
begin
wait for 10 * cp * 1 ns;
shift(false, 6, B"010000", dr, tck, tms, tdi, tdo, cp); -- inst = addrreg
wait for 5 * cp * 1 ns;
tmp2 := '0' & hsize & addr;
shift(true, 35, tmp2, dr2, tck, tms, tdi, tdo, cp); -- write add reg
wait for 5 * cp * 1 ns;
shift(false, 6, B"110000", dr, tck, tms, tdi, tdo, cp); -- inst = datareg
wait for 5 * cp * 1 ns;
for i in data'left to data'right-1 loop
tmp := (others => '0'); tmp(32) := '1';
shift(true, 33, tmp, dr, tck, tms, tdi, tdo, cp); -- read data reg
assert dr(32) = '1' or not assertions
report "JTAG READ: data read out before AHB access completed"
severity warning;
while dr(32) /= '1' and reread loop
assert not assertions report "Re-reading JTAG data register" severity note;
tmp := (others => '0'); tmp(32) := '1';
shift(true, 33, tmp, dr, tck, tms, tdi, tdo, cp); -- read data reg
end loop;
data(i) := dr(31 downto 0);
end loop;
tmp := (others => '0');
shift(true, 33, tmp, dr, tck, tms, tdi, tdo, cp); -- read data reg
assert dr(32) = '1' or not assertions
report "JTAG READ: data read out before AHB access completed"
severity warning;
while dr(32) /= '1' and reread loop
assert not assertions report "Re-reading JTAG data register" severity note;
tmp := (others => '0');
shift(true, 33, tmp, dr, tck, tms, tdi, tdo, cp); -- read data reg
end loop;
data(data'right) := dr(31 downto 0);
end;
procedure jtagcom(signal tdo : in std_ulogic;
signal tck, tms, tdi : out std_ulogic;
cp, start, addr : in integer;
haltcpu : in boolean;
justinit : in boolean := false;
reread : in boolean := false;
assertions : in boolean := false) is
variable dc : std_ulogic;
variable dr : std_logic_vector(32 downto 0);
variable tmp : std_logic_vector(32 downto 0);
variable data : std_logic_vector(31 downto 0);
variable datav : jdata_vector_type(0 to 3);
begin
tck <= '0'; tms <= '0'; tdi <= '0';
wait for start * 1 us;
print("AHB JTAG TEST");
for i in 1 to 5 loop -- reset
clkj('1', '0', dc, tck, tms, tdi, tdo, cp);
end loop;
clkj('0', '0', dc, tck, tms, tdi, tdo, cp);
--read IDCODE
wait for 10 * cp * 1 ns;
shift(true, 32, conv_std_logic_vector(0, 32), dr, tck, tms, tdi, tdo, cp);
print("JTAG TAP ID:" & tost(dr(31 downto 0)));
wait for 10 * cp * 1 ns;
shift(false, 6, conv_std_logic_vector(63, 6), dr, tck, tms, tdi, tdo, cp); -- BYPASS
--shift data through BYPASS reg
shift(true, 32, conv_std_logic_vector(16#AAAA#, 16) & conv_std_logic_vector(16#AAAA#, 16), dr,
tck, tms, tdi, tdo, cp);
-- put CPUs in debug mode
if haltcpu then
jwrite(X"90000000", X"00000004", tck, tms, tdi, tdo, cp);
jwrite(X"90000020", X"0000FFFF", tck, tms, tdi, tdo, cp);
print("JTAG: Putting CPU in debug mode");
end if;
if false then
jwrite(X"90000000", X"FFFFFFFF", tck, tms, tdi, tdo, cp);
jread (X"90000000", data, tck, tms, tdi, tdo, cp, reread, assertions);
print("JTAG WRITE " & tost(X"90000000") & ":" & tost(X"FFFFFFFF"));
print("JTAG READ " & tost(X"90000000") & ":" & tost(data));
jwrite(X"90100034", X"ABCD1234", tck, tms, tdi, tdo, cp);
jread (X"90100034", data, tck, tms, tdi, tdo, cp, reread, assertions);
print("JTAG WRITE " & tost(X"90100034") & ":" & tost(X"ABCD1234"));
print("JTAG READ " & tost(X"90100034") & ":" & tost(data));
jwrite(X"90200058", X"ABCDEF01", tck, tms, tdi, tdo, cp);
jread (X"90200058", data, tck, tms, tdi, tdo, cp, reread, assertions);
print("JTAG WRITE " & tost(X"90200058") & ":" & tost(X"ABCDEF01"));
print("JTAG READ " & tost(X"90200058") & ":" & tost(data));
jwrite(X"90300000", X"ABCD1234", tck, tms, tdi, tdo, cp);
jread (X"90300000", data, tck, tms, tdi, tdo, cp, reread, assertions);
print("JTAG WRITE " & tost(X"90300000") & ":" & tost(X"ABCD1234"));
print("JTAG READ " & tost(X"90300000") & ":" & tost(data));
jwrite(X"90400000", X"ABCD1234", tck, tms, tdi, tdo, cp);
jread (X"90400000", data, tck, tms, tdi, tdo, cp, reread, assertions);
print("JTAG WRITE " & tost(X"90400000") & ":" & tost(X"ABCD1234"));
print("JTAG READ " & tost(X"90400000") & ":" & tost(data));
jwrite(X"90400024", X"0000000C", tck, tms, tdi, tdo, cp);
jwrite(X"90700100", X"ABCD1234", tck, tms, tdi, tdo, cp);
jread (X"90700100", data, tck, tms, tdi, tdo, cp, reread, assertions);
print("JTAG WRITE ITAG :" & tost(X"00000100") & ":" & tost(X"ABCD1234"));
print("JTAG READ ITAG :" & tost(X"00000100") & ":" & tost(data));
jwrite(X"90400024", X"0000000D", tck, tms, tdi, tdo, cp);
jwrite(X"90700100", X"ABCD1234", tck, tms, tdi, tdo, cp);
jread (X"90700100", data, tck, tms, tdi, tdo, cp, reread, assertions);
print("JTAG WRITE IDATA:" & tost(X"00000100") & ":" & tost(X"ABCD1234"));
print("JTAG READ IDATA:" & tost(X"00000100") & ":" & tost(data));
jwrite(X"90400024", X"0000000E", tck, tms, tdi, tdo, cp);
jwrite(X"90700100", X"ABCD1234", tck, tms, tdi, tdo, cp);
jread (X"90700100", data, tck, tms, tdi, tdo, cp, reread, assertions);
print("JTAG WRITE DTAG :" & tost(X"00000100") & ":" & tost(X"ABCD1234"));
print("JTAG READ DTAG :" & tost(X"00000100") & ":" & tost(data));
jwrite(X"90400024", X"0000000F", tck, tms, tdi, tdo, cp);
jwrite(X"90700100", X"ABCD1234", tck, tms, tdi, tdo, cp);
jread (X"90700100", data, tck, tms, tdi, tdo, cp, reread, assertions);
print("JTAG WRITE DDATA:" & tost(X"00000100") & ":" & tost(X"ABCD1234"));
print("JTAG READ DDATA:" & tost(X"00000100") & ":" & tost(data));
end if;
if not justinit then
--jwritem(addr, (X"00000010", X"00000010", X"00000010", X"00000010"), tck, tms, tdi, tdo, cp);
datav(0) := X"00000010"; datav(1) := X"00000011"; datav(2) := X"00000012"; datav(3) := X"00000013";
jwritem(conv_std_logic_vector(addr, 32), datav, tck, tms, tdi, tdo, cp);
print("JTAG WRITE " & tost(conv_std_logic_vector(addr,32)) & ":" & tost(X"00000010") & " " & tost(X"00000011") & " " & tost(X"00000012") & " " & tost(X"00000013"));
datav := (others => (others => '0'));
jreadm(conv_std_logic_vector(addr, 32), datav, tck, tms, tdi, tdo, cp, reread, assertions);
print("JTAG READ " & tost(conv_std_logic_vector(addr,32)) & ":" & tost(datav(0)) & " " & tost(datav(1)) & " " & tost(datav(2)) & " " & tost(datav(3)));
-- Not affected by 'assertions' parameter
assert (datav(0) = X"00000010") and (datav(1) = X"00000011") and (datav(2) = X"00000012") and (datav(3) = X"00000013")
report "JTAG test failed" severity failure;
print("JTAG test passed");
end if;
end procedure;
-- Sample/Preload
procedure bscansampre(signal tdo : in std_ulogic;
signal tck, tms, tdi : out std_ulogic;
nsigs: in integer;
sigpre: in std_logic_vector; sigsamp: out std_logic_vector;
cp: in integer; inst_samp: integer) is
variable tmp: std_logic_vector(5 downto 0);
begin
shift(false,6, conv_std_logic_vector(inst_samp,6), tmp, tck,tms,tdi,tdo, cp);
shift(true, nsigs, sigpre, sigsamp, tck,tms,tdi,tdo, cp);
end procedure;
-- Boundary scan test
procedure bscantest(signal tdo : in std_ulogic;
signal tck, tms, tdi : out std_ulogic;
cp: in integer;
inst_samp: integer := 5;
inst_extest: integer := 6;
inst_intest: integer := 7;
inst_mbist: integer := 11;
fastmode: boolean := false) is
variable tmpin,tmpout: std_logic_vector(1999 downto 0);
variable i,bslen: integer;
variable dc: std_logic;
variable tmp6: std_logic_vector(5 downto 0);
variable tmp1: std_logic_vector(0 downto 0);
begin
print("[bscan] Boundary scan test starting...");
for i in 1 to 5 loop -- reset
clkj('1', '0', dc, tck, tms, tdi, tdo, cp);
end loop;
clkj('0', '0', dc, tck, tms, tdi, tdo, cp);
-- Probe length of boundary scan chain
tmpin := (others => '0');
tmpin(tmpin'length/2) := '1';
bscansampre(tdo,tck,tms,tdi,tmpin'length,tmpin,tmpout,cp,inst_samp);
i := tmpout'length/2;
for x in tmpout'length/2 to tmpout'high loop
if tmpout(x)='1' then
-- print("tmpout(" & tost(x) & ") set");
i := x;
end if;
end loop;
bslen := i-tmpout'length/2;
if bslen=0 then
print("[bscan] Scan chain not present, skipping test");
return;
end if;
print("[bscan] Detected boundary scan chain length: " & tost(bslen));
if fastmode then
print("[bscan] Setting EXTEST with all chain regs=0");
shift(false,6, conv_std_logic_vector(inst_extest,6), tmp6, tck,tms,tdi,tdo, cp); -- extest
print("[bscan] In EXTEST, changing all chain regs to 1");
tmpin := (others => '1');
shift(true, bslen, tmpin(bslen-1 downto 0), tmpout(bslen-1 downto 0), tck,tms,tdi,tdo, cp);
print("[bscan] Setting INTEST with all chain regs=1");
shift(false,6, conv_std_logic_vector(inst_intest,6), tmp6, tck,tms,tdi,tdo, cp); -- intest
print("[bscan] In INTEST, changing all chain regs to 0");
tmpin := (others => '0');
shift(true, bslen, tmpin(bslen-1 downto 0), tmpout(bslen-1 downto 0), tck,tms,tdi,tdo, cp);
else
print("[bscan] Looping over outputs...");
shift(false,6, conv_std_logic_vector(inst_extest,6), tmp6, tck,tms,tdi,tdo, cp); -- extest
for x in 0 to bslen loop
tmpin :=(others => '0');
tmpin(x) := '1';
shift(true, bslen, tmpin(bslen-1 downto 0), tmpout(bslen-1 downto 0), tck,tms,tdi,tdo, cp);
end loop;
print("[bscan] Looping over inputs...");
shift(false,6, conv_std_logic_vector(inst_intest,6), tmp6, tck,tms,tdi,tdo, cp); -- intest
for x in 0 to bslen loop
tmpin :=(others => '0');
tmpin(x) := '1';
shift(true, bslen, tmpin(bslen-1 downto 0), tmpout(bslen-1 downto 0), tck,tms,tdi,tdo, cp);
end loop;
end if;
if inst_mbist >= 0 then
print("[bscan] Shifting in MBIST command");
shift(false,6, conv_std_logic_vector(inst_mbist,6), tmp6, tck,tms,tdi,tdo, cp); -- MBIST command
end if;
print("[bscan] Test done");
end procedure;
end;
-- pragma translate_on
| gpl-3.0 | 3697b58dec5120423ef0058d07b078d3 | 0.520448 | 3.663593 | false | false | false | false |
yishinli/emc2 | src/hal/drivers/mesa-hostmot2/firmware/src/i43usbhm2.vhd | 1 | 21,634 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
--
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
-- http://www.mesanet.com
--
-- This program is is licensed under a disjunctive dual license giving you
-- the choice of one of the two following sets of free software/open source
-- licensing terms:
--
-- * GNU General Public License (GPL), version 2.0 or later
-- * 3-clause BSD License
--
--
-- The GNU GPL License:
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- The 3-clause BSD License:
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- * Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- * Neither the name of Mesa Electronics nor the names of its
-- contributors may be used to endorse or promote products
-- derived from this software without specific prior written
-- permission.
--
--
-- Disclaimer:
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
use work.IDROMParms.all;
use work.NumberOfModules.all;
use work.MaxPinsPerModule.all;
entity i43usbhm2 is
generic
(
-- Note: all pinout/module count information is derived from
-- the PinDesc and ModuleID records in IDParms.vhd and passed through
-- to the lower levels. That is, these next two assignments determine
-- the modules contained and the pinout of a FPGA firmware configuration
ThePinDesc: PinDescType := PinDesc_SVST4_12NA;
TheModuleID: ModuleIDType := ModuleID_SVST4_12NA;
PWMRefWidth: integer := 13; -- PWM resolution is PWMRefWidth-1 bits
IDROMType: integer := 2;
SepClocks: boolean := true;
OneWS: boolean := true;
UseStepGenPrescaler : boolean := false;
UseIRQLogic: boolean := true;
UseWatchDog: boolean := true;
OffsetToModules: integer := 64;
OffsetToPinDesc: integer := 512;
ClockHigh: integer := ClockHigh43U;
ClockLow: integer := ClockLow43U;
BoardNameLow : std_Logic_Vector(31 downto 0) := BoardNameMESA;
BoardNameHigh : std_Logic_Vector(31 downto 0) := BoardName7I43;
FPGASize: integer := 400;
FPGAPins: integer := 144;
IOPorts: integer := 2;
IOWidth: integer := 48;
PortWidth: integer := 24;
BusWidth: integer := 32;
AddrWidth: integer := 16;
InstStride0: integer := 4;
InstStride1: integer := 16;
RegStride0: integer := 256;
RegStride1: integer := 4;
LEDCount: integer := 8
);
Port ( CLK : in std_logic;
LEDS : out std_logic_vector(7 downto 0);
IOBITS : inout std_logic_vector(47 downto 0);
DATABUS : inout std_logic_vector(7 downto 0);
USB_WRITE : out std_logic;
USB_RD :out std_logic;
USB_TXE : in std_logic;
USB_RXF : in std_logic;
RECONFIG : out std_logic;
PARACONFIG : out std_logic;
SPICLK : out std_logic;
SPIIN : in std_logic;
SPIOUT : out std_logic;
SPICS : out std_logic
);
end i43usbhm2;
architecture Behavioral of i43usbhm2 is
-- GPIO interface signals
signal ReconfigSel : std_logic;
signal ReConfigreg : std_logic := '0';
signal LoadSPIReg : std_logic;
signal ReadSPIReg : std_logic;
signal LoadSPICS : std_logic;
signal ReadSPICS : std_logic;
signal LoadUSBDataReg : std_logic;
signal ReadUSBData : std_logic;
signal LoadUSBControlReg : std_logic;
signal ReadUSBStatus : std_logic;
signal USBDataReg : std_logic_vector(7 downto 0);
signal USBContReg : std_logic_vector(2 downto 0) := "011";
alias USB_RdReg : std_logic is USBContReg(0);
alias USB_WriteReg : std_logic is USBContReg(1);
alias USB_TSEn : std_logic is USBContReg(2);
signal iabus : std_logic_vector(9 downto 0); -- program address bus
signal idbus : std_logic_vector(15 downto 0); -- program data bus
signal mradd : std_logic_vector(11 downto 0); -- memory read address
signal ioradd : std_logic_vector(11 downto 0); -- I/O read address
signal mwadd : std_logic_vector(11 downto 0); -- memory write address
signal mibus : std_logic_vector(7 downto 0); -- memory data in bus
signal mobus : std_logic_vector(7 downto 0); -- memory data out bus
signal mwrite : std_logic; -- memory write signal
signal mread : std_logic; -- memory read signal
signal pagedmradd : std_logic_vector(10 downto 0);
signal pagedmwadd : std_logic_vector(10 downto 0);
signal pagedmwrite : std_logic;
signal mibus_ram : std_logic_vector(7 downto 0); -- memory data in bus RAM
signal mibus_io : std_logic_vector(7 downto 0); -- memory data in bus IO
alias wiosel : std_logic is mwadd(10);
alias riosel : std_logic is ioradd(10);
signal WriteLEDs : std_logic;
Signal LocalLEDs : std_logic_vector(7 downto 0);
signal ReadExtData : std_logic;
signal WriteExtData : std_logic;
signal ReadExtAddLow : std_logic;
signal WriteExtAddLow : std_logic;
signal ReadExtAddHigh : std_logic;
signal WriteExtAddHigh : std_logic;
signal StartExtRead : std_logic;
signal StartExtReadRQ : std_logic;
signal StartExtReadDel : std_logic_vector(1 downto 0);
signal StartExtWrite : std_logic;
signal StartExtWriteRQ : std_logic;
signal StartExtWriteDel : std_logic_vector(1 downto 0);
signal ReadEIOCookie : std_logic;
signal HM2ReadBuffer0 : std_logic_vector(31 downto 0);
signal HM2WriteBuffer0 : std_logic_vector(31 downto 0);
signal HM2ReadBuffer1 : std_logic_vector(31 downto 0);
signal HM2WriteBuffer1 : std_logic_vector(31 downto 0);
signal Write32 : std_logic;
signal Read32 : std_logic;
signal ExtAddress0: std_logic_vector(15 downto 0);
signal ExtAddress1: std_logic_vector(15 downto 0);
signal HM2obus : std_logic_vector(31 downto 0);
signal wseladd: std_logic_vector(7 downto 0);
signal rseladd: std_logic_vector(7 downto 0);
signal clk0fx : std_logic;
signal clk0 : std_logic;
signal procclk : std_logic;
signal clk1fx : std_logic;
signal clk1 : std_logic;
signal hm2fastclock : std_logic;
signal clk2fx : std_logic;
signal clk2 : std_logic;
signal hm2interfaceclock : std_logic;
constant EIOCookie: std_logic_vector(7 downto 0) := x"EE";
-- Extract the number of modules of each type from the ModuleID
constant StepGens: integer := NumberOfModules(TheModuleID,StepGenTag);
constant QCounters: integer := NumberOfModules(TheModuleID,QCountTag);
constant MuxedQCounters: integer := NumberOfModules(TheModuleID,MuxedQCountTag);
constant PWMGens : integer := NumberOfModules(TheModuleID,PWMTag);
constant SPIs: integer := NumberOfModules(TheModuleID,SPITag);
constant BSPIs: integer := NumberOfModules(TheModuleID,BSPITag);
constant SSIs: integer := NumberOfModules(TheModuleID,SSITag);
constant UARTs: integer := NumberOfModules(TheModuleID,UARTRTag);
-- extract the needed Stepgen table width from the max pin# used with a stepgen tag
constant StepGenTableWidth: integer := MaxPinsPerModule(ThePinDesc,StepGenTag);
-- extract how many BSPI CS pins are needed from the max pin# used with a BSPI tag skipping the first 4
constant BSPICSWidth: integer := MaxPinsPerModule(ThePinDesc,BSPITag)-4;
begin
ahostmot2: entity HostMot2
generic map (
thepindesc => ThePinDesc,
themoduleid => TheModuleID,
stepgens => StepGens,
qcounters => QCounters,
muxedqcounters => MuxedQCounters,
pwmgens => PWMGens,
spis => SPIs,
bspis => BSPIs,
ssis => SSIs,
uarts => UARTs,
pwmrefwidth => PWMRefWidth,
stepgentablewidth => StepGenTableWidth,
bspicswidth => BSPICSWidth,
idromtype => IDROMType,
sepclocks => SepClocks,
onews => OneWS,
usestepgenprescaler => UseStepGenPrescaler,
useirqlogic => UseIRQLogic,
usewatchdog => UseWatchDog,
offsettomodules => OffsetToModules,
offsettopindesc => OffsetToPinDesc,
clockhigh => ClockHigh,
clocklow => ClockLow,
boardnamelow => BoardNameLow,
boardnamehigh => BoardNameHigh,
fpgasize => FPGASize,
fpgapins => FPGAPins,
ioports => IOPorts,
iowidth => IOWidth,
portwidth => PortWidth,
buswidth => BusWidth,
addrwidth => AddrWidth,
inststride0 => InstStride0,
inststride1 => InstStride1,
regstride0 => RegStride0,
regstride1 => RegStride1,
ledcount => LEDCount )
port map (
ibus => HM2WriteBuffer1,
obus => HM2obus,
addr => ExtAddress1(15 downto 2),
read => Read32,
write => Write32,
clklow => hm2interfaceclock,
clkhigh => hm2fastclock,
-- int => INT,
iobits => IOBITS,
leds => LEDS
);
ClockMult0 : DCM
generic map (
CLKDV_DIVIDE => 2.0,
CLKFX_DIVIDE => 2,
CLKFX_MULTIPLY =>3, -- 3/2 FOR 75 MHz, 4/2 for 100 MHz, 8/5 for 80MHz, 7/4 for 87.5MHz
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 20.0,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => X"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map (
CLK0 => clk0, --
CLKFB => clk0, -- DCM clock feedback
CLKFX => clk0fx,
CLKIN => CLK, -- Clock input (from IBUFG, BUFG or DCM)
PSCLK => '0', -- Dynamic phase adjust clock input
PSEN => '0', -- Dynamic phase adjust enable input
PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
RST => '0' -- DCM asynchronous reset input
);
BUFG0_inst : BUFG
port map (
O => procclk, -- Clock buffer output
I => clk0fx -- Clock buffer input
);
-- End of DCM_inst instantiation
ClockMult1 : DCM
generic map (
CLKDV_DIVIDE => 2.0,
CLKFX_DIVIDE => 2,
CLKFX_MULTIPLY =>4, -- 3/2 *50 FOR 75 MHz, 4/2 for 100 MHz, 8/5 for 80MHz, 7/4 for 87.5MHz
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 20.0,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => X"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map (
CLK0 => clk1, --
CLKFB => clk1, -- DCM clock feedback
CLKFX => clk1fx,
CLKIN => CLK, -- Clock input (from IBUFG, BUFG or DCM)
PSCLK => '0', -- Dynamic phase adjust clock input
PSEN => '0', -- Dynamic phase adjust enable input
PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
RST => '0' -- DCM asynchronous reset input
);
BUFG1_inst : BUFG
port map (
O => hm2fastclock, -- Clock buffer output
I => clk1fx -- Clock buffer input
);
-- End of DCM_inst instantiation
ClockMult2 : DCM
generic map (
CLKDV_DIVIDE => 2.0,
CLKFX_DIVIDE => 3,
CLKFX_MULTIPLY =>2, -- 2/3 for 33 MHz 3/2 *50 FOR 75 MHz, 4/2 for 100 MHz, 8/5 for 80MHz, 7/4 for 87.5MHz
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 20.0,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => X"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map (
CLK0 => clk2, --
CLKFB => clk2, -- DCM clock feedback
CLKFX => clk2fx,
CLKIN => CLK, -- Clock input (from IBUFG, BUFG or DCM)
PSCLK => '0', -- Dynamic phase adjust clock input
PSEN => '0', -- Dynamic phase adjust enable input
PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
RST => '0' -- DCM asynchronous reset input
);
BUFG2_inst : BUFG
port map (
O => hm2interfaceclock, -- Clock buffer output
I => clk2fx -- Clock buffer input
);
-- End of DCM_inst instantiation
asimplspi: entity simplespi8
generic map
(
buswidth => 8,
div => 2,
bits => 8
)
port map
(
clk => procclk,
ibus => mobus,
obus => mibus_io,
loaddata => LoadSPIReg,
readdata => ReadSPIReg,
loadcs => LoadSPICS,
readcs => ReadSPICS,
spiclk => SPIClk,
spiin => SPIIn,
spiout => SPIOut,
spics =>SPICS
);
processor: entity DumbAss8
port map (
clk => procclk,
reset => '0',
iabus => iabus, -- program address bus
idbus => idbus, -- program data bus
mradd => mradd, -- memory read address
mwadd => mwadd, -- memory write address
mibus => mibus, -- memory data in bus
mobus => mobus, -- memory data out bus
mwrite => mwrite, -- memory write signal
mread => mread -- memory read signal
-- carryflg => -- carry flag
);
programROM : entity usbrom
port map(
addr => iabus,
clk => procclk,
din => x"0000",
dout => idbus,
we => '0'
);
DataRam : entity usbram
port map(
addra => pagedmwadd,
addrb => pagedmradd,
clk => procclk,
dina => mobus,
-- douta =>
doutb => mibus_ram,
wea => pagedmwrite
);
MiscProcFixes : process (procclk) -- need to match BlockRAM address pipeline register for I/O
begin -- and map memory/IO so 1K IO,1K memory, 1K IO, 1K memory
if rising_edge(procclk) then
ioradd <= mradd;
end if;
pagedmradd <= mradd(11) & mradd(9 downto 0);
pagedmwadd <= mwadd(11) & mwadd(9 downto 0);
pagedmwrite <= mwrite and mwadd(10);
end process;
ram_iomux : process (ioradd(10),mibus_ram,mibus_io)
begin
if ioradd(10) = '1' then
mibus <= mibus_ram;
else
mibus <= mibus_io;
end if;
end process;
iodecode: process(ioradd,mwadd,mwrite)
begin
rseladd <= ioradd(7 downto 0);
wseladd <= mwadd(7 downto 0);
if rseladd (7 downto 3) = "01100" and riosel = '0' then -- 0x60 through 0x67
ReadExtData <= '1';
else
ReadExtData <= '0';
end if;
if wseladd (7 downto 3) = "01100" and wiosel = '0' and mwrite = '1' then -- 0x60 through 0x67
WriteExtData <= '1';
else
WriteExtData <= '0';
end if;
if rseladd = x"68" and riosel = '0' then
ReadExtAddLow <= '1';
else
ReadExtAddLow <= '0';
end if;
if wseladd = x"68" and wiosel = '0' and mwrite= '1' then
WriteExtAddLow <= '1';
else
WriteExtAddLow <= '0';
end if;
if rseladd = x"69" and riosel = '0' then
ReadExtAddHigh <= '1';
else
ReadExtAddHigh <= '0';
end if;
if wseladd = x"69" and wiosel = '0' and mwrite= '1' then
WriteExtAddHigh <= '1';
else
WriteExtAddHigh <= '0';
end if;
if wseladd = x"6D" and wiosel = '0' and mwrite = '1' then
StartExtRead <= '1';
else
StartExtRead <= '0';
end if;
if wseladd = x"6E" and wiosel = '0' and mwrite= '1' then
StartExtWrite <= '1';
else
StartExtWrite <= '0';
end if;
if rseladd = x"6F" and riosel = '0' then
ReadEIOCookie <= '1';
else
ReadEIOCookie <= '0';
end if;
if wseladd = x"7A" and wiosel = '0' and mwrite = '1'then
WriteLEDs <= '1';
else
WriteLEDs <= '0';
end if;
if wseladd = x"7B" and wiosel = '0' and mwrite = '1'then
LoadUSBControlReg <= '1';
else
LoadUSBControlReg <= '0';
end if;
if rseladd = x"7B" and riosel = '0' then
ReadUSBStatus <= '1';
else
ReadUSBStatus <= '0';
end if;
if wseladd = x"7C" and wiosel = '0' and mwrite = '1'then
LoadUSBDataReg <= '1';
else
LoadUSBDataReg <= '0';
end if;
if rseladd = x"7C" and riosel = '0' then
ReadUSBData <= '1';
else
ReadUSBData <= '0';
end if;
if ExtAddress0 = x"007D" and WriteExtData = '1' and wiosel = '0' and mwrite = '1' then
LoadSPICS <= '1';
else
LoadSPICS <= '0';
end if;
if ExtAddress0 = x"007D" and ReadExtData = '1' and riosel = '0' then
ReadSPICS <= '1';
else
ReadSPICS <= '0';
end if;
if ExtAddress0 = x"007E" and WriteExtData = '1' and wiosel = '0' and mwrite = '1'then
LoadSPIReg <= '1';
else
LoadSPIReg <= '0';
end if;
if ExtAddress0 = x"007E" and ReadExtData = '1' and riosel = '0' then
ReadSPIReg <= '1';
else
ReadSPIReg <= '0';
end if;
if ExtAddress0 = x"7F7F" and WriteExtData = '1' and wiosel = '0' and mwrite = '1' then
ReconfigSel <= '1';
else
ReconfigSel <= '0';
end if;
end process iodecode;
doreconfig: process (procclk,ReConfigreg)
begin
if rising_edge(procclk) then
if ReconfigSel = '1' then
if mobus = x"5A" then
ReConfigreg <= '1';
end if;
end if;
end if;
RECONFIG <= not ReConfigreg;
end process doreconfig;
HM2InterfaceShim: process (procclk,hm2interfaceclock)
begin
if rising_edge(procclk) then
if WriteLEDS = '1' then
LocalLEDs <= mobus;
end if;
HM2ReadBuffer1 <= HM2ReadBuffer0;
if WriteExtData = '1' then
case wseladd(1 downto 0) is
when "00" => HM2WriteBuffer0( 7 downto 0) <= mobus;
when "01" => HM2WriteBuffer0(15 downto 8) <= mobus;
when "10" => HM2WriteBuffer0(23 downto 16) <= mobus;
when "11" => HM2WriteBuffer0(31 downto 24) <= mobus;
when others => null;
end case;
end if;
if StartExtRead = '1' then -- set read request - this is to sync processor I/O to
StartExtReadRq <= '1'; -- slower HM2 base clock
end if;
if StartExtWrite = '1' then -- set write request - this is to sync processor I/O to
StartExtWriteRq <= '1'; -- slower HM2 base clock
end if;
if WriteExtAddLow = '1' then
ExtAddress0(7 downto 0) <= mobus;
end if;
if WriteExtAddHigh = '1' then
ExtAddress0(15 downto 8) <= mobus;
end if;
end if; -- procclk
if rising_edge(hm2interfaceclock) then
HM2WriteBuffer1 <= HM2WriteBuffer0;
ExtAddress1 <= ExtAddress0;
StartExtReadDel <= StartExtReadDel(0) & StartExtReadRq;
StartExtWriteDel <= StartExtWriteDel(0) & StartExtWriteRq;
if Read32 = '1' then
HM2ReadBuffer0 <= HM2OBus;
end if;
end if;
if StartExtReadDel = "11" then
Read32 <= '1';
else
Read32 <= '0';
end if;
if StartExtWriteDel = "11" then
Write32 <= '1';
else
Write32 <= '0';
end if;
if StartExtReadDel(1) = '1' then -- asynchronous clear read request
StartExtReadRq <= '0';
end if;
if StartExtWriteDel(1) = '1' then -- asynchronous clear write request
StartExtWriteRq <= '0';
end if;
mibus_io <= "ZZZZZZZZ";
if ReadExtData = '1' then
case rseladd(1 downto 0) is
when "00" => mibus_io <= HM2ReadBuffer1( 7 downto 0);
when "01" => mibus_io <= HM2ReadBuffer1(15 downto 8);
when "10" => mibus_io <= HM2ReadBuffer1(23 downto 16);
when "11" => mibus_io <= HM2ReadBuffer1(31 downto 24);
when others => null;
end case;
end if;
if ReadExtAddLow = '1' then
mibus_io <= ExtAddress0( 7 downto 0);
end if;
if ReadExtAddHigh = '1' then
mibus_io <= ExtAddress0(15 downto 8);
end if;
if ReadEIOCookie = '1' then
mibus_io <= EIOCookie;
end if;
-- LEDS <= HM2WriteBuffer1(7 downto 0); -- debug kludge
end process;
USBInterfaceDrive: process (procclk, USBDataReg, DATABUS, USB_TSEn, ReadUSBData, ReadUSBStatus)
begin
DATABUS <= "ZZZZZZZZ";
if USB_TSEn = '1' then
DATABUS <= USBDataReg;
end if;
mibus_io <= "ZZZZZZZZ";
if ReadUSBData = '1' and ReadUSBStatus = '0' then
mibus_io <= DATABUS;
end if;
if ReadUSBStatus = '1' and ReadUSBData = '0' then
mibus_io(0) <= USB_RXF; -- active low receiver has data
mibus_io(1) <= USB_TXE; -- active low xmit buffer has space
mibus_io(7 downto 2) <= "101010";
end if;
if rising_edge(procclk) then
if LoadUSBControlReg = '1' then
USBContReg <= mobus(2 downto 0);
end if;
if LoadUSBDataReg = '1' then
USBDataReg <= mobus;
end if;
end if;
USB_RD <= USB_RdReg;
USB_WRITE <= USB_WriteReg;
-- LEDS <= not LocalLEDs;
PARACONFIG <= '0';
end process USBInterfaceDrive;
end Behavioral;
| lgpl-2.1 | 46c4e77f39e06cd26097535ee4acf1da | 0.648378 | 3.025734 | false | false | false | false |
pwsoft/fpga_examples | rtl/chameleon/chameleon2_io_ps2iec.vhd | 1 | 3,965 | -- -----------------------------------------------------------------------
--
-- Turbo Chameleon 64
--
-- Multi purpose FPGA expansion for the Commodore 64 computer
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2018 by Peter Wendrich ([email protected])
-- http://www.syntiac.com
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
-- I/O controller entity for the PS2IEC multiplexer.
-- This provides capturing and reading the state of the (multiplexed)
-- PS/2 and IEC lines.
--
-- -----------------------------------------------------------------------
-- clk - System clock
-- ps2iec_sel - Select line, connect on toplevel to port with same name
-- ps2iec - Multiplexed signals, connect on toplevel to port with same name
--
-- ps2_mouse_clk - State of the PS/2 mouse clock signal
-- ps2_mouse_dat - State of the PS/2 mouse data signal
-- ps2_mouse_clk - State of the PS/2 keyboard clock signal
-- ps2_mouse_dat - State of the PS/2 keyboard data signal
--
-- iec_clk - State of the CLK line on the IEC bus
-- iec_srq - State of the SRQ line on the IEC bus
-- iec_atn - State of the ATN line on the IEC bus
-- iec_dat - State of the DAT line on the IEC bus
-- -----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- -----------------------------------------------------------------------
entity chameleon2_io_ps2iec is
port (
clk : in std_logic;
-- Mux signals
ps2iec_sel : out std_logic;
ps2iec : in unsigned(3 downto 0);
-- Decoded
ps2_mouse_clk : out std_logic;
ps2_mouse_dat : out std_logic;
ps2_keyboard_clk : out std_logic;
ps2_keyboard_dat : out std_logic;
iec_clk : out std_logic;
iec_srq : out std_logic;
iec_atn : out std_logic;
iec_dat : out std_logic
);
end entity;
architecture rtl of chameleon2_io_ps2iec is
signal state_reg : unsigned(2 downto 0) := "000";
signal ps2iec_reg : unsigned(3 downto 0) := "1111";
signal ps2_mouse_clk_reg : std_logic := '1';
signal ps2_mouse_dat_reg : std_logic := '1';
signal ps2_keyboard_clk_reg : std_logic := '1';
signal ps2_keyboard_dat_reg : std_logic := '1';
signal iec_clk_reg : std_logic := '1';
signal iec_srq_reg : std_logic := '1';
signal iec_atn_reg : std_logic := '1';
signal iec_dat_reg : std_logic := '1';
begin
ps2iec_sel <= state_reg(2);
ps2_mouse_clk <= ps2_mouse_clk_reg;
ps2_mouse_dat <= ps2_mouse_dat_reg;
ps2_keyboard_clk <= ps2_keyboard_clk_reg;
ps2_keyboard_dat <= ps2_keyboard_dat_reg;
iec_clk <= iec_clk_reg;
iec_srq <= iec_srq_reg;
iec_atn <= iec_atn_reg;
iec_dat <= iec_dat_reg;
process(clk)
begin
if rising_edge(clk) then
state_reg <= state_reg + 1;
ps2iec_reg <= ps2iec;
if state_reg = "011" then
-- Capture PS2 lines
ps2_mouse_dat_reg <= ps2iec_reg(0);
ps2_mouse_clk_reg <= ps2iec_reg(1);
ps2_keyboard_clk_reg <= ps2iec_reg(2);
ps2_keyboard_dat_reg <= ps2iec_reg(3);
end if;
if state_reg = "111" then
-- Capture IEC lines
iec_atn_reg <= ps2iec_reg(0);
iec_dat_reg <= ps2iec_reg(1);
iec_clk_reg <= ps2iec_reg(2);
iec_srq_reg <= ps2iec_reg(3);
end if;
end if;
end process;
end architecture;
| lgpl-2.1 | a67986db0af4aff59e8e75c623b95cc5 | 0.595208 | 3.255337 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/maps/syncram256bw.vhd | 1 | 6,386 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: syncram256bw
-- File: syncram256bw.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: 256-bit syncronous 1-port ram with 8-bit write strobes
-- and tech selection
------------------------------------------------------------------------------
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
library grlib;
use grlib.config.all;
use grlib.config_types.all;
use grlib.stdlib.all;
entity syncram256bw is
generic (tech : integer := 0; abits : integer := 6; testen : integer := 0; custombits: integer := 1);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (255 downto 0);
dataout : out std_logic_vector (255 downto 0);
enable : in std_logic_vector (31 downto 0);
write : in std_logic_vector (31 downto 0);
testin : in std_logic_vector (TESTIN_WIDTH-1 downto 0) := testin_none
);
end;
architecture rtl of syncram256bw is
component unisim_syncram128bw
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (127 downto 0);
dataout : out std_logic_vector (127 downto 0);
enable : in std_logic_vector (15 downto 0);
write : in std_logic_vector (15 downto 0)
);
end component;
component altera_syncram128bw
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (127 downto 0);
dataout : out std_logic_vector (127 downto 0);
enable : in std_logic_vector (15 downto 0);
write : in std_logic_vector (15 downto 0)
);
end component;
component altera_syncram256bw
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (255 downto 0);
dataout : out std_logic_vector (255 downto 0);
enable : in std_logic_vector (31 downto 0);
write : in std_logic_vector (31 downto 0)
);
end component;
component tm65gplus_syncram256bw
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (255 downto 0);
dataout : out std_logic_vector (255 downto 0);
enable : in std_logic_vector (31 downto 0);
write : in std_logic_vector (31 downto 0);
testin : in std_logic_vector (3 downto 0) := "0000"
);
end component;
component cmos9sf_syncram256bw
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (255 downto 0);
dataout : out std_logic_vector (255 downto 0);
enable : in std_logic_vector (31 downto 0);
write : in std_logic_vector (31 downto 0);
testin : in std_logic_vector (3 downto 0) := "0000"
);
end component;
signal xenable, xwrite : std_logic_vector(31 downto 0);
signal custominx,customoutx: std_logic_vector(syncram_customif_maxwidth downto 0);
begin
xenable <= enable when testen=0 or testin(TESTIN_WIDTH-2)='0' else (others => '0');
xwrite <= write when testen=0 or testin(TESTIN_WIDTH-2)='0' else (others => '0');
custominx <= (others => '0');
nocust: if has_sram256bw(tech)=0 or syncram_has_customif(tech)=0 generate
customoutx <= (others => '0');
end generate;
s256 : if has_sram256bw(tech) = 1 generate
uni : if (is_unisim(tech) = 1) generate
x0 : unisim_syncram128bw generic map (abits)
port map (clk, address, datain(127 downto 0), dataout(127 downto 0),
xenable(15 downto 0), xwrite(15 downto 0));
x1 : unisim_syncram128bw generic map (abits)
port map (clk, address, datain(255 downto 128), dataout(255 downto 128),
xenable(31 downto 16), xwrite(31 downto 16));
end generate;
alt : if (tech = stratix2) or (tech = stratix3) or (tech = stratix4) or
(tech = cyclone3) or (tech = altera) generate
x0 : altera_syncram256bw generic map (abits)
port map (clk, address, datain, dataout, xenable, xwrite);
end generate;
tm65: if tech = tm65gplus generate
x0 : tm65gplus_syncram256bw generic map (abits)
port map (clk, address, datain, dataout, xenable, xwrite, testin);
end generate;
cm9s: if tech = cmos9sf generate
x0 : cmos9sf_syncram256bw generic map (abits)
port map (clk, address, datain, dataout, xenable, xwrite, testin);
end generate;
-- pragma translate_off
dmsg : if GRLIB_CONFIG_ARRAY(grlib_debug_level) >= 2 generate
x : process
begin
assert false report "syncram256bw: " & tost(2**abits) & "x256" &
" (" & tech_table(tech) & ")"
severity note;
wait;
end process;
end generate;
-- pragma translate_on
end generate;
nos256 : if has_sram256bw(tech) = 0 generate
rx : for i in 0 to 31 generate
x0 : syncram generic map (tech, abits, 8, testen, custombits)
port map (clk, address, datain(i*8+7 downto i*8),
dataout(i*8+7 downto i*8), enable(i), write(i), testin
);
end generate;
end generate;
end;
| gpl-3.0 | c282bedc7a4dac6e7e0833b915017abc | 0.628093 | 3.628409 | false | true | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-terasic-de2-115/testbench.vhd | 1 | 11,001 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
use work.debug.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library grlib;
use grlib.stdlib.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romdepth : integer := 20; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 20; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal sma_clkout : std_ulogic;
signal address : std_logic_vector(22 downto 0);
signal data : std_logic_vector(31 downto 24);
signal ramsn : std_logic_vector(4 downto 0);
signal ramoen : std_logic_vector(4 downto 0);
signal rwen : std_logic_vector(3 downto 0);
signal rwenx : std_logic_vector(3 downto 0);
signal romsn : std_logic;
signal iosn : std_logic;
signal oen : std_logic;
signal read : std_logic;
signal writen : std_logic;
signal brdyn : std_logic;
signal bexcn : std_logic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_logic;
signal dsurst : std_logic;
signal test : std_logic;
signal error : std_logic;
signal gpio : std_logic_vector(35 downto 0);
signal GND : std_logic := '0';
signal VCC : std_logic := '1';
signal NC : std_logic := 'Z';
signal clk2 : std_logic := '1';
signal sdcke : std_logic;
signal sdcsn : std_logic;
signal sdwen : std_logic; -- write en
signal sdrasn : std_logic; -- row addr stb
signal sdcasn : std_logic; -- col addr stb
signal sddqm : std_logic_vector ( 3 downto 0); -- data i/o mask
signal sdclk : std_logic;
signal plllock : std_logic;
signal txd1, rxd1 : std_logic;
signal etx_clk, erx_clk, erx_dv, erx_er, erx_col : std_logic := '0';
signal eth_gtxclk, erx_crs, etx_en, etx_er : std_logic :='0';
signal eth_macclk : std_logic := '0';
signal erxd, etxd : std_logic_vector(7 downto 0) := (others => '0');
signal emdc, emdio : std_logic; --dummy signal for the mdc,mdio in the phy which is not used
signal emdintn : std_logic := '1';
signal emddis : std_logic;
signal epwrdwn : std_logic;
signal ereset : std_logic;
signal esleep : std_logic;
signal epause : std_logic;
constant lresp : boolean := false;
signal sa : std_logic_vector(14 downto 0);
signal sd : std_logic_vector(31 downto 0);
signal can_txd : std_logic_vector(0 to CFG_CAN_NUM-1);
signal can_rxd : std_logic_vector(0 to CFG_CAN_NUM-1);
signal can_stb : std_logic_vector(0 to CFG_CAN_NUM-1);
signal clk_1553 : std_logic;
signal busainen : std_logic;
signal busainp : std_logic;
signal busainn : std_logic;
signal busaoutin : std_logic;
signal busaoutp : std_logic;
signal busaoutn : std_logic;
signal busbinen : std_logic;
signal busbinp : std_logic;
signal busbinn : std_logic;
signal busboutin : std_logic;
signal busboutp : std_logic;
signal busboutn : std_logic;
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
rst <= dsurst;
dsuen <= '1';
dsubre <= '1'; -- inverted on the board
rxd1 <= '1';
can_rxd <= (others => 'H'); bexcn <= '1';
gpio(2 downto 0) <= "LHL";
gpio(CFG_GRGPIO_WIDTH-1 downto 3) <= (others => 'H');
eth_macclk <= not eth_macclk after 4 ns;
ereset <= 'H';
d3 : entity work.leon3mp
generic map ( fabtech, memtech, padtech, clktech, disas, dbguart, pclow )
port map (rst, clk, sma_clkout, error, address(22 downto 0), data,
sa(12 downto 0), sa(14 downto 13), sd, sdclk, sdcke, sdcsn, sdwen,
sdrasn, sdcasn, sddqm, dsutx, dsurx, dsubre, dsuact,
oen, writen, open, open, romsn, gpio,
emdio, eth_macclk, etx_clk, erx_clk, erxd(3 downto 0), erx_dv, erx_er,
erx_col, erx_crs, emdintn, ereset, etxd(3 downto 0), etx_en, etx_er, emdc,
can_txd, can_rxd, can_stb,
clk_1553, busainen, busainp, busainn, busaoutin, busaoutp, busaoutn,
busbinen, busbinp, busbinn, busboutin, busboutp, busboutn
);
sd1 : if ((CFG_MCTRL_SDEN = 1) and (CFG_MCTRL_SEPBUS = 1)) generate
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke,
Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke,
Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
end generate;
prom0 : sram generic map (index => 6, abits => romdepth, fname => promfile)
port map (address(romdepth-1 downto 0), data(31 downto 24), romsn,
writen, oen);
-- sram0 : for i in 0 to (sramwidth/8)-1 generate
-- sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
-- port map (address(sramdepth+1 downto 2), data(31-i*8 downto 24-i*8), ramsn(0),
-- rwen(0), ramoen(0));
-- end generate;
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
p0: phy
generic map(address => 16)
port map(ereset, emdio, etx_clk, erx_clk, erxd, erx_dv,
erx_er, erx_col, erx_crs, etxd, etx_en, etx_er, emdc, eth_macclk);
end generate;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
-- test0 : grtestmod
-- port map ( rst, clk, error, address(21 downto 2), data,
-- iosn, oen, writen, brdyn);
-- data <= buskeep(data), (others => 'H') after 250 ns;
data <= buskeep(data) after 5 ns;
-- sd <= buskeep(sd), (others => 'H') after 250 ns;
sd <= buskeep(sd) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_logic; signal dsutx : out std_logic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
| gpl-3.0 | e6d8815a016db7a2f1280769273bc55d | 0.58831 | 3.073764 | false | false | false | false |
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