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EliasLuiz/TCC | Leon3/lib/techmap/maps/inpad.vhd | 1 | 5,326 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: inpad
-- File: inpad.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: input pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity inpad is
generic (tech : integer := 0; level : integer := 0;
voltage : integer := x33v; filter : integer := 0;
strength : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of inpad is
begin
gen0 : if has_pads(tech) = 0 generate
o <= transport to_X01(pad)
-- pragma translate_off
after 1 ns
-- pragma translate_on
;
end generate;
xcv : if (is_unisim(tech) = 1) generate
x0 : unisim_inpad generic map (level, voltage) port map (pad, o);
end generate;
axc : if (tech = axcel) or (tech = axdsp) generate
x0 : axcel_inpad generic map (level, voltage) port map (pad, o);
end generate;
pa3 : if (tech = proasic) or (tech = apa3) generate
x0 : apa3_inpad generic map (level, voltage, filter) port map (pad, o);
end generate;
pa3e : if (tech = apa3e) generate
x0 : apa3e_inpad generic map (level, voltage, filter) port map (pad, o);
end generate;
igl2 : if (tech = igloo2) or (tech = rtg4) generate
x0 : igloo2_inpad port map (pad, o);
end generate;
pa3l : if (tech = apa3l) generate
x0 : apa3l_inpad generic map (level, voltage, filter) port map (pad, o);
end generate;
fus : if (tech = actfus) generate
x0 : fusion_inpad generic map (level, voltage, filter) port map (pad, o);
end generate;
atc : if (tech = atc18s) generate
x0 : atc18_inpad generic map (level, voltage) port map (pad, o);
end generate;
atcrh : if (tech = atc18rha) generate
x0 : atc18rha_inpad generic map (level, voltage) port map (pad, o);
end generate;
um : if (tech = umc) generate
x0 : umc_inpad generic map (level, voltage, filter) port map (pad, o);
end generate;
rhu : if (tech = rhumc) generate
x0 : rhumc_inpad generic map (level, voltage, filter) port map (pad, o);
end generate;
saed : if (tech = saed32) generate
x0 : saed32_inpad generic map (level, voltage, filter) port map (pad, o);
end generate;
rhs : if (tech = rhs65) generate
x0 : rhs65_inpad generic map (level, voltage, filter) port map (pad, o);
end generate;
dar : if (tech = dare) generate
x0 : dare_inpad generic map (level, voltage, filter) port map (pad, o);
end generate;
ihp : if (tech = ihp25) generate
x0 : ihp25_inpad generic map(level, voltage) port map(pad, o);
end generate;
ihprh : if (tech = ihp25rh) generate
x0 : ihp25rh_inpad generic map(level, voltage) port map(pad, o);
end generate;
rh18t : if (tech = rhlib18t) generate
x0 : rh_lib18t_inpad generic map (voltage, filter) port map(pad, o);
end generate;
ut025 : if (tech = ut25) generate
x0 : ut025crh_inpad generic map (level, voltage, filter) port map(pad, o);
end generate;
ut13 : if (tech = ut130) generate
x0 : ut130hbd_inpad generic map (level, voltage, filter) port map(pad, o);
end generate;
pereg : if (tech = peregrine) generate
x0 : peregrine_inpad generic map (level, voltage, filter, strength) port map(pad, o);
end generate;
eas : if (tech = easic90) generate
x0 : nextreme_inpad generic map (level, voltage) port map (pad, o);
end generate;
n2x : if (tech = easic45) generate
x0 : n2x_inpad generic map (level, voltage) port map (pad, o);
end generate;
ut90nhbd : if (tech = ut90) generate
x0 : ut90nhbd_inpad generic map (level, voltage, filter) port map(pad, o);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity inpadv is
generic (tech : integer := 0; level : integer := 0;
voltage : integer := 0; width : integer := 1;
filter : integer := 0; strength : integer := 0);
port (
pad : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0));
end;
architecture rtl of inpadv is
begin
v : for i in width-1 downto 0 generate
x0 : inpad generic map (tech, level, voltage, filter, strength) port map (pad(i), o(i));
end generate;
end;
| gpl-3.0 | e0f3de0fd9ff27e0e31fa49529cd7004 | 0.645325 | 3.501644 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-altera-ep3c25-eek/altera_eek_clkgen.vhd | 1 | 4,217 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library altera_mf;
use altera_mf.altpll;
library grlib;
use grlib.stdlib.all;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity altera_eek_clkgen is
generic (
clk0_mul : integer := 1;
clk0_div : integer := 1;
clk1_mul : integer := 1;
clk1_div : integer := 1;
clk_freq : integer := 25000);
port (
inclk0 : in std_ulogic;
clk0 : out std_ulogic;
clk0x3 : out std_ulogic;
clksel : in std_logic_vector(1 downto 0);
locked : out std_ulogic);
end;
architecture rtl of altera_eek_clkgen is
component altpll
generic (
intended_device_family : string := "CycloneIII" ;
operation_mode : string := "NORMAL" ;
compensate_clock : string := "clock0";
inclk0_input_frequency : positive;
width_clock : positive := 6;
clk0_multiply_by : positive := 1;
clk0_divide_by : positive := 1;
clk1_multiply_by : positive := 1;
clk1_divide_by : positive := 1;
clk2_multiply_by : positive := 1;
clk2_divide_by : positive := 1;
clk3_multiply_by : positive := 1;
clk3_divide_by : positive := 1
);
port (
inclk : in std_logic_vector(1 downto 0);
clkena : in std_logic_vector(5 downto 0);
clk : out std_logic_vector(width_clock-1 downto 0);
locked : out std_logic
);
end component;
signal clkena : std_logic_vector (5 downto 0);
signal clkout : std_logic_vector (4 downto 0);
signal inclk : std_logic_vector (1 downto 0);
constant clk_period : integer := 1000000000/clk_freq;
constant CLK0_MUL3X : integer := clk0_mul * 3;
constant CLK1_MUL3X : integer := clk1_mul * 3;
constant VERSION : integer := 1;
attribute syn_keep : boolean;
attribute syn_keep of clkout : signal is true;
begin
clkena(5 downto 4) <= (others => '0');
clkena(0) <= '1';
clkena(1) <= '1';
clkena(2) <= '1';
clkena(3) <= '1';
inclk <= '0' & inclk0;
clk_select: process (clkout, clksel)
begin -- process clk_select
case clksel is
when "00" => clk0 <= clkout(0); clk0x3 <= clkout(1);
when "01" => clk0 <= clkout(2); clk0x3 <= clkout(3);
when others => clk0 <= '0'; clk0x3 <= '0';
end case;
end process clk_select;
altpll0 : altpll
generic map (
intended_device_family => "Cyclone III",
operation_mode => "NO_COMPENSATION", inclk0_input_frequency => clk_period,
width_clock => 5, compensate_clock => "CLK1",
clk0_multiply_by => clk0_mul, clk0_divide_by => clk0_div,
clk1_multiply_by => CLK0_MUL3X, clk1_divide_by => clk0_div,
clk2_multiply_by => clk1_mul, clk2_divide_by => clk1_div,
clk3_multiply_by => CLK1_MUL3X, clk3_divide_by => clk1_div)
port map (clkena => clkena, inclk => inclk,
clk => clkout, locked => locked);
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_cycloneiii" & ": altpll lcd/vga clock generator, version " & tost(VERSION)
);
-- pragma translate_on
end;
| gpl-3.0 | 6cc910dbbc67dbd5dffa0de9d5f22156 | 0.606118 | 3.555649 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/umc18/memory_umc18.vhd | 1 | 9,471 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: mem_umc_gen.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: Memory generators for UMC rams
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library umc18;
use umc18.SRAM_2048wx32b;
use umc18.SRAM_1024wx32b;
use umc18.SRAM_512wx32b;
use umc18.SRAM_256wx32b;
use umc18.SRAM_128wx32b;
use umc18.SRAM_64wx32b;
use umc18.SRAM_32wx32b;
use umc18.SRAM_2048wx40b;
use umc18.SRAM_1024wx40b;
use umc18.SRAM_512wx40b;
use umc18.SRAM_256wx40b;
use umc18.SRAM_128wx40b;
use umc18.SRAM_64wx40b;
use umc18.SRAM_32wx40b;
-- pragma translate_on
entity umc_syncram is
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector(abits -1 downto 0);
datain : in std_logic_vector(dbits -1 downto 0);
dataout : out std_logic_vector(dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end;
architecture rtl of umc_syncram is
component SRAM_2048wx32b is
port (
a : in std_logic_vector(10 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end component;
component SRAM_1024wx32b is
port (
a : in std_logic_vector(9 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end component;
component SRAM_512wx32b is
port (
a : in std_logic_vector(8 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end component;
component SRAM_256wx32b is
port (
a : in std_logic_vector(7 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end component;
component SRAM_128wx32b is
port (
a : in std_logic_vector(6 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end component;
component SRAM_64wx32b is
port (
a : in std_logic_vector(5 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end component;
component SRAM_32wx32b is
port (
a : in std_logic_vector(4 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end component;
component SRAM_2048wx40b is
port (
a : in std_logic_vector(10 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end component;
component SRAM_1024wx40b is
port (
a : in std_logic_vector(9 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end component;
component SRAM_512wx40b is
port (
a : in std_logic_vector(8 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end component;
component SRAM_256wx40b is
port (
a : in std_logic_vector(7 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end component;
component SRAM_128wx40b is
port (
a : in std_logic_vector(6 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end component;
component SRAM_64wx40b is
port (
a : in std_logic_vector(5 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end component;
component SRAM_32wx40b is
port (
a : in std_logic_vector(4 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end component;
signal d, q, gnd : std_logic_vector(41 downto 0);
signal a : std_logic_vector(17 downto 0);
signal vcc, csn, wen : std_ulogic;
constant synopsys_bug : std_logic_vector(41 downto 0) := (others => '0');
begin
csn <= not enable; wen <= not write;
gnd <= (others => '0'); vcc <= '1';
a(abits -1 downto 0) <= address;
d(dbits -1 downto 0) <= datain(dbits -1 downto 0);
a(17 downto abits) <= synopsys_bug(17 downto abits);
d(41 downto dbits) <= synopsys_bug(41 downto dbits);
dataout <= q(dbits -1 downto 0);
-- q(41 downto dbits) <= synopsys_bug(41 downto dbits);
d32 : if (dbits <= 32) generate
a5d32 : if (abits <= 5) generate
id0 : SRAM_32wx32b port map (a(4 downto 0), d(31 downto 0), csn,
wen, gnd(0), q(31 downto 0), clk);
end generate;
a6d32 : if (abits = 6) generate
id0 : SRAM_64wx32b port map (a(5 downto 0), d(31 downto 0), csn,
wen, gnd(0), q(31 downto 0), clk);
end generate;
a7d32 : if (abits = 7) generate
id0 : SRAM_128wx32b port map (a(6 downto 0), d(31 downto 0), csn,
wen, gnd(0), q(31 downto 0), clk);
end generate;
a8d32 : if (abits = 8) generate
id0 : SRAM_256wx32b port map (a(7 downto 0), d(31 downto 0), csn,
wen, gnd(0), q(31 downto 0), clk);
end generate;
a9d32 : if (abits = 9) generate
id0 : SRAM_512wx32b port map (a(8 downto 0), d(31 downto 0), csn,
wen, gnd(0), q(31 downto 0), clk);
end generate;
a10d32 : if (abits = 10) generate
id0 : SRAM_1024wx32b port map (a(9 downto 0), d(31 downto 0), csn,
wen, gnd(0), q(31 downto 0), clk);
end generate;
a11d32 : if (abits = 11) generate
id0 : SRAM_2048wx32b port map (a(10 downto 0), d(31 downto 0), csn,
wen, gnd(0), q(31 downto 0), clk);
end generate;
end generate;
d40 : if (dbits > 32) and (dbits <= 40) generate
a5d40 : if (abits <= 5) generate
id0 : SRAM_32wx40b port map (a(4 downto 0), d(39 downto 0), csn,
wen, gnd(0), q(39 downto 0), clk);
end generate;
a6d40 : if (abits = 6) generate
id0 : SRAM_64wx40b port map (a(5 downto 0), d(39 downto 0), csn,
wen, gnd(0), q(39 downto 0), clk);
end generate;
a7d40 : if (abits = 7) generate
id0 : SRAM_128wx40b port map (a(6 downto 0), d(39 downto 0), csn,
wen, gnd(0), q(39 downto 0), clk);
end generate;
a8d40 : if (abits = 8) generate
id0 : SRAM_256wx40b port map (a(7 downto 0), d(39 downto 0), csn,
wen, gnd(0), q(39 downto 0), clk);
end generate;
a9d40 : if (abits = 9) generate
id0 : SRAM_512wx40b port map (a(8 downto 0), d(39 downto 0), csn,
wen, gnd(0), q(39 downto 0), clk);
end generate;
a10d40 : if (abits = 10) generate
id0 : SRAM_1024wx40b port map (a(9 downto 0), d(39 downto 0), csn,
wen, gnd(0), q(39 downto 0), clk);
end generate;
a11d40 : if (abits = 11) generate
id0 : SRAM_2048wx40b port map (a(10 downto 0), d(39 downto 0), csn,
wen, gnd(0), q(39 downto 0), clk);
end generate;
end generate;
-- pragma translate_off
a_to_high : if (abits > 11) or (dbits > 40) generate
x : process
begin
assert false
report "Unsupported memory size (umc18)"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end;
| gpl-3.0 | 55c851b7c9cd7829ffeba5ed9bdc7cd9 | 0.606589 | 2.912362 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/spw/comp/spwcomp.vhd | 1 | 31,506 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package spwcomp is
component grspwc2 is
generic(
rmap : integer range 0 to 2 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 64 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
scantest : integer range 0 to 1 := 0;
ports : integer range 1 to 2 := 1;
dmachan : integer range 1 to 4 := 1;
tech : integer;
input_type : integer range 0 to 4 := 0;
output_type : integer range 0 to 2 := 0;
rxtx_sameclk : integer range 0 to 1 := 0;
nodeaddr : integer range 0 to 255 := 254;
destkey : integer range 0 to 255 := 0;
interruptdist : integer range 0 to 32 := 0;
intscalerbits : integer range 0 to 31 := 0;
intisrtimerbits : integer range 0 to 31 := 0;
intiatimerbits : integer range 0 to 31 := 0;
intctimerbits : integer range 0 to 31 := 0;
tickinasync : integer range 0 to 1 := 0;
pnp : integer range 0 to 2 := 0;
pnpvendid : integer range 0 to 16#FFFF# := 0;
pnpprodid : integer range 0 to 16#FFFF# := 0;
pnpmajorver : integer range 0 to 16#FF# := 0;
pnpminorver : integer range 0 to 16#FF# := 0;
pnppatch : integer range 0 to 16#FF# := 0;
num_txdesc : integer range 64 to 512 := 64;
num_rxdesc : integer range 128 to 1024 := 128
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxclk0 : in std_ulogic;
rxclk1 : in std_ulogic;
txclk : in std_ulogic;
txclkn : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
d : in std_logic_vector(3 downto 0);
dv : in std_logic_vector(3 downto 0);
dconnect : in std_logic_vector(3 downto 0);
--spw out
do : out std_logic_vector(3 downto 0);
so : out std_logic_vector(3 downto 0);
--time iface
tickin : in std_ulogic;
tickinraw : in std_ulogic;
timein : in std_logic_vector(7 downto 0);
tickindone : out std_ulogic;
tickout : out std_ulogic;
tickoutraw : out std_ulogic;
timeout : out std_logic_vector(7 downto 0);
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
--rmapen
rmapen : in std_ulogic;
rmapnodeaddr : in std_logic_vector(7 downto 0);
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(5 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(5 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(5 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(5 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--nchar fifo
ncrenable : out std_ulogic;
ncraddress : out std_logic_vector(5 downto 0);
ncwrite : out std_ulogic;
ncwdata : out std_logic_vector(9 downto 0);
ncwaddress : out std_logic_vector(5 downto 0);
ncrdata : in std_logic_vector(9 downto 0);
--rmap buf
rmrenable : out std_ulogic;
rmraddress : out std_logic_vector(7 downto 0);
rmwrite : out std_ulogic;
rmwdata : out std_logic_vector(7 downto 0);
rmwaddress : out std_logic_vector(7 downto 0);
rmrdata : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0';
--parallel rx data out
rxdav : out std_ulogic;
rxdataout : out std_logic_vector(8 downto 0);
loopback : out std_ulogic;
-- interrupt dist. default values
intpreload : in std_logic_vector(30 downto 0);
inttreload : in std_logic_vector(30 downto 0);
intiareload : in std_logic_vector(30 downto 0);
intcreload : in std_logic_vector(30 downto 0);
irqtxdefault : in std_logic_vector(4 downto 0);
-- SpW PnP enable
pnpen : in std_ulogic;
pnpuvendid : in std_logic_vector(15 downto 0);
pnpuprodid : in std_logic_vector(15 downto 0);
pnpusn : in std_logic_vector(31 downto 0)
);
end component;
component grspwc is
generic(
sysfreq : integer := 40000;
usegen : integer range 0 to 1 := 1;
nsync : integer range 1 to 2 := 1;
rmap : integer range 0 to 2 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 32 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
scantest : integer range 0 to 1 := 0;
ports : integer range 1 to 2 := 1;
tech : integer;
nodeaddr : integer range 0 to 255 := 254;
destkey : integer range 0 to 255 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
d : in std_logic_vector(1 downto 0);
nd : in std_logic_vector(9 downto 0);
dconnect : in std_logic_vector(3 downto 0);
--spw out
do : out std_logic_vector(1 downto 0);
so : out std_logic_vector(1 downto 0);
rxrsto : out std_ulogic;
--time iface
tickin : in std_ulogic;
tickout : out std_ulogic;
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
dcrstval : in std_logic_vector(9 downto 0);
timerrstval : in std_logic_vector(11 downto 0);
--rmapen
rmapen : in std_ulogic;
rmapnodeaddr : in std_logic_vector(7 downto 0);
--clk bufs
rxclki : in std_logic_vector(1 downto 0);
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(4 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(4 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(4 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(4 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--nchar fifo
ncrenable : out std_ulogic;
ncraddress : out std_logic_vector(5 downto 0);
ncwrite : out std_ulogic;
ncwdata : out std_logic_vector(8 downto 0);
ncwaddress : out std_logic_vector(5 downto 0);
ncrdata : in std_logic_vector(8 downto 0);
--rmap buf
rmrenable : out std_ulogic;
rmraddress : out std_logic_vector(7 downto 0);
rmwrite : out std_ulogic;
rmwdata : out std_logic_vector(7 downto 0);
rmwaddress : out std_logic_vector(7 downto 0);
rmrdata : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testclk : in std_ulogic := '0';
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0';
rmapact : out std_ulogic
);
end component;
component grspwc_axcelerator is
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
d : in std_logic_vector(1 downto 0);
nd : in std_logic_vector(1 downto 0);
--spw out
do : out std_logic_vector(1 downto 0);
so : out std_logic_vector(1 downto 0);
rxrsto : out std_ulogic;
--time iface
tickin : in std_ulogic;
tickout : out std_ulogic;
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
dcrstval : in std_logic_vector(9 downto 0);
timerrstval : in std_logic_vector(11 downto 0);
--rmapen
rmapen : in std_ulogic;
rmapnodeaddr : in std_logic_vector(7 downto 0);
--clk bufs
rxclki : in std_logic_vector(1 downto 0);
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(4 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(4 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(4 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(4 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--nchar fifo
ncrenable : out std_ulogic;
ncraddress : out std_logic_vector(5 downto 0);
ncwrite : out std_ulogic;
ncwdata : out std_logic_vector(8 downto 0);
ncwaddress : out std_logic_vector(5 downto 0);
ncrdata : in std_logic_vector(8 downto 0);
--rmap buf
rmrenable : out std_ulogic;
rmraddress : out std_logic_vector(7 downto 0);
rmwrite : out std_ulogic;
rmwdata : out std_logic_vector(7 downto 0);
rmwaddress : out std_logic_vector(7 downto 0);
rmrdata : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testclk : in std_ulogic := '0';
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0'
);
end component;
component grspwc_unisim is
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
d : in std_logic_vector(1 downto 0);
nd : in std_logic_vector(1 downto 0);
--spw out
do : out std_logic_vector(1 downto 0);
so : out std_logic_vector(1 downto 0);
rxrsto : out std_ulogic;
--time iface
tickin : in std_ulogic;
tickout : out std_ulogic;
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
dcrstval : in std_logic_vector(9 downto 0);
timerrstval : in std_logic_vector(11 downto 0);
--rmapen
rmapen : in std_ulogic;
rmapnodeaddr : in std_logic_vector(7 downto 0);
--clk bufs
rxclki : in std_logic_vector(1 downto 0);
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(4 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(4 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(4 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(4 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--nchar fifo
ncrenable : out std_ulogic;
ncraddress : out std_logic_vector(5 downto 0);
ncwrite : out std_ulogic;
ncwdata : out std_logic_vector(8 downto 0);
ncwaddress : out std_logic_vector(5 downto 0);
ncrdata : in std_logic_vector(8 downto 0);
--rmap buf
rmrenable : out std_ulogic;
rmraddress : out std_logic_vector(7 downto 0);
rmwrite : out std_ulogic;
rmwdata : out std_logic_vector(7 downto 0);
rmwaddress : out std_logic_vector(7 downto 0);
rmrdata : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testclk : in std_ulogic := '0';
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0'
);
end component;
component grspw_gen is
generic(
tech : integer := 0;
sysfreq : integer := 10000;
usegen : integer range 0 to 1 := 1;
nsync : integer range 1 to 2 := 1;
rmap : integer range 0 to 2 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 32 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxclkbuftype : integer range 0 to 2 := 0;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
ft : integer range 0 to 2 := 0;
scantest : integer range 0 to 1 := 0;
techfifo : integer range 0 to 1 := 1;
ports : integer range 1 to 2 := 1;
memtech : integer := 0;
nodeaddr : integer range 0 to 255 := 254;
destkey : integer range 0 to 255 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
rxclk : in std_logic_vector(1 downto 0);
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
d : in std_logic_vector(1 downto 0);
nd : in std_logic_vector(9 downto 0);
dconnect : in std_logic_vector(3 downto 0);
--spw out
do : out std_logic_vector(1 downto 0);
so : out std_logic_vector(1 downto 0);
rxrsto : out std_ulogic;
--time iface
tickin : in std_ulogic;
tickout : out std_ulogic;
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
dcrstval : in std_logic_vector(9 downto 0);
timerrstval : in std_logic_vector(11 downto 0);
--rmapen
rmapen : in std_ulogic;
rmapnodeaddr : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testclk : in std_ulogic := '0';
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0'
);
end component;
component grspw_codec_core is
generic(
ports : integer range 1 to 2 := 1;
input_type : integer range 0 to 4 := 0;
output_type : integer range 0 to 2 := 0;
rxtx_sameclk : integer range 0 to 1 := 0;
fifosize : integer range 16 to 2048 := 64;
tech : integer;
scantest : integer range 0 to 1 := 0;
inputtest : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxclk0 : in std_ulogic;
rxclk1 : in std_ulogic;
txclk : in std_ulogic;
txclkn : in std_ulogic;
testen : in std_ulogic;
testrst : in std_ulogic;
--spw in
d : in std_logic_vector(3 downto 0);
dv : in std_logic_vector(3 downto 0);
dconnect : in std_logic_vector(3 downto 0);
--spw out
do : out std_logic_vector(3 downto 0);
so : out std_logic_vector(3 downto 0);
--link fsm
linkdisabled : in std_ulogic;
linkstart : in std_ulogic;
autostart : in std_ulogic;
portsel : in std_ulogic;
noportforce : in std_ulogic;
rdivisor : in std_logic_vector(7 downto 0);
idivisor : in std_logic_vector(7 downto 0);
state : out std_logic_vector(2 downto 0);
actport : out std_ulogic;
dconnecterr : out std_ulogic;
crederr : out std_ulogic;
escerr : out std_ulogic;
parerr : out std_ulogic;
--rx fifo signals
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(10 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(9 downto 0);
rxwaddress : out std_logic_vector(10 downto 0);
rxrdata : in std_logic_vector(9 downto 0);
rxaccess : out std_ulogic;
--rx iface
rxicharav : out std_ulogic;
rxicharcnt : out std_logic_vector(11 downto 0);
rxichar : out std_logic_vector(8 downto 0);
rxiread : in std_ulogic;
rxififorst : in std_ulogic;
--tx fifo signals
txrenable : out std_ulogic;
txraddress : out std_logic_vector(10 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(8 downto 0);
txwaddress : out std_logic_vector(10 downto 0);
txrdata : in std_logic_vector(8 downto 0);
txaccess : out std_ulogic;
--tx iface
txicharcnt : out std_logic_vector(11 downto 0);
txifull : out std_ulogic;
txiempty : out std_ulogic;
txiwrite : in std_ulogic;
txichar : in std_logic_vector(8 downto 0);
txififorst : in std_ulogic;
txififorstact: out std_ulogic;
--time iface
tickin : in std_ulogic;
timein : in std_logic_vector(7 downto 0);
tickin_done : out std_ulogic;
tickin_busy : out std_ulogic;
tickout : out std_ulogic;
timeout : out std_logic_vector(7 downto 0);
credcnt : out std_logic_vector(5 downto 0);
ocredcnt : out std_logic_vector(5 downto 0);
--misc
powerdown : out std_ulogic;
powerdownrx : out std_ulogic;
-- input timing testing
testdi : in std_logic_vector(1 downto 0) := "00";
testsi : in std_logic_vector(1 downto 0) := "00";
testinput : in std_ulogic := '0'
);
end component;
component grspw2_gen is
generic(
rmap : integer range 0 to 2 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 64 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
scantest : integer range 0 to 1 := 0;
ports : integer range 1 to 2 := 1;
dmachan : integer range 1 to 4 := 1;
tech : integer;
input_type : integer range 0 to 4 := 0;
output_type : integer range 0 to 2 := 0;
rxtx_sameclk : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
techfifo : integer range 0 to 1 := 1;
memtech : integer := 0;
nodeaddr : integer range 0 to 255 := 254;
destkey : integer range 0 to 255 := 0;
interruptdist : integer range 0 to 32 := 0;
intscalerbits : integer range 0 to 31 := 0;
intisrtimerbits : integer range 0 to 31 := 0;
intiatimerbits : integer range 0 to 31 := 0;
intctimerbits : integer range 0 to 31 := 0;
tickinasync : integer range 0 to 1 := 0;
pnp : integer range 0 to 2 := 0;
pnpvendid : integer range 0 to 16#FFFF# := 0;
pnpprodid : integer range 0 to 16#FFFF# := 0;
pnpmajorver : integer range 0 to 16#FF# := 0;
pnpminorver : integer range 0 to 16#FF# := 0;
pnppatch : integer range 0 to 16#FF# := 0;
num_txdesc : integer range 64 to 512 := 64;
num_rxdesc : integer range 128 to 1024 := 128
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxclk0 : in std_ulogic;
rxclk1 : in std_ulogic;
txclk : in std_ulogic;
txclkn : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
d : in std_logic_vector(3 downto 0);
dv : in std_logic_vector(3 downto 0);
dconnect : in std_logic_vector(3 downto 0);
--spw out
do : out std_logic_vector(3 downto 0);
so : out std_logic_vector(3 downto 0);
--time iface
tickin : in std_ulogic;
tickinraw : in std_ulogic;
timein : in std_logic_vector(7 downto 0);
tickindone : out std_ulogic;
tickout : out std_ulogic;
tickoutraw : out std_ulogic;
timeout : out std_logic_vector(7 downto 0);
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0';
--rmapen
rmapen : in std_ulogic;
rmapnodeaddr : in std_logic_vector(7 downto 0);
--parallel rx data out
rxdav : out std_ulogic;
rxdataout : out std_logic_vector(8 downto 0);
loopback : out std_ulogic;
-- interrupt dist. default values
intpreload : in std_logic_vector(30 downto 0);
inttreload : in std_logic_vector(30 downto 0);
intiareload : in std_logic_vector(30 downto 0);
intcreload : in std_logic_vector(30 downto 0);
irqtxdefault : in std_logic_vector(4 downto 0);
-- SpW PnP enable
pnpen : in std_ulogic;
pnpuvendid : in std_logic_vector(15 downto 0);
pnpuprodid : in std_logic_vector(15 downto 0);
pnpusn : in std_logic_vector(31 downto 0)
);
end component;
component grspw_codec_gen is
generic(
ports : integer range 1 to 2 := 1;
input_type : integer range 0 to 4 := 0;
output_type : integer range 0 to 2 := 0;
rxtx_sameclk : integer range 0 to 1 := 0;
fifosize : integer range 16 to 2048 := 64;
tech : integer;
scantest : integer range 0 to 1 := 0;
techfifo : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxclk0 : in std_ulogic;
rxclk1 : in std_ulogic;
txclk : in std_ulogic;
txclkn : in std_ulogic;
testen : in std_ulogic;
testrst : in std_ulogic;
--spw in
d : in std_logic_vector(3 downto 0);
dv : in std_logic_vector(3 downto 0);
dconnect : in std_logic_vector(3 downto 0);
--spw out
do : out std_logic_vector(3 downto 0);
so : out std_logic_vector(3 downto 0);
--link fsm
linkdisabled : in std_ulogic;
linkstart : in std_ulogic;
autostart : in std_ulogic;
portsel : in std_ulogic;
noportforce : in std_ulogic;
rdivisor : in std_logic_vector(7 downto 0);
idivisor : in std_logic_vector(7 downto 0);
state : out std_logic_vector(2 downto 0);
actport : out std_ulogic;
dconnecterr : out std_ulogic;
crederr : out std_ulogic;
escerr : out std_ulogic;
parerr : out std_ulogic;
--rx iface
rxicharav : out std_ulogic;
rxicharcnt : out std_logic_vector(11 downto 0);
rxichar : out std_logic_vector(8 downto 0);
rxiread : in std_ulogic;
rxififorst : in std_ulogic;
--tx iface
txicharcnt : out std_logic_vector(11 downto 0);
txifull : out std_ulogic;
txiempty : out std_ulogic;
txiwrite : in std_ulogic;
txichar : in std_logic_vector(8 downto 0);
txififorst : in std_ulogic;
txififorstact: out std_ulogic;
--time iface
tickin : in std_ulogic;
timein : in std_logic_vector(7 downto 0);
tickin_done : out std_ulogic;
tickout : out std_ulogic;
timeout : out std_logic_vector(7 downto 0);
--misc
merror : out std_ulogic
);
end component;
end package;
| gpl-3.0 | dacaaa02453ba2297a19c266769b5dfa | 0.530724 | 3.670744 | false | false | false | false |
yishinli/emc2 | src/hal/drivers/m5i20/hostmot5_src/idreadback.vhd | 1 | 631 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity idreadback is
Generic ( id : std_logic_vector(31 downto 0);
mc : std_logic_vector(31 downto 0));
Port ( readid : in std_logic;
readmc : in std_logic;
obus : out std_logic_vector(31 downto 0));
end idreadback;
architecture Behavioral of idreadback is
begin
areadidprocess: process (readid, readmc)
begin
if readid = '1' and readmc = '0' then
obus <= id;
elsif readmc = '1' and readid = '0' then
obus <= mc;
else
obus <= (others => 'Z');
end if;
end process areadidprocess;
end Behavioral;
| lgpl-2.1 | 1a0e027bded8d49a81dab1573463a850 | 0.608558 | 3.155 | false | false | false | false |
freecores/cryptopan_core | tb/sbsr_tb.vhd | 1 | 2,199 | library ieee;
use ieee.std_logic_1164.all;
use work.cryptopan.all;
entity sbsr_tb is
end sbsr_tb;
architecture tb of sbsr_tb is
component subbytesshiftrows
port (
bytes_in : in s_vector;
bytes_out : out s_vector;
clk : in std_logic;
reset : in std_logic);
end component;
component mixcolumns
port (
bytes_in : in s_vector;
bytes_out : out s_vector;
clk : in std_logic;
reset : in std_logic);
end component;
signal clk : std_logic;
signal reset : std_logic;
signal bytes_in : s_vector;
signal bytes_out : s_vector;
signal mix_bytes_out : s_vector;
begin -- tb
CLKGEN: process
begin -- process CLKGEN
clk <= '1';
wait for 5 ns;
clk <= '0';
wait for 5 ns;
end process CLKGEN;
SUBBYTESSHIFTROWS0: subbytesshiftrows
port map (
bytes_in => bytes_in,
bytes_out => bytes_out,
clk => clk,
reset => reset);
MIX0: mixcolumns
port map (
bytes_in => bytes_out,
bytes_out => mix_bytes_out,
clk => clk,
reset => reset);
TB: process
begin -- process TB
reset <= '1';
wait for 55 ns;
reset <= '0';
wait for 20 ns;
bytes_in(0) <= X"19";
bytes_in(1) <= X"A0";
bytes_in(2) <= X"9A";
bytes_in(3) <= X"E9";
bytes_in(4) <= X"3D";
bytes_in(5) <= X"F4";
bytes_in(6) <= X"C6";
bytes_in(7) <= X"F8";
bytes_in(8) <= X"E3";
bytes_in(9) <= X"E2";
bytes_in(10) <= X"8D";
bytes_in(11) <= X"48";
bytes_in(12) <= X"BE";
bytes_in(13) <= X"2B";
bytes_in(14) <= X"2A";
bytes_in(15) <= X"08";
wait for 10 ns;
bytes_in(0) <= X"A4";
bytes_in(1) <= X"68";
bytes_in(2) <= X"6B";
bytes_in(3) <= X"02";
bytes_in(4) <= X"9C";
bytes_in(5) <= X"9F";
bytes_in(6) <= X"5B";
bytes_in(7) <= X"6A";
bytes_in(8) <= X"7F";
bytes_in(9) <= X"35";
bytes_in(10) <= X"EA";
bytes_in(11) <= X"50";
bytes_in(12) <= X"F2";
bytes_in(13) <= X"2B";
bytes_in(14) <= X"43";
bytes_in(15) <= X"49";
wait for 10 ns;
wait;
end process TB;
end tb;
| gpl-2.0 | 038a8810e7c2c3bc4f6a24fe3a361413 | 0.502956 | 2.714815 | false | false | false | false |
tmeissner/vhdl_verification | osvvm_fsm_psl_coverage/osvvm_fsm_psl_coverage.vhd | 1 | 3,274 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.env.all;
library osvvm;
use osvvm.NamePkg.all ;
use osvvm.TranscriptPkg.all ;
use osvvm.OsvvmGlobalPkg.all ;
use osvvm.AlertLogPkg.all ;
use osvvm.RandomPkg.all ;
use osvvm.CoveragePkg.all ;
use osvvm.MemoryPkg.all ;
entity osvvm_fsm_psl_coverage is
end entity osvvm_fsm_psl_coverage;
architecture sim of osvvm_fsm_psl_coverage is
type t_fsm_state is (IDLE, ADDR, DATA);
signal s_fsm_state : t_fsm_state;
signal s_clk : std_logic := '0';
signal s_reset_n : std_logic := '0';
signal s_state_cover : unsigned(2 downto 0);
shared variable sv_cover : CovPType;
begin
s_clk <= not(s_clk) after 5 ns;
s_reset_n <= '1' after 20 ns;
FsmP : process (s_reset_n, s_clk) is
begin
if (s_reset_n = '0') then
s_fsm_state <= IDLE;
elsif (rising_edge(s_clk)) then
case s_fsm_state is
when IDLE => s_fsm_state <= ADDR;
when ADDR => s_fsm_state <= DATA;
when DATA => s_fsm_state <= IDLE;
when others =>
null;
end case;
end if;
end process FsmP;
-- psl endpoint E_IDLE_ADDR is {s_fsm_state = IDLE; s_fsm_state = ADDR}@s_clk'active;
-- psl endpoint E_ADDR_DATA is {s_fsm_state = ADDR; s_fsm_state = DATA}@s_clk'active;
-- psl endpoint E_DATA_IDLE is {s_fsm_state = DATA; s_fsm_state = IDLE}@s_clk'active;
EndpointRegP : process is
begin
s_state_cover <= (others => '0');
if (E_IDLE_ADDR) then
s_state_cover(0) <= '1';
end if;
if (E_ADDR_DATA) then
s_state_cover(1) <= '1';
end if;
if (E_DATA_IDLE) then
s_state_cover(2) <= '1';
end if;
wait until rising_edge(s_clk);
end process;
sv_cover.AddBins("IDLE->ADDR", GenBin(1));
sv_cover.AddBins("ADDR->DATA", GenBin(2));
sv_cover.AddBins("DATA->IDLE", GenBin(4));
sv_cover.AddBins(ALL_ILLEGAL);
CovCollectP : process is
begin
wait until s_reset_n = '1' and rising_edge(s_clk);
-- we have to wait another cycle because endpoints are delayed by one cycle
-- if we don't wait, we get an illegal BIN hit in second cycle after released reset
wait until rising_edge(s_clk);
loop
wait until rising_edge(s_clk);
sv_cover.ICover(to_integer(s_state_cover));
end loop;
end process CovCollectP;
FinishP : process is
begin
wait until s_clk'active;
if (sv_cover.IsCovered) then
Log("FSM full covered :)", ALWAYS);
sv_cover.SetName("FSM state coverage report");
sv_cover.WriteBin;
stop(0);
end if;
end process FinishP;
-- psl default clock is rising_edge(s_clk);
-- psl IDLE_ADDR : assert always (s_fsm_state = IDLE and s_reset_n = '1') -> next (s_fsm_state = ADDR) abort not(s_reset_n)
-- report "FSM error: IDLE should be followed by ADDR state";
-- psl ADDR_DATA : assert always (s_fsm_state = ADDR and s_reset_n = '1') -> next (s_fsm_state = DATA) abort not(s_reset_n);
-- report "FSM error: ADDR should be followed by DATA state";
-- psl DATA_IDLE : assert always (s_fsm_state = DATA and s_reset_n = '1') -> next (s_fsm_state = IDLE) abort not(s_reset_n);
-- report "FSM error: DATA should be followed by IDLE state";
end architecture sim;
| lgpl-3.0 | ff53c15c4c3ac0b730a8d2ed1cc8dfea | 0.629505 | 3.068416 | false | false | false | false |
yishinli/emc2 | src/hal/drivers/mesa-hostmot2/firmware/src/I20HostMot2.vhd | 1 | 12,109 | library IEEE;
use IEEE.std_logic_1164.all; -- defines std_logic types
use IEEE.std_logic_ARITH.ALL;
use IEEE.std_logic_UNSIGNED.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
--
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
-- http://www.mesanet.com
--
-- This program is is licensed under a disjunctive dual license giving you
-- the choice of one of the two following sets of free software/open source
-- licensing terms:
--
-- * GNU General Public License (GPL), version 2.0 or later
-- * 3-clause BSD License
--
--
-- The GNU GPL License:
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- The 3-clause BSD License:
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- * Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- * Neither the name of Mesa Electronics nor the names of its
-- contributors may be used to endorse or promote products
-- derived from this software without specific prior written
-- permission.
--
--
-- Disclaimer:
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
use work.IDROMParms.all;
use work.NumberOfModules.all;
use work.MaxPinsPerModule.all;
entity HM2_${prefix} is
generic
(
-- Note: all pinout/module count information is derived
-- from the PinDesc and ModuleID which are inserted here
-- by the build system, using data from the .spec file
ThePinDesc: PinDescType := ${pin_desc};
TheModuleID: ModuleIDType := ${module_id};
PWMRefWidth: integer := 13; -- PWM resolution is PWMRefWidth-1 bits
IDROMType: integer := 2;
SepClocks: boolean := true;
OneWS: boolean := true;
UseStepGenPrescaler : boolean := true;
UseIRQLogic: boolean := true;
UseWatchDog: boolean := true;
OffsetToModules: integer := 64;
OffsetToPinDesc: integer := 512;
ClockHigh: integer := ClockHigh20;
ClockLow: integer := ClockLow20;
BoardNameLow : std_Logic_Vector(31 downto 0) := BoardNameMESA;
BoardNameHigh : std_Logic_Vector(31 downto 0) := BoardName5I20;
FPGASize: integer := 200;
FPGAPins: integer := 208;
IOPorts: integer := 3;
IOWidth: integer := 72;
PortWidth: integer := 24;
BusWidth: integer := 32;
AddrWidth: integer := 16;
InstStride0: integer := 4; -- instance stride 0 = 4 bytes = 1 x 32 bit
InstStride1: integer := 64; -- instance stride 1 = 64 bytes = 16 x 32 bit registers
RegStride0: integer := 256; -- register stride 0 = 256 bytes = 64 x 32 bit registers
RegStride1: integer := 4; -- register stride 1 = 4 bytes - 1 x 32 bit
LEDCount: integer := 8
);
port
(
-- bus interface signals --
-- LRD: in std_logic;
-- LWR: in std_logic;
LW_R: in std_logic;
-- ALE: in std_logic;
ADS: in std_logic;
BLAST: in std_logic;
-- WAITOUT: in std_logic;
-- LOCKO: in std_logic;
-- CS0: in std_logic;
-- CS1: in std_logic;
READY: out std_logic;
INT: out std_logic;
-- HOLD: in std_logic;
-- HOLDA: inout std_logic;
-- CCS: out std_logic;
RESET: in std_logic;
-- DISABLECONF: out std_logic;
LAD: inout std_logic_vector (31 downto 0); -- data/address bus
-- LA: in std_logic_vector (8 downto 2); -- non-muxed address bus
LBE: in std_logic_vector (3 downto 0); -- byte enables
IOBITS: inout std_logic_vector (IOWidth -1 downto 0);
LCLK: in std_logic;
SYNCLK: in std_logic;
-- led bits
LEDS: out std_logic_vector(LEDCount -1 downto 0)
);
end HM2_${prefix};
architecture dataflow of HM2_${prefix} is
-- alias SYNCLK: std_logic is LCLK;
-- misc global signals --
signal D: std_logic_vector (BusWidth-1 downto 0); -- internal data bus
signal DPipe: std_logic_vector (BusWidth-1 downto 0); -- read pipeline reg
signal LADPipe: std_logic_vector (BusWidth-1 downto 0); -- write pipeline reg
signal LW_RPipe: std_logic;
signal A: std_logic_vector (15 downto 2);
signal Read: std_logic;
signal ReadTSEn: std_logic;
signal Write: std_logic;
signal Burst: std_logic;
signal BurstCount: std_logic_vector (7 downto 0);
signal NextA: std_logic_vector (15 downto 2);
signal ReadyFF: std_logic;
signal EnableHS: std_logic;
-- CLK multiplier DLL signals
signal FClk: STD_LOGIC; -- high speed clock = 100 MHz
signal Clk0: STD_LOGIC;
signal CLK2X: STD_LOGIC;
-- Extract the number of modules of each type from the ModuleID
constant StepGens: integer := NumberOfModules(TheModuleID,StepGenTag);
constant QCounters: integer := NumberOfModules(TheModuleID,QCountTag);
constant MuxedQCounters: integer := NumberOfModules(TheModuleID,MuxedQCountTag);
constant PWMGens : integer := NumberOfModules(TheModuleID,PWMTag);
constant SPIs: integer := NumberOfModules(TheModuleID,SPITag);
constant BSPIs: integer := NumberOfModules(TheModuleID,BSPITag);
constant SSIs: integer := NumberOfModules(TheModuleID,SSITag);
constant UARTs: integer := NumberOfModules(TheModuleID,UARTRTag);
-- extract the needed Stepgen table width from the max pin# used with a stepgen tag
constant StepGenTableWidth: integer := MaxPinsPerModule(ThePinDesc,StepGenTag);
-- extract how many BSPI CS pins are needed from the max pin# used with a BSPI tag skipping the first 4
constant BSPICSWidth: integer := MaxPinsPerModule(ThePinDesc,BSPITag)-4;
begin
CombinedClock: if (not Sepclocks) and ((PWMGens >0) or UseIRQLogic) generate
CLKDLL_inst : CLKDLL
generic map (
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,4.0,5.0,8.0 or 16.0
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"C080", -- FACTORY JF Values
STARTUP_WAIT => FALSE) -- Delay config DONE until DLL LOCK, TRUE/FALSE
port map (
CLK0 => CLK0, -- 0 degree DLL CLK output
CLKFB =>FClk, -- DLL feedback
CLK2X => CLK2X, -- 2X DLL CLK output
CLKIN => LCLK, -- Clock input (from IBUFG, BUFG or DLL)
RST => '0' -- DLL asynchronous reset input
);
BUFG_inst : BUFG
port map (
O => FClk, -- Clock buffer output
I => CLK2X -- Clock buffer input
);
end generate;
SeparateClock: if Sepclocks and ((PWMGens >0) or UseIRQLogic) generate
CLKDLL_inst : CLKDLL
generic map (
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,4.0,5.0,8.0 or 16.0
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"C080", -- FACTORY JF Values
STARTUP_WAIT => FALSE) -- Delay config DONE until DLL LOCK, TRUE/FALSE
port map (
CLK0 => CLK0, -- 0 degree DLL CLK output
CLKFB =>FClk, -- DLL feedback
CLK2X => CLK2X, -- 2X DLL CLK output
CLKIN => SYNCLK, -- Clock input (from IBUFG, BUFG or DLL)
RST => '0' -- DLL asynchronous reset input
);
BUFG_inst : BUFG
port map (
O => FClk, -- Clock buffer output
I => CLK2X -- Clock buffer input
);
end generate;
ahostmot2: entity HostMot2
generic map (
thepindesc => ThePinDesc,
themoduleid => TheModuleID,
stepgens => StepGens,
qcounters => QCounters,
muxedqcounters => MuxedQCounters,
pwmgens => PWMGens,
spis => SPIs,
bspis => BSPIs,
ssis => SSIs,
uarts => UARTs,
pwmrefwidth => PWMRefWidth,
stepgentablewidth => StepGenTableWidth,
bspicswidth => BSPICSWidth,
idromtype => IDROMType,
sepclocks => SepClocks,
onews => OneWS,
usestepgenprescaler => UseStepGenPrescaler,
useirqlogic => UseIRQLogic,
usewatchdog => UseWatchDog,
offsettomodules => OffsetToModules,
offsettopindesc => OffsetToPinDesc,
clockhigh => ClockHigh,
clocklow => ClockLow,
boardnamelow => BoardNameLow,
boardnamehigh => BoardNameHigh,
fpgasize => FPGASize,
fpgapins => FPGAPins,
ioports => IOPorts,
iowidth => IOWidth,
portwidth => PortWidth,
buswidth => BusWidth,
addrwidth => AddrWidth,
inststride0 => InstStride0,
inststride1 => InstStride1,
regstride0 => RegStride0,
regstride1 => RegStride1,
ledcount => LEDCount
)
port map (
ibus => LADPipe,
obus => D,
addr => NextA,
read => Read,
write => Write,
clklow => LCLK,
clkhigh => FClk,
int => INT,
iobits => IOBITS,
leds => LEDS
);
LADDrivers: process (DPipe,ReadTSEn,LCLK)
begin
if rising_edge(LCLK) then
DPipe <= D;
LADPipe <= LAD;
end if;
if ReadTSEn ='1' then
LAD <= DPipe;
else
LAD <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
end if;
end process LADDrivers;
BusCycleGen: process (LCLK,ADS, LAD, ReadyFF, A, Burst, LW_RPipe) -- added 1 wait state (read/write)
begin
if rising_edge(LCLK) then
A <= NextA; -- always update our latched address
if ADS = '0' then -- if *ADS then latch address & indicate start of burst
Burst <= '1';
end if;
if BLAST = '0' and ReadyFF= '1' then -- end of burst
Burst <= '0';
end if;
if OneWS then
if Burst = '1' then
ReadyFF <= not ReadyFF; -- just one wait state so toggle ReadyFF
else
ReadyFF <= '0'; -- idle not ready
end if;
else
ReadyFF <= '1'; -- always ready if OneWS not used
end if;
LW_RPipe <= LW_R;
end if; -- lclk
if ADS = '0' then -- NextA is combinatorial next address
NextA <= LAD(15 downto 2); -- we need this for address lookahead for block RAM
else
if ReadyFF = '1' then
NextA <= A+1;
else
NextA <= A;
end if;
end if;
Write <= Burst and LW_RPipe and ReadyFF; -- A write is any time during burst when LW_R is high and ReadyFF is high
-- Note that write writes the data from the LADPipe register to the destination
ReadTSEn <= Burst and not LW_RPipe; -- ReadTSEn is any time during burst when LW_R is low = tri state enable on DPipe output
Read <= Burst and not LW_RPipe and not ReadyFF; -- A read is any time during burst when LW_R is low and ReadyFF is low = internal read data enable to DPipe input
READY <= not ReadyFF; -- note: target only!
end process BusCycleGen;
-- DoHandshake: process (HOLD,EnableHS)
-- begin
-- if EnableHS = '1' then
-- HOLDAHOLD;
-- else
-- HOLDA'Z';
-- end if;
-- end process DoHandShake;
end dataflow;
| lgpl-2.1 | ea6b90d5cb42ebc04a8f663c8727fcb1 | 0.665538 | 3.295863 | false | false | false | false |
hoglet67/CoPro6502 | src/T80/T80.vhd | 1 | 32,532 | -- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
-- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
--
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0208 : First complete release
--
-- 0210 : Fixed wait and halt
--
-- 0211 : Fixed Refresh addition and IM 1
--
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
--
-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
--
-- 0235 : Added clock enable and IM 2 fix by Mike Johnson
--
-- 0237 : Changed 8080 I/O address output, added IntE output
--
-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
--
-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
--
-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
--
-- 0247 : Fixed bus req/ack cycle
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80 is
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
IORQ : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DInst : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
MC : out std_logic_vector(2 downto 0);
TS : out std_logic_vector(2 downto 0);
IntCycle_n : out std_logic;
IntE : out std_logic;
Stop : out std_logic
);
end T80;
architecture rtl of T80 is
-- Registers
signal ACC, F : std_logic_vector(7 downto 0);
signal Ap, Fp : std_logic_vector(7 downto 0);
signal I : std_logic_vector(7 downto 0);
signal R : unsigned(7 downto 0);
signal SP, PC : unsigned(15 downto 0);
signal RegDIH : std_logic_vector(7 downto 0);
signal RegDIL : std_logic_vector(7 downto 0);
signal RegBusA : std_logic_vector(15 downto 0);
signal RegBusB : std_logic_vector(15 downto 0);
signal RegBusC : std_logic_vector(15 downto 0);
signal RegAddrA_r : std_logic_vector(2 downto 0);
signal RegAddrA : std_logic_vector(2 downto 0);
signal RegAddrB_r : std_logic_vector(2 downto 0);
signal RegAddrB : std_logic_vector(2 downto 0);
signal RegAddrC : std_logic_vector(2 downto 0);
signal RegWEH : std_logic;
signal RegWEL : std_logic;
signal Alternate : std_logic;
-- Help Registers
signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register
signal IR : std_logic_vector(7 downto 0); -- Instruction register
signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector
signal RegBusA_r : std_logic_vector(15 downto 0);
signal ID16 : signed(15 downto 0);
signal Save_Mux : std_logic_vector(7 downto 0);
signal TState : unsigned(2 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal IntE_FF1 : std_logic;
signal IntE_FF2 : std_logic;
signal Halt_FF : std_logic;
signal BusReq_s : std_logic;
signal BusAck : std_logic;
signal ClkEn : std_logic;
signal NMI_s : std_logic;
signal INT_s : std_logic;
signal IStatus : std_logic_vector(1 downto 0);
signal DI_Reg : std_logic_vector(7 downto 0);
signal T_Res : std_logic;
signal XY_State : std_logic_vector(1 downto 0);
signal Pre_XY_F_M : std_logic_vector(2 downto 0);
signal NextIs_XY_Fetch : std_logic;
signal XY_Ind : std_logic;
signal No_BTR : std_logic;
signal BTR_r : std_logic;
signal Auto_Wait : std_logic;
signal Auto_Wait_t1 : std_logic;
signal Auto_Wait_t2 : std_logic;
signal IncDecZ : std_logic;
-- ALU signals
signal BusB : std_logic_vector(7 downto 0);
signal BusA : std_logic_vector(7 downto 0);
signal ALU_Q : std_logic_vector(7 downto 0);
signal F_Out : std_logic_vector(7 downto 0);
-- Registered micro code outputs
signal Read_To_Reg_r : std_logic_vector(4 downto 0);
signal Arith16_r : std_logic;
signal Z16_r : std_logic;
signal ALU_Op_r : std_logic_vector(3 downto 0);
signal Save_ALU_r : std_logic;
signal PreserveC_r : std_logic;
signal MCycles : std_logic_vector(2 downto 0);
-- Micro code outputs
signal MCycles_d : std_logic_vector(2 downto 0);
signal TStates : std_logic_vector(2 downto 0);
signal IntCycle : std_logic;
signal NMICycle : std_logic;
signal Inc_PC : std_logic;
signal Inc_WZ : std_logic;
signal IncDec_16 : std_logic_vector(3 downto 0);
signal Prefix : std_logic_vector(1 downto 0);
signal Read_To_Acc : std_logic;
signal Read_To_Reg : std_logic;
signal Set_BusB_To : std_logic_vector(3 downto 0);
signal Set_BusA_To : std_logic_vector(3 downto 0);
signal ALU_Op : std_logic_vector(3 downto 0);
signal Save_ALU : std_logic;
signal PreserveC : std_logic;
signal Arith16 : std_logic;
signal Set_Addr_To : std_logic_vector(2 downto 0);
signal Jump : std_logic;
signal JumpE : std_logic;
signal JumpXY : std_logic;
signal Call : std_logic;
signal RstP : std_logic;
signal LDZ : std_logic;
signal LDW : std_logic;
signal LDSPHL : std_logic;
signal IORQ_i : std_logic;
signal Special_LD : std_logic_vector(2 downto 0);
signal ExchangeDH : std_logic;
signal ExchangeRp : std_logic;
signal ExchangeAF : std_logic;
signal ExchangeRS : std_logic;
signal I_DJNZ : std_logic;
signal I_CPL : std_logic;
signal I_CCF : std_logic;
signal I_SCF : std_logic;
signal I_RETN : std_logic;
signal I_BT : std_logic;
signal I_BC : std_logic;
signal I_BTR : std_logic;
signal I_RLD : std_logic;
signal I_RRD : std_logic;
signal I_INRC : std_logic;
signal SetDI : std_logic;
signal SetEI : std_logic;
signal IMode : std_logic_vector(1 downto 0);
signal Halt : std_logic;
signal XYbit_undoc : std_logic;
begin
mcode : T80_MCode
generic map(
Mode => Mode,
Flag_C => Flag_C,
Flag_N => Flag_N,
Flag_P => Flag_P,
Flag_X => Flag_X,
Flag_H => Flag_H,
Flag_Y => Flag_Y,
Flag_Z => Flag_Z,
Flag_S => Flag_S)
port map(
IR => IR,
ISet => ISet,
MCycle => MCycle,
F => F,
NMICycle => NMICycle,
IntCycle => IntCycle,
XY_State => XY_State,
MCycles => MCycles_d,
TStates => TStates,
Prefix => Prefix,
Inc_PC => Inc_PC,
Inc_WZ => Inc_WZ,
IncDec_16 => IncDec_16,
Read_To_Acc => Read_To_Acc,
Read_To_Reg => Read_To_Reg,
Set_BusB_To => Set_BusB_To,
Set_BusA_To => Set_BusA_To,
ALU_Op => ALU_Op,
Save_ALU => Save_ALU,
PreserveC => PreserveC,
Arith16 => Arith16,
Set_Addr_To => Set_Addr_To,
IORQ => IORQ_i,
Jump => Jump,
JumpE => JumpE,
JumpXY => JumpXY,
Call => Call,
RstP => RstP,
LDZ => LDZ,
LDW => LDW,
LDSPHL => LDSPHL,
Special_LD => Special_LD,
ExchangeDH => ExchangeDH,
ExchangeRp => ExchangeRp,
ExchangeAF => ExchangeAF,
ExchangeRS => ExchangeRS,
I_DJNZ => I_DJNZ,
I_CPL => I_CPL,
I_CCF => I_CCF,
I_SCF => I_SCF,
I_RETN => I_RETN,
I_BT => I_BT,
I_BC => I_BC,
I_BTR => I_BTR,
I_RLD => I_RLD,
I_RRD => I_RRD,
I_INRC => I_INRC,
SetDI => SetDI,
SetEI => SetEI,
IMode => IMode,
Halt => Halt,
NoRead => NoRead,
Write => Write,
XYbit_undoc => XYbit_undoc);
alu : T80_ALU
generic map(
Mode => Mode,
Flag_C => Flag_C,
Flag_N => Flag_N,
Flag_P => Flag_P,
Flag_X => Flag_X,
Flag_H => Flag_H,
Flag_Y => Flag_Y,
Flag_Z => Flag_Z,
Flag_S => Flag_S)
port map(
Arith16 => Arith16_r,
Z16 => Z16_r,
ALU_Op => ALU_Op_r,
IR => IR(5 downto 0),
ISet => ISet,
BusA => BusA,
BusB => BusB,
F_In => F,
Q => ALU_Q,
F_Out => F_Out);
ClkEn <= CEN and not BusAck;
T_Res <= '1' when TState = unsigned(TStates) else '0';
NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
((Set_Addr_To = aXY) or
(MCycle = "001" and IR = "11001011") or
(MCycle = "001" and IR = "00110110")) else '0';
Save_Mux <= BusB when ExchangeRp = '1' else
DI_Reg when Save_ALU_r = '0' else
ALU_Q;
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
PC <= (others => '0'); -- Program Counter
A <= (others => '0');
TmpAddr <= (others => '0');
IR <= "00000000";
ISet <= "00";
XY_State <= "00";
IStatus <= "00";
MCycles <= "000";
DO <= "00000000";
ACC <= (others => '1');
F <= (others => '1');
Ap <= (others => '1');
Fp <= (others => '1');
I <= (others => '0');
R <= (others => '0');
SP <= (others => '1');
Alternate <= '0';
Read_To_Reg_r <= "00000";
F <= (others => '1');
Arith16_r <= '0';
BTR_r <= '0';
Z16_r <= '0';
ALU_Op_r <= "0000";
Save_ALU_r <= '0';
PreserveC_r <= '0';
XY_Ind <= '0';
elsif CLK_n'event and CLK_n = '1' then
if ClkEn = '1' then
ALU_Op_r <= "0000";
Save_ALU_r <= '0';
Read_To_Reg_r <= "00000";
MCycles <= MCycles_d;
if Mode = 3 then
IStatus <= "10";
elsif IMode /= "11" then
IStatus <= IMode;
end if;
Arith16_r <= Arith16;
PreserveC_r <= PreserveC;
if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
Z16_r <= '1';
else
Z16_r <= '0';
end if;
if MCycle = "001" and TState(2) = '0' then
-- MCycle = 1 and TState = 1, 2, or 3
if TState = 2 and Wait_n = '1' then
if Mode < 2 then
A(7 downto 0) <= std_logic_vector(R);
A(15 downto 8) <= I;
R(6 downto 0) <= R(6 downto 0) + 1;
end if;
if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
PC <= PC + 1;
end if;
if IntCycle = '1' and IStatus = "01" then
IR <= "11111111";
elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
IR <= "00000000";
else
IR <= DInst;
end if;
ISet <= "00";
if Prefix /= "00" then
if Prefix = "11" then
if IR(5) = '1' then
XY_State <= "10";
else
XY_State <= "01";
end if;
else
if Prefix = "10" then
XY_State <= "00";
XY_Ind <= '0';
end if;
ISet <= Prefix;
end if;
else
XY_State <= "00";
XY_Ind <= '0';
end if;
end if;
else
-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
if MCycle = "110" then
XY_Ind <= '1';
if Prefix = "01" then
ISet <= "01";
end if;
end if;
if T_Res = '1' then
BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
if Jump = '1' then
A(15 downto 8) <= DI_Reg;
A(7 downto 0) <= TmpAddr(7 downto 0);
PC(15 downto 8) <= unsigned(DI_Reg);
PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
elsif JumpXY = '1' then
A <= RegBusC;
PC <= unsigned(RegBusC);
elsif Call = '1' or RstP = '1' then
A <= TmpAddr;
PC <= unsigned(TmpAddr);
elsif MCycle = MCycles and NMICycle = '1' then
A <= "0000000001100110";
PC <= "0000000001100110";
elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
A(15 downto 8) <= I;
A(7 downto 0) <= TmpAddr(7 downto 0);
PC(15 downto 8) <= unsigned(I);
PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
else
case Set_Addr_To is
when aXY =>
if XY_State = "00" then
A <= RegBusC;
else
if NextIs_XY_Fetch = '1' then
A <= std_logic_vector(PC);
else
A <= TmpAddr;
end if;
end if;
when aIOA =>
if Mode = 3 then
-- Memory map I/O on GBZ80
A(15 downto 8) <= (others => '1');
elsif Mode = 2 then
-- Duplicate I/O address on 8080
A(15 downto 8) <= DI_Reg;
else
A(15 downto 8) <= ACC;
end if;
A(7 downto 0) <= DI_Reg;
when aSP =>
A <= std_logic_vector(SP);
when aBC =>
if Mode = 3 and IORQ_i = '1' then
-- Memory map I/O on GBZ80
A(15 downto 8) <= (others => '1');
A(7 downto 0) <= RegBusC(7 downto 0);
else
A <= RegBusC;
end if;
when aDE =>
A <= RegBusC;
when aZI =>
if Inc_WZ = '1' then
A <= std_logic_vector(unsigned(TmpAddr) + 1);
else
A(15 downto 8) <= DI_Reg;
A(7 downto 0) <= TmpAddr(7 downto 0);
end if;
when others =>
A <= std_logic_vector(PC);
end case;
end if;
Save_ALU_r <= Save_ALU;
ALU_Op_r <= ALU_Op;
if I_CPL = '1' then
-- CPL
ACC <= not ACC;
F(Flag_Y) <= not ACC(5);
F(Flag_H) <= '1';
F(Flag_X) <= not ACC(3);
F(Flag_N) <= '1';
end if;
if I_CCF = '1' then
-- CCF
F(Flag_C) <= not F(Flag_C);
F(Flag_Y) <= ACC(5);
F(Flag_H) <= F(Flag_C);
F(Flag_X) <= ACC(3);
F(Flag_N) <= '0';
end if;
if I_SCF = '1' then
-- SCF
F(Flag_C) <= '1';
F(Flag_Y) <= ACC(5);
F(Flag_H) <= '0';
F(Flag_X) <= ACC(3);
F(Flag_N) <= '0';
end if;
end if;
if TState = 2 and Wait_n = '1' then
if ISet = "01" and MCycle = "111" then
IR <= DInst;
end if;
if JumpE = '1' then
PC <= unsigned(signed(PC) + signed(DI_Reg));
elsif Inc_PC = '1' then
PC <= PC + 1;
end if;
if BTR_r = '1' then
PC <= PC - 2;
end if;
if RstP = '1' then
TmpAddr <= (others =>'0');
TmpAddr(5 downto 3) <= IR(5 downto 3);
end if;
end if;
if TState = 3 and MCycle = "110" then
TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
end if;
if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
if IncDec_16(2 downto 0) = "111" then
if IncDec_16(3) = '1' then
SP <= SP - 1;
else
SP <= SP + 1;
end if;
end if;
end if;
if LDSPHL = '1' then
SP <= unsigned(RegBusC);
end if;
if ExchangeAF = '1' then
Ap <= ACC;
ACC <= Ap;
Fp <= F;
F <= Fp;
end if;
if ExchangeRS = '1' then
Alternate <= not Alternate;
end if;
end if;
if TState = 3 then
if LDZ = '1' then
TmpAddr(7 downto 0) <= DI_Reg;
end if;
if LDW = '1' then
TmpAddr(15 downto 8) <= DI_Reg;
end if;
if Special_LD(2) = '1' then
case Special_LD(1 downto 0) is
when "00" =>
ACC <= I;
F(Flag_P) <= IntE_FF2;
if I = X"00" then
F(Flag_Z) <= '1';
else
F(Flag_Z) <= '0';
end if;
F(Flag_S) <= I(7);
when "01" =>
ACC <= std_logic_vector(R);
F(Flag_P) <= IntE_FF2;
if R = X"00" then
F(Flag_Z) <= '1';
else
F(Flag_Z) <= '0';
end if;
F(Flag_S) <= R(7);
when "10" =>
I <= ACC;
when others =>
R <= unsigned(ACC);
end case;
end if;
end if;
if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
if Mode = 3 then
F(6) <= F_Out(6);
F(5) <= F_Out(5);
F(7) <= F_Out(7);
if PreserveC_r = '0' then
F(4) <= F_Out(4);
end if;
else
F(7 downto 1) <= F_Out(7 downto 1);
if PreserveC_r = '0' then
F(Flag_C) <= F_Out(0);
end if;
end if;
end if;
if T_Res = '1' and I_INRC = '1' then
F(Flag_H) <= '0';
F(Flag_N) <= '0';
if DI_Reg(7 downto 0) = "00000000" then
F(Flag_Z) <= '1';
else
F(Flag_Z) <= '0';
end if;
F(Flag_S) <= DI_Reg(7);
F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
end if;
if TState = 1 then
DO <= BusB;
if I_RLD = '1' then
DO(3 downto 0) <= BusA(3 downto 0);
DO(7 downto 4) <= BusB(3 downto 0);
end if;
if I_RRD = '1' then
DO(3 downto 0) <= BusB(7 downto 4);
DO(7 downto 4) <= BusA(3 downto 0);
end if;
end if;
if T_Res = '1' then
Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
Read_To_Reg_r(4) <= Read_To_Reg;
if Read_To_Acc = '1' then
Read_To_Reg_r(3 downto 0) <= "0111";
Read_To_Reg_r(4) <= '1';
end if;
end if;
if TState = 1 and I_BT = '1' then
F(Flag_X) <= ALU_Q(3);
F(Flag_Y) <= ALU_Q(1);
F(Flag_H) <= '0';
F(Flag_N) <= '0';
end if;
if I_BC = '1' or I_BT = '1' then
F(Flag_P) <= IncDecZ;
end if;
if (TState = 1 and Save_ALU_r = '0') or
(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
case Read_To_Reg_r is
when "10111" =>
ACC <= Save_Mux;
when "10110" =>
DO <= Save_Mux;
when "11000" =>
SP(7 downto 0) <= unsigned(Save_Mux);
when "11001" =>
SP(15 downto 8) <= unsigned(Save_Mux);
when "11011" =>
F <= Save_Mux;
when others =>
end case;
if XYbit_undoc='1' then
DO <= ALU_Q;
end if;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------
--
-- BC('), DE('), HL('), IX and IY
--
---------------------------------------------------------------------------
process (CLK_n)
begin
if CLK_n'event and CLK_n = '1' then
if ClkEn = '1' then
-- Bus A / Write
RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
RegAddrA_r <= XY_State(1) & "11";
end if;
-- Bus B
RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
RegAddrB_r <= XY_State(1) & "11";
end if;
-- Address from register
RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
-- Jump (HL), LD SP,HL
if (JumpXY = '1' or LDSPHL = '1') then
RegAddrC <= Alternate & "10";
end if;
if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
RegAddrC <= XY_State(1) & "11";
end if;
if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
IncDecZ <= F_Out(Flag_Z);
end if;
if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
if ID16 = 0 then
IncDecZ <= '0';
else
IncDecZ <= '1';
end if;
end if;
RegBusA_r <= RegBusA;
end if;
end if;
end process;
RegAddrA <=
-- 16 bit increment/decrement
Alternate & IncDec_16(1 downto 0) when (TState = 2 or
(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
XY_State(1) & "11" when (TState = 2 or
(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
-- EX HL,DL
Alternate & "10" when ExchangeDH = '1' and TState = 3 else
Alternate & "01" when ExchangeDH = '1' and TState = 4 else
-- Bus A / Write
RegAddrA_r;
RegAddrB <=
-- EX HL,DL
Alternate & "01" when ExchangeDH = '1' and TState = 3 else
-- Bus B
RegAddrB_r;
ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
signed(RegBusA) + 1;
process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
begin
RegWEH <= '0';
RegWEL <= '0';
if (TState = 1 and Save_ALU_r = '0') or
(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
case Read_To_Reg_r is
when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
RegWEH <= not Read_To_Reg_r(0);
RegWEL <= Read_To_Reg_r(0);
when others =>
end case;
end if;
if ExchangeDH = '1' and (TState = 3 or TState = 4) then
RegWEH <= '1';
RegWEL <= '1';
end if;
if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
case IncDec_16(1 downto 0) is
when "00" | "01" | "10" =>
RegWEH <= '1';
RegWEL <= '1';
when others =>
end case;
end if;
end process;
process (Save_Mux, RegBusB, RegBusA_r, ID16,
ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
begin
RegDIH <= Save_Mux;
RegDIL <= Save_Mux;
if ExchangeDH = '1' and TState = 3 then
RegDIH <= RegBusB(15 downto 8);
RegDIL <= RegBusB(7 downto 0);
end if;
if ExchangeDH = '1' and TState = 4 then
RegDIH <= RegBusA_r(15 downto 8);
RegDIL <= RegBusA_r(7 downto 0);
end if;
if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
RegDIH <= std_logic_vector(ID16(15 downto 8));
RegDIL <= std_logic_vector(ID16(7 downto 0));
end if;
end process;
Regs : T80_Reg
port map(
Clk => CLK_n,
CEN => ClkEn,
WEH => RegWEH,
WEL => RegWEL,
AddrA => RegAddrA,
AddrB => RegAddrB,
AddrC => RegAddrC,
DIH => RegDIH,
DIL => RegDIL,
DOAH => RegBusA(15 downto 8),
DOAL => RegBusA(7 downto 0),
DOBH => RegBusB(15 downto 8),
DOBL => RegBusB(7 downto 0),
DOCH => RegBusC(15 downto 8),
DOCL => RegBusC(7 downto 0));
---------------------------------------------------------------------------
--
-- Buses
--
---------------------------------------------------------------------------
process (CLK_n)
begin
if CLK_n'event and CLK_n = '1' then
if ClkEn = '1' then
case Set_BusB_To is
when "0111" =>
BusB <= ACC;
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
if Set_BusB_To(0) = '1' then
BusB <= RegBusB(7 downto 0);
else
BusB <= RegBusB(15 downto 8);
end if;
when "0110" =>
BusB <= DI_Reg;
when "1000" =>
BusB <= std_logic_vector(SP(7 downto 0));
when "1001" =>
BusB <= std_logic_vector(SP(15 downto 8));
when "1010" =>
BusB <= "00000001";
when "1011" =>
BusB <= F;
when "1100" =>
BusB <= std_logic_vector(PC(7 downto 0));
when "1101" =>
BusB <= std_logic_vector(PC(15 downto 8));
when "1110" =>
BusB <= "00000000";
when others =>
BusB <= "--------";
end case;
case Set_BusA_To is
when "0111" =>
BusA <= ACC;
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
if Set_BusA_To(0) = '1' then
BusA <= RegBusA(7 downto 0);
else
BusA <= RegBusA(15 downto 8);
end if;
when "0110" =>
BusA <= DI_Reg;
when "1000" =>
BusA <= std_logic_vector(SP(7 downto 0));
when "1001" =>
BusA <= std_logic_vector(SP(15 downto 8));
when "1010" =>
BusA <= "00000000";
when others =>
BusA <= "--------";
end case;
if XYbit_undoc='1' then
BusA <= DI_Reg;
BusB <= DI_Reg;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------
--
-- Generate external control signals
--
---------------------------------------------------------------------------
process (RESET_n,CLK_n)
begin
if RESET_n = '0' then
RFSH_n <= '1';
elsif CLK_n'event and CLK_n = '1' then
if CEN = '1' then
if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then
RFSH_n <= '0';
else
RFSH_n <= '1';
end if;
end if;
end if;
end process;
MC <= std_logic_vector(MCycle);
TS <= std_logic_vector(TState);
DI_Reg <= DI;
HALT_n <= not Halt_FF;
BUSAK_n <= not BusAck;
IntCycle_n <= not IntCycle;
IntE <= IntE_FF1;
IORQ <= IORQ_i;
Stop <= I_DJNZ;
-------------------------------------------------------------------------
--
-- Syncronise inputs
--
-------------------------------------------------------------------------
process (RESET_n, CLK_n)
variable OldNMI_n : std_logic;
begin
if RESET_n = '0' then
BusReq_s <= '0';
INT_s <= '0';
NMI_s <= '0';
OldNMI_n := '0';
elsif CLK_n'event and CLK_n = '1' then
if CEN = '1' then
BusReq_s <= not BUSRQ_n;
INT_s <= not INT_n;
if NMICycle = '1' then
NMI_s <= '0';
elsif NMI_n = '0' and OldNMI_n = '1' then
NMI_s <= '1';
end if;
OldNMI_n := NMI_n;
end if;
end if;
end process;
-------------------------------------------------------------------------
--
-- Main state machine
--
-------------------------------------------------------------------------
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
MCycle <= "001";
TState <= "000";
Pre_XY_F_M <= "000";
Halt_FF <= '0';
BusAck <= '0';
NMICycle <= '0';
IntCycle <= '0';
IntE_FF1 <= '0';
IntE_FF2 <= '0';
No_BTR <= '0';
Auto_Wait_t1 <= '0';
Auto_Wait_t2 <= '0';
M1_n <= '1';
elsif CLK_n'event and CLK_n = '1' then
if CEN = '1' then
Auto_Wait_t1 <= Auto_Wait;
Auto_Wait_t2 <= Auto_Wait_t1;
No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
(I_BTR and (not IR(4) or F(Flag_Z)));
if TState = 2 then
if SetEI = '1' then
IntE_FF1 <= '1';
IntE_FF2 <= '1';
end if;
if I_RETN = '1' then
IntE_FF1 <= IntE_FF2;
end if;
end if;
if TState = 3 then
if SetDI = '1' then
IntE_FF1 <= '0';
IntE_FF2 <= '0';
end if;
end if;
if IntCycle = '1' or NMICycle = '1' then
Halt_FF <= '0';
end if;
if MCycle = "001" and TState = 2 and Wait_n = '1' then
M1_n <= '1';
end if;
if BusReq_s = '1' and BusAck = '1' then
else
BusAck <= '0';
if TState = 2 and Wait_n = '0' then
elsif T_Res = '1' then
if Halt = '1' then
Halt_FF <= '1';
end if;
if BusReq_s = '1' then
BusAck <= '1';
else
TState <= "001";
if NextIs_XY_Fetch = '1' then
MCycle <= "110";
Pre_XY_F_M <= MCycle;
if IR = "00110110" and Mode = 0 then
Pre_XY_F_M <= "010";
end if;
elsif (MCycle = "111") or
(MCycle = "110" and Mode = 1 and ISet /= "01") then
MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
elsif (MCycle = MCycles) or
No_BTR = '1' or
(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
M1_n <= '0';
MCycle <= "001";
IntCycle <= '0';
NMICycle <= '0';
if NMI_s = '1' and Prefix = "00" then
NMICycle <= '1';
IntE_FF1 <= '0';
elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
IntCycle <= '1';
IntE_FF1 <= '0';
IntE_FF2 <= '0';
end if;
else
MCycle <= std_logic_vector(unsigned(MCycle) + 1);
end if;
end if;
else
if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
TState <= TState + 1;
end if;
end if;
end if;
if TState = 0 then
M1_n <= '0';
end if;
end if;
end if;
end process;
process (IntCycle, NMICycle, MCycle)
begin
Auto_Wait <= '0';
if IntCycle = '1' or NMICycle = '1' then
if MCycle = "001" then
Auto_Wait <= '1';
end if;
end if;
end process;
end;
| gpl-3.0 | 5f1722fd9efcdf4c0a57cc36e2fa3266 | 0.488965 | 3.074277 | false | false | false | false |
richjyoung/lfsr-package | test/LFSR_TB/pulse_tb.vhd | 1 | 3,155 | library IEEE, JUNIT_TB, LFSR, STD;
use IEEE.std_logic_1164.all;
use JUNIT_TB.junit.all;
use LFSR.lfsr_components.all;
use STD.textio.all;
--------------------------------------------------------------------------------
entity pulse_tb is
end pulse_tb;
--------------------------------------------------------------------------------
architecture tb of pulse_tb is
constant C_PERIOD : time := 10 ns;
constant C_EXPECTED : natural := 7;
constant C_EXPECTED_TIME : time := C_PERIOD * C_EXPECTED;
signal CLK : std_logic;
signal RESET : std_logic;
signal P : std_logic;
begin
stim_proc: process
variable STARTED : time;
variable FINISHED : time;
variable OUTLINE : line;
variable RUNTIME : real;
file JFILE : text open write_mode is "junit.xml";
variable JLINE : line;
begin
write(OUTLINE, string'("[+] Asserting Reset"));
writeline(OUTPUT, OUTLINE);
RESET <= '1';
wait for C_PERIOD * 10;
write(OUTLINE, string'("[+] Releasing Reset"));
writeline(OUTPUT, OUTLINE);
RESET <= '0';
wait until rising_edge(P);
write(OUTLINE, string'("[+] ("));
write(OUTLINE, now);
write(OUTLINE, string'(") First rising edge"));
writeline(OUTPUT, OUTLINE);
STARTED := now;
wait until rising_edge(P);
write(OUTLINE, string'("[+] ("));
write(OUTLINE, now);
write(OUTLINE, string'(") Second rising edge"));
writeline(OUTPUT, OUTLINE);
FINISHED := now;
write(OUTLINE, string'("[+] ("));
write(OUTLINE, FINISHED-STARTED);
write(OUTLINE, string'(") Measured duration"));
writeline(OUTPUT, OUTLINE);
junit_xml_declaration(JFILE);
if (FINISHED-STARTED) /= C_EXPECTED_TIME then
assert false report "[FAIL] Incorrect pulse period" severity failure;
else
assert false report "[PASS]" severity note;
RUNTIME := real((FINISHED-STARTED)/(1 fs)) / 1.0e15;
--RUNTIME := 0.000000070;
write(OUTLINE, RUNTIME);
writeline(OUTPUT, OUTLINE);
junit_start_testsuites(JFILE, "main", "Main", 1, 0, RUNTIME);
junit_start_testsuite(JFILE, "pulse_tb", "Pulse TB", 1, 0, RUNTIME);
junit_testcase(JFILE, "period", "Period", RUNTIME);
junit_end_testsuite(JFILE);
junit_end_testsuites(JFILE);
end if;
wait for C_PERIOD * 10;
file_close(JFILE);
assert false report "SIMULATION FINISHED" severity failure;
wait;
end process stim_proc;
clk_proc: process
begin
CLK <= '0';
wait for C_PERIOD / 2;
CLK <= '1';
wait for C_PERIOD / 2;
end process clk_proc;
U_UUT: pulse
generic map (
G_lfsr_width => 3,
G_period => 7
)
port map (
CLK => CLK,
RESET => RESET,
PULSE => P
);
end tb; | mit | 5212f0283711ac1a05b06da696248898 | 0.504279 | 4.162269 | false | false | false | false |
pwsoft/fpga_examples | rtl/ttl/ttl_7420.vhd | 1 | 2,020 | -- -----------------------------------------------------------------------
--
-- Syntiac VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2018 by Peter Wendrich ([email protected])
-- http://www.syntiac.com
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
-- Dual 4-input NAND gate
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.ttl_pkg.all;
-- -----------------------------------------------------------------------
entity ttl_7420 is
generic (
latency : integer := 1
);
port (
emuclk : in std_logic;
p1 : in ttl_t;
p2 : in ttl_t;
p4 : in ttl_t;
p5 : in ttl_t;
p6 : out ttl_t;
p9 : in ttl_t;
p10 : in ttl_t;
p12 : in ttl_t;
p13 : in ttl_t;
p8 : out ttl_t
);
end entity;
architecture rtl of ttl_7420 is
signal p6_loc : ttl_t;
signal p8_loc : ttl_t;
begin
p6_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p6_loc, q => p6);
p8_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p8_loc, q => p8);
p6_loc <= not(p1 and p2 and p4 and p5);
p8_loc <= not(p9 and p10 and p12 and p13);
end architecture;
| lgpl-2.1 | 03d5f552c35b35ed28754dd80a38817c | 0.55297 | 3.49481 | false | false | false | false |
hoglet67/CoPro6502 | src/CPU65C02/fsm_execution_unit.vhd | 1 | 236,027 | -- VHDL Entity r65c02_tc.fsm_execution_unit.symbol
--
-- Created:
-- by - eda.UNKNOWN (ENTW-7HPZ200)
-- at - 15:56:20 27.08.2018
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
entity fsm_execution_unit is
port(
adr_nxt_pc_i : in std_logic_vector (15 downto 0);
adr_pc_i : in std_logic_vector (15 downto 0);
adr_sp_i : in std_logic_vector (15 downto 0);
clk_clk_i : in std_logic;
d_alu_i : in std_logic_vector ( 7 downto 0 );
d_alu_prio_i : in std_logic_vector (7 downto 0);
d_i : in std_logic_vector ( 7 downto 0 );
d_regs_out_i : in std_logic_vector ( 7 downto 0 );
irq_n_i : in std_logic;
nmi_i : in std_logic;
q_a_i : in std_logic_vector ( 7 downto 0 );
q_x_i : in std_logic_vector ( 7 downto 0 );
q_y_i : in std_logic_vector ( 7 downto 0 );
rdy_i : in std_logic;
reg_0flag_i : in std_logic;
reg_1flag_i : in std_logic;
reg_7flag_i : in std_logic;
rst_rst_n_i : in std_logic;
so_n_i : in std_logic;
a_o : out std_logic_vector (15 downto 0);
adr_o : out std_logic_vector (15 downto 0);
ch_a_o : out std_logic_vector ( 7 downto 0 );
ch_b_o : out std_logic_vector ( 7 downto 0 );
d_o : out std_logic_vector ( 7 downto 0 );
d_regs_in_o : out std_logic_vector ( 7 downto 0 );
ld_o : out std_logic_vector ( 1 downto 0 );
ld_pc_o : out std_logic;
ld_sp_o : out std_logic;
load_regs_o : out std_logic;
offset_o : out std_logic_vector ( 15 downto 0 );
rd_o : out std_logic;
rst_nmi_o : out std_logic;
sel_pc_in_o : out std_logic;
sel_pc_val_o : out std_logic_vector ( 1 downto 0 );
sel_rb_in_o : out std_logic_vector ( 1 downto 0 );
sel_rb_out_o : out std_logic_vector ( 1 downto 0 );
sel_reg_o : out std_logic_vector ( 1 downto 0 );
sel_sp_as_o : out std_logic;
sel_sp_in_o : out std_logic;
sync_o : out std_logic;
wr_n_o : out std_logic;
wr_o : out std_logic
);
-- Declarations
end fsm_execution_unit ;
-- (C) 2008 - 2018 Jens Gutschmidt
-- (email: [email protected])
--
-- Versions:
-- Revision 1.1202 2018/09/09 17:48:00 jens
-- - RESET generates SYNC now
-- Revision 1.1202 RC 2018/09/09 03:00:00 jens
-- - ADC / SBC flags and A like R65C02 now
-- Revision 1.1202 BETA 2018/09/05 19:35:00 jens
-- - BBRx/BBSx internal cycles like real 65C02 now
-- - Bug Fix ADC and SBC in decimal mode (all op codes -
-- 1 cycle is missing
-- - Bug Fix ADC and SBC in decimal mode (all op codes -
-- "Overflow" flag was computed wrong)
-- Revision 1.1202 BETA 2018/09/02 18:49:00 jens
-- - Interrupt NMI and IRQ processing via FETCH stage now
-- Revision 1.1202 BETA 2018/08/30 15:39:00 jens
-- - Interrupt priority order is now: BRQ - NMI - IRQ
-- - Performance improvements on-going (Mealy -> Moore)
-- Revision 1.1202 BETA 2018/08/23 20:27:00 jens
-- - Bug Fixes All Branch Instructions
-- (BCC, BCS, BEQ, BNE, BPL, BMI, BVC, BVS, BRA)
-- 3 cycles now if branch forward occur and the branch
-- instruction lies on a xxFEh location.
-- (BBR, BBS) 6 cycles now if branch forward occur and the
-- branch instruction lies on a xxFDh location.
-- - Bug Fix Hardware Interrupts NMI & IRQ - 7 cycles & "SYNC" now
-- - Bug Fix Now all cycles are delayable (WR and internal)
--
-- Revision 1.1201 BETA 2014/04/19 14:44:00 jens
-- (never submitted to opencores)
-- - Bug Fix JMP ABS - produced a 6502 like JMP (IND) PCH.
-- When the ABS address data bytes cross the page
-- boundary (e.g. $02FE JMP hhll reads hh from
-- $02FF and ll from $0200, instead $02FF and $0300)
--
-- Revision 1.12 RC 2013/07/31 11:53:00 jens
-- - Bug Fix CMP (IND) - wrongly decoded as function AND
-- - Bug Fix BRK should clear decimal flag P Reg
-- - Bug Fix JMP (ABS,X) - Low Address outputted twice - no High Address
-- - Bug Fix Unknown Ops - Used allways 1b2c NOP ($EA) - new NOPs created
-- - Bug Fix DECIMAL ADC and SBC (all op codes - "C" flag was computed wrong)
-- - Bug Fix INC/DEC ABS,X - N/Z flag wrongly computed
-- - Bug Fix RTI - should increment stack pointer (decremented)
-- - Bug Fix "E" & "B" flags (Bits 5 & 4) - should be always "1" in P Reg. Change "RES", "RTI", "IRQ" & "NMI" substates.
-- - Bug Fix ADC and SBC (all op codes - "Overflow" flag was computed wrong)
-- - Bug Fix RMB, SMB Bug - Bit position decoded wrong.
--
-- Revision 1.11 2013/07/21 11:11:00 jens
-- - Changing the title block and internal revision history
-- - Bug Fix STA [(IND)] op$92 ($92 was missed in the connection list at state FETCH)
--
-- Revision 1.10 2010/02/08 17:34:20 eda
-- BUGFIX for IRQn, NMIn and RTI
-- After detection of NMI or IRQ the address of the next instruction stacked wrong.
-- NMI now overwrites the vector address of IRQ if NMI asserted after IRQ and the
-- vector address is not loaded yet.
--
--
-- Revision 1.9 2010/02/08 17:32:19 eda
-- BUGFIX for IRQn, NMIn and RTI
-- After detection of NMI or IRQ the address of the next instruction stacked wrong.
-- NMI now overwrites the vector address of IRQ if NMI asserted after IRQ and the
-- vector address is not loaded yet.
--
--
-- Revision 1.8 2009/01/04 20:23:42 eda
-- *** EMERGENCY BUGFIX ***
-- - Signal rd_o was corrupted in last version. wr_o and wr_n are not effected.
-- - OP JMP (indirect) produced a 65C02 like jump. On 6502 a special case exist
-- when the (indirect) address cross the page boundary (e.g. JMP (02FF) reads from
-- $02FF and $0200, instead of $02FF and $0300)
--
-- Revision 1.7 2009/01/04 16:54:59 eda
-- - Removed unused bits in ALU (zw_ALUx)
--
-- Revision 1.6 2009/01/04 10:27:49 eda
-- Changes for cosmetic issues only
--
-- Revision 1.5 2009/01/04 10:25:04 eda
-- Changes for cosmetic issues only
--
-- Revision 1.4 2009/01/03 16:53:01 eda
-- - Unused nets and blocks deleted
-- - Re-arragend symbols in block FSM_Execution_Unit
-- - Renamed blocks
-- - Input SO implemented
--
-- Revision 1.3 2009/01/03 16:42:02 eda
-- - Unused nets and blocks deleted
-- - Re-arragend symbols in block FSM_Execution_Unit
-- - Renamed blocks
-- - Input SO implemented
--
-- Revision 1.2 2008/12/31 19:31:24 eda
-- Production Release
--
--
--
-- VHDL Architecture r65c02_tc.fsm_execution_unit.fsm
--
-- Created:
-- by - eda.UNKNOWN (ENTW-7HPZ200)
-- at - 18:23:45 09.09.2018
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5)
--
-- COPYRIGHT (C) 2008 - 2018 by Jens Gutschmidt
--
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
architecture fsm of fsm_execution_unit is
-- Architecture Declarations
signal reg_F : std_logic_vector( 7 DOWNTO 0 );
signal reg_PC : std_logic_vector(15 DOWNTO 0);
signal reg_PC1 : std_logic_vector( 15 DOWNTO 0 );
signal reg_sel_pc_in : std_logic;
signal reg_sel_pc_val : std_logic_vector( 1 DOWNTO 0 );
signal reg_sel_rb_in : std_logic_vector( 1 DOWNTO 0 );
signal reg_sel_rb_out : std_logic_vector( 1 DOWNTO 0 );
signal reg_sel_reg : std_logic_vector( 1 DOWNTO 0 );
signal reg_sel_sp_as : std_logic;
signal reg_sel_sp_in : std_logic;
signal sig_D_OUT : std_logic_vector( 7 DOWNTO 0 );
signal sig_PC : std_logic_vector(15 DOWNTO 0);
signal sig_RD : std_logic;
signal sig_RWn : std_logic;
signal sig_SYNC : std_logic;
signal sig_WR : std_logic;
signal zw_100_a : std_logic;
signal zw_100_alu : std_logic;
signal zw_100_d : std_logic;
signal zw_50_a : std_logic;
signal zw_50_alu : std_logic;
signal zw_50_d : std_logic;
signal zw_ALU : std_logic_vector(9 DOWNTO 0);
signal zw_ALU1 : std_logic_vector(9 DOWNTO 0);
signal zw_ALU2 : std_logic_vector(9 DOWNTO 0);
signal zw_ALU3 : std_logic_vector(9 DOWNTO 0);
signal zw_ALU4 : std_logic_vector(9 DOWNTO 0);
signal zw_ALU5 : std_logic_vector(9 DOWNTO 0);
signal zw_ALU6 : std_logic_vector(9 DOWNTO 0);
signal zw_PC : std_logic_vector( 15 DOWNTO 0 );
signal zw_REG_ALU : std_logic_vector( 8 DOWNTO 0 );
signal zw_REG_OP : std_logic_vector( 7 DOWNTO 0 );
signal zw_REG_sig_PC : std_logic_vector(15 DOWNTO 0);
signal zw_b1 : std_logic_vector( 7 DOWNTO 0 );
signal zw_b2 : std_logic_vector( 7 DOWNTO 0 );
signal zw_b3 : std_logic_vector( 7 DOWNTO 0 );
signal zw_b4 : std_logic_vector( 7 DOWNTO 0 );
signal zw_so : std_logic;
signal zw_w1 : std_logic_vector( 15 DOWNTO 0 );
signal zw_w2 : std_logic_vector( 15 DOWNTO 0 );
signal zw_w3 : std_logic_vector( 15 DOWNTO 0 );
subtype state_type is
std_logic_vector(7 downto 0);
-- State vector declaration
attribute state_vector : string;
attribute state_vector of fsm : architecture is "current_state";
-- Hard encoding
constant s544 : state_type := "00000000";
constant s545 : state_type := "00000001";
constant s546 : state_type := "00000011";
constant s547 : state_type := "00000010";
constant s549 : state_type := "00000110";
constant s550 : state_type := "00000111";
constant RES : state_type := "00000101";
constant FETCH : state_type := "00000100";
constant s6 : state_type := "00001100";
constant s7 : state_type := "00001101";
constant s8 : state_type := "00001111";
constant s9 : state_type := "00001110";
constant s10 : state_type := "00001010";
constant s13 : state_type := "00001011";
constant s18 : state_type := "00001001";
constant s19 : state_type := "00001000";
constant s26 : state_type := "00011000";
constant s27 : state_type := "00011001";
constant s203 : state_type := "00011011";
constant s204 : state_type := "00011010";
constant s212 : state_type := "00011110";
constant s216 : state_type := "00011111";
constant s219 : state_type := "00011101";
constant s220 : state_type := "00011100";
constant s227 : state_type := "00010100";
constant s228 : state_type := "00010101";
constant s230 : state_type := "00010111";
constant s231 : state_type := "00010110";
constant s229 : state_type := "00010010";
constant s512 : state_type := "00010011";
constant s554 : state_type := "00010001";
constant s578 : state_type := "00010000";
constant s581 : state_type := "00110000";
constant s582 : state_type := "00110001";
constant s583 : state_type := "00110011";
constant s584 : state_type := "00110010";
constant s585 : state_type := "00110110";
constant s586 : state_type := "00110111";
constant s587 : state_type := "00110101";
constant s580 : state_type := "00110100";
constant s178 : state_type := "00111100";
constant s194 : state_type := "00111101";
constant s195 : state_type := "00111111";
constant s196 : state_type := "00111110";
constant s197 : state_type := "00111010";
constant s198 : state_type := "00111011";
constant s199 : state_type := "00111001";
constant s200 : state_type := "00111000";
constant s205 : state_type := "00101000";
constant s206 : state_type := "00101001";
constant s207 : state_type := "00101011";
constant s208 : state_type := "00101010";
constant s209 : state_type := "00101110";
constant s213 : state_type := "00101111";
constant s214 : state_type := "00101101";
constant s513 : state_type := "00101100";
constant s588 : state_type := "00100100";
constant s589 : state_type := "00100101";
constant s590 : state_type := "00100111";
constant s591 : state_type := "00100110";
constant s592 : state_type := "00100010";
constant s593 : state_type := "00100011";
constant s594 : state_type := "00100001";
constant s595 : state_type := "00100000";
constant s596 : state_type := "01100000";
constant s597 : state_type := "01100001";
constant s405 : state_type := "01100011";
constant s408 : state_type := "01100010";
constant s410 : state_type := "01100110";
constant s411 : state_type := "01100111";
constant s414 : state_type := "01100101";
constant s415 : state_type := "01100100";
constant s417 : state_type := "01101100";
constant s419 : state_type := "01101101";
constant s420 : state_type := "01101111";
constant s598 : state_type := "01101110";
constant s599 : state_type := "01101010";
constant s600 : state_type := "01101011";
constant s268 : state_type := "01101001";
constant s305 : state_type := "01101000";
constant s306 : state_type := "01111000";
constant jmp1 : state_type := "01111001";
constant jmp2_1 : state_type := "01111011";
constant jmp4_12 : state_type := "01111010";
constant jmp_ex : state_type := "01111110";
constant jmp2_2 : state_type := "01111111";
constant jmp3_1 : state_type := "01111101";
constant s402 : state_type := "01111100";
constant s421 : state_type := "01110100";
constant s422 : state_type := "01110101";
constant s423 : state_type := "01110111";
constant s424 : state_type := "01110110";
constant s362 : state_type := "01110010";
constant s221 : state_type := "01110011";
constant s232 : state_type := "01110001";
constant s233 : state_type := "01110000";
constant s234 : state_type := "01010000";
constant s235 : state_type := "01010001";
constant brk1 : state_type := "01010011";
constant brk2 : state_type := "01010010";
constant brk3 : state_type := "01010110";
constant brk4 : state_type := "01010111";
constant brk6 : state_type := "01010101";
constant brk5 : state_type := "01010100";
constant s425 : state_type := "01011100";
constant s426 : state_type := "01011101";
constant s427 : state_type := "01011111";
constant s428 : state_type := "01011110";
constant s429 : state_type := "01011010";
constant s430 : state_type := "01011011";
constant s431 : state_type := "01011001";
constant s432 : state_type := "01011000";
constant s433 : state_type := "01001000";
constant s434 : state_type := "01001001";
constant s236 : state_type := "01001011";
constant s245 : state_type := "01001010";
constant s246 : state_type := "01001110";
constant s248 : state_type := "01001111";
constant s345 : state_type := "01001101";
constant s346 : state_type := "01001100";
constant s252 : state_type := "01000100";
constant s253 : state_type := "01000101";
constant s435 : state_type := "01000111";
constant s436 : state_type := "01000110";
constant s437 : state_type := "01000010";
constant s438 : state_type := "01000011";
constant s439 : state_type := "01000001";
constant s440 : state_type := "01000000";
constant s441 : state_type := "11000000";
constant s442 : state_type := "11000001";
constant s443 : state_type := "11000011";
constant s444 : state_type := "11000010";
constant irq1 : state_type := "11000110";
constant irq2 : state_type := "11000111";
constant irq3 : state_type := "11000101";
constant irq5b : state_type := "11000100";
constant irq5a : state_type := "11001100";
constant irq4 : state_type := "11001101";
constant irq6 : state_type := "11001111";
constant s11 : state_type := "11001110";
constant s12 : state_type := "11001010";
constant s20 : state_type := "11001011";
constant s14 : state_type := "11001001";
constant s21 : state_type := "11001000";
constant s23 : state_type := "11011000";
constant s15 : state_type := "11011001";
constant s25 : state_type := "11011011";
constant s28 : state_type := "11011010";
constant s16 : state_type := "11011110";
constant s30 : state_type := "11011111";
constant s31 : state_type := "11011101";
constant s32 : state_type := "11011100";
constant s33 : state_type := "11010100";
constant s34 : state_type := "11010101";
constant s36 : state_type := "11010111";
constant jmp3_2 : state_type := "11010110";
constant s601 : state_type := "11010010";
constant s602 : state_type := "11010011";
constant s270 : state_type := "11010001";
constant s307 : state_type := "11010000";
constant s308 : state_type := "11110000";
constant s271 : state_type := "11110001";
constant s272 : state_type := "11110011";
constant s309 : state_type := "11110010";
constant RES2 : state_type := "11110110";
-- Declare current and next state signals
signal current_state : state_type;
signal next_state : state_type;
-- Declare any pre-registered internal signals
signal d_o_cld : std_logic_vector ( 7 downto 0 );
signal rd_o_cld : std_logic ;
signal sync_o_cld : std_logic ;
signal wr_n_o_cld : std_logic ;
signal wr_o_cld : std_logic ;
begin
-----------------------------------------------------------------
clocked_proc : process (
clk_clk_i,
rst_rst_n_i
)
-----------------------------------------------------------------
begin
if (rst_rst_n_i = '0') then
current_state <= RES;
-- Default Reset Values
d_o_cld <= X"00";
rd_o_cld <= '0';
sync_o_cld <= '0';
wr_n_o_cld <= '1';
wr_o_cld <= '0';
reg_F <= "00110100";
reg_PC <= X"0000";
reg_PC1 <= X"0000";
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_rb_in <= "00";
reg_sel_rb_out <= "00";
reg_sel_reg <= "00";
reg_sel_sp_as <= '0';
reg_sel_sp_in <= '0';
sig_PC <= X"0000";
zw_PC <= X"0000";
zw_REG_ALU <= '0' & X"00";
zw_REG_OP <= X"00";
zw_REG_sig_PC <= X"0000";
zw_b1 <= X"00";
zw_b2 <= X"00";
zw_b3 <= X"00";
zw_b4 <= X"00";
zw_so <= '0';
zw_w1 <= X"0000";
zw_w2 <= X"0000";
zw_w3 <= X"0000";
elsif (clk_clk_i'event and clk_clk_i = '1') then
current_state <= next_state;
-- Default Assignment To Internals
reg_F <= reg_F(7) & (zw_so OR reg_F(6)) & reg_F(5 downto 0);
reg_PC <= reg_PC;
reg_PC1 <= reg_PC1;
reg_sel_pc_in <= reg_sel_pc_in;
reg_sel_pc_val <= reg_sel_pc_val;
reg_sel_rb_in <= reg_sel_rb_in;
reg_sel_rb_out <= reg_sel_rb_out;
reg_sel_reg <= reg_sel_reg;
reg_sel_sp_as <= reg_sel_sp_as;
reg_sel_sp_in <= reg_sel_sp_in;
sig_PC <= sig_PC;
zw_PC <= zw_PC;
zw_REG_ALU <= zw_REG_ALU;
zw_REG_OP <= zw_REG_OP;
zw_REG_sig_PC <= zw_REG_sig_PC;
zw_b1 <= zw_b1;
zw_b2 <= zw_b2;
zw_b3 <= zw_b3;
zw_b4 <= zw_b4;
zw_so <= (zw_so OR (NOT(so_n_i))) AND (NOT(reg_F(6)));
zw_w1 <= zw_w1;
zw_w2 <= zw_w2;
zw_w3 <= zw_w3;
d_o_cld <= sig_D_OUT;
rd_o_cld <= sig_RD;
sync_o_cld <= sig_SYNC;
wr_n_o_cld <= sig_RWn;
wr_o_cld <= sig_WR;
-- Combined Actions
case current_state is
when s544 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s545 =>
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s546 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
end if;
when s547 =>
zw_w1 (7 downto 0) <= d_i;
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "11";
end if;
when s549 =>
reg_F(2) <= '1';
reg_F(3) <= '0';
reg_F(5) <= '1';
if (rdy_i = '1') then
sig_PC <= d_i & zw_w1 (7 downto 0);
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s550 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "00";
end if;
when RES =>
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
when FETCH =>
zw_REG_OP <= d_i;
if ((d_i = X"00") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
elsif ((nmi_i = '1') and (rdy_i = '1')) then
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
sig_PC <= adr_nxt_pc_i;
zw_w3 <= adr_pc_i;
elsif ((irq_n_i = '0' and
reg_F(2) = '0') and (rdy_i = '1')) then
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
sig_PC <= adr_nxt_pc_i;
zw_w3 <= adr_pc_i;
elsif ((d_i = X"58") and (rdy_i = '1')) then
elsif ((d_i = X"28") and (rdy_i = '1')) then
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '0';
elsif ((d_i = X"78") and (rdy_i = '1')) then
elsif ((d_i = X"69" or
d_i = X"65" or
d_i = X"75" or
d_i = X"6D" or
d_i = X"7D" or
d_i = X"79" or
d_i = X"61" or
d_i = X"71" or
d_i = X"72") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
elsif ((d_i = X"06" or
d_i = X"16" or
d_i = X"0E" or
d_i = X"1E" or
d_i (3 downto 0) = X"7" or
d_i = X"14" or
d_i = X"04" or
d_i = X"0C" or
d_i = X"1C") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"90" or
d_i = X"B0" or
d_i = X"F0" or
d_i = X"30" or
d_i = X"D0" or
d_i = X"10" or
d_i = X"50" or
d_i = X"70" or
d_i = X"80") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"24" or
d_i = X"2C" or
d_i = X"3C" or
d_i = X"34" or
d_i = X"89") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"18") and (rdy_i = '1')) then
elsif ((d_i = X"D8") and (rdy_i = '1')) then
elsif ((d_i = X"8F" or
d_i = X"9F" or
d_i = X"AF" or
d_i = X"BF" or
d_i = X"CF" or
d_i = X"DF" or
d_i = X"EF" or
d_i = X"FF" or
d_i = X"0F" or
d_i = X"1F" or
d_i = X"2F" or
d_i = X"3F" or
d_i = X"4F" or
d_i = X"5F" or
d_i = X"6F" or
d_i = X"7F") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"B8") and (rdy_i = '1')) then
elsif ((d_i = X"E0" or
d_i = X"E4" or
d_i = X"EC") and (rdy_i = '1')) then
reg_sel_rb_out <= "01";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"C0" or
d_i = X"C4" or
d_i = X"CC") and (rdy_i = '1')) then
reg_sel_rb_out <= "10";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"C6" or
d_i = X"D6" or
d_i = X"CE" or
d_i = X"DE") and (rdy_i = '1')) then
zw_b4 <= X"FF";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"CA") and (rdy_i = '1')) then
reg_sel_rb_out <= "01";
reg_sel_reg <= "01";
reg_sel_rb_in <= "11";
zw_b4 <= X"FF";
elsif ((d_i = X"88") and (rdy_i = '1')) then
reg_sel_rb_out <= "10";
reg_sel_reg <= "10";
reg_sel_rb_in <= "11";
zw_b4 <= X"FF";
elsif ((d_i = X"49" or
d_i = X"45" or
d_i = X"55" or
d_i = X"4D" or
d_i = X"5D" or
d_i = X"59" or
d_i = X"41" or
d_i = X"51" or
d_i = X"09" or
d_i = X"05" or
d_i = X"15" or
d_i = X"0D" or
d_i = X"1D" or
d_i = X"19" or
d_i = X"01" or
d_i = X"11" or
d_i = X"29" or
d_i = X"25" or
d_i = X"35" or
d_i = X"2D" or
d_i = X"3D" or
d_i = X"39" or
d_i = X"21" or
d_i = X"31" or
d_i = X"C9" or
d_i = X"C5" or
d_i = X"D5" or
d_i = X"CD" or
d_i = X"DD" or
d_i = X"D9" or
d_i = X"C1" or
d_i = X"D1" or
d_i = X"32" or
d_i = X"D2" or
d_i = X"52" or
d_i = X"12") and (rdy_i = '1')) then
reg_sel_rb_out <= "00";
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"E6" or
d_i = X"F6" or
d_i = X"EE" or
d_i = X"FE") and (rdy_i = '1')) then
zw_b4 <= X"01";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"E8") and (rdy_i = '1')) then
reg_sel_rb_out <= "01";
reg_sel_reg <= "01";
reg_sel_rb_in <= "11";
zw_b4 <= X"01";
elsif ((d_i = X"C8") and (rdy_i = '1')) then
reg_sel_rb_out <= "10";
reg_sel_reg <= "10";
reg_sel_rb_in <= "11";
zw_b4 <= X"01";
elsif ((d_i = X"4C" or
d_i = X"6C" or
d_i = X"7C") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"20") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"A9" or
d_i = X"A5" or
d_i = X"B5" or
d_i = X"AD" or
d_i = X"BD" or
d_i = X"B9" or
d_i = X"A1" or
d_i = X"B1" or
d_i = X"B2") and (rdy_i = '1')) then
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"A2" or
d_i = X"A6" or
d_i = X"B6" or
d_i = X"AE" or
d_i = X"BE") and (rdy_i = '1')) then
reg_sel_reg <= "01";
reg_sel_rb_in <= "11";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"A0" or
d_i = X"A4" or
d_i = X"B4" or
d_i = X"AC" or
d_i = X"BC") and (rdy_i = '1')) then
reg_sel_reg <= "10";
reg_sel_rb_in <= "11";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"46" or
d_i = X"56" or
d_i = X"4E" or
d_i = X"5E") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"EA") and (rdy_i = '1')) then
elsif ((d_i = X"48") and (rdy_i = '1')) then
reg_sel_rb_out <= "00";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"08") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"7A") and (rdy_i = '1')) then
reg_sel_reg <= "10";
reg_sel_rb_in <= "11";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '0';
elsif ((d_i = X"26" or
d_i = X"36" or
d_i = X"2E" or
d_i = X"3E") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"66" or
d_i = X"76" or
d_i = X"6E" or
d_i = X"7E") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"40") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '0';
elsif ((d_i = X"60") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '0';
elsif ((d_i = X"E9" or
d_i = X"E5" or
d_i = X"F5" or
d_i = X"ED" or
d_i = X"FD" or
d_i = X"F9" or
d_i = X"E1" or
d_i = X"F1" or
d_i = X"F2") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
elsif ((d_i = X"38") and (rdy_i = '1')) then
elsif ((d_i = X"F8") and (rdy_i = '1')) then
elsif ((d_i = X"85" or
d_i = X"95" or
d_i = X"8D" or
d_i = X"9D" or
d_i = X"99" or
d_i = X"81" or
d_i = X"91" or
d_i = X"92") and (rdy_i = '1')) then
reg_sel_rb_out <= "00";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"86" or
d_i = X"96" or
d_i = X"8E") and (rdy_i = '1')) then
reg_sel_rb_out <= "01";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"84" or
d_i = X"94" or
d_i = X"8C") and (rdy_i = '1')) then
reg_sel_rb_out <= "10";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"AA") and (rdy_i = '1')) then
reg_sel_rb_out <= "00";
reg_sel_reg <= "01";
reg_sel_rb_in <= "00";
reg_sel_sp_in <= '1';
reg_sel_sp_as <= '0';
elsif ((d_i = X"0A") and (rdy_i = '1')) then
reg_sel_rb_out <= "00";
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
elsif ((d_i = X"4A") and (rdy_i = '1')) then
reg_sel_rb_out <= "00";
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
elsif ((d_i = X"2A") and (rdy_i = '1')) then
reg_sel_rb_out <= "00";
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
elsif ((d_i = X"6A") and (rdy_i = '1')) then
reg_sel_rb_out <= "00";
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
elsif ((d_i = X"A8") and (rdy_i = '1')) then
reg_sel_rb_out <= "00";
reg_sel_reg <= "10";
reg_sel_rb_in <= "00";
reg_sel_sp_in <= '1';
reg_sel_sp_as <= '0';
elsif ((d_i = X"98") and (rdy_i = '1')) then
reg_sel_rb_out <= "10";
reg_sel_reg <= "00";
reg_sel_rb_in <= "01";
reg_sel_sp_in <= '1';
reg_sel_sp_as <= '0';
elsif ((d_i = X"BA") and (rdy_i = '1')) then
reg_sel_rb_out <= "01";
reg_sel_reg <= "01";
reg_sel_rb_in <= "11";
reg_sel_sp_in <= '1';
reg_sel_sp_as <= '0';
elsif ((d_i = X"8A") and (rdy_i = '1')) then
reg_sel_rb_out <= "01";
reg_sel_reg <= "00";
reg_sel_rb_in <= "10";
reg_sel_sp_in <= '1';
reg_sel_sp_as <= '0';
elsif ((d_i = X"9A") and (rdy_i = '1')) then
reg_sel_rb_out <= "01";
reg_sel_reg <= "11";
reg_sel_rb_in <= "11";
reg_sel_sp_in <= '1';
reg_sel_sp_as <= '0';
elsif ((d_i = X"DA") and (rdy_i = '1')) then
reg_sel_rb_out <= "01";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"5A") and (rdy_i = '1')) then
reg_sel_rb_out <= "10";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"68") and (rdy_i = '1')) then
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '0';
elsif ((d_i = X"FA") and (rdy_i = '1')) then
reg_sel_reg <= "01";
reg_sel_rb_in <= "11";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '0';
elsif ((d_i = X"9C" or
d_i = X"9E" or
d_i = X"64" or
d_i = X"74") and (rdy_i = '1')) then
reg_sel_rb_out <= "11";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"3A") and (rdy_i = '1')) then
reg_sel_rb_out <= "00";
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
zw_b4 <= X"FF";
elsif ((d_i = X"1A") and (rdy_i = '1')) then
reg_sel_rb_out <= "00";
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
zw_b4 <= X"01";
elsif ((d_i = X"EA") and (rdy_i = '1')) then
elsif ((d_i = X"02" or
d_i = X"22" or
d_i = X"42" or
d_i = X"62" or
d_i = X"82" or
d_i = X"C2" or
d_i = X"E2") and (rdy_i = '1')) then
elsif ((d_i = X"44") and (rdy_i = '1')) then
elsif ((d_i = X"54" or
d_i = X"D4" or
d_i = X"F4") and (rdy_i = '1')) then
elsif ((d_i = X"DC" or
d_i = X"FC") and (rdy_i = '1')) then
elsif ((d_i = X"5C") and (rdy_i = '1')) then
elsif ((d_i(3 downto 0) = X"3" or
d_i(3 downto 0) = X"B") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s6 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s7 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(0) <= '1';
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s8 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(3) <= '1';
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s9 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(2) <= '1';
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s10 =>
if (rdy_i = '1' and
zw_REG_OP = X"9A") then
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"BA") then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s13 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(0) <= '0';
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s18 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(3) <= '0';
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s19 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(2) <= '0';
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s26 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(6) <= '0';
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s27 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s203 =>
if (rdy_i = '1' and
(zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR
zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR
zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR
zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) then
sig_PC <= X"00" & d_i;
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11" or
zw_REG_OP = X"12")) then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51" or
zw_REG_OP = X"52")) then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31" or
zw_REG_OP = X"32")) then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC" or
zw_REG_OP = X"D2")) then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(0) <= zw_ALU(8);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"B5" OR
zw_REG_OP = X"B4" OR
zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR
zw_REG_OP = X"35" OR
zw_REG_OP = X"D5")) then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"AD" OR
zw_REG_OP = X"AE" OR
zw_REG_OP = X"AC" OR
zw_REG_OP = X"4D" OR
zw_REG_OP = X"0D" OR
zw_REG_OP = X"2D" OR
zw_REG_OP = X"CD" OR
zw_REG_OP = X"EC" OR
zw_REG_OP = X"CC")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"BD" OR
zw_REG_OP = X"BC" OR
zw_REG_OP = X"5D" OR
zw_REG_OP = X"1D" OR
zw_REG_OP = X"3D" OR
zw_REG_OP = X"DD")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"B9" OR
zw_REG_OP = X"BE" OR
zw_REG_OP = X"59" OR
zw_REG_OP = X"19" OR
zw_REG_OP = X"39" OR
zw_REG_OP = X"D9")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"B1" OR
zw_REG_OP = X"51" OR
zw_REG_OP = X"11" OR
zw_REG_OP = X"31" OR
zw_REG_OP = X"D1")) then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"A1" OR
zw_REG_OP = X"41" OR
zw_REG_OP = X"01" OR
zw_REG_OP = X"21" OR
zw_REG_OP = X"C1")) then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"B6") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"32" OR
zw_REG_OP = X"D2" OR
zw_REG_OP = X"52" OR
zw_REG_OP = X"B2" OR
zw_REG_OP = X"12")) then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
end if;
when s204 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
end if;
when s212 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s216 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
end if;
when s219 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s220 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s227 =>
if (rdy_i = '1') then
sig_PC <= X"00" & d_alu_i;
zw_b1 <= d_i;
end if;
when s228 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s230 =>
if ((rdy_i = '1') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11" or
zw_REG_OP = X"12")) then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif ((rdy_i = '1') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51" or
zw_REG_OP = X"52")) then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif ((rdy_i = '1') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31" or
zw_REG_OP = X"32")) then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif ((rdy_i = '1') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC" or
zw_REG_OP = X"D2")) then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(0) <= zw_ALU(8);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s231 =>
if ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11" or
zw_REG_OP = X"12")) then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51" or
zw_REG_OP = X"52")) then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31" or
zw_REG_OP = X"32")) then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC" or
zw_REG_OP = X"D2")) then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(0) <= zw_ALU(8);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' AND
zw_b2(0) = '0') then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1') then
sig_PC <= zw_b3 & zw_b1;
end if;
when s229 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
zw_b1 <= d_i;
end if;
when s512 =>
if (rdy_i = '1' and
zw_REG_OP = X"65") then
sig_PC <= X"00" & d_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '0') then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= (zw_ALU(7) AND (NOT q_a_i(7)) AND (NOT d_i(7))) OR
(NOT zw_ALU(7) AND (q_a_i(7)) AND (d_i(7)));
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU(8);
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"75") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"6D") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"7D") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"79") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"71") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"61") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '1') then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= (zw_ALU5(3) XOR q_a_i(7)) AND (NOT (q_a_i(7) XOR d_i(7)));
reg_F(1) <= NOT (zw_ALU(7) OR zw_ALU(6) OR zw_ALU(5) OR
zw_ALU(4) OR zw_ALU(3) OR zw_ALU(2) OR zw_ALU(1) OR
zw_ALU(0));
reg_F(0) <= zw_ALU4(4);
elsif (rdy_i = '1' and
zw_REG_OP = X"72") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
end if;
when s554 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
end if;
when s578 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s581 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
end if;
when s582 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s583 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s584 =>
if (rdy_i = '1') then
sig_PC <= X"00" & d_alu_i;
zw_b1 <= d_i;
end if;
when s585 =>
if (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= (zw_ALU(7) AND (NOT q_a_i(7)) AND (NOT d_i(7))) OR
(NOT zw_ALU(7) AND (q_a_i(7)) AND (d_i(7)));
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU(8);
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= (zw_ALU5(3) XOR q_a_i(7)) AND (NOT (q_a_i(7) XOR d_i(7)));
reg_F(1) <= NOT (zw_ALU(7) OR zw_ALU(6) OR zw_ALU(5) OR
zw_ALU(4) OR zw_ALU(3) OR zw_ALU(2) OR zw_ALU(1) OR
zw_ALU(0));
reg_F(0) <= zw_ALU4(4);
elsif (rdy_i = '1') then
sig_PC <= zw_b3 & zw_b1;
end if;
when s586 =>
if (rdy_i = '1' and
reg_F(3) = '0') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= (zw_ALU(7) AND (NOT q_a_i(7)) AND (NOT d_i(7))) OR
(NOT zw_ALU(7) AND (q_a_i(7)) AND (d_i(7)));
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU(8);
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' and
reg_F(3) = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= (zw_ALU5(3) XOR q_a_i(7)) AND (NOT (q_a_i(7) XOR d_i(7)));
reg_F(1) <= NOT (zw_ALU(7) OR zw_ALU(6) OR zw_ALU(5) OR
zw_ALU(4) OR zw_ALU(3) OR zw_ALU(2) OR zw_ALU(1) OR
zw_ALU(0));
reg_F(0) <= zw_ALU4(4);
end if;
when s587 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s580 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
zw_b1 <= d_i;
end if;
when s178 =>
if (rdy_i = '1' and
(zw_REG_OP = X"85" OR
zw_REG_OP = X"86" OR
zw_REG_OP = X"64" OR
zw_REG_OP = X"84")) then
sig_PC <= X"00" & d_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"95" OR
zw_REG_OP = X"74" OR
zw_REG_OP = X"94")) then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"8D" OR
zw_REG_OP = X"8E" OR
zw_REG_OP = X"9C" OR
zw_REG_OP = X"8C")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"9D" OR
zw_REG_OP = X"9E")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"99") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"91") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"81") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"96") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"92") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
end if;
when s194 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s195 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
end if;
when s196 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
end if;
when s197 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s198 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s199 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s200 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s205 =>
if (rdy_i = '1') then
sig_PC <= X"00" & d_alu_i;
zw_b1 <= d_i;
end if;
when s206 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s207 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s208 =>
if (rdy_i = '1') then
sig_PC <= zw_b3 & zw_b1;
end if;
when s209 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
end if;
when s213 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s214 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
zw_b1 <= d_i;
end if;
when s513 =>
if (rdy_i = '1' and
zw_REG_OP = X"E5") then
sig_PC <= X"00" & d_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '0') then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= (zw_ALU(7) AND (NOT q_a_i(7)) AND (d_i(7))) OR
(NOT zw_ALU(7) AND (q_a_i(7)) AND (NOT d_i(7)));
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= (zw_ALU(8) AND (NOT q_a_i(7)) AND (NOT d_i(7))) OR
(zw_ALU(8) AND (q_a_i(7)) AND (d_i(7))) OR
(NOT zw_ALU(8) AND (q_a_i(7)) AND (NOT d_i(7))) OR
(zw_ALU(8) AND (q_a_i(7)) AND (NOT d_i(7)));
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"F5") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"ED") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"FD") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"F9") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"F1") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"E1") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '1') then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= (zw_ALU2(3) XOR q_a_i(7)) AND (q_a_i(7) XOR d_i(7));
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= (zw_ALU2(4));
elsif (rdy_i = '1' and
zw_REG_OP = X"F2") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
end if;
when s588 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
end if;
when s589 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s590 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
end if;
when s591 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s592 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s593 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s594 =>
if (rdy_i = '1') then
sig_PC <= X"00" & d_alu_i;
zw_b1 <= d_i;
end if;
when s595 =>
if (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= (zw_ALU(7) AND (NOT q_a_i(7)) AND (d_i(7))) OR
(NOT zw_ALU(7) AND (q_a_i(7)) AND (NOT d_i(7)));
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= (zw_ALU(8) AND (NOT q_a_i(7)) AND (NOT d_i(7))) OR
(zw_ALU(8) AND (q_a_i(7)) AND (d_i(7))) OR
(NOT zw_ALU(8) AND (q_a_i(7)) AND (NOT d_i(7))) OR
(zw_ALU(8) AND (q_a_i(7)) AND (NOT d_i(7)));
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= (zw_ALU2(3) XOR q_a_i(7)) AND (q_a_i(7) XOR d_i(7));
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= (zw_ALU2(4));
elsif (rdy_i = '1') then
sig_PC <= zw_b3 & zw_b1;
end if;
when s596 =>
if (rdy_i = '1' and
reg_F(3) = '0') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= (zw_ALU(7) AND (NOT q_a_i(7)) AND (d_i(7))) OR
(NOT zw_ALU(7) AND (q_a_i(7)) AND (NOT d_i(7)));
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= (zw_ALU(8) AND (NOT q_a_i(7)) AND (NOT d_i(7))) OR
(zw_ALU(8) AND (q_a_i(7)) AND (d_i(7))) OR
(NOT zw_ALU(8) AND (q_a_i(7)) AND (NOT d_i(7))) OR
(zw_ALU(8) AND (q_a_i(7)) AND (NOT d_i(7)));
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' and
reg_F(3) = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= (zw_ALU2(3) XOR q_a_i(7)) AND (q_a_i(7) XOR d_i(7));
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= (zw_ALU2(4));
end if;
when s597 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
zw_b1 <= d_i;
end if;
when s405 =>
if (rdy_i = '1' and
(zw_REG_OP = X"1E" or
zw_REG_OP = X"7E" or
zw_REG_OP = X"3E" or
zw_REG_OP = X"5E")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"06" or zw_REG_OP = X"66" or
zw_REG_OP = X"26" or zw_REG_OP = X"46" or
zw_REG_OP = X"04" or zw_REG_OP = X"14")) then
sig_PC <= X"00" & d_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"16" or
zw_REG_OP = X"76" or
zw_REG_OP = X"36" or
zw_REG_OP = X"56")) then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"0E" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"4E"or
zw_REG_OP = X"0C" or
zw_REG_OP = X"1C")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
elsif (rdy_i = '1' and
zw_REG_OP (3 downto 0) = X"7") then
sig_PC <= X"00" & d_i;
end if;
when s408 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
end if;
when s410 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s411 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s414 =>
if (rdy_i = '1') then
sig_PC <= zw_b3 & zw_b1;
end if;
when s417 =>
if ((rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"16" or
zw_REG_OP = X"0E" or
zw_REG_OP = X"1E")) and (rdy_i = '1')) then
zw_b1 <= d_i(6 downto 0) & '0';
zw_b2(0) <= d_i(7);
elsif ((rdy_i = '1' and
(zw_REG_OP = X"46" or
zw_REG_OP = X"56" or
zw_REG_OP = X"4E" or
zw_REG_OP = X"5E")) and (rdy_i = '1')) then
zw_b1 <= '0' & d_i(7 downto 1);
zw_b2(0) <= d_i(0);
elsif ((rdy_i = '1' and
(zw_REG_OP = X"26" or
zw_REG_OP = X"36" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"3E")) and (rdy_i = '1')) then
zw_b1 <= d_i(6 downto 0) & reg_F(0);
zw_b2(0) <= d_i(7);
elsif ((rdy_i = '1' and
(zw_REG_OP = X"66" or
zw_REG_OP = X"76" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"7E")) and (rdy_i = '1')) then
zw_b1 <= reg_F(0) & d_i(7 downto 1);
zw_b2(0) <= d_i(0);
elsif ((rdy_i = '1' and
zw_REG_OP (7) = '0' and
zw_REG_OP (3 downto 0) = X"7") and (rdy_i = '1')) then
elsif ((rdy_i = '1' and
zw_REG_OP (7) = '1' and
zw_REG_OP (3 downto 0) = X"7") and (rdy_i = '1')) then
elsif ((rdy_i = '1' and
(zw_REG_OP = X"14" or
zw_REG_OP = X"1C")) and (rdy_i = '1')) then
zw_b1 <= d_i and q_a_i;
elsif ((rdy_i = '1' and
(zw_REG_OP = X"04" or
zw_REG_OP = X"0C")) and (rdy_i = '1')) then
zw_b1 <= d_i and q_a_i;
end if;
when s419 =>
if ((zw_REG_OP (3 downto 0) = X"7") and (rdy_i = '1')) then
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (((zw_REG_OP = X"14" or
zw_REG_OP = X"04" or
zw_REG_OP = X"0C" or
zw_REG_OP = X"1C")) and (rdy_i = '1')) then
reg_F(1) <= reg_1flag_i;
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1') then
reg_F(0) <= zw_b2(0);
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s420 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(0) <= q_a_i(7);
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s598 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(0) <= q_a_i(0);
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s599 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(0) <= q_a_i(0);
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s600 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(0) <= q_a_i(7);
reg_F(0) <= q_a_i(7);
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s268 =>
zw_b1 <= d_i;
zw_b3 <= adr_nxt_pc_i (15 downto 8);
zw_b2 <= d_i;
if (rdy_i = '1' and (
(reg_F(0) = '1' and zw_REG_OP = X"90") or (reg_F(0) = '0' and zw_REG_OP = X"B0") or
(reg_F(1) = '0' and zw_REG_OP = X"F0") or (reg_F(7) = '0' and zw_REG_OP = X"30") or
(reg_F(1) = '1' and zw_REG_OP = X"D0") or (reg_F(7) = '1' and zw_REG_OP = X"10") or
(reg_F(6) = '1' and zw_REG_OP = X"50") or (reg_F(6) = '0' and zw_REG_OP = X"70"))) then
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1') then
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "10";
end if;
when s305 =>
if (rdy_i = '1' and
zw_b3 = adr_nxt_pc_i (15 downto 8)) then
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1') then
sig_PC <= zw_b3 & adr_nxt_pc_i (7 downto 0);
end if;
when s306 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when jmp1 =>
zw_b1 <= d_i;
if (rdy_i = '1' and
zw_REG_OP = X"4C") then
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "11";
elsif (rdy_i = '1' and
zw_REG_OP = X"6C") then
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "00";
elsif (rdy_i = '1' and
zw_REG_OP = X"7C") then
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "10";
end if;
when jmp2_1 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
end if;
when jmp4_12 =>
zw_b1 <= d_i;
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "11";
end if;
when jmp_ex =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when jmp2_2 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
end if;
when s402 =>
zw_b1 <= d_i;
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s422 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s423 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "11";
end if;
when s424 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1 (7 downto 0);
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s362 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
end if;
when s221 =>
if (rdy_i = '1' and
zw_REG_OP = X"34") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"3C") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"24") then
sig_PC <= X"00" & d_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"2C") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"89") then
sig_PC <= adr_nxt_pc_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s232 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s233 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s234 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= d_i(7);
reg_F(6) <= d_i(6);
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s235 =>
if (rdy_i = '1' AND
zw_b2(0) = '0') then
sig_PC <= adr_pc_i;
reg_F(7) <= d_i(7);
reg_F(6) <= d_i(6);
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1') then
sig_PC <= zw_b3 & zw_b1;
end if;
when brk1 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when brk2 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when brk3 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when brk4 =>
if (rdy_i = '1') then
sig_PC <= X"FFFE";
end if;
when brk6 =>
reg_F(2) <= '1';
reg_F(3) <= '0';
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when brk5 =>
zw_b1 <= d_i;
if (rdy_i = '1') then
sig_PC <= X"FFFF";
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "11";
end if;
when s425 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s426 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s427 =>
reg_F(7 downto 6) <= d_i(7 downto 6);
reg_F(3 downto 0) <= d_i(3 downto 0);
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "11";
end if;
when s428 =>
zw_b1 <= d_i;
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s429 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s430 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s431 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s432 =>
zw_b1 <= d_i;
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "00";
end if;
when s433 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
end if;
when s434 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s236 =>
if (rdy_i = '1' and
(zw_REG_OP = X"C6" OR
zw_REG_OP = X"E6")) then
sig_PC <= X"00" & d_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"D6" OR
zw_REG_OP = X"F6")) then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"CE" OR
zw_REG_OP = X"EE")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"DE" OR
zw_REG_OP = X"FE")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
end if;
when s245 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
end if;
when s246 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s248 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s345 =>
if (rdy_i = '1') then
sig_PC <= zw_b3 & zw_b1;
end if;
when s346 =>
if (rdy_i = '1') then
zw_b1 <= d_alu_i;
end if;
when s253 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s435 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s436 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s437 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s438 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s440 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s441 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s443 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s444 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(7 downto 6) <= d_i(7 downto 6);
reg_F(3 downto 0) <= d_i(3 downto 0);
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when irq1 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when irq2 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when irq3 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when irq5b =>
zw_b1 <= d_i;
if (rdy_i = '1') then
sig_PC <= X"FFFF";
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "11";
end if;
when irq5a =>
zw_b1 <= d_i;
if (rdy_i = '1') then
sig_PC <= X"FFFB";
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "11";
end if;
when irq4 =>
if (rdy_i = '1' and
nmi_i = '1') then
sig_PC <= X"FFFA";
elsif (rdy_i = '1') then
sig_PC <= X"FFFE";
end if;
when irq6 =>
reg_F(2) <= '1';
reg_F(3) <= '0';
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s11 =>
if (rdy_i = '1') then
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s20 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s23 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s28 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s33 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when jmp3_2 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
end if;
when s601 =>
if (rdy_i = '1') then
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s602 =>
if (rdy_i = '1') then
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s270 =>
if (rdy_i = '1') then
sig_PC <= X"00" & d_i;
end if;
when s307 =>
if (rdy_i = '1' and
zw_b3 = adr_nxt_pc_i (15 downto 8)) then
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1') then
sig_PC <= zw_b3 & adr_nxt_pc_i (7 downto 0);
end if;
when s308 =>
zw_b2 <= d_i;
zw_b3 <= adr_nxt_pc_i (15 downto 8);
if (rdy_i = '1' and (
(zw_b1(0) = '0' and zw_REG_OP = X"8F") or
(zw_b1(1) = '0' and zw_REG_OP = X"9F") or
(zw_b1(2) = '0' and zw_REG_OP = X"AF") or
(zw_b1(3) = '0' and zw_REG_OP = X"BF") or
(zw_b1(4) = '0' and zw_REG_OP = X"CF") or
(zw_b1(5) = '0' and zw_REG_OP = X"DF") or
(zw_b1(6) = '0' and zw_REG_OP = X"EF") or
(zw_b1(7) = '0' and zw_REG_OP = X"FF") or
(zw_b1(0) = '1' and zw_REG_OP = X"0F") or
(zw_b1(1) = '1' and zw_REG_OP = X"1F") or
(zw_b1(2) = '1' and zw_REG_OP = X"2F") or
(zw_b1(3) = '1' and zw_REG_OP = X"3F") or
(zw_b1(4) = '1' and zw_REG_OP = X"4F") or
(zw_b1(5) = '1' and zw_REG_OP = X"5F") or
(zw_b1(6) = '1' and zw_REG_OP = X"6F") or
(zw_b1(7) = '1' and zw_REG_OP = X"7F"))) then
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1') then
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "10";
end if;
when s272 =>
zw_b1 <= d_i;
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
end if;
when s309 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when RES2 =>
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
when others =>
null;
end case;
end if;
end process clocked_proc;
-----------------------------------------------------------------
nextstate_proc : process (
adr_nxt_pc_i,
current_state,
d_i,
irq_n_i,
nmi_i,
rdy_i,
reg_F,
zw_REG_OP,
zw_b1,
zw_b2,
zw_b3
)
-----------------------------------------------------------------
begin
case current_state is
when s544 =>
if (rdy_i = '1') then
next_state <= s550;
else
next_state <= s544;
end if;
when s545 =>
if (rdy_i = '1') then
next_state <= s546;
else
next_state <= s545;
end if;
when s546 =>
if (rdy_i = '1') then
next_state <= s547;
else
next_state <= s546;
end if;
when s547 =>
if (rdy_i = '1') then
next_state <= s549;
else
next_state <= s547;
end if;
when s549 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s549;
end if;
when s550 =>
if (rdy_i = '1') then
next_state <= s545;
else
next_state <= s550;
end if;
when RES =>
next_state <= RES2;
when FETCH =>
if ((d_i = X"00") and (rdy_i = '1')) then
next_state <= brk1;
elsif ((nmi_i = '1') and (rdy_i = '1')) then
next_state <= irq1;
elsif ((irq_n_i = '0' and
reg_F(2) = '0') and (rdy_i = '1')) then
next_state <= irq1;
elsif ((d_i = X"58") and (rdy_i = '1')) then
next_state <= s19;
elsif ((d_i = X"28") and (rdy_i = '1')) then
next_state <= s442;
elsif ((d_i = X"78") and (rdy_i = '1')) then
next_state <= s9;
elsif ((d_i = X"69" or
d_i = X"65" or
d_i = X"75" or
d_i = X"6D" or
d_i = X"7D" or
d_i = X"79" or
d_i = X"61" or
d_i = X"71" or
d_i = X"72") and (rdy_i = '1')) then
next_state <= s512;
elsif ((d_i = X"06" or
d_i = X"16" or
d_i = X"0E" or
d_i = X"1E" or
d_i (3 downto 0) = X"7" or
d_i = X"14" or
d_i = X"04" or
d_i = X"0C" or
d_i = X"1C") and (rdy_i = '1')) then
next_state <= s405;
elsif ((d_i = X"90" or
d_i = X"B0" or
d_i = X"F0" or
d_i = X"30" or
d_i = X"D0" or
d_i = X"10" or
d_i = X"50" or
d_i = X"70" or
d_i = X"80") and (rdy_i = '1')) then
next_state <= s268;
elsif ((d_i = X"24" or
d_i = X"2C" or
d_i = X"3C" or
d_i = X"34" or
d_i = X"89") and (rdy_i = '1')) then
next_state <= s221;
elsif ((d_i = X"18") and (rdy_i = '1')) then
next_state <= s13;
elsif ((d_i = X"D8") and (rdy_i = '1')) then
next_state <= s18;
elsif ((d_i = X"8F" or
d_i = X"9F" or
d_i = X"AF" or
d_i = X"BF" or
d_i = X"CF" or
d_i = X"DF" or
d_i = X"EF" or
d_i = X"FF" or
d_i = X"0F" or
d_i = X"1F" or
d_i = X"2F" or
d_i = X"3F" or
d_i = X"4F" or
d_i = X"5F" or
d_i = X"6F" or
d_i = X"7F") and (rdy_i = '1')) then
next_state <= s270;
elsif ((d_i = X"B8") and (rdy_i = '1')) then
next_state <= s26;
elsif ((d_i = X"E0" or
d_i = X"E4" or
d_i = X"EC") and (rdy_i = '1')) then
next_state <= s203;
elsif ((d_i = X"C0" or
d_i = X"C4" or
d_i = X"CC") and (rdy_i = '1')) then
next_state <= s203;
elsif ((d_i = X"C6" or
d_i = X"D6" or
d_i = X"CE" or
d_i = X"DE") and (rdy_i = '1')) then
next_state <= s236;
elsif ((d_i = X"CA") and (rdy_i = '1')) then
next_state <= s27;
elsif ((d_i = X"88") and (rdy_i = '1')) then
next_state <= s27;
elsif ((d_i = X"49" or
d_i = X"45" or
d_i = X"55" or
d_i = X"4D" or
d_i = X"5D" or
d_i = X"59" or
d_i = X"41" or
d_i = X"51" or
d_i = X"09" or
d_i = X"05" or
d_i = X"15" or
d_i = X"0D" or
d_i = X"1D" or
d_i = X"19" or
d_i = X"01" or
d_i = X"11" or
d_i = X"29" or
d_i = X"25" or
d_i = X"35" or
d_i = X"2D" or
d_i = X"3D" or
d_i = X"39" or
d_i = X"21" or
d_i = X"31" or
d_i = X"C9" or
d_i = X"C5" or
d_i = X"D5" or
d_i = X"CD" or
d_i = X"DD" or
d_i = X"D9" or
d_i = X"C1" or
d_i = X"D1" or
d_i = X"32" or
d_i = X"D2" or
d_i = X"52" or
d_i = X"12") and (rdy_i = '1')) then
next_state <= s203;
elsif ((d_i = X"E6" or
d_i = X"F6" or
d_i = X"EE" or
d_i = X"FE") and (rdy_i = '1')) then
next_state <= s236;
elsif ((d_i = X"E8") and (rdy_i = '1')) then
next_state <= s27;
elsif ((d_i = X"C8") and (rdy_i = '1')) then
next_state <= s27;
elsif ((d_i = X"4C" or
d_i = X"6C" or
d_i = X"7C") and (rdy_i = '1')) then
next_state <= jmp1;
elsif ((d_i = X"20") and (rdy_i = '1')) then
next_state <= s402;
elsif ((d_i = X"A9" or
d_i = X"A5" or
d_i = X"B5" or
d_i = X"AD" or
d_i = X"BD" or
d_i = X"B9" or
d_i = X"A1" or
d_i = X"B1" or
d_i = X"B2") and (rdy_i = '1')) then
next_state <= s203;
elsif ((d_i = X"A2" or
d_i = X"A6" or
d_i = X"B6" or
d_i = X"AE" or
d_i = X"BE") and (rdy_i = '1')) then
next_state <= s203;
elsif ((d_i = X"A0" or
d_i = X"A4" or
d_i = X"B4" or
d_i = X"AC" or
d_i = X"BC") and (rdy_i = '1')) then
next_state <= s203;
elsif ((d_i = X"46" or
d_i = X"56" or
d_i = X"4E" or
d_i = X"5E") and (rdy_i = '1')) then
next_state <= s405;
elsif ((d_i = X"EA") and (rdy_i = '1')) then
next_state <= s6;
elsif ((d_i = X"48") and (rdy_i = '1')) then
next_state <= s435;
elsif ((d_i = X"08") and (rdy_i = '1')) then
next_state <= s437;
elsif ((d_i = X"7A") and (rdy_i = '1')) then
next_state <= s439;
elsif ((d_i = X"26" or
d_i = X"36" or
d_i = X"2E" or
d_i = X"3E") and (rdy_i = '1')) then
next_state <= s405;
elsif ((d_i = X"66" or
d_i = X"76" or
d_i = X"6E" or
d_i = X"7E") and (rdy_i = '1')) then
next_state <= s405;
elsif ((d_i = X"40") and (rdy_i = '1')) then
next_state <= s425;
elsif ((d_i = X"60") and (rdy_i = '1')) then
next_state <= s430;
elsif ((d_i = X"E9" or
d_i = X"E5" or
d_i = X"F5" or
d_i = X"ED" or
d_i = X"FD" or
d_i = X"F9" or
d_i = X"E1" or
d_i = X"F1" or
d_i = X"F2") and (rdy_i = '1')) then
next_state <= s513;
elsif ((d_i = X"38") and (rdy_i = '1')) then
next_state <= s7;
elsif ((d_i = X"F8") and (rdy_i = '1')) then
next_state <= s8;
elsif ((d_i = X"85" or
d_i = X"95" or
d_i = X"8D" or
d_i = X"9D" or
d_i = X"99" or
d_i = X"81" or
d_i = X"91" or
d_i = X"92") and (rdy_i = '1')) then
next_state <= s178;
elsif ((d_i = X"86" or
d_i = X"96" or
d_i = X"8E") and (rdy_i = '1')) then
next_state <= s178;
elsif ((d_i = X"84" or
d_i = X"94" or
d_i = X"8C") and (rdy_i = '1')) then
next_state <= s178;
elsif ((d_i = X"AA") and (rdy_i = '1')) then
next_state <= s10;
elsif ((d_i = X"0A") and (rdy_i = '1')) then
next_state <= s420;
elsif ((d_i = X"4A") and (rdy_i = '1')) then
next_state <= s599;
elsif ((d_i = X"2A") and (rdy_i = '1')) then
next_state <= s600;
elsif ((d_i = X"6A") and (rdy_i = '1')) then
next_state <= s598;
elsif ((d_i = X"A8") and (rdy_i = '1')) then
next_state <= s10;
elsif ((d_i = X"98") and (rdy_i = '1')) then
next_state <= s10;
elsif ((d_i = X"BA") and (rdy_i = '1')) then
next_state <= s10;
elsif ((d_i = X"8A") and (rdy_i = '1')) then
next_state <= s10;
elsif ((d_i = X"9A") and (rdy_i = '1')) then
next_state <= s10;
elsif ((d_i = X"DA") and (rdy_i = '1')) then
next_state <= s435;
elsif ((d_i = X"5A") and (rdy_i = '1')) then
next_state <= s435;
elsif ((d_i = X"68") and (rdy_i = '1')) then
next_state <= s439;
elsif ((d_i = X"FA") and (rdy_i = '1')) then
next_state <= s439;
elsif ((d_i = X"9C" or
d_i = X"9E" or
d_i = X"64" or
d_i = X"74") and (rdy_i = '1')) then
next_state <= s178;
elsif ((d_i = X"3A") and (rdy_i = '1')) then
next_state <= s27;
elsif ((d_i = X"1A") and (rdy_i = '1')) then
next_state <= s27;
elsif ((d_i = X"EA") and (rdy_i = '1')) then
next_state <= s6;
elsif ((d_i = X"02" or
d_i = X"22" or
d_i = X"42" or
d_i = X"62" or
d_i = X"82" or
d_i = X"C2" or
d_i = X"E2") and (rdy_i = '1')) then
next_state <= s11;
elsif ((d_i = X"44") and (rdy_i = '1')) then
next_state <= s12;
elsif ((d_i = X"54" or
d_i = X"D4" or
d_i = X"F4") and (rdy_i = '1')) then
next_state <= s14;
elsif ((d_i = X"DC" or
d_i = X"FC") and (rdy_i = '1')) then
next_state <= s15;
elsif ((d_i = X"5C") and (rdy_i = '1')) then
next_state <= s16;
elsif ((d_i(3 downto 0) = X"3" or
d_i(3 downto 0) = X"B") and (rdy_i = '1')) then
next_state <= FETCH;
else
next_state <= FETCH;
end if;
when s6 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s6;
end if;
when s7 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s7;
end if;
when s8 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s8;
end if;
when s9 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s9;
end if;
when s10 =>
if (rdy_i = '1' and
zw_REG_OP = X"9A") then
next_state <= FETCH;
elsif (rdy_i = '1' and
zw_REG_OP = X"BA") then
next_state <= FETCH;
elsif (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s10;
end if;
when s13 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s13;
end if;
when s18 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s18;
end if;
when s19 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s19;
end if;
when s26 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s26;
end if;
when s27 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s27;
end if;
when s203 =>
if (rdy_i = '1' and
(zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR
zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR
zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR
zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) then
next_state <= s230;
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11" or
zw_REG_OP = X"12")) then
next_state <= FETCH;
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51" or
zw_REG_OP = X"52")) then
next_state <= FETCH;
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31" or
zw_REG_OP = X"32")) then
next_state <= FETCH;
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC" or
zw_REG_OP = X"D2")) then
next_state <= FETCH;
elsif (rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) then
next_state <= FETCH;
elsif (rdy_i = '1' and
(zw_REG_OP = X"B5" OR
zw_REG_OP = X"B4" OR
zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR
zw_REG_OP = X"35" OR
zw_REG_OP = X"D5")) then
next_state <= s219;
elsif (rdy_i = '1' and
(zw_REG_OP = X"AD" OR
zw_REG_OP = X"AE" OR
zw_REG_OP = X"AC" OR
zw_REG_OP = X"4D" OR
zw_REG_OP = X"0D" OR
zw_REG_OP = X"2D" OR
zw_REG_OP = X"CD" OR
zw_REG_OP = X"EC" OR
zw_REG_OP = X"CC")) then
next_state <= s204;
elsif (rdy_i = '1' and
(zw_REG_OP = X"BD" OR
zw_REG_OP = X"BC" OR
zw_REG_OP = X"5D" OR
zw_REG_OP = X"1D" OR
zw_REG_OP = X"3D" OR
zw_REG_OP = X"DD")) then
next_state <= s212;
elsif (rdy_i = '1' and
(zw_REG_OP = X"B9" OR
zw_REG_OP = X"BE" OR
zw_REG_OP = X"59" OR
zw_REG_OP = X"19" OR
zw_REG_OP = X"39" OR
zw_REG_OP = X"D9")) then
next_state <= s212;
elsif (rdy_i = '1' and
(zw_REG_OP = X"B1" OR
zw_REG_OP = X"51" OR
zw_REG_OP = X"11" OR
zw_REG_OP = X"31" OR
zw_REG_OP = X"D1")) then
next_state <= s216;
elsif (rdy_i = '1' and
(zw_REG_OP = X"A1" OR
zw_REG_OP = X"41" OR
zw_REG_OP = X"01" OR
zw_REG_OP = X"21" OR
zw_REG_OP = X"C1")) then
next_state <= s220;
elsif (rdy_i = '1' and
zw_REG_OP = X"B6") then
next_state <= s219;
elsif (rdy_i = '1' and
(zw_REG_OP = X"32" OR
zw_REG_OP = X"D2" OR
zw_REG_OP = X"52" OR
zw_REG_OP = X"B2" OR
zw_REG_OP = X"12")) then
next_state <= s229;
else
next_state <= s203;
end if;
when s204 =>
if (rdy_i = '1') then
next_state <= s230;
else
next_state <= s204;
end if;
when s212 =>
if (rdy_i = '1') then
next_state <= s231;
else
next_state <= s212;
end if;
when s216 =>
if (rdy_i = '1') then
next_state <= s228;
else
next_state <= s216;
end if;
when s219 =>
if (rdy_i = '1') then
next_state <= s230;
else
next_state <= s219;
end if;
when s220 =>
if (rdy_i = '1') then
next_state <= s227;
else
next_state <= s220;
end if;
when s227 =>
if (rdy_i = '1') then
next_state <= s204;
else
next_state <= s227;
end if;
when s228 =>
if (rdy_i = '1') then
next_state <= s231;
else
next_state <= s228;
end if;
when s230 =>
if ((rdy_i = '1') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11" or
zw_REG_OP = X"12")) then
next_state <= FETCH;
elsif ((rdy_i = '1') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51" or
zw_REG_OP = X"52")) then
next_state <= FETCH;
elsif ((rdy_i = '1') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31" or
zw_REG_OP = X"32")) then
next_state <= FETCH;
elsif ((rdy_i = '1') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC" or
zw_REG_OP = X"D2")) then
next_state <= FETCH;
elsif (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s230;
end if;
when s231 =>
if ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11" or
zw_REG_OP = X"12")) then
next_state <= FETCH;
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51" or
zw_REG_OP = X"52")) then
next_state <= FETCH;
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31" or
zw_REG_OP = X"32")) then
next_state <= FETCH;
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC" or
zw_REG_OP = X"D2")) then
next_state <= FETCH;
elsif (rdy_i = '1' AND
zw_b2(0) = '0') then
next_state <= FETCH;
elsif (rdy_i = '1') then
next_state <= s230;
else
next_state <= s231;
end if;
when s229 =>
if (rdy_i = '1') then
next_state <= s204;
else
next_state <= s229;
end if;
when s512 =>
if (rdy_i = '1' and
zw_REG_OP = X"65") then
next_state <= s586;
elsif (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '0') then
next_state <= FETCH;
elsif (rdy_i = '1' and
zw_REG_OP = X"75") then
next_state <= s582;
elsif (rdy_i = '1' and
zw_REG_OP = X"6D") then
next_state <= s554;
elsif (rdy_i = '1' and
zw_REG_OP = X"7D") then
next_state <= s578;
elsif (rdy_i = '1' and
zw_REG_OP = X"79") then
next_state <= s578;
elsif (rdy_i = '1' and
zw_REG_OP = X"71") then
next_state <= s581;
elsif (rdy_i = '1' and
zw_REG_OP = X"61") then
next_state <= s583;
elsif (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '1') then
next_state <= s601;
elsif (rdy_i = '1' and
zw_REG_OP = X"72") then
next_state <= s580;
else
next_state <= s512;
end if;
when s554 =>
if (rdy_i = '1') then
next_state <= s586;
else
next_state <= s554;
end if;
when s578 =>
if (rdy_i = '1') then
next_state <= s585;
else
next_state <= s578;
end if;
when s581 =>
if (rdy_i = '1') then
next_state <= s587;
else
next_state <= s581;
end if;
when s582 =>
if (rdy_i = '1') then
next_state <= s586;
else
next_state <= s582;
end if;
when s583 =>
if (rdy_i = '1') then
next_state <= s584;
else
next_state <= s583;
end if;
when s584 =>
if (rdy_i = '1') then
next_state <= s554;
else
next_state <= s584;
end if;
when s585 =>
if (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') then
next_state <= FETCH;
elsif (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') then
next_state <= s601;
elsif (rdy_i = '1') then
next_state <= s586;
else
next_state <= s585;
end if;
when s586 =>
if (rdy_i = '1' and
reg_F(3) = '0') then
next_state <= FETCH;
elsif (rdy_i = '1' and
reg_F(3) = '1') then
next_state <= s601;
else
next_state <= s586;
end if;
when s587 =>
if (rdy_i = '1') then
next_state <= s585;
else
next_state <= s587;
end if;
when s580 =>
if (rdy_i = '1') then
next_state <= s554;
else
next_state <= s580;
end if;
when s178 =>
if (rdy_i = '1' and
(zw_REG_OP = X"85" OR
zw_REG_OP = X"86" OR
zw_REG_OP = X"64" OR
zw_REG_OP = X"84")) then
next_state <= s197;
elsif (rdy_i = '1' and
(zw_REG_OP = X"95" OR
zw_REG_OP = X"74" OR
zw_REG_OP = X"94")) then
next_state <= s198;
elsif (rdy_i = '1' and
(zw_REG_OP = X"8D" OR
zw_REG_OP = X"8E" OR
zw_REG_OP = X"9C" OR
zw_REG_OP = X"8C")) then
next_state <= s196;
elsif (rdy_i = '1' and
(zw_REG_OP = X"9D" OR
zw_REG_OP = X"9E")) then
next_state <= s194;
elsif (rdy_i = '1' and
zw_REG_OP = X"99") then
next_state <= s194;
elsif (rdy_i = '1' and
zw_REG_OP = X"91") then
next_state <= s195;
elsif (rdy_i = '1' and
zw_REG_OP = X"81") then
next_state <= s199;
elsif (rdy_i = '1' and
zw_REG_OP = X"96") then
next_state <= s198;
elsif (rdy_i = '1' and
zw_REG_OP = X"92") then
next_state <= s214;
else
next_state <= s178;
end if;
when s194 =>
if (rdy_i = '1') then
next_state <= s208;
else
next_state <= s194;
end if;
when s195 =>
if (rdy_i = '1') then
next_state <= s206;
else
next_state <= s195;
end if;
when s196 =>
if (rdy_i = '1') then
next_state <= s200;
else
next_state <= s196;
end if;
when s197 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s197;
end if;
when s198 =>
if (rdy_i = '1') then
next_state <= s207;
else
next_state <= s198;
end if;
when s199 =>
if (rdy_i = '1') then
next_state <= s205;
else
next_state <= s199;
end if;
when s200 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s200;
end if;
when s205 =>
if (rdy_i = '1') then
next_state <= s209;
else
next_state <= s205;
end if;
when s206 =>
if (rdy_i = '1') then
next_state <= s208;
else
next_state <= s206;
end if;
when s207 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s207;
end if;
when s208 =>
if (rdy_i = '1') then
next_state <= s213;
end if;
when s209 =>
if (rdy_i = '1') then
next_state <= s213;
end if;
when s213 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s213;
end if;
when s214 =>
if (rdy_i = '1') then
next_state <= s196;
else
next_state <= s214;
end if;
when s513 =>
if (rdy_i = '1' and
zw_REG_OP = X"E5") then
next_state <= s596;
elsif (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '0') then
next_state <= FETCH;
elsif (rdy_i = '1' and
zw_REG_OP = X"F5") then
next_state <= s591;
elsif (rdy_i = '1' and
zw_REG_OP = X"ED") then
next_state <= s588;
elsif (rdy_i = '1' and
zw_REG_OP = X"FD") then
next_state <= s589;
elsif (rdy_i = '1' and
zw_REG_OP = X"F9") then
next_state <= s589;
elsif (rdy_i = '1' and
zw_REG_OP = X"F1") then
next_state <= s590;
elsif (rdy_i = '1' and
zw_REG_OP = X"E1") then
next_state <= s592;
elsif (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '1') then
next_state <= s602;
elsif (rdy_i = '1' and
zw_REG_OP = X"F2") then
next_state <= s597;
else
next_state <= s513;
end if;
when s588 =>
if (rdy_i = '1') then
next_state <= s596;
else
next_state <= s588;
end if;
when s589 =>
if (rdy_i = '1') then
next_state <= s595;
else
next_state <= s589;
end if;
when s590 =>
if (rdy_i = '1') then
next_state <= s593;
else
next_state <= s590;
end if;
when s591 =>
if (rdy_i = '1') then
next_state <= s596;
else
next_state <= s591;
end if;
when s592 =>
if (rdy_i = '1') then
next_state <= s594;
else
next_state <= s592;
end if;
when s593 =>
if (rdy_i = '1') then
next_state <= s595;
else
next_state <= s593;
end if;
when s594 =>
if (rdy_i = '1') then
next_state <= s588;
else
next_state <= s594;
end if;
when s595 =>
if (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') then
next_state <= FETCH;
elsif (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') then
next_state <= s602;
elsif (rdy_i = '1') then
next_state <= s596;
else
next_state <= s595;
end if;
when s596 =>
if (rdy_i = '1' and
reg_F(3) = '0') then
next_state <= FETCH;
elsif (rdy_i = '1' and
reg_F(3) = '1') then
next_state <= s602;
else
next_state <= s596;
end if;
when s597 =>
if (rdy_i = '1') then
next_state <= s588;
else
next_state <= s597;
end if;
when s405 =>
if (rdy_i = '1' and
(zw_REG_OP = X"1E" or
zw_REG_OP = X"7E" or
zw_REG_OP = X"3E" or
zw_REG_OP = X"5E")) then
next_state <= s410;
elsif (rdy_i = '1' and
(zw_REG_OP = X"06" or zw_REG_OP = X"66" or
zw_REG_OP = X"26" or zw_REG_OP = X"46" or
zw_REG_OP = X"04" or zw_REG_OP = X"14")) then
next_state <= s415;
elsif (rdy_i = '1' and
(zw_REG_OP = X"16" or
zw_REG_OP = X"76" or
zw_REG_OP = X"36" or
zw_REG_OP = X"56")) then
next_state <= s411;
elsif (rdy_i = '1' and
(zw_REG_OP = X"0E" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"4E"or
zw_REG_OP = X"0C" or
zw_REG_OP = X"1C")) then
next_state <= s408;
elsif (rdy_i = '1' and
zw_REG_OP (3 downto 0) = X"7") then
next_state <= s415;
else
next_state <= s405;
end if;
when s408 =>
if (rdy_i = '1') then
next_state <= s415;
else
next_state <= s408;
end if;
when s410 =>
if (rdy_i = '1') then
next_state <= s414;
else
next_state <= s410;
end if;
when s411 =>
if (rdy_i = '1') then
next_state <= s415;
else
next_state <= s411;
end if;
when s414 =>
if (rdy_i = '1') then
next_state <= s417;
else
next_state <= s414;
end if;
when s415 =>
if (rdy_i = '1') then
next_state <= s417;
else
next_state <= s415;
end if;
when s417 =>
if ((rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"16" or
zw_REG_OP = X"0E" or
zw_REG_OP = X"1E")) and (rdy_i = '1')) then
next_state <= s419;
elsif ((rdy_i = '1' and
(zw_REG_OP = X"46" or
zw_REG_OP = X"56" or
zw_REG_OP = X"4E" or
zw_REG_OP = X"5E")) and (rdy_i = '1')) then
next_state <= s419;
elsif ((rdy_i = '1' and
(zw_REG_OP = X"26" or
zw_REG_OP = X"36" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"3E")) and (rdy_i = '1')) then
next_state <= s419;
elsif ((rdy_i = '1' and
(zw_REG_OP = X"66" or
zw_REG_OP = X"76" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"7E")) and (rdy_i = '1')) then
next_state <= s419;
elsif ((rdy_i = '1' and
zw_REG_OP (7) = '0' and
zw_REG_OP (3 downto 0) = X"7") and (rdy_i = '1')) then
next_state <= s419;
elsif ((rdy_i = '1' and
zw_REG_OP (7) = '1' and
zw_REG_OP (3 downto 0) = X"7") and (rdy_i = '1')) then
next_state <= s419;
elsif ((rdy_i = '1' and
(zw_REG_OP = X"14" or
zw_REG_OP = X"1C")) and (rdy_i = '1')) then
next_state <= s419;
elsif ((rdy_i = '1' and
(zw_REG_OP = X"04" or
zw_REG_OP = X"0C")) and (rdy_i = '1')) then
next_state <= s419;
else
next_state <= s417;
end if;
when s419 =>
if ((zw_REG_OP (3 downto 0) = X"7") and (rdy_i = '1')) then
next_state <= FETCH;
elsif (((zw_REG_OP = X"14" or
zw_REG_OP = X"04" or
zw_REG_OP = X"0C" or
zw_REG_OP = X"1C")) and (rdy_i = '1')) then
next_state <= FETCH;
elsif (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s419;
end if;
when s420 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s420;
end if;
when s598 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s598;
end if;
when s599 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s599;
end if;
when s600 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s600;
end if;
when s268 =>
if (rdy_i = '1' and (
(reg_F(0) = '1' and zw_REG_OP = X"90") or (reg_F(0) = '0' and zw_REG_OP = X"B0") or
(reg_F(1) = '0' and zw_REG_OP = X"F0") or (reg_F(7) = '0' and zw_REG_OP = X"30") or
(reg_F(1) = '1' and zw_REG_OP = X"D0") or (reg_F(7) = '1' and zw_REG_OP = X"10") or
(reg_F(6) = '1' and zw_REG_OP = X"50") or (reg_F(6) = '0' and zw_REG_OP = X"70"))) then
next_state <= FETCH;
elsif (rdy_i = '1') then
next_state <= s305;
else
next_state <= s268;
end if;
when s305 =>
if (rdy_i = '1' and
zw_b3 = adr_nxt_pc_i (15 downto 8)) then
next_state <= FETCH;
elsif (rdy_i = '1') then
next_state <= s306;
else
next_state <= s305;
end if;
when s306 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s306;
end if;
when jmp1 =>
if (rdy_i = '1' and
zw_REG_OP = X"4C") then
next_state <= jmp_ex;
elsif (rdy_i = '1' and
zw_REG_OP = X"6C") then
next_state <= jmp2_1;
elsif (rdy_i = '1' and
zw_REG_OP = X"7C") then
next_state <= jmp2_2;
else
next_state <= jmp1;
end if;
when jmp2_1 =>
if (rdy_i = '1') then
next_state <= jmp3_1;
else
next_state <= jmp2_1;
end if;
when jmp4_12 =>
if (rdy_i = '1') then
next_state <= jmp_ex;
else
next_state <= jmp4_12;
end if;
when jmp_ex =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= jmp_ex;
end if;
when jmp2_2 =>
if (rdy_i = '1') then
next_state <= jmp3_2;
else
next_state <= jmp2_2;
end if;
when jmp3_1 =>
if (rdy_i = '1') then
next_state <= jmp4_12;
else
next_state <= jmp3_1;
end if;
when s402 =>
if (rdy_i = '1') then
next_state <= s421;
else
next_state <= s402;
end if;
when s421 =>
if (rdy_i = '1') then
next_state <= s422;
else
next_state <= s421;
end if;
when s422 =>
if (rdy_i = '1') then
next_state <= s423;
else
next_state <= s422;
end if;
when s423 =>
if (rdy_i = '1') then
next_state <= s424;
else
next_state <= s423;
end if;
when s424 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s424;
end if;
when s362 =>
if (rdy_i = '1') then
next_state <= s234;
else
next_state <= s362;
end if;
when s221 =>
if (rdy_i = '1' and
zw_REG_OP = X"34") then
next_state <= s233;
elsif (rdy_i = '1' and
zw_REG_OP = X"3C") then
next_state <= s232;
elsif (rdy_i = '1' and
zw_REG_OP = X"24") then
next_state <= s234;
elsif (rdy_i = '1' and
zw_REG_OP = X"2C") then
next_state <= s362;
elsif (rdy_i = '1' and
zw_REG_OP = X"89") then
next_state <= FETCH;
else
next_state <= s221;
end if;
when s232 =>
if (rdy_i = '1') then
next_state <= s235;
else
next_state <= s232;
end if;
when s233 =>
if (rdy_i = '1') then
next_state <= s234;
else
next_state <= s233;
end if;
when s234 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s234;
end if;
when s235 =>
if (rdy_i = '1' AND
zw_b2(0) = '0') then
next_state <= FETCH;
elsif (rdy_i = '1') then
next_state <= s234;
else
next_state <= s235;
end if;
when brk1 =>
if (rdy_i = '1') then
next_state <= brk2;
else
next_state <= brk1;
end if;
when brk2 =>
if (rdy_i = '1') then
next_state <= brk3;
else
next_state <= brk2;
end if;
when brk3 =>
if (rdy_i = '1') then
next_state <= brk4;
else
next_state <= brk3;
end if;
when brk4 =>
if (rdy_i = '1') then
next_state <= brk5;
else
next_state <= brk4;
end if;
when brk6 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= brk6;
end if;
when brk5 =>
if (rdy_i = '1') then
next_state <= brk6;
else
next_state <= brk5;
end if;
when s425 =>
if (rdy_i = '1') then
next_state <= s426;
else
next_state <= s425;
end if;
when s426 =>
if (rdy_i = '1') then
next_state <= s427;
else
next_state <= s426;
end if;
when s427 =>
if (rdy_i = '1') then
next_state <= s428;
else
next_state <= s427;
end if;
when s428 =>
if (rdy_i = '1') then
next_state <= s429;
else
next_state <= s428;
end if;
when s429 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s429;
end if;
when s430 =>
if (rdy_i = '1') then
next_state <= s431;
else
next_state <= s430;
end if;
when s431 =>
if (rdy_i = '1') then
next_state <= s432;
else
next_state <= s431;
end if;
when s432 =>
if (rdy_i = '1') then
next_state <= s433;
else
next_state <= s432;
end if;
when s433 =>
if (rdy_i = '1') then
next_state <= s434;
else
next_state <= s433;
end if;
when s434 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s434;
end if;
when s236 =>
if (rdy_i = '1' and
(zw_REG_OP = X"C6" OR
zw_REG_OP = X"E6")) then
next_state <= s346;
elsif (rdy_i = '1' and
(zw_REG_OP = X"D6" OR
zw_REG_OP = X"F6")) then
next_state <= s248;
elsif (rdy_i = '1' and
(zw_REG_OP = X"CE" OR
zw_REG_OP = X"EE")) then
next_state <= s245;
elsif (rdy_i = '1' and
(zw_REG_OP = X"DE" OR
zw_REG_OP = X"FE")) then
next_state <= s246;
else
next_state <= s236;
end if;
when s245 =>
if (rdy_i = '1') then
next_state <= s346;
else
next_state <= s245;
end if;
when s246 =>
if (rdy_i = '1') then
next_state <= s345;
else
next_state <= s246;
end if;
when s248 =>
if (rdy_i = '1') then
next_state <= s346;
else
next_state <= s248;
end if;
when s345 =>
if (rdy_i = '1') then
next_state <= s346;
else
next_state <= s345;
end if;
when s346 =>
if (rdy_i = '1') then
next_state <= s252;
else
next_state <= s346;
end if;
when s252 =>
if (rdy_i = '1') then
next_state <= s253;
else
next_state <= s252;
end if;
when s253 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s253;
end if;
when s435 =>
if (rdy_i = '1') then
next_state <= s436;
else
next_state <= s435;
end if;
when s436 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s436;
end if;
when s437 =>
if (rdy_i = '1') then
next_state <= s438;
else
next_state <= s437;
end if;
when s438 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s438;
end if;
when s439 =>
if (rdy_i = '1') then
next_state <= s440;
else
next_state <= s439;
end if;
when s440 =>
if (rdy_i = '1') then
next_state <= s441;
else
next_state <= s440;
end if;
when s441 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s441;
end if;
when s442 =>
if (rdy_i = '1') then
next_state <= s443;
else
next_state <= s442;
end if;
when s443 =>
if (rdy_i = '1') then
next_state <= s444;
else
next_state <= s443;
end if;
when s444 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s444;
end if;
when irq1 =>
if (rdy_i = '1') then
next_state <= irq2;
else
next_state <= irq1;
end if;
when irq2 =>
if (rdy_i = '1') then
next_state <= irq3;
else
next_state <= irq2;
end if;
when irq3 =>
if (rdy_i = '1') then
next_state <= irq4;
else
next_state <= irq3;
end if;
when irq5b =>
if (rdy_i = '1') then
next_state <= irq6;
else
next_state <= irq5b;
end if;
when irq5a =>
if (rdy_i = '1') then
next_state <= irq6;
else
next_state <= irq5a;
end if;
when irq4 =>
if (rdy_i = '1' and
nmi_i = '1') then
next_state <= irq5a;
elsif (rdy_i = '1') then
next_state <= irq5b;
else
next_state <= irq4;
end if;
when irq6 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= irq6;
end if;
when s11 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s11;
end if;
when s12 =>
if (rdy_i = '1') then
next_state <= s20;
else
next_state <= s12;
end if;
when s20 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s20;
end if;
when s14 =>
if (rdy_i = '1') then
next_state <= s21;
else
next_state <= s14;
end if;
when s21 =>
if (rdy_i = '1') then
next_state <= s23;
else
next_state <= s21;
end if;
when s23 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s23;
end if;
when s15 =>
if (rdy_i = '1') then
next_state <= s25;
else
next_state <= s15;
end if;
when s25 =>
if (rdy_i = '1') then
next_state <= s28;
else
next_state <= s25;
end if;
when s28 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s28;
end if;
when s16 =>
if (rdy_i = '1') then
next_state <= s30;
else
next_state <= s16;
end if;
when s30 =>
if (rdy_i = '1') then
next_state <= s31;
else
next_state <= s30;
end if;
when s31 =>
if (rdy_i = '1') then
next_state <= s32;
else
next_state <= s31;
end if;
when s32 =>
if (rdy_i = '1') then
next_state <= s34;
else
next_state <= s32;
end if;
when s33 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s33;
end if;
when s34 =>
if (rdy_i = '1') then
next_state <= s36;
else
next_state <= s34;
end if;
when s36 =>
if (rdy_i = '1') then
next_state <= s33;
else
next_state <= s36;
end if;
when jmp3_2 =>
if (rdy_i = '1') then
next_state <= jmp4_12;
else
next_state <= jmp3_2;
end if;
when s601 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s601;
end if;
when s602 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s602;
end if;
when s270 =>
if (rdy_i = '1') then
next_state <= s271;
else
next_state <= s270;
end if;
when s307 =>
if (rdy_i = '1' and
zw_b3 = adr_nxt_pc_i (15 downto 8)) then
next_state <= FETCH;
elsif (rdy_i = '1') then
next_state <= s309;
else
next_state <= s307;
end if;
when s308 =>
if (rdy_i = '1' and (
(zw_b1(0) = '0' and zw_REG_OP = X"8F") or
(zw_b1(1) = '0' and zw_REG_OP = X"9F") or
(zw_b1(2) = '0' and zw_REG_OP = X"AF") or
(zw_b1(3) = '0' and zw_REG_OP = X"BF") or
(zw_b1(4) = '0' and zw_REG_OP = X"CF") or
(zw_b1(5) = '0' and zw_REG_OP = X"DF") or
(zw_b1(6) = '0' and zw_REG_OP = X"EF") or
(zw_b1(7) = '0' and zw_REG_OP = X"FF") or
(zw_b1(0) = '1' and zw_REG_OP = X"0F") or
(zw_b1(1) = '1' and zw_REG_OP = X"1F") or
(zw_b1(2) = '1' and zw_REG_OP = X"2F") or
(zw_b1(3) = '1' and zw_REG_OP = X"3F") or
(zw_b1(4) = '1' and zw_REG_OP = X"4F") or
(zw_b1(5) = '1' and zw_REG_OP = X"5F") or
(zw_b1(6) = '1' and zw_REG_OP = X"6F") or
(zw_b1(7) = '1' and zw_REG_OP = X"7F"))) then
next_state <= FETCH;
elsif (rdy_i = '1') then
next_state <= s307;
else
next_state <= s308;
end if;
when s271 =>
if (rdy_i = '1') then
next_state <= s272;
else
next_state <= s271;
end if;
when s272 =>
if (rdy_i = '1') then
next_state <= s308;
else
next_state <= s272;
end if;
when s309 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s309;
end if;
when RES2 =>
next_state <= s544;
when others =>
next_state <= RES;
end case;
end process nextstate_proc;
-----------------------------------------------------------------
output_proc : process (
adr_nxt_pc_i,
adr_pc_i,
adr_sp_i,
current_state,
d_alu_i,
d_alu_prio_i,
d_i,
d_regs_out_i,
irq_n_i,
nmi_i,
q_a_i,
q_x_i,
q_y_i,
rdy_i,
reg_F,
reg_sel_pc_in,
reg_sel_pc_val,
reg_sel_rb_in,
reg_sel_rb_out,
reg_sel_reg,
reg_sel_sp_as,
reg_sel_sp_in,
sig_PC,
zw_ALU,
zw_ALU1,
zw_ALU2,
zw_ALU3,
zw_ALU4,
zw_ALU5,
zw_ALU6,
zw_REG_OP,
zw_b1,
zw_b2,
zw_b3,
zw_b4,
zw_w1,
zw_w3
)
-----------------------------------------------------------------
begin
-- Default Assignment
a_o <= sig_PC;
adr_o <= X"0000";
ch_a_o <= X"00";
ch_b_o <= X"00";
d_regs_in_o <= X"00";
ld_o <= "00";
ld_pc_o <= '0';
ld_sp_o <= '0';
load_regs_o <= '0';
offset_o <= X"0000";
rst_nmi_o <= '0';
sel_pc_in_o <= reg_sel_pc_in;
sel_pc_val_o <= reg_sel_pc_val;
sel_rb_in_o <= reg_sel_rb_in;
sel_rb_out_o <= reg_sel_rb_out;
sel_reg_o <= reg_sel_reg;
sel_sp_as_o <= reg_sel_sp_as;
sel_sp_in_o <= reg_sel_sp_in;
-- Default Assignment To Internals
sig_D_OUT <= X"00";
sig_RD <= '1';
sig_RWn <= '1';
sig_SYNC <= '0';
sig_WR <= '0';
zw_100_a <= '0';
zw_100_alu <= '0';
zw_100_d <= '0';
zw_50_a <= '0';
zw_50_alu <= '0';
zw_50_d <= '0';
zw_ALU <= "00" & X"00";
zw_ALU1 <= "00" & X"00";
zw_ALU2 <= "00" & X"00";
zw_ALU3 <= "00" & X"00";
zw_ALU4 <= "00" & X"00";
zw_ALU5 <= "00" & X"00";
zw_ALU6 <= "00" & X"00";
-- Combined Actions
case current_state is
when s544 =>
ld_sp_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
end if;
when s545 =>
adr_o <= X"FFFB";
ld_pc_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
end if;
when s546 =>
ld_pc_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
end if;
when s549 =>
ld_pc_o <= '1';
if (rdy_i = '1') then
adr_o <= d_i & zw_w1 (7 downto 0);
ld_o <= "11";
sig_SYNC <= '1';
end if;
when s550 =>
ld_sp_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
end if;
when RES =>
sig_SYNC <= '1';
when FETCH =>
sig_RWn <= '1';
sig_RD <= '1';
sig_SYNC <= NOT (rdy_i);
ld_pc_o <= '1';
if ((d_i = X"00") and (rdy_i = '1')) then
ld_o <= "11";
elsif ((nmi_i = '1') and (rdy_i = '1')) then
ld_o <= "11";
elsif ((irq_n_i = '0' and
reg_F(2) = '0') and (rdy_i = '1')) then
ld_o <= "11";
elsif ((d_i = X"58") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"28") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"78") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"69" or
d_i = X"65" or
d_i = X"75" or
d_i = X"6D" or
d_i = X"7D" or
d_i = X"79" or
d_i = X"61" or
d_i = X"71" or
d_i = X"72") and (rdy_i = '1')) then
ld_o <= "11";
elsif ((d_i = X"06" or
d_i = X"16" or
d_i = X"0E" or
d_i = X"1E" or
d_i (3 downto 0) = X"7" or
d_i = X"14" or
d_i = X"04" or
d_i = X"0C" or
d_i = X"1C") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"90" or
d_i = X"B0" or
d_i = X"F0" or
d_i = X"30" or
d_i = X"D0" or
d_i = X"10" or
d_i = X"50" or
d_i = X"70" or
d_i = X"80") and (rdy_i = '1')) then
ld_o <= "11";
elsif ((d_i = X"24" or
d_i = X"2C" or
d_i = X"3C" or
d_i = X"34" or
d_i = X"89") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"18") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"D8") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"8F" or
d_i = X"9F" or
d_i = X"AF" or
d_i = X"BF" or
d_i = X"CF" or
d_i = X"DF" or
d_i = X"EF" or
d_i = X"FF" or
d_i = X"0F" or
d_i = X"1F" or
d_i = X"2F" or
d_i = X"3F" or
d_i = X"4F" or
d_i = X"5F" or
d_i = X"6F" or
d_i = X"7F") and (rdy_i = '1')) then
ld_o <= "11";
elsif ((d_i = X"B8") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"E0" or
d_i = X"E4" or
d_i = X"EC") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"C0" or
d_i = X"C4" or
d_i = X"CC") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"C6" or
d_i = X"D6" or
d_i = X"CE" or
d_i = X"DE") and (rdy_i = '1')) then
ld_o <= "11";
elsif ((d_i = X"CA") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"88") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"49" or
d_i = X"45" or
d_i = X"55" or
d_i = X"4D" or
d_i = X"5D" or
d_i = X"59" or
d_i = X"41" or
d_i = X"51" or
d_i = X"09" or
d_i = X"05" or
d_i = X"15" or
d_i = X"0D" or
d_i = X"1D" or
d_i = X"19" or
d_i = X"01" or
d_i = X"11" or
d_i = X"29" or
d_i = X"25" or
d_i = X"35" or
d_i = X"2D" or
d_i = X"3D" or
d_i = X"39" or
d_i = X"21" or
d_i = X"31" or
d_i = X"C9" or
d_i = X"C5" or
d_i = X"D5" or
d_i = X"CD" or
d_i = X"DD" or
d_i = X"D9" or
d_i = X"C1" or
d_i = X"D1" or
d_i = X"32" or
d_i = X"D2" or
d_i = X"52" or
d_i = X"12") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"E6" or
d_i = X"F6" or
d_i = X"EE" or
d_i = X"FE") and (rdy_i = '1')) then
ld_o <= "11";
elsif ((d_i = X"E8") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"C8") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"4C" or
d_i = X"6C" or
d_i = X"7C") and (rdy_i = '1')) then
ld_o <= "11";
elsif ((d_i = X"20") and (rdy_i = '1')) then
ld_o <= "11";
elsif ((d_i = X"A9" or
d_i = X"A5" or
d_i = X"B5" or
d_i = X"AD" or
d_i = X"BD" or
d_i = X"B9" or
d_i = X"A1" or
d_i = X"B1" or
d_i = X"B2") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"A2" or
d_i = X"A6" or
d_i = X"B6" or
d_i = X"AE" or
d_i = X"BE") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"A0" or
d_i = X"A4" or
d_i = X"B4" or
d_i = X"AC" or
d_i = X"BC") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"46" or
d_i = X"56" or
d_i = X"4E" or
d_i = X"5E") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"EA") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"48") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"08") and (rdy_i = '1')) then
ld_o <= "11";
elsif ((d_i = X"7A") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"26" or
d_i = X"36" or
d_i = X"2E" or
d_i = X"3E") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"66" or
d_i = X"76" or
d_i = X"6E" or
d_i = X"7E") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"40") and (rdy_i = '1')) then
ld_o <= "11";
elsif ((d_i = X"60") and (rdy_i = '1')) then
ld_o <= "11";
elsif ((d_i = X"E9" or
d_i = X"E5" or
d_i = X"F5" or
d_i = X"ED" or
d_i = X"FD" or
d_i = X"F9" or
d_i = X"E1" or
d_i = X"F1" or
d_i = X"F2") and (rdy_i = '1')) then
ld_o <= "11";
elsif ((d_i = X"38") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"F8") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"85" or
d_i = X"95" or
d_i = X"8D" or
d_i = X"9D" or
d_i = X"99" or
d_i = X"81" or
d_i = X"91" or
d_i = X"92") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"86" or
d_i = X"96" or
d_i = X"8E") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"84" or
d_i = X"94" or
d_i = X"8C") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"AA") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"0A") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"4A") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"2A") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"6A") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"A8") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"98") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"BA") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"8A") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"9A") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"DA") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"5A") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"68") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"FA") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"9C" or
d_i = X"9E" or
d_i = X"64" or
d_i = X"74") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"3A") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"1A") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"EA") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"02" or
d_i = X"22" or
d_i = X"42" or
d_i = X"62" or
d_i = X"82" or
d_i = X"C2" or
d_i = X"E2") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"44") and (rdy_i = '1')) then
ld_o <= "11";
elsif ((d_i = X"54" or
d_i = X"D4" or
d_i = X"F4") and (rdy_i = '1')) then
ld_o <= "11";
elsif ((d_i = X"DC" or
d_i = X"FC") and (rdy_i = '1')) then
ld_o <= "11";
elsif ((d_i = X"5C") and (rdy_i = '1')) then
ld_o <= "11";
elsif ((d_i(3 downto 0) = X"3" or
d_i(3 downto 0) = X"B") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
end if;
when s6 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s7 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s8 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s9 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s10 =>
if (rdy_i = '1' and
zw_REG_OP = X"9A") then
adr_o <= X"01" & d_regs_out_i;
ld_o <= "11";
ld_sp_o <= '1';
sig_SYNC <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"BA") then
d_regs_in_o <= adr_sp_i (7 downto 0);
ch_a_o <= adr_sp_i (7 downto 0);
ch_b_o <= X"00";
load_regs_o <= '1';
sig_SYNC <= '1';
elsif (rdy_i = '1') then
ch_a_o <= d_regs_out_i;
ch_b_o <= X"00";
load_regs_o <= '1';
sig_SYNC <= '1';
end if;
when s13 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s18 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s19 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s26 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s27 =>
if (rdy_i = '1') then
d_regs_in_o <= d_alu_i;
ch_a_o <= d_regs_out_i;
ch_b_o <= zw_b4;
load_regs_o <= '1';
sig_SYNC <= '1';
end if;
when s203 =>
if (rdy_i = '1' and
(zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR
zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR
zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR
zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11" or
zw_REG_OP = X"12")) then
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= d_i OR q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i OR q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51" or
zw_REG_OP = X"52")) then
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= d_i XOR q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i XOR q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31" or
zw_REG_OP = X"32")) then
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= d_i AND q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i AND q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC" or
zw_REG_OP = X"D2")) then
ld_o <= "11";
ld_pc_o <= '1';
zw_ALU (8 downto 0) <= unsigned ('0' & d_regs_out_i) + unsigned ('0' & NOT (d_i)) + 1;
sig_SYNC <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) then
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= d_i;
load_regs_o <= '1';
ch_a_o <= d_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"B5" OR
zw_REG_OP = X"B4" OR
zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR
zw_REG_OP = X"35" OR
zw_REG_OP = X"D5")) then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"AD" OR
zw_REG_OP = X"AE" OR
zw_REG_OP = X"AC" OR
zw_REG_OP = X"4D" OR
zw_REG_OP = X"0D" OR
zw_REG_OP = X"2D" OR
zw_REG_OP = X"CD" OR
zw_REG_OP = X"EC" OR
zw_REG_OP = X"CC")) then
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"BD" OR
zw_REG_OP = X"BC" OR
zw_REG_OP = X"5D" OR
zw_REG_OP = X"1D" OR
zw_REG_OP = X"3D" OR
zw_REG_OP = X"DD")) then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"B9" OR
zw_REG_OP = X"BE" OR
zw_REG_OP = X"59" OR
zw_REG_OP = X"19" OR
zw_REG_OP = X"39" OR
zw_REG_OP = X"D9")) then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_y_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"B1" OR
zw_REG_OP = X"51" OR
zw_REG_OP = X"11" OR
zw_REG_OP = X"31" OR
zw_REG_OP = X"D1")) then
ch_a_o <= d_i;
ch_b_o <= X"01";
elsif (rdy_i = '1' and
(zw_REG_OP = X"A1" OR
zw_REG_OP = X"41" OR
zw_REG_OP = X"01" OR
zw_REG_OP = X"21" OR
zw_REG_OP = X"C1")) then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"B6") then
ch_a_o <= d_i;
ch_b_o <= q_y_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"32" OR
zw_REG_OP = X"D2" OR
zw_REG_OP = X"52" OR
zw_REG_OP = X"B2" OR
zw_REG_OP = X"12")) then
ch_a_o <= d_i;
ch_b_o <= X"01";
end if;
when s204 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s212 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s216 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= q_y_i;
end if;
when s219 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s227 =>
if (rdy_i = '1') then
ch_a_o <= zw_b1;
ch_b_o <= X"01";
end if;
when s228 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s230 =>
if ((rdy_i = '1') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11" or
zw_REG_OP = X"12")) then
d_regs_in_o <= d_i OR q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i OR q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
elsif ((rdy_i = '1') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51" or
zw_REG_OP = X"52")) then
d_regs_in_o <= d_i XOR q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i XOR q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
elsif ((rdy_i = '1') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31" or
zw_REG_OP = X"32")) then
d_regs_in_o <= d_i AND q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i AND q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
elsif ((rdy_i = '1') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC" or
zw_REG_OP = X"D2")) then
zw_ALU (8 downto 0) <= unsigned ('0' & d_regs_out_i) + unsigned ('0' & NOT (d_i)) + 1;
sig_SYNC <= '1';
elsif (rdy_i = '1') then
d_regs_in_o <= d_i;
load_regs_o <= '1';
ch_a_o <= d_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
end if;
when s231 =>
if ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11" or
zw_REG_OP = X"12")) then
d_regs_in_o <= d_i OR q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i OR q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51" or
zw_REG_OP = X"52")) then
d_regs_in_o <= d_i XOR q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i XOR q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31" or
zw_REG_OP = X"32")) then
d_regs_in_o <= d_i AND q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i AND q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC" or
zw_REG_OP = X"D2")) then
zw_ALU (8 downto 0) <= unsigned ('0' & d_regs_out_i) + unsigned ('0' & NOT (d_i)) + 1;
sig_SYNC <= '1';
elsif (rdy_i = '1' AND
zw_b2(0) = '0') then
d_regs_in_o <= d_i;
load_regs_o <= '1';
ch_a_o <= d_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
end if;
when s512 =>
ld_pc_o <= '1';
if (rdy_i = '1' and
zw_REG_OP = X"65") then
ld_o <= "11";
elsif (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '0') then
ld_o <= "11";
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(8 downto 0) <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0);
sig_SYNC <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"75") then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"6D") then
ld_o <= "11";
elsif (rdy_i = '1' and
zw_REG_OP = X"7D") then
ld_o <= "11";
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"79") then
ld_o <= "11";
ch_a_o <= d_i;
ch_b_o <= q_y_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"71") then
ch_a_o <= d_i;
ch_b_o <= X"01";
elsif (rdy_i = '1' and
zw_REG_OP = X"61") then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '1') then
ld_o <= "11";
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU5(3 downto 0)) + unsigned (zw_ALU4(8 downto 5));
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU3(8 downto 5));
zw_ALU4(8 downto 5) <= '0' & ((zw_ALU4(4))) & ((zw_ALU4(4))) & '0';
zw_ALU4(4) <= zw_ALU5(4) OR
(zw_ALU5(3) AND zw_ALU5(2)) OR
(zw_ALU5(3) AND zw_ALU5(1));
zw_ALU5(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & d_i(7 downto 4)) + (zw_ALU3(4));
zw_ALU3(8 downto 5) <= '0' & ((zw_ALU3(4))) & ((zw_ALU3(4))) & '0';
zw_ALU3(4) <= zw_ALU1(4) OR
(zw_ALU1(3) AND zw_ALU1(2)) OR
(zw_ALU1(3) AND zw_ALU1(1));
zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & d_i(3 downto 0)) + reg_F(0);
elsif (rdy_i = '1' and
zw_REG_OP = X"72") then
ch_a_o <= d_i;
ch_b_o <= X"01";
end if;
when s554 =>
ld_pc_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
end if;
when s578 =>
ld_pc_o <= '1';
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= X"01";
ld_o <= "11";
end if;
when s581 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= q_y_i;
end if;
when s582 =>
ld_pc_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
end if;
when s584 =>
if (rdy_i = '1') then
ch_a_o <= zw_b1;
ch_b_o <= X"01";
end if;
when s585 =>
if (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(8 downto 0) <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0);
sig_SYNC <= '1';
elsif (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU5(3 downto 0)) + unsigned (zw_ALU4(8 downto 5));
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU3(8 downto 5));
zw_ALU4(8 downto 5) <= '0' & ((zw_ALU4(4))) & ((zw_ALU4(4))) & '0';
zw_ALU4(4) <= zw_ALU5(4) OR
(zw_ALU5(3) AND zw_ALU5(2)) OR
(zw_ALU5(3) AND zw_ALU5(1));
zw_ALU5(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & d_i(7 downto 4)) + (zw_ALU3(4));
zw_ALU3(8 downto 5) <= '0' & ((zw_ALU3(4))) & ((zw_ALU3(4))) & '0';
zw_ALU3(4) <= zw_ALU1(4) OR
(zw_ALU1(3) AND zw_ALU1(2)) OR
(zw_ALU1(3) AND zw_ALU1(1));
zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & d_i(3 downto 0)) + reg_F(0);
end if;
when s586 =>
if (rdy_i = '1' and
reg_F(3) = '0') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(8 downto 0) <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0);
sig_SYNC <= '1';
elsif (rdy_i = '1' and
reg_F(3) = '1') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU5(3 downto 0)) + unsigned (zw_ALU4(8 downto 5));
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU3(8 downto 5));
zw_ALU4(8 downto 5) <= '0' & ((zw_ALU4(4))) & ((zw_ALU4(4))) & '0';
zw_ALU4(4) <= zw_ALU5(4) OR
(zw_ALU5(3) AND zw_ALU5(2)) OR
(zw_ALU5(3) AND zw_ALU5(1));
zw_ALU5(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & d_i(7 downto 4)) + (zw_ALU3(4));
zw_ALU3(8 downto 5) <= '0' & ((zw_ALU3(4))) & ((zw_ALU3(4))) & '0';
zw_ALU3(4) <= zw_ALU1(4) OR
(zw_ALU1(3) AND zw_ALU1(2)) OR
(zw_ALU1(3) AND zw_ALU1(1));
zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & d_i(3 downto 0)) + reg_F(0);
end if;
when s587 =>
ld_pc_o <= '1';
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= X"01";
ld_o <= "11";
end if;
when s178 =>
if (rdy_i = '1' and
(zw_REG_OP = X"85" OR
zw_REG_OP = X"86" OR
zw_REG_OP = X"64" OR
zw_REG_OP = X"84")) then
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= d_regs_out_i;
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"95" OR
zw_REG_OP = X"74" OR
zw_REG_OP = X"94")) then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"8D" OR
zw_REG_OP = X"8E" OR
zw_REG_OP = X"9C" OR
zw_REG_OP = X"8C")) then
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"9D" OR
zw_REG_OP = X"9E")) then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"99") then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_y_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"91") then
ch_a_o <= d_i;
ch_b_o <= X"01";
elsif (rdy_i = '1' and
zw_REG_OP = X"81") then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"96") then
ch_a_o <= d_i;
ch_b_o <= q_y_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"92") then
ch_a_o <= d_i;
ch_b_o <= X"01";
end if;
when s194 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s195 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= q_y_i;
end if;
when s196 =>
if (rdy_i = '1') then
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= d_regs_out_i;
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s197 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s198 =>
if (rdy_i = '1') then
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= d_regs_out_i;
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s200 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s205 =>
if (rdy_i = '1') then
ch_a_o <= zw_b1;
ch_b_o <= X"01";
end if;
when s206 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s207 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s208 =>
if (rdy_i = '1') then
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= d_regs_out_i;
end if;
when s209 =>
if (rdy_i = '1') then
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= d_regs_out_i;
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s213 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s513 =>
ld_pc_o <= '1';
if (rdy_i = '1' and
zw_REG_OP = X"E5") then
ld_o <= "11";
elsif (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '0') then
ld_o <= "11";
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(8 downto 0) <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0);
sig_SYNC <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"F5") then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"ED") then
ld_o <= "11";
elsif (rdy_i = '1' and
zw_REG_OP = X"FD") then
ld_o <= "11";
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"F9") then
ld_o <= "11";
ch_a_o <= d_i;
ch_b_o <= q_y_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"F1") then
ch_a_o <= d_i;
ch_b_o <= X"01";
elsif (rdy_i = '1' and
zw_REG_OP = X"E1") then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '1') then
ld_o <= "11";
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 0) <= unsigned (( zw_ALU2(3 downto 0)) & ( zw_ALU1(3 downto 0))) -
unsigned (zw_ALU6(7 downto 0));
zw_ALU6(7 downto 0) <= '0' &
(NOT zw_ALU2(4)) &
(NOT zw_ALU2(4)) &
'0' &
'0' &
(NOT zw_ALU1(4)) &
(NOT zw_ALU1(4)) &
'0';
zw_ALU2(5 downto 0) <= unsigned ("00" & q_a_i(7 downto 4)) + unsigned ("00" & NOT (d_i(7 downto 4))) +
(zw_ALU1(4));
zw_ALU1(5 downto 0) <= unsigned ("00" & q_a_i(3 downto 0)) + unsigned ("00" & NOT (d_i(3 downto 0))) +
reg_F(0);
elsif (rdy_i = '1' and
zw_REG_OP = X"F2") then
ch_a_o <= d_i;
ch_b_o <= X"01";
end if;
when s588 =>
ld_pc_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
end if;
when s589 =>
ld_pc_o <= '1';
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= X"01";
ld_o <= "11";
end if;
when s590 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= q_y_i;
end if;
when s591 =>
ld_pc_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
end if;
when s593 =>
ld_pc_o <= '1';
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= X"01";
ld_o <= "11";
end if;
when s594 =>
if (rdy_i = '1') then
ch_a_o <= zw_b1;
ch_b_o <= X"01";
end if;
when s595 =>
if (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(8 downto 0) <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0);
sig_SYNC <= '1';
elsif (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 0) <= unsigned (( zw_ALU2(3 downto 0)) & ( zw_ALU1(3 downto 0))) -
unsigned (zw_ALU6(7 downto 0));
zw_ALU6(7 downto 0) <= '0' &
(NOT zw_ALU2(4)) &
(NOT zw_ALU2(4)) &
'0' &
'0' &
(NOT zw_ALU1(4)) &
(NOT zw_ALU1(4)) &
'0';
zw_ALU2(5 downto 0) <= unsigned ("00" & q_a_i(7 downto 4)) + unsigned ("00" & NOT (d_i(7 downto 4))) +
(zw_ALU1(4));
zw_ALU1(5 downto 0) <= unsigned ("00" & q_a_i(3 downto 0)) + unsigned ("00" & NOT (d_i(3 downto 0))) +
reg_F(0);
end if;
when s596 =>
if (rdy_i = '1' and
reg_F(3) = '0') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(8 downto 0) <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0);
sig_SYNC <= '1';
elsif (rdy_i = '1' and
reg_F(3) = '1') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 0) <= unsigned (( zw_ALU2(3 downto 0)) & ( zw_ALU1(3 downto 0))) -
unsigned (zw_ALU6(7 downto 0));
zw_ALU6(7 downto 0) <= '0' &
(NOT zw_ALU2(4)) &
(NOT zw_ALU2(4)) &
'0' &
'0' &
(NOT zw_ALU1(4)) &
(NOT zw_ALU1(4)) &
'0';
zw_ALU2(5 downto 0) <= unsigned ("00" & q_a_i(7 downto 4)) + unsigned ("00" & NOT (d_i(7 downto 4))) +
(zw_ALU1(4));
zw_ALU1(5 downto 0) <= unsigned ("00" & q_a_i(3 downto 0)) + unsigned ("00" & NOT (d_i(3 downto 0))) +
reg_F(0);
end if;
when s405 =>
if (rdy_i = '1' and
(zw_REG_OP = X"1E" or
zw_REG_OP = X"7E" or
zw_REG_OP = X"3E" or
zw_REG_OP = X"5E")) then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"06" or zw_REG_OP = X"66" or
zw_REG_OP = X"26" or zw_REG_OP = X"46" or
zw_REG_OP = X"04" or zw_REG_OP = X"14")) then
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"16" or
zw_REG_OP = X"76" or
zw_REG_OP = X"36" or
zw_REG_OP = X"56")) then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"0E" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"4E"or
zw_REG_OP = X"0C" or
zw_REG_OP = X"1C")) then
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
zw_REG_OP (3 downto 0) = X"7") then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s408 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s410 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s411 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s417 =>
if ((rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"16" or
zw_REG_OP = X"0E" or
zw_REG_OP = X"1E")) and (rdy_i = '1')) then
sig_D_OUT <= d_i(6 downto 0) & '0';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
elsif ((rdy_i = '1' and
(zw_REG_OP = X"46" or
zw_REG_OP = X"56" or
zw_REG_OP = X"4E" or
zw_REG_OP = X"5E")) and (rdy_i = '1')) then
sig_D_OUT <= '0' & d_i(7 downto 1);
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
elsif ((rdy_i = '1' and
(zw_REG_OP = X"26" or
zw_REG_OP = X"36" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"3E")) and (rdy_i = '1')) then
sig_D_OUT <= d_i(6 downto 0) & reg_F(0);
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
elsif ((rdy_i = '1' and
(zw_REG_OP = X"66" or
zw_REG_OP = X"76" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"7E")) and (rdy_i = '1')) then
sig_D_OUT <= reg_F(0) & d_i(7 downto 1);
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
elsif ((rdy_i = '1' and
zw_REG_OP (7) = '0' and
zw_REG_OP (3 downto 0) = X"7") and (rdy_i = '1')) then
sig_D_OUT <= d_i and NOT (d_alu_prio_i);
ch_a_o <= "00000" & zw_REG_OP (6 downto 4) ;
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
elsif ((rdy_i = '1' and
zw_REG_OP (7) = '1' and
zw_REG_OP (3 downto 0) = X"7") and (rdy_i = '1')) then
sig_D_OUT <= d_i or d_alu_prio_i;
ch_a_o <= "00000" & zw_REG_OP (6 downto 4) ;
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
elsif ((rdy_i = '1' and
(zw_REG_OP = X"14" or
zw_REG_OP = X"1C")) and (rdy_i = '1')) then
sig_D_OUT <= d_i and NOT (q_a_i);
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
elsif ((rdy_i = '1' and
(zw_REG_OP = X"04" or
zw_REG_OP = X"0C")) and (rdy_i = '1')) then
sig_D_OUT <= d_i or q_a_i;
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
end if;
when s419 =>
if ((zw_REG_OP (3 downto 0) = X"7") and (rdy_i = '1')) then
sig_SYNC <= '1';
elsif (((zw_REG_OP = X"14" or
zw_REG_OP = X"04" or
zw_REG_OP = X"0C" or
zw_REG_OP = X"1C")) and (rdy_i = '1')) then
ch_a_o <= zw_b1;
ch_b_o <= X"00";
sig_SYNC <= '1';
elsif (rdy_i = '1') then
ch_a_o <= zw_b1;
ch_b_o <= X"00";
sig_SYNC <= '1';
end if;
when s420 =>
if (rdy_i = '1') then
ch_a_o <= q_a_i (6 downto 0) & '0';
ch_b_o <= X"00";
d_regs_in_o <= q_a_i (6 downto 0) & '0';
load_regs_o <= '1';
sig_SYNC <= '1';
end if;
when s598 =>
if (rdy_i = '1') then
ch_a_o <= reg_F(0) & q_a_i (7 downto 1);
ch_b_o <= X"00";
d_regs_in_o <= reg_F(0) & q_a_i (7 downto 1);
load_regs_o <= '1';
sig_SYNC <= '1';
end if;
when s599 =>
if (rdy_i = '1') then
ch_a_o <= '0' & q_a_i (7 downto 1);
ch_b_o <= X"00";
d_regs_in_o <= '0' & q_a_i (7 downto 1);
load_regs_o <= '1';
sig_SYNC <= '1';
end if;
when s600 =>
if (rdy_i = '1') then
ch_a_o <= q_a_i (6 downto 0) & reg_F(0);
ch_b_o <= X"00";
d_regs_in_o <= q_a_i (6 downto 0) & reg_F(0);
load_regs_o <= '1';
sig_SYNC <= '1';
end if;
when s268 =>
ld_pc_o <= '1';
if (rdy_i = '1' and (
(reg_F(0) = '1' and zw_REG_OP = X"90") or (reg_F(0) = '0' and zw_REG_OP = X"B0") or
(reg_F(1) = '0' and zw_REG_OP = X"F0") or (reg_F(7) = '0' and zw_REG_OP = X"30") or
(reg_F(1) = '1' and zw_REG_OP = X"D0") or (reg_F(7) = '1' and zw_REG_OP = X"10") or
(reg_F(6) = '1' and zw_REG_OP = X"50") or (reg_F(6) = '0' and zw_REG_OP = X"70"))) then
ld_o <= "11";
sig_SYNC <= '1';
elsif (rdy_i = '1') then
ld_o <= "11";
end if;
when s305 =>
offset_o <= (zw_b2(7) & zw_b2(7) &
zw_b2(7) & zw_b2(7) & zw_b2(7) &
zw_b2(7) & zw_b2(7) & zw_b2(7) &
zw_b2(7) & zw_b2(6 downto 0));
ld_pc_o <= '1';
if (rdy_i = '1' and
zw_b3 = adr_nxt_pc_i (15 downto 8)) then
ld_o <= "11";
sig_SYNC <= '1';
elsif (rdy_i = '1') then
ld_o <= "11";
end if;
when s306 =>
offset_o <= (zw_b2(7) & zw_b2(7) & zw_b2(7) &
zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) &
zw_b2(7) & zw_b2(7) & zw_b2(6 downto 0));
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when jmp1 =>
ld_pc_o <= '1';
when jmp2_1 =>
ld_pc_o <= '1';
if (rdy_i = '1') then
adr_o <= d_i & zw_b1;
ld_o <= "11";
end if;
when jmp_ex =>
ld_pc_o <= '1';
if (rdy_i = '1') then
adr_o <= d_i & zw_b1;
ld_o <= "11";
sig_SYNC <= '1';
end if;
when jmp2_2 =>
offset_o <= (X"00" & q_x_i);
ld_pc_o <= '1';
if (rdy_i = '1') then
adr_o <= d_i & zw_b1;
ld_o <= "11";
end if;
when s402 =>
ld_sp_o <= '1';
ld_pc_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
end if;
when s421 =>
if (rdy_i = '1') then
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (15 downto 8);
end if;
when s422 =>
ld_sp_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (7 downto 0);
end if;
when s424 =>
ld_pc_o <= '1';
if (rdy_i = '1') then
adr_o <= d_i & zw_b1;
ld_o <= "11";
sig_SYNC <= '1';
end if;
when s362 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s221 =>
if (rdy_i = '1' and
zw_REG_OP = X"34") then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"3C") then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"24") then
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"2C") then
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"89") then
ch_a_o <= q_a_i AND d_i;
ch_b_o <= X"00";
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
end if;
when s232 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s233 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s234 =>
if (rdy_i = '1') then
ch_a_o <= q_a_i AND d_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
end if;
when s235 =>
if (rdy_i = '1' AND
zw_b2(0) = '0') then
ch_a_o <= q_a_i AND d_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
end if;
when brk1 =>
ld_sp_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_nxt_pc_i (15 downto 8);
end if;
when brk2 =>
ld_sp_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_nxt_pc_i (7 downto 0);
end if;
when brk3 =>
ld_sp_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= reg_F OR X"30";
end if;
when brk6 =>
ld_pc_o <= '1';
if (rdy_i = '1') then
adr_o <= d_i & zw_b1;
ld_o <= "11";
sig_SYNC <= '1';
end if;
when s425 =>
ld_sp_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
end if;
when s426 =>
ld_sp_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
end if;
when s427 =>
ld_sp_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
end if;
when s429 =>
ld_pc_o <= '1';
if (rdy_i = '1') then
adr_o <= d_i & zw_b1;
ld_o <= "11";
sig_SYNC <= '1';
end if;
when s430 =>
ld_sp_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
end if;
when s431 =>
ld_sp_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
end if;
when s433 =>
ld_pc_o <= '1';
if (rdy_i = '1') then
adr_o <= d_i & zw_b1;
ld_o <= "11";
end if;
when s434 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s236 =>
ld_pc_o <= '1';
if (rdy_i = '1' and
(zw_REG_OP = X"C6" OR
zw_REG_OP = X"E6")) then
ld_o <= "11";
elsif (rdy_i = '1' and
(zw_REG_OP = X"D6" OR
zw_REG_OP = X"F6")) then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"CE" OR
zw_REG_OP = X"EE")) then
ld_o <= "11";
elsif (rdy_i = '1' and
(zw_REG_OP = X"DE" OR
zw_REG_OP = X"FE")) then
ld_o <= "11";
ch_a_o <= d_i;
ch_b_o <= q_x_i;
end if;
when s245 =>
ld_pc_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
end if;
when s246 =>
ld_pc_o <= '1';
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
end if;
when s248 =>
ld_pc_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
end if;
when s346 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= zw_b4;
end if;
when s252 =>
if (rdy_i = '1') then
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= zw_b1;
end if;
when s253 =>
if (rdy_i = '1') then
ch_a_o <= zw_b1;
ch_b_o <= X"00";
sig_SYNC <= '1';
end if;
when s435 =>
if (rdy_i = '1') then
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= d_regs_out_i;
ld_o <= "11";
ld_sp_o <= '1';
end if;
when s436 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s437 =>
ld_sp_o <= '1';
if (rdy_i = '1') then
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= reg_F OR X"30";
ld_o <= "11";
end if;
when s438 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s439 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
end if;
when s441 =>
if (rdy_i = '1') then
d_regs_in_o <= d_i;
load_regs_o <= '1';
ch_a_o <= d_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
end if;
when s442 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
end if;
when s444 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when irq1 =>
ld_sp_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= zw_w3 (15 downto 8);
end if;
when irq2 =>
ld_sp_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= zw_w3 (7 downto 0);
end if;
when irq3 =>
ld_sp_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= (reg_F AND X"EF");
end if;
when irq6 =>
ld_pc_o <= '1';
if (rdy_i = '1') then
adr_o <= d_i & zw_b1;
rst_nmi_o <= '1';
ld_o <= "11";
sig_SYNC <= '1';
end if;
when s11 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
end if;
when s12 =>
ld_pc_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
end if;
when s20 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s14 =>
ld_pc_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
end if;
when s23 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s15 =>
ld_pc_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
end if;
when s25 =>
ld_pc_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
end if;
when s28 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s16 =>
ld_pc_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
end if;
when s30 =>
ld_pc_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
end if;
when s33 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when jmp3_2 =>
ld_pc_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
end if;
when s601 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s602 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s270 =>
ld_pc_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
end if;
when s307 =>
offset_o <= (zw_b2(7) & zw_b2(7) &
zw_b2(7) & zw_b2(7) & zw_b2(7) &
zw_b2(7) & zw_b2(7) & zw_b2(7) &
zw_b2(7) & zw_b2(6 downto 0));
ld_pc_o <= '1';
if (rdy_i = '1' and
zw_b3 = adr_nxt_pc_i (15 downto 8)) then
ld_o <= "11";
sig_SYNC <= '1';
elsif (rdy_i = '1') then
ld_o <= "11";
end if;
when s308 =>
ld_pc_o <= '1';
if (rdy_i = '1' and (
(zw_b1(0) = '0' and zw_REG_OP = X"8F") or
(zw_b1(1) = '0' and zw_REG_OP = X"9F") or
(zw_b1(2) = '0' and zw_REG_OP = X"AF") or
(zw_b1(3) = '0' and zw_REG_OP = X"BF") or
(zw_b1(4) = '0' and zw_REG_OP = X"CF") or
(zw_b1(5) = '0' and zw_REG_OP = X"DF") or
(zw_b1(6) = '0' and zw_REG_OP = X"EF") or
(zw_b1(7) = '0' and zw_REG_OP = X"FF") or
(zw_b1(0) = '1' and zw_REG_OP = X"0F") or
(zw_b1(1) = '1' and zw_REG_OP = X"1F") or
(zw_b1(2) = '1' and zw_REG_OP = X"2F") or
(zw_b1(3) = '1' and zw_REG_OP = X"3F") or
(zw_b1(4) = '1' and zw_REG_OP = X"4F") or
(zw_b1(5) = '1' and zw_REG_OP = X"5F") or
(zw_b1(6) = '1' and zw_REG_OP = X"6F") or
(zw_b1(7) = '1' and zw_REG_OP = X"7F"))) then
ld_o <= "11";
sig_SYNC <= '1';
elsif (rdy_i = '1') then
ld_o <= "11";
end if;
when s309 =>
offset_o <= (zw_b2(7) & zw_b2(7) & zw_b2(7) &
zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) &
zw_b2(7) & zw_b2(7) & zw_b2(6 downto 0));
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when RES2 =>
ld_o <= "11";
ld_pc_o <= '1';
ld_sp_o <= '1';
sig_RWn <= '1';
sig_RD <= '1';
when others =>
null;
end case;
end process output_proc;
-- Concurrent Statements
-- Clocked output assignments
d_o <= d_o_cld;
rd_o <= rd_o_cld;
sync_o <= sync_o_cld;
wr_n_o <= wr_n_o_cld;
wr_o <= wr_o_cld;
end fsm;
| gpl-3.0 | 0563a7e3b94efa314558fad0c8df914e | 0.324887 | 3.362495 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/grlib/amba/amba_tp.vhd | 1 | 72,495 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--============================================================================--
-- Design unit : AMBA_TestPackage (Package and body declarations)
--
-- File name : amba_tp.vhd
--
-- Purpose : AMBA AHB and APB interface access procedures
--
-- Library : {independent}
--
-- Authors : Aeroflex Gaisler AB
--
-- Contact : mailto:[email protected]
-- http://www.aeroflex.com/gaisler
--
-- Disclaimer : All information is provided "as is", there is no warranty that
-- the information is correct or suitable for any purpose,
-- neither implicit nor explicit.
--------------------------------------------------------------------------------
-- Version Author Date Changes
-- 0.1 SH 15 Mar 2002 New package
-- 0.2 SH 17 Mar 2003 Updated most packages
-- 0.3 SH 20 May 2003 Memory based on Integer elements
-- 0.4 SH 1 Jul 2003 Name of package changed
-- Compare function improved
-- AHB 32 bit memory with preload added
-- AHB initialisation added
-- 0.5 SH 21 Jul 2003 AHB 32 memory with diagnostics added
-- 0.6 SH 1 Nov 2003 APB read access data sample made earlier
-- AHB 32 memory extended with byte/halfword
-- 0.7 SH 25 Jan 2004 AHB read access data output corrected
-- AHB 32 memory allows overlay addressing
-- 1.7 SH 1 Oct 2004 Ported to GRLIB
-- 1.8 SH 1 Jul 2005 Added configuration support for memories
-- Modified all procedure declarations
-- 1.9 SH 10 Nov 2005 AHB 32 responds with HREADY=0 when error
-- 1.11 SH 27 Dec 2004 Split support added, using HSPLIT element
-- Proper two-cycle error response implemented
-- 1.12 SH 15 Feb 2006 Added bank select to AHB bus accesses
-- 1.13 SH 1 May 2009 AHBQuite gave incorrect TP on error resps.
--------------------------------------------------------------------------------
library Std;
use Std.Standard.all;
use Std.TextIO.all;
library IEEE;
use IEEE.Std_Logic_1164.all;
library GRLIB;
use GRLIB.AMBA.all;
use GRLIB.StdLib.all;
use GRLIB.StdIO.all;
package AMBA_TestPackage is
-----------------------------------------------------------------------------
-- AMBA APB write access
-----------------------------------------------------------------------------
procedure APBInit(
signal PCLK: in Std_ULogic;
signal APBIn: out APB_Slv_In_Type;
constant InstancePath: in String := "APBInit";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := True);
-----------------------------------------------------------------------------
-- AMBA APB write access
-----------------------------------------------------------------------------
procedure APBWrite(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(31 downto 0);
signal PCLK: in Std_ULogic;
signal APBIn: out APB_Slv_In_Type;
signal APBOut: in APB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "APBWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant PINDEX: in Integer := 0);
-----------------------------------------------------------------------------
-- AMBA APB read access
-----------------------------------------------------------------------------
procedure APBQuiet(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal PCLK: in Std_ULogic;
signal APBIn: out APB_Slv_In_Type;
signal APBOut: in APB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "APBQuiet";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant PINDEX: in Integer := 0);
-----------------------------------------------------------------------------
-- AMBA APB read access
-----------------------------------------------------------------------------
procedure APBRead(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal PCLK: in Std_ULogic;
signal APBIn: out APB_Slv_In_Type;
signal APBOut: in APB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "APBRead";
constant ScreenOutput: in Boolean := True;
constant cBack2Back: in Boolean := False;
constant PINDEX: in Integer := 0);
-----------------------------------------------------------------------------
-- AMBA APB read access
-----------------------------------------------------------------------------
procedure APBComp(
constant Address: in Std_Logic_Vector(31 downto 0);
constant CxData: in Std_Logic_Vector(31 downto 0);
variable RxData: out Std_Logic_Vector(31 downto 0);
signal PCLK: in Std_ULogic;
signal APBIn: out APB_Slv_In_Type;
signal APBOut: in APB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "APBComp";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant PINDEX: in Integer := 0);
-----------------------------------------------------------------------------
-- Initialise AMBA AHB interface
-----------------------------------------------------------------------------
procedure AHBInit(
signal HCLK: in Std_ULogic;
signal AHBIn: out AHB_Slv_In_Type;
constant InstancePath: in String := "AHBInit";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := True);
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure AHBWriteQuiet(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBIn: out AHB_Slv_In_Type;
signal AHBOut: in AHB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "AHBWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant HINDEX: in Integer := 0;
constant HMBINDEX: in Integer := 0);
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure AHBWrite(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBIn: out AHB_Slv_In_Type;
signal AHBOut: in AHB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "AHBWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant HINDEX: in Integer := 0;
constant HMBINDEX: in Integer := 0);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure AHBQuiet(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBIn: out AHB_Slv_In_Type;
signal AHBOut: in AHB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "AHBQuiet";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant HINDEX: in Integer := 0;
constant HMBINDEX: in Integer := 0);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure AHBRead(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBIn: out AHB_Slv_In_Type;
signal AHBOut: in AHB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "AHBRead";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant HINDEX: in Integer := 0;
constant HMBINDEX: in Integer := 0);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure AHBComp(
constant Address: in Std_Logic_Vector(31 downto 0);
constant CxData: in Std_Logic_Vector(31 downto 0);
variable RxData: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBIn: out AHB_Slv_In_Type;
signal AHBOut: in AHB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "AHBComp";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant HINDEX: in Integer := 0;
constant HMBINDEX: in Integer := 0);
-----------------------------------------------------------------------------
-- Diagnstics types for behavioural model of memory with AHB interface
-----------------------------------------------------------------------------
type AHB_Diagnostics_In_Type is
record
HADDR: Std_Logic_Vector(31 downto 0);
HWRITE: Std_ULogic;
HWDATA: Std_Logic_Vector(31 downto 0);
HRESP: Std_Logic_Vector(1 downto 0); -- response type
HSPLIT: Std_Logic_Vector(NAHBMST-1 downto 0); -- split completion
end record AHB_Diagnostics_In_Type;
type AHB_Diagnostics_Out_Type is
record
HRDATA: Std_Logic_Vector(31 downto 0);
end record AHB_Diagnostics_Out_Type;
constant AHB_Diagnostics_Init: AHB_Diagnostics_In_Type :=
(X"00000000", '0', X"00000000", HRESP_OKAY, zero32(NAHBMST-1 downto 0));
-----------------------------------------------------------------------------
-- Behavioural model of memory with AHB interface, no wait states
-----------------------------------------------------------------------------
procedure AHBMemory(
constant gAWidth: in Positive := 15; -- address width
constant gDWidth: in Positive := 8; -- data width
signal HCLK: in Std_ULogic;
signal HRESETn: in Std_ULogic;
signal AHBIn: in AHB_Slv_In_Type;
signal AHBOut: out AHB_Slv_Out_Type;
constant InstancePath: in String := "AHBMemory";
constant ScreenOutput: in Boolean := False;
constant HINDEX: in Integer := 0;
constant HADDR: in Integer := 0;
constant HMASK: in Integer := 16#FFF#);
-----------------------------------------------------------------------------
-- Behavioural model of memory with AMBA AHB interface, no wait states
-----------------------------------------------------------------------------
procedure AHBMemory32(
constant gAWidth: in Positive := 18; -- address width
signal HCLK: in Std_ULogic;
signal HRESETn: in Std_ULogic;
signal AHBIn: in AHB_Slv_In_Type;
signal AHBOut: out AHB_Slv_Out_Type;
constant InstancePath: in String := "AHBMemory32";
constant ScreenOutput: in Boolean := False;
constant FileName: in String := ""; -- file name
constant HINDEX: in Integer := 0;
constant HADDR: in Integer := 0;
constant HMASK: in Integer := 16#FFF#);
-----------------------------------------------------------------------------
-- Behavioural model of memory with AHB interface, no wait states
-- Supporting byte, halfword and word read/write accesses.
-- Provices diagnostic support.
-----------------------------------------------------------------------------
procedure AHBMemory32(
constant gAWidth: in Positive := 18; -- address width
signal HCLK: in Std_ULogic;
signal HRESETn: in Std_ULogic;
signal AHBIn: in AHB_Slv_In_Type;
signal AHBOut: out AHB_Slv_Out_Type;
signal AHBInDiag: in AHB_Diagnostics_In_Type;
signal AHBOutDiag: out AHB_Diagnostics_Out_Type;
constant InstancePath: in String := "AHBMemory32";
constant ScreenOutput: in Boolean := False;
constant FileName: in String := ""; -- file name
constant HINDEX: in Integer := 0;
constant HADDR: in Integer := 0;
constant HMASK: in Integer := 16#FFF#);
-----------------------------------------------------------------------------
-- Routine for writig data directly to AHB memory
-----------------------------------------------------------------------------
procedure WrAHBMem32(
constant Addr: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBInDiag: out AHB_Diagnostics_In_Type;
signal AHBOutDiag: in AHB_Diagnostics_Out_Type;
variable TP: inout Boolean;
constant Comment: in String := "";
constant Screen: in Boolean := False);
-----------------------------------------------------------------------------
-- Routine for reading data directly from AHB memory
-----------------------------------------------------------------------------
procedure RdAHBMem32(
constant Addr: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBInDiag: out AHB_Diagnostics_In_Type;
signal AHBOutDiag: in AHB_Diagnostics_Out_Type;
variable TP: inout Boolean;
constant Comment: in String := "";
constant Screen: in Boolean := False);
-----------------------------------------------------------------------------
-- Routine for reading data directly from AHB memory
-----------------------------------------------------------------------------
procedure RcAHBMem32(
constant Addr: in Std_Logic_Vector(31 downto 0);
constant Expected: in Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBInDiag: out AHB_Diagnostics_In_Type;
signal AHBOutDiag: in AHB_Diagnostics_Out_Type;
variable TP: inout Boolean;
constant Comment: in String := "";
constant Screen: in Boolean := False);
-----------------------------------------------------------------------------
-- Routine for generating a split ack from AHB memory
-----------------------------------------------------------------------------
procedure SplitAHBMem32(
constant Split: in Integer range 0 to NAHBMST-1;
signal HCLK: in Std_ULogic;
signal AHBInDiag: out AHB_Diagnostics_In_Type;
signal AHBOutDiag: in AHB_Diagnostics_Out_Type;
variable TP: inout Boolean;
constant Comment: in String := "";
constant Screen: in Boolean := False);
end AMBA_TestPackage;
--============================================================================--
package body AMBA_TestPackage is
-----------------------------------------------------------------------------
-- Compare function handling '-'
-----------------------------------------------------------------------------
function Compare(O, C: in Std_Logic_Vector) return Boolean is
variable T: Std_Logic_Vector(O'Range) := C;
variable Result: Boolean;
begin
Result := True;
for i in O'Range loop
if not (O(i)=T(i) or T(i)='-' or T(i)='U') then
Result := False;
end if;
end loop;
return Result;
end function Compare;
-----------------------------------------------------------------------------
-- Synchronisation with respect to clock and with output offset
-----------------------------------------------------------------------------
procedure Synchronise(
signal Clk: in Std_ULogic;
constant Offset: in Time := 5 ns) is
begin
wait until CLK = '1'; -- Synchronise
wait for Offset; -- output offset delay
end procedure Synchronise;
-----------------------------------------------------------------------------
-- AMBA APB write access
-----------------------------------------------------------------------------
procedure APBInit(
signal PCLK: in Std_ULogic;
signal APBIn: out APB_Slv_In_Type;
constant InstancePath: in String := "APBInit";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := True) is
variable L: Line;
begin
if cBack2Back then
Synchronise(PCLK);
end if;
APBIn.PSEL <= (others => '0');
APBIn.PENABLE <= '0';
APBIn.PADDR <= (others => '0');
APBIn.PWRITE <= '0';
APBIn.PWDATA <= (others => '0');
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : APB initalised"));
WriteLine(Output, L);
end if;
end procedure APBInit;
-----------------------------------------------------------------------------
-- AMBA APB write access
-----------------------------------------------------------------------------
procedure APBWrite(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(31 downto 0);
signal PCLK: in Std_ULogic;
signal APBIn: out APB_Slv_In_Type;
signal APBOut: in APB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "APBWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant PINDEX: in Integer := 0) is
variable L: Line;
begin
-- do not Synchronise when a back-to-back access is requested
if not cBack2Back then
Synchronise(PCLK);
end if;
APBIn.PSEL <= (others => '0');
APBIn.PSEL(PINDEX) <= '1'; -- first clock period
APBIn.PENABLE <= '0';
APBIn.PADDR <= Address;
APBIn.PWRITE <= '1';
APBIn.PWDATA <= Data;
Synchronise(PCLK); -- second clock period
APBIn.PENABLE <= '1';
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : APB write access, address: "));
HWrite(L, Address);
Write (L, String'(" : data: "));
HWrite(L, Data);
WriteLine(Output, L);
end if;
Synchronise(PCLK); -- end of access
APBIn.PSEL <= (others => '0');
APBIn.PENABLE <= '0';
APBIn.PADDR <= (others => '-');
APBIn.PWRITE <= '0';
APBIn.PWDATA <= (others => '-');
end procedure APBWrite;
-----------------------------------------------------------------------------
-- AMBA APB read access
-----------------------------------------------------------------------------
procedure APBQuiet(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal PCLK: in Std_ULogic;
signal APBIn: out APB_Slv_In_Type;
signal APBOut: in APB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "APBQuiet";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant PINDEX: in Integer := 0) is
begin
-- do not Synchronise when a back-to-back access is requested
if not cBack2Back then
Synchronise(PCLK);
end if;
APBIn.PSEL <= (others => '0');
APBIn.PSEL(PINDEX) <= '1'; -- first clock period
APBIn.PENABLE <= '0';
APBIn.PADDR <= Address;
APBIn.PWRITE <= '0';
APBIn.PWDATA <= (others => '-');
Synchronise(PCLK); -- second clock period
APBIn.PENABLE <= '1';
wait for 5 ns;
Data := APBOut.PRDATA;
Synchronise(PCLK); -- end of access
APBIn.PSEL <= (others => '0');
APBIn.PENABLE <= '0';
APBIn.PADDR <= (others => '-');
end procedure APBQuiet;
-----------------------------------------------------------------------------
-- AMBA APB read access
-----------------------------------------------------------------------------
procedure APBRead(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal PCLK: in Std_ULogic;
signal APBIn: out APB_Slv_In_Type;
signal APBOut: in APB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "APBRead";
constant ScreenOutput: in Boolean := True;
constant cBack2Back: in Boolean := False;
constant PINDEX: in Integer := 0) is
variable L: Line;
variable Temp: Std_Logic_Vector(31 downto 0);
begin
APBQuiet(Address, Temp, PCLK, APBIn, APBOut, TP, InstancePath, False, cBack2Back, PINDEX);
Data := Temp;
if ScreenOutput then
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath);
Write(L, String'(" : APB read access, address: "));
HWrite(L, Address);
Write(L, String'(" : data: "));
HWrite(L, Temp);
WriteLine(Output, L);
end if;
end procedure APBRead;
-----------------------------------------------------------------------------
-- AMBA APB read access
-----------------------------------------------------------------------------
procedure APBComp(
constant Address: in Std_Logic_Vector(31 downto 0);
constant CxData: in Std_Logic_Vector(31 downto 0);
variable RxData: out Std_Logic_Vector(31 downto 0);
signal PCLK: in Std_ULogic;
signal APBIn: out APB_Slv_In_Type;
signal APBOut: in APB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "APBComp";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant PINDEX: in Integer := 0) is
variable L: Line;
variable Data: Std_Logic_Vector(31 downto 0);
begin
APBQuiet(Address, Data, PCLK, APBIn, APBOut, TP, InstancePath, False, cBack2Back, PINDEX);
if not Compare(Data, CxData) then
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath);
Write(L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write(L, String'(" : data: "));
HWrite(L, Data);
Write(L, String'(" : expected: "));
HWrite(L, CxData);
Write(L, String'(" # Error #"));
WriteLine(Output, L);
TP := False;
elsif ScreenOutput then
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath);
Write(L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write(L, String'(" : data: "));
HWrite(L, Data);
WriteLine(Output, L);
end if;
RxData := Data;
end procedure APBComp;
-----------------------------------------------------------------------------
-- Initialise AHB interface
-----------------------------------------------------------------------------
procedure AHBInit(
signal HCLK: in Std_ULogic;
signal AHBIn: out AHB_Slv_In_Type;
constant InstancePath: in String := "AHBInit";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := True) is
variable L: Line;
begin
if cBack2Back then
Synchronise(HCLK);
end if;
AHBIn.HSEL <= (others => '0');
AHBIn.HADDR <= (others => '0');
AHBIn.HWRITE <= '0';
AHBIn.HTRANS <= HTRANS_IDLE;
AHBIn.HSIZE <= HSIZE_WORD;
AHBIn.HBURST <= HBURST_SINGLE;
AHBIn.HWDATA <= (others => '-');
AHBIn.HPROT <= (others => '0');
AHBIn.HREADY <= '0';
AHBIn.HMASTER <= (others => '0');
AHBIn.HMASTLOCK <= '0';
AHBIn.HMBSEL <= (others => '0');
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB initalised"));
WriteLine(Output, L);
end if;
end procedure AHBInit;
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure AHBWriteQuiet(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBIn: out AHB_Slv_In_Type;
signal AHBOut: in AHB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "AHBWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant HINDEX: in Integer := 0;
constant HMBINDEX: in Integer := 0) is
variable L: Line;
begin
-- do not Synchronise when a back-to-back access is requested
if not cBack2Back then
Synchronise(HCLK); -- first clock period
end if;
AHBIn.HSEL <= (others => '0');
AHBIn.HSEL(HINDEX)<= '1';
AHBIn.HADDR <= Address;
AHBIn.HWRITE <= '1';
AHBIn.HTRANS <= HTRANS_NONSEQ;
AHBIn.HSIZE <= HSIZE_WORD;
AHBIn.HBURST <= HBURST_SINGLE;
AHBIn.HWDATA <= (others => '-');
AHBIn.HPROT <= (others => '0');
AHBIn.HREADY <= '1';
AHBIn.HMASTER <= (others => '0');
AHBIn.HMASTLOCK <= '0';
AHBIn.HMBSEL <= (others => '0');
AHBIn.HMBSEL(HMBINDEX) <= '1';
Synchronise(HCLK); -- second clock period
AHBIn.HSEL <= (others => '0');
AHBIn.HSEL(HINDEX)<= '1';
AHBIn.HADDR <= (others => '-');
AHBIn.HWRITE <= '0';
AHBIn.HTRANS <= HTRANS_IDLE;
AHBIn.HWDATA <= ahbdrivedata(Data);
AHBIn.HREADY <= AHBOut.HREADY;
AHBIn.HMBSEL <= (others => '0');
AHBIn.HMBSEL(HMBINDEX) <= '1';
while AHBOut.HREADY='0' loop
Synchronise(HCLK);
end loop;
if AHBOut.HRESP=HRESP_ERROR then
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Address);
Write (L, String'(" ERROR response "));
WriteLine(Output, L);
end if;
TP := False;
elsif AHBOut.HRESP=HRESP_RETRY then
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Address);
Write (L, String'(" RETRY response "));
WriteLine(Output, L);
end if;
TP := False;
elsif AHBOut.HRESP=HRESP_SPLIT then
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Address);
Write (L, String'(" SPLIT response "));
WriteLine(Output, L);
end if;
TP := False;
else
end if;
Synchronise(HCLK); -- end of access
AHBIn.HSEL <= (others => '0');
AHBIn.HADDR <= (others => '-');
AHBIn.HWRITE <= '1';
AHBIn.HTRANS <= HTRANS_IDLE;
AHBIn.HSIZE <= HSIZE_WORD;
AHBIn.HBURST <= HBURST_SINGLE;
AHBIn.HWDATA <= (others => '-');
AHBIn.HPROT <= (others => '0');
AHBIn.HREADY <= '1';
AHBIn.HMASTER <= (others => '0');
AHBIn.HMASTLOCK <= '0';
AHBIn.HMBSEL <= (others => '0');
end procedure AHBWriteQuiet;
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure AHBWrite(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBIn: out AHB_Slv_In_Type;
signal AHBOut: in AHB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "AHBWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant HINDEX: in Integer := 0;
constant HMBINDEX: in Integer := 0) is
variable OK: Boolean := True;
variable L: Line;
begin
AHBWriteQuiet(Address, Data, HCLK, AHBIn, AHBOut, OK,
InstancePath, False, cBack2Back, HINDEX, HMBINDEX);
if ScreenOutput and OK then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Address);
Write (L, String'(" : data: "));
HWrite(L, Data);
WriteLine(Output, L);
elsif not OK then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Address);
Write (L, String'(" : ## Failed ##"));
WriteLine(Output, L);
TP := False;
end if;
end procedure AHBWrite;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure AHBQuiet(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBIn: out AHB_Slv_In_Type;
signal AHBOut: in AHB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "AHBQuiet";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant HINDEX: in Integer := 0;
constant HMBINDEX: in Integer := 0) is
variable L: Line;
begin
-- do not Synchronise when a back-to-back access is requested
if not cBack2Back then
Synchronise(HCLK);
end if;
AHBIn.HSEL <= (others => '0');
AHBIn.HSEL(HINDEX)<= '1';
AHBIn.HADDR <= Address;
AHBIn.HWRITE <= '0';
AHBIn.HTRANS <= HTRANS_NONSEQ;
AHBIn.HSIZE <= HSIZE_WORD;
AHBIn.HBURST <= HBURST_SINGLE;
AHBIn.HWDATA <= (others => '-');
AHBIn.HPROT <= (others => '0');
AHBIn.HREADY <= '1';
AHBIn.HMASTER <= (others => '0');
AHBIn.HMASTLOCK <= '0';
AHBIn.HMBSEL <= (others => '0');
AHBIn.HMBSEL(HMBINDEX) <= '1';
Synchronise(HCLK); -- second clock period
AHBIn.HSEL <= (others => '0');
AHBIn.HSEL(HINDEX)<= '1';
AHBIn.HADDR <= (others => '-');
AHBIn.HWRITE <= '0';
AHBIn.HTRANS <= HTRANS_IDLE;
AHBIn.HWDATA <= (others => '-');
AHBIn.HREADY <= AHBOut.HREADY;
AHBIn.HMBSEL <= (others => '0');
AHBIn.HMBSEL(HMBINDEX) <= '1';
while AHBOut.HREADY='0' loop
Synchronise(HCLK);
end loop;
Data := AHBOut.HRDATA(31 downto 0);
if AHBOut.HRESP=HRESP_ERROR then
if ScreenOutput then
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath);
Write(L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write(L, String'(" ERROR response "));
WriteLine(Output, L);
end if;
TP := False;
elsif AHBOut.HRESP=HRESP_RETRY then
if ScreenOutput then
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath);
Write(L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write(L, String'(" RETRY response "));
WriteLine(Output, L);
end if;
TP := False;
elsif AHBOut.HRESP=HRESP_SPLIT then
if ScreenOutput then
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath);
Write(L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write(L, String'(" SPLIT response "));
WriteLine(Output, L);
end if;
TP := False;
else
end if;
Synchronise(HCLK); -- end of access
AHBIn.HSEL <= (others => '0');
AHBIn.HADDR <= (others => '-');
AHBIn.HWRITE <= '0';
AHBIn.HTRANS <= HTRANS_IDLE;
AHBIn.HSIZE <= HSIZE_WORD;
AHBIn.HBURST <= HBURST_SINGLE;
AHBIn.HWDATA <= (others => '-');
AHBIn.HPROT <= (others => '0');
AHBIn.HREADY <= '1';
AHBIn.HMASTER <= (others => '0');
AHBIn.HMASTLOCK <= '0';
AHBIn.HMBSEL <= (others => '0');
end procedure AHBQuiet;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure AHBRead(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBIn: out AHB_Slv_In_Type;
signal AHBOut: in AHB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "AHBRead";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant HINDEX: in Integer := 0;
constant HMBINDEX: in Integer := 0) is
variable OK: Boolean := True;
variable L: Line;
variable Temp: Std_Logic_Vector(31 downto 0);
begin
AHBQuiet(Address, Temp, HCLK, AHBIn, AHBOut, OK,
InstancePath, False, cBack2Back, HINDEX, HMBINDEX);
if ScreenOutput and OK then
Data := Temp;
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath);
Write(L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write(L, String'(" : data: "));
HWrite(L, Temp);
WriteLine(Output, L);
elsif OK then
Data := Temp;
else
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write (L, String'(" : ## Failed ##"));
WriteLine(Output, L);
Data := (others => '-');
TP := False;
end if;
end procedure AHBRead;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure AHBComp(
constant Address: in Std_Logic_Vector(31 downto 0);
constant CxData: in Std_Logic_Vector(31 downto 0);
variable RxData: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBIn: out AHB_Slv_In_Type;
signal AHBOut: in AHB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "AHBComp";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant HINDEX: in Integer := 0;
constant HMBINDEX: in Integer := 0) is
variable OK: Boolean := True;
variable L: Line;
variable Data: Std_Logic_Vector(31 downto 0);
variable Failed: Boolean;
begin
AHBQuiet(Address, Data, HCLK, AHBIn, AHBOut, OK,
InstancePath, False, cBack2Back, HINDEX, HMBINDEX);
if not OK then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write (L, String'(" : ## Failed ##"));
WriteLine(Output, L);
TP := False;
RxData := (others => '-');
elsif not Compare(Data, CxData) then
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath);
Write(L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write(L, String'(" : data: "));
HWrite(L, Data);
Write(L, String'(" : expected: "));
HWrite(L, CxData);
Write(L, String'(" # Error #"));
WriteLine(Output, L);
TP := False;
RxData := Data;
elsif ScreenOutput then
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath);
Write(L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write(L, String'(" : data: "));
HWrite(L, Data);
WriteLine(Output, L);
RxData := Data;
else
RxData := Data;
end if;
end procedure AHBComp;
-----------------------------------------------------------------------------
-- Behavioural model of memory with AHB interface, no wait states
-----------------------------------------------------------------------------
procedure AHBMemory(
constant gAWidth: in Positive := 15; -- address width
constant gDWidth: in Positive := 8; -- data width
signal HCLK: in Std_ULogic;
signal HRESETn: in Std_ULogic;
signal AHBIn: in AHB_Slv_In_Type;
signal AHBOut: out AHB_Slv_Out_Type;
constant InstancePath: in String := "AHBMemory";
constant ScreenOutput: in Boolean := False;
constant HINDEX: in Integer := 0;
constant HADDR: in Integer := 0;
constant HMASK: in Integer := 16#FFF#) is
-- memory definition
subtype ARange is Natural range 0 to 2**gAWidth-1;
subtype DRange is Natural range 0 to gDWidth-1;
type MType is array (ARange) of Integer;
-- memory initialisation
function Init return MType is
variable r: MType;
begin
for i in ARange loop
r(i) := -1;
end loop;
return r;
end function Init;
variable M: MType;
variable A: Std_Logic_Vector(gAWidth-1 downto 0);
variable D: Std_Logic_Vector(0 to gDWidth-1);
variable W: Std_Logic;
-- reset values
procedure Reset is
begin
AHBOut.HREADY <= '1';
AHBOut.HRESP <= HRESP_OKAY;
AHBOut.HRDATA <= (others => '0');
W := '0';
end procedure Reset;
-- plug&play configuration
constant HCONFIG : ahb_config_type := (
0 => ahb_device_reg (0, 0, 0, gAWidth, 0),
4 => ahb_membar(HADDR, '1', '1', HMASK),
others => zero32);
variable alow : std_logic_vector(1 downto 0);
begin
-- fixed AMBA AHB signals, etc.
AHBOut.HSPLIT <= (others => '0');
AHBOut.HCONFIG <= HCONFIG;
loop
if HRESETn='0' then -- asynchronous reset
Reset;
elsif HCLK'Event and HCLK='1' then -- rising edge
-- data phase
if AHBIn.HREADY='1' then
if W='1' then
alow := A(1 downto 0);
case alow is
when "00" =>
D := AHBIn.HWDATA(31 downto 24);
when "01" =>
D := AHBIn.HWDATA(23 downto 16);
when "10" =>
D := AHBIn.HWDATA(15 downto 8);
when others =>
D := AHBIn.HWDATA( 7 downto 0);
end case;
M(Conv_Integer(A)) := Conv_Integer(D);
W := '0';
end if;
end if;
-- address phase
if AHBIn.HSEL(HINDEX)='1' and
AHBIn.HREADY='1' and
AHBIn.HSIZE=HSIZE_BYTE and
(AHBIn.HTRANS=HTRANS_SEQ or
AHBIn.HTRANS=HTRANS_NONSEQ) and
AHBIn.HMASTLOCK='0' then
W := AHBIn.HWRITE;
A := AHBIn.HADDR(gAWidth-1 downto 0);
AHBOut.HREADY <= '1';
AHBOut.HRESP <= HRESP_OKAY;
D := Conv_Std_Logic_Vector(
M(Conv_Integer(A)), D'Length);
case alow is
when "00" =>
AHBOut.HRDATA(31 downto 24) <= D;
when "01" =>
AHBOut.HRDATA(23 downto 16) <= D;
when "10" =>
AHBOut.HRDATA(15 downto 8) <= D;
when others =>
AHBOut.HRDATA( 7 downto 0) <= D;
end case;
else
w :='0';
AHBOut.HREADY <= '1';
AHBOut.HRESP <= HRESP_OKAY;
end if;
end if;
-- signal sensitivity
wait on HCLK, HRESETn;
end loop;
end procedure AHBMemory;
-----------------------------------------------------------------------------
-- Behavioural model of memory with AHB interface, no wait states
-----------------------------------------------------------------------------
procedure AHBMemory32(
constant gAWidth: in Positive := 18; -- address width
signal HCLK: in Std_ULogic;
signal HRESETn: in Std_ULogic;
signal AHBIn: in AHB_Slv_In_Type;
signal AHBOut: out AHB_Slv_Out_Type;
constant InstancePath: in String := "AHBMemory32";
constant ScreenOutput: in Boolean := False;
constant FileName: in String := ""; -- File name
constant HINDEX: in Integer := 0;
constant HADDR: in Integer := 0;
constant HMASK: in Integer := 16#FFF#) is
-- memory definition
type MType is array (0 to 2**(gAWidth-2)-1) of
Std_Logic_Vector(31 downto 0);
--------------------------------------------------------------------------
-- Load memory contents
--------------------------------------------------------------------------
-- ## Does not warn if there is insufficient data in a line.
-- Address read from file is always byte oriented, always 32 bit wide
-- For 16 and 32 bit wide data, each data word read from file must be on a
-- single line and without white space between the characters. For 8 bit
-- wide date, no restrictions apply. Files generated for 32 bit wide data
-- can always be read by 16 or 8 bit memories. The byte/halfwrod address
-- is incremented internally.
--------------------------------------------------------------------------
-- -----------------------------------------------------------------------
-- -- PROM Initialisation Example
-- -----------------------------------------------------------------------
-- -- Supports by 8, 16, 32 bit wide memories
-- 00000000 00010203
-- 00000004 04050607 08090A0B
-- 0000000C 0C0D0E0F
--
-- -- Supported by 8, 16 bit wide memories
-- 00000010 1011 1213
-- 00000014 1415
-- 00000016 1617 1819 1A1B 1C1D 1E1F 2021
-- 00000022 2223 2425 2627 2829 2A2B 2C2D 2E2F
--
-- -- Supported by 8 bit wide memories
-- 00000030 30 31 32 33 3435 3637 3839 3A3B 3C3D 3E3F
-- 00000040 40
-- 00000041 41
-- 00000042 42 43
-- 00000044 4445
-- 00000046 46474849
-- 0000004A 4A4B 4C4D4E4F
--------------------------------------------------------------------------
impure function Initialise(
constant FileName: in String := "";
constant AWidth: in Natural;
constant DWidth: in Natural)
return MType is
variable L: Line;
variable Address: Std_Logic_Vector(31 downto 0);
variable Data: Std_Logic_Vector(31 downto 0);
variable Byte: Std_Logic_Vector( 7 downto 0);
variable Addr: Natural range 0 to 2**AWidth-1;
file ReadFile: Text;
variable Test: Boolean;
variable Result: MType;
begin
-- initialse all data to all zeros
Result := (others => (others => 'U'));
-- load contents from file only if a file name has been provided
if FileName /= "" then
File_Open(ReadFile, FileName, Read_Mode);
-- read data from file
while not EndFile(ReadFile) loop
-- read line
ReadLine(ReadFile, L);
-- read address, always byte oriented, always 32 bit wide
HRead(L, Address, Test);
if Test then -- address read
-- check whether byte address aligned with data width
if Conv_Integer(Address) mod (DWidth/8) /= 0 then
report "Unaligned data in memory initalisation file: " &
FileName
severity Failure;
Test := False;
else -- convert address
-- adapt byte address to address corresponding to the data
-- width of the memory
Addr := (Conv_Integer(Address)/(DWidth/8)) mod
(2**AWidth);
end if;
else -- comment detected
null;
end if;
while Test loop
-- read data
HRead(L, Data(DWidth-1 downto 0), Test);
if Test then
-- initialize memory element
Result(Addr) := Data(DWidth-1 downto 0);
-- increment address, with the memory width
Addr := (Addr + 1) mod (2**AWidth);
end if;
end loop;
end loop;
File_Close(ReadFile);
end if;
return Result;
end function Initialise;
-- memory contents
variable M: MType := Initialise(FileName, gAWidth-2, 32);
variable A: Std_Logic_Vector(gAWidth-1 downto 2);
variable W: Std_Logic;
-- reset values
procedure Reset is
begin
AHBOut.HREADY <= '1';
AHBOut.HRESP <= HRESP_OKAY;
AHBOut.HRDATA <= (others => '0');
W := '0';
end procedure Reset;
-- plug&play configuration
constant HCONFIG : ahb_config_type := (
0 => ahb_device_reg (0, 0, 0, gAWidth, 0),
4 => ahb_membar(HADDR, '1', '1', HMASK),
others => zero32);
begin
-- fixed AMBA AHB signals, etc.
AHBOut.HSPLIT <= (others => '0');
AHBOut.HCONFIG <= HCONFIG;
loop
if HRESETn='0' then -- asynchronous reset
Reset;
elsif HCLK'Event and HCLK='1' then -- rising edge
-- data phase
if AHBIn.HREADY='1' then
if W='1' then
M(Conv_Integer(A)) := AHBIn.HWDATA(31 downto 0);
W := '0';
end if;
end if;
-- address phase
if AHBIn.HSEL(HINDEX)='1' and
AHBIn.HREADY='1' and
AHBIn.HSIZE=HSIZE_WORD and
(AHBIn.HTRANS=HTRANS_SEQ or
AHBIn.HTRANS=HTRANS_NONSEQ) and
AHBIn.HMASTLOCK='0' then
W := AHBIn.HWRITE;
A := AHBIn.HADDR(gAWidth-1 downto 2);
AHBOut.HREADY <= '1';
AHBOut.HRESP <= HRESP_OKAY;
AHBOut.HRDATA <= ahbdrivedata(M(Conv_Integer(A)));
else
W :='0';
AHBOut.HREADY <= '1';
AHBOut.HRESP <= HRESP_OKAY;
end if;
end if;
-- signal sensitivity
wait on HCLK, HRESETn;
end loop;
end procedure AHBMemory32;
-----------------------------------------------------------------------------
-- Behavioural model of memory with AHB interface, no wait states
-- Supporting byte, halfword and word read/write accesses.
-- Provices diagnostic support.
-----------------------------------------------------------------------------
procedure AHBMemory32(
constant gAWidth: in Positive := 18; -- address width
signal HCLK: in Std_ULogic;
signal HRESETn: in Std_ULogic;
signal AHBIn: in AHB_Slv_In_Type;
signal AHBOut: out AHB_Slv_Out_Type;
signal AHBInDiag: in AHB_Diagnostics_In_Type;
signal AHBOutDiag: out AHB_Diagnostics_Out_Type;
constant InstancePath: in String := "AHBMemory32";
constant ScreenOutput: in Boolean := False;
constant FileName: in String := ""; -- File name
constant HINDEX: in Integer := 0;
constant HADDR: in Integer := 0;
constant HMASK: in Integer := 16#FFF#) is
-- memory definition
type MType is array (0 to 2**(gAWidth-2)-1) of
Std_Logic_Vector(31 downto 0);
variable L: Line;
constant Padding: Std_ULogic_Vector(1 to
(4-((gAWidth-2) mod 4))) :=
(others => '0');
--------------------------------------------------------------------------
-- Load memory contents
--------------------------------------------------------------------------
-- ## Does not warn if there is insufficient data in a line.
-- Address read from file is always byte oriented, always 32 bit wide
-- For 16 and 32 bit wide data, each data word read from file must be on a
-- single line and without white space between the characters. For 8 bit
-- wide date, no restrictions apply. Files generated for 32 bit wide data
-- can always be read by 16 or 8 bit memories. The byte/halfwrod address
-- is incremented internally.
--------------------------------------------------------------------------
-- -----------------------------------------------------------------------
-- -- PROM Initialisation Example
-- -----------------------------------------------------------------------
-- -- Supports by 8, 16, 32 bit wide memories
-- 00000000 00010203
-- 00000004 04050607 08090A0B
-- 0000000C 0C0D0E0F
--
-- -- Supported by 8, 16 bit wide memories
-- 00000010 1011 1213
-- 00000014 1415
-- 00000016 1617 1819 1A1B 1C1D 1E1F 2021
-- 00000022 2223 2425 2627 2829 2A2B 2C2D 2E2F
--
-- -- Supported by 8 bit wide memories
-- 00000030 30 31 32 33 3435 3637 3839 3A3B 3C3D 3E3F
-- 00000040 40
-- 00000041 41
-- 00000042 42 43
-- 00000044 4445
-- 00000046 46474849
-- 0000004A 4A4B 4C4D4E4F
--------------------------------------------------------------------------
impure function Initialise(
constant FileName: in String := "";
constant AWidth: in Natural;
constant DWidth: in Natural)
return MType is
variable L: Line;
variable Address: Std_Logic_Vector(31 downto 0);
variable Data: Std_Logic_Vector(31 downto 0);
variable Byte: Std_Logic_Vector( 7 downto 0);
variable Addr: Natural range 0 to 2**AWidth-1;
file ReadFile: Text;
variable Test: Boolean;
variable Result: MType;
begin
-- initialse all data to all zeros
Result := (others => (others => 'U'));
-- load contents from file only if a file name has been provided
if FileName /= "" then
File_Open(ReadFile, FileName, Read_Mode);
-- read data from file
while not EndFile(ReadFile) loop
-- read line
ReadLine(ReadFile, L);
-- read address, always byte oriented, always 32 bit wide
HRead(L, Address, Test);
if Test then -- address read
-- check whether byte address aligned with data width
if Conv_Integer(Address) mod (DWidth/8) /= 0 then
report "Unaligned data in memory initalisation file: " &
FileName
severity Failure;
Test := False;
else -- convert address
-- adapt byte address to address corresponding to the data
-- width of the memory
Addr := (Conv_Integer(Address)/(DWidth/8)) mod
(2**AWidth);
end if;
else -- comment detected
null;
end if;
while Test loop
-- read data
HRead(L, Data(DWidth-1 downto 0), Test);
if Test then
-- initialize memory element
Result(Addr) := Data(DWidth-1 downto 0);
-- increment address, with the memory width
Addr := (Addr + 1) mod (2**AWidth);
end if;
end loop;
end loop;
File_Close(ReadFile);
end if;
return Result;
end function Initialise;
-- memory contents
variable M: MType := Initialise(FileName, gAWidth-2, 32);
variable A: Std_Logic_Vector(gAWidth-1 downto 2);
variable B: Std_Logic_Vector(1 downto 0);
variable W: Std_Logic;
variable S: Std_Logic_Vector(2 downto 0);
variable D: Std_Logic_Vector(31 downto 0);
variable twocycle:Boolean := False;
-- reset values
procedure Reset is
begin
AHBOut.HREADY <= '1';
AHBOut.HRESP <= HRESP_OKAY;
AHBOut.HRDATA <= (others => '0');
W := '0';
twocycle := False;
end procedure Reset;
-- plug&play configuration
constant HCONFIG : ahb_config_type := (
0 => ahb_device_reg (0, 0, 0, gAWidth, 0),
4 => ahb_membar(HADDR, '1', '1', HMASK),
others => zero32);
begin
-- fixed AMBA AHB signals, etc.
AHBOut.HSPLIT <= (others => '0');
AHBOut.HCONFIG <= HCONFIG;
loop
if HRESETn='0' then -- asynchronous reset
Reset;
elsif HCLK'Event and HCLK='1' then -- rising edge
-- data phase
if AHBIn.HREADY='1' then
if W='1' then
-- read back memory
D := M(Conv_Integer(A));
-- replace with new data
if S="000" then -- byte
if B(1 downto 0)="00" then
D := AHBIn.HWDATA(31 downto 24) &
D(23 downto 0);
elsif B(1 downto 0)="01" then
D := D(31 downto 24) &
AHBIn.HWDATA(23 downto 16) &
D(15 downto 0);
elsif B(1 downto 0)="10" then
D := D(31 downto 16) &
AHBIn.HWDATA(15 downto 8) &
D(7 downto 0);
elsif B(1 downto 0)="11" then
D := D(31 downto 8) &
AHBIn.HWDATA(7 downto 0);
end if;
elsif S="001" then -- halfword
if B(1 downto 0)="00" then
D := AHBIn.HWDATA(31 downto 16) &
D(15 downto 0);
elsif B(1 downto 0)="10" then
D := D(31 downto 16) &
AHBIn.HWDATA(15 downto 0);
end if;
else
D := AHBIn.HWDATA(31 downto 0);
end if;
-- write back memory
M(Conv_Integer(A)) := D;
W := '0';
-- comment
if ScreenOutput then
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath & " Write acces to address :");
if Padding'Length > 0 and Padding'Length < 4 then
HWrite(L, Std_Logic_Vector(Padding) & Std_Logic_Vector(A));
else
HWrite(L, Std_Logic_Vector(A));
end if;
Write(L, String'(" data :"));
HWrite(L, D);
Write(L, String'(" data :"));
Write(L, To_BitVector(D));
Write(L, String'(" size :"));
HWrite(L, "0" & S);
WriteLine(Output, L);
end if;
end if;
end if;
-- address phase
if AHBIn.HSEL(HINDEX)='1' and
AHBIn.HREADY='1' and
(AHBIn.HSIZE=HSIZE_BYTE or
AHBIn.HSIZE=HSIZE_HWORD or
AHBIn.HSIZE=HSIZE_WORD) and
(AHBIn.HTRANS=HTRANS_SEQ or
AHBIn.HTRANS=HTRANS_NONSEQ) and
AHBIn.HMASTLOCK='0' then
if AHBInDiag.HRESP=HRESP_OKAY then
W := AHBIn.HWRITE;
S := AHBIn.HSIZE;
B := AHBIn.HADDR( 1 downto 0);
A := AHBIn.HADDR(gAWidth-1 downto 2);
AHBOut.HREADY <= '1';
AHBOut.HRESP <= HRESP_OKAY;
AHBOut.HRDATA <= ahbdrivedata(M(Conv_Integer(A)));
elsif AHBInDiag.HRESP=HRESP_RETRY then
W :='0';
AHBOut.HREADY <= '0';
AHBOut.HRESP <= HRESP_RETRY;
AHBOut.HRDATA <= (others => 'X');
twocycle := True;
elsif AHBInDiag.HRESP=HRESP_SPLIT then
W :='0';
AHBOut.HREADY <= '0';
AHBOut.HRESP <= HRESP_SPLIT;
AHBOut.HRDATA <= (others => 'X');
twocycle := True;
else
W :='0';
AHBOut.HREADY <= '0';
AHBOut.HRESP <= HRESP_ERROR;
AHBOut.HRDATA <= (others => 'X');
twocycle := True;
end if;
else
W :='0';
AHBOut.HREADY <= '1';
if twocycle then
twocycle := False;
else
AHBOut.HRESP <= HRESP_OKAY;
end if;
end if;
end if;
if HCLK'Event and HCLK='1' then -- rising edge
-- diagnostics
AHBOutDiag.HRData <= M((Conv_Integer(AHBInDiag.HAddr)/4) mod (2**(gAWidth-2)));
if AHBInDiag.HWrite='1' then
M((Conv_Integer(AHBInDiag.HAddr)/4) mod (2**(gAWidth-2))) := AHBInDiag.HWData;
-- Print("Diagnostic write to memory, address: " &
-- Integer'Image(Conv_Integer(AHBInDiag.HAddr)) &
-- " data: " &
-- Integer'Image(Conv_Integer(AHBInDiag.HWData)));
end if;
AHBOut.HSPLIT <= AHBInDiag.HSplit;
end if;
-- signal sensitivity
wait on HCLK, HRESETn;
end loop;
end procedure AHBMemory32;
-----------------------------------------------------------------------------
-- Routine for writig data directly to AHB memory
-----------------------------------------------------------------------------
procedure WrAHBMem32(
constant Addr: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBInDiag: out AHB_Diagnostics_In_Type;
signal AHBOutDiag: in AHB_Diagnostics_Out_Type;
variable TP: inout Boolean;
constant Comment: in String := "";
constant Screen: in Boolean := False) is
variable L: Line;
begin
Synchronise(HCLK);
if Screen then
Write(L, Now, Right, 15);
Write(L, String'(" : WrAHBMem32: "));
HWrite(L, Std_Logic_Vector(Addr));
Write(L, String'(" : "));
HWrite(L, Std_Logic_Vector(Data));
if Comment /= "" then
Write(L, " : " & Comment);
end if;
WriteLine(Output, L);
end if;
AHBInDiag.HAddr <= Addr;
AHBInDiag.HWData <= Data;
AHBInDiag.HWrite <= '1';
Synchronise(HCLK);
AHBInDiag.HWrite <= '0';
end procedure WrAHBMem32;
-----------------------------------------------------------------------------
-- Routine for reading data directly from AHB memory
-----------------------------------------------------------------------------
procedure RdAHBMem32(
constant Addr: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBInDiag: out AHB_Diagnostics_In_Type;
signal AHBOutDiag: in AHB_Diagnostics_Out_Type;
variable TP: inout Boolean;
constant Comment: in String := "";
constant Screen: in Boolean := False) is
variable L: Line;
begin
Synchronise(HCLK);
AHBInDiag.HAddr <= Addr;
AHBInDiag.HWrite <= '0';
Synchronise(HCLK);
Data := AHBOutDiag.HRData;
if Screen then
Write(L, Now, Right, 15);
Write(L, String'(" : RdAHBMem32: "));
HWrite(L, Std_Logic_Vector(Addr));
Write(L, String'(" : "));
HWrite(L, Std_Logic_Vector(AHBOutDiag.HRData));
if Comment /= "" then
Write(L, " : " & Comment);
end if;
WriteLine(Output, L);
end if;
end procedure RdAHBMem32;
-----------------------------------------------------------------------------
-- Routine for reading data directly from AHB memory
-----------------------------------------------------------------------------
procedure RcAHBMem32(
constant Addr: in Std_Logic_Vector(31 downto 0);
constant Expected: in Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBInDiag: out AHB_Diagnostics_In_Type;
signal AHBOutDiag: in AHB_Diagnostics_Out_Type;
variable TP: inout Boolean;
constant Comment: in String := "";
constant Screen: in Boolean := False) is
variable Data: Std_Logic_Vector(31 downto 0);
variable L: Line;
begin
Synchronise(HCLK);
AHBInDiag.HAddr <= Addr;
AHBInDiag.HWrite <= '0';
Synchronise(HCLK);
Data := AHBOutDiag.HRData;
if not Compare(Data, Expected) then
Write(L, Now, Right, 15);
Write(L, String'(" : RcAHBMem32: "));
HWrite(L, Std_Logic_Vector(Addr));
Write(L, String'(", value: "));
HWrite(L, Std_Logic_Vector(Data));
Write(L, String'(", expected: "));
HWrite(L, Std_Logic_Vector(Expected));
Write(L, String'(" # Error "));
if Comment /= "" then
Write(L, " : " & Comment);
end if;
WriteLine(Output, L);
TP := False;
elsif Screen then
Write(L, Now, Right, 15);
Write(L, String'(" : RcAHBMem32: "));
HWrite(L, Std_Logic_Vector(Addr));
Write(L, String'(" : "));
HWrite(L, Std_Logic_Vector(Data));
Write(L, String'(" : "));
HWrite(L, Std_Logic_Vector(Expected));
if Comment /= "" then
Write(L, " : " & Comment);
end if;
WriteLine(Output, L);
end if;
end procedure RcAHBMem32;
-----------------------------------------------------------------------------
-- Routine for generating a split ack from AHB memory
-----------------------------------------------------------------------------
procedure SplitAHBMem32(
constant Split: in Integer range 0 to NAHBMST-1;
signal HCLK: in Std_ULogic;
signal AHBInDiag: out AHB_Diagnostics_In_Type;
signal AHBOutDiag: in AHB_Diagnostics_Out_Type;
variable TP: inout Boolean;
constant Comment: in String := "";
constant Screen: in Boolean := False) is
variable L: Line;
begin
Synchronise(HCLK);
AHBInDiag.HSPLIT <= (others => '0');
AHBInDiag.HSPLIT(Split) <= '1';
Synchronise(HCLK);
AHBInDiag.HSPLIT <= (others => '0');
if Screen then
Write(L, Now, Right, 15);
Write(L, String'(" : SplitAHBMem32: split acknowledge to master: "));
Write(L, Split);
if Comment /= "" then
Write(L, " : " & Comment);
end if;
WriteLine(Output, L);
end if;
end procedure SplitAHBMem32;
end package body AMBA_TestPackage; --=========================================--
| gpl-3.0 | cabcba51d8e18b88c023c6a09d568c91 | 0.44472 | 4.828493 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/grlib/stdlib/stdio.vhd | 1 | 9,067 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--------------------------------------------------------------------------------
-- Package: StdIO
-- File: stdio.vhd
-- Author: Gaisler Research
-- Description: Package for common I/O functions
--------------------------------------------------------------------------------
-- pragma translate_off
library Std;
use Std.Standard.all;
use Std.TextIO.all;
library IEEE;
use IEEE.Std_Logic_1164.all;
-- pragma translate_on
package StdIO is
-- pragma translate_off
procedure HRead(
variable L: inout Line;
variable VALUE: out Std_ULogic_Vector;
variable GOOD: out Boolean);
procedure HRead(
variable L: inout Line;
variable VALUE: out Std_ULogic_Vector);
procedure HRead(
variable L: inout Line;
variable VALUE: out bit_vector);
procedure HRead(
variable L: inout Line;
variable VALUE: out Std_Logic_Vector;
variable GOOD: out Boolean);
procedure HRead(
variable L: inout Line;
variable VALUE: out Std_Logic_Vector);
procedure HWrite(
variable L: inout Line;
constant VALUE: in Std_ULogic_Vector;
constant JUSTIFIED: in SIDE := RIGHT;
constant FIELD: in WIDTH := 0);
procedure HWrite(
variable L: inout Line;
constant VALUE: in Std_Logic_Vector;
constant JUSTIFIED: in SIDE := RIGHT;
constant FIELD: in WIDTH := 0);
procedure Write(
variable L: inout Line;
constant VALUE: in Std_ULogic;
constant JUSTIFIED: in SIDE := RIGHT;
constant FIELD: in WIDTH := 0);
-- pragma translate_on
end package StdIO;
package body StdIO is
-- pragma translate_off
function ToChar(N: Std_ULogic_Vector(0 to 3)) return Character is
begin
case N is
when "0000" => return('0');
when "0001" => return('1');
when "0010" => return('2');
when "0011" => return('3');
when "0100" => return('4');
when "0101" => return('5');
when "0110" => return('6');
when "0111" => return('7');
when "1000" => return('8');
when "1001" => return('9');
when "1010" => return('A');
when "1011" => return('B');
when "1100" => return('C');
when "1101" => return('D');
when "1110" => return('E');
when "1111" => return('F');
when others => return('X');
end case;
end ToChar;
function FromChar(C: Character) return Std_ULogic_Vector is
variable R: Std_ULogic_Vector(0 to 3);
begin
case C is
when '0' => R := "0000";
when '1' => R := "0001";
when '2' => R := "0010";
when '3' => R := "0011";
when '4' => R := "0100";
when '5' => R := "0101";
when '6' => R := "0110";
when '7' => R := "0111";
when '8' => R := "1000";
when '9' => R := "1001";
when 'A' => R := "1010";
when 'B' => R := "1011";
when 'C' => R := "1100";
when 'D' => R := "1101";
when 'E' => R := "1110";
when 'F' => R := "1111";
when 'a' => R := "1010";
when 'b' => R := "1011";
when 'c' => R := "1100";
when 'd' => R := "1101";
when 'e' => R := "1110";
when 'f' => R := "1111";
when others => R := "XXXX";
end case;
return R;
end FromChar;
procedure HRead(
variable L: inout Line;
variable VALUE: out Std_ULogic_Vector;
variable GOOD: out Boolean) is
variable B: Boolean;
variable C: Character;
constant SL: Integer := VALUE'Length;
variable SV: Std_ULogic_Vector(0 to SL-1);
variable S: String(1 to SL/4-1);
begin
if VALUE'Length mod 4 /= 0 then
GOOD := False;
SV := (others => 'X');
VALUE := SV;
return;
end if;
loop
Read(L, C, B);
exit when ((C /= ' ') and (C /= CR) and (C /= HT)) or (not B);
end loop;
SV(0 to 3) := FromChar(C);
if Is_X(SV(0 to 3)) or (not B) then
GOOD := False;
SV := (others => 'X');
VALUE := SV;
return;
end if;
Read(L, S, B);
if not B then
GOOD := False;
SV := (others => 'X');
VALUE := SV;
return;
end if;
for i in 1 to SL/4-1 loop
SV(4*i to 4*i+3) := FromChar(S(i));
if Is_X(SV(4*i to 4*i+3)) then
GOOD := False;
SV := (others => 'X');
VALUE := SV;
return;
end if;
end loop;
GOOD := True;
VALUE := SV;
end HRead;
procedure HRead(
variable L: inout Line;
variable VALUE: out Std_ULogic_Vector) is
variable GOOD: Boolean;
begin
HRead(L, VALUE, GOOD);
--assert GOOD
-- report "HREAD: access incorrect";
end HRead;
procedure HRead(
variable L: inout Line;
variable VALUE: out bit_vector) is
variable GOOD: Boolean;
variable V: Std_ULogic_Vector(0 to Value'Length-1);
begin
HRead(L, V, GOOD);
--assert GOOD
-- report "HREAD: access incorrect";
VALUE := to_bitvector(V);
end HRead;
procedure HRead(
variable L: inout Line;
variable VALUE: out Std_Logic_Vector;
variable GOOD: out Boolean) is
variable V: Std_ULogic_Vector(0 to Value'Length-1);
begin
HRead(L, V, GOOD);
VALUE := Std_Logic_Vector(V);
end HRead;
procedure HRead(
variable L: inout Line;
variable VALUE: out Std_Logic_Vector) is
variable GOOD: Boolean;
variable V: Std_ULogic_Vector(0 to Value'Length-1);
begin
HRead(L, V, GOOD);
VALUE := Std_Logic_Vector(V);
--assert GOOD
-- report "HREAD: access incorrect";
end HRead;
procedure HWrite(
variable L: inout Line;
constant VALUE: in Std_ULogic_Vector;
constant JUSTIFIED: in SIDE := RIGHT;
constant FIELD: in WIDTH := 0) is
constant PL: Integer := 4-(VALUE'Length mod 4);
constant PV: Std_ULogic_Vector(1 to PL) := (others => '0');
constant TL: Integer := PL + VALUE'Length;
constant TV: Std_ULogic_Vector(0 to TL-1) := PV & Value;
variable S: String(1 to TL/4);
begin
if PL /= 4 then
for i in 0 to TL/4 -1 loop
S(i+1) := ToChar(TV(4*i to 4*i+3));
end loop;
Write(L, S(1 to TL/4), JUSTIFIED, FIELD);
else
for i in 1 to TL/4 -1 loop
S(i+1) := ToChar(TV(4*i to 4*i+3));
end loop;
Write(L, S(2 to TL/4), JUSTIFIED, FIELD);
end if;
end HWrite;
procedure HWrite(
variable L: inout Line;
constant VALUE: in Std_Logic_Vector;
constant JUSTIFIED: in SIDE := RIGHT;
constant FIELD: in WIDTH := 0) is
begin
HWrite(L, Std_ULogic_Vector(VALUE), JUSTIFIED, FIELD);
end HWrite;
procedure Write(
variable L: inout Line;
constant VALUE: in Std_ULogic;
constant JUSTIFIED: in SIDE := RIGHT;
constant FIELD: in WIDTH := 0) is
type Char_Array is array (Std_ULogic) of Character;
constant ToChar: Char_Array := "UX01ZWLH-";
begin
Write(L, ToChar(VALUE), JUSTIFIED, FIELD);
end Write;
-- pragma translate_on
end package body StdIO;
| gpl-3.0 | 03dd15048a7e0ea86393039547743893 | 0.492666 | 3.873131 | false | false | false | false |
yishinli/emc2 | src/hal/drivers/mesa-hostmot2/firmware/src/usbrom.vhd | 1 | 10,573 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
-- Created from usb.obj
-- On 1/14/2009
entity usbrom is
port (
addr: in std_logic_vector(9 downto 0);
clk: in std_logic;
din: in std_logic_vector(15 downto 0);
dout: out std_logic_vector(15 downto 0);
we: in std_logic);
end usbrom;
architecture syn of usbrom is
type ram_type is array (0 to 1023) of std_logic_vector(15 downto 0);
signal RAM : ram_type :=
(
x"0000", x"0000", x"63CB", x"0100", x"E7EE", x"203E", x"0000", x"0000",
x"0000", x"0101", x"B07B", x"0100", x"B7EE", x"0100", x"B7F1", x"0109",
x"B7F2", x"013D", x"B7F3", x"0100", x"B7F4", x"0101", x"B07B", x"707B",
x"97D7", x"A7D1", x"3031", x"0100", x"B07B", x"0000", x"0000", x"0000",
x"0000", x"0000", x"707C", x"B7DC", x"0101", x"B07B", x"77DC", x"C416",
x"B416", x"0100", x"B7F1", x"0109", x"B7F2", x"013D", x"B7F3", x"0100",
x"B7F4", x"77F1", x"E7D1", x"B7F1", x"77F2", x"F7D0", x"B7F2", x"77F3",
x"F7D0", x"B7F3", x"77F4", x"F7D0", x"B7F4", x"4015", x"63CB", x"0100",
x"B07A", x"01EE", x"E06F", x"2047", x"0000", x"01FF", x"B7FF", x"0150",
x"0800", x"0104", x"0A00", x"0100", x"B7FE", x"0100", x"B416", x"0100",
x"B417", x"0100", x"B7DF", x"6361", x"77DC", x"B7D9", x"01C0", x"A7DC",
x"304D", x"0000", x"01FF", x"B7FE", x"011F", x"A7D9", x"B7EB", x"01C0",
x"A7D9", x"B7EA", x"0000", x"0000", x"01C0", x"E7EA", x"206F", x"0000",
x"0000", x"01FF", x"E7D9", x"206F", x"0000", x"0000", x"1047", x"0180",
x"E7EA", x"208E", x"013F", x"A7D9", x"B7EC", x"01FF", x"B7DF", x"0000",
x"77EC", x"C7D0", x"0200", x"0200", x"0200", x"0200", x"0200", x"0B00",
x"0300", x"A7E1", x"0900", x"0700", x"A7E2", x"C7E3", x"0B00", x"0000",
x"0000", x"7900", x"B7D9", x"0D01", x"0000", x"0000", x"77D9", x"B800",
x"0C01", x"01C0", x"A7D9", x"B7EA", x"013F", x"A7D9", x"B7EC", x"0108",
x"A7D9", x"B7F5", x"0104", x"A7D9", x"B7DA", x"0103", x"A7D9", x"B7DB",
x"0120", x"A7D9", x"B7D8", x"0110", x"A7EB", x"B7E0", x"01C0", x"E7EA",
x"20B6", x"0120", x"E7D8", x"20B6", x"0100", x"E7DF", x"30B5", x"0000",
x"0000", x"7900", x"B800", x"0C01", x"10B6", x"632B", x"0140", x"E7EA",
x"2122", x"0104", x"E7DA", x"20CA", x"0100", x"E7DF", x"30C8", x"0000",
x"0000", x"7900", x"B800", x"7901", x"B801", x"0C02", x"0D02", x"10CA",
x"632B", x"632B", x"0120", x"E7D8", x"2122", x"0100", x"E7DB", x"20DA",
x"0110", x"E7E0", x"20D9", x"0000", x"7900", x"B800", x"0C01", x"0D01",
x"10DA", x"632B", x"0101", x"E7DB", x"20EA", x"0110", x"E7E0", x"20E8",
x"0000", x"7900", x"B800", x"7901", x"B801", x"0C02", x"0D02", x"10EA",
x"632B", x"632B", x"0102", x"E7DB", x"2100", x"0110", x"E7E0", x"20FC",
x"0000", x"7900", x"B800", x"7901", x"B801", x"7902", x"B802", x"7903",
x"B803", x"0C04", x"0D04", x"1100", x"632B", x"632B", x"632B", x"632B",
x"0103", x"E7DB", x"2122", x"0110", x"E7E0", x"211A", x"0000", x"7900",
x"B800", x"7901", x"B801", x"7902", x"B802", x"7903", x"B803", x"7904",
x"B804", x"7905", x"B805", x"7906", x"B806", x"7907", x"B807", x"0C08",
x"0D08", x"1122", x"632B", x"632B", x"632B", x"632B", x"632B", x"632B",
x"632B", x"632B", x"0100", x"E7DF", x"2128", x"0000", x"0100", x"B7D9",
x"0100", x"B800", x"0100", x"E7DF", x"313E", x"0000", x"7900", x"B7D9",
x"0D01", x"B800", x"0C01", x"0400", x"E7DD", x"0600", x"F7DE", x"513E",
x"0000", x"0000", x"0110", x"8411", x"B411", x"1047", x"77D9", x"2091",
x"0000", x"0100", x"B7DF", x"0100", x"B800", x"0150", x"0800", x"0104",
x"0A00", x"0000", x"0000", x"7800", x"B7D9", x"0C01", x"0000", x"0000",
x"01C0", x"A7D9", x"B7EA", x"0108", x"A7D9", x"B7F5", x"0104", x"A7D9",
x"B7DA", x"0103", x"A7D9", x"B7DB", x"0120", x"A7D9", x"B7D8", x"01C0",
x"E7EA", x"2250", x"011F", x"A7D9", x"B7EB", x"0120", x"A7D9", x"B7D8",
x"0500", x"B7E6", x"0700", x"B7E7", x"010F", x"E7EB", x"5188", x"0000",
x"0000", x"0110", x"0900", x"0104", x"0B00", x"0500", x"C7EB", x"0900",
x"0700", x"D7D0", x"0B00", x"0120", x"E7D8", x"2184", x"0000", x"0000",
x"7800", x"0C01", x"B900", x"1187", x"0000", x"7900", x"6395", x"124C",
x"0120", x"E7D8", x"21EA", x"0000", x"0000", x"01F7", x"E7D9", x"2195",
x"0000", x"7800", x"0C01", x"B07A", x"11E9", x"01F8", x"E7D9", x"21A7",
x"0100", x"E41A", x"21A2", x"0000", x"0000", x"0000", x"7800", x"0C01",
x"B7E4", x"11A6", x"0000", x"7800", x"0C01", x"B7E8", x"11E9", x"01F9",
x"E7D9", x"21B9", x"0100", x"E41A", x"21B4", x"0000", x"0000", x"0000",
x"7800", x"0C01", x"B7E5", x"11B8", x"0000", x"7800", x"0C01", x"B7E9",
x"11E9", x"01FA", x"E7D9", x"21D1", x"0100", x"E41A", x"21C8", x"0000",
x"7800", x"0C01", x"C7E4", x"B7E4", x"77E5", x"D7D0", x"B7E5", x"11D0",
x"0000", x"7800", x"0C01", x"C7E8", x"B7E8", x"77E9", x"D7D0", x"B7E9",
x"11E9", x"01FD", x"E7D9", x"21D9", x"0000", x"7800", x"0C01", x"B7FB",
x"11E9", x"01FE", x"E7D9", x"21E9", x"0000", x"7800", x"0C01", x"B7DC",
x"0000", x"0000", x"015A", x"E7DC", x"21E8", x"0000", x"0000", x"103E",
x"11E9", x"124C", x"01D0", x"E7D9", x"21F1", x"0000", x"0137", x"6395",
x"124C", x"01D1", x"E7D9", x"21F8", x"0000", x"0149", x"6395", x"124C",
x"01D2", x"E7D9", x"21FF", x"0000", x"0134", x"6395", x"124C", x"01D3",
x"E7D9", x"2206", x"0000", x"0133", x"6395", x"124C", x"01DA", x"E7D9",
x"220D", x"0000", x"0103", x"6395", x"124C", x"01DB", x"E7D9", x"2214",
x"0000", x"742B", x"6395", x"124C", x"01DD", x"E7D9", x"221B", x"0000",
x"0100", x"6395", x"124C", x"01DE", x"E7D9", x"2222", x"0000", x"0104",
x"6395", x"124C", x"01DC", x"E7D9", x"2229", x"0000", x"0110", x"6395",
x"124C", x"01D8", x"E7D9", x"2237", x"0000", x"0100", x"E41A", x"2234",
x"0000", x"0000", x"77E4", x"1235", x"77E8", x"6395", x"124C", x"01D9",
x"E7D9", x"2245", x"0000", x"0100", x"E41A", x"2242", x"0000", x"0000",
x"77E5", x"1243", x"77E9", x"6395", x"124C", x"01DF", x"E7D9", x"224C",
x"0000", x"015A", x"6395", x"124C", x"77E6", x"0900", x"77E7", x"0B00",
x"013F", x"A7D9", x"B7EC", x"0140", x"E7EA", x"2324", x"0104", x"E7DA",
x"2269", x"0100", x"E41A", x"2263", x"0000", x"7800", x"B7E4", x"7801",
x"B7E5", x"0C02", x"1269", x"0000", x"7800", x"B7E8", x"7801", x"B7E9",
x"0C02", x"0100", x"E41A", x"2282", x"0000", x"0000", x"77FF", x"2276",
x"0000", x"77E4", x"0900", x"77E5", x"0B00", x"1281", x"77E4", x"B068",
x"A7D3", x"B7D5", x"77E5", x"B069", x"0100", x"0B00", x"0160", x"C7D5",
x"0900", x"1287", x"77E8", x"0900", x"77E9", x"C7E3", x"0B00", x"0100",
x"E41A", x"2293", x"0000", x"0000", x"77FF", x"2292", x"01FF", x"E7E4",
x"0103", x"F7E5", x"1297", x"01FF", x"E7E8", x"0103", x"F7E9", x"42A1",
x"0000", x"0000", x"0100", x"0900", x"0104", x"0B00", x"0120", x"8411",
x"B411", x"0120", x"E7D8", x"22E4", x"0100", x"E7DB", x"22AD", x"0000",
x"7800", x"B900", x"0C01", x"77D1", x"63A9", x"0101", x"E7DB", x"22B8",
x"0000", x"7800", x"B900", x"7801", x"B901", x"0C02", x"77D2", x"63A9",
x"0102", x"E7DB", x"22C7", x"0000", x"7800", x"B900", x"7801", x"B901",
x"7802", x"B902", x"7803", x"B903", x"0C04", x"77D4", x"63A9", x"0103",
x"E7DB", x"22DE", x"0000", x"7800", x"B900", x"7801", x"B901", x"7802",
x"B902", x"7803", x"B903", x"7804", x"B904", x"7805", x"B905", x"7806",
x"B906", x"7807", x"B907", x"0C08", x"77D6", x"63A9", x"77FF", x"32E3",
x"0000", x"0000", x"B06E", x"1324", x"77FF", x"32E9", x"0000", x"0000",
x"B06D", x"0000", x"0000", x"0000", x"0000", x"0000", x"0100", x"E7DB",
x"22F6", x"0000", x"7900", x"6395", x"77D1", x"63A9", x"0101", x"E7DB",
x"2300", x"0000", x"7900", x"6395", x"7901", x"6395", x"77D2", x"63A9",
x"0102", x"E7DB", x"230E", x"0000", x"7900", x"6395", x"7901", x"6395",
x"7902", x"6395", x"7903", x"6395", x"77D4", x"63A9", x"0103", x"E7DB",
x"2324", x"0000", x"7900", x"6395", x"7901", x"6395", x"7902", x"6395",
x"7903", x"6395", x"7904", x"6395", x"7905", x"6395", x"7906", x"6395",
x"7907", x"6395", x"77D6", x"63A9", x"7800", x"214B", x"0000", x"0000",
x"1047", x"0000", x"0000", x"013B", x"B7FB", x"0111", x"B7FC", x"741B",
x"B7FD", x"77FB", x"E7D1", x"B7FB", x"77FC", x"F7D0", x"B7FC", x"4348",
x"0000", x"013B", x"B7FB", x"0111", x"B7FC", x"77FD", x"E7D1", x"B7FD",
x"4348", x"0000", x"77FE", x"3348", x"0140", x"8411", x"B411", x"1047",
x"0101", x"B07B", x"707B", x"97D7", x"A7D1", x"3331", x"0000", x"0100",
x"B07B", x"0000", x"0000", x"0000", x"0000", x"0000", x"707C", x"B7DC",
x"0101", x"B07B", x"77DC", x"C416", x"B416", x"77DC", x"B800", x"0C01",
x"1800", x"013B", x"B7FB", x"0111", x"B7FC", x"741B", x"B7FD", x"77FB",
x"E7D1", x"B7FB", x"77FC", x"F7D0", x"B7FC", x"437E", x"0000", x"013B",
x"B7FB", x"0111", x"B7FC", x"77FD", x"E7D1", x"B7FD", x"437E", x"0000",
x"77FE", x"337E", x"0140", x"8411", x"B411", x"1047", x"0101", x"B07B",
x"707B", x"97D7", x"A7D1", x"3367", x"0000", x"0100", x"B07B", x"0000",
x"0000", x"0000", x"0000", x"0000", x"707C", x"B7DC", x"0101", x"B07B",
x"77DC", x"C416", x"B416", x"0000", x"1800", x"B7DC", x"0101", x"B07B",
x"707B", x"97D7", x"A7D2", x"3396", x"0000", x"0000", x"0105", x"B07B",
x"0107", x"B07B", x"77DC", x"B07C", x"C417", x"B417", x"0101", x"B07B",
x"1800", x"B7F6", x"77F5", x"3800", x"0500", x"C7F6", x"0900", x"0700",
x"D7D0", x"0B00", x"0100", x"E41A", x"23C5", x"0000", x"0000", x"77FF",
x"33C0", x"77E4", x"C7F6", x"B7E4", x"77E5", x"D7D0", x"B7E5", x"13C4",
x"0500", x"B7E4", x"0700", x"B7E5", x"13CA", x"0500", x"B7E8", x"0700",
x"E7E3", x"B7E9", x"1800", x"0100", x"B7DC", x"B7E0", x"B410", x"B411",
x"B412", x"B413", x"B415", x"B416", x"B417", x"B418", x"B419", x"B41A",
x"B42B", x"B7FB", x"B7D0", x"01FF", x"B41B", x"0101", x"B7D1", x"0102",
x"B7D2", x"0103", x"B7D3", x"0104", x"B7D4", x"0108", x"B7D6", x"01FF",
x"B7D7", x"01F0", x"B7E1", x"0103", x"B7E2", x"010C", x"B7E3", x"01C0",
x"B7EA", x"017A", x"B7E4", x"0100", x"B7E5", x"0100", x"B7E8", x"0100",
x"B7E9", x"01BE", x"B7DD", x"0107", x"B7DE", x"1800", x"0000", x"0000"
);
signal daddr: std_logic_vector(9 downto 0);
begin
ausbrom: process (clk)
begin
if (clk'event and clk = '1') then
if (we = '1') then
RAM(conv_integer(addr)) <= din;
end if;
daddr <= addr;
end if; -- clk
end process;
dout <= RAM(conv_integer(daddr));
end;
| lgpl-2.1 | 872a05707f3e31e05b21292f458fe66b | 0.53211 | 1.87931 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/greth/greths_mb.vhd | 1 | 9,644 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: greths_mb
-- File: greths_mb.vhd
-- Authors: Andrea Gianarro
-- Description: Gigabit Ethernet Media Access Controller with Ethernet Debug
-- Communication Link, dual AHB master interfaces and Serial
-- GMII interface
------------------------------------------------------------------------------
library ieee;
library grlib;
library gaisler;
use ieee.std_logic_1164.all;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use gaisler.net.all;
use gaisler.ethernet_mac.all;
library eth;
use eth.ethcomp.all;
entity greths_mb is
generic(
hindex : integer := 0;
ehindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
fabtech : integer := 0;
memtech : integer := 0;
transtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 64 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
burstlength : integer range 4 to 128 := 32;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
rmii : integer range 0 to 1 := 0;
sim : integer range 0 to 1 := 0;
giga : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 2 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
edclsepahbg : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
maxsize : integer := 1500;
pcs_phyaddr : integer range 0 to 32 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbmi2 : in ahb_mst_in_type;
ahbmo2 : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
-- High-speed Serial Interface
clk_125 : in std_logic;
rst_125 : in std_logic;
eth_rx_p : in std_logic;
eth_rx_n : in std_logic := '0';
eth_tx_p : out std_logic;
eth_tx_n : out std_logic;
-- MDIO interface
reset : out std_logic;
mdio_o : out std_logic;
mdio_oe : out std_logic;
mdio_i : in std_logic;
mdc : out std_logic;
mdint : in std_logic;
-- Control signals
phyrstaddr : in std_logic_vector(4 downto 0);
edcladdr : in std_logic_vector(3 downto 0);
edclsepahb : in std_logic;
edcldisable : in std_logic;
debug_pcs_mdio : in std_logic := '0';
-- added for igloo2_serdes
apbin : in apb_in_serdes := apb_in_serdes_none;
apbout : out apb_out_serdes;
m2gl_padin : in pad_in_serdes := pad_in_serdes_none;
m2gl_padout : out pad_out_serdes;
serdes_clk125 : out std_logic;
rx_aligned : out std_logic
);
end entity;
architecture rtl of greths_mb is
-- GMII and MII signals between MAC and PCS
signal mac_ethi : eth_in_type;
signal pcs_ethi : eth_in_type;
signal mac_etho : eth_out_type;
signal pcs_etho : eth_out_type;
signal int_tx_rstn : std_logic;
signal int_rx_rstn : std_logic;
-- MDIO signals
signal mdio_o_pcs : std_logic;
signal mdio_oe_pcs : std_logic;
signal mdio_i_pcs : std_logic;
begin
-------------------------------------------------------------------------------
-- Ethernet MAC
-------------------------------------------------------------------------------
u0 : grethm_mb
generic map (
hindex => hindex,
ehindex => ehindex,
pindex => pindex,
paddr => paddr,
pmask => pmask,
pirq => pirq,
memtech => memtech,
ifg_gap => ifg_gap,
attempt_limit => attempt_limit,
backoff_limit => backoff_limit,
slot_time => slot_time,
mdcscaler => mdcscaler,
enable_mdio => enable_mdio,
fifosize => fifosize,
nsync => nsync,
edcl => edcl,
edclbufsz => edclbufsz,
burstlength => burstlength,
macaddrh => macaddrh,
macaddrl => macaddrl,
ipaddrh => ipaddrh,
ipaddrl => ipaddrl,
phyrstadr => phyrstadr,
rmii => rmii,
sim => sim,
giga => giga,
oepol => oepol,
scanen => scanen,
ft => ft,
edclft => edclft,
mdint_pol => mdint_pol,
enable_mdint => enable_mdint,
multicast => multicast,
edclsepahb => edclsepahbg,
ramdebug => ramdebug,
mdiohold => mdiohold,
maxsize => maxsize,
gmiimode => 1
)
port map (
rst => rst,
clk => clk,
ahbmi => ahbmi,
ahbmo => ahbmo,
ahbmi2 => ahbmi2,
ahbmo2 => ahbmo2,
apbi => apbi,
apbo => apbo,
ethi => mac_ethi,
etho => mac_etho
);
-------------------------------------------------------------------------------
-- 1000baseX-compliant SGMII bridge
-------------------------------------------------------------------------------
sgmii0: sgmii
generic map (
fabtech => fabtech,
memtech => memtech,
transtech => transtech,
phy_addr => pcs_phyaddr
)
port map(
clk_125 => clk_125,
rst_125 => rst_125,
ser_rx_p => eth_rx_p,
ser_rx_n => eth_rx_n,
ser_tx_p => eth_tx_p,
ser_tx_n => eth_tx_n,
txd => pcs_etho.txd,
tx_en => pcs_etho.tx_en,
tx_er => pcs_etho.tx_er,
tx_clk => pcs_ethi.gtx_clk,
tx_rstn => int_tx_rstn,
rxd => pcs_ethi.rxd,
rx_dv => pcs_ethi.rx_dv,
rx_er => pcs_ethi.rx_er,
rx_col => pcs_ethi.rx_col,
rx_crs => pcs_ethi.rx_crs,
rx_clk => pcs_ethi.rx_clk,
rx_rstn => int_rx_rstn,
-- optional MDIO interface to PCS
mdc => pcs_etho.mdc,
mdio_o => mdio_o_pcs,
mdio_oe => mdio_oe_pcs,
mdio_i => mdio_i_pcs,
-- added for igloo2_serdes
apbin => apbin,
apbout => apbout,
m2gl_padin => m2gl_padin,
m2gl_padout => m2gl_padout,
serdes_clk125 => serdes_clk125,
rx_aligned => rx_aligned
);
-- 10/100 Mbit GMII to MII adapter
adapt_10_100_0 : gmii_to_mii
port map (
tx_rstn => int_tx_rstn,
rx_rstn => int_rx_rstn,
gmiii => mac_ethi, -- OUT
gmiio => mac_etho, -- IN
miii => pcs_ethi, -- IN
miio => pcs_etho -- OUT
);
-- Drive MDIO signals (including PCS bypass to MAC)
reset <= pcs_etho.reset;
mdc <= pcs_etho.mdc;
mdio_oe <= '1' when debug_pcs_mdio = '1' else pcs_etho.mdio_oe;
mdio_o <= '0' when debug_pcs_mdio = '1' else pcs_etho.mdio_o;
mdio_oe_pcs <= pcs_etho.mdio_oe when debug_pcs_mdio = '1' else '1';
mdio_o_pcs <= pcs_etho.mdio_o when debug_pcs_mdio = '1' else '0';
pcs_ethi.mdint <= mdint;
pcs_ethi.mdio_i <= mdio_i_pcs when debug_pcs_mdio = '1' else mdio_i;
-- MAC input signals integration
pcs_ethi.tx_clk <= pcs_ethi.gtx_clk;
pcs_ethi.phyrstaddr <= phyrstaddr;
pcs_ethi.edcladdr <= edcladdr;
pcs_ethi.edclsepahb <= edclsepahb;
pcs_ethi.edcldisable <= edcldisable;
end architecture;
| gpl-3.0 | d7a62b96ee7101f73c1ab619dbe76b1c | 0.49523 | 3.834592 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/ec/memory_ec.vhd | 1 | 92,641 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: mem_ec_gen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Memory generators for Lattice XP/EC/ECP RAM blocks
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.dp8ka;
-- pragma translate_on
entity EC_RAMB8_S1_S1 is
port (
DataInA: in std_logic_vector(0 downto 0);
DataInB: in std_logic_vector(0 downto 0);
AddressA: in std_logic_vector(12 downto 0);
AddressB: in std_logic_vector(12 downto 0);
ClockA: in std_logic;
ClockB: in std_logic;
ClockEnA: in std_logic;
ClockEnB: in std_logic;
WrA: in std_logic;
WrB: in std_logic;
QA: out std_logic_vector(0 downto 0);
QB: out std_logic_vector(0 downto 0));
end;
architecture Structure of EC_RAMB8_S1_S1 is
COMPONENT dp8ka
GENERIC(
DATA_WIDTH_A : in Integer := 18;
DATA_WIDTH_B : in Integer := 18;
REGMODE_A : String := "NOREG";
REGMODE_B : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE_A : String := "000";
CSDECODE_B : String := "000";
WRITEMODE_A : String := "NORMAL";
WRITEMODE_B : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic := 'X';
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic := 'X';
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic := 'X';
ada9, ada10, ada11, ada12 : in std_logic := 'X';
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic := 'X';
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic := 'X';
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic := 'X';
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic := 'X';
adb9, adb10, adb11, adb12 : in std_logic := 'X';
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic := 'X';
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic := 'X';
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic := 'X';
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic := 'X';
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: DP8KA
generic map (CSDECODE_B=>"000", CSDECODE_A=>"000",
WRITEMODE_B=>"NORMAL", WRITEMODE_A=>"NORMAL",
GSR=>"DISABLED", RESETMODE=>"ASYNC", REGMODE_B=>"NOREG",
REGMODE_A=>"NOREG", DATA_WIDTH_B=> 1, DATA_WIDTH_A=> 1)
port map (CEA=>ClockEnA, CLKA=>ClockA, WEA=>WrA, CSA0=>gnd,
CSA1=>gnd, CSA2=>gnd, RSTA=>gnd,
CEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB, CSB0=>gnd,
CSB1=>gnd, CSB2=>gnd, RSTB=>gnd,
DIA0=>gnd, DIA1=>gnd, DIA2=>gnd,
DIA3=>gnd, DIA4=>gnd, DIA5=>gnd,
DIA6=>gnd, DIA7=>gnd, DIA8=>gnd,
DIA9=>gnd, DIA10=>gnd, DIA11=>DataInA(0),
DIA12=>gnd, DIA13=>gnd, DIA14=>gnd,
DIA15=>gnd, DIA16=>gnd, DIA17=>gnd,
ADA0=>AddressA(0), ADA1=>AddressA(1), ADA2=>AddressA(2),
ADA3=>AddressA(3), ADA4=>AddressA(4), ADA5=>AddressA(5),
ADA6=>AddressA(6), ADA7=>AddressA(7), ADA8=>AddressA(8),
ADA9=>AddressA(9), ADA10=>AddressA(10), ADA11=>AddressA(11),
ADA12=>AddressA(12), DIB0=>gnd, DIB1=>gnd,
DIB2=>gnd, DIB3=>gnd, DIB4=>gnd,
DIB5=>gnd, DIB6=>gnd, DIB7=>gnd,
DIB8=>gnd, DIB9=>gnd, DIB10=>gnd,
DIB11=>DataInB(0), DIB12=>gnd, DIB13=>gnd,
DIB14=>gnd, DIB15=>gnd, DIB16=>gnd,
DIB17=>gnd, ADB0=>AddressB(0), ADB1=>AddressB(1),
ADB2=>AddressB(2), ADB3=>AddressB(3), ADB4=>AddressB(4),
ADB5=>AddressB(5), ADB6=>AddressB(6), ADB7=>AddressB(7),
ADB8=>AddressB(8), ADB9=>AddressB(9), ADB10=>AddressB(10),
ADB11=>AddressB(11), ADB12=>AddressB(12), DOA0=>QA(0),
DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
DOA17=>open, DOB0=>QB(0), DOB1=>open, DOB2=>open,
DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open,
DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
DOB15=>open, DOB16=>open, DOB17=>open);
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.dp8ka;
-- pragma translate_on
entity EC_RAMB8_S2_S2 is
port (
DataInA: in std_logic_vector(1 downto 0);
DataInB: in std_logic_vector(1 downto 0);
AddressA: in std_logic_vector(11 downto 0);
AddressB: in std_logic_vector(11 downto 0);
ClockA: in std_logic;
ClockB: in std_logic;
ClockEnA: in std_logic;
ClockEnB: in std_logic;
WrA: in std_logic;
WrB: in std_logic;
QA: out std_logic_vector(1 downto 0);
QB: out std_logic_vector(1 downto 0));
end;
architecture Structure of EC_RAMB8_S2_S2 is
COMPONENT dp8ka
GENERIC(
DATA_WIDTH_A : in Integer := 18;
DATA_WIDTH_B : in Integer := 18;
REGMODE_A : String := "NOREG";
REGMODE_B : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE_A : String := "000";
CSDECODE_B : String := "000";
WRITEMODE_A : String := "NORMAL";
WRITEMODE_B : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic := 'X';
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic := 'X';
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic := 'X';
ada9, ada10, ada11, ada12 : in std_logic := 'X';
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic := 'X';
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic := 'X';
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic := 'X';
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic := 'X';
adb9, adb10, adb11, adb12 : in std_logic := 'X';
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic := 'X';
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic := 'X';
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic := 'X';
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic := 'X';
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: DP8KA
generic map (CSDECODE_B=>"000", CSDECODE_A=>"000",
WRITEMODE_B=>"NORMAL", WRITEMODE_A=>"NORMAL",
GSR=>"DISABLED", RESETMODE=>"ASYNC", REGMODE_B=>"NOREG",
REGMODE_A=>"NOREG", DATA_WIDTH_B=> 2, DATA_WIDTH_A=> 2)
port map (CEA=>ClockEnA, CLKA=>ClockA, WEA=>WrA, CSA0=>gnd,
CSA1=>gnd, CSA2=>gnd, RSTA=>gnd,
CEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB, CSB0=>gnd,
CSB1=>gnd, CSB2=>gnd, RSTB=>gnd,
DIA0=>gnd, DIA1=>DataInA(0), DIA2=>gnd,
DIA3=>gnd, DIA4=>gnd, DIA5=>gnd,
DIA6=>gnd, DIA7=>gnd, DIA8=>gnd,
DIA9=>gnd, DIA10=>gnd, DIA11=>DataInA(1),
DIA12=>gnd, DIA13=>gnd, DIA14=>gnd,
DIA15=>gnd, DIA16=>gnd, DIA17=>gnd,
ADA0=>vcc, ADA1=>AddressA(0), ADA2=>AddressA(1),
ADA3=>AddressA(2), ADA4=>AddressA(3), ADA5=>AddressA(4),
ADA6=>AddressA(6), ADA7=>AddressA(6), ADA8=>AddressA(7),
ADA9=>AddressA(8), ADA10=>AddressA(9), ADA11=>AddressA(10),
ADA12=>AddressA(11), DIB0=>gnd, DIB1=>DataInB(0),
DIB2=>gnd, DIB3=>gnd, DIB4=>gnd,
DIB5=>gnd, DIB6=>gnd, DIB7=>gnd,
DIB8=>gnd, DIB9=>gnd, DIB10=>gnd,
DIB11=>DataInB(1), DIB12=>gnd, DIB13=>gnd,
DIB14=>gnd, DIB15=>gnd, DIB16=>gnd,
DIB17=>gnd, ADB0=>vcc, ADB1=>AddressB(0),
ADB2=>AddressB(1), ADB3=>AddressB(2), ADB4=>AddressB(3),
ADB5=>AddressB(4), ADB6=>AddressB(5), ADB7=>AddressB(6),
ADB8=>AddressB(7), ADB9=>AddressB(8), ADB10=>AddressB(9),
ADB11=>AddressB(10), ADB12=>AddressB(11), DOA0=>QA(1),
DOA1=>QA(0), DOA2=>open, DOA3=>open, DOA4=>open,
DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
DOA17=>open, DOB0=>QB(1), DOB1=>QB(0), DOB2=>open,
DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open,
DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
DOB15=>open, DOB16=>open, DOB17=>open);
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.dp8ka;
-- pragma translate_on
entity EC_RAMB8_S4_S4 is
port (
DataInA: in std_logic_vector(3 downto 0);
DataInB: in std_logic_vector(3 downto 0);
AddressA: in std_logic_vector(10 downto 0);
AddressB: in std_logic_vector(10 downto 0);
ClockA: in std_logic;
ClockB: in std_logic;
ClockEnA: in std_logic;
ClockEnB: in std_logic;
WrA: in std_logic;
WrB: in std_logic;
QA: out std_logic_vector(3 downto 0);
QB: out std_logic_vector(3 downto 0));
end;
architecture Structure of EC_RAMB8_S4_S4 is
COMPONENT dp8ka
GENERIC(
DATA_WIDTH_A : in Integer := 18;
DATA_WIDTH_B : in Integer := 18;
REGMODE_A : String := "NOREG";
REGMODE_B : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE_A : String := "000";
CSDECODE_B : String := "000";
WRITEMODE_A : String := "NORMAL";
WRITEMODE_B : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic := 'X';
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic := 'X';
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic := 'X';
ada9, ada10, ada11, ada12 : in std_logic := 'X';
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic := 'X';
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic := 'X';
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic := 'X';
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic := 'X';
adb9, adb10, adb11, adb12 : in std_logic := 'X';
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic := 'X';
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic := 'X';
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic := 'X';
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic := 'X';
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: DP8KA
generic map (CSDECODE_B=>"000", CSDECODE_A=>"000",
WRITEMODE_B=>"NORMAL", WRITEMODE_A=>"NORMAL",
GSR=>"DISABLED", RESETMODE=>"ASYNC", REGMODE_B=>"NOREG",
REGMODE_A=>"NOREG", DATA_WIDTH_B=> 4, DATA_WIDTH_A=> 4)
port map (CEA=>ClockEnA, CLKA=>ClockA, WEA=>WrA, CSA0=>gnd,
CSA1=>gnd, CSA2=>gnd, RSTA=>gnd,
CEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB, CSB0=>gnd,
CSB1=>gnd, CSB2=>gnd, RSTB=>gnd,
DIA0=>DataInA(0), DIA1=>DataInA(1), DIA2=>DataInA(2),
DIA3=>DataInA(3), DIA4=>gnd, DIA5=>gnd,
DIA6=>gnd, DIA7=>gnd, DIA8=>gnd,
DIA9=>gnd, DIA10=>gnd, DIA11=>gnd,
DIA12=>gnd, DIA13=>gnd, DIA14=>gnd,
DIA15=>gnd, DIA16=>gnd, DIA17=>gnd,
ADA0=>vcc, ADA1=>vcc, ADA2=>AddressA(0),
ADA3=>AddressA(1), ADA4=>AddressA(2), ADA5=>AddressA(3),
ADA6=>AddressA(4), ADA7=>AddressA(5), ADA8=>AddressA(6),
ADA9=>AddressA(7), ADA10=>AddressA(8), ADA11=>AddressA(9),
ADA12=>AddressA(10), DIB0=>DataInB(0), DIB1=>DataInB(1),
DIB2=>DataInB(2), DIB3=>DataInB(3), DIB4=>gnd,
DIB5=>gnd, DIB6=>gnd, DIB7=>gnd,
DIB8=>gnd, DIB9=>gnd, DIB10=>gnd,
DIB11=>gnd, DIB12=>gnd, DIB13=>gnd,
DIB14=>gnd, DIB15=>gnd, DIB16=>gnd,
DIB17=>gnd, ADB0=>vcc, ADB1=>vcc,
ADB2=>AddressB(0), ADB3=>AddressB(1), ADB4=>AddressB(2),
ADB5=>AddressB(3), ADB6=>AddressB(4), ADB7=>AddressB(5),
ADB8=>AddressB(6), ADB9=>AddressB(7), ADB10=>AddressB(8),
ADB11=>AddressB(9), ADB12=>AddressB(10), DOA0=>QA(0),
DOA1=>QA(1), DOA2=>QA(2), DOA3=>QA(3), DOA4=>open,
DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
DOA17=>open, DOB0=>QB(0), DOB1=>QB(1), DOB2=>QB(2),
DOB3=>QB(3), DOB4=>open, DOB5=>open, DOB6=>open,
DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open,
DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
DOB15=>open, DOB16=>open, DOB17=>open);
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.dp8ka;
-- pragma translate_on
entity EC_RAMB8_S9_S9 is
port (
DataInA: in std_logic_vector(8 downto 0);
DataInB: in std_logic_vector(8 downto 0);
AddressA: in std_logic_vector(9 downto 0);
AddressB: in std_logic_vector(9 downto 0);
ClockA: in std_logic;
ClockB: in std_logic;
ClockEnA: in std_logic;
ClockEnB: in std_logic;
WrA: in std_logic;
WrB: in std_logic;
QA: out std_logic_vector(8 downto 0);
QB: out std_logic_vector(8 downto 0));
end;
architecture Structure of EC_RAMB8_S9_S9 is
COMPONENT dp8ka
GENERIC(
DATA_WIDTH_A : in Integer := 18;
DATA_WIDTH_B : in Integer := 18;
REGMODE_A : String := "NOREG";
REGMODE_B : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE_A : String := "000";
CSDECODE_B : String := "000";
WRITEMODE_A : String := "NORMAL";
WRITEMODE_B : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic := 'X';
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic := 'X';
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic := 'X';
ada9, ada10, ada11, ada12 : in std_logic := 'X';
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic := 'X';
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic := 'X';
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic := 'X';
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic := 'X';
adb9, adb10, adb11, adb12 : in std_logic := 'X';
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic := 'X';
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic := 'X';
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic := 'X';
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic := 'X';
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: DP8KA
generic map (CSDECODE_B=>"000", CSDECODE_A=>"000",
WRITEMODE_B=>"NORMAL", WRITEMODE_A=>"NORMAL",
GSR=>"DISABLED", RESETMODE=>"ASYNC", REGMODE_B=>"NOREG",
REGMODE_A=>"NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 9)
port map (CEA=>ClockEnA, CLKA=>ClockA, WEA=>WrA, CSA0=>gnd,
CSA1=>gnd, CSA2=>gnd, RSTA=>gnd,
CEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB, CSB0=>gnd,
CSB1=>gnd, CSB2=>gnd, RSTB=>gnd,
DIA0=>DataInA(0), DIA1=>DataInA(1), DIA2=>DataInA(2),
DIA3=>DataInA(3), DIA4=>DataInA(4), DIA5=>DataInA(5),
DIA6=>DataInA(6), DIA7=>DataInA(7), DIA8=>DataInA(8),
DIA9=>gnd, DIA10=>gnd, DIA11=>gnd,
DIA12=>gnd, DIA13=>gnd, DIA14=>gnd,
DIA15=>gnd, DIA16=>gnd, DIA17=>gnd,
ADA0=>vcc, ADA1=>vcc, ADA2=>gnd,
ADA3=>AddressA(0), ADA4=>AddressA(1), ADA5=>AddressA(2),
ADA6=>AddressA(3), ADA7=>AddressA(4), ADA8=>AddressA(5),
ADA9=>AddressA(6), ADA10=>AddressA(7), ADA11=>AddressA(8),
ADA12=>AddressA(9), DIB0=>DataInB(0), DIB1=>DataInB(1),
DIB2=>DataInB(2), DIB3=>DataInB(3), DIB4=>DataInB(4),
DIB5=>DataInB(5), DIB6=>DataInB(6), DIB7=>DataInB(7),
DIB8=>DataInB(8), DIB9=>gnd, DIB10=>gnd,
DIB11=>gnd, DIB12=>gnd, DIB13=>gnd,
DIB14=>gnd, DIB15=>gnd, DIB16=>gnd,
DIB17=>gnd, ADB0=>vcc, ADB1=>vcc,
ADB2=>gnd, ADB3=>AddressB(0), ADB4=>AddressB(1),
ADB5=>AddressB(2), ADB6=>AddressB(3), ADB7=>AddressB(4),
ADB8=>AddressB(5), ADB9=>AddressB(6), ADB10=>AddressB(7),
ADB11=>AddressB(8), ADB12=>AddressB(9), DOA0=>QA(0),
DOA1=>QA(1), DOA2=>QA(2), DOA3=>QA(3), DOA4=>QA(4),
DOA5=>QA(5), DOA6=>QA(6), DOA7=>QA(7), DOA8=>QA(8),
DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
DOA17=>open, DOB0=>QB(0), DOB1=>QB(1), DOB2=>QB(2),
DOB3=>QB(3), DOB4=>QB(4), DOB5=>QB(5), DOB6=>QB(6),
DOB7=>QB(7), DOB8=>QB(8), DOB9=>open, DOB10=>open,
DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
DOB15=>open, DOB16=>open, DOB17=>open);
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.dp8ka;
-- pragma translate_on
entity EC_RAMB8_S18_S18 is
port (
DataInA: in std_logic_vector(17 downto 0);
DataInB: in std_logic_vector(17 downto 0);
AddressA: in std_logic_vector(8 downto 0);
AddressB: in std_logic_vector(8 downto 0);
ClockA: in std_logic;
ClockB: in std_logic;
ClockEnA: in std_logic;
ClockEnB: in std_logic;
WrA: in std_logic;
WrB: in std_logic;
QA: out std_logic_vector(17 downto 0);
QB: out std_logic_vector(17 downto 0));
end;
architecture Structure of EC_RAMB8_S18_S18 is
COMPONENT dp8ka
GENERIC(
DATA_WIDTH_A : in Integer := 18;
DATA_WIDTH_B : in Integer := 18;
REGMODE_A : String := "NOREG";
REGMODE_B : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE_A : String := "000";
CSDECODE_B : String := "000";
WRITEMODE_A : String := "NORMAL";
WRITEMODE_B : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic := 'X';
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic := 'X';
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic := 'X';
ada9, ada10, ada11, ada12 : in std_logic := 'X';
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic := 'X';
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic := 'X';
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic := 'X';
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic := 'X';
adb9, adb10, adb11, adb12 : in std_logic := 'X';
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic := 'X';
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic := 'X';
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic := 'X';
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic := 'X';
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: DP8KA
generic map (CSDECODE_B=>"000", CSDECODE_A=>"000",
WRITEMODE_B=>"NORMAL", WRITEMODE_A=>"NORMAL",
GSR=>"DISABLED", RESETMODE=>"ASYNC", REGMODE_B=>"NOREG",
REGMODE_A=>"NOREG", DATA_WIDTH_B=> 18, DATA_WIDTH_A=> 18)
port map (CEA=>ClockEnA, CLKA=>ClockA, WEA=>WrA, CSA0=>gnd,
CSA1=>gnd, CSA2=>gnd, RSTA=>gnd,
CEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB, CSB0=>gnd,
CSB1=>gnd, CSB2=>gnd, RSTB=>gnd,
DIA0=>DataInA(0), DIA1=>DataInA(1), DIA2=>DataInA(2),
DIA3=>DataInA(3), DIA4=>DataInA(4), DIA5=>DataInA(5),
DIA6=>DataInA(6), DIA7=>DataInA(7), DIA8=>DataInA(8),
DIA9=>DataInA(9), DIA10=>DataInA(10), DIA11=>DataInA(11),
DIA12=>DataInA(12), DIA13=>DataInA(13), DIA14=>DataInA(14),
DIA15=>DataInA(15), DIA16=>DataInA(16), DIA17=>DataInA(17),
ADA0=>vcc, ADA1=>vcc, ADA2=>gnd,
ADA3=>gnd, ADA4=>AddressA(0), ADA5=>AddressA(1),
ADA6=>AddressA(2), ADA7=>AddressA(3), ADA8=>AddressA(4),
ADA9=>AddressA(5), ADA10=>AddressA(6), ADA11=>AddressA(7),
ADA12=>AddressA(8), DIB0=>DataInB(0), DIB1=>DataInB(1),
DIB2=>DataInB(2), DIB3=>DataInB(3), DIB4=>DataInB(4),
DIB5=>DataInB(5), DIB6=>DataInB(6), DIB7=>DataInB(7),
DIB8=>DataInB(8), DIB9=>DataInB(9), DIB10=>DataInB(10),
DIB11=>DataInB(11), DIB12=>DataInB(12), DIB13=>DataInB(13),
DIB14=>DataInB(14), DIB15=>DataInB(15), DIB16=>DataInB(16),
DIB17=>DataInB(17), ADB0=>vcc, ADB1=>vcc,
ADB2=>gnd, ADB3=>gnd, ADB4=>AddressB(0),
ADB5=>AddressB(1), ADB6=>AddressB(2), ADB7=>AddressB(3),
ADB8=>AddressB(4), ADB9=>AddressB(5), ADB10=>AddressB(6),
ADB11=>AddressB(7), ADB12=>AddressB(8), DOA0=>QA(0),
DOA1=>QA(1), DOA2=>QA(2), DOA3=>QA(3), DOA4=>QA(4),
DOA5=>QA(5), DOA6=>QA(6), DOA7=>QA(7), DOA8=>QA(8),
DOA9=>QA(9), DOA10=>QA(10), DOA11=>QA(11), DOA12=>QA(12),
DOA13=>QA(13), DOA14=>QA(14), DOA15=>QA(15), DOA16=>QA(16),
DOA17=>QA(17), DOB0=>QB(0), DOB1=>QB(1), DOB2=>QB(2),
DOB3=>QB(3), DOB4=>QB(4), DOB5=>QB(5), DOB6=>QB(6),
DOB7=>QB(7), DOB8=>QB(8), DOB9=>QB(9), DOB10=>QB(10),
DOB11=>QB(11), DOB12=>QB(12), DOB13=>QB(13), DOB14=>QB(14),
DOB15=>QB(15), DOB16=>QB(16), DOB17=>QB(17));
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.sp8ka;
-- pragma translate_on
entity EC_RAMB8_S1 is
port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (12 downto 0);
data : in std_logic_vector (0 downto 0);
q : out std_logic_vector (0 downto 0));
end;
architecture behav of EC_RAMB8_S1 is
COMPONENT sp8ka
GENERIC(
DATA_WIDTH : in Integer := 18;
REGMODE : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE : String := "000";
WRITEMODE : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
di0, di1, di2, di3, di4, di5, di6, di7, di8 : in std_logic := 'X';
di9, di10, di11, di12, di13, di14, di15, di16, di17 : in std_logic := 'X';
ad0, ad1, ad2, ad3, ad4, ad5, ad6, ad7, ad8 : in std_logic := 'X';
ad9, ad10, ad11, ad12 : in std_logic := 'X';
ce, clk, we, cs0, cs1, cs2, rst : in std_logic := 'X';
do0, do1, do2, do3, do4, do5, do6, do7, do8 : out std_logic := 'X';
do9, do10, do11, do12, do13, do14, do15, do16, do17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: SP8KA
generic map (CSDECODE=>"000", GSR=>"DISABLED",
WRITEMODE=>"WRITETHROUGH", RESETMODE=>"ASYNC",
REGMODE=>"NOREG", DATA_WIDTH=> 1)
port map (CE=>En, CLK=>Clk, WE=>WE, CS0=>gnd,
CS1=>gnd, CS2=>gnd, RST=>gnd, DI0=>gnd,
DI1=>gnd, DI2=>gnd, DI3=>gnd, DI4=>gnd,
DI5=>gnd, DI6=>gnd, DI7=>gnd, DI8=>gnd,
DI9=>gnd, DI10=>gnd, DI11=>Data(0),
DI12=>gnd, DI13=>gnd, DI14=>gnd,
DI15=>gnd, DI16=>gnd, DI17=>gnd,
AD0=>Address(0), AD1=>Address(1), AD2=>Address(2),
AD3=>Address(3), AD4=>Address(4), AD5=>Address(5),
AD6=>Address(6), AD7=>Address(7), AD8=>Address(8),
AD9=>Address(9), AD10=>Address(10), AD11=>Address(11),
AD12=>Address(12), DO0=>Q(0), DO1=>open, DO2=>open, DO3=>open,
DO4=>open, DO5=>open, DO6=>open, DO7=>open, DO8=>open,
DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
DO14=>open, DO15=>open, DO16=>open, DO17=>open);
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.sp8ka;
-- pragma translate_on
entity EC_RAMB8_S2 is
port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (11 downto 0);
data : in std_logic_vector (1 downto 0);
q : out std_logic_vector (1 downto 0));
end;
architecture behav of EC_RAMB8_S2 is
COMPONENT sp8ka
GENERIC(
DATA_WIDTH : in Integer := 18;
REGMODE : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE : String := "000";
WRITEMODE : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
di0, di1, di2, di3, di4, di5, di6, di7, di8 : in std_logic := 'X';
di9, di10, di11, di12, di13, di14, di15, di16, di17 : in std_logic := 'X';
ad0, ad1, ad2, ad3, ad4, ad5, ad6, ad7, ad8 : in std_logic := 'X';
ad9, ad10, ad11, ad12 : in std_logic := 'X';
ce, clk, we, cs0, cs1, cs2, rst : in std_logic := 'X';
do0, do1, do2, do3, do4, do5, do6, do7, do8 : out std_logic := 'X';
do9, do10, do11, do12, do13, do14, do15, do16, do17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: SP8KA
generic map (CSDECODE=>"000", GSR=>"DISABLED",
WRITEMODE=>"WRITETHROUGH", RESETMODE=>"ASYNC",
REGMODE=>"NOREG", DATA_WIDTH=> 2)
port map (CE=>En, CLK=>Clk, WE=>WE, CS0=>gnd,
CS1=>gnd, CS2=>gnd, RST=>gnd, DI0=>gnd,
DI1=>Data(0), DI2=>gnd, DI3=>gnd, DI4=>gnd,
DI5=>gnd, DI6=>gnd, DI7=>gnd, DI8=>gnd,
DI9=>gnd, DI10=>gnd, DI11=>Data(1),
DI12=>gnd, DI13=>gnd, DI14=>gnd,
DI15=>gnd, DI16=>gnd, DI17=>gnd,
AD0=>gnd, AD1=>Address(0), AD2=>Address(1),
AD3=>Address(2), AD4=>Address(3), AD5=>Address(4),
AD6=>Address(5), AD7=>Address(6), AD8=>Address(7),
AD9=>Address(8), AD10=>Address(9), AD11=>Address(10),
AD12=>Address(11), DO0=>Q(1), DO1=>Q(0), DO2=>open, DO3=>open,
DO4=>open, DO5=>open, DO6=>open, DO7=>open, DO8=>open,
DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
DO14=>open, DO15=>open, DO16=>open, DO17=>open);
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.sp8ka;
-- pragma translate_on
entity EC_RAMB8_S4 is
port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (10 downto 0);
data : in std_logic_vector (3 downto 0);
q : out std_logic_vector (3 downto 0));
end;
architecture behav of EC_RAMB8_S4 is
COMPONENT sp8ka
GENERIC(
DATA_WIDTH : in Integer := 18;
REGMODE : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE : String := "000";
WRITEMODE : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
di0, di1, di2, di3, di4, di5, di6, di7, di8 : in std_logic := 'X';
di9, di10, di11, di12, di13, di14, di15, di16, di17 : in std_logic := 'X';
ad0, ad1, ad2, ad3, ad4, ad5, ad6, ad7, ad8 : in std_logic := 'X';
ad9, ad10, ad11, ad12 : in std_logic := 'X';
ce, clk, we, cs0, cs1, cs2, rst : in std_logic := 'X';
do0, do1, do2, do3, do4, do5, do6, do7, do8 : out std_logic := 'X';
do9, do10, do11, do12, do13, do14, do15, do16, do17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: SP8KA
generic map (CSDECODE=>"000", GSR=>"DISABLED",
WRITEMODE=>"WRITETHROUGH", RESETMODE=>"ASYNC",
REGMODE=>"NOREG", DATA_WIDTH=> 4)
port map (CE=>En, CLK=>Clk, WE=>WE, CS0=>gnd,
CS1=>gnd, CS2=>gnd, RST=>gnd, DI0=>Data(0),
DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), DI4=>gnd,
DI5=>gnd, DI6=>gnd, DI7=>gnd, DI8=>gnd,
DI9=>gnd, DI10=>gnd, DI11=>gnd,
DI12=>gnd, DI13=>gnd, DI14=>gnd,
DI15=>gnd, DI16=>gnd, DI17=>gnd,
AD0=>gnd, AD1=>gnd, AD2=>Address(0),
AD3=>Address(1), AD4=>Address(2), AD5=>Address(3),
AD6=>Address(4), AD7=>Address(5), AD8=>Address(6),
AD9=>Address(7), AD10=>Address(8), AD11=>Address(9),
AD12=>Address(10), DO0=>Q(0), DO1=>Q(1), DO2=>Q(2), DO3=>Q(3),
DO4=>open, DO5=>open, DO6=>open, DO7=>open, DO8=>open,
DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
DO14=>open, DO15=>open, DO16=>open, DO17=>open);
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.sp8ka;
-- pragma translate_on
entity EC_RAMB8_S9 is
port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (9 downto 0);
data : in std_logic_vector (8 downto 0);
q : out std_logic_vector (8 downto 0));
end;
architecture behav of EC_RAMB8_S9 is
COMPONENT sp8ka
GENERIC(
DATA_WIDTH : in Integer := 18;
REGMODE : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE : String := "000";
WRITEMODE : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
di0, di1, di2, di3, di4, di5, di6, di7, di8 : in std_logic := 'X';
di9, di10, di11, di12, di13, di14, di15, di16, di17 : in std_logic := 'X';
ad0, ad1, ad2, ad3, ad4, ad5, ad6, ad7, ad8 : in std_logic := 'X';
ad9, ad10, ad11, ad12 : in std_logic := 'X';
ce, clk, we, cs0, cs1, cs2, rst : in std_logic := 'X';
do0, do1, do2, do3, do4, do5, do6, do7, do8 : out std_logic := 'X';
do9, do10, do11, do12, do13, do14, do15, do16, do17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: SP8KA
generic map (CSDECODE=>"000", GSR=>"DISABLED",
WRITEMODE=>"WRITETHROUGH", RESETMODE=>"ASYNC",
REGMODE=>"NOREG", DATA_WIDTH=> 9)
port map (CE=>En, CLK=>Clk, WE=>WE, CS0=>gnd,
CS1=>gnd, CS2=>gnd, RST=>gnd, DI0=>Data(0),
DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), DI4=>Data(4),
DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), DI8=>Data(8),
DI9=>gnd, DI10=>gnd, DI11=>gnd,
DI12=>gnd, DI13=>gnd, DI14=>gnd,
DI15=>gnd, DI16=>gnd, DI17=>gnd,
AD0=>gnd, AD1=>gnd, AD2=>gnd,
AD3=>Address(0), AD4=>Address(1), AD5=>Address(2),
AD6=>Address(3), AD7=>Address(4), AD8=>Address(5),
AD9=>Address(6), AD10=>Address(7), AD11=>Address(8),
AD12=>Address(9), DO0=>Q(0), DO1=>Q(1), DO2=>Q(2), DO3=>Q(3),
DO4=>Q(4), DO5=>Q(5), DO6=>Q(6), DO7=>Q(7), DO8=>Q(8),
DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
DO14=>open, DO15=>open, DO16=>open, DO17=>open);
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.sp8ka;
-- pragma translate_on
entity EC_RAMB8_S18 is
port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (8 downto 0);
data : in std_logic_vector (17 downto 0);
q : out std_logic_vector (17 downto 0));
end;
architecture behav of EC_RAMB8_S18 is
COMPONENT sp8ka
GENERIC(
DATA_WIDTH : in Integer := 18;
REGMODE : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE : String := "000";
WRITEMODE : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
di0, di1, di2, di3, di4, di5, di6, di7, di8 : in std_logic := 'X';
di9, di10, di11, di12, di13, di14, di15, di16, di17 : in std_logic := 'X';
ad0, ad1, ad2, ad3, ad4, ad5, ad6, ad7, ad8 : in std_logic := 'X';
ad9, ad10, ad11, ad12 : in std_logic := 'X';
ce, clk, we, cs0, cs1, cs2, rst : in std_logic := 'X';
do0, do1, do2, do3, do4, do5, do6, do7, do8 : out std_logic := 'X';
do9, do10, do11, do12, do13, do14, do15, do16, do17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: SP8KA
generic map (CSDECODE=>"000", GSR=>"DISABLED",
WRITEMODE=>"WRITETHROUGH", RESETMODE=>"ASYNC",
REGMODE=>"NOREG", DATA_WIDTH=> 18)
port map (CE=>En, CLK=>Clk, WE=>WE, CS0=>gnd,
CS1=>gnd, CS2=>gnd, RST=>gnd, DI0=>Data(0),
DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), DI4=>Data(4),
DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), DI8=>Data(8),
DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
AD0=>gnd, AD1=>gnd, AD2=>gnd,
AD3=>gnd, AD4=>Address(0), AD5=>Address(1),
AD6=>Address(2), AD7=>Address(3), AD8=>Address(4),
AD9=>Address(5), AD10=>Address(6), AD11=>Address(7),
AD12=>Address(8), DO0=>Q(0), DO1=>Q(1), DO2=>Q(2), DO3=>Q(3),
DO4=>Q(4), DO5=>Q(5), DO6=>Q(6), DO7=>Q(7), DO8=>Q(8),
DO9=>Q(9), DO10=>Q(10), DO11=>Q(11), DO12=>Q(12), DO13=>Q(13),
DO14=>Q(14), DO15=>Q(15), DO16=>Q(16), DO17=>Q(17));
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.dp8ka;
-- pragma translate_on
entity EC_RAMB8_S36 is
port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (7 downto 0);
data : in std_logic_vector (35 downto 0);
q : out std_logic_vector (35 downto 0));
end;
architecture behav of EC_RAMB8_S36 is
COMPONENT dp8ka
GENERIC(
DATA_WIDTH_A : in Integer := 18;
DATA_WIDTH_B : in Integer := 18;
REGMODE_A : String := "NOREG";
REGMODE_B : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE_A : String := "000";
CSDECODE_B : String := "000";
WRITEMODE_A : String := "NORMAL";
WRITEMODE_B : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic := 'X';
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic := 'X';
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic := 'X';
ada9, ada10, ada11, ada12 : in std_logic := 'X';
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic := 'X';
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic := 'X';
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic := 'X';
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic := 'X';
adb9, adb10, adb11, adb12 : in std_logic := 'X';
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic := 'X';
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic := 'X';
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic := 'X';
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic := 'X';
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: DP8KA
generic map (CSDECODE_B=>"000", CSDECODE_A=>"000",
WRITEMODE_B=>"NORMAL", WRITEMODE_A=>"NORMAL", GSR=>"DISABLED",
RESETMODE=>"ASYNC", REGMODE_B=>"NOREG", REGMODE_A=>"NOREG",
DATA_WIDTH_B=> 18, DATA_WIDTH_A=> 18)
port map (CEA => en, CLKA => clk, WEA => we, CSA0 => gnd,
CSA1=>gnd, CSA2=>gnd, RSTA=> gnd, CEB=> en,
CLKB=> clk, WEB=> we, CSB0=>gnd, CSB1=>gnd,
CSB2=>gnd, RSTB=>gnd, DIA0=>Data(0), DIA1=>Data(1),
DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5),
DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9),
DIA10=>Data(10), DIA11=>Data(11), DIA12=>Data(12),
DIA13=>Data(13), DIA14=>Data(14), DIA15=>Data(15),
DIA16=>Data(16), DIA17=>Data(17), ADA0=>vcc,
ADA1=>vcc, ADA2=>vcc, ADA3=>vcc,
ADA4=>Address(0), ADA5=>Address(1), ADA6=>Address(2),
ADA7=>Address(3), ADA8=>Address(4), ADA9=>Address(5),
ADA10=>Address(6), ADA11=>Address(7), ADA12=>gnd,
DIB0=>Data(18), DIB1=>Data(19), DIB2=>Data(20),
DIB3=>Data(21), DIB4=>Data(22), DIB5=>Data(23),
DIB6=>Data(24), DIB7=>Data(25), DIB8=>Data(26),
DIB9=>Data(27), DIB10=>Data(28), DIB11=>Data(29),
DIB12=>Data(30), DIB13=>Data(31), DIB14=>Data(32),
DIB15=>Data(33), DIB16=>Data(34), DIB17=>Data(35),
ADB0=>vcc, ADB1=>vcc, ADB2=>gnd,
ADB3=>gnd, ADB4=>Address(0), ADB5=>Address(1),
ADB6=>Address(2), ADB7=>Address(3), ADB8=>Address(4),
ADB9=>Address(5), ADB10=>Address(6), ADB11=>Address(7),
ADB12=>vcc, DOA0=>Q(0), DOA1=>Q(1), DOA2=>Q(2),
DOA3=>Q(3), DOA4=>Q(4), DOA5=>Q(5), DOA6=>Q(6), DOA7=>Q(7),
DOA8=>Q(8), DOA9=>Q(9), DOA10=>Q(10), DOA11=>Q(11),
DOA12=>Q(12), DOA13=>Q(13), DOA14=>Q(14), DOA15=>Q(15),
DOA16=>Q(16), DOA17=>Q(17), DOB0=>Q(18), DOB1=>Q(19),
DOB2=>Q(20), DOB3=>Q(21), DOB4=>Q(22), DOB5=>Q(23),
DOB6=>Q(24), DOB7=>Q(25), DOB8=>Q(26), DOB9=>Q(27),
DOB10=>Q(28), DOB11=>Q(29), DOB12=>Q(30), DOB13=>Q(31),
DOB14=>Q(32), DOB15=>Q(33), DOB16=>Q(34), DOB17=>Q(35));
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
entity ec_syncram is
generic (abits : integer := 9; dbits : integer := 32);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (dbits -1 downto 0);
dataout : out std_logic_vector (dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end;
architecture behav of ec_syncram is
component EC_RAMB8_S1 port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (12 downto 0);
data : in std_logic_vector (0 downto 0);
q : out std_logic_vector (0 downto 0));
end component;
component EC_RAMB8_S2 port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (11 downto 0);
data : in std_logic_vector (1 downto 0);
q : out std_logic_vector (1 downto 0));
end component;
component EC_RAMB8_S4 port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (10 downto 0);
data : in std_logic_vector (3 downto 0);
q : out std_logic_vector (3 downto 0));
end component;
component EC_RAMB8_S9 port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (9 downto 0);
data : in std_logic_vector (8 downto 0);
q : out std_logic_vector (8 downto 0));
end component;
component EC_RAMB8_S18 port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (8 downto 0);
data : in std_logic_vector (17 downto 0);
q : out std_logic_vector (17 downto 0));
end component;
component EC_RAMB8_S36 port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (7 downto 0);
data : in std_logic_vector (35 downto 0);
q : out std_logic_vector (35 downto 0));
end component;
constant DMAX : integer := dbits+36;
constant AMAX : integer := 13;
signal gnd : std_ulogic;
signal do, di : std_logic_vector(DMAX downto 0);
signal xa, ya : std_logic_vector(AMAX downto 0);
begin
gnd <= '0'; dataout <= do(dbits-1 downto 0); di(dbits-1 downto 0) <= datain;
di(DMAX downto dbits) <= (others => '0'); xa(abits-1 downto 0) <= address;
xa(AMAX downto abits) <= (others => '0'); ya(abits-1 downto 0) <= address;
ya(AMAX downto abits) <= (others => '1');
a8 : if (abits <= 8) generate
x : for i in 0 to ((dbits-1)/36) generate
r : EC_RAMB8_S36 port map ( clk, enable, write, xa(7 downto 0),
di((i+1)*36-1 downto i*36), do((i+1)*36-1 downto i*36));
end generate;
end generate;
a9 : if (abits = 9) generate
x : for i in 0 to ((dbits-1)/18) generate
r : EC_RAMB8_S18 port map ( clk, enable, write, xa(8 downto 0),
di((i+1)*18-1 downto i*18), do((i+1)*18-1 downto i*18));
end generate;
end generate;
a10 : if (abits = 10) generate
x : for i in 0 to ((dbits-1)/9) generate
r : EC_RAMB8_S9 port map ( clk, enable, write, xa(9 downto 0),
di((i+1)*9-1 downto i*9), do((i+1)*9-1 downto i*9));
end generate;
end generate;
a11 : if (abits = 11) generate
x : for i in 0 to ((dbits-1)/4) generate
r : EC_RAMB8_S4 port map ( clk, enable, write, xa(10 downto 0),
di((i+1)*4-1 downto i*4), do((i+1)*4-1 downto i*4));
end generate;
end generate;
a12 : if (abits = 12) generate
x : for i in 0 to ((dbits-1)/2) generate
r : EC_RAMB8_S2 port map ( clk, enable, write, xa(11 downto 0),
di((i+1)*2-1 downto i*2), do((i+1)*2-1 downto i*2));
end generate;
end generate;
a13 : if (abits = 13) generate
x : for i in 0 to ((dbits-1)/1) generate
r : EC_RAMB8_S1 port map ( clk, enable, write, xa(12 downto 0),
di((i+1)*1-1 downto i*1), do((i+1)*1-1 downto i*1));
end generate;
end generate;
-- pragma translate_off
unsup : if (abits > 13) generate
x : process
begin
assert false
report "Lattice EC syncram mapper: unsupported memory configuration!"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
entity ec_syncram_dp is
generic (
abits : integer := 4; dbits : integer := 32
);
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic);
end;
architecture behav of ec_syncram_dp is
component EC_RAMB8_S1_S1 is port (
DataInA, DataInB: in std_logic_vector(0 downto 0);
AddressA, AddressB: in std_logic_vector(12 downto 0);
ClockA, ClockB: in std_logic;
ClockEnA, ClockEnB: in std_logic;
WrA, WrB: in std_logic;
QA, QB: out std_logic_vector(0 downto 0));
end component;
component EC_RAMB8_S2_S2 is port (
DataInA, DataInB: in std_logic_vector(1 downto 0);
AddressA, AddressB: in std_logic_vector(11 downto 0);
ClockA, ClockB: in std_logic;
ClockEnA, ClockEnB: in std_logic;
WrA, WrB: in std_logic;
QA, QB: out std_logic_vector(1 downto 0));
end component;
component EC_RAMB8_S4_S4 is port (
DataInA, DataInB: in std_logic_vector(3 downto 0);
AddressA, AddressB: in std_logic_vector(10 downto 0);
ClockA, ClockB: in std_logic;
ClockEnA, ClockEnB: in std_logic;
WrA, WrB: in std_logic;
QA, QB: out std_logic_vector(3 downto 0));
end component;
component EC_RAMB8_S9_S9 is port (
DataInA, DataInB: in std_logic_vector(8 downto 0);
AddressA, AddressB: in std_logic_vector(9 downto 0);
ClockA, ClockB: in std_logic;
ClockEnA, ClockEnB: in std_logic;
WrA, WrB: in std_logic;
QA, QB: out std_logic_vector(8 downto 0));
end component;
component EC_RAMB8_S18_S18 is port (
DataInA, DataInB: in std_logic_vector(17 downto 0);
AddressA, AddressB: in std_logic_vector(8 downto 0);
ClockA, ClockB: in std_logic;
ClockEnA, ClockEnB: in std_logic;
WrA, WrB: in std_logic;
QA, QB: out std_logic_vector(17 downto 0));
end component;
constant DMAX : integer := dbits+18;
constant AMAX : integer := 13;
signal gnd, vcc : std_ulogic;
signal do1, do2, di1, di2 : std_logic_vector(DMAX downto 0);
signal addr1, addr2 : std_logic_vector(AMAX downto 0);
begin
gnd <= '0'; vcc <= '1';
dataout1 <= do1(dbits-1 downto 0); dataout2 <= do2(dbits-1 downto 0);
di1(dbits-1 downto 0) <= datain1; di1(DMAX downto dbits) <= (others => '0');
di2(dbits-1 downto 0) <= datain2; di2(DMAX downto dbits) <= (others => '0');
addr1(abits-1 downto 0) <= address1; addr1(AMAX downto abits) <= (others => '0');
addr2(abits-1 downto 0) <= address2; addr2(AMAX downto abits) <= (others => '0');
a9 : if abits <= 9 generate
x : for i in 0 to ((dbits-1)/18) generate
r0 : EC_RAMB8_S18_S18 port map (
di1((i+1)*18-1 downto i*18), di2((i+1)*18-1 downto i*18),
addr1(8 downto 0), addr2(8 downto 0), clk1, clk2,
enable1, enable2, write1, write2,
do1((i+1)*18-1 downto i*18), do2((i+1)*18-1 downto i*18));
end generate;
end generate;
a10 : if abits = 10 generate
x : for i in 0 to ((dbits-1)/9) generate
r0 : EC_RAMB8_S9_S9 port map (
di1((i+1)*9-1 downto i*9), di2((i+1)*9-1 downto i*9),
addr1(9 downto 0), addr2(9 downto 0), clk1, clk2,
enable1, enable2, write1, write2,
do1((i+1)*9-1 downto i*9), do2((i+1)*9-1 downto i*9));
end generate;
end generate;
a11 : if abits = 11 generate
x : for i in 0 to ((dbits-1)/4) generate
r0 : EC_RAMB8_S4_S4 port map (
di1((i+1)*4-1 downto i*4), di2((i+1)*4-1 downto i*4),
addr1(10 downto 0), addr2(10 downto 0), clk1, clk2,
enable1, enable2, write1, write2,
do1((i+1)*4-1 downto i*4), do2((i+1)*4-1 downto i*4));
end generate;
end generate;
a12 : if abits = 12 generate
x : for i in 0 to ((dbits-1)/2) generate
r0 : EC_RAMB8_S2_S2 port map (
di1((i+1)*2-1 downto i*2), di2((i+1)*2-1 downto i*2),
addr1(11 downto 0), addr2(11 downto 0), clk1, clk2,
enable1, enable2, write1, write2,
do1((i+1)*2-1 downto i*2), do2((i+1)*2-1 downto i*2));
end generate;
end generate;
a13 : if abits = 13 generate
x : for i in 0 to ((dbits-1)/1) generate
r0 : EC_RAMB8_S1_S1 port map (
di1((i+1)*1-1 downto i*1), di2((i+1)*1-1 downto i*1),
addr1(12 downto 0), addr2(12 downto 0), clk1, clk2,
enable1, enable2, write1, write2,
do1((i+1)*1-1 downto i*1), do2((i+1)*1-1 downto i*1));
end generate;
end generate;
-- pragma translate_off
unsup : if (abits > 13) generate
x : process
begin
assert false
report "Lattice EC syncram_dp: unsupported memory configuration!"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end;
| gpl-3.0 | 945dbfab002a0af9790d4d2ca315d09f | 0.666238 | 4.282591 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-clock-gate/testbench.vhd | 1 | 19,920 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
use gaisler.jtagtst.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 18; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
port (
pci_rst : inout std_logic; -- PCI bus
pci_clk : in std_logic;
pci_gnt : in std_logic;
pci_idsel : in std_logic;
pci_lock : inout std_logic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_logic;
pci_irdy : inout std_logic;
pci_trdy : inout std_logic;
pci_devsel : inout std_logic;
pci_stop : inout std_logic;
pci_perr : inout std_logic;
pci_par : inout std_logic;
pci_req : inout std_logic;
pci_serr : inout std_logic;
pci_host : in std_logic;
pci_66 : in std_logic
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
component leon3mp
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_logic;
clk : in std_logic;
pllref : in std_logic;
errorn : out std_logic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
sa : out std_logic_vector(14 downto 0);
sd : inout std_logic_vector(63 downto 0);
sdclk : out std_logic;
sdcke : out std_logic_vector (1 downto 0); -- sdram clock enable
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_logic; -- sdram write enable
sdrasn : out std_logic; -- sdram ras
sdcasn : out std_logic; -- sdram cas
sddqm : out std_logic_vector (7 downto 0); -- sdram dqm
dsutx : out std_logic; -- DSU tx data
dsurx : in std_logic; -- DSU rx data
dsuen : in std_logic;
dsubre : in std_logic;
dsuact : out std_logic;
txd1 : out std_logic; -- UART1 tx data
rxd1 : in std_logic; -- UART1 rx data
txd2 : out std_logic; -- UART1 tx data
rxd2 : in std_logic; -- UART1 rx data
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_logic;
writen : out std_logic;
read : out std_logic;
iosn : out std_logic;
romsn : out std_logic_vector (1 downto 0);
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_logic;
erx_clk : in std_logic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_logic;
erx_er : in std_logic;
erx_col : in std_logic;
erx_crs : in std_logic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_logic;
etx_er : out std_logic;
emdc : out std_logic;
emddis : out std_logic;
epwrdwn : out std_logic;
ereset : out std_logic;
esleep : out std_logic;
epause : out std_logic;
pci_rst : inout std_logic; -- PCI bus
pci_clk : in std_logic;
pci_gnt : in std_logic;
pci_idsel : in std_logic;
pci_lock : inout std_logic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_logic;
pci_irdy : inout std_logic;
pci_trdy : inout std_logic;
pci_devsel : inout std_logic;
pci_stop : inout std_logic;
pci_perr : inout std_logic;
pci_par : inout std_logic;
pci_req : inout std_logic;
pci_serr : inout std_logic;
pci_host : in std_logic;
pci_66 : in std_logic;
pci_arb_req : in std_logic_vector(0 to 3);
pci_arb_gnt : out std_logic_vector(0 to 3);
can_txd : out std_logic;
can_rxd : in std_logic;
can_stb : out std_logic;
spw_clk : in std_logic;
spw_rxd : in std_logic_vector(0 to 2);
spw_rxdn : in std_logic_vector(0 to 2);
spw_rxs : in std_logic_vector(0 to 2);
spw_rxsn : in std_logic_vector(0 to 2);
spw_txd : out std_logic_vector(0 to 2);
spw_txdn : out std_logic_vector(0 to 2);
spw_txs : out std_logic_vector(0 to 2);
spw_txsn : out std_logic_vector(0 to 2);
tck, tms, tdi : in std_logic;
tdo : out std_logic
);
end component;
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(27 downto 0);
signal data : std_logic_vector(31 downto 0);
signal ramsn : std_logic_vector(4 downto 0);
signal ramoen : std_logic_vector(4 downto 0);
signal rwen : std_logic_vector(3 downto 0);
signal rwenx : std_logic_vector(3 downto 0);
signal romsn : std_logic_vector(1 downto 0);
signal iosn : std_logic;
signal oen : std_logic;
signal read : std_logic;
signal writen : std_logic;
signal brdyn : std_logic;
signal bexcn : std_logic;
signal wdog : std_logic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_logic;
signal dsurst : std_logic;
signal test : std_logic;
signal error : std_logic;
signal gpio : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal GND : std_logic := '0';
signal VCC : std_logic := '1';
signal NC : std_logic := 'Z';
signal clk2 : std_logic := '1';
signal sdcke : std_logic_vector ( 1 downto 0); -- clk en
signal sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
signal sdwen : std_logic; -- write en
signal sdrasn : std_logic; -- row addr stb
signal sdcasn : std_logic; -- col addr stb
signal sddqm : std_logic_vector ( 7 downto 0); -- data i/o mask
signal sdclk : std_logic;
signal plllock : std_logic;
signal txd1, rxd1 : std_logic;
signal txd2, rxd2 : std_logic;
signal etx_clk, erx_clk, erx_dv, erx_er, erx_col, erx_crs, etx_en, etx_er : std_logic:='0';
signal erxd, etxd: std_logic_vector(3 downto 0):=(others=>'0');
signal erxdt, etxdt: std_logic_vector(7 downto 0):=(others=>'0');
signal gtx_clk : std_logic := '0';
signal emdc, emdio: std_logic;
signal emddis : std_logic;
signal epwrdwn : std_logic;
signal ereset : std_logic;
signal esleep : std_logic;
signal epause : std_logic;
constant lresp : boolean := false;
signal sa : std_logic_vector(14 downto 0);
signal sd : std_logic_vector(63 downto 0);
signal pci_arb_req, pci_arb_gnt : std_logic_vector(0 to 3);
signal can_txd : std_logic;
signal can_rxd : std_logic;
signal can_stb : std_logic;
signal spw_clk : std_logic := '0';
signal spw_rxd : std_logic_vector(0 to 2) := "000";
signal spw_rxdn : std_logic_vector(0 to 2) := "000";
signal spw_rxs : std_logic_vector(0 to 2) := "000";
signal spw_rxsn : std_logic_vector(0 to 2) := "000";
signal spw_txd : std_logic_vector(0 to 2);
signal spw_txdn : std_logic_vector(0 to 2);
signal spw_txs : std_logic_vector(0 to 2);
signal spw_txsn : std_logic_vector(0 to 2);
signal tck, tms, tdi, tdo : std_logic;
constant CFG_SDEN : integer := CFG_SDCTRL + CFG_MCTRL_SDEN ;
constant CFG_SD64 : integer := CFG_SDCTRL_SD64 + CFG_MCTRL_SD64;
begin
-- clock and reset
spw_clk <= not spw_clk after 20 ns;
spw_rxd(0) <= spw_txd(0); spw_rxdn(0) <= spw_txdn(0);
spw_rxs(0) <= spw_txs(0); spw_rxsn(0) <= spw_txsn(0);
spw_rxd(1) <= spw_txd(1); spw_rxdn(1) <= spw_txdn(1);
spw_rxs(1) <= spw_txs(1); spw_rxsn(1) <= spw_txsn(1);
spw_rxd(2) <= spw_txd(0); spw_rxdn(2) <= spw_txdn(2);
spw_rxs(2) <= spw_txs(0); spw_rxsn(2) <= spw_txsn(2);
clk <= not clk after ct * 1 ns;
rst <= dsurst;
dsuen <= '1'; dsubre <= '0'; rxd1 <= '1';
--## can_rxd <= '1';
can_rxd <= can_txd; -- CAN LOOP BACK ##
d3 : leon3mp
generic map ( fabtech, memtech, padtech, clktech,
disas, dbguart, pclow )
port map (rst, clk, sdclk, error, address(27 downto 0), data,
sa, sd, sdclk, sdcke, sdcsn, sdwen, sdrasn, sdcasn, sddqm,
dsutx, dsurx, dsuen, dsubre, dsuact, txd1, rxd1, txd2, rxd2,
ramsn, ramoen, rwen, oen, writen, read, iosn, romsn, gpio,
emdio, etx_clk, erx_clk, erxd, erx_dv, erx_er, erx_col, erx_crs,
etxd, etx_en, etx_er, emdc, emddis, epwrdwn, ereset, esleep, epause,
pci_rst, pci_clk, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr, pci_par,
pci_req, pci_serr, pci_host, pci_66, pci_arb_req, pci_arb_gnt,
can_txd, can_rxd, can_stb, spw_clk, spw_rxd, spw_rxdn, spw_rxs,
spw_rxsn, spw_txd, spw_txdn, spw_txs, spw_txsn, tck, tms, tdi, tdo);
-- optional sdram
sd0 : if (CFG_SDEN /= 0) and (CFG_MCTRL_SEPBUS = 0) generate
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => data(31 downto 16), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => data(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
u2: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => data(31 downto 16), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u3: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => data(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
end generate;
sd1 : if (CFG_SDEN /= 0) and (CFG_MCTRL_SEPBUS = 1) generate
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
u2: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u3: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
sd64 : if (CFG_SD64 /= 0) generate
u4: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(63 downto 48), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(7 downto 6));
u5: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(47 downto 32), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(5 downto 4));
u6: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(63 downto 48), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(7 downto 6));
u7: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(47 downto 32), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(5 downto 4));
end generate;
end generate;
prom0 : for i in 0 to (romwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => romdepth, fname => promfile)
port map (address(romdepth+1 downto 2), data(31-i*8 downto 24-i*8), romsn(0),
rwen(i), oen);
end generate;
sbanks : for k in 0 to srambanks-1 generate
sram0 : for i in 0 to (sramwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
port map (address(sramdepth+1 downto 2), data(31-i*8 downto 24-i*8),
ramsn(k), rwen(i), ramoen(k));
end generate;
end generate;
emdio <= 'H';
erxd <= erxdt(3 downto 0);
etxdt <= "0000" & etxd;
p0: phy
generic map(base1000_t_fd => 0, base1000_t_hd => 0)
port map(rst, emdio, etx_clk, erx_clk, erxdt, erx_dv,
erx_er, erx_col, erx_crs, etxdt, etx_en, etx_er, emdc, gtx_clk);
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= buskeep(data), (others => 'H') after 250 ns;
sd <= buskeep(sd), (others => 'H') after 250 ns;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, oen, writen, brdyn);
dsucom : process
procedure dsucfg(signal dsurx : in std_logic; signal dsutx : out std_logic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
-- wait;
wait for 355000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#0F#, 16#DD#, 16#94#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
wait;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
jtagproc : process
begin
wait;
jtagcom(tdo, tck, tms, tdi, 100, 20, 16#40000000#, true);
wait;
end process;
end;
| gpl-3.0 | e6407a7abe39bc0dbdcfc2b9b8242f70 | 0.573042 | 3.020012 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-xilinx-kc705/config.vhd | 1 | 7,199 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := kintex7;
constant CFG_MEMTECH : integer := kintex7;
constant CFG_PADTECH : integer := kintex7;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := kintex7;
constant CFG_CLKMUL : integer := (4);
constant CFG_CLKDIV : integer := (8);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON processor core
constant CFG_LEON : integer := 3;
constant CFG_NCPU : integer := (4);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NWP : integer := (4);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 4;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 4;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_BWMASK : integer := 16#0#;
constant CFG_CACHEBW : integer := 128;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 16;
constant CFG_DTLBNUM : integer := 16;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 4 + 64*0;
constant CFG_ATBSZ : integer := 4;
constant CFG_AHBPF : integer := 2;
constant CFG_AHBWP : integer := 2;
constant CFG_LEONFT_EN : integer := 0 + 0*8;
constant CFG_LEON_NETLIST : integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 1;
constant CFG_NP_ASI : integer := 1;
constant CFG_WRPSR : integer := 1;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- L2 Cache
constant CFG_L2_EN : integer := 0;
constant CFG_L2_SIZE : integer := 64;
constant CFG_L2_WAYS : integer := 1;
constant CFG_L2_HPROT : integer := 0;
constant CFG_L2_PEN : integer := 0;
constant CFG_L2_WT : integer := 0;
constant CFG_L2_RAN : integer := 0;
constant CFG_L2_SHARE : integer := 0;
constant CFG_L2_LSZ : integer := 32;
constant CFG_L2_MAP : integer := 16#00F0#;
constant CFG_L2_MTRR : integer := (0);
constant CFG_L2_EDAC : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 1;
constant CFG_FPNPEN : integer := 1;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#00AA#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000000#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- Xilinx MIG 7-Series
constant CFG_MIG_7SERIES : integer := 1;
constant CFG_MIG_7SERIES_MODEL : integer := 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 0;
constant CFG_AHBSTATN : integer := (1);
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 1;
constant CFG_AHBRSZ : integer := 4;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 1;
constant CFG_ETH_FIFO : integer := 8;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 1;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- I2C master
constant CFG_I2C_ENABLE : integer := 1;
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 0;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 0;
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 0;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#0B#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 0;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := (1);
constant CFG_SPIMCTRL_ASCALER : integer := (8);
constant CFG_SPIMCTRL_PWRUPCNT : integer := (0);
constant CFG_SPIMCTRL_OFFSET : integer := 16#0#;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-3.0 | fa2a128cb03a87dfc3582f19dc499e57 | 0.646756 | 3.563861 | false | false | false | false |
kdgwill/VHDL_Framer_Example | VHDL_Framer_Example/Example2/Average.vhd | 1 | 4,282 | LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_unsigned.all ;
USE ieee.numeric_std.ALL;
entity Average is
generic (
bits: integer
);
port (clk : in std_logic;
resetb : in std_logic;
data_sig_in : in std_ulogic;
clk_div_8 : in std_ulogic;
decode_F628_out : in std_ulogic;
ram_wren : OUT STD_LOGIC ;
ram_address : out STD_LOGIC_VECTOR (4 DOWNTO 0);
ram_data : out STD_LOGIC_VECTOR (bits-1 DOWNTO 0);
ram_q : in STD_LOGIC_VECTOR (bits-1 DOWNTO 0);
add_value0x : Out STD_LOGIC_VECTOR (bits-1 DOWNTO 0);
add_value1x : Out STD_LOGIC_VECTOR (bits-1 DOWNTO 0);
add_sum : In STD_LOGIC_VECTOR (bits-1 DOWNTO 0);
div_denom : Out STD_LOGIC_VECTOR (bits-1 DOWNTO 0);
div_numer : Out STD_LOGIC_VECTOR (bits-1 DOWNTO 0)
);
end Average;
ARCHITECTURE Average of Average IS
---Default Variables----
Signal shiftreg : STD_LOGIC_VECTOR (7 DOWNTO 0);
Signal shiftreg8 : STD_LOGIC_VECTOR (7 DOWNTO 0);
Signal byte_count:integer:=0;
Signal enabled : STD_LOGIC := '0';
begin
------Shiftreg----
Process (clk, resetb)
begin
if (resetb = '0')then
shiftreg <= (others => '0');
elsif rising_edge (clk) then
shiftreg <= shiftreg (6 downto 0) & data_sig_in;
end if;
end process;
-------Receiving values
Process(clk_div_8,resetb)
Begin
if(resetb = '0') then
shiftreg8 <= (others => '0');
elsif falling_edge (clk_div_8) then
shiftreg8 <=shiftreg;
end if;
End Process;
--bit counter
process (clk_div_8, resetb)
begin
if (resetb = '0') then
byte_count <= 0;
elsif falling_edge (clk_div_8) then
if (decode_F628_out = '1') then
byte_count <= -1;
enabled <= '1';
else
byte_count <= byte_count + 1;
end if;
end if;
end process;
--------------------------------
-----------RAM------------------
--------------------------------
Process(clk_div_8,resetb)
Begin
if(resetb = '0') then
ram_wren <= '0';
elsif falling_edge (clk_div_8) then
ram_wren <= '1';
elsif rising_edge(clk_div_8) then
ram_wren <= '0';
end if;
End Process;
Process(clk_div_8,resetb)
variable saddr : integer := 10-1;
variable daddr : integer := 0 - 1;
begin
if (resetb = '0') then
saddr := 0;
daddr := 0;
ram_address <= (others => '0' );
ram_data <= (others => '0' );
elsif falling_edge (clk_div_8) then
if (decode_F628_out = '1') then
saddr := 10 - 1;
daddr := 0 - 1;
else
case byte_count is
when 180 to 182 |
450 to 452 |
540 to 542 |
630 to 632 => saddr := saddr + 1;
ram_address<= std_logic_vector(to_unsigned (saddr,5));
ram_data <= STD_LOGIC_VECTOR(RESIZE(UNSIGNED(shiftreg8), bits));
daddr := 0 - 1; --reset payload packet counter
when 3 to 89 |
93 to 179 |
183 to 269 |
273 to 359 |
363 to 449 |
453 to 539 |
543 to 629 |
633 to 719 |
723 to 809=> daddr := (daddr + 1) mod 10;
ram_address<= std_logic_vector(to_unsigned (daddr,5));
ram_data <= STD_LOGIC_VECTOR(RESIZE(UNSIGNED(shiftreg8), bits));
when others => null;
end case;
end if;
end if;
end process;
--------------------------------
--------------ADDER AND DIVIDER-------------
Process(clk_div_8,resetb)
variable saddr : integer := 0;
Begin
if(resetb = '0') then
saddr := 0-1;
elsif falling_edge(clk_div_8) then
if (decode_F628_out = '1') then
saddr := 0-1;
end if;
elsif rising_edge(clk_div_8) then
saddr := (saddr + 1) mod 10;
add_value1x <= ram_q;
--ram_address <= std_logic_vector(to_unsigned (saddr,5));
if(saddr = 10 - 1) then
div_numer <= add_sum;
add_value0x <= (others => '0');
else
add_value0x <= add_sum;
end if;
end if;
div_denom <= X"0000000A";--always 10
End Process;
END Average;
| gpl-3.0 | 04f3756ed6723c80766b673110fa18a2 | 0.512377 | 3.501226 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-digilent-nexys4/leon3mp.vhd | 1 | 26,811 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2013 Aeroflex Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.net.all;
use gaisler.jtag.all;
--pragma translate_off
use gaisler.sim.all;
library unisim;
use unisim.BUFG;
use unisim.PLLE2_ADV;
use unisim.STARTUPE2;
--pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
clk : in std_ulogic;
-- onBoard Cellular RAM, Numonyx StrataFlash and Numonyx Quad Flash
RamOE : out std_ulogic;
RamWE : out std_ulogic;
RamAdv : out std_ulogic;
RamCE : out std_ulogic;
RamClk : out std_ulogic;
RamCRE : out std_ulogic;
RamLB : out std_ulogic;
RamUB : out std_ulogic;
--RamWait : in std_ulogic;
QspiCSn : out std_ulogic;
QspiDB : inout std_logic_vector(3 downto 0);
address : out std_logic_vector(22 downto 0);
data : inout std_logic_vector(15 downto 0);
-- 7 segment display
--seg : out std_logic_vector(6 downto 0);
--an : out std_logic_vector(7 downto 0);
-- LEDs
Led : out std_logic_vector(15 downto 0);
-- Switches
sw : in std_logic_vector(15 downto 0);
-- Buttons
btnCpuResetn : in std_ulogic;
btn : in std_logic_vector(4 downto 0);
-- VGA Connector
--vgaRed : out std_logic_vector(2 downto 0);
--vgaGreen : out std_logic_vector(2 downto 0);
--vgaBlue : out std_logic_vector(2 downto 1);
--Hsync : out std_ulogic;
--Vsync : out std_ulogic;
-- 12 pin connectors
--ja : inout std_logic_vector(7 downto 0);
--jb : inout std_logic_vector(7 downto 0);
--jc : inout std_logic_vector(7 downto 0);
--jd : inout std_logic_vector(7 downto 0);
-- SMSC ethernet PHY
PhyRstn : out std_ulogic;
PhyCrs : in std_ulogic;
PhyClk50Mhz : out std_ulogic;
PhyTxd : out std_logic_vector(1 downto 0);
PhyTxEn : out std_ulogic;
PhyRxd : in std_logic_vector(1 downto 0);
PhyRxEr : in std_ulogic;
PhyMdc : out std_ulogic;
PhyMdio : inout std_logic;
-- Pic USB-HID interface
--~ PS2KeyboardData : inout std_logic;
--~ PS2KeyboardClk : inout std_logic;
--~ PS2MouseData : inout std_logic;
--~ PS2MouseClk : inout std_logic;
--~ PicGpio : out std_logic_vector(1 downto 0);
-- USB-RS232 interface
RsRx : in std_logic;
RsTx : out std_logic
);
end;
architecture rtl of leon3mp is
component PLLE2_ADV
generic (
BANDWIDTH : string := "OPTIMIZED";
CLKFBOUT_MULT : integer := 5;
CLKFBOUT_PHASE : real := 0.0;
CLKIN1_PERIOD : real := 0.0;
CLKIN2_PERIOD : real := 0.0;
CLKOUT0_DIVIDE : integer := 1;
CLKOUT0_DUTY_CYCLE : real := 0.5;
CLKOUT0_PHASE : real := 0.0;
CLKOUT1_DIVIDE : integer := 1;
CLKOUT1_DUTY_CYCLE : real := 0.5;
CLKOUT1_PHASE : real := 0.0;
CLKOUT2_DIVIDE : integer := 1;
CLKOUT2_DUTY_CYCLE : real := 0.5;
CLKOUT2_PHASE : real := 0.0;
CLKOUT3_DIVIDE : integer := 1;
CLKOUT3_DUTY_CYCLE : real := 0.5;
CLKOUT3_PHASE : real := 0.0;
CLKOUT4_DIVIDE : integer := 1;
CLKOUT4_DUTY_CYCLE : real := 0.5;
CLKOUT4_PHASE : real := 0.0;
CLKOUT5_DIVIDE : integer := 1;
CLKOUT5_DUTY_CYCLE : real := 0.5;
CLKOUT5_PHASE : real := 0.0;
COMPENSATION : string := "ZHOLD";
DIVCLK_DIVIDE : integer := 1;
REF_JITTER1 : real := 0.0;
REF_JITTER2 : real := 0.0;
STARTUP_WAIT : string := "FALSE"
);
port (
CLKFBOUT : out std_ulogic := '0';
CLKOUT0 : out std_ulogic := '0';
CLKOUT1 : out std_ulogic := '0';
CLKOUT2 : out std_ulogic := '0';
CLKOUT3 : out std_ulogic := '0';
CLKOUT4 : out std_ulogic := '0';
CLKOUT5 : out std_ulogic := '0';
DO : out std_logic_vector (15 downto 0);
DRDY : out std_ulogic := '0';
LOCKED : out std_ulogic := '0';
CLKFBIN : in std_ulogic;
CLKIN1 : in std_ulogic;
CLKIN2 : in std_ulogic;
CLKINSEL : in std_ulogic;
DADDR : in std_logic_vector(6 downto 0);
DCLK : in std_ulogic;
DEN : in std_ulogic;
DI : in std_logic_vector(15 downto 0);
DWE : in std_ulogic;
PWRDWN : in std_ulogic;
RST : in std_ulogic
);
end component;
component STARTUPE2
generic (
PROG_USR : string := "FALSE";
SIM_CCLK_FREQ : real := 0.0
);
port (
CFGCLK : out std_ulogic;
CFGMCLK : out std_ulogic;
EOS : out std_ulogic;
PREQ : out std_ulogic;
CLK : in std_ulogic;
GSR : in std_ulogic;
GTS : in std_ulogic;
KEYCLEARB : in std_ulogic;
PACK : in std_ulogic;
USRCCLKO : in std_ulogic;
USRCCLKTS : in std_ulogic;
USRDONEO : in std_ulogic;
USRDONETS : in std_ulogic
);
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
signal CLKFBOUT : std_logic;
signal CLKFBIN : std_logic;
signal eth_pll_rst : std_logic;
signal eth_clk_nobuf : std_logic;
signal eth_clk90_nobuf : std_logic;
signal eth_clk : std_logic;
signal eth_clk90 : std_logic;
signal vcc : std_logic;
signal gnd : std_logic;
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ndsuact : std_ulogic;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal gpti : gptimer_in_type;
signal spii : spi_in_type;
signal spio : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal spmi : spimctrl_in_type;
signal spmo : spimctrl_out_type;
signal clkm, rstn, clkml : std_ulogic;
signal tck, tms, tdi, tdo : std_ulogic;
signal rstraw : std_logic;
signal btnCpuReset : std_logic;
signal lock : std_logic;
-- RS232 APB Uart
signal rxd1 : std_logic;
signal txd1 : std_logic;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of lock : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_keep of clkm : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute keep of lock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
constant BOARD_FREQ : integer := 100000; -- CLK input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1';
gnd <= '0';
led(15 downto 4) <= (others =>'0'); -- unused leds off
btnCpuReset<= not btnCpuResetn;
cgi.pllctrl <= "00";
cgi.pllrst <= rstraw;
rst0 : rstgen generic map (acthigh => 1)
port map (btnCpuReset, clkm, lock, rstn, rstraw);
lock <= cgo.clklock;
-- clock generator
clkgen0 : clkgen
generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (clk, gnd, clkm, open, open, open, open, cgi, cgo, open, open, open);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH,
nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
-- LEON3 processor
leon3gen : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR,
CFG_NCPU-1, CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
led(3) <= not dbgo(0).error;
led(2) <= not dsuo.active;
-- LEON3 Debug Support Unit
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#, ahbpf => CFG_AHBPF,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
--dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsui.enable <= '1';
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
-- Debug UART
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (RsRx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (RsTx, duo.txd);
led(0) <= not dui.rxd;
led(1) <= not duo.txd;
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd);
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 5, pindex => 0, paddr => 0, rommask => 0,
iomask => 0, ram8 => CFG_MCTRL_RAM8BIT, ram16 => CFG_MCTRL_RAM16BIT,srbanks=>1)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(5), apbi, apbo(0), wpo, open);
end generate;
memi.brdyn <= '1';
memi.bexcn <= '1';
memi.writen <= '1';
memi.wrn <= "1111";
memi.bwidth <= "01";
mg0 : if (CFG_MCTRL_LEON2 = 0) generate
apbo(0) <= apb_none;
ahbso(5) <= ahbs_none;
memo.bdrive(0) <= '1';
end generate;
mgpads : if (CFG_MCTRL_LEON2 /= 0) generate
addr_pad : outpadv generic map (tech => padtech, width => 23)
port map (address, memo.address(23 downto 1));
oen_pad : outpad generic map (tech => padtech)
port map (RamOE, memo.oen);
cs_pad : outpad generic map (tech => padtech)
port map (RamCE, memo.ramsn(0));
lb_pad : outpad generic map (tech => padtech)
port map (RamLB, memo.mben(0));
ub_pad : outpad generic map (tech => padtech)
port map (RamUB, memo.mben(1));
wri_pad : outpad generic map (tech => padtech)
port map (RamWE, memo.writen);
end generate;
bdr : iopadv generic map (tech => padtech, width => 8)
port map (data(7 downto 0), memo.data(23 downto 16),
memo.bdrive(1), memi.data(23 downto 16));
bdr2 : iopadv generic map (tech => padtech, width => 8)
port map (data(15 downto 8), memo.data(31 downto 24),
memo.bdrive(0), memi.data(31 downto 24));
RamCRE <= '0';
RamClk <= '0';
RamAdv <= '0';
----------------------------------------------------------------------
--- SPI Memory controller -------------------------------------------
----------------------------------------------------------------------
-- OPTIONALY set the offset generic (only affect reads).
-- The first 4MB are used for loading the FPGA.
-- For dual ouptut: readcmd => 16#3B#, dualoutput => 1
spimctrl1 : spimctrl
generic map (hindex => 7, hirq => 7, faddr => 16#b00#, fmask => 16#ff0#,
ioaddr => 16#700#, iomask => 16#fff#, spliten => CFG_SPLIT,
sdcard => 0, readcmd => 16#0B#, dummybyte => 1, dualoutput => 0,
scaler => 1, altscaler => 2)
port map (rstn, clkm, ahbsi, ahbso(7), spmi, spmo);
--QspiDB(3) <= '1'; QspiDB(2) <= '1';
spi_QspiDB_2_pad : outpad generic map (tech => padtech)
port map (QspiDB(2), '1');
spi_QspiDB_3_pad : outpad generic map (tech => padtech)
port map (QspiDB(3), '1');
-- spi_bdr : iopad generic map (tech => padtech)
-- port map (QspiDB(0), spmo.mosi, spmo.mosioen, spmi.mosi);
spi_mosi_pad : outpad generic map (tech => padtech)
port map (QspiDB(0), spmo.mosi);
spi_miso_pad : inpad generic map (tech => padtech)
port map (QspiDB(1), spmi.miso);
spi_slvsel0_pad : outpad generic map (tech => padtech)
port map (QspiCSn, spmo.csn);
-- MACRO for assigning the SPI output clock
spicclk: STARTUPE2
port map (--CFGCLK => open, CFGMCLK => open, EOS => open, PREQ => open,
CLK => '0', GSR => '0', GTS => '0', KEYCLEARB => '0', PACK => '0',
USRCCLKO => spmo.sck, USRCCLKTS => '0', USRDONEO => '1', USRDONETS => '0' );
----------------------------------------------------------------------
--- DDR2 memory controller ------------------------------------------
----------------------------------------------------------------------
noddr : if (CFG_DDR2SP+CFG_MIG_DDR2) = 0 generate lock <= '1'; end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
-- APB Bridge
apb0 : apbctrl
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
-- Interrupt controller
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
-- Time Unit
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW,
ntimers => CFG_GPT_NTIM, nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti <= gpti_dhalt_drive(dsuo.tstop);
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1;
u1i.ctsn <= '0';
u1i.extclk <= '0';
txd1 <= u1o.txd;
-- serrx_pad : inpad generic map (tech => padtech) port map (dsurx, rxd1);
-- sertx_pad : outpad generic map (tech => padtech) port map (dsutx, txd1);
-- led(0) <= not rxd1;
-- led(1) <= not txd1;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
nospi: if CFG_SPICTRL_ENABLE = 0 and CFG_SPIMCTRL = 0 generate
apbo(7) <= apb_none;
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm
generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 15, paddr => 15, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 7,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G, rmii => 1)
port map(rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
apbi => apbi, apbo => apbo(15), ethi => ethi, etho => etho);
PhyRstn<=rstn;
end generate;
etxc_pad : outpad generic map (tech => padtech)
port map (PhyClk50Mhz, eth_clk);
ethpads : if (CFG_GRETH = 1) generate
emdio_pad : iopad generic map (tech => padtech)
port map (PhyMdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
ethi.rmii_clk<=eth_clk90;
erxd_pad : inpadv generic map (tech => padtech, width => 2) --8
port map (PhyRxd, ethi.rxd(1 downto 0));
erxer_pad : inpad generic map (tech => padtech)
port map (PhyRxEr, ethi.rx_er);
erxcr_pad : inpad generic map (tech => padtech)
port map (PhyCrs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 2)
port map (PhyTxd, etho.txd(1 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (PhyTxEn, etho.tx_en);
emdc_pad : outpad generic map (tech => padtech)
port map (PhyMdc, etho.mdc);
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram
generic map (hindex => 3, haddr => CFG_AHBRADDR, tech => CFG_MEMTECH,
kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
-- Test report module, only used for simulation ----------------------
-----------------------------------------------------------------------
--pragma translate_off
test0 : ahbrep generic map (hindex => 4, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(4));
--pragma translate_on
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+1) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Demonstration design for Digilent NEXYS 4 board",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
-----------------------------------------------------------------------
--- Ethernet Clock Generation ---------------------------------------
-----------------------------------------------------------------------
-- 50 MHz clock for output
bufgclk0 : BUFG port map (I => eth_clk_nobuf, O => eth_clk);
-- 50 MHz with +90 deg phase for Rx GRETH
bufgclk45 : BUFG port map (I => eth_clk90_nobuf, O => eth_clk90);
CLKFBIN <= CLKFBOUT;
eth_pll_rst <= not cgi.pllrst;
PLLE2_ADV_inst : PLLE2_ADV generic map (
BANDWIDTH => "OPTIMIZED", -- OPTIMIZED, HIGH, LOW
CLKFBOUT_MULT => 8, -- Multiply value for all CLKOUT, (2-64)
CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB, (-360.000-360.000).
-- CLKIN_PERIOD: Input clock period in nS to ps resolution (i.e. 33.333 is 30 MHz).
CLKIN1_PERIOD => 1000000.0/real(100000.0),
CLKIN2_PERIOD => 0.0,
-- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for CLKOUT (1-128)
CLKOUT0_DIVIDE => 16,
CLKOUT1_DIVIDE => 16,
CLKOUT2_DIVIDE => 1,
CLKOUT3_DIVIDE => 1,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
-- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for CLKOUT outputs (0.001-0.999).
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT2_DUTY_CYCLE => 0.5,
CLKOUT3_DUTY_CYCLE => 0.5,
CLKOUT4_DUTY_CYCLE => 0.5,
CLKOUT5_DUTY_CYCLE => 0.5,
-- CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for CLKOUT outputs (-360.000-360.000).
CLKOUT0_PHASE => 0.0,
CLKOUT1_PHASE => 90.0,
CLKOUT2_PHASE => 0.0,
CLKOUT3_PHASE => 0.0,
CLKOUT4_PHASE => 0.0,
CLKOUT5_PHASE => 0.0,
COMPENSATION => "ZHOLD", -- ZHOLD, BUF_IN, EXTERNAL, INTERNAL
DIVCLK_DIVIDE => 1, -- Master division value (1-56)
-- REF_JITTER: Reference input jitter in UI (0.000-0.999).
REF_JITTER1 => 0.0,
REF_JITTER2 => 0.0,
STARTUP_WAIT => "TRUE" -- Delay DONE until PLL Locks, ("TRUE"/"FALSE")
)
port map (
-- Clock Outputs: 1-bit (each) output: User configurable clock outputs
CLKOUT0 => eth_clk_nobuf,
CLKOUT1 => eth_clk90_nobuf,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
-- DRP Ports: 16-bit (each) output: Dynamic reconfigration ports
DO => open,
DRDY => open,
-- Feedback Clocks: 1-bit (each) output: Clock feedback ports
CLKFBOUT => CLKFBOUT,
-- Status Ports: 1-bit (each) output: PLL status ports
LOCKED => open,
-- Clock Inputs: 1-bit (each) input: Clock inputs
CLKIN1 => clk,
CLKIN2 => '0',
-- Con trol Ports: 1-bit (each) input: PLL control ports
CLKINSEL => '1',
PWRDWN => '0',
RST => eth_pll_rst,
-- DRP Ports: 7-bit (each) input: Dynamic reconfigration ports
DADDR => "0000000",
DCLK => '0',
DEN => '0',
DI => "0000000000000000",
DWE => '0',
-- Feedback Clocks: 1-bit (each) input: Clock feedback ports
CLKFBIN => CLKFBIN
);
end rtl;
| gpl-3.0 | a6319edb22086ab0ed6124925e4ee761 | 0.522994 | 3.835622 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/maps/syncfifo_2p.vhd | 1 | 5,612 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: syncfifo_2p
-- File: syncfifo_2p.vhd
-- Authors: Pascal Trotta
-- Andrea Gianarro - Cobham Gaisler AB
-- Description: Syncronous 2-port fifo with tech selection
-----------------------------------------------------------------------------
-- Notes: Generic fifo has the following features & limitations:
-- -almost full is driven only in write clock domain;
-- -almost empty is driven only in read clock domain;
-- -full and empty are driven in both clock domains;
-- -usedw is re-computed in each clock domain;
-- -in "first word fall through" mode rempty should be observed as data
-- valid signal, as the first word written into the FIFO immediately
-- appears on the output. If renable is asserted while empty='0', and
-- at the next read clock rising edge empty='1', then new read data is
-- not valid because fifo is empty. This does not apply in standard fifo
-- mode, i.e., when empty is asserted, the last read data is valid;
-- -it works also if rclk = wclk. With sepclk=0 synchronization stages
-- and gray encoder/decoder are not instantiated, since not necessary.
------------------------------------------------------------------------------
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use work.allmem.all;
library grlib;
use grlib.config.all;
use grlib.config_types.all;
use grlib.stdlib.all;
entity syncfifo_2p is
generic (
tech : integer := 0; -- target technology
abits : integer := 10; -- fifo address bits (actual fifo depth = 2**abits)
dbits : integer := 32; -- fifo data width
sepclk : integer := 1; -- 1 = asynchrounous read/write clocks, 0 = synchronous read/write clocks
pfull : integer := 100; -- almost full threshold (max 2**abits - 3)
pempty : integer := 10; -- almost empty threshold (min 2)
fwft : integer := 0 -- 1 = first word fall trough mode, 0 = standard mode
);
port (
rclk : in std_logic; -- read clock
rrstn : in std_logic; -- read clock domain synchronous reset
wrstn : in std_logic; -- write clock domain synchronous reset
renable : in std_logic; -- read enable
rfull : out std_logic; -- fifo full (synchronized in read clock domain)
rempty : out std_logic; -- fifo empty
aempty : out std_logic; -- fifo almost empty (depending on pempty threshold)
rusedw : out std_logic_vector(abits-1 downto 0); -- fifo used words (synchronized in read clock domain)
dataout : out std_logic_vector(dbits-1 downto 0); -- fifo data output
wclk : in std_logic; -- write clock
write : in std_logic; -- write enable
wfull : out std_logic; -- fifo full
afull : out std_logic; -- fifo almost full (depending on pfull threshold)
wempty : out std_logic; -- fifo empty (synchronized in write clock domain)
wusedw : out std_logic_vector(abits-1 downto 0); -- fifo used words (synchronized in write clock domain)
datain : in std_logic_vector(dbits-1 downto 0)); -- fifo data input
end;
architecture rtl of syncfifo_2p is
begin
-- Altera fifo
alt : if (tech = altera) or (tech = stratix1) or (tech = stratix2) or
(tech = stratix3) or (tech = stratix4) generate
x0 : altera_fifo_dp generic map (tech, abits, dbits)
port map (rclk, renable, rfull, rempty, rusedw, dataout, wclk,
write, wfull, wempty, wusedw, datain);
end generate;
-- generic FIFO implemented using syncram_2p component
inf : if (tech /= altera) and (tech /= stratix1) and (tech /= stratix2) and
(tech /= stratix3) and (tech /= stratix4) generate
x0: generic_fifo generic map (tech, abits, dbits, sepclk, pfull, pempty, fwft)
port map (rclk, rrstn, wrstn, renable, rfull, rempty, aempty, rusedw, dataout,
wclk, write, wfull, afull, wempty, wusedw, datain);
end generate;
-- pragma translate_off
nofifo : if (has_2pfifo(tech) = 0) and (has_2pram(tech) = 0) generate
x : process
begin
assert false report "syncfifo_2p: technology " & tech_table(tech) &
" not supported"
severity failure;
wait;
end process;
end generate;
dmsg : if GRLIB_CONFIG_ARRAY(grlib_debug_level) >= 2 generate
x : process
begin
assert false report "syncfifo_2p: " & tost(2**abits) & "x" & tost(dbits) &
" (" & tech_table(tech) & ")"
severity note;
wait;
end process;
end generate;
-- pragma translate_on
end;
| gpl-3.0 | aaaa49a615184c11940de2d8133e8dc6 | 0.629009 | 3.952113 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-gr-xc6s/ahb2mig_grxc6s_2p.vhd | 1 | 23,108 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: ahb2mig_grxc6s_2p
-- File: ahb2mig_grxc6s_2p.vhd
-- Author: Jiri Gaisler - Aeroflex Gaisler AB
--
-- This is a AHB-2.0 interface for the Xilinx Spartan-6 MIG.
-- One bidir 32-bit port is used for the main AHB bus, while
-- a second read-only port can be enabled for a VGA frame buffer.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahb2mig_grxc6s_2p is
generic(
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
vgamst : integer := 0;
vgaburst : integer := 0;
clkdiv : integer := 2
);
port(
mcb3_dram_dq : inout std_logic_vector(15 downto 0);
mcb3_dram_a : out std_logic_vector(12 downto 0);
mcb3_dram_ba : out std_logic_vector(2 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
ahbmi : out ahb_mst_in_type;
ahbmo : in ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
calib_done : out std_logic;
test_error : out std_logic;
rst_n_syn : out std_logic;
rst_n_async : in std_logic;
clk_amba : out std_logic;
clk_mem_n : in std_logic;
clk_mem_p : in std_logic;
clk_125 : out std_logic;
clk_100 : out std_logic
);
end ;
architecture rtl of ahb2mig_grxc6s_2p is
component mig_37
generic
(
C3_P0_MASK_SIZE : integer := 4;
C3_P0_DATA_PORT_SIZE : integer := 32;
C3_P1_MASK_SIZE : integer := 4;
C3_P1_DATA_PORT_SIZE : integer := 32;
C3_MEMCLK_PERIOD : integer := 5000; -- Memory data transfer clock period.
C3_RST_ACT_LOW : integer := 0; -- # = 1 for active low reset, -- # = 0 for active high reset.
C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED"; -- input clock type DIFFERENTIAL or SINGLE_ENDED.
C3_CALIB_SOFT_IP : string := "TRUE"; -- # = TRUE, Enables the soft calibration logic, -- # = FALSE, Disables the soft calibration logic.
C3_SIMULATION : string := "FALSE"; -- # = TRUE, Simulating the design. Useful to reduce the simulation time, -- # = FALSE, Implementing the design.
DEBUG_EN : integer := 0; -- # = 1, Enable debug signals/controls, -- = 0, Disable debug signals/controls.
C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN"; -- The order in which user address is provided to the memory controller, -- ROW_BANK_COLUMN or BANK_ROW_COLUMN.
C3_NUM_DQ_PINS : integer := 16; -- External memory data width.
C3_MEM_ADDR_WIDTH : integer := 13; -- External memory address width.
C3_MEM_BANKADDR_WIDTH : integer := 3; -- External memory bank address width.
C3_CLKOUT5_DIVIDE : integer := 10 -- Extra clock divider
);
port (
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udm : out std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_n : in std_logic;
c3_calib_done : out std_logic;
c3_clk0 : out std_logic;
c3_rst0 : out std_logic;
clk_125 : out std_logic; -- 125 MHz for RGMII
clk_100 : out std_logic; -- Extra clock
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
c3_p0_cmd_clk : in std_logic;
c3_p0_cmd_en : in std_logic;
c3_p0_cmd_instr : in std_logic_vector(2 downto 0);
c3_p0_cmd_bl : in std_logic_vector(5 downto 0);
c3_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p0_cmd_empty : out std_logic;
c3_p0_cmd_full : out std_logic;
c3_p0_wr_clk : in std_logic;
c3_p0_wr_en : in std_logic;
c3_p0_wr_mask : in std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
c3_p0_wr_data : in std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_wr_full : out std_logic;
c3_p0_wr_empty : out std_logic;
c3_p0_wr_count : out std_logic_vector(6 downto 0);
c3_p0_wr_underrun : out std_logic;
c3_p0_wr_error : out std_logic;
c3_p0_rd_clk : in std_logic;
c3_p0_rd_en : in std_logic;
c3_p0_rd_data : out std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_rd_full : out std_logic;
c3_p0_rd_empty : out std_logic;
c3_p0_rd_count : out std_logic_vector(6 downto 0);
c3_p0_rd_overflow : out std_logic;
c3_p0_rd_error : out std_logic;
c3_p2_cmd_clk : in std_logic;
c3_p2_cmd_en : in std_logic;
c3_p2_cmd_instr : in std_logic_vector(2 downto 0);
c3_p2_cmd_bl : in std_logic_vector(5 downto 0);
c3_p2_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p2_cmd_empty : out std_logic;
c3_p2_cmd_full : out std_logic;
c3_p2_rd_clk : in std_logic;
c3_p2_rd_en : in std_logic;
c3_p2_rd_data : out std_logic_vector(31 downto 0);
c3_p2_rd_full : out std_logic;
c3_p2_rd_empty : out std_logic;
c3_p2_rd_count : out std_logic_vector(6 downto 0);
c3_p2_rd_overflow : out std_logic;
c3_p2_rd_error : out std_logic
);
end component;
type bstate_type is (idle, start, read1);
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
-- 5 => ahb_iobar(ioaddr, iomask),
others => zero32);
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, 0, 0),
1 => apb_iobar(paddr, pmask));
type reg_type is record
bstate : bstate_type;
cmd_bl : std_logic_vector(5 downto 0);
wr_count : std_logic_vector(6 downto 0);
rd_cnt : std_logic_vector(5 downto 0);
hready : std_logic;
hsel : std_logic;
hwrite : std_logic;
htrans : std_logic_vector(1 downto 0);
hburst : std_logic_vector(2 downto 0);
hsize : std_logic_vector(2 downto 0);
hrdata : std_logic_vector(31 downto 0);
haddr : std_logic_vector(31 downto 0);
hmaster : std_logic_vector(3 downto 0);
end record;
type mcb_type is record
cmd_en : std_logic;
cmd_instr : std_logic_vector(2 downto 0);
cmd_empty : std_logic;
cmd_full : std_logic;
cmd_bl : std_logic_vector(5 downto 0);
cmd_byte_addr : std_logic_vector(29 downto 0);
wr_full : std_logic;
wr_empty : std_logic;
wr_underrun : std_logic;
wr_error : std_logic;
wr_mask : std_logic_vector(3 downto 0);
wr_en : std_logic;
wr_data : std_logic_vector(31 downto 0);
wr_count : std_logic_vector(6 downto 0);
rd_data : std_logic_vector(31 downto 0);
rd_full : std_logic;
rd_empty : std_logic;
rd_count : std_logic_vector(6 downto 0);
rd_overflow : std_logic;
rd_error : std_logic;
rd_en : std_logic;
end record;
type reg2_type is record
bstate : bstate_type;
cmd_bl : std_logic_vector(5 downto 0);
rd_cnt : std_logic_vector(5 downto 0);
hready : std_logic;
hsel : std_logic;
hrdata : std_logic_vector(31 downto 0);
haddr : std_logic_vector(31 downto 0);
end record;
type p2_if_type is record
cmd_en : std_logic;
cmd_instr : std_logic_vector(2 downto 0);
cmd_bl : std_logic_vector(5 downto 0);
cmd_empty : std_logic;
cmd_full : std_logic;
rd_en : std_logic;
rd_data : std_logic_vector(31 downto 0);
rd_full : std_logic;
rd_empty : std_logic;
rd_count : std_logic_vector(6 downto 0);
rd_overflow : std_logic;
rd_error : std_logic;
end record;
signal r, rin : reg_type;
signal r2, r2in : reg2_type;
signal i : mcb_type;
signal p2 : p2_if_type;
signal clk_amba_i : std_logic;
signal rst_n_syn_i : std_logic;
signal rst_syn : std_logic;
signal calib_done_i : std_logic;
begin
clk_amba <= clk_amba_i;
rst_n_syn <= rst_n_syn_i and calib_done_i;
rst_n_syn_i <= not rst_syn;
calib_done <= calib_done_i;
comb: process( rst_n_syn_i, r, ahbsi, i )
variable v : reg_type;
variable wmask : std_logic_vector(3 downto 0);
variable wr_en : std_logic;
variable cmd_en : std_logic;
variable cmd_instr : std_logic_vector(2 downto 0);
variable rd_en : std_logic;
variable cmd_bl : std_logic_vector(5 downto 0);
variable hwdata : std_logic_vector(31 downto 0);
variable readdata : std_logic_vector(31 downto 0);
begin
v := r; wr_en := '0'; cmd_en := '0'; cmd_instr := "000";
rd_en := '0';
if (ahbsi.hready = '1') then
if (ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '1' then
v.hsel := '1'; v.hburst := ahbsi.hburst;
v.hwrite := ahbsi.hwrite; v.hsize := ahbsi.hsize;
v.hmaster := ahbsi.hmaster;
v.hready := '0';
if ahbsi.htrans(0) = '0' then v.haddr := ahbsi.haddr; end if;
else
v.hsel := '0'; v.hready := '1';
end if;
v.htrans := ahbsi.htrans;
end if;
hwdata := ahbsi.hwdata(15 downto 0) & ahbsi.hwdata(31 downto 16);
case r.hsize(1 downto 0) is
when "00" => wmask := not decode(r.haddr(1 downto 0));
case r.haddr(1 downto 0) is
when "00" => wmask := "1101";
when "01" => wmask := "1110";
when "10" => wmask := "0111";
when others => wmask := "1011";
end case;
when "01" => wmask := not decode(r.haddr(1 downto 0));
wmask(3) := wmask(2); wmask(1) := wmask(0);
when others => wmask := "0000";
end case;
i.wr_mask <= wmask;
cmd_bl := r.cmd_bl;
case r.bstate is
when idle =>
if v.hsel = '1' then
v.bstate := start;
v.hready := ahbsi.hwrite and not i.cmd_full and not i.wr_full;
v.haddr := ahbsi.haddr;
end if;
v.cmd_bl := (others => '0');
when start =>
if r.hwrite = '1' then
v.haddr := r.haddr;
if r.hready = '1' then
v.cmd_bl := r.cmd_bl + 1; v.hready := '1'; wr_en := '1';
if (ahbsi.htrans /= "11") then
if v.hsel = '1' then
if (ahbsi.hwrite = '0') or (i.wr_count >= "0000100") then
v.hready := '0';
else v.hready := '1'; end if;
else v.bstate := idle; end if;
v.cmd_bl := (others => '0'); v.haddr := ahbsi.haddr;
cmd_en := '1';
elsif (i.cmd_full = '1') then
v.hready := '0';
elsif (i.wr_count >= "0101111") then
v.hready := '0'; cmd_en := '1';
v.cmd_bl := (others => '0'); v.haddr := ahbsi.haddr;
end if;
else
if (i.cmd_full = '0') and (i.wr_count <= "0001111") then
v.hready := '1';
end if;
end if;
else
if i.cmd_full = '0' then
cmd_en := '1'; cmd_instr(0) := '1';
v.cmd_bl := "000" & not r.haddr(4 downto 2);
cmd_bl := v.cmd_bl;
v.bstate := read1;
end if;
end if;
when read1 =>
v.hready := '0';
if (r.rd_cnt = "000000") then -- flush data from previous line
if (i.rd_empty = '0') or ((r.hready = '1') and (ahbsi.htrans /= "11")) then
v.hrdata(31 downto 0) := i.rd_data(15 downto 0) & i.rd_data(31 downto 16);
v.hready := '1';
if (i.rd_empty = '0') then v.cmd_bl := r.cmd_bl - 1; rd_en := '1'; end if;
if (r.cmd_bl = "000000") or (ahbsi.htrans /= "11") then
if (ahbsi.hsel(hindex) = '1') and (ahbsi.htrans = "10") and (r.hready = '1') then
v.bstate := start; v.hready := ahbsi.hwrite and not i.cmd_full and not i.wr_full;
v.cmd_bl := (others => '0');
else
v.bstate := idle;
end if;
if (i.rd_empty = '1') then v.rd_cnt := r.cmd_bl + 1;
else v.rd_cnt := r.cmd_bl; end if;
end if;
end if;
end if;
when others =>
end case;
readdata := (others => '0');
-- case apbi.paddr(5 downto 2) is
-- when "0000" => readdata(nbits-1 downto 0) := r.din2;
-- when "0001" => readdata(nbits-1 downto 0) := r.dout;
-- when others =>
-- end case;
readdata(20 downto 0) :=
i.rd_error & i.rd_overflow & i.wr_error & i.wr_underrun &
i.cmd_full & i.rd_full & i.rd_empty & i.wr_full & i.wr_empty &
r.rd_cnt & r.cmd_bl;
if (r.rd_cnt /= "000000") and (i.rd_empty = '0') then
rd_en := '1'; v.rd_cnt := r.rd_cnt - 1;
end if;
if rst_n_syn_i = '0' then
v.rd_cnt := "000000"; v.bstate := idle; v.hready := '1';
end if;
rin <= v;
apbo.prdata <= readdata;
i.rd_en <= rd_en;
i.wr_en <= wr_en;
i.cmd_bl <= cmd_bl;
i.cmd_en <= cmd_en;
i.cmd_instr <= cmd_instr;
i.wr_data <= hwdata;
end process;
i.cmd_byte_addr <= r.haddr(29 downto 2) & "00";
ahbso.hready <= r.hready;
ahbso.hresp <= "00"; --r.hresp;
ahbso.hrdata <= r.hrdata;
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
apbo.pirq <= (others => '0');
regs : process(clk_amba_i)
begin
if rising_edge(clk_amba_i) then
r <= rin;
end if;
end process;
port2 : if vgamst /= 0 generate
comb2: process( rst_n_syn_i, r2, ahbmo, p2 )
variable v2 : reg2_type;
variable cmd_en : std_logic;
variable rd_en : std_logic;
begin
v2 := r2; cmd_en := '0'; rd_en := '0';
case r2.bstate is
when idle =>
if ahbmo.htrans(1) = '1' then
v2.bstate := start;
v2.hready := '0';
v2.haddr := ahbmo.haddr;
else v2.hready := '1'; end if;
v2.cmd_bl := (others => '0');
when start =>
if p2.cmd_full = '0' then
cmd_en := '1';
v2.cmd_bl := conv_std_logic_vector(vgaburst-1, 6);
v2.bstate := read1;
end if;
when read1 =>
v2.hready := '0';
if (r2.rd_cnt = "000000") then -- flush data from previous line
if (p2.rd_empty = '0') or ((r2.hready = '1') and (ahbmo.htrans /= "11")) then
v2.hrdata(31 downto 0) := p2.rd_data(15 downto 0) & p2.rd_data(31 downto 16);
v2.hready := '1';
if (p2.rd_empty = '0') then v2.cmd_bl := r2.cmd_bl - 1; rd_en := '1'; end if;
if (r2.cmd_bl = "000000") or (ahbmo.htrans /= "11") then
if (ahbmo.htrans = "10") and (r2.hready = '1') then
v2.bstate := start; v2.hready := '0';
v2.cmd_bl := (others => '0');
else
v2.bstate := idle;
end if;
if (p2.rd_empty = '1') then v2.rd_cnt := r2.cmd_bl + 1;
else v2.rd_cnt := r2.cmd_bl; end if;
end if;
end if;
end if;
when others =>
end case;
if (r2.rd_cnt /= "000000") and (p2.rd_empty = '0') then
rd_en := '1'; v2.rd_cnt := r2.rd_cnt - 1;
end if;
v2.haddr(1 downto 0) := "00";
if rst_n_syn_i = '0' then
v2.rd_cnt := "000000"; v2.bstate := idle; v2.hready := '1';
end if;
r2in <= v2;
p2.rd_en <= rd_en;
p2.cmd_bl <= v2.cmd_bl;
p2.cmd_en <= cmd_en;
p2.cmd_instr <= "001";
end process;
ahbmi.hrdata <= r2.hrdata;
ahbmi.hresp <= "00";
ahbmi.hgrant <= (others => '1');
ahbmi.hready <= r2.hready;
ahbmi.testen <= '0';
ahbmi.testrst <= '0';
ahbmi.scanen <= '0';
ahbmi.testoen <= '0';
ahbmi.hirq <= (others => '0');
ahbmi.testin <= (others => '0');
regs : process(clk_amba_i)
begin
if rising_edge(clk_amba_i) then
r2 <= r2in;
end if;
end process;
end generate;
noport2 : if vgamst = 0 generate
p2.cmd_en <= '0';
p2.rd_en <= '0';
end generate;
MCB_inst : mig_37 generic map(
C3_P0_MASK_SIZE => 4,
C3_P0_DATA_PORT_SIZE => 32,
C3_P1_MASK_SIZE => 4,
C3_P1_DATA_PORT_SIZE => 32,
C3_MEMCLK_PERIOD => 4000,
C3_RST_ACT_LOW => 1,
-- C3_INPUT_CLK_TYPE => "DIFFERENTIAL",
C3_CALIB_SOFT_IP => "TRUE",
-- pragma translate_off
C3_SIMULATION => "TRUE",
-- pragma translate_on
C3_MEM_ADDR_ORDER => "BANK_ROW_COLUMN",
C3_NUM_DQ_PINS => 16,
C3_MEM_ADDR_WIDTH => 13,
C3_MEM_BANKADDR_WIDTH => 3,
C3_CLKOUT5_DIVIDE => clkdiv
-- C3_MC_CALIB_BYPASS => "YES"
)
port map (
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_odt => mcb3_dram_odt,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_dm => mcb3_dram_dm,
mcb3_dram_udqs => mcb3_dram_udqs,
mcb3_dram_udqs_n => mcb3_dram_udqs_n,
mcb3_rzq => mcb3_rzq,
mcb3_zio => mcb3_zio,
mcb3_dram_udm => mcb3_dram_udm,
-- c3_sys_clk_p => clk_mem_p,
-- c3_sys_clk_n => clk_mem_n,
c3_sys_clk => clk_mem_p,
c3_sys_rst_n => rst_n_async,
c3_calib_done => calib_done_i,
c3_clk0 => clk_amba_i,
c3_rst0 => rst_syn,
clk_125 => clk_125,
clk_100 => clk_100,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
c3_p0_cmd_clk => clk_amba_i,
c3_p0_cmd_en => i.cmd_en,
c3_p0_cmd_instr => i.cmd_instr,
c3_p0_cmd_bl => i.cmd_bl,
c3_p0_cmd_byte_addr => i.cmd_byte_addr,
c3_p0_cmd_empty => i.cmd_empty,
c3_p0_cmd_full => i.cmd_full,
c3_p0_wr_clk => clk_amba_i,
c3_p0_wr_en => i.wr_en,
c3_p0_wr_mask => i.wr_mask,
c3_p0_wr_data => i.wr_data,
c3_p0_wr_full => i.wr_full,
c3_p0_wr_empty => i.wr_empty,
c3_p0_wr_count => i.wr_count,
c3_p0_wr_underrun => i.wr_underrun,
c3_p0_wr_error => i.wr_error,
c3_p0_rd_clk => clk_amba_i,
c3_p0_rd_en => i.rd_en,
c3_p0_rd_data => i.rd_data,
c3_p0_rd_full => i.rd_full,
c3_p0_rd_empty => i.rd_empty,
c3_p0_rd_count => i.rd_count,
c3_p0_rd_overflow => i.rd_overflow,
c3_p0_rd_error => i.rd_error,
c3_p2_cmd_clk => clk_amba_i,
c3_p2_cmd_en => p2.cmd_en,
c3_p2_cmd_instr => p2.cmd_instr,
c3_p2_cmd_bl => p2.cmd_bl,
c3_p2_cmd_byte_addr => r2.haddr(29 downto 0),
c3_p2_cmd_empty => p2.cmd_empty,
c3_p2_cmd_full => p2.cmd_full,
c3_p2_rd_clk => clk_amba_i,
c3_p2_rd_en => p2.rd_en,
c3_p2_rd_data => p2.rd_data,
c3_p2_rd_full => p2.rd_full,
c3_p2_rd_empty => p2.rd_empty,
c3_p2_rd_count => p2.rd_count,
c3_p2_rd_overflow => p2.rd_overflow,
c3_p2_rd_error => p2.rd_error
);
end;
| gpl-3.0 | 3a1e47d6fc4a2169e80698222143d697 | 0.50225 | 3.034936 | false | false | false | false |
ggaray/nicsim-vhd | arbiter.vhd | 1 | 7,667 | -- NICSim-vhd: A VHDL-based modelling and simulation of NIC's buffers
-- Copyright (C) 2013 Godofredo R. Garay <godofredo.garay (-at-) gmail.com>
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
use std.textio.all;
library ieee;
use ieee.math_real.all; -- for uniform
--use ieee.numeric_std.all; -- for TO_UNSIGNED
use ieee.std_logic_1164.all;
entity arbiter is
port (
req : in bit;
gnt : out bit := '1';
-- bus_transfer_cycles_counter_out : out integer := 0;
arb_latency_cycles_counter_out : out integer := 0;
pciclk : in bit
);
end arbiter;
-- Architecture begin
architecture V1 of arbiter is
--------------- Random number generator configuration ---------------
constant arbiter_seed1_value : positive := 14;
constant arbiter_seed2_value : positive := 49;
--------------- Bus arbitration latency configuration ---------------
constant min_arbitration_latency : positive := 1;
constant max_arbitration_latency : positive := 100;
--------------- Burst size configuration ---------------
constant dma_burst_size_in_cycles : integer := 32; -- DMA busrt size = 256 bytes (PCI-X bus)
--constant dma_burst_size_in_cycles : integer := 64; -- DMA busrt size = 512 bytes (PCI-X bus)
--constant dma_burst_size_in_cycles : integer := 128; -- DMA busrt size = 1024 bytes (PCI-X bus)
--constant dma_burst_size_in_cycles : integer := 256; -- DMA busrt size = 2048 bytes (PCI-X bus)
--constant dma_burst_size_in_cycles : integer := 512; -- DMA busrt size = 4096 bytes (PCI-X bus)
-- ****** In the future, constant pcilck_period should be removed a function based on the pciclk signal should be implemented
--constant pciclk_period : time := 0.03030303 us; -- PCI 33
--constant pciclk_period : time := 0.015151515 us; -- PCI-X 66
constant pciclk_period : time := 0.007518797 us; -- PCI-X 133
--constant pciclk_period : time := 0.003759398 us; -- PCI-X 266
--constant pciclk_period : time := 0.001876173 us; -- PCI-X 533
--------------- Variables Declarations ---------------
shared variable random_cycles_count : integer := 0;
shared variable bus_transfer_cycles_counter : integer := dma_burst_size_in_cycles;
shared variable total_latency_cycles : integer := 0;
shared variable total_bus_transfer_cycles : integer := 0;
shared variable latency_cycles_count : integer := 0;
shared variable gnt_value : bit := '1';
shared variable max_arbitration_latency_in_cycles : integer;
-- Variables needed for arbiter FSM
type pci_bus_state is (idle, waiting_arbitration_latency, bus_granted);
shared variable state : pci_bus_state := idle;
shared variable next_state : pci_bus_state := idle;
-- Variables needed for printing out simulation statistics
shared variable transmission_cycles_count : natural := 0;
shared variable non_transmission_cycles_count : natural := 0;
-- Architecture Begin
begin
-- Arbiter FSM
pci_arbiter_fsm: process
begin
wait until pciclk'event and pciclk = '1';
case state is
when idle =>
gnt_value := '1';
bus_transfer_cycles_counter := 0;
latency_cycles_count := 0;
if req = '1'
then gnt_value := '1';
next_state := idle;
elsif req = '0'
then --latency_cycles_count := generate_random_latency_in_cycles;
latency_cycles_count := random_cycles_count;
total_latency_cycles := total_latency_cycles + latency_cycles_count;
bus_transfer_cycles_counter := dma_burst_size_in_cycles;
--total_bus_transfer_cycles = total_bus_transfer_cycles + bus_transfer_cycles_counter;
assert false
report "pci_arbiter_fsm: waiting_arbitration_latency"
severity note;
next_state := waiting_arbitration_latency;
end if;
when waiting_arbitration_latency =>
if req = '1'
then next_state := idle;
elsif req = '0'
and latency_cycles_count = 0
then gnt_value := '0';
assert false
report "pci_arbiter_fsm: bus_granted"
severity note;
next_state := bus_granted;
elsif req = '0'
and latency_cycles_count > 0
then latency_cycles_count := latency_cycles_count - 1;
next_state := waiting_arbitration_latency;
end if;
when bus_granted =>
if req = '0'
and gnt_value = '1'
and bus_transfer_cycles_counter > 0
and gnt_value = '0'
then assert false
report "pci_arbiter_fsm: bus_granted"
severity note;
next_state := bus_granted;
elsif req = '0'
and gnt_value = '1'
and bus_transfer_cycles_counter = 0
then next_state := idle;
elsif (req = '0'
and bus_transfer_cycles_counter = 0)
or req = '1'
then next_state := idle;
end if;
end case;
state := next_state;
end process pci_arbiter_fsm;
-- FSM of Latecy Cycles Generator
random_number_generator_fsm: process
type generator_state is (idle, generating_random_number, waiting);
variable state : generator_state := idle;
variable next_state : generator_state := idle;
variable random_number : integer := 1;
variable seed1 : positive := arbiter_seed1_value;
variable seed2 : positive := arbiter_seed2_value;
variable rand: real;
file random_arbitration_cycles_file : text open write_mode is "random_arbitration_cycles.out";
variable output_line : line;
begin
case state is
when idle =>
wait until req'event and req = '0';
assert false
report "generating random arbitration latency"
severity note;
next_state := generating_random_number;
when generating_random_number =>
uniform(seed1, seed2, rand);
-- Since rand values are in the interval 0..1, the values are multiplicated by 1000 and rounded.
-- This way, an integer random value in the interval 1..1000 is obtained
random_number := integer(round(rand*1000.0));
--random_number := integer(round(rand * max_arbitration_latency));
if random_number >= min_arbitration_latency
and random_number <= max_arbitration_latency
then random_cycles_count := random_number;
write(output_line, random_cycles_count);
writeline(random_arbitration_cycles_file, output_line);
next_state := waiting;
else next_state := generating_random_number;
end if;
when waiting =>
wait until req'event and req = '0';
next_state := generating_random_number;
end case;
state := next_state;
end process random_number_generator_fsm;
arb_cycles_counter_out_driver: process
begin
wait until pciclk'event and pciclk = '0';
-- bus_transfer_cycles_counter_out <= bus_transfer_cycles_counter;
arb_latency_cycles_counter_out <= latency_cycles_count;
end process arb_cycles_counter_out_driver;
output_signals_driver: process
begin
wait until pciclk'event and pciclk = '1';
gnt <= gnt_value;
end process output_signals_driver;
end V1;
| gpl-3.0 | d5ebf76ba382b2a76e925e781418ff3d | 0.650189 | 3.361245 | false | false | false | false |
hoglet67/CoPro6502 | src/ROM/tuberom_z80_banner.vhd | 1 | 172,760 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tuberom_z80_banner is
port (
CLK : in std_logic;
ADDR : in std_logic_vector(11 downto 0);
DATA : out std_logic_vector(7 downto 0)
);
end;
architecture RTL of tuberom_z80_banner is
signal rom_addr : std_logic_vector(11 downto 0);
begin
p_addr : process(ADDR)
begin
rom_addr <= (others => '0');
rom_addr(11 downto 0) <= ADDR;
end process;
p_rom : process
begin
wait until rising_edge(CLK);
DATA <= (others => '0');
case rom_addr is
when x"000" => DATA <= x"F3";
when x"001" => DATA <= x"11";
when x"002" => DATA <= x"00";
when x"003" => DATA <= x"F0";
when x"004" => DATA <= x"21";
when x"005" => DATA <= x"00";
when x"006" => DATA <= x"00";
when x"007" => DATA <= x"01";
when x"008" => DATA <= x"00";
when x"009" => DATA <= x"10";
when x"00A" => DATA <= x"ED";
when x"00B" => DATA <= x"B0";
when x"00C" => DATA <= x"C3";
when x"00D" => DATA <= x"80";
when x"00E" => DATA <= x"F2";
when x"00F" => DATA <= x"43";
when x"010" => DATA <= x"6F";
when x"011" => DATA <= x"70";
when x"012" => DATA <= x"79";
when x"013" => DATA <= x"72";
when x"014" => DATA <= x"69";
when x"015" => DATA <= x"67";
when x"016" => DATA <= x"68";
when x"017" => DATA <= x"74";
when x"018" => DATA <= x"20";
when x"019" => DATA <= x"41";
when x"01A" => DATA <= x"63";
when x"01B" => DATA <= x"6F";
when x"01C" => DATA <= x"72";
when x"01D" => DATA <= x"6E";
when x"01E" => DATA <= x"20";
when x"01F" => DATA <= x"43";
when x"020" => DATA <= x"6F";
when x"021" => DATA <= x"6D";
when x"022" => DATA <= x"70";
when x"023" => DATA <= x"75";
when x"024" => DATA <= x"74";
when x"025" => DATA <= x"65";
when x"026" => DATA <= x"72";
when x"027" => DATA <= x"73";
when x"028" => DATA <= x"20";
when x"029" => DATA <= x"4C";
when x"02A" => DATA <= x"74";
when x"02B" => DATA <= x"64";
when x"02C" => DATA <= x"2E";
when x"02D" => DATA <= x"20";
when x"02E" => DATA <= x"31";
when x"02F" => DATA <= x"39";
when x"030" => DATA <= x"38";
when x"031" => DATA <= x"34";
when x"032" => DATA <= x"0D";
when x"033" => DATA <= x"48";
when x"034" => DATA <= x"3A";
when x"035" => DATA <= x"7D";
when x"036" => DATA <= x"3C";
when x"037" => DATA <= x"B7";
when x"038" => DATA <= x"C4";
when x"039" => DATA <= x"C0";
when x"03A" => DATA <= x"2C";
when x"03B" => DATA <= x"3A";
when x"03C" => DATA <= x"22";
when x"03D" => DATA <= x"3A";
when x"03E" => DATA <= x"B7";
when x"03F" => DATA <= x"C4";
when x"040" => DATA <= x"F1";
when x"041" => DATA <= x"2C";
when x"042" => DATA <= x"F1";
when x"043" => DATA <= x"21";
when x"044" => DATA <= x"1B";
when x"045" => DATA <= x"3A";
when x"046" => DATA <= x"34";
when x"047" => DATA <= x"7E";
when x"048" => DATA <= x"3D";
when x"049" => DATA <= x"C2";
when x"04A" => DATA <= x"AB";
when x"04B" => DATA <= x"2B";
when x"04C" => DATA <= x"21";
when x"04D" => DATA <= x"EC";
when x"04E" => DATA <= x"3B";
when x"04F" => DATA <= x"7E";
when x"050" => DATA <= x"B7";
when x"051" => DATA <= x"C2";
when x"052" => DATA <= x"34";
when x"053" => DATA <= x"2B";
when x"054" => DATA <= x"21";
when x"055" => DATA <= x"4A";
when x"056" => DATA <= x"3B";
when x"057" => DATA <= x"7E";
when x"058" => DATA <= x"B7";
when x"059" => DATA <= x"C2";
when x"05A" => DATA <= x"34";
when x"05B" => DATA <= x"2B";
when x"05C" => DATA <= x"21";
when x"05D" => DATA <= x"58";
when x"05E" => DATA <= x"3D";
when x"05F" => DATA <= x"23";
when x"060" => DATA <= x"01";
when x"061" => DATA <= x"06";
when x"062" => DATA <= x"00";
when x"063" => DATA <= x"11";
when x"064" => DATA <= x"EC";
when x"065" => DATA <= x"3B";
when x"066" => DATA <= x"C3";
when x"067" => DATA <= x"61";
when x"068" => DATA <= x"FC";
when x"069" => DATA <= x"54";
when x"06A" => DATA <= x"68";
when x"06B" => DATA <= x"65";
when x"06C" => DATA <= x"20";
when x"06D" => DATA <= x"42";
when x"06E" => DATA <= x"75";
when x"06F" => DATA <= x"73";
when x"070" => DATA <= x"69";
when x"071" => DATA <= x"6E";
when x"072" => DATA <= x"65";
when x"073" => DATA <= x"73";
when x"074" => DATA <= x"73";
when x"075" => DATA <= x"20";
when x"076" => DATA <= x"53";
when x"077" => DATA <= x"79";
when x"078" => DATA <= x"73";
when x"079" => DATA <= x"74";
when x"07A" => DATA <= x"65";
when x"07B" => DATA <= x"6D";
when x"07C" => DATA <= x"73";
when x"07D" => DATA <= x"20";
when x"07E" => DATA <= x"47";
when x"07F" => DATA <= x"72";
when x"080" => DATA <= x"6F";
when x"081" => DATA <= x"75";
when x"082" => DATA <= x"70";
when x"083" => DATA <= x"20";
when x"084" => DATA <= x"77";
when x"085" => DATA <= x"6F";
when x"086" => DATA <= x"75";
when x"087" => DATA <= x"6C";
when x"088" => DATA <= x"64";
when x"089" => DATA <= x"20";
when x"08A" => DATA <= x"6C";
when x"08B" => DATA <= x"69";
when x"08C" => DATA <= x"6B";
when x"08D" => DATA <= x"65";
when x"08E" => DATA <= x"20";
when x"08F" => DATA <= x"74";
when x"090" => DATA <= x"6F";
when x"091" => DATA <= x"20";
when x"092" => DATA <= x"74";
when x"093" => DATA <= x"68";
when x"094" => DATA <= x"61";
when x"095" => DATA <= x"6E";
when x"096" => DATA <= x"6B";
when x"097" => DATA <= x"4D";
when x"098" => DATA <= x"69";
when x"099" => DATA <= x"6B";
when x"09A" => DATA <= x"65";
when x"09B" => DATA <= x"20";
when x"09C" => DATA <= x"42";
when x"09D" => DATA <= x"6F";
when x"09E" => DATA <= x"6C";
when x"09F" => DATA <= x"6C";
when x"0A0" => DATA <= x"65";
when x"0A1" => DATA <= x"79";
when x"0A2" => DATA <= x"2C";
when x"0A3" => DATA <= x"4D";
when x"0A4" => DATA <= x"69";
when x"0A5" => DATA <= x"6B";
when x"0A6" => DATA <= x"65";
when x"0A7" => DATA <= x"20";
when x"0A8" => DATA <= x"26";
when x"0A9" => DATA <= x"20";
when x"0AA" => DATA <= x"41";
when x"0AB" => DATA <= x"6C";
when x"0AC" => DATA <= x"6C";
when x"0AD" => DATA <= x"65";
when x"0AE" => DATA <= x"6E";
when x"0AF" => DATA <= x"20";
when x"0B0" => DATA <= x"42";
when x"0B1" => DATA <= x"6F";
when x"0B2" => DATA <= x"6F";
when x"0B3" => DATA <= x"74";
when x"0B4" => DATA <= x"68";
when x"0B5" => DATA <= x"72";
when x"0B6" => DATA <= x"6F";
when x"0B7" => DATA <= x"79";
when x"0B8" => DATA <= x"64";
when x"0B9" => DATA <= x"2C";
when x"0BA" => DATA <= x"52";
when x"0BB" => DATA <= x"69";
when x"0BC" => DATA <= x"63";
when x"0BD" => DATA <= x"68";
when x"0BE" => DATA <= x"61";
when x"0BF" => DATA <= x"72";
when x"0C0" => DATA <= x"64";
when x"0C1" => DATA <= x"20";
when x"0C2" => DATA <= x"43";
when x"0C3" => DATA <= x"6C";
when x"0C4" => DATA <= x"61";
when x"0C5" => DATA <= x"79";
when x"0C6" => DATA <= x"74";
when x"0C7" => DATA <= x"6F";
when x"0C8" => DATA <= x"6E";
when x"0C9" => DATA <= x"2C";
when x"0CA" => DATA <= x"41";
when x"0CB" => DATA <= x"6E";
when x"0CC" => DATA <= x"64";
when x"0CD" => DATA <= x"72";
when x"0CE" => DATA <= x"65";
when x"0CF" => DATA <= x"77";
when x"0D0" => DATA <= x"20";
when x"0D1" => DATA <= x"47";
when x"0D2" => DATA <= x"6F";
when x"0D3" => DATA <= x"72";
when x"0D4" => DATA <= x"64";
when x"0D5" => DATA <= x"6F";
when x"0D6" => DATA <= x"6E";
when x"0D7" => DATA <= x"2C";
when x"0D8" => DATA <= x"43";
when x"0D9" => DATA <= x"68";
when x"0DA" => DATA <= x"72";
when x"0DB" => DATA <= x"69";
when x"0DC" => DATA <= x"73";
when x"0DD" => DATA <= x"20";
when x"0DE" => DATA <= x"48";
when x"0DF" => DATA <= x"61";
when x"0E0" => DATA <= x"6C";
when x"0E1" => DATA <= x"6C";
when x"0E2" => DATA <= x"2C";
when x"0E3" => DATA <= x"4B";
when x"0E4" => DATA <= x"69";
when x"0E5" => DATA <= x"6D";
when x"0E6" => DATA <= x"20";
when x"0E7" => DATA <= x"53";
when x"0E8" => DATA <= x"70";
when x"0E9" => DATA <= x"65";
when x"0EA" => DATA <= x"6E";
when x"0EB" => DATA <= x"63";
when x"0EC" => DATA <= x"65";
when x"0ED" => DATA <= x"2D";
when x"0EE" => DATA <= x"4A";
when x"0EF" => DATA <= x"6F";
when x"0F0" => DATA <= x"6E";
when x"0F1" => DATA <= x"65";
when x"0F2" => DATA <= x"73";
when x"0F3" => DATA <= x"2C";
when x"0F4" => DATA <= x"50";
when x"0F5" => DATA <= x"61";
when x"0F6" => DATA <= x"75";
when x"0F7" => DATA <= x"6C";
when x"0F8" => DATA <= x"20";
when x"0F9" => DATA <= x"4F";
when x"0FA" => DATA <= x"76";
when x"0FB" => DATA <= x"65";
when x"0FC" => DATA <= x"72";
when x"0FD" => DATA <= x"65";
when x"0FE" => DATA <= x"6C";
when x"0FF" => DATA <= x"6C";
when x"100" => DATA <= x"2C";
when x"101" => DATA <= x"44";
when x"102" => DATA <= x"61";
when x"103" => DATA <= x"76";
when x"104" => DATA <= x"69";
when x"105" => DATA <= x"64";
when x"106" => DATA <= x"20";
when x"107" => DATA <= x"50";
when x"108" => DATA <= x"61";
when x"109" => DATA <= x"72";
when x"10A" => DATA <= x"6B";
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when x"2F3" => DATA <= x"B7";
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when x"2F5" => DATA <= x"18";
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when x"2FA" => DATA <= x"3E";
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when x"300" => DATA <= x"11";
when x"301" => DATA <= x"45";
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when x"305" => DATA <= x"70";
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when x"30E" => DATA <= x"C2";
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when x"310" => DATA <= x"F7";
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when x"313" => DATA <= x"F8";
when x"314" => DATA <= x"06";
when x"315" => DATA <= x"00";
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when x"31C" => DATA <= x"FE";
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when x"320" => DATA <= x"F7";
when x"321" => DATA <= x"3A";
when x"322" => DATA <= x"AA";
when x"323" => DATA <= x"FC";
when x"324" => DATA <= x"32";
when x"325" => DATA <= x"A8";
when x"326" => DATA <= x"FC";
when x"327" => DATA <= x"3A";
when x"328" => DATA <= x"AB";
when x"329" => DATA <= x"FC";
when x"32A" => DATA <= x"32";
when x"32B" => DATA <= x"A9";
when x"32C" => DATA <= x"FC";
when x"32D" => DATA <= x"C3";
when x"32E" => DATA <= x"DF";
when x"32F" => DATA <= x"F7";
when x"330" => DATA <= x"CD";
when x"331" => DATA <= x"76";
when x"332" => DATA <= x"F8";
when x"333" => DATA <= x"06";
when x"334" => DATA <= x"00";
when x"335" => DATA <= x"CD";
when x"336" => DATA <= x"39";
when x"337" => DATA <= x"F4";
when x"338" => DATA <= x"CD";
when x"339" => DATA <= x"77";
when x"33A" => DATA <= x"F8";
when x"33B" => DATA <= x"FE";
when x"33C" => DATA <= x"0D";
when x"33D" => DATA <= x"C2";
when x"33E" => DATA <= x"CC";
when x"33F" => DATA <= x"F7";
when x"340" => DATA <= x"3E";
when x"341" => DATA <= x"04";
when x"342" => DATA <= x"21";
when x"343" => DATA <= x"01";
when x"344" => DATA <= x"00";
when x"345" => DATA <= x"CD";
when x"346" => DATA <= x"F4";
when x"347" => DATA <= x"FF";
when x"348" => DATA <= x"7D";
when x"349" => DATA <= x"32";
when x"34A" => DATA <= x"AE";
when x"34B" => DATA <= x"FC";
when x"34C" => DATA <= x"2A";
when x"34D" => DATA <= x"AA";
when x"34E" => DATA <= x"FC";
when x"34F" => DATA <= x"CD";
when x"350" => DATA <= x"E7";
when x"351" => DATA <= x"FF";
when x"352" => DATA <= x"CD";
when x"353" => DATA <= x"71";
when x"354" => DATA <= x"F4";
when x"355" => DATA <= x"CD";
when x"356" => DATA <= x"1D";
when x"357" => DATA <= x"F4";
when x"358" => DATA <= x"7E";
when x"359" => DATA <= x"CD";
when x"35A" => DATA <= x"0D";
when x"35B" => DATA <= x"F4";
when x"35C" => DATA <= x"CD";
when x"35D" => DATA <= x"1D";
when x"35E" => DATA <= x"F4";
when x"35F" => DATA <= x"7E";
when x"360" => DATA <= x"CD";
when x"361" => DATA <= x"76";
when x"362" => DATA <= x"F4";
when x"363" => DATA <= x"E5";
when x"364" => DATA <= x"06";
when x"365" => DATA <= x"01";
when x"366" => DATA <= x"21";
when x"367" => DATA <= x"00";
when x"368" => DATA <= x"00";
when x"369" => DATA <= x"CD";
when x"36A" => DATA <= x"E0";
when x"36B" => DATA <= x"FF";
when x"36C" => DATA <= x"CD";
when x"36D" => DATA <= x"40";
when x"36E" => DATA <= x"F4";
when x"36F" => DATA <= x"06";
when x"370" => DATA <= x"00";
when x"371" => DATA <= x"5D";
when x"372" => DATA <= x"E1";
when x"373" => DATA <= x"FE";
when x"374" => DATA <= x"8A";
when x"375" => DATA <= x"28";
when x"376" => DATA <= x"27";
when x"377" => DATA <= x"FE";
when x"378" => DATA <= x"8B";
when x"379" => DATA <= x"28";
when x"37A" => DATA <= x"20";
when x"37B" => DATA <= x"FE";
when x"37C" => DATA <= x"01";
when x"37D" => DATA <= x"C2";
when x"37E" => DATA <= x"A1";
when x"37F" => DATA <= x"F3";
when x"380" => DATA <= x"7E";
when x"381" => DATA <= x"CB";
when x"382" => DATA <= x"27";
when x"383" => DATA <= x"CB";
when x"384" => DATA <= x"27";
when x"385" => DATA <= x"CB";
when x"386" => DATA <= x"27";
when x"387" => DATA <= x"CB";
when x"388" => DATA <= x"27";
when x"389" => DATA <= x"83";
when x"38A" => DATA <= x"77";
when x"38B" => DATA <= x"3E";
when x"38C" => DATA <= x"08";
when x"38D" => DATA <= x"CD";
when x"38E" => DATA <= x"71";
when x"38F" => DATA <= x"F6";
when x"390" => DATA <= x"CD";
when x"391" => DATA <= x"71";
when x"392" => DATA <= x"F6";
when x"393" => DATA <= x"CD";
when x"394" => DATA <= x"71";
when x"395" => DATA <= x"F6";
when x"396" => DATA <= x"CD";
when x"397" => DATA <= x"71";
when x"398" => DATA <= x"F6";
when x"399" => DATA <= x"18";
when x"39A" => DATA <= x"BD";
when x"39B" => DATA <= x"23";
when x"39C" => DATA <= x"18";
when x"39D" => DATA <= x"B1";
when x"39E" => DATA <= x"2B";
when x"39F" => DATA <= x"18";
when x"3A0" => DATA <= x"AE";
when x"3A1" => DATA <= x"3A";
when x"3A2" => DATA <= x"AE";
when x"3A3" => DATA <= x"FC";
when x"3A4" => DATA <= x"6F";
when x"3A5" => DATA <= x"26";
when x"3A6" => DATA <= x"00";
when x"3A7" => DATA <= x"3E";
when x"3A8" => DATA <= x"04";
when x"3A9" => DATA <= x"CD";
when x"3AA" => DATA <= x"F4";
when x"3AB" => DATA <= x"FF";
when x"3AC" => DATA <= x"CD";
when x"3AD" => DATA <= x"E7";
when x"3AE" => DATA <= x"FF";
when x"3AF" => DATA <= x"D1";
when x"3B0" => DATA <= x"C1";
when x"3B1" => DATA <= x"F1";
when x"3B2" => DATA <= x"C9";
when x"3B3" => DATA <= x"CD";
when x"3B4" => DATA <= x"76";
when x"3B5" => DATA <= x"F8";
when x"3B6" => DATA <= x"06";
when x"3B7" => DATA <= x"00";
when x"3B8" => DATA <= x"CD";
when x"3B9" => DATA <= x"39";
when x"3BA" => DATA <= x"F4";
when x"3BB" => DATA <= x"FE";
when x"3BC" => DATA <= x"0D";
when x"3BD" => DATA <= x"28";
when x"3BE" => DATA <= x"10";
when x"3BF" => DATA <= x"FE";
when x"3C0" => DATA <= x"20";
when x"3C1" => DATA <= x"C2";
when x"3C2" => DATA <= x"CC";
when x"3C3" => DATA <= x"F7";
when x"3C4" => DATA <= x"2A";
when x"3C5" => DATA <= x"AA";
when x"3C6" => DATA <= x"FC";
when x"3C7" => DATA <= x"CD";
when x"3C8" => DATA <= x"77";
when x"3C9" => DATA <= x"F8";
when x"3CA" => DATA <= x"CD";
when x"3CB" => DATA <= x"39";
when x"3CC" => DATA <= x"F4";
when x"3CD" => DATA <= x"18";
when x"3CE" => DATA <= x"03";
when x"3CF" => DATA <= x"2A";
when x"3D0" => DATA <= x"AA";
when x"3D1" => DATA <= x"FC";
when x"3D2" => DATA <= x"ED";
when x"3D3" => DATA <= x"5B";
when x"3D4" => DATA <= x"AA";
when x"3D5" => DATA <= x"FC";
when x"3D6" => DATA <= x"3A";
when x"3D7" => DATA <= x"80";
when x"3D8" => DATA <= x"FF";
when x"3D9" => DATA <= x"CB";
when x"3DA" => DATA <= x"7F";
when x"3DB" => DATA <= x"C2";
when x"3DC" => DATA <= x"F7";
when x"3DD" => DATA <= x"F2";
when x"3DE" => DATA <= x"CD";
when x"3DF" => DATA <= x"E7";
when x"3E0" => DATA <= x"FF";
when x"3E1" => DATA <= x"CD";
when x"3E2" => DATA <= x"71";
when x"3E3" => DATA <= x"F4";
when x"3E4" => DATA <= x"06";
when x"3E5" => DATA <= x"08";
when x"3E6" => DATA <= x"E5";
when x"3E7" => DATA <= x"CD";
when x"3E8" => DATA <= x"1D";
when x"3E9" => DATA <= x"F4";
when x"3EA" => DATA <= x"7E";
when x"3EB" => DATA <= x"CD";
when x"3EC" => DATA <= x"76";
when x"3ED" => DATA <= x"F4";
when x"3EE" => DATA <= x"23";
when x"3EF" => DATA <= x"10";
when x"3F0" => DATA <= x"F6";
when x"3F1" => DATA <= x"06";
when x"3F2" => DATA <= x"08";
when x"3F3" => DATA <= x"E1";
when x"3F4" => DATA <= x"CD";
when x"3F5" => DATA <= x"1D";
when x"3F6" => DATA <= x"F4";
when x"3F7" => DATA <= x"7E";
when x"3F8" => DATA <= x"CD";
when x"3F9" => DATA <= x"0D";
when x"3FA" => DATA <= x"F4";
when x"3FB" => DATA <= x"23";
when x"3FC" => DATA <= x"10";
when x"3FD" => DATA <= x"F9";
when x"3FE" => DATA <= x"CD";
when x"3FF" => DATA <= x"23";
when x"400" => DATA <= x"F4";
when x"401" => DATA <= x"D2";
when x"402" => DATA <= x"06";
when x"403" => DATA <= x"F4";
when x"404" => DATA <= x"18";
when x"405" => DATA <= x"D0";
when x"406" => DATA <= x"CD";
when x"407" => DATA <= x"E7";
when x"408" => DATA <= x"FF";
when x"409" => DATA <= x"D1";
when x"40A" => DATA <= x"C1";
when x"40B" => DATA <= x"F1";
when x"40C" => DATA <= x"C9";
when x"40D" => DATA <= x"FE";
when x"40E" => DATA <= x"20";
when x"40F" => DATA <= x"38";
when x"410" => DATA <= x"06";
when x"411" => DATA <= x"FE";
when x"412" => DATA <= x"7F";
when x"413" => DATA <= x"30";
when x"414" => DATA <= x"02";
when x"415" => DATA <= x"18";
when x"416" => DATA <= x"02";
when x"417" => DATA <= x"3E";
when x"418" => DATA <= x"2E";
when x"419" => DATA <= x"CD";
when x"41A" => DATA <= x"71";
when x"41B" => DATA <= x"F6";
when x"41C" => DATA <= x"C9";
when x"41D" => DATA <= x"3E";
when x"41E" => DATA <= x"20";
when x"41F" => DATA <= x"CD";
when x"420" => DATA <= x"71";
when x"421" => DATA <= x"F6";
when x"422" => DATA <= x"C9";
when x"423" => DATA <= x"E5";
when x"424" => DATA <= x"01";
when x"425" => DATA <= x"08";
when x"426" => DATA <= x"00";
when x"427" => DATA <= x"BF";
when x"428" => DATA <= x"ED";
when x"429" => DATA <= x"42";
when x"42A" => DATA <= x"30";
when x"42B" => DATA <= x"06";
when x"42C" => DATA <= x"21";
when x"42D" => DATA <= x"00";
when x"42E" => DATA <= x"00";
when x"42F" => DATA <= x"BF";
when x"430" => DATA <= x"18";
when x"431" => DATA <= x"02";
when x"432" => DATA <= x"E1";
when x"433" => DATA <= x"E5";
when x"434" => DATA <= x"2B";
when x"435" => DATA <= x"ED";
when x"436" => DATA <= x"52";
when x"437" => DATA <= x"E1";
when x"438" => DATA <= x"C9";
when x"439" => DATA <= x"22";
when x"43A" => DATA <= x"AC";
when x"43B" => DATA <= x"FC";
when x"43C" => DATA <= x"21";
when x"43D" => DATA <= x"00";
when x"43E" => DATA <= x"00";
when x"43F" => DATA <= x"1A";
when x"440" => DATA <= x"CB";
when x"441" => DATA <= x"77";
when x"442" => DATA <= x"28";
when x"443" => DATA <= x"02";
when x"444" => DATA <= x"E6";
when x"445" => DATA <= x"DF";
when x"446" => DATA <= x"FE";
when x"447" => DATA <= x"30";
when x"448" => DATA <= x"FA";
when x"449" => DATA <= x"6D";
when x"44A" => DATA <= x"F4";
when x"44B" => DATA <= x"FE";
when x"44C" => DATA <= x"47";
when x"44D" => DATA <= x"F2";
when x"44E" => DATA <= x"6D";
when x"44F" => DATA <= x"F4";
when x"450" => DATA <= x"FE";
when x"451" => DATA <= x"3A";
when x"452" => DATA <= x"38";
when x"453" => DATA <= x"07";
when x"454" => DATA <= x"FE";
when x"455" => DATA <= x"41";
when x"456" => DATA <= x"FA";
when x"457" => DATA <= x"6D";
when x"458" => DATA <= x"F4";
when x"459" => DATA <= x"C6";
when x"45A" => DATA <= x"09";
when x"45B" => DATA <= x"E6";
when x"45C" => DATA <= x"0F";
when x"45D" => DATA <= x"29";
when x"45E" => DATA <= x"29";
when x"45F" => DATA <= x"29";
when x"460" => DATA <= x"29";
when x"461" => DATA <= x"B5";
when x"462" => DATA <= x"6F";
when x"463" => DATA <= x"3E";
when x"464" => DATA <= x"01";
when x"465" => DATA <= x"B8";
when x"466" => DATA <= x"C8";
when x"467" => DATA <= x"13";
when x"468" => DATA <= x"22";
when x"469" => DATA <= x"AA";
when x"46A" => DATA <= x"FC";
when x"46B" => DATA <= x"18";
when x"46C" => DATA <= x"D2";
when x"46D" => DATA <= x"2A";
when x"46E" => DATA <= x"AC";
when x"46F" => DATA <= x"FC";
when x"470" => DATA <= x"C9";
when x"471" => DATA <= x"7C";
when x"472" => DATA <= x"CD";
when x"473" => DATA <= x"76";
when x"474" => DATA <= x"F4";
when x"475" => DATA <= x"7D";
when x"476" => DATA <= x"F5";
when x"477" => DATA <= x"0F";
when x"478" => DATA <= x"0F";
when x"479" => DATA <= x"0F";
when x"47A" => DATA <= x"0F";
when x"47B" => DATA <= x"CD";
when x"47C" => DATA <= x"7F";
when x"47D" => DATA <= x"F4";
when x"47E" => DATA <= x"F1";
when x"47F" => DATA <= x"E6";
when x"480" => DATA <= x"0F";
when x"481" => DATA <= x"C6";
when x"482" => DATA <= x"30";
when x"483" => DATA <= x"FE";
when x"484" => DATA <= x"3A";
when x"485" => DATA <= x"FA";
when x"486" => DATA <= x"71";
when x"487" => DATA <= x"F6";
when x"488" => DATA <= x"C6";
when x"489" => DATA <= x"07";
when x"48A" => DATA <= x"C3";
when x"48B" => DATA <= x"71";
when x"48C" => DATA <= x"F6";
when x"48D" => DATA <= x"13";
when x"48E" => DATA <= x"1A";
when x"48F" => DATA <= x"E6";
when x"490" => DATA <= x"DF";
when x"491" => DATA <= x"FE";
when x"492" => DATA <= x"50";
when x"493" => DATA <= x"C2";
when x"494" => DATA <= x"CC";
when x"495" => DATA <= x"F7";
when x"496" => DATA <= x"13";
when x"497" => DATA <= x"1A";
when x"498" => DATA <= x"E6";
when x"499" => DATA <= x"DF";
when x"49A" => DATA <= x"FE";
when x"49B" => DATA <= x"4D";
when x"49C" => DATA <= x"C2";
when x"49D" => DATA <= x"CC";
when x"49E" => DATA <= x"F7";
when x"49F" => DATA <= x"CD";
when x"4A0" => DATA <= x"76";
when x"4A1" => DATA <= x"F8";
when x"4A2" => DATA <= x"FE";
when x"4A3" => DATA <= x"0D";
when x"4A4" => DATA <= x"C2";
when x"4A5" => DATA <= x"CC";
when x"4A6" => DATA <= x"F7";
when x"4A7" => DATA <= x"18";
when x"4A8" => DATA <= x"26";
when x"4A9" => DATA <= x"CD";
when x"4AA" => DATA <= x"0E";
when x"4AB" => DATA <= x"F6";
when x"4AC" => DATA <= x"49";
when x"4AD" => DATA <= x"6E";
when x"4AE" => DATA <= x"73";
when x"4AF" => DATA <= x"65";
when x"4B0" => DATA <= x"72";
when x"4B1" => DATA <= x"74";
when x"4B2" => DATA <= x"20";
when x"4B3" => DATA <= x"43";
when x"4B4" => DATA <= x"50";
when x"4B5" => DATA <= x"2F";
when x"4B6" => DATA <= x"4D";
when x"4B7" => DATA <= x"20";
when x"4B8" => DATA <= x"53";
when x"4B9" => DATA <= x"79";
when x"4BA" => DATA <= x"73";
when x"4BB" => DATA <= x"74";
when x"4BC" => DATA <= x"65";
when x"4BD" => DATA <= x"6D";
when x"4BE" => DATA <= x"20";
when x"4BF" => DATA <= x"64";
when x"4C0" => DATA <= x"69";
when x"4C1" => DATA <= x"73";
when x"4C2" => DATA <= x"63";
when x"4C3" => DATA <= x"20";
when x"4C4" => DATA <= x"69";
when x"4C5" => DATA <= x"6E";
when x"4C6" => DATA <= x"20";
when x"4C7" => DATA <= x"64";
when x"4C8" => DATA <= x"72";
when x"4C9" => DATA <= x"69";
when x"4CA" => DATA <= x"76";
when x"4CB" => DATA <= x"65";
when x"4CC" => DATA <= x"20";
when x"4CD" => DATA <= x"41";
when x"4CE" => DATA <= x"00";
when x"4CF" => DATA <= x"3E";
when x"4D0" => DATA <= x"E5";
when x"4D1" => DATA <= x"21";
when x"4D2" => DATA <= x"01";
when x"4D3" => DATA <= x"00";
when x"4D4" => DATA <= x"CD";
when x"4D5" => DATA <= x"8E";
when x"4D6" => DATA <= x"F8";
when x"4D7" => DATA <= x"21";
when x"4D8" => DATA <= x"82";
when x"4D9" => DATA <= x"F5";
when x"4DA" => DATA <= x"CD";
when x"4DB" => DATA <= x"4A";
when x"4DC" => DATA <= x"F5";
when x"4DD" => DATA <= x"21";
when x"4DE" => DATA <= x"00";
when x"4DF" => DATA <= x"EB";
when x"4E0" => DATA <= x"11";
when x"4E1" => DATA <= x"F0";
when x"4E2" => DATA <= x"EA";
when x"4E3" => DATA <= x"01";
when x"4E4" => DATA <= x"F0";
when x"4E5" => DATA <= x"00";
when x"4E6" => DATA <= x"ED";
when x"4E7" => DATA <= x"B0";
when x"4E8" => DATA <= x"21";
when x"4E9" => DATA <= x"F0";
when x"4EA" => DATA <= x"EB";
when x"4EB" => DATA <= x"11";
when x"4EC" => DATA <= x"E0";
when x"4ED" => DATA <= x"EB";
when x"4EE" => DATA <= x"01";
when x"4EF" => DATA <= x"00";
when x"4F0" => DATA <= x"06";
when x"4F1" => DATA <= x"ED";
when x"4F2" => DATA <= x"B0";
when x"4F3" => DATA <= x"CD";
when x"4F4" => DATA <= x"3B";
when x"4F5" => DATA <= x"F5";
when x"4F6" => DATA <= x"3A";
when x"4F7" => DATA <= x"00";
when x"4F8" => DATA <= x"D4";
when x"4F9" => DATA <= x"FE";
when x"4FA" => DATA <= x"C3";
when x"4FB" => DATA <= x"CA";
when x"4FC" => DATA <= x"22";
when x"4FD" => DATA <= x"F5";
when x"4FE" => DATA <= x"3E";
when x"4FF" => DATA <= x"E5";
when x"500" => DATA <= x"21";
when x"501" => DATA <= x"00";
when x"502" => DATA <= x"00";
when x"503" => DATA <= x"CD";
when x"504" => DATA <= x"8E";
when x"505" => DATA <= x"F8";
when x"506" => DATA <= x"CD";
when x"507" => DATA <= x"E7";
when x"508" => DATA <= x"FF";
when x"509" => DATA <= x"FF";
when x"50A" => DATA <= x"C8";
when x"50B" => DATA <= x"4E";
when x"50C" => DATA <= x"6F";
when x"50D" => DATA <= x"74";
when x"50E" => DATA <= x"20";
when x"50F" => DATA <= x"61";
when x"510" => DATA <= x"20";
when x"511" => DATA <= x"43";
when x"512" => DATA <= x"50";
when x"513" => DATA <= x"2F";
when x"514" => DATA <= x"4D";
when x"515" => DATA <= x"20";
when x"516" => DATA <= x"53";
when x"517" => DATA <= x"79";
when x"518" => DATA <= x"73";
when x"519" => DATA <= x"74";
when x"51A" => DATA <= x"65";
when x"51B" => DATA <= x"6D";
when x"51C" => DATA <= x"20";
when x"51D" => DATA <= x"64";
when x"51E" => DATA <= x"69";
when x"51F" => DATA <= x"73";
when x"520" => DATA <= x"63";
when x"521" => DATA <= x"00";
when x"522" => DATA <= x"21";
when x"523" => DATA <= x"B2";
when x"524" => DATA <= x"FA";
when x"525" => DATA <= x"22";
when x"526" => DATA <= x"FA";
when x"527" => DATA <= x"FF";
when x"528" => DATA <= x"3E";
when x"529" => DATA <= x"90";
when x"52A" => DATA <= x"32";
when x"52B" => DATA <= x"A3";
when x"52C" => DATA <= x"FC";
when x"52D" => DATA <= x"21";
when x"52E" => DATA <= x"00";
when x"52F" => DATA <= x"01";
when x"530" => DATA <= x"CD";
when x"531" => DATA <= x"8E";
when x"532" => DATA <= x"F8";
when x"533" => DATA <= x"CD";
when x"534" => DATA <= x"0E";
when x"535" => DATA <= x"F6";
when x"536" => DATA <= x"16";
when x"537" => DATA <= x"00";
when x"538" => DATA <= x"C3";
when x"539" => DATA <= x"00";
when x"53A" => DATA <= x"EA";
when x"53B" => DATA <= x"21";
when x"53C" => DATA <= x"8D";
when x"53D" => DATA <= x"F5";
when x"53E" => DATA <= x"CD";
when x"53F" => DATA <= x"4A";
when x"540" => DATA <= x"F5";
when x"541" => DATA <= x"21";
when x"542" => DATA <= x"98";
when x"543" => DATA <= x"F5";
when x"544" => DATA <= x"CD";
when x"545" => DATA <= x"4A";
when x"546" => DATA <= x"F5";
when x"547" => DATA <= x"21";
when x"548" => DATA <= x"A3";
when x"549" => DATA <= x"F5";
when x"54A" => DATA <= x"CD";
when x"54B" => DATA <= x"5C";
when x"54C" => DATA <= x"F5";
when x"54D" => DATA <= x"B7";
when x"54E" => DATA <= x"C8";
when x"54F" => DATA <= x"FF";
when x"550" => DATA <= x"C7";
when x"551" => DATA <= x"44";
when x"552" => DATA <= x"69";
when x"553" => DATA <= x"73";
when x"554" => DATA <= x"63";
when x"555" => DATA <= x"20";
when x"556" => DATA <= x"66";
when x"557" => DATA <= x"61";
when x"558" => DATA <= x"75";
when x"559" => DATA <= x"6C";
when x"55A" => DATA <= x"74";
when x"55B" => DATA <= x"00";
when x"55C" => DATA <= x"06";
when x"55D" => DATA <= x"04";
when x"55E" => DATA <= x"48";
when x"55F" => DATA <= x"06";
when x"560" => DATA <= x"0A";
when x"561" => DATA <= x"3E";
when x"562" => DATA <= x"7F";
when x"563" => DATA <= x"CD";
when x"564" => DATA <= x"EF";
when x"565" => DATA <= x"F8";
when x"566" => DATA <= x"11";
when x"567" => DATA <= x"0A";
when x"568" => DATA <= x"00";
when x"569" => DATA <= x"EB";
when x"56A" => DATA <= x"19";
when x"56B" => DATA <= x"7E";
when x"56C" => DATA <= x"32";
when x"56D" => DATA <= x"A7";
when x"56E" => DATA <= x"FC";
when x"56F" => DATA <= x"EB";
when x"570" => DATA <= x"FE";
when x"571" => DATA <= x"12";
when x"572" => DATA <= x"C8";
when x"573" => DATA <= x"B7";
when x"574" => DATA <= x"C8";
when x"575" => DATA <= x"10";
when x"576" => DATA <= x"EA";
when x"577" => DATA <= x"7E";
when x"578" => DATA <= x"CD";
when x"579" => DATA <= x"1B";
when x"57A" => DATA <= x"F6";
when x"57B" => DATA <= x"41";
when x"57C" => DATA <= x"10";
when x"57D" => DATA <= x"E0";
when x"57E" => DATA <= x"3A";
when x"57F" => DATA <= x"A7";
when x"580" => DATA <= x"FC";
when x"581" => DATA <= x"C9";
when x"582" => DATA <= x"00";
when x"583" => DATA <= x"F0";
when x"584" => DATA <= x"E9";
when x"585" => DATA <= x"00";
when x"586" => DATA <= x"00";
when x"587" => DATA <= x"03";
when x"588" => DATA <= x"53";
when x"589" => DATA <= x"00";
when x"58A" => DATA <= x"00";
when x"58B" => DATA <= x"28";
when x"58C" => DATA <= x"FF";
when x"58D" => DATA <= x"00";
when x"58E" => DATA <= x"00";
when x"58F" => DATA <= x"D4";
when x"590" => DATA <= x"00";
when x"591" => DATA <= x"00";
when x"592" => DATA <= x"03";
when x"593" => DATA <= x"53";
when x"594" => DATA <= x"00";
when x"595" => DATA <= x"08";
when x"596" => DATA <= x"22";
when x"597" => DATA <= x"FF";
when x"598" => DATA <= x"00";
when x"599" => DATA <= x"00";
when x"59A" => DATA <= x"D6";
when x"59B" => DATA <= x"00";
when x"59C" => DATA <= x"00";
when x"59D" => DATA <= x"03";
when x"59E" => DATA <= x"53";
when x"59F" => DATA <= x"01";
when x"5A0" => DATA <= x"00";
when x"5A1" => DATA <= x"2A";
when x"5A2" => DATA <= x"FF";
when x"5A3" => DATA <= x"00";
when x"5A4" => DATA <= x"00";
when x"5A5" => DATA <= x"E0";
when x"5A6" => DATA <= x"00";
when x"5A7" => DATA <= x"00";
when x"5A8" => DATA <= x"03";
when x"5A9" => DATA <= x"53";
when x"5AA" => DATA <= x"02";
when x"5AB" => DATA <= x"00";
when x"5AC" => DATA <= x"2A";
when x"5AD" => DATA <= x"FF";
when x"5AE" => DATA <= x"F3";
when x"5AF" => DATA <= x"21";
when x"5B0" => DATA <= x"00";
when x"5B1" => DATA <= x"25";
when x"5B2" => DATA <= x"11";
when x"5B3" => DATA <= x"30";
when x"5B4" => DATA <= x"FD";
when x"5B5" => DATA <= x"06";
when x"5B6" => DATA <= x"AA";
when x"5B7" => DATA <= x"CD";
when x"5B8" => DATA <= x"F3";
when x"5B9" => DATA <= x"F5";
when x"5BA" => DATA <= x"21";
when x"5BB" => DATA <= x"00";
when x"5BC" => DATA <= x"02";
when x"5BD" => DATA <= x"11";
when x"5BE" => DATA <= x"DC";
when x"5BF" => DATA <= x"FD";
when x"5C0" => DATA <= x"06";
when x"5C1" => DATA <= x"02";
when x"5C2" => DATA <= x"CD";
when x"5C3" => DATA <= x"DD";
when x"5C4" => DATA <= x"F5";
when x"5C5" => DATA <= x"21";
when x"5C6" => DATA <= x"03";
when x"5C7" => DATA <= x"25";
when x"5C8" => DATA <= x"11";
when x"5C9" => DATA <= x"DC";
when x"5CA" => DATA <= x"FD";
when x"5CB" => DATA <= x"06";
when x"5CC" => DATA <= x"02";
when x"5CD" => DATA <= x"CD";
when x"5CE" => DATA <= x"F3";
when x"5CF" => DATA <= x"F5";
when x"5D0" => DATA <= x"21";
when x"5D1" => DATA <= x"00";
when x"5D2" => DATA <= x"02";
when x"5D3" => DATA <= x"11";
when x"5D4" => DATA <= x"DA";
when x"5D5" => DATA <= x"FD";
when x"5D6" => DATA <= x"06";
when x"5D7" => DATA <= x"02";
when x"5D8" => DATA <= x"CD";
when x"5D9" => DATA <= x"F3";
when x"5DA" => DATA <= x"F5";
when x"5DB" => DATA <= x"FB";
when x"5DC" => DATA <= x"C9";
when x"5DD" => DATA <= x"22";
when x"5DE" => DATA <= x"09";
when x"5DF" => DATA <= x"F6";
when x"5E0" => DATA <= x"E5";
when x"5E1" => DATA <= x"21";
when x"5E2" => DATA <= x"09";
when x"5E3" => DATA <= x"F6";
when x"5E4" => DATA <= x"3E";
when x"5E5" => DATA <= x"05";
when x"5E6" => DATA <= x"CD";
when x"5E7" => DATA <= x"F1";
when x"5E8" => DATA <= x"FF";
when x"5E9" => DATA <= x"3A";
when x"5EA" => DATA <= x"0D";
when x"5EB" => DATA <= x"F6";
when x"5EC" => DATA <= x"12";
when x"5ED" => DATA <= x"13";
when x"5EE" => DATA <= x"E1";
when x"5EF" => DATA <= x"23";
when x"5F0" => DATA <= x"10";
when x"5F1" => DATA <= x"EB";
when x"5F2" => DATA <= x"C9";
when x"5F3" => DATA <= x"22";
when x"5F4" => DATA <= x"09";
when x"5F5" => DATA <= x"F6";
when x"5F6" => DATA <= x"1A";
when x"5F7" => DATA <= x"32";
when x"5F8" => DATA <= x"0D";
when x"5F9" => DATA <= x"F6";
when x"5FA" => DATA <= x"E5";
when x"5FB" => DATA <= x"21";
when x"5FC" => DATA <= x"09";
when x"5FD" => DATA <= x"F6";
when x"5FE" => DATA <= x"3E";
when x"5FF" => DATA <= x"06";
when x"600" => DATA <= x"CD";
when x"601" => DATA <= x"F1";
when x"602" => DATA <= x"FF";
when x"603" => DATA <= x"13";
when x"604" => DATA <= x"E1";
when x"605" => DATA <= x"23";
when x"606" => DATA <= x"10";
when x"607" => DATA <= x"EB";
when x"608" => DATA <= x"C9";
when x"609" => DATA <= x"00";
when x"60A" => DATA <= x"00";
when x"60B" => DATA <= x"00";
when x"60C" => DATA <= x"00";
when x"60D" => DATA <= x"00";
when x"60E" => DATA <= x"E3";
when x"60F" => DATA <= x"F5";
when x"610" => DATA <= x"7E";
when x"611" => DATA <= x"CD";
when x"612" => DATA <= x"E3";
when x"613" => DATA <= x"FF";
when x"614" => DATA <= x"23";
when x"615" => DATA <= x"B7";
when x"616" => DATA <= x"20";
when x"617" => DATA <= x"F8";
when x"618" => DATA <= x"F1";
when x"619" => DATA <= x"E3";
when x"61A" => DATA <= x"C9";
when x"61B" => DATA <= x"F5";
when x"61C" => DATA <= x"E5";
when x"61D" => DATA <= x"32";
when x"61E" => DATA <= x"36";
when x"61F" => DATA <= x"F6";
when x"620" => DATA <= x"21";
when x"621" => DATA <= x"36";
when x"622" => DATA <= x"F6";
when x"623" => DATA <= x"3E";
when x"624" => DATA <= x"7F";
when x"625" => DATA <= x"ED";
when x"626" => DATA <= x"73";
when x"627" => DATA <= x"A5";
when x"628" => DATA <= x"FC";
when x"629" => DATA <= x"31";
when x"62A" => DATA <= x"80";
when x"62B" => DATA <= x"FF";
when x"62C" => DATA <= x"CD";
when x"62D" => DATA <= x"EF";
when x"62E" => DATA <= x"F8";
when x"62F" => DATA <= x"ED";
when x"630" => DATA <= x"7B";
when x"631" => DATA <= x"A5";
when x"632" => DATA <= x"FC";
when x"633" => DATA <= x"E1";
when x"634" => DATA <= x"F1";
when x"635" => DATA <= x"C9";
when x"636" => DATA <= x"00";
when x"637" => DATA <= x"00";
when x"638" => DATA <= x"00";
when x"639" => DATA <= x"00";
when x"63A" => DATA <= x"00";
when x"63B" => DATA <= x"01";
when x"63C" => DATA <= x"69";
when x"63D" => DATA <= x"00";
when x"63E" => DATA <= x"00";
when x"63F" => DATA <= x"E5";
when x"640" => DATA <= x"21";
when x"641" => DATA <= x"FF";
when x"642" => DATA <= x"FF";
when x"643" => DATA <= x"3E";
when x"644" => DATA <= x"80";
when x"645" => DATA <= x"CD";
when x"646" => DATA <= x"8E";
when x"647" => DATA <= x"F8";
when x"648" => DATA <= x"7D";
when x"649" => DATA <= x"B7";
when x"64A" => DATA <= x"28";
when x"64B" => DATA <= x"02";
when x"64C" => DATA <= x"18";
when x"64D" => DATA <= x"0C";
when x"64E" => DATA <= x"3E";
when x"64F" => DATA <= x"D8";
when x"650" => DATA <= x"21";
when x"651" => DATA <= x"00";
when x"652" => DATA <= x"FF";
when x"653" => DATA <= x"CD";
when x"654" => DATA <= x"8E";
when x"655" => DATA <= x"F8";
when x"656" => DATA <= x"7D";
when x"657" => DATA <= x"B7";
when x"658" => DATA <= x"28";
when x"659" => DATA <= x"02";
when x"65A" => DATA <= x"3E";
when x"65B" => DATA <= x"FF";
when x"65C" => DATA <= x"E1";
when x"65D" => DATA <= x"C9";
when x"65E" => DATA <= x"C5";
when x"65F" => DATA <= x"D5";
when x"660" => DATA <= x"E5";
when x"661" => DATA <= x"21";
when x"662" => DATA <= x"BC";
when x"663" => DATA <= x"FF";
when x"664" => DATA <= x"11";
when x"665" => DATA <= x"38";
when x"666" => DATA <= x"00";
when x"667" => DATA <= x"01";
when x"668" => DATA <= x"03";
when x"669" => DATA <= x"00";
when x"66A" => DATA <= x"ED";
when x"66B" => DATA <= x"B0";
when x"66C" => DATA <= x"E1";
when x"66D" => DATA <= x"D1";
when x"66E" => DATA <= x"C1";
when x"66F" => DATA <= x"C9";
when x"670" => DATA <= x"C9";
when x"671" => DATA <= x"F5";
when x"672" => DATA <= x"DB";
when x"673" => DATA <= x"00";
when x"674" => DATA <= x"CB";
when x"675" => DATA <= x"77";
when x"676" => DATA <= x"28";
when x"677" => DATA <= x"FA";
when x"678" => DATA <= x"F1";
when x"679" => DATA <= x"D3";
when x"67A" => DATA <= x"01";
when x"67B" => DATA <= x"C9";
when x"67C" => DATA <= x"DB";
when x"67D" => DATA <= x"00";
when x"67E" => DATA <= x"CB";
when x"67F" => DATA <= x"7F";
when x"680" => DATA <= x"20";
when x"681" => DATA <= x"0B";
when x"682" => DATA <= x"DB";
when x"683" => DATA <= x"06";
when x"684" => DATA <= x"CB";
when x"685" => DATA <= x"7F";
when x"686" => DATA <= x"28";
when x"687" => DATA <= x"F4";
when x"688" => DATA <= x"CD";
when x"689" => DATA <= x"0B";
when x"68A" => DATA <= x"FB";
when x"68B" => DATA <= x"18";
when x"68C" => DATA <= x"EF";
when x"68D" => DATA <= x"DB";
when x"68E" => DATA <= x"01";
when x"68F" => DATA <= x"C9";
when x"690" => DATA <= x"3E";
when x"691" => DATA <= x"00";
when x"692" => DATA <= x"CD";
when x"693" => DATA <= x"A3";
when x"694" => DATA <= x"F6";
when x"695" => DATA <= x"CD";
when x"696" => DATA <= x"9A";
when x"697" => DATA <= x"F6";
when x"698" => DATA <= x"CB";
when x"699" => DATA <= x"27";
when x"69A" => DATA <= x"DB";
when x"69B" => DATA <= x"02";
when x"69C" => DATA <= x"CB";
when x"69D" => DATA <= x"7F";
when x"69E" => DATA <= x"28";
when x"69F" => DATA <= x"FA";
when x"6A0" => DATA <= x"DB";
when x"6A1" => DATA <= x"03";
when x"6A2" => DATA <= x"C9";
when x"6A3" => DATA <= x"F5";
when x"6A4" => DATA <= x"DB";
when x"6A5" => DATA <= x"02";
when x"6A6" => DATA <= x"CB";
when x"6A7" => DATA <= x"77";
when x"6A8" => DATA <= x"28";
when x"6A9" => DATA <= x"FA";
when x"6AA" => DATA <= x"F1";
when x"6AB" => DATA <= x"D3";
when x"6AC" => DATA <= x"03";
when x"6AD" => DATA <= x"C9";
when x"6AE" => DATA <= x"DB";
when x"6AF" => DATA <= x"06";
when x"6B0" => DATA <= x"CB";
when x"6B1" => DATA <= x"7F";
when x"6B2" => DATA <= x"28";
when x"6B3" => DATA <= x"FA";
when x"6B4" => DATA <= x"DB";
when x"6B5" => DATA <= x"07";
when x"6B6" => DATA <= x"C9";
when x"6B7" => DATA <= x"F5";
when x"6B8" => DATA <= x"C5";
when x"6B9" => DATA <= x"D5";
when x"6BA" => DATA <= x"54";
when x"6BB" => DATA <= x"5D";
when x"6BC" => DATA <= x"CD";
when x"6BD" => DATA <= x"7E";
when x"6BE" => DATA <= x"F8";
when x"6BF" => DATA <= x"CD";
when x"6C0" => DATA <= x"77";
when x"6C1" => DATA <= x"F8";
when x"6C2" => DATA <= x"FE";
when x"6C3" => DATA <= x"2A";
when x"6C4" => DATA <= x"28";
when x"6C5" => DATA <= x"F6";
when x"6C6" => DATA <= x"E6";
when x"6C7" => DATA <= x"DF";
when x"6C8" => DATA <= x"FE";
when x"6C9" => DATA <= x"48";
when x"6CA" => DATA <= x"28";
when x"6CB" => DATA <= x"20";
when x"6CC" => DATA <= x"4F";
when x"6CD" => DATA <= x"3A";
when x"6CE" => DATA <= x"A3";
when x"6CF" => DATA <= x"FC";
when x"6D0" => DATA <= x"B7";
when x"6D1" => DATA <= x"79";
when x"6D2" => DATA <= x"C2";
when x"6D3" => DATA <= x"CC";
when x"6D4" => DATA <= x"F7";
when x"6D5" => DATA <= x"FE";
when x"6D6" => DATA <= x"47";
when x"6D7" => DATA <= x"CA";
when x"6D8" => DATA <= x"08";
when x"6D9" => DATA <= x"F3";
when x"6DA" => DATA <= x"FE";
when x"6DB" => DATA <= x"44";
when x"6DC" => DATA <= x"CA";
when x"6DD" => DATA <= x"B3";
when x"6DE" => DATA <= x"F3";
when x"6DF" => DATA <= x"FE";
when x"6E0" => DATA <= x"53";
when x"6E1" => DATA <= x"CA";
when x"6E2" => DATA <= x"30";
when x"6E3" => DATA <= x"F3";
when x"6E4" => DATA <= x"FE";
when x"6E5" => DATA <= x"43";
when x"6E6" => DATA <= x"CA";
when x"6E7" => DATA <= x"8D";
when x"6E8" => DATA <= x"F4";
when x"6E9" => DATA <= x"C3";
when x"6EA" => DATA <= x"CC";
when x"6EB" => DATA <= x"F7";
when x"6EC" => DATA <= x"13";
when x"6ED" => DATA <= x"1A";
when x"6EE" => DATA <= x"FE";
when x"6EF" => DATA <= x"2E";
when x"6F0" => DATA <= x"28";
when x"6F1" => DATA <= x"2E";
when x"6F2" => DATA <= x"E6";
when x"6F3" => DATA <= x"DF";
when x"6F4" => DATA <= x"FE";
when x"6F5" => DATA <= x"45";
when x"6F6" => DATA <= x"C2";
when x"6F7" => DATA <= x"CC";
when x"6F8" => DATA <= x"F7";
when x"6F9" => DATA <= x"13";
when x"6FA" => DATA <= x"1A";
when x"6FB" => DATA <= x"FE";
when x"6FC" => DATA <= x"2E";
when x"6FD" => DATA <= x"28";
when x"6FE" => DATA <= x"21";
when x"6FF" => DATA <= x"E6";
when x"700" => DATA <= x"DF";
when x"701" => DATA <= x"FE";
when x"702" => DATA <= x"4C";
when x"703" => DATA <= x"C2";
when x"704" => DATA <= x"CC";
when x"705" => DATA <= x"F7";
when x"706" => DATA <= x"13";
when x"707" => DATA <= x"1A";
when x"708" => DATA <= x"FE";
when x"709" => DATA <= x"2E";
when x"70A" => DATA <= x"28";
when x"70B" => DATA <= x"14";
when x"70C" => DATA <= x"E6";
when x"70D" => DATA <= x"DF";
when x"70E" => DATA <= x"FE";
when x"70F" => DATA <= x"50";
when x"710" => DATA <= x"C2";
when x"711" => DATA <= x"CC";
when x"712" => DATA <= x"F7";
when x"713" => DATA <= x"13";
when x"714" => DATA <= x"1A";
when x"715" => DATA <= x"CD";
when x"716" => DATA <= x"6D";
when x"717" => DATA <= x"F8";
when x"718" => DATA <= x"D2";
when x"719" => DATA <= x"CC";
when x"71A" => DATA <= x"F7";
when x"71B" => DATA <= x"CD";
when x"71C" => DATA <= x"77";
when x"71D" => DATA <= x"F8";
when x"71E" => DATA <= x"18";
when x"71F" => DATA <= x"03";
when x"720" => DATA <= x"CD";
when x"721" => DATA <= x"76";
when x"722" => DATA <= x"F8";
when x"723" => DATA <= x"CD";
when x"724" => DATA <= x"B3";
when x"725" => DATA <= x"FF";
when x"726" => DATA <= x"0D";
when x"727" => DATA <= x"5A";
when x"728" => DATA <= x"38";
when x"729" => DATA <= x"30";
when x"72A" => DATA <= x"20";
when x"72B" => DATA <= x"54";
when x"72C" => DATA <= x"55";
when x"72D" => DATA <= x"42";
when x"72E" => DATA <= x"45";
when x"72F" => DATA <= x"20";
when x"730" => DATA <= x"31";
when x"731" => DATA <= x"2E";
when x"732" => DATA <= x"32";
when x"733" => DATA <= x"31";
when x"734" => DATA <= x"0D";
when x"735" => DATA <= x"00";
when x"736" => DATA <= x"4F";
when x"737" => DATA <= x"3A";
when x"738" => DATA <= x"A3";
when x"739" => DATA <= x"FC";
when x"73A" => DATA <= x"B7";
when x"73B" => DATA <= x"79";
when x"73C" => DATA <= x"C2";
when x"73D" => DATA <= x"CC";
when x"73E" => DATA <= x"F7";
when x"73F" => DATA <= x"FE";
when x"740" => DATA <= x"0D";
when x"741" => DATA <= x"28";
when x"742" => DATA <= x"29";
when x"743" => DATA <= x"E6";
when x"744" => DATA <= x"DF";
when x"745" => DATA <= x"FE";
when x"746" => DATA <= x"4D";
when x"747" => DATA <= x"28";
when x"748" => DATA <= x"09";
when x"749" => DATA <= x"FE";
when x"74A" => DATA <= x"0D";
when x"74B" => DATA <= x"CA";
when x"74C" => DATA <= x"CC";
when x"74D" => DATA <= x"F7";
when x"74E" => DATA <= x"13";
when x"74F" => DATA <= x"1A";
when x"750" => DATA <= x"18";
when x"751" => DATA <= x"F1";
when x"752" => DATA <= x"13";
when x"753" => DATA <= x"1A";
when x"754" => DATA <= x"E6";
when x"755" => DATA <= x"DF";
when x"756" => DATA <= x"FE";
when x"757" => DATA <= x"4F";
when x"758" => DATA <= x"20";
when x"759" => DATA <= x"F4";
when x"75A" => DATA <= x"13";
when x"75B" => DATA <= x"1A";
when x"75C" => DATA <= x"E6";
when x"75D" => DATA <= x"DF";
when x"75E" => DATA <= x"FE";
when x"75F" => DATA <= x"4E";
when x"760" => DATA <= x"20";
when x"761" => DATA <= x"EC";
when x"762" => DATA <= x"13";
when x"763" => DATA <= x"1A";
when x"764" => DATA <= x"CD";
when x"765" => DATA <= x"6D";
when x"766" => DATA <= x"F8";
when x"767" => DATA <= x"D2";
when x"768" => DATA <= x"4E";
when x"769" => DATA <= x"F7";
when x"76A" => DATA <= x"18";
when x"76B" => DATA <= x"0C";
when x"76C" => DATA <= x"CD";
when x"76D" => DATA <= x"0E";
when x"76E" => DATA <= x"F6";
when x"76F" => DATA <= x"20";
when x"770" => DATA <= x"20";
when x"771" => DATA <= x"4D";
when x"772" => DATA <= x"4F";
when x"773" => DATA <= x"4E";
when x"774" => DATA <= x"0D";
when x"775" => DATA <= x"00";
when x"776" => DATA <= x"18";
when x"777" => DATA <= x"54";
when x"778" => DATA <= x"CD";
when x"779" => DATA <= x"0E";
when x"77A" => DATA <= x"F6";
when x"77B" => DATA <= x"20";
when x"77C" => DATA <= x"20";
when x"77D" => DATA <= x"43";
when x"77E" => DATA <= x"50";
when x"77F" => DATA <= x"4D";
when x"780" => DATA <= x"0D";
when x"781" => DATA <= x"20";
when x"782" => DATA <= x"20";
when x"783" => DATA <= x"44";
when x"784" => DATA <= x"75";
when x"785" => DATA <= x"6D";
when x"786" => DATA <= x"70";
when x"787" => DATA <= x"20";
when x"788" => DATA <= x"3C";
when x"789" => DATA <= x"73";
when x"78A" => DATA <= x"74";
when x"78B" => DATA <= x"61";
when x"78C" => DATA <= x"72";
when x"78D" => DATA <= x"74";
when x"78E" => DATA <= x"20";
when x"78F" => DATA <= x"61";
when x"790" => DATA <= x"64";
when x"791" => DATA <= x"64";
when x"792" => DATA <= x"72";
when x"793" => DATA <= x"65";
when x"794" => DATA <= x"73";
when x"795" => DATA <= x"73";
when x"796" => DATA <= x"3E";
when x"797" => DATA <= x"20";
when x"798" => DATA <= x"3C";
when x"799" => DATA <= x"65";
when x"79A" => DATA <= x"6E";
when x"79B" => DATA <= x"64";
when x"79C" => DATA <= x"20";
when x"79D" => DATA <= x"61";
when x"79E" => DATA <= x"64";
when x"79F" => DATA <= x"64";
when x"7A0" => DATA <= x"72";
when x"7A1" => DATA <= x"65";
when x"7A2" => DATA <= x"73";
when x"7A3" => DATA <= x"73";
when x"7A4" => DATA <= x"3E";
when x"7A5" => DATA <= x"0D";
when x"7A6" => DATA <= x"20";
when x"7A7" => DATA <= x"20";
when x"7A8" => DATA <= x"47";
when x"7A9" => DATA <= x"4F";
when x"7AA" => DATA <= x"20";
when x"7AB" => DATA <= x"3C";
when x"7AC" => DATA <= x"61";
when x"7AD" => DATA <= x"64";
when x"7AE" => DATA <= x"64";
when x"7AF" => DATA <= x"72";
when x"7B0" => DATA <= x"65";
when x"7B1" => DATA <= x"73";
when x"7B2" => DATA <= x"73";
when x"7B3" => DATA <= x"3E";
when x"7B4" => DATA <= x"0D";
when x"7B5" => DATA <= x"20";
when x"7B6" => DATA <= x"20";
when x"7B7" => DATA <= x"53";
when x"7B8" => DATA <= x"65";
when x"7B9" => DATA <= x"74";
when x"7BA" => DATA <= x"20";
when x"7BB" => DATA <= x"3C";
when x"7BC" => DATA <= x"73";
when x"7BD" => DATA <= x"74";
when x"7BE" => DATA <= x"61";
when x"7BF" => DATA <= x"72";
when x"7C0" => DATA <= x"74";
when x"7C1" => DATA <= x"20";
when x"7C2" => DATA <= x"61";
when x"7C3" => DATA <= x"64";
when x"7C4" => DATA <= x"64";
when x"7C5" => DATA <= x"72";
when x"7C6" => DATA <= x"65";
when x"7C7" => DATA <= x"73";
when x"7C8" => DATA <= x"73";
when x"7C9" => DATA <= x"3E";
when x"7CA" => DATA <= x"0D";
when x"7CB" => DATA <= x"00";
when x"7CC" => DATA <= x"3E";
when x"7CD" => DATA <= x"02";
when x"7CE" => DATA <= x"CD";
when x"7CF" => DATA <= x"A3";
when x"7D0" => DATA <= x"F6";
when x"7D1" => DATA <= x"CD";
when x"7D2" => DATA <= x"84";
when x"7D3" => DATA <= x"F8";
when x"7D4" => DATA <= x"CD";
when x"7D5" => DATA <= x"9A";
when x"7D6" => DATA <= x"F6";
when x"7D7" => DATA <= x"FE";
when x"7D8" => DATA <= x"80";
when x"7D9" => DATA <= x"28";
when x"7DA" => DATA <= x"04";
when x"7DB" => DATA <= x"D1";
when x"7DC" => DATA <= x"C1";
when x"7DD" => DATA <= x"F1";
when x"7DE" => DATA <= x"C9";
when x"7DF" => DATA <= x"3E";
when x"7E0" => DATA <= x"01";
when x"7E1" => DATA <= x"32";
when x"7E2" => DATA <= x"AF";
when x"7E3" => DATA <= x"FC";
when x"7E4" => DATA <= x"CD";
when x"7E5" => DATA <= x"EB";
when x"7E6" => DATA <= x"F7";
when x"7E7" => DATA <= x"D1";
when x"7E8" => DATA <= x"C1";
when x"7E9" => DATA <= x"F1";
when x"7EA" => DATA <= x"C9";
when x"7EB" => DATA <= x"2A";
when x"7EC" => DATA <= x"A8";
when x"7ED" => DATA <= x"FC";
when x"7EE" => DATA <= x"11";
when x"7EF" => DATA <= x"07";
when x"7F0" => DATA <= x"00";
when x"7F1" => DATA <= x"19";
when x"7F2" => DATA <= x"E5";
when x"7F3" => DATA <= x"7E";
when x"7F4" => DATA <= x"2A";
when x"7F5" => DATA <= x"A8";
when x"7F6" => DATA <= x"FC";
when x"7F7" => DATA <= x"5F";
when x"7F8" => DATA <= x"19";
when x"7F9" => DATA <= x"22";
when x"7FA" => DATA <= x"82";
when x"7FB" => DATA <= x"FF";
when x"7FC" => DATA <= x"7E";
when x"7FD" => DATA <= x"11";
when x"7FE" => DATA <= x"22";
when x"7FF" => DATA <= x"FF";
when x"800" => DATA <= x"06";
when x"801" => DATA <= x"04";
when x"802" => DATA <= x"1A";
when x"803" => DATA <= x"BE";
when x"804" => DATA <= x"20";
when x"805" => DATA <= x"20";
when x"806" => DATA <= x"23";
when x"807" => DATA <= x"13";
when x"808" => DATA <= x"10";
when x"809" => DATA <= x"F8";
when x"80A" => DATA <= x"E1";
when x"80B" => DATA <= x"2B";
when x"80C" => DATA <= x"3A";
when x"80D" => DATA <= x"AF";
when x"80E" => DATA <= x"FC";
when x"80F" => DATA <= x"B7";
when x"810" => DATA <= x"20";
when x"811" => DATA <= x"17";
when x"812" => DATA <= x"7E";
when x"813" => DATA <= x"E6";
when x"814" => DATA <= x"4F";
when x"815" => DATA <= x"FE";
when x"816" => DATA <= x"40";
when x"817" => DATA <= x"38";
when x"818" => DATA <= x"09";
when x"819" => DATA <= x"FE";
when x"81A" => DATA <= x"48";
when x"81B" => DATA <= x"20";
when x"81C" => DATA <= x"05";
when x"81D" => DATA <= x"BF";
when x"81E" => DATA <= x"2A";
when x"81F" => DATA <= x"A8";
when x"820" => DATA <= x"FC";
when x"821" => DATA <= x"E9";
when x"822" => DATA <= x"BF";
when x"823" => DATA <= x"C3";
when x"824" => DATA <= x"A9";
when x"825" => DATA <= x"F4";
when x"826" => DATA <= x"E1";
when x"827" => DATA <= x"18";
when x"828" => DATA <= x"F4";
when x"829" => DATA <= x"AF";
when x"82A" => DATA <= x"32";
when x"82B" => DATA <= x"AF";
when x"82C" => DATA <= x"FC";
when x"82D" => DATA <= x"7E";
when x"82E" => DATA <= x"E6";
when x"82F" => DATA <= x"4F";
when x"830" => DATA <= x"FE";
when x"831" => DATA <= x"40";
when x"832" => DATA <= x"38";
when x"833" => DATA <= x"09";
when x"834" => DATA <= x"FE";
when x"835" => DATA <= x"48";
when x"836" => DATA <= x"20";
when x"837" => DATA <= x"1E";
when x"838" => DATA <= x"3E";
when x"839" => DATA <= x"01";
when x"83A" => DATA <= x"18";
when x"83B" => DATA <= x"E1";
when x"83C" => DATA <= x"00";
when x"83D" => DATA <= x"FF";
when x"83E" => DATA <= x"F9";
when x"83F" => DATA <= x"54";
when x"840" => DATA <= x"68";
when x"841" => DATA <= x"69";
when x"842" => DATA <= x"73";
when x"843" => DATA <= x"20";
when x"844" => DATA <= x"69";
when x"845" => DATA <= x"73";
when x"846" => DATA <= x"20";
when x"847" => DATA <= x"6E";
when x"848" => DATA <= x"6F";
when x"849" => DATA <= x"74";
when x"84A" => DATA <= x"20";
when x"84B" => DATA <= x"61";
when x"84C" => DATA <= x"20";
when x"84D" => DATA <= x"6C";
when x"84E" => DATA <= x"61";
when x"84F" => DATA <= x"6E";
when x"850" => DATA <= x"67";
when x"851" => DATA <= x"75";
when x"852" => DATA <= x"61";
when x"853" => DATA <= x"67";
when x"854" => DATA <= x"65";
when x"855" => DATA <= x"00";
when x"856" => DATA <= x"FF";
when x"857" => DATA <= x"F9";
when x"858" => DATA <= x"54";
when x"859" => DATA <= x"68";
when x"85A" => DATA <= x"69";
when x"85B" => DATA <= x"73";
when x"85C" => DATA <= x"20";
when x"85D" => DATA <= x"69";
when x"85E" => DATA <= x"73";
when x"85F" => DATA <= x"20";
when x"860" => DATA <= x"6E";
when x"861" => DATA <= x"6F";
when x"862" => DATA <= x"74";
when x"863" => DATA <= x"20";
when x"864" => DATA <= x"5A";
when x"865" => DATA <= x"38";
when x"866" => DATA <= x"30";
when x"867" => DATA <= x"20";
when x"868" => DATA <= x"63";
when x"869" => DATA <= x"6F";
when x"86A" => DATA <= x"64";
when x"86B" => DATA <= x"65";
when x"86C" => DATA <= x"00";
when x"86D" => DATA <= x"E6";
when x"86E" => DATA <= x"DF";
when x"86F" => DATA <= x"FE";
when x"870" => DATA <= x"41";
when x"871" => DATA <= x"D8";
when x"872" => DATA <= x"FE";
when x"873" => DATA <= x"5B";
when x"874" => DATA <= x"3F";
when x"875" => DATA <= x"C9";
when x"876" => DATA <= x"13";
when x"877" => DATA <= x"1A";
when x"878" => DATA <= x"FE";
when x"879" => DATA <= x"20";
when x"87A" => DATA <= x"28";
when x"87B" => DATA <= x"FA";
when x"87C" => DATA <= x"C9";
when x"87D" => DATA <= x"13";
when x"87E" => DATA <= x"1A";
when x"87F" => DATA <= x"FE";
when x"880" => DATA <= x"2A";
when x"881" => DATA <= x"28";
when x"882" => DATA <= x"FA";
when x"883" => DATA <= x"C9";
when x"884" => DATA <= x"7E";
when x"885" => DATA <= x"CD";
when x"886" => DATA <= x"A3";
when x"887" => DATA <= x"F6";
when x"888" => DATA <= x"23";
when x"889" => DATA <= x"FE";
when x"88A" => DATA <= x"0D";
when x"88B" => DATA <= x"20";
when x"88C" => DATA <= x"F7";
when x"88D" => DATA <= x"C9";
when x"88E" => DATA <= x"FE";
when x"88F" => DATA <= x"80";
when x"890" => DATA <= x"30";
when x"891" => DATA <= x"15";
when x"892" => DATA <= x"F5";
when x"893" => DATA <= x"3E";
when x"894" => DATA <= x"04";
when x"895" => DATA <= x"CD";
when x"896" => DATA <= x"A3";
when x"897" => DATA <= x"F6";
when x"898" => DATA <= x"7D";
when x"899" => DATA <= x"CD";
when x"89A" => DATA <= x"A3";
when x"89B" => DATA <= x"F6";
when x"89C" => DATA <= x"F1";
when x"89D" => DATA <= x"F5";
when x"89E" => DATA <= x"CD";
when x"89F" => DATA <= x"A3";
when x"8A0" => DATA <= x"F6";
when x"8A1" => DATA <= x"CD";
when x"8A2" => DATA <= x"9A";
when x"8A3" => DATA <= x"F6";
when x"8A4" => DATA <= x"6F";
when x"8A5" => DATA <= x"F1";
when x"8A6" => DATA <= x"C9";
when x"8A7" => DATA <= x"FE";
when x"8A8" => DATA <= x"82";
when x"8A9" => DATA <= x"28";
when x"8AA" => DATA <= x"31";
when x"8AB" => DATA <= x"FE";
when x"8AC" => DATA <= x"83";
when x"8AD" => DATA <= x"28";
when x"8AE" => DATA <= x"31";
when x"8AF" => DATA <= x"FE";
when x"8B0" => DATA <= x"84";
when x"8B1" => DATA <= x"28";
when x"8B2" => DATA <= x"31";
when x"8B3" => DATA <= x"F5";
when x"8B4" => DATA <= x"3E";
when x"8B5" => DATA <= x"06";
when x"8B6" => DATA <= x"CD";
when x"8B7" => DATA <= x"A3";
when x"8B8" => DATA <= x"F6";
when x"8B9" => DATA <= x"7D";
when x"8BA" => DATA <= x"CD";
when x"8BB" => DATA <= x"A3";
when x"8BC" => DATA <= x"F6";
when x"8BD" => DATA <= x"7C";
when x"8BE" => DATA <= x"CD";
when x"8BF" => DATA <= x"A3";
when x"8C0" => DATA <= x"F6";
when x"8C1" => DATA <= x"F1";
when x"8C2" => DATA <= x"F5";
when x"8C3" => DATA <= x"CD";
when x"8C4" => DATA <= x"A3";
when x"8C5" => DATA <= x"F6";
when x"8C6" => DATA <= x"FE";
when x"8C7" => DATA <= x"9D";
when x"8C8" => DATA <= x"28";
when x"8C9" => DATA <= x"10";
when x"8CA" => DATA <= x"CD";
when x"8CB" => DATA <= x"9A";
when x"8CC" => DATA <= x"F6";
when x"8CD" => DATA <= x"6F";
when x"8CE" => DATA <= x"F1";
when x"8CF" => DATA <= x"CB";
when x"8D0" => DATA <= x"25";
when x"8D1" => DATA <= x"F5";
when x"8D2" => DATA <= x"CD";
when x"8D3" => DATA <= x"9A";
when x"8D4" => DATA <= x"F6";
when x"8D5" => DATA <= x"67";
when x"8D6" => DATA <= x"CD";
when x"8D7" => DATA <= x"9A";
when x"8D8" => DATA <= x"F6";
when x"8D9" => DATA <= x"6F";
when x"8DA" => DATA <= x"F1";
when x"8DB" => DATA <= x"C9";
when x"8DC" => DATA <= x"21";
when x"8DD" => DATA <= x"00";
when x"8DE" => DATA <= x"00";
when x"8DF" => DATA <= x"C9";
when x"8E0" => DATA <= x"21";
when x"8E1" => DATA <= x"03";
when x"8E2" => DATA <= x"3B";
when x"8E3" => DATA <= x"C9";
when x"8E4" => DATA <= x"21";
when x"8E5" => DATA <= x"00";
when x"8E6" => DATA <= x"DC";
when x"8E7" => DATA <= x"C9";
when x"8E8" => DATA <= x"F5";
when x"8E9" => DATA <= x"3E";
when x"8EA" => DATA <= x"01";
when x"8EB" => DATA <= x"32";
when x"8EC" => DATA <= x"A4";
when x"8ED" => DATA <= x"FC";
when x"8EE" => DATA <= x"F1";
when x"8EF" => DATA <= x"B7";
when x"8F0" => DATA <= x"28";
when x"8F1" => DATA <= x"6B";
when x"8F2" => DATA <= x"C5";
when x"8F3" => DATA <= x"E5";
when x"8F4" => DATA <= x"DD";
when x"8F5" => DATA <= x"E5";
when x"8F6" => DATA <= x"F5";
when x"8F7" => DATA <= x"3E";
when x"8F8" => DATA <= x"08";
when x"8F9" => DATA <= x"CD";
when x"8FA" => DATA <= x"A3";
when x"8FB" => DATA <= x"F6";
when x"8FC" => DATA <= x"F1";
when x"8FD" => DATA <= x"F5";
when x"8FE" => DATA <= x"CD";
when x"8FF" => DATA <= x"A3";
when x"900" => DATA <= x"F6";
when x"901" => DATA <= x"06";
when x"902" => DATA <= x"00";
when x"903" => DATA <= x"4F";
when x"904" => DATA <= x"FE";
when x"905" => DATA <= x"80";
when x"906" => DATA <= x"38";
when x"907" => DATA <= x"06";
when x"908" => DATA <= x"46";
when x"909" => DATA <= x"23";
when x"90A" => DATA <= x"4E";
when x"90B" => DATA <= x"2B";
when x"90C" => DATA <= x"18";
when x"90D" => DATA <= x"15";
when x"90E" => DATA <= x"FE";
when x"90F" => DATA <= x"15";
when x"910" => DATA <= x"38";
when x"911" => DATA <= x"05";
when x"912" => DATA <= x"01";
when x"913" => DATA <= x"10";
when x"914" => DATA <= x"10";
when x"915" => DATA <= x"18";
when x"916" => DATA <= x"0C";
when x"917" => DATA <= x"DD";
when x"918" => DATA <= x"21";
when x"919" => DATA <= x"75";
when x"91A" => DATA <= x"FC";
when x"91B" => DATA <= x"DD";
when x"91C" => DATA <= x"09";
when x"91D" => DATA <= x"DD";
when x"91E" => DATA <= x"46";
when x"91F" => DATA <= x"FF";
when x"920" => DATA <= x"DD";
when x"921" => DATA <= x"4E";
when x"922" => DATA <= x"13";
when x"923" => DATA <= x"E5";
when x"924" => DATA <= x"C5";
when x"925" => DATA <= x"48";
when x"926" => DATA <= x"06";
when x"927" => DATA <= x"00";
when x"928" => DATA <= x"09";
when x"929" => DATA <= x"C1";
when x"92A" => DATA <= x"78";
when x"92B" => DATA <= x"CD";
when x"92C" => DATA <= x"A3";
when x"92D" => DATA <= x"F6";
when x"92E" => DATA <= x"B7";
when x"92F" => DATA <= x"28";
when x"930" => DATA <= x"07";
when x"931" => DATA <= x"2B";
when x"932" => DATA <= x"7E";
when x"933" => DATA <= x"CD";
when x"934" => DATA <= x"A3";
when x"935" => DATA <= x"F6";
when x"936" => DATA <= x"10";
when x"937" => DATA <= x"F9";
when x"938" => DATA <= x"79";
when x"939" => DATA <= x"CD";
when x"93A" => DATA <= x"A3";
when x"93B" => DATA <= x"F6";
when x"93C" => DATA <= x"E1";
when x"93D" => DATA <= x"F5";
when x"93E" => DATA <= x"3A";
when x"93F" => DATA <= x"A4";
when x"940" => DATA <= x"FC";
when x"941" => DATA <= x"B7";
when x"942" => DATA <= x"28";
when x"943" => DATA <= x"06";
when x"944" => DATA <= x"62";
when x"945" => DATA <= x"6B";
when x"946" => DATA <= x"AF";
when x"947" => DATA <= x"32";
when x"948" => DATA <= x"A4";
when x"949" => DATA <= x"FC";
when x"94A" => DATA <= x"F1";
when x"94B" => DATA <= x"B7";
when x"94C" => DATA <= x"28";
when x"94D" => DATA <= x"09";
when x"94E" => DATA <= x"09";
when x"94F" => DATA <= x"41";
when x"950" => DATA <= x"2B";
when x"951" => DATA <= x"CD";
when x"952" => DATA <= x"9A";
when x"953" => DATA <= x"F6";
when x"954" => DATA <= x"77";
when x"955" => DATA <= x"10";
when x"956" => DATA <= x"F9";
when x"957" => DATA <= x"F1";
when x"958" => DATA <= x"DD";
when x"959" => DATA <= x"E1";
when x"95A" => DATA <= x"E1";
when x"95B" => DATA <= x"C1";
when x"95C" => DATA <= x"C9";
when x"95D" => DATA <= x"C5";
when x"95E" => DATA <= x"F5";
when x"95F" => DATA <= x"3E";
when x"960" => DATA <= x"0A";
when x"961" => DATA <= x"CD";
when x"962" => DATA <= x"A3";
when x"963" => DATA <= x"F6";
when x"964" => DATA <= x"23";
when x"965" => DATA <= x"23";
when x"966" => DATA <= x"23";
when x"967" => DATA <= x"23";
when x"968" => DATA <= x"06";
when x"969" => DATA <= x"03";
when x"96A" => DATA <= x"7E";
when x"96B" => DATA <= x"CD";
when x"96C" => DATA <= x"A3";
when x"96D" => DATA <= x"F6";
when x"96E" => DATA <= x"2B";
when x"96F" => DATA <= x"10";
when x"970" => DATA <= x"F9";
when x"971" => DATA <= x"3E";
when x"972" => DATA <= x"07";
when x"973" => DATA <= x"CD";
when x"974" => DATA <= x"A3";
when x"975" => DATA <= x"F6";
when x"976" => DATA <= x"97";
when x"977" => DATA <= x"CD";
when x"978" => DATA <= x"A3";
when x"979" => DATA <= x"F6";
when x"97A" => DATA <= x"CD";
when x"97B" => DATA <= x"9A";
when x"97C" => DATA <= x"F6";
when x"97D" => DATA <= x"07";
when x"97E" => DATA <= x"38";
when x"97F" => DATA <= x"18";
when x"980" => DATA <= x"7E";
when x"981" => DATA <= x"2B";
when x"982" => DATA <= x"6E";
when x"983" => DATA <= x"67";
when x"984" => DATA <= x"06";
when x"985" => DATA <= x"FF";
when x"986" => DATA <= x"CD";
when x"987" => DATA <= x"9A";
when x"988" => DATA <= x"F6";
when x"989" => DATA <= x"77";
when x"98A" => DATA <= x"23";
when x"98B" => DATA <= x"04";
when x"98C" => DATA <= x"FE";
when x"98D" => DATA <= x"0D";
when x"98E" => DATA <= x"20";
when x"98F" => DATA <= x"F6";
when x"990" => DATA <= x"2E";
when x"991" => DATA <= x"00";
when x"992" => DATA <= x"60";
when x"993" => DATA <= x"F1";
when x"994" => DATA <= x"C1";
when x"995" => DATA <= x"37";
when x"996" => DATA <= x"3F";
when x"997" => DATA <= x"C9";
when x"998" => DATA <= x"21";
when x"999" => DATA <= x"FF";
when x"99A" => DATA <= x"00";
when x"99B" => DATA <= x"F1";
when x"99C" => DATA <= x"C1";
when x"99D" => DATA <= x"37";
when x"99E" => DATA <= x"C9";
when x"99F" => DATA <= x"E5";
when x"9A0" => DATA <= x"D5";
when x"9A1" => DATA <= x"C5";
when x"9A2" => DATA <= x"F5";
when x"9A3" => DATA <= x"3E";
when x"9A4" => DATA <= x"0C";
when x"9A5" => DATA <= x"CD";
when x"9A6" => DATA <= x"A3";
when x"9A7" => DATA <= x"F6";
when x"9A8" => DATA <= x"7B";
when x"9A9" => DATA <= x"CD";
when x"9AA" => DATA <= x"A3";
when x"9AB" => DATA <= x"F6";
when x"9AC" => DATA <= x"23";
when x"9AD" => DATA <= x"23";
when x"9AE" => DATA <= x"23";
when x"9AF" => DATA <= x"06";
when x"9B0" => DATA <= x"04";
when x"9B1" => DATA <= x"7E";
when x"9B2" => DATA <= x"CD";
when x"9B3" => DATA <= x"A3";
when x"9B4" => DATA <= x"F6";
when x"9B5" => DATA <= x"2B";
when x"9B6" => DATA <= x"10";
when x"9B7" => DATA <= x"F9";
when x"9B8" => DATA <= x"23";
when x"9B9" => DATA <= x"F1";
when x"9BA" => DATA <= x"CD";
when x"9BB" => DATA <= x"A3";
when x"9BC" => DATA <= x"F6";
when x"9BD" => DATA <= x"CD";
when x"9BE" => DATA <= x"9A";
when x"9BF" => DATA <= x"F6";
when x"9C0" => DATA <= x"F5";
when x"9C1" => DATA <= x"23";
when x"9C2" => DATA <= x"23";
when x"9C3" => DATA <= x"23";
when x"9C4" => DATA <= x"06";
when x"9C5" => DATA <= x"04";
when x"9C6" => DATA <= x"CD";
when x"9C7" => DATA <= x"9A";
when x"9C8" => DATA <= x"F6";
when x"9C9" => DATA <= x"77";
when x"9CA" => DATA <= x"2B";
when x"9CB" => DATA <= x"10";
when x"9CC" => DATA <= x"F9";
when x"9CD" => DATA <= x"F1";
when x"9CE" => DATA <= x"C1";
when x"9CF" => DATA <= x"D1";
when x"9D0" => DATA <= x"E1";
when x"9D1" => DATA <= x"C9";
when x"9D2" => DATA <= x"F5";
when x"9D3" => DATA <= x"3E";
when x"9D4" => DATA <= x"12";
when x"9D5" => DATA <= x"CD";
when x"9D6" => DATA <= x"A3";
when x"9D7" => DATA <= x"F6";
when x"9D8" => DATA <= x"F1";
when x"9D9" => DATA <= x"CD";
when x"9DA" => DATA <= x"A3";
when x"9DB" => DATA <= x"F6";
when x"9DC" => DATA <= x"FE";
when x"9DD" => DATA <= x"00";
when x"9DE" => DATA <= x"20";
when x"9DF" => DATA <= x"0A";
when x"9E0" => DATA <= x"F5";
when x"9E1" => DATA <= x"7C";
when x"9E2" => DATA <= x"CD";
when x"9E3" => DATA <= x"A3";
when x"9E4" => DATA <= x"F6";
when x"9E5" => DATA <= x"CD";
when x"9E6" => DATA <= x"9A";
when x"9E7" => DATA <= x"F6";
when x"9E8" => DATA <= x"F1";
when x"9E9" => DATA <= x"C9";
when x"9EA" => DATA <= x"CD";
when x"9EB" => DATA <= x"84";
when x"9EC" => DATA <= x"F8";
when x"9ED" => DATA <= x"C3";
when x"9EE" => DATA <= x"9A";
when x"9EF" => DATA <= x"F6";
when x"9F0" => DATA <= x"3E";
when x"9F1" => DATA <= x"0E";
when x"9F2" => DATA <= x"CD";
when x"9F3" => DATA <= x"A3";
when x"9F4" => DATA <= x"F6";
when x"9F5" => DATA <= x"7C";
when x"9F6" => DATA <= x"CD";
when x"9F7" => DATA <= x"A3";
when x"9F8" => DATA <= x"F6";
when x"9F9" => DATA <= x"C3";
when x"9FA" => DATA <= x"95";
when x"9FB" => DATA <= x"F6";
when x"9FC" => DATA <= x"F5";
when x"9FD" => DATA <= x"3E";
when x"9FE" => DATA <= x"10";
when x"9FF" => DATA <= x"CD";
when x"A00" => DATA <= x"A3";
when x"A01" => DATA <= x"F6";
when x"A02" => DATA <= x"7C";
when x"A03" => DATA <= x"CD";
when x"A04" => DATA <= x"A3";
when x"A05" => DATA <= x"F6";
when x"A06" => DATA <= x"F1";
when x"A07" => DATA <= x"CD";
when x"A08" => DATA <= x"A3";
when x"A09" => DATA <= x"F6";
when x"A0A" => DATA <= x"F5";
when x"A0B" => DATA <= x"CD";
when x"A0C" => DATA <= x"9A";
when x"A0D" => DATA <= x"F6";
when x"A0E" => DATA <= x"F1";
when x"A0F" => DATA <= x"C9";
when x"A10" => DATA <= x"C5";
when x"A11" => DATA <= x"F5";
when x"A12" => DATA <= x"22";
when x"A13" => DATA <= x"AC";
when x"A14" => DATA <= x"FC";
when x"A15" => DATA <= x"3E";
when x"A16" => DATA <= x"14";
when x"A17" => DATA <= x"CD";
when x"A18" => DATA <= x"A3";
when x"A19" => DATA <= x"F6";
when x"A1A" => DATA <= x"01";
when x"A1B" => DATA <= x"11";
when x"A1C" => DATA <= x"00";
when x"A1D" => DATA <= x"09";
when x"A1E" => DATA <= x"06";
when x"A1F" => DATA <= x"10";
when x"A20" => DATA <= x"7E";
when x"A21" => DATA <= x"CD";
when x"A22" => DATA <= x"A3";
when x"A23" => DATA <= x"F6";
when x"A24" => DATA <= x"2B";
when x"A25" => DATA <= x"10";
when x"A26" => DATA <= x"F9";
when x"A27" => DATA <= x"7E";
when x"A28" => DATA <= x"2B";
when x"A29" => DATA <= x"6E";
when x"A2A" => DATA <= x"67";
when x"A2B" => DATA <= x"CD";
when x"A2C" => DATA <= x"84";
when x"A2D" => DATA <= x"F8";
when x"A2E" => DATA <= x"F1";
when x"A2F" => DATA <= x"CD";
when x"A30" => DATA <= x"A3";
when x"A31" => DATA <= x"F6";
when x"A32" => DATA <= x"CD";
when x"A33" => DATA <= x"9A";
when x"A34" => DATA <= x"F6";
when x"A35" => DATA <= x"E6";
when x"A36" => DATA <= x"FF";
when x"A37" => DATA <= x"F5";
when x"A38" => DATA <= x"2A";
when x"A39" => DATA <= x"AC";
when x"A3A" => DATA <= x"FC";
when x"A3B" => DATA <= x"01";
when x"A3C" => DATA <= x"11";
when x"A3D" => DATA <= x"00";
when x"A3E" => DATA <= x"09";
when x"A3F" => DATA <= x"06";
when x"A40" => DATA <= x"10";
when x"A41" => DATA <= x"CD";
when x"A42" => DATA <= x"9A";
when x"A43" => DATA <= x"F6";
when x"A44" => DATA <= x"77";
when x"A45" => DATA <= x"2B";
when x"A46" => DATA <= x"10";
when x"A47" => DATA <= x"F9";
when x"A48" => DATA <= x"2A";
when x"A49" => DATA <= x"AC";
when x"A4A" => DATA <= x"FC";
when x"A4B" => DATA <= x"F1";
when x"A4C" => DATA <= x"C1";
when x"A4D" => DATA <= x"C9";
when x"A4E" => DATA <= x"C5";
when x"A4F" => DATA <= x"F5";
when x"A50" => DATA <= x"22";
when x"A51" => DATA <= x"AC";
when x"A52" => DATA <= x"FC";
when x"A53" => DATA <= x"3E";
when x"A54" => DATA <= x"16";
when x"A55" => DATA <= x"CD";
when x"A56" => DATA <= x"A3";
when x"A57" => DATA <= x"F6";
when x"A58" => DATA <= x"01";
when x"A59" => DATA <= x"0C";
when x"A5A" => DATA <= x"00";
when x"A5B" => DATA <= x"09";
when x"A5C" => DATA <= x"06";
when x"A5D" => DATA <= x"0D";
when x"A5E" => DATA <= x"7E";
when x"A5F" => DATA <= x"CD";
when x"A60" => DATA <= x"A3";
when x"A61" => DATA <= x"F6";
when x"A62" => DATA <= x"2B";
when x"A63" => DATA <= x"10";
when x"A64" => DATA <= x"F9";
when x"A65" => DATA <= x"F1";
when x"A66" => DATA <= x"CD";
when x"A67" => DATA <= x"A3";
when x"A68" => DATA <= x"F6";
when x"A69" => DATA <= x"2A";
when x"A6A" => DATA <= x"AC";
when x"A6B" => DATA <= x"FC";
when x"A6C" => DATA <= x"01";
when x"A6D" => DATA <= x"0C";
when x"A6E" => DATA <= x"00";
when x"A6F" => DATA <= x"09";
when x"A70" => DATA <= x"06";
when x"A71" => DATA <= x"0D";
when x"A72" => DATA <= x"CD";
when x"A73" => DATA <= x"9A";
when x"A74" => DATA <= x"F6";
when x"A75" => DATA <= x"77";
when x"A76" => DATA <= x"2B";
when x"A77" => DATA <= x"10";
when x"A78" => DATA <= x"F9";
when x"A79" => DATA <= x"2A";
when x"A7A" => DATA <= x"AC";
when x"A7B" => DATA <= x"FC";
when x"A7C" => DATA <= x"C1";
when x"A7D" => DATA <= x"C3";
when x"A7E" => DATA <= x"95";
when x"A7F" => DATA <= x"F6";
when x"A80" => DATA <= x"00";
when x"A81" => DATA <= x"00";
when x"A82" => DATA <= x"ED";
when x"A83" => DATA <= x"73";
when x"A84" => DATA <= x"80";
when x"A85" => DATA <= x"FA";
when x"A86" => DATA <= x"31";
when x"A87" => DATA <= x"60";
when x"A88" => DATA <= x"FF";
when x"A89" => DATA <= x"CD";
when x"A8A" => DATA <= x"93";
when x"A8B" => DATA <= x"FA";
when x"A8C" => DATA <= x"ED";
when x"A8D" => DATA <= x"7B";
when x"A8E" => DATA <= x"80";
when x"A8F" => DATA <= x"FA";
when x"A90" => DATA <= x"FB";
when x"A91" => DATA <= x"ED";
when x"A92" => DATA <= x"4D";
when x"A93" => DATA <= x"F5";
when x"A94" => DATA <= x"DB";
when x"A95" => DATA <= x"06";
when x"A96" => DATA <= x"CB";
when x"A97" => DATA <= x"7F";
when x"A98" => DATA <= x"20";
when x"A99" => DATA <= x"71";
when x"A9A" => DATA <= x"DB";
when x"A9B" => DATA <= x"00";
when x"A9C" => DATA <= x"CB";
when x"A9D" => DATA <= x"7F";
when x"A9E" => DATA <= x"20";
when x"A9F" => DATA <= x"39";
when x"AA0" => DATA <= x"F1";
when x"AA1" => DATA <= x"C3";
when x"AA2" => DATA <= x"B0";
when x"AA3" => DATA <= x"FF";
when x"AA4" => DATA <= x"E1";
when x"AA5" => DATA <= x"22";
when x"AA6" => DATA <= x"82";
when x"AA7" => DATA <= x"FF";
when x"AA8" => DATA <= x"2A";
when x"AA9" => DATA <= x"FA";
when x"AAA" => DATA <= x"FF";
when x"AAB" => DATA <= x"E9";
when x"AAC" => DATA <= x"CD";
when x"AAD" => DATA <= x"C6";
when x"AAE" => DATA <= x"FA";
when x"AAF" => DATA <= x"C3";
when x"AB0" => DATA <= x"CB";
when x"AB1" => DATA <= x"F2";
when x"AB2" => DATA <= x"3E";
when x"AB3" => DATA <= x"03";
when x"AB4" => DATA <= x"2E";
when x"AB5" => DATA <= x"00";
when x"AB6" => DATA <= x"CD";
when x"AB7" => DATA <= x"8E";
when x"AB8" => DATA <= x"F8";
when x"AB9" => DATA <= x"3E";
when x"ABA" => DATA <= x"02";
when x"ABB" => DATA <= x"2E";
when x"ABC" => DATA <= x"02";
when x"ABD" => DATA <= x"CD";
when x"ABE" => DATA <= x"8E";
when x"ABF" => DATA <= x"F8";
when x"AC0" => DATA <= x"CD";
when x"AC1" => DATA <= x"C6";
when x"AC2" => DATA <= x"FA";
when x"AC3" => DATA <= x"C3";
when x"AC4" => DATA <= x"00";
when x"AC5" => DATA <= x"00";
when x"AC6" => DATA <= x"2A";
when x"AC7" => DATA <= x"82";
when x"AC8" => DATA <= x"FF";
when x"AC9" => DATA <= x"3E";
when x"ACA" => DATA <= x"0D";
when x"ACB" => DATA <= x"CD";
when x"ACC" => DATA <= x"71";
when x"ACD" => DATA <= x"F6";
when x"ACE" => DATA <= x"3E";
when x"ACF" => DATA <= x"0A";
when x"AD0" => DATA <= x"CD";
when x"AD1" => DATA <= x"71";
when x"AD2" => DATA <= x"F6";
when x"AD3" => DATA <= x"23";
when x"AD4" => DATA <= x"7E";
when x"AD5" => DATA <= x"B7";
when x"AD6" => DATA <= x"20";
when x"AD7" => DATA <= x"F8";
when x"AD8" => DATA <= x"C9";
when x"AD9" => DATA <= x"DB";
when x"ADA" => DATA <= x"01";
when x"ADB" => DATA <= x"CB";
when x"ADC" => DATA <= x"7F";
when x"ADD" => DATA <= x"20";
when x"ADE" => DATA <= x"25";
when x"ADF" => DATA <= x"3E";
when x"AE0" => DATA <= x"01";
when x"AE1" => DATA <= x"32";
when x"AE2" => DATA <= x"A2";
when x"AE3" => DATA <= x"FC";
when x"AE4" => DATA <= x"E5";
when x"AE5" => DATA <= x"DD";
when x"AE6" => DATA <= x"E5";
when x"AE7" => DATA <= x"CD";
when x"AE8" => DATA <= x"7C";
when x"AE9" => DATA <= x"F6";
when x"AEA" => DATA <= x"67";
when x"AEB" => DATA <= x"CD";
when x"AEC" => DATA <= x"7C";
when x"AED" => DATA <= x"F6";
when x"AEE" => DATA <= x"6F";
when x"AEF" => DATA <= x"CD";
when x"AF0" => DATA <= x"7C";
when x"AF1" => DATA <= x"F6";
when x"AF2" => DATA <= x"CD";
when x"AF3" => DATA <= x"FE";
when x"AF4" => DATA <= x"FA";
when x"AF5" => DATA <= x"AF";
when x"AF6" => DATA <= x"32";
when x"AF7" => DATA <= x"A2";
when x"AF8" => DATA <= x"FC";
when x"AF9" => DATA <= x"DD";
when x"AFA" => DATA <= x"E1";
when x"AFB" => DATA <= x"E1";
when x"AFC" => DATA <= x"F1";
when x"AFD" => DATA <= x"C9";
when x"AFE" => DATA <= x"DD";
when x"AFF" => DATA <= x"2A";
when x"B00" => DATA <= x"FC";
when x"B01" => DATA <= x"FF";
when x"B02" => DATA <= x"DD";
when x"B03" => DATA <= x"E9";
when x"B04" => DATA <= x"CB";
when x"B05" => DATA <= x"27";
when x"B06" => DATA <= x"32";
when x"B07" => DATA <= x"80";
when x"B08" => DATA <= x"FF";
when x"B09" => DATA <= x"F1";
when x"B0A" => DATA <= x"C9";
when x"B0B" => DATA <= x"DB";
when x"B0C" => DATA <= x"07";
when x"B0D" => DATA <= x"CB";
when x"B0E" => DATA <= x"7F";
when x"B0F" => DATA <= x"28";
when x"B10" => DATA <= x"45";
when x"B11" => DATA <= x"DB";
when x"B12" => DATA <= x"02";
when x"B13" => DATA <= x"CB";
when x"B14" => DATA <= x"7F";
when x"B15" => DATA <= x"28";
when x"B16" => DATA <= x"FA";
when x"B17" => DATA <= x"DB";
when x"B18" => DATA <= x"03";
when x"B19" => DATA <= x"FB";
when x"B1A" => DATA <= x"21";
when x"B1B" => DATA <= x"B0";
when x"B1C" => DATA <= x"FC";
when x"B1D" => DATA <= x"36";
when x"B1E" => DATA <= x"CD";
when x"B1F" => DATA <= x"23";
when x"B20" => DATA <= x"3A";
when x"B21" => DATA <= x"BD";
when x"B22" => DATA <= x"FF";
when x"B23" => DATA <= x"77";
when x"B24" => DATA <= x"23";
when x"B25" => DATA <= x"3A";
when x"B26" => DATA <= x"BE";
when x"B27" => DATA <= x"FF";
when x"B28" => DATA <= x"77";
when x"B29" => DATA <= x"23";
when x"B2A" => DATA <= x"CD";
when x"B2B" => DATA <= x"9A";
when x"B2C" => DATA <= x"F6";
when x"B2D" => DATA <= x"77";
when x"B2E" => DATA <= x"B7";
when x"B2F" => DATA <= x"20";
when x"B30" => DATA <= x"1A";
when x"B31" => DATA <= x"CD";
when x"B32" => DATA <= x"0E";
when x"B33" => DATA <= x"F6";
when x"B34" => DATA <= x"0D";
when x"B35" => DATA <= x"46";
when x"B36" => DATA <= x"61";
when x"B37" => DATA <= x"74";
when x"B38" => DATA <= x"61";
when x"B39" => DATA <= x"6C";
when x"B3A" => DATA <= x"20";
when x"B3B" => DATA <= x"65";
when x"B3C" => DATA <= x"72";
when x"B3D" => DATA <= x"72";
when x"B3E" => DATA <= x"6F";
when x"B3F" => DATA <= x"72";
when x"B40" => DATA <= x"00";
when x"B41" => DATA <= x"3A";
when x"B42" => DATA <= x"A3";
when x"B43" => DATA <= x"FC";
when x"B44" => DATA <= x"B7";
when x"B45" => DATA <= x"C2";
when x"B46" => DATA <= x"00";
when x"B47" => DATA <= x"00";
when x"B48" => DATA <= x"C3";
when x"B49" => DATA <= x"CB";
when x"B4A" => DATA <= x"F2";
when x"B4B" => DATA <= x"23";
when x"B4C" => DATA <= x"CD";
when x"B4D" => DATA <= x"9A";
when x"B4E" => DATA <= x"F6";
when x"B4F" => DATA <= x"77";
when x"B50" => DATA <= x"B7";
when x"B51" => DATA <= x"20";
when x"B52" => DATA <= x"F8";
when x"B53" => DATA <= x"C3";
when x"B54" => DATA <= x"B0";
when x"B55" => DATA <= x"FC";
when x"B56" => DATA <= x"C5";
when x"B57" => DATA <= x"D5";
when x"B58" => DATA <= x"E5";
when x"B59" => DATA <= x"F5";
when x"B5A" => DATA <= x"07";
when x"B5B" => DATA <= x"5F";
when x"B5C" => DATA <= x"07";
when x"B5D" => DATA <= x"07";
when x"B5E" => DATA <= x"83";
when x"B5F" => DATA <= x"07";
when x"B60" => DATA <= x"5F";
when x"B61" => DATA <= x"16";
when x"B62" => DATA <= x"00";
when x"B63" => DATA <= x"21";
when x"B64" => DATA <= x"C1";
when x"B65" => DATA <= x"FB";
when x"B66" => DATA <= x"19";
when x"B67" => DATA <= x"11";
when x"B68" => DATA <= x"61";
when x"B69" => DATA <= x"FC";
when x"B6A" => DATA <= x"01";
when x"B6B" => DATA <= x"14";
when x"B6C" => DATA <= x"00";
when x"B6D" => DATA <= x"ED";
when x"B6E" => DATA <= x"B0";
when x"B6F" => DATA <= x"CD";
when x"B70" => DATA <= x"AE";
when x"B71" => DATA <= x"F6";
when x"B72" => DATA <= x"F1";
when x"B73" => DATA <= x"FE";
when x"B74" => DATA <= x"05";
when x"B75" => DATA <= x"28";
when x"B76" => DATA <= x"33";
when x"B77" => DATA <= x"F5";
when x"B78" => DATA <= x"CD";
when x"B79" => DATA <= x"AE";
when x"B7A" => DATA <= x"F6";
when x"B7B" => DATA <= x"CD";
when x"B7C" => DATA <= x"AE";
when x"B7D" => DATA <= x"F6";
when x"B7E" => DATA <= x"CD";
when x"B7F" => DATA <= x"AE";
when x"B80" => DATA <= x"F6";
when x"B81" => DATA <= x"67";
when x"B82" => DATA <= x"CD";
when x"B83" => DATA <= x"AE";
when x"B84" => DATA <= x"F6";
when x"B85" => DATA <= x"6F";
when x"B86" => DATA <= x"22";
when x"B87" => DATA <= x"A8";
when x"B88" => DATA <= x"FC";
when x"B89" => DATA <= x"0E";
when x"B8A" => DATA <= x"05";
when x"B8B" => DATA <= x"06";
when x"B8C" => DATA <= x"00";
when x"B8D" => DATA <= x"CD";
when x"B8E" => DATA <= x"AE";
when x"B8F" => DATA <= x"F6";
when x"B90" => DATA <= x"F1";
when x"B91" => DATA <= x"FE";
when x"B92" => DATA <= x"06";
when x"B93" => DATA <= x"38";
when x"B94" => DATA <= x"15";
when x"B95" => DATA <= x"20";
when x"B96" => DATA <= x"1D";
when x"B97" => DATA <= x"DB";
when x"B98" => DATA <= x"04";
when x"B99" => DATA <= x"B7";
when x"B9A" => DATA <= x"F2";
when x"B9B" => DATA <= x"97";
when x"B9C" => DATA <= x"FB";
when x"B9D" => DATA <= x"ED";
when x"B9E" => DATA <= x"A3";
when x"B9F" => DATA <= x"C2";
when x"BA0" => DATA <= x"97";
when x"BA1" => DATA <= x"FB";
when x"BA2" => DATA <= x"DB";
when x"BA3" => DATA <= x"04";
when x"BA4" => DATA <= x"B7";
when x"BA5" => DATA <= x"F2";
when x"BA6" => DATA <= x"A2";
when x"BA7" => DATA <= x"FB";
when x"BA8" => DATA <= x"D3";
when x"BA9" => DATA <= x"05";
when x"BAA" => DATA <= x"E1";
when x"BAB" => DATA <= x"D1";
when x"BAC" => DATA <= x"C1";
when x"BAD" => DATA <= x"3A";
when x"BAE" => DATA <= x"A2";
when x"BAF" => DATA <= x"FC";
when x"BB0" => DATA <= x"B7";
when x"BB1" => DATA <= x"C0";
when x"BB2" => DATA <= x"F1";
when x"BB3" => DATA <= x"C9";
when x"BB4" => DATA <= x"DB";
when x"BB5" => DATA <= x"04";
when x"BB6" => DATA <= x"B7";
when x"BB7" => DATA <= x"F2";
when x"BB8" => DATA <= x"B4";
when x"BB9" => DATA <= x"FB";
when x"BBA" => DATA <= x"ED";
when x"BBB" => DATA <= x"A2";
when x"BBC" => DATA <= x"C2";
when x"BBD" => DATA <= x"B4";
when x"BBE" => DATA <= x"FB";
when x"BBF" => DATA <= x"18";
when x"BC0" => DATA <= x"E9";
when x"BC1" => DATA <= x"E5";
when x"BC2" => DATA <= x"F5";
when x"BC3" => DATA <= x"2A";
when x"BC4" => DATA <= x"A8";
when x"BC5" => DATA <= x"FC";
when x"BC6" => DATA <= x"7E";
when x"BC7" => DATA <= x"D3";
when x"BC8" => DATA <= x"05";
when x"BC9" => DATA <= x"23";
when x"BCA" => DATA <= x"22";
when x"BCB" => DATA <= x"A8";
when x"BCC" => DATA <= x"FC";
when x"BCD" => DATA <= x"F1";
when x"BCE" => DATA <= x"E1";
when x"BCF" => DATA <= x"ED";
when x"BD0" => DATA <= x"45";
when x"BD1" => DATA <= x"3A";
when x"BD2" => DATA <= x"12";
when x"BD3" => DATA <= x"3B";
when x"BD4" => DATA <= x"B7";
when x"BD5" => DATA <= x"E5";
when x"BD6" => DATA <= x"F5";
when x"BD7" => DATA <= x"DB";
when x"BD8" => DATA <= x"05";
when x"BD9" => DATA <= x"2A";
when x"BDA" => DATA <= x"A8";
when x"BDB" => DATA <= x"FC";
when x"BDC" => DATA <= x"77";
when x"BDD" => DATA <= x"23";
when x"BDE" => DATA <= x"22";
when x"BDF" => DATA <= x"A8";
when x"BE0" => DATA <= x"FC";
when x"BE1" => DATA <= x"F1";
when x"BE2" => DATA <= x"E1";
when x"BE3" => DATA <= x"ED";
when x"BE4" => DATA <= x"45";
when x"BE5" => DATA <= x"01";
when x"BE6" => DATA <= x"3B";
when x"BE7" => DATA <= x"EB";
when x"BE8" => DATA <= x"CD";
when x"BE9" => DATA <= x"E5";
when x"BEA" => DATA <= x"F5";
when x"BEB" => DATA <= x"2A";
when x"BEC" => DATA <= x"A8";
when x"BED" => DATA <= x"FC";
when x"BEE" => DATA <= x"7E";
when x"BEF" => DATA <= x"D3";
when x"BF0" => DATA <= x"05";
when x"BF1" => DATA <= x"23";
when x"BF2" => DATA <= x"7E";
when x"BF3" => DATA <= x"D3";
when x"BF4" => DATA <= x"05";
when x"BF5" => DATA <= x"23";
when x"BF6" => DATA <= x"22";
when x"BF7" => DATA <= x"A8";
when x"BF8" => DATA <= x"FC";
when x"BF9" => DATA <= x"F1";
when x"BFA" => DATA <= x"E1";
when x"BFB" => DATA <= x"ED";
when x"BFC" => DATA <= x"45";
when x"BFD" => DATA <= x"E5";
when x"BFE" => DATA <= x"F5";
when x"BFF" => DATA <= x"DB";
when x"C00" => DATA <= x"05";
when x"C01" => DATA <= x"2A";
when x"C02" => DATA <= x"A8";
when x"C03" => DATA <= x"FC";
when x"C04" => DATA <= x"77";
when x"C05" => DATA <= x"23";
when x"C06" => DATA <= x"DB";
when x"C07" => DATA <= x"05";
when x"C08" => DATA <= x"77";
when x"C09" => DATA <= x"23";
when x"C0A" => DATA <= x"22";
when x"C0B" => DATA <= x"A8";
when x"C0C" => DATA <= x"FC";
when x"C0D" => DATA <= x"F1";
when x"C0E" => DATA <= x"E1";
when x"C0F" => DATA <= x"ED";
when x"C10" => DATA <= x"45";
when x"C11" => DATA <= x"D3";
when x"C12" => DATA <= x"05";
when x"C13" => DATA <= x"ED";
when x"C14" => DATA <= x"45";
when x"C15" => DATA <= x"23";
when x"C16" => DATA <= x"56";
when x"C17" => DATA <= x"2B";
when x"C18" => DATA <= x"C9";
when x"C19" => DATA <= x"2A";
when x"C1A" => DATA <= x"A0";
when x"C1B" => DATA <= x"3C";
when x"C1C" => DATA <= x"19";
when x"C1D" => DATA <= x"23";
when x"C1E" => DATA <= x"23";
when x"C1F" => DATA <= x"5E";
when x"C20" => DATA <= x"23";
when x"C21" => DATA <= x"56";
when x"C22" => DATA <= x"2B";
when x"C23" => DATA <= x"C9";
when x"C24" => DATA <= x"2A";
when x"C25" => DATA <= x"D3";
when x"C26" => DATA <= x"05";
when x"C27" => DATA <= x"ED";
when x"C28" => DATA <= x"45";
when x"C29" => DATA <= x"CA";
when x"C2A" => DATA <= x"0D";
when x"C2B" => DATA <= x"37";
when x"C2C" => DATA <= x"EB";
when x"C2D" => DATA <= x"D5";
when x"C2E" => DATA <= x"CD";
when x"C2F" => DATA <= x"ED";
when x"C30" => DATA <= x"36";
when x"C31" => DATA <= x"EB";
when x"C32" => DATA <= x"22";
when x"C33" => DATA <= x"A4";
when x"C34" => DATA <= x"3C";
when x"C35" => DATA <= x"D1";
when x"C36" => DATA <= x"C3";
when x"C37" => DATA <= x"39";
when x"C38" => DATA <= x"37";
when x"C39" => DATA <= x"D3";
when x"C3A" => DATA <= x"05";
when x"C3B" => DATA <= x"ED";
when x"C3C" => DATA <= x"45";
when x"C3D" => DATA <= x"20";
when x"C3E" => DATA <= x"00";
when x"C3F" => DATA <= x"EB";
when x"C40" => DATA <= x"19";
when x"C41" => DATA <= x"22";
when x"C42" => DATA <= x"A2";
when x"C43" => DATA <= x"3C";
when x"C44" => DATA <= x"D5";
when x"C45" => DATA <= x"EB";
when x"C46" => DATA <= x"2A";
when x"C47" => DATA <= x"AC";
when x"C48" => DATA <= x"3C";
when x"C49" => DATA <= x"CD";
when x"C4A" => DATA <= x"82";
when x"C4B" => DATA <= x"0D";
when x"C4C" => DATA <= x"D1";
when x"C4D" => DATA <= x"D3";
when x"C4E" => DATA <= x"05";
when x"C4F" => DATA <= x"ED";
when x"C50" => DATA <= x"45";
when x"C51" => DATA <= x"7B";
when x"C52" => DATA <= x"3C";
when x"C53" => DATA <= x"25";
when x"C54" => DATA <= x"3A";
when x"C55" => DATA <= x"7D";
when x"C56" => DATA <= x"3C";
when x"C57" => DATA <= x"B7";
when x"C58" => DATA <= x"CD";
when x"C59" => DATA <= x"82";
when x"C5A" => DATA <= x"0D";
when x"C5B" => DATA <= x"DA";
when x"C5C" => DATA <= x"87";
when x"C5D" => DATA <= x"38";
when x"C5E" => DATA <= x"2A";
when x"C5F" => DATA <= x"A0";
when x"C60" => DATA <= x"3C";
when x"C61" => DATA <= x"D3";
when x"C62" => DATA <= x"05";
when x"C63" => DATA <= x"ED";
when x"C64" => DATA <= x"45";
when x"C65" => DATA <= x"D5";
when x"C66" => DATA <= x"CD";
when x"C67" => DATA <= x"E4";
when x"C68" => DATA <= x"36";
when x"C69" => DATA <= x"EB";
when x"C6A" => DATA <= x"2A";
when x"C6B" => DATA <= x"A8";
when x"C6C" => DATA <= x"3C";
when x"C6D" => DATA <= x"EB";
when x"C6E" => DATA <= x"7B";
when x"C6F" => DATA <= x"E6";
when x"C70" => DATA <= x"E0";
when x"C71" => DATA <= x"5F";
when x"C72" => DATA <= x"7B";
when x"C73" => DATA <= x"B2";
when x"C74" => DATA <= x"C2";
when x"C75" => DATA <= x"00";
when x"C76" => DATA <= x"05";
when x"C77" => DATA <= x"00";
when x"C78" => DATA <= x"05";
when x"C79" => DATA <= x"04";
when x"C7A" => DATA <= x"05";
when x"C7B" => DATA <= x"08";
when x"C7C" => DATA <= x"0E";
when x"C7D" => DATA <= x"04";
when x"C7E" => DATA <= x"01";
when x"C7F" => DATA <= x"01";
when x"C80" => DATA <= x"05";
when x"C81" => DATA <= x"00";
when x"C82" => DATA <= x"20";
when x"C83" => DATA <= x"20";
when x"C84" => DATA <= x"10";
when x"C85" => DATA <= x"0D";
when x"C86" => DATA <= x"00";
when x"C87" => DATA <= x"08";
when x"C88" => DATA <= x"80";
when x"C89" => DATA <= x"05";
when x"C8A" => DATA <= x"00";
when x"C8B" => DATA <= x"05";
when x"C8C" => DATA <= x"00";
when x"C8D" => DATA <= x"05";
when x"C8E" => DATA <= x"00";
when x"C8F" => DATA <= x"00";
when x"C90" => DATA <= x"00";
when x"C91" => DATA <= x"05";
when x"C92" => DATA <= x"09";
when x"C93" => DATA <= x"05";
when x"C94" => DATA <= x"00";
when x"C95" => DATA <= x"08";
when x"C96" => DATA <= x"20";
when x"C97" => DATA <= x"10";
when x"C98" => DATA <= x"01";
when x"C99" => DATA <= x"0D";
when x"C9A" => DATA <= x"80";
when x"C9B" => DATA <= x"08";
when x"C9C" => DATA <= x"80";
when x"C9D" => DATA <= x"B0";
when x"C9E" => DATA <= x"FC";
when x"C9F" => DATA <= x"80";
when x"CA0" => DATA <= x"20";
when x"CA1" => DATA <= x"FF";
when x"CA2" => DATA <= x"00";
when x"CA3" => DATA <= x"00";
when x"CA4" => DATA <= x"00";
when x"CA5" => DATA <= x"D5";
when x"CA6" => DATA <= x"F5";
when x"CA7" => DATA <= x"2A";
when x"CA8" => DATA <= x"A8";
when x"CA9" => DATA <= x"FC";
when x"CAA" => DATA <= x"00";
when x"CAB" => DATA <= x"00";
when x"CAC" => DATA <= x"B0";
when x"CAD" => DATA <= x"FC";
when x"CAE" => DATA <= x"00";
when x"CAF" => DATA <= x"00";
when x"CB0" => DATA <= x"36";
when x"CB1" => DATA <= x"2A";
when x"CB2" => DATA <= x"A0";
when x"CB3" => DATA <= x"3C";
when x"CB4" => DATA <= x"19";
when x"CB5" => DATA <= x"F1";
when x"CB6" => DATA <= x"F5";
when x"CB7" => DATA <= x"77";
when x"CB8" => DATA <= x"7B";
when x"CB9" => DATA <= x"E6";
when x"CBA" => DATA <= x"1F";
when x"CBB" => DATA <= x"FE";
when x"CBC" => DATA <= x"1F";
when x"CBD" => DATA <= x"CA";
when x"CBE" => DATA <= x"95";
when x"CBF" => DATA <= x"37";
when x"CC0" => DATA <= x"13";
when x"CC1" => DATA <= x"CC";
when x"CC2" => DATA <= x"9F";
when x"CC3" => DATA <= x"37";
when x"CC4" => DATA <= x"EB";
when x"CC5" => DATA <= x"22";
when x"CC6" => DATA <= x"A8";
when x"CC7" => DATA <= x"3C";
when x"CC8" => DATA <= x"F1";
when x"CC9" => DATA <= x"D1";
when x"CCA" => DATA <= x"C9";
when x"CCB" => DATA <= x"7B";
when x"CCC" => DATA <= x"E6";
when x"CCD" => DATA <= x"E0";
when x"CCE" => DATA <= x"5F";
when x"CCF" => DATA <= x"CD";
when x"CD0" => DATA <= x"ED";
when x"CD1" => DATA <= x"36";
when x"CD2" => DATA <= x"7A";
when x"CD3" => DATA <= x"B3";
when x"CD4" => DATA <= x"CA";
when x"CD5" => DATA <= x"F8";
when x"CD6" => DATA <= x"36";
when x"CD7" => DATA <= x"13";
when x"CD8" => DATA <= x"13";
when x"CD9" => DATA <= x"13";
when x"CDA" => DATA <= x"13";
when x"CDB" => DATA <= x"C9";
when x"CDC" => DATA <= x"D5";
when x"CDD" => DATA <= x"EB";
when x"CDE" => DATA <= x"2A";
when x"CDF" => DATA <= x"A0";
when x"CE0" => DATA <= x"3C";
when x"CE1" => DATA <= x"EB";
when x"CE2" => DATA <= x"7D";
when x"CE3" => DATA <= x"E6";
when x"CE4" => DATA <= x"1F";
when x"CE5" => DATA <= x"C2";
when x"CE6" => DATA <= x"C0";
when x"CE7" => DATA <= x"37";
when x"CE8" => DATA <= x"7D";
when x"CE9" => DATA <= x"F6";
when x"CEA" => DATA <= x"04";
when x"CEB" => DATA <= x"6F";
when x"CEC" => DATA <= x"EB";
when x"CED" => DATA <= x"19";
when x"CEE" => DATA <= x"7E";
when x"CEF" => DATA <= x"EB";
when x"CF0" => DATA <= x"D1";
when x"CF1" => DATA <= x"C9";
when x"CF2" => DATA <= x"CD";
when x"CF3" => DATA <= x"B0";
when x"CF4" => DATA <= x"37";
when x"CF5" => DATA <= x"F5";
when x"CF6" => DATA <= x"D5";
when x"CF7" => DATA <= x"EB";
when x"CF8" => DATA <= x"7B";
when x"CF9" => DATA <= x"E6";
when x"CFA" => DATA <= x"1F";
when x"CFB" => DATA <= x"FE";
when x"CFC" => DATA <= x"1F";
when x"CFD" => DATA <= x"CA";
when x"CFE" => DATA <= x"D5";
when x"CFF" => DATA <= x"37";
when x"D00" => DATA <= x"13";
when x"D01" => DATA <= x"CC";
when x"D02" => DATA <= x"9F";
when x"D03" => DATA <= x"37";
when x"D04" => DATA <= x"EB";
when x"D05" => DATA <= x"D1";
when x"D06" => DATA <= x"F1";
when x"D07" => DATA <= x"C9";
when x"D08" => DATA <= x"EB";
when x"D09" => DATA <= x"7B";
when x"D0A" => DATA <= x"E6";
when x"D0B" => DATA <= x"E0";
when x"D0C" => DATA <= x"5F";
when x"D0D" => DATA <= x"D5";
when x"D0E" => DATA <= x"CD";
when x"D0F" => DATA <= x"ED";
when x"D10" => DATA <= x"36";
when x"D11" => DATA <= x"7B";
when x"D12" => DATA <= x"B2";
when x"D13" => DATA <= x"C1";
when x"D14" => DATA <= x"C8";
when x"D15" => DATA <= x"AF";
when x"D16" => DATA <= x"77";
when x"D17" => DATA <= x"23";
when x"D18" => DATA <= x"77";
when x"D19" => DATA <= x"2A";
when x"D1A" => DATA <= x"A0";
when x"D1B" => DATA <= x"3C";
when x"D1C" => DATA <= x"19";
when x"D1D" => DATA <= x"73";
when x"D1E" => DATA <= x"23";
when x"D1F" => DATA <= x"72";
when x"D20" => DATA <= x"C5";
when x"D21" => DATA <= x"CD";
when x"D22" => DATA <= x"D2";
when x"D23" => DATA <= x"36";
when x"D24" => DATA <= x"C1";
when x"D25" => DATA <= x"2A";
when x"D26" => DATA <= x"A6";
when x"D27" => DATA <= x"3C";
when x"D28" => DATA <= x"EB";
when x"D29" => DATA <= x"CD";
when x"D2A" => DATA <= x"E4";
when x"D2B" => DATA <= x"36";
when x"D2C" => DATA <= x"71";
when x"D2D" => DATA <= x"23";
when x"D2E" => DATA <= x"70";
when x"D2F" => DATA <= x"C9";
when x"D30" => DATA <= x"4C";
when x"D31" => DATA <= x"05";
when x"D32" => DATA <= x"25";
when x"D33" => DATA <= x"10";
when x"D34" => DATA <= x"E3";
when x"D35" => DATA <= x"C9";
when x"D36" => DATA <= x"FF";
when x"D37" => DATA <= x"F0";
when x"D38" => DATA <= x"03";
when x"D39" => DATA <= x"6C";
when x"D3A" => DATA <= x"03";
when x"D3B" => DATA <= x"25";
when x"D3C" => DATA <= x"86";
when x"D3D" => DATA <= x"70";
when x"D3E" => DATA <= x"84";
when x"D3F" => DATA <= x"71";
when x"D40" => DATA <= x"85";
when x"D41" => DATA <= x"72";
when x"D42" => DATA <= x"A0";
when x"D43" => DATA <= x"02";
when x"D44" => DATA <= x"B1";
when x"D45" => DATA <= x"70";
when x"D46" => DATA <= x"85";
when x"D47" => DATA <= x"74";
when x"D48" => DATA <= x"C8";
when x"D49" => DATA <= x"B1";
when x"D4A" => DATA <= x"70";
when x"D4B" => DATA <= x"85";
when x"D4C" => DATA <= x"75";
when x"D4D" => DATA <= x"20";
when x"D4E" => DATA <= x"9C";
when x"D4F" => DATA <= x"25";
when x"D50" => DATA <= x"A0";
when x"D51" => DATA <= x"0C";
when x"D52" => DATA <= x"B1";
when x"D53" => DATA <= x"70";
when x"D54" => DATA <= x"48";
when x"D55" => DATA <= x"A5";
when x"D56" => DATA <= x"70";
when x"D57" => DATA <= x"18";
when x"D58" => DATA <= x"69";
when x"D59" => DATA <= x"06";
when x"D5A" => DATA <= x"AA";
when x"D5B" => DATA <= x"A9";
when x"D5C" => DATA <= x"00";
when x"D5D" => DATA <= x"65";
when x"D5E" => DATA <= x"71";
when x"D5F" => DATA <= x"A8";
when x"D60" => DATA <= x"68";
when x"D61" => DATA <= x"48";
when x"D62" => DATA <= x"20";
when x"D63" => DATA <= x"06";
when x"D64" => DATA <= x"04";
when x"D65" => DATA <= x"A0";
when x"D66" => DATA <= x"0A";
when x"D67" => DATA <= x"B1";
when x"D68" => DATA <= x"70";
when x"D69" => DATA <= x"AA";
when x"D6A" => DATA <= x"C8";
when x"D6B" => DATA <= x"B1";
when x"D6C" => DATA <= x"70";
when x"D6D" => DATA <= x"85";
when x"D6E" => DATA <= x"76";
when x"D6F" => DATA <= x"D0";
when x"D70" => DATA <= x"03";
when x"D71" => DATA <= x"8A";
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when x"D74" => DATA <= x"8A";
when x"D75" => DATA <= x"F0";
when x"D76" => DATA <= x"02";
when x"D77" => DATA <= x"E6";
when x"D78" => DATA <= x"76";
when x"D79" => DATA <= x"68";
when x"D7A" => DATA <= x"6A";
when x"D7B" => DATA <= x"B0";
when x"D7C" => DATA <= x"28";
when x"D7D" => DATA <= x"20";
when x"D7E" => DATA <= x"9B";
when x"D7F" => DATA <= x"25";
when x"D80" => DATA <= x"20";
when x"D81" => DATA <= x"9B";
when x"D82" => DATA <= x"25";
when x"D83" => DATA <= x"20";
when x"D84" => DATA <= x"9B";
when x"D85" => DATA <= x"25";
when x"D86" => DATA <= x"A0";
when x"D87" => DATA <= x"00";
when x"D88" => DATA <= x"AD";
when x"D89" => DATA <= x"E5";
when x"D8A" => DATA <= x"FE";
when x"D8B" => DATA <= x"91";
when x"D8C" => DATA <= x"74";
when x"D8D" => DATA <= x"20";
when x"D8E" => DATA <= x"9B";
when x"D8F" => DATA <= x"25";
when x"D90" => DATA <= x"20";
when x"D91" => DATA <= x"9B";
when x"D92" => DATA <= x"25";
when x"D93" => DATA <= x"20";
when x"D94" => DATA <= x"9B";
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when x"D96" => DATA <= x"E6";
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when x"D98" => DATA <= x"D0";
when x"D99" => DATA <= x"02";
when x"D9A" => DATA <= x"E6";
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when x"D9C" => DATA <= x"CA";
when x"D9D" => DATA <= x"D0";
when x"D9E" => DATA <= x"E9";
when x"D9F" => DATA <= x"C6";
when x"DA0" => DATA <= x"76";
when x"DA1" => DATA <= x"D0";
when x"DA2" => DATA <= x"E5";
when x"DA3" => DATA <= x"F0";
when x"DA4" => DATA <= x"1D";
when x"DA5" => DATA <= x"A0";
when x"DA6" => DATA <= x"00";
when x"DA7" => DATA <= x"B1";
when x"DA8" => DATA <= x"74";
when x"DA9" => DATA <= x"8D";
when x"DAA" => DATA <= x"E5";
when x"DAB" => DATA <= x"FE";
when x"DAC" => DATA <= x"20";
when x"DAD" => DATA <= x"9B";
when x"DAE" => DATA <= x"25";
when x"DAF" => DATA <= x"20";
when x"DB0" => DATA <= x"9B";
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when x"DB2" => DATA <= x"20";
when x"DB3" => DATA <= x"9B";
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when x"DB5" => DATA <= x"E6";
when x"DB6" => DATA <= x"74";
when x"DB7" => DATA <= x"D0";
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when x"DB9" => DATA <= x"E6";
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when x"DBB" => DATA <= x"CA";
when x"DBC" => DATA <= x"D0";
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when x"DBF" => DATA <= x"76";
when x"DC0" => DATA <= x"D0";
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when x"DC3" => DATA <= x"A4";
when x"DC4" => DATA <= x"25";
when x"DC5" => DATA <= x"A6";
when x"DC6" => DATA <= x"70";
when x"DC7" => DATA <= x"A4";
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when x"DC9" => DATA <= x"A5";
when x"DCA" => DATA <= x"72";
when x"DCB" => DATA <= x"60";
when x"DCC" => DATA <= x"A9";
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when x"DCE" => DATA <= x"20";
when x"DCF" => DATA <= x"06";
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when x"DD1" => DATA <= x"90";
when x"DD2" => DATA <= x"F9";
when x"DD3" => DATA <= x"60";
when x"DD4" => DATA <= x"A9";
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when x"DD6" => DATA <= x"20";
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when x"DD9" => DATA <= x"60";
when x"DDA" => DATA <= x"00";
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when x"DDC" => DATA <= x"36";
when x"DDD" => DATA <= x"42";
when x"DDE" => DATA <= x"FE";
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when x"DE0" => DATA <= x"30";
when x"DE1" => DATA <= x"22";
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when x"DE4" => DATA <= x"81";
when x"DE5" => DATA <= x"FF";
when x"DE6" => DATA <= x"E6";
when x"DE7" => DATA <= x"01";
when x"DE8" => DATA <= x"32";
when x"DE9" => DATA <= x"AA";
when x"DEA" => DATA <= x"FC";
when x"DEB" => DATA <= x"F1";
when x"DEC" => DATA <= x"32";
when x"DED" => DATA <= x"81";
when x"DEE" => DATA <= x"FF";
when x"DEF" => DATA <= x"B7";
when x"DF0" => DATA <= x"20";
when x"DF1" => DATA <= x"08";
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when x"DF4" => DATA <= x"F6";
when x"DF5" => DATA <= x"22";
when x"DF6" => DATA <= x"9F";
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when x"DF8" => DATA <= x"18";
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when x"DFA" => DATA <= x"21";
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when x"DFD" => DATA <= x"22";
when x"DFE" => DATA <= x"9F";
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when x"E00" => DATA <= x"3A";
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when x"E04" => DATA <= x"FE";
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when x"E06" => DATA <= x"C0";
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when x"E08" => DATA <= x"81";
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when x"E0C" => DATA <= x"C9";
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when x"E0E" => DATA <= x"3A";
when x"E0F" => DATA <= x"81";
when x"E10" => DATA <= x"FF";
when x"E11" => DATA <= x"CB";
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when x"E14" => DATA <= x"12";
when x"E15" => DATA <= x"79";
when x"E16" => DATA <= x"FE";
when x"E17" => DATA <= x"1B";
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when x"E19" => DATA <= x"04";
when x"E1A" => DATA <= x"CD";
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when x"E1C" => DATA <= x"F6";
when x"E1D" => DATA <= x"C9";
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when x"E1F" => DATA <= x"81";
when x"E20" => DATA <= x"FF";
when x"E21" => DATA <= x"CB";
when x"E22" => DATA <= x"FF";
when x"E23" => DATA <= x"32";
when x"E24" => DATA <= x"81";
when x"E25" => DATA <= x"FF";
when x"E26" => DATA <= x"C9";
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when x"E28" => DATA <= x"77";
when x"E29" => DATA <= x"C2";
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when x"E2B" => DATA <= x"FE";
when x"E2C" => DATA <= x"CB";
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when x"E2E" => DATA <= x"C2";
when x"E2F" => DATA <= x"D9";
when x"E30" => DATA <= x"FE";
when x"E31" => DATA <= x"79";
when x"E32" => DATA <= x"FE";
when x"E33" => DATA <= x"3D";
when x"E34" => DATA <= x"28";
when x"E35" => DATA <= x"15";
when x"E36" => DATA <= x"FE";
when x"E37" => DATA <= x"3E";
when x"E38" => DATA <= x"28";
when x"E39" => DATA <= x"1A";
when x"E3A" => DATA <= x"FE";
when x"E3B" => DATA <= x"3F";
when x"E3C" => DATA <= x"28";
when x"E3D" => DATA <= x"1F";
when x"E3E" => DATA <= x"FE";
when x"E3F" => DATA <= x"40";
when x"E40" => DATA <= x"28";
when x"E41" => DATA <= x"3E";
when x"E42" => DATA <= x"3A";
when x"E43" => DATA <= x"81";
when x"E44" => DATA <= x"FF";
when x"E45" => DATA <= x"CB";
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when x"E47" => DATA <= x"32";
when x"E48" => DATA <= x"81";
when x"E49" => DATA <= x"FF";
when x"E4A" => DATA <= x"C9";
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when x"E4C" => DATA <= x"81";
when x"E4D" => DATA <= x"FF";
when x"E4E" => DATA <= x"CB";
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when x"E50" => DATA <= x"32";
when x"E51" => DATA <= x"81";
when x"E52" => DATA <= x"FF";
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when x"E54" => DATA <= x"3A";
when x"E55" => DATA <= x"81";
when x"E56" => DATA <= x"FF";
when x"E57" => DATA <= x"CB";
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when x"E59" => DATA <= x"32";
when x"E5A" => DATA <= x"81";
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when x"E5C" => DATA <= x"C9";
when x"E5D" => DATA <= x"CD";
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when x"E60" => DATA <= x"28";
when x"E61" => DATA <= x"08";
when x"E62" => DATA <= x"FE";
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when x"E65" => DATA <= x"DC";
when x"E66" => DATA <= x"3E";
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when x"E68" => DATA <= x"18";
when x"E69" => DATA <= x"02";
when x"E6A" => DATA <= x"3E";
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when x"E6C" => DATA <= x"32";
when x"E6D" => DATA <= x"18";
when x"E6E" => DATA <= x"FF";
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when x"E71" => DATA <= x"FE";
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when x"E74" => DATA <= x"21";
when x"E75" => DATA <= x"10";
when x"E76" => DATA <= x"FF";
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when x"E78" => DATA <= x"CD";
when x"E79" => DATA <= x"71";
when x"E7A" => DATA <= x"F6";
when x"E7B" => DATA <= x"23";
when x"E7C" => DATA <= x"10";
when x"E7D" => DATA <= x"F9";
when x"E7E" => DATA <= x"18";
when x"E7F" => DATA <= x"C2";
when x"E80" => DATA <= x"CD";
when x"E81" => DATA <= x"EC";
when x"E82" => DATA <= x"FE";
when x"E83" => DATA <= x"28";
when x"E84" => DATA <= x"04";
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when x"E87" => DATA <= x"20";
when x"E88" => DATA <= x"B9";
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when x"E8B" => DATA <= x"FE";
when x"E8C" => DATA <= x"06";
when x"E8D" => DATA <= x"06";
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when x"E8F" => DATA <= x"10";
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when x"E91" => DATA <= x"7E";
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when x"E93" => DATA <= x"71";
when x"E94" => DATA <= x"F6";
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when x"E9B" => DATA <= x"1B";
when x"E9C" => DATA <= x"FF";
when x"E9D" => DATA <= x"7E";
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when x"E9F" => DATA <= x"71";
when x"EA0" => DATA <= x"F6";
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when x"EA5" => DATA <= x"9C";
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when x"EA8" => DATA <= x"20";
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when x"EAB" => DATA <= x"D6";
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when x"EAD" => DATA <= x"32";
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when x"EB0" => DATA <= x"3A";
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when x"EB2" => DATA <= x"FF";
when x"EB3" => DATA <= x"CB";
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when x"EB5" => DATA <= x"32";
when x"EB6" => DATA <= x"81";
when x"EB7" => DATA <= x"FF";
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when x"EB9" => DATA <= x"79";
when x"EBA" => DATA <= x"D6";
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when x"EBC" => DATA <= x"32";
when x"EBD" => DATA <= x"20";
when x"EBE" => DATA <= x"FF";
when x"EBF" => DATA <= x"3E";
when x"EC0" => DATA <= x"1F";
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when x"EC2" => DATA <= x"71";
when x"EC3" => DATA <= x"F6";
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when x"EC9" => DATA <= x"F6";
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when x"ECC" => DATA <= x"FF";
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when x"ECF" => DATA <= x"F6";
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when x"ED2" => DATA <= x"FF";
when x"ED3" => DATA <= x"E6";
when x"ED4" => DATA <= x"01";
when x"ED5" => DATA <= x"32";
when x"ED6" => DATA <= x"81";
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when x"EDA" => DATA <= x"B7";
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when x"EDC" => DATA <= x"06";
when x"EDD" => DATA <= x"D6";
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when x"EDF" => DATA <= x"CD";
when x"EE0" => DATA <= x"71";
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when x"EE2" => DATA <= x"C9";
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when x"EE4" => DATA <= x"81";
when x"EE5" => DATA <= x"FF";
when x"EE6" => DATA <= x"E6";
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when x"EE8" => DATA <= x"32";
when x"EE9" => DATA <= x"81";
when x"EEA" => DATA <= x"FF";
when x"EEB" => DATA <= x"C9";
when x"EEC" => DATA <= x"3E";
when x"EED" => DATA <= x"87";
when x"EEE" => DATA <= x"CD";
when x"EEF" => DATA <= x"8E";
when x"EF0" => DATA <= x"F8";
when x"EF1" => DATA <= x"7C";
when x"EF2" => DATA <= x"FE";
when x"EF3" => DATA <= x"03";
when x"EF4" => DATA <= x"C9";
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when x"EF7" => DATA <= x"CD";
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when x"EFA" => DATA <= x"7D";
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when x"EFC" => DATA <= x"11";
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when x"EFE" => DATA <= x"32";
when x"EFF" => DATA <= x"1E";
when x"F00" => DATA <= x"FF";
when x"F01" => DATA <= x"7C";
when x"F02" => DATA <= x"32";
when x"F03" => DATA <= x"12";
when x"F04" => DATA <= x"FF";
when x"F05" => DATA <= x"32";
when x"F06" => DATA <= x"14";
when x"F07" => DATA <= x"FF";
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when x"F09" => DATA <= x"1F";
when x"F0A" => DATA <= x"FF";
when x"F0B" => DATA <= x"3C";
when x"F0C" => DATA <= x"32";
when x"F0D" => DATA <= x"1A";
when x"F0E" => DATA <= x"FF";
when x"F0F" => DATA <= x"C9";
when x"F10" => DATA <= x"1C";
when x"F11" => DATA <= x"C4";
when x"F12" => DATA <= x"48";
when x"F13" => DATA <= x"4F";
when x"F14" => DATA <= x"C1";
when x"F15" => DATA <= x"0C";
when x"F16" => DATA <= x"1C";
when x"F17" => DATA <= x"00";
when x"F18" => DATA <= x"1F";
when x"F19" => DATA <= x"4F";
when x"F1A" => DATA <= x"48";
when x"F1B" => DATA <= x"0C";
when x"F1C" => DATA <= x"1A";
when x"F1D" => DATA <= x"1F";
when x"F1E" => DATA <= x"22";
when x"F1F" => DATA <= x"28";
when x"F20" => DATA <= x"00";
when x"F21" => DATA <= x"00";
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when x"F23" => DATA <= x"28";
when x"F24" => DATA <= x"43";
when x"F25" => DATA <= x"29";
when x"F26" => DATA <= x"3B";
when x"F27" => DATA <= x"36";
when x"F28" => DATA <= x"00";
when x"F29" => DATA <= x"21";
when x"F2A" => DATA <= x"2A";
when x"F2B" => DATA <= x"3B";
when x"F2C" => DATA <= x"C3";
when x"F2D" => DATA <= x"77";
when x"F2E" => DATA <= x"19";
when x"F2F" => DATA <= x"C5";
when x"F30" => DATA <= x"E5";
when x"F31" => DATA <= x"7E";
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when x"F33" => DATA <= x"03";
when x"F34" => DATA <= x"47";
when x"F35" => DATA <= x"0E";
when x"F36" => DATA <= x"06";
when x"F37" => DATA <= x"23";
when x"F38" => DATA <= x"5E";
when x"F39" => DATA <= x"23";
when x"F3A" => DATA <= x"56";
when x"F3B" => DATA <= x"CD";
when x"F3C" => DATA <= x"48";
when x"F3D" => DATA <= x"1A";
when x"F3E" => DATA <= x"E1";
when x"F3F" => DATA <= x"C1";
when x"F40" => DATA <= x"C9";
when x"F41" => DATA <= x"53";
when x"F42" => DATA <= x"00";
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when x"F44" => DATA <= x"00";
when x"F45" => DATA <= x"00";
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when x"F48" => DATA <= x"00";
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when x"F4C" => DATA <= x"0A";
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when x"F50" => DATA <= x"00";
when x"F51" => DATA <= x"00";
when x"F52" => DATA <= x"00";
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when x"F54" => DATA <= x"00";
when x"F55" => DATA <= x"00";
when x"F56" => DATA <= x"00";
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when x"F5A" => DATA <= x"00";
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when x"F5C" => DATA <= x"00";
when x"F5D" => DATA <= x"00";
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when x"F5F" => DATA <= x"00";
when x"F60" => DATA <= x"00";
when x"F61" => DATA <= x"00";
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when x"F63" => DATA <= x"00";
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when x"F65" => DATA <= x"00";
when x"F66" => DATA <= x"00";
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when x"F6A" => DATA <= x"00";
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when x"F6C" => DATA <= x"00";
when x"F6D" => DATA <= x"00";
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when x"F6F" => DATA <= x"00";
when x"F70" => DATA <= x"00";
when x"F71" => DATA <= x"00";
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when x"F73" => DATA <= x"00";
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when x"F75" => DATA <= x"00";
when x"F76" => DATA <= x"00";
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when x"F78" => DATA <= x"00";
when x"F79" => DATA <= x"00";
when x"F7A" => DATA <= x"00";
when x"F7B" => DATA <= x"00";
when x"F7C" => DATA <= x"00";
when x"F7D" => DATA <= x"00";
when x"F7E" => DATA <= x"00";
when x"F7F" => DATA <= x"00";
when x"F80" => DATA <= x"00";
when x"F81" => DATA <= x"00";
when x"F82" => DATA <= x"00";
when x"F83" => DATA <= x"01";
when x"F84" => DATA <= x"B2";
when x"F85" => DATA <= x"FA";
when x"F86" => DATA <= x"02";
when x"F87" => DATA <= x"14";
when x"F88" => DATA <= x"95";
when x"F89" => DATA <= x"00";
when x"F8A" => DATA <= x"01";
when x"F8B" => DATA <= x"00";
when x"F8C" => DATA <= x"00";
when x"F8D" => DATA <= x"3C";
when x"F8E" => DATA <= x"1A";
when x"F8F" => DATA <= x"FF";
when x"F90" => DATA <= x"FF";
when x"F91" => DATA <= x"01";
when x"F92" => DATA <= x"00";
when x"F93" => DATA <= x"00";
when x"F94" => DATA <= x"00";
when x"F95" => DATA <= x"00";
when x"F96" => DATA <= x"00";
when x"F97" => DATA <= x"00";
when x"F98" => DATA <= x"00";
when x"F99" => DATA <= x"00";
when x"F9A" => DATA <= x"74";
when x"F9B" => DATA <= x"4C";
when x"F9C" => DATA <= x"D6";
when x"F9D" => DATA <= x"5E";
when x"F9E" => DATA <= x"C3";
when x"F9F" => DATA <= x"71";
when x"FA0" => DATA <= x"F6";
when x"FA1" => DATA <= x"C3";
when x"FA2" => DATA <= x"AE";
when x"FA3" => DATA <= x"F5";
when x"FA4" => DATA <= x"C3";
when x"FA5" => DATA <= x"5C";
when x"FA6" => DATA <= x"F5";
when x"FA7" => DATA <= x"C3";
when x"FA8" => DATA <= x"3B";
when x"FA9" => DATA <= x"F5";
when x"FAA" => DATA <= x"C3";
when x"FAB" => DATA <= x"76";
when x"FAC" => DATA <= x"F4";
when x"FAD" => DATA <= x"C3";
when x"FAE" => DATA <= x"71";
when x"FAF" => DATA <= x"F4";
when x"FB0" => DATA <= x"C3";
when x"FB1" => DATA <= x"FD";
when x"FB2" => DATA <= x"FA";
when x"FB3" => DATA <= x"C3";
when x"FB4" => DATA <= x"0E";
when x"FB5" => DATA <= x"F6";
when x"FB6" => DATA <= x"C3";
when x"FB7" => DATA <= x"0E";
when x"FB8" => DATA <= x"FE";
when x"FB9" => DATA <= x"C3";
when x"FBA" => DATA <= x"CE";
when x"FBB" => DATA <= x"F2";
when x"FBC" => DATA <= x"C3";
when x"FBD" => DATA <= x"A4";
when x"FBE" => DATA <= x"FA";
when x"FBF" => DATA <= x"C3";
when x"FC0" => DATA <= x"5E";
when x"FC1" => DATA <= x"F6";
when x"FC2" => DATA <= x"C3";
when x"FC3" => DATA <= x"1B";
when x"FC4" => DATA <= x"F6";
when x"FC5" => DATA <= x"C3";
when x"FC6" => DATA <= x"3F";
when x"FC7" => DATA <= x"F6";
when x"FC8" => DATA <= x"C3";
when x"FC9" => DATA <= x"DE";
when x"FCA" => DATA <= x"FD";
when x"FCB" => DATA <= x"C3";
when x"FCC" => DATA <= x"E8";
when x"FCD" => DATA <= x"F8";
when x"FCE" => DATA <= x"C3";
when x"FCF" => DATA <= x"D2";
when x"FD0" => DATA <= x"F9";
when x"FD1" => DATA <= x"C3";
when x"FD2" => DATA <= x"4E";
when x"FD3" => DATA <= x"FA";
when x"FD4" => DATA <= x"C3";
when x"FD5" => DATA <= x"FC";
when x"FD6" => DATA <= x"F9";
when x"FD7" => DATA <= x"C3";
when x"FD8" => DATA <= x"F0";
when x"FD9" => DATA <= x"F9";
when x"FDA" => DATA <= x"C3";
when x"FDB" => DATA <= x"9F";
when x"FDC" => DATA <= x"F9";
when x"FDD" => DATA <= x"C3";
when x"FDE" => DATA <= x"10";
when x"FDF" => DATA <= x"FA";
when x"FE0" => DATA <= x"C3";
when x"FE1" => DATA <= x"90";
when x"FE2" => DATA <= x"F6";
when x"FE3" => DATA <= x"FE";
when x"FE4" => DATA <= x"0D";
when x"FE5" => DATA <= x"20";
when x"FE6" => DATA <= x"07";
when x"FE7" => DATA <= x"3E";
when x"FE8" => DATA <= x"0A";
when x"FE9" => DATA <= x"CD";
when x"FEA" => DATA <= x"EE";
when x"FEB" => DATA <= x"FF";
when x"FEC" => DATA <= x"3E";
when x"FED" => DATA <= x"0D";
when x"FEE" => DATA <= x"C3";
when x"FEF" => DATA <= x"71";
when x"FF0" => DATA <= x"F6";
when x"FF1" => DATA <= x"C3";
when x"FF2" => DATA <= x"EF";
when x"FF3" => DATA <= x"F8";
when x"FF4" => DATA <= x"C3";
when x"FF5" => DATA <= x"8E";
when x"FF6" => DATA <= x"F8";
when x"FF7" => DATA <= x"C3";
when x"FF8" => DATA <= x"B7";
when x"FF9" => DATA <= x"F6";
when x"FFA" => DATA <= x"AC";
when x"FFB" => DATA <= x"FA";
when x"FFC" => DATA <= x"70";
when x"FFD" => DATA <= x"F6";
when x"FFE" => DATA <= x"82";
when x"FFF" => DATA <= x"FA";
when others => DATA <= (others => '0');
end case;
end process;
end RTL;
| gpl-3.0 | c22c2897ff7c2a9e3cbfbf87116d9ac4 | 0.357965 | 2.930967 | false | false | false | false |
ggaray/nicsim-vhd | traffgen.vhd | 1 | 3,455 | -- NICSim-vhd: A VHDL-based modelling and simulation of NIC's buffers
-- Copyright (C) 2013 Godofredo R. Garay <godofredo.garay (-at-) gmail.com>
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
use std.textio.all;
entity traffgen is
port (
pktarrival : out bit := '0';
pktsize : out integer := 0; -- in bytes
ethclk : in bit
);
end traffgen;
architecture beh of traffgen is
--------------- Input Workload Parameters ---------------
--constant packet_size_in_bytes : integer := 72; -- Minimum (Ethernet)
constant packet_size_in_bytes : integer := 1526; -- Maximum (Ethernet)
--constant packet_size_in_bytes : integer := 9026; -- Jumbo Frames
constant ifg : integer := 96; -- Inter Frame Gap in bit times
--------------- Variables Declarations ---------------
-- Buffer Memory
constant eth_trace_size : integer := 5;
type pktsize_array is
array (integer range 1 to eth_trace_size) of integer;
shared variable pktsize_trace : pktsize_array;
type inter_pkt_gap_array is
array (integer range 1 to eth_trace_size) of time;
shared variable inter_pkt_gap_trace : inter_pkt_gap_array;
begin
traffgen_fsm: process
type traffgen_state is (initiating_pktarrival_pulse_generation,
ending_pktarrival_pulse_generation,
waiting_packet_time,
waiting_ifg);
variable state : traffgen_state := initiating_pktarrival_pulse_generation;
variable next_state : traffgen_state := initiating_pktarrival_pulse_generation;
variable bit_time_counter : integer := packet_size_in_bytes * 8;
begin
wait until ethclk'event and ethclk = '1';
case state is
when initiating_pktarrival_pulse_generation =>
pktarrival <= '1';
pktsize <= packet_size_in_bytes;
--bit_time_counter := packet_size_in_bytes * 8;
bit_time_counter := bit_time_counter - 1;
next_state := ending_pktarrival_pulse_generation;
when ending_pktarrival_pulse_generation =>
pktarrival <= '0';
bit_time_counter := bit_time_counter - 1;
next_state := waiting_packet_time;
when waiting_packet_time =>
if bit_time_counter = 0
then bit_time_counter := ifg;
bit_time_counter := bit_time_counter - 1;
next_state := waiting_ifg;
else bit_time_counter := bit_time_counter - 1;
next_state := waiting_packet_time;
end if;
when waiting_ifg =>
if bit_time_counter = 0
then bit_time_counter := packet_size_in_bytes * 8;
pktarrival <= '1';
bit_time_counter := bit_time_counter - 1;
next_state := ending_pktarrival_pulse_generation;
else bit_time_counter := bit_time_counter - 1;
next_state := waiting_ifg;
end if;
end case;
state := next_state;
end process traffgen_fsm;
end architecture beh;
| gpl-3.0 | b2a98e00670fa06436fa23f8144266f4 | 0.654414 | 3.303059 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-minimal/leon3mp.vhd | 1 | 10,495 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2013 Aeroflex Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.jtag.all;
--pragma translate_off
use gaisler.sim.all;
--pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH
);
port (
clk : in std_ulogic; -- FPGA main clock input
-- Buttons & LEDs
btnCpuResetn : in std_ulogic; -- Reset button
Led : out std_logic_vector(15 downto 0);
-- Onboard Cellular RAM
RamOE : out std_ulogic;
RamWE : out std_ulogic;
RamAdv : out std_ulogic;
RamCE : out std_ulogic;
RamClk : out std_ulogic;
RamCRE : out std_ulogic;
RamLB : out std_ulogic;
RamUB : out std_ulogic;
address : out std_logic_vector(22 downto 0);
data : inout std_logic_vector(15 downto 0);
-- USB-RS232 interface
RsRx : in std_logic;
RsTx : out std_logic
);
end;
architecture rtl of leon3mp is
signal vcc : std_logic;
signal gnd : std_logic;
-- Memory controler signals
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
-- AMBA bus signals
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to 0);
signal irqo : irq_out_vector(0 to 0);
signal dbgi : l3_debug_in_vector(0 to 0);
signal dbgo : l3_debug_out_vector(0 to 0);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ndsuact : std_ulogic;
signal gpti : gptimer_in_type;
signal clkm, rstn : std_ulogic;
signal tck, tms, tdi, tdo : std_ulogic;
signal rstraw : std_logic;
signal lock : std_logic;
-- RS232 APB Uart (unconnected)
signal rxd1 : std_logic;
signal txd1 : std_logic;
attribute keep : boolean;
attribute keep of lock : signal is true;
attribute keep of clkm : signal is true;
constant clock_mult : integer := 10; -- Clock multiplier
constant clock_div : integer := 20; -- Clock divider
constant BOARD_FREQ : integer := 100000; -- CLK input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * clock_mult / clock_div; -- CPU freq in KHz
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1';
gnd <= '0';
cgi.pllctrl <= "00";
cgi.pllrst <= rstraw;
rst0 : rstgen generic map (acthigh => 0)
port map (btnCpuResetn, clkm, lock, rstn, rstraw);
lock <= cgo.clklock;
-- clock generator
clkgen0 : clkgen
generic map (fabtech, clock_mult, clock_div, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (clk, gnd, clkm, open, open, open, open, cgi, cgo, open, open, open);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl
generic map (ioen => 1, nahbm => 4, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
-- LEON3 processor
u0 : leon3s
generic map (hindex=>0, fabtech=>fabtech, memtech=>memtech, dsu=>1, fpu=>0, v8=>2,
mac=>0, isetsize=>8, dsetsize=>8,icen=>1, dcen=>1,tbuf=>2)
port map (clkm, rstn, ahbmi, ahbmo(0), ahbsi, ahbso, irqi(0), irqo(0), dbgi(0), dbgo(0));
-- LEON3 Debug Support Unit
dsu0 : dsu3
generic map (hindex => 2, ncpu => 1, tech => memtech, irq => 0, kbytes => 2)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
-- Debug UART
dcom0 : ahbuart
generic map (hindex => 1, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(1));
dsurx_pad : inpad generic map (tech => padtech) port map (RsRx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (RsTx, duo.txd);
led(0) <= not dui.rxd;
led(1) <= not duo.txd;
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => 3)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(3),
open, open, open, open, open, open, open, gnd);
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
-- LEON2 memory controller
sr1 : mctrl generic map (hindex => 5, pindex => 0, paddr => 0, rommask => 0,
iomask => 0, ram8 => 0, ram16 => 1,srbanks=>1)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(5), apbi, apbo(0), wpo, open);
memi.brdyn <= '1';
memi.bexcn <= '1';
memi.writen <= '1';
memi.wrn <= "1111";
memi.bwidth <= "01"; -- Sets data bus width for PROM accesses.
-- Bidirectional data bus
bdr : iopadv generic map (tech => padtech, width => 8)
port map (data(7 downto 0), memo.data(23 downto 16),
memo.bdrive(1), memi.data(23 downto 16));
bdr2 : iopadv generic map (tech => padtech, width => 8)
port map (data(15 downto 8), memo.data(31 downto 24),
memo.bdrive(0), memi.data(31 downto 24));
-- Out signals to memory
addr_pad : outpadv generic map (tech => padtech, width => 23) -- Address bus
port map (address, memo.address(23 downto 1));
oen_pad : outpad generic map (tech => padtech) -- Output Enable
port map (RamOE, memo.oen);
cs_pad : outpad generic map (tech => padtech) -- SRAM Chip select
port map (RamCE, memo.ramsn(0));
lb_pad : outpad generic map (tech => padtech)
port map (RamLB, memo.mben(0));
ub_pad : outpad generic map (tech => padtech)
port map (RamUB, memo.mben(1));
wri_pad : outpad generic map (tech => padtech) -- Write enable
port map (RamWE, memo.writen);
RamCRE <= '0'; -- Special SRAM signals specific
RamClk <= '0'; -- to Nexys4 board
RamAdv <= '0';
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- APB Bridge
generic map (hindex => 1, haddr => 16#800#)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
irqctrl0 : irqmp -- Interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => 1)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
timer0 : gptimer -- Time Unit
generic map (pindex => 3, paddr => 3, pirq => 8,
sepirq => 1, ntimers => 2)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti <= gpti_dhalt_drive(dsuo.tstop);
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => 1)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1;
u1i.ctsn <= '0';
u1i.extclk <= '0';
txd1 <= u1o.txd;
-----------------------------------------------------------------------
-- Test report module, only used for simulation ----------------------
-----------------------------------------------------------------------
--pragma translate_off
test0 : ahbrep generic map (hindex => 4, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(4));
--pragma translate_on
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end rtl;
| gpl-3.0 | e21ad4d360b1ff6a04795a7e5fdf7ea8 | 0.515388 | 4.052124 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/stratixiii/clkgen_stratixiii.vhd | 1 | 7,261 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library altera_mf;
use altera_mf.altpll;
-- pragma translate_on
entity stratix3_pll is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic
);
end;
architecture rtl of stratix3_pll is
component altpll
generic (
intended_device_family : string := "Stratix III" ;
operation_mode : string := "NORMAL" ;
compensate_clock : string := "CLK0";
inclk0_input_frequency : positive;
width_clock : positive := 10;
clk0_multiply_by : positive := 1;
clk0_divide_by : positive := 1;
clk1_multiply_by : positive := 1;
clk1_divide_by : positive := 1;
clk2_multiply_by : positive := 1;
clk2_divide_by : positive := 1
);
port (
inclk : in std_logic_vector(1 downto 0);
clkena : in std_logic_vector(5 downto 0);
clk : out std_logic_vector(width_clock-1 downto 0);
locked : out std_logic
);
end component;
signal clkena : std_logic_vector (5 downto 0);
signal clkout : std_logic_vector (9 downto 0);
signal inclk : std_logic_vector (1 downto 0);
signal fb : std_logic;
constant clk_period : integer := 1000000000/clk_freq;
constant CLK_MUL2X : integer := clk_mul * 2;
begin
clkena(5 downto 3) <= (others => '0');
clkena(0) <= '1';
clkena(1) <= '1' when sdramen = 1 else '0';
clkena(2) <= '1' when clk2xen = 1 else '0';
inclk <= '0' & inclk0;
c0 <= clkout(0); c0_2x <= clkout(2); e0 <= clkout(1);
sden : if sdramen = 1 generate
altpll0 : altpll
generic map (
intended_device_family => "Stratix III",
--operation_mode => "ZERO_DELAY_BUFFER", inclk0_input_frequency => clk_period,
operation_mode => "NORMAL", inclk0_input_frequency => clk_period,
width_clock => 10, compensate_clock => "CLK1",
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => clk_mul, clk1_divide_by => clk_div,
clk2_multiply_by => CLK_MUL2X, clk2_divide_by => clk_div)
port map ( clkena => clkena, inclk => inclk,
clk => clkout, locked => locked);
end generate;
nosd : if sdramen = 0 generate
altpll0 : altpll
generic map (
intended_device_family => "Stratix III",
operation_mode => "NORMAL", inclk0_input_frequency => clk_period,
width_clock => 10,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => clk_mul, clk1_divide_by => clk_div,
clk2_multiply_by => CLK_MUL2X, clk2_divide_by => clk_div)
port map ( clkena => clkena, inclk => inclk,
clk => clkout, locked => locked);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library altera_mf;
library grlib;
use grlib.stdlib.all;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkgen_stratixiii is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0;
tech : integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end;
architecture rtl of clkgen_stratixiii is
constant VERSION : integer := 1;
constant CLKIN_PERIOD : integer := 20;
signal clk_i : std_logic;
signal clkint, pciclkint : std_logic;
signal pllclk, pllclkn : std_logic; -- generated clocks
signal s_clk : std_logic;
component stratix3_pll
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic);
end component;
begin
cgo.pcilock <= '1';
-- c0 : if (PCISYSCLK = 0) generate
-- Clkint <= Clkin;
-- end generate;
-- c1 : if (PCISYSCLK = 1) generate
-- Clkint <= pciclkin;
-- end generate;
-- c2 : if (PCIEN = 1) generate
-- p0 : if (PCIDLL = 1) generate
-- pciclkint <= pciclkin;
-- pciclk <= pciclkint;
-- end generate;
-- p1 : if (PCIDLL = 0) generate
-- u0 : if (PCISYSCLK = 0) generate
-- pciclkint <= pciclkin;
-- end generate;
-- pciclk <= clk_i when (PCISYSCLK = 1) else pciclkint;
-- end generate;
-- end generate;
-- c3 : if (PCIEN = 0) generate
-- pciclk <= Clkint;
-- end generate;
c0: if (PCISYSCLK = 0) or (PCIEN = 0) generate
clkint <= clkin;
end generate c0;
c1: if PCIEN /= 0 generate
d0: if PCISYSCLK = 1 generate
clkint <= pciclkin;
end generate d0;
pciclk <= pciclkin;
end generate c1;
c2: if PCIEN = 0 generate
pciclk <= '0';
end generate c2;
sdclk_pll : stratix3_pll
generic map (clk_mul, clk_div, freq, clk2xen, sdramen)
port map ( inclk0 => clkint, e0 => sdclk, c0 => s_clk, c0_2x => clk2x,
locked => cgo.clklock);
clk <= s_clk;
clkn <= not s_clk;
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_stratixiii" & ": altpll sdram/pci clock generator, version " & tost(VERSION),
"clkgen_stratixiii" & ": Frequency " & tost(freq) & " KHz, PLL scaler " & tost(clk_mul) & "/" & tost(clk_div));
-- pragma translate_on
end;
| gpl-3.0 | 0efa4bc170de9d40a61453fa8b5810f8 | 0.586007 | 3.492544 | false | false | false | false |
richjyoung/lfsr-package | src/LFSR/pulse.vhd | 1 | 1,162 | library IEEE, LFSR;
use IEEE.std_logic_1164.all;
use LFSR.lfsr.all;
--------------------------------------------------------------------------------
entity pulse is
generic (
G_lfsr_width : natural := 17;
G_period : natural := 10000
);
port(
CLK : in std_logic;
RESET : in std_logic;
PULSE : out std_logic
);
end pulse;
--------------------------------------------------------------------------------
architecture rtl of pulse is
subtype T_LFSR is std_logic_vector(G_lfsr_width-1 downto 0);
constant C_ZERO : T_LFSR := (others => '0');
signal LFSR : T_LFSR;
constant C_LFSR_RESET : T_LFSR := lfsr_evaluate(LFSR, G_period-1);
begin
PULSE <= '1' when LFSR = C_ZERO else '0';
lfsr_proc: process (CLK) is
begin
if rising_edge(CLK) then
if RESET = '1' then
LFSR <= C_ZERO; -- XNOR LFSR requires zero reset
else
lfsr_advance(LFSR, C_LFSR_RESET);
end if;
end if;
end process lfsr_proc;
end rtl; | mit | 8fecb784be4b98504d107e1fec09f986 | 0.433735 | 4.25641 | false | false | false | false |
richjyoung/lfsr-package | test/LFSR_TB/pulse_tester.vhd | 1 | 1,702 | library IEEE, JUNIT_TB, LFSR, STD;
use IEEE.std_logic_1164.all;
use JUNIT_TB.junit.all;
use LFSR.lfsr_components.all;
use STD.textio.all;
--------------------------------------------------------------------------------
entity pulse_tester is
generic (
G_lfsr_width : natural := 3;
G_period : natural := 7;
G_expected : time := 70 ns
);
port(
CLK : in std_logic;
RESET : in std_logic;
GO : in std_logic;
DONE : out std_logic;
PASS_nFAIL : out std_logic;
RUNTIME : out time
);
end pulse_tester;
--------------------------------------------------------------------------------
architecture tb of pulse_tester is
signal P : std_logic;
begin
stim_proc: process
variable V_STARTED : time;
variable V_FINISHED : time;
variable V_RUNTIME : time;
begin
DONE <= '0';
PASS_nFAIL <= '0';
wait until GO = '1';
wait until rising_edge(P);
V_STARTED := now;
wait until rising_edge(P);
V_FINISHED := now;
V_RUNTIME := V_FINISHED - V_STARTED;
RUNTIME <= V_RUNTIME;
if V_RUNTIME = G_expected then
PASS_nFAIL <= '1';
end if;
DONE <= '1';
wait;
end process stim_proc;
U_UUT: pulse
generic map (
G_lfsr_width => G_lfsr_width,
G_period => G_period
)
port map (
CLK => CLK,
RESET => RESET,
PULSE => P
);
end tb; | mit | 9f5c5b2d9d998d8c14863c367c0e6992 | 0.410693 | 4.131068 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-xilinx-ml40x/leon3mp.vhd | 1 | 28,095 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.i2c.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.spacewire.all;
use gaisler.ddrpkg.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
sys_rst_in : in std_ulogic;
sys_clk : in std_ulogic; -- 100 MHz main clock
sysace_clk_in : in std_ulogic; -- System ACE clock
plb_error : out std_logic; -- IU error mode
opb_error : out std_logic; -- DSU active
flash_a23 : out std_ulogic;
sram_flash_addr : out std_logic_vector(22 downto 0);
sram_flash_data : inout std_logic_vector(31 downto 0);
sram_cen : out std_logic;
sram_bw : out std_logic_vector (0 to 3);
sram_flash_oe_n : out std_ulogic;
sram_flash_we_n : out std_ulogic;
flash_ce : out std_logic;
sram_clk : out std_ulogic;
sram_clk_fb : in std_ulogic;
sram_mode : out std_ulogic;
sram_adv_ld_n : out std_ulogic;
--pragma translate_off
iosn : out std_ulogic;
--pragma translate_on
ddr_clk : out std_logic;
ddr_clkb : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic;
ddr_csb : out std_logic;
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (3 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (3 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (12 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (31 downto 0); -- ddr data
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
gpio : inout std_logic_vector(26 downto 0); -- I/O port
phy_gtx_clk : out std_logic;
phy_mii_data: inout std_logic; -- ethernet PHY interface
phy_tx_clk : in std_ulogic;
phy_rx_clk : in std_ulogic;
phy_rx_data : in std_logic_vector(7 downto 0);
phy_dv : in std_ulogic;
phy_rx_er : in std_ulogic;
phy_col : in std_ulogic;
phy_crs : in std_ulogic;
phy_int_n : in std_ulogic;
phy_tx_data : out std_logic_vector(7 downto 0);
phy_tx_en : out std_ulogic;
phy_tx_er : out std_ulogic;
phy_mii_clk : out std_ulogic;
phy_rst_n : out std_ulogic;
ps2_keyb_clk : inout std_logic;
ps2_keyb_data : inout std_logic;
ps2_mouse_clk : inout std_logic;
ps2_mouse_data : inout std_logic;
tft_lcd_clk : out std_ulogic;
vid_blankn : out std_ulogic;
vid_syncn : out std_ulogic;
vid_hsync : out std_ulogic;
vid_vsync : out std_ulogic;
vid_r : out std_logic_vector(7 downto 0);
vid_g : out std_logic_vector(7 downto 0);
vid_b : out std_logic_vector(7 downto 0);
usb_csn : out std_logic;
iic_scl : inout std_ulogic;
iic_sda : inout std_ulogic;
sace_usb_a : out std_logic_vector(6 downto 0);
sace_mpce : out std_ulogic;
sace_usb_d : inout std_logic_vector(15 downto 0);
sace_usb_oen : out std_ulogic;
sace_usb_wen : out std_ulogic;
sysace_mpirq : in std_ulogic
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := NCPU+CFG_AHB_UART
+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdctrl_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, srclkl : std_ulogic;
signal clkm_90, clkm_180, clkm_270 : std_ulogic;
signal cgi, cgi2 : clkgen_in_type;
signal cgo, cgo2 : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal clklock, lock, lclk, clkml, rst, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal ddrclk, ddrrst : std_ulogic;
signal ethclk, egtx_clk_fb : std_ulogic;
signal egtx_clk, legtx_clk, l2egtx_clk : std_ulogic;
signal kbdi : ps2_in_type;
signal kbdo : ps2_out_type;
signal moui : ps2_in_type;
signal mouo : ps2_out_type;
signal vgao : apbvga_out_type;
signal clk_sel : std_logic_vector(1 downto 0);
signal clkval : std_logic_vector(1 downto 0);
signal clkvga, clk1x, video_clk, dac_clk : std_ulogic;
signal i2ci : i2c_in_type;
signal i2co : i2c_out_type;
constant BOARD_FREQ : integer := 100000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant I2C_FILTER : integer := (CPU_FREQ*5+50000)/100000+1;
constant IOAEN : integer := CFG_DDRSP;
signal stati : ahbstat_in_type;
signal ddrclkfb, ssrclkfb, ddr_clkl, ddr_clk90l, ddr_clknl, ddr_clk270l : std_ulogic;
signal ddr_clkv : std_logic_vector(2 downto 0);
signal ddr_clkbv : std_logic_vector(2 downto 0);
signal ddr_ckev : std_logic_vector(1 downto 0);
signal ddr_csbv : std_logic_vector(1 downto 0);
signal ddr_adl : std_logic_vector (13 downto 0);
signal clkace : std_ulogic;
signal acei : gracectrl_in_type;
signal aceo : gracectrl_out_type;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of lock : signal is true;
attribute syn_preserve of lock : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute syn_keep of egtx_clk : signal is true;
attribute syn_preserve of egtx_clk : signal is true;
attribute keep : boolean;
attribute keep of lock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
attribute keep of egtx_clk : signal is true;
attribute syn_noprune : boolean;
attribute syn_noprune of sysace_clk_in_pad : label is true;
signal romsn : std_ulogic;
constant SPW_LOOP_BACK : integer := 0;
begin
usb_csn <= '1';
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; cgi.pllref <= ssrclkfb;
ssrref_pad : clkpad generic map (tech => padtech)
port map (sram_clk_fb, ssrclkfb);
clk_pad : clkpad generic map (tech => padtech, arch => 2)
port map (sys_clk, lclk);
srclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (sram_clk, srclkl);
sysace_clk_in_pad : clkpad generic map (tech => padtech)
port map (sysace_clk_in, clkace);
clkgen0 : clkgen -- system clock generator
generic map (CFG_FABTECH, CFG_CLKMUL, CFG_CLKDIV, 1, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd(0), clkm, open, open, srclkl, open, cgi, cgo, open, clk1x);
clkgen1 : clkgen -- Ethernet 1G PHY clock generator
generic map (CFG_FABTECH, 5, 4, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd(0), egtx_clk, open, open, open, open, cgi2, cgo2);
cgi2.pllctrl <= "00"; cgi2.pllrst <= rstraw; --cgi2.pllref <= egtx_clk_fb;
egtx_clk_pad : outpad generic map (tech => padtech)
port map (phy_gtx_clk, egtx_clk);
resetn_pad : inpad generic map (tech => padtech) port map (sys_rst_in, rst);
rst0 : rstgen -- reset generator
port map (rst, clkm, clklock, rstn, rstraw);
clklock <= lock and cgo2.clklock;
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, devid => XILINX_ML401,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (plb_error, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
-- dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
dsui.enable <= '1';
-- dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsui.break <= gpioo.val(11); -- South Button
-- dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, ndsuact);
dsuact_pad : outpad generic map (tech => padtech) port map (opb_error, ndsuact);
ndsuact <= not dsuo.active;
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(NCPU));
-- dsurx_pad : inpad generic map (tech => padtech) port map (rxd1, dui.rxd);
-- dsutx_pad : outpad generic map (tech => padtech) port map (txd1, duo.txd);
dui.rxd <= rxd1 when gpioo.val(21) = '1' else '1';
end generate;
txd1 <= duo.txd when gpioo.val(21) = '1' else u1o.txd;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10";
memi.brdyn <= '1'; memi.bexcn <= '1';
ssr0 : if CFG_SSCTRL = 1 generate
ssrctrl0 : ssrctrl generic map (hindex => 3, pindex => 0, ramaddr => 16#600#)
port map (rstn, clkm, ahbsi, ahbso(3), apbi, apbo(0), memi, memo);
end generate;
mctrl0 : if CFG_MCTRL_LEON2 = 1 generate
mctrl0 : mctrl generic map (hindex => 3, pindex => 0,
ramaddr => 16#C00#, rammask => 16#FF0#,
paddr => 0, srbanks => 1, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN,
invclk => CFG_MCTRL_INVCLK, sepbus => CFG_MCTRL_SEPBUS)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(3), apbi, apbo(0), wpo, open);
end generate;
romsn <= not memo.romsn(0);
sram_adv_ld_n_pad : outpad generic map (tech => padtech)
port map (sram_adv_ld_n, gnd(0));
sram_mode_pad : outpad generic map (tech => padtech)
port map (sram_mode, gnd(0));
addr_pad : outpadv generic map (width => 23, tech => padtech)
port map (sram_flash_addr, memo.address(24 downto 2));
addr23_pad : outpad generic map (tech => padtech)
port map (flash_a23, gnd(0));
rams_pad : outpad generic map ( tech => padtech)
port map (sram_cen, memo.ramsn(0));
roms_pad : outpad generic map (tech => padtech)
port map (flash_ce, romsn);
oen_pad : outpad generic map (tech => padtech)
port map (sram_flash_oe_n, memo.oen);
--pragma translate_off
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
--pragma translate_on
rwen_pad : outpadv generic map (width => 4, tech => padtech)
port map (sram_bw, memo.wrn);
wri_pad : outpad generic map (tech => padtech)
port map (sram_flash_we_n, memo.writen);
data_pads : iopadvv generic map (tech => padtech, width => 32)
port map (sram_flash_data, memo.data, memo.vbdrive, memi.data);
ddrsp0 : if (CFG_DDRSP /= 0) generate
-- phyiconf => 1 = no diff pads for DDR clock pairs
ddrc0 : ddrspa generic map ( fabtech => CFG_FABTECH, memtech => memtech,
hindex => 0, haddr => 16#400#, hmask => 16#F00#, ioaddr => 1,
pwron => CFG_DDRSP_INIT, MHz => BOARD_FREQ/1000,
clkmul => CFG_DDRSP_FREQ/10, clkdiv => 10, ahbfreq => CPU_FREQ/1000,
col => CFG_DDRSP_COL, Mbyte => CFG_DDRSP_SIZE, ddrbits => 32,
phyiconf => 1)
port map (
rst, rstn, lclk, clkm, lock, clkml, clkml, ahbsi, ahbso(0),
ddr_clkv, ddr_clkbv, open, ddr_clk_fb,
ddr_ckev, ddr_csbv, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_adl, ddr_ba, ddr_dq);
ddr_ad <= ddr_adl(12 downto 0);
ddr_clk <= ddr_clkv(0); ddr_clkb <= ddr_clkbv(0);
ddr_cke <= ddr_ckev(0); ddr_csb <= ddr_csbv(0);
end generate;
noddr : if (CFG_DDRSP = 0) generate lock <= '1'; end generate;
----------------------------------------------------------------------
--- System ACE I/F Controller ---------------------------------------
----------------------------------------------------------------------
grace: if CFG_GRACECTRL = 1 generate
grace0 : gracectrl generic map (hindex => 4, hirq => 10,
haddr => 16#002#, hmask => 16#fff#, split => CFG_SPLIT)
port map (rstn, clkm, clkace, ahbsi, ahbso(4), acei, aceo);
end generate;
nograce: if CFG_GRACECTRL /= 1 generate
aceo <= gracectrl_none;
end generate;
sace_usb_a_pads : outpadv generic map (width => 7, tech => padtech)
port map (sace_usb_a, aceo.addr);
sace_mpce_pad : outpad generic map (tech => padtech)
port map (sace_mpce, aceo.cen);
sace_usb_d_pads : iopadv generic map (tech => padtech, width => 16)
port map (sace_usb_d, aceo.do, aceo.doen, acei.di);
sace_usb_oen_pad : outpad generic map (tech => padtech)
port map (sace_usb_oen, aceo.oen);
sace_usb_wen_pad : outpad generic map (tech => padtech)
port map (sace_usb_wen, aceo.wen);
sysace_mpirq_pad : inpad generic map (tech => padtech)
port map (sysace_mpirq, acei.irq);
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0'; u1i.ctsn <= '0';
u1i.rxd <= rxd1 when gpioo.val(21) = '0' else '1';
end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti <= gpti_dhalt_drive(dsuo.tstop);
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
kbd : if CFG_KBD_ENABLE /= 0 generate
ps21 : apbps2 generic map(pindex => 4, paddr => 4, pirq => 4)
port map(rstn, clkm, apbi, apbo(4), moui, mouo);
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
end generate;
nokbd : if CFG_KBD_ENABLE = 0 generate apbo(5) <= apb_none; kbdo <= ps2o_none; end generate;
kbdclk_pad : iopad generic map (tech => padtech)
port map (ps2_keyb_clk,kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
kbdata_pad : iopad generic map (tech => padtech)
port map (ps2_keyb_data, kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
mouclk_pad : iopad generic map (tech => padtech)
port map (ps2_mouse_clk, mouo.ps2_clk_o, mouo.ps2_clk_oe, moui.ps2_clk_i);
mouata_pad : iopad generic map (tech => padtech)
port map (ps2_mouse_data, mouo.ps2_data_o, mouo.ps2_data_oe, moui.ps2_data_i);
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, ethclk, apbi, apbo(6), vgao);
clk_sel <= "00";
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
clk0 => 4*(1000000000/BOARD_FREQ), clk1 => 2*(1000000000/BOARD_FREQ),
clk2 => 1000000000/CPU_FREQ, burstlen => 6)
port map(rstn, clkm, clkvga, apbi, apbo(6), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), clk_sel);
end generate;
vgadiv : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) /= 0 generate
clkdiv : process(clk1x, rstn)
begin
if rstn = '0' then clkval <= "00";
elsif rising_edge(clk1x) then
clkval <= clkval + 1;
end if;
end process;
video_clk <= clkval(1) when clk_sel = "00" else clkval(0) when clk_sel = "01" else clkm;
b1 : techbuf generic map (2, CFG_FABTECH) port map (video_clk, clkvga);
dac_clk <= not clkvga;
end generate;
novga : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) = 0 generate
apbo(6) <= apb_none; vgao <= vgao_none;
end generate;
blank_pad : outpad generic map (tech => padtech)
port map (vid_blankn, vgao.blank);
comp_sync_pad : outpad generic map (tech => padtech)
port map (vid_syncn, vgao.comp_sync);
vert_sync_pad : outpad generic map (tech => padtech)
port map (vid_vsync, vgao.vsync);
horiz_sync_pad : outpad generic map (tech => padtech)
port map (vid_hsync, vgao.hsync);
video_out_r_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_r, vgao.video_out_r);
video_out_g_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_g, vgao.video_out_g);
video_out_b_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_b, vgao.video_out_b);
video_clock_pad : outpad generic map ( tech => padtech)
port map (tft_lcd_clk, dac_clk);
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 8, paddr => 8, imask => 16#00F0#, nbits => 27)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(8),
gpioi => gpioi, gpioo => gpioo);
gpio_pads : iopadvv generic map (tech => padtech, width => 27)
port map (gpio, gpioo.dout(26 downto 0), gpioo.oen(26 downto 0),
gpioi.din(26 downto 0));
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
stati <= ahbstat_in_none;
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master
i2c0 : i2cmst
generic map (pindex => 12, paddr => 12, pmask => 16#FFF#,
pirq => 11, filter => I2C_FILTER)
port map (rstn, clkm, apbi, apbo(12), i2ci, i2co);
i2c_scl_pad : iopad generic map (tech => padtech)
port map (iic_scl, i2co.scl, i2co.scloen, i2ci.scl);
i2c_sda_pad : iopad generic map (tech => padtech)
port map (iic_sda, i2co.sda, i2co.sdaoen, i2ci.sda);
end generate i2cm;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth1 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(hindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 11, paddr => 11, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, enable_mdint => 1,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
apbi => apbi, apbo => apbo(11), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (phy_mii_data, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (phy_tx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (phy_rx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 8)
port map (phy_rx_data, ethi.rxd(7 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (phy_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (phy_rx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (phy_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (phy_crs, ethi.rx_crs);
emdint_pad : inpad generic map (tech => padtech)
port map (phy_int_n, ethi.mdint);
etxd_pad : outpadv generic map (tech => padtech, width => 8)
port map (phy_tx_data, etho.txd(7 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( phy_tx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (phy_tx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (phy_mii_clk, etho.mdc);
erst_pad : outpad generic map (tech => padtech)
port map (phy_rst_n, rstn);
ethi.gtx_clk <= egtx_clk;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- AHB DEBUG --------------------------------------------------------
-----------------------------------------------------------------------
-- dma0 : ahbdma
-- generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG,
-- pindex => 13, paddr => 13, dbuf => 6)
-- port map (rstn, clkm, apbi, apbo(13), ahbmi,
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG));
-- at0 : ahbtrace
-- generic map ( hindex => 7, ioaddr => 16#200#, iomask => 16#E00#,
-- tech => memtech, irq => 0, kbytes => 8)
-- port map ( rstn, clkm, ahbmi, ahbsi, ahbso(7));
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (NCPU+CFG_AHB_UART+CFG_ETH+CFG_AHB_ETH+CFG_AHB_JTAG) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Avnet ML401 (Virtex4 LX25) Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech), mdel => 1
);
-- pragma translate_on
end;
| gpl-3.0 | d5cb9170cb80b456eb65b5e0a621f079 | 0.579818 | 3.409174 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/greth/greth_mb.vhd | 1 | 14,091 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: greth_mb
-- File: greth_mb.vhd
-- Author: Marko Isomaki
-- Description: Ethernet Media Access Controller with Ethernet Debug
-- Communication Link and dual AHB master interfaces
------------------------------------------------------------------------------
library ieee;
library grlib;
library gaisler;
use ieee.std_logic_1164.all;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use gaisler.net.all;
use gaisler.ethernet_mac.all;
library eth;
use eth.ethcomp.all;
entity greth_mb is
generic(
hindex : integer := 0;
ehindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 512 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
rmii : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 2 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
edclsepahb : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
maxsize : integer;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbmi2 : in ahb_mst_in_type;
ahbmo2 : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ethi : in eth_in_type;
etho : out eth_out_type
);
end entity;
architecture rtl of greth_mb is
function getfifosize(edcl, fifosize, ebufsize : in integer) return integer is
begin
if (edcl /= 0) and (ebufsize > fifosize) then
return ebufsize;
else
return fifosize;
end if;
end function;
constant fabits : integer := log2(fifosize);
type szvct is array (0 to 6) of integer;
constant ebuf : szvct := (64, 128, 128, 256, 256, 256, 256);
constant eabits : integer := log2(edclbufsz) + 8;
constant bufsize : std_logic_vector(2 downto 0) :=
conv_std_logic_vector(log2(edclbufsz), 3);
constant ebufsize : integer := ebuf(log2(edclbufsz));
constant txfifosize : integer := getfifosize(edcl, fifosize, ebufsize);
constant txfabits : integer := log2(txfifosize);
constant REVISION : amba_version_type := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_ETHMAC, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_ETHMAC, 0, revision, 0),
others => zero32);
constant ehconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_EDCLMST, 0, REVISION, 0),
others => zero32);
signal irq : std_ulogic;
--rx ahb fifo
signal rxrenable : std_ulogic;
signal rxraddress : std_logic_vector(10 downto 0);
signal rxwrite : std_ulogic;
signal rxwdata : std_logic_vector(31 downto 0);
signal rxwaddress : std_logic_vector(10 downto 0);
signal rxrdata : std_logic_vector(31 downto 0);
--tx ahb fifo
signal txrenable : std_ulogic;
signal txraddress : std_logic_vector(10 downto 0);
signal txwrite : std_ulogic;
signal txwdata : std_logic_vector(31 downto 0);
signal txwaddress : std_logic_vector(10 downto 0);
signal txrdata : std_logic_vector(31 downto 0);
--edcl buf
signal erenable : std_ulogic;
signal eraddress : std_logic_vector(15 downto 0);
signal ewritem : std_ulogic;
signal ewritel : std_ulogic;
signal ewaddressm : std_logic_vector(15 downto 0);
signal ewaddressl : std_logic_vector(15 downto 0);
signal ewdata : std_logic_vector(31 downto 0);
signal erdata : std_logic_vector(31 downto 0);
signal lmdio_oe : std_ulogic;
-- Fix for wider bus
signal hwdata : std_logic_vector(31 downto 0);
signal hrdata : std_logic_vector(31 downto 0);
signal ehwdata : std_logic_vector(31 downto 0);
signal ehrdata : std_logic_vector(31 downto 0);
begin
ethc0: grethc
generic map(
ifg_gap => ifg_gap,
attempt_limit => attempt_limit,
backoff_limit => backoff_limit,
mdcscaler => mdcscaler,
enable_mdio => enable_mdio,
fifosize => fifosize,
nsync => nsync,
edcl => edcl,
edclbufsz => edclbufsz,
macaddrh => macaddrh,
macaddrl => macaddrl,
ipaddrh => ipaddrh,
ipaddrl => ipaddrl,
phyrstadr => phyrstadr,
rmii => rmii,
oepol => oepol,
scanen => scanen,
mdint_pol => mdint_pol,
enable_mdint => enable_mdint,
multicast => multicast,
edclsepahbg => edclsepahb,
ramdebug => ramdebug,
mdiohold => mdiohold,
maxsize => maxsize,
gmiimode => gmiimode
)
port map(
rst => rst,
clk => clk,
--ahb mst in
hgrant => ahbmi.hgrant(hindex),
hready => ahbmi.hready,
hresp => ahbmi.hresp,
hrdata => hrdata,
--ahb mst out
hbusreq => ahbmo.hbusreq,
hlock => ahbmo.hlock,
htrans => ahbmo.htrans,
haddr => ahbmo.haddr,
hwrite => ahbmo.hwrite,
hsize => ahbmo.hsize,
hburst => ahbmo.hburst,
hprot => ahbmo.hprot,
hwdata => hwdata,
--edcl ahb mst in
ehgrant => ahbmi2.hgrant(ehindex),
ehready => ahbmi2.hready,
ehresp => ahbmi2.hresp,
ehrdata => ehrdata,
--edcl ahb mst out
ehbusreq => ahbmo2.hbusreq,
ehlock => ahbmo2.hlock,
ehtrans => ahbmo2.htrans,
ehaddr => ahbmo2.haddr,
ehwrite => ahbmo2.hwrite,
ehsize => ahbmo2.hsize,
ehburst => ahbmo2.hburst,
ehprot => ahbmo2.hprot,
ehwdata => ehwdata,
--apb slv in
psel => apbi.psel(pindex),
penable => apbi.penable,
paddr => apbi.paddr,
pwrite => apbi.pwrite,
pwdata => apbi.pwdata,
--apb slv out
prdata => apbo.prdata,
--irq
irq => irq,
--rx ahb fifo
rxrenable => rxrenable,
rxraddress => rxraddress,
rxwrite => rxwrite,
rxwdata => rxwdata,
rxwaddress => rxwaddress,
rxrdata => rxrdata,
--tx ahb fifo
txrenable => txrenable,
txraddress => txraddress,
txwrite => txwrite,
txwdata => txwdata,
txwaddress => txwaddress,
txrdata => txrdata,
--edcl buf
erenable => erenable,
eraddress => eraddress,
ewritem => ewritem,
ewritel => ewritel,
ewaddressm => ewaddressm,
ewaddressl => ewaddressl,
ewdata => ewdata,
erdata => erdata,
--ethernet input signals
rmii_clk => ethi.rmii_clk,
tx_clk => ethi.tx_clk,
tx_dv => ethi.tx_dv,
rx_clk => ethi.rx_clk,
rxd => ethi.rxd(3 downto 0),
rx_dv => ethi.rx_dv,
rx_er => ethi.rx_er,
rx_col => ethi.rx_col,
rx_crs => ethi.rx_crs,
rx_en => ethi.rx_en,
mdio_i => ethi.mdio_i,
phyrstaddr => ethi.phyrstaddr,
mdint => ethi.mdint,
--ethernet output signals
reset => etho.reset,
txd => etho.txd(3 downto 0),
tx_en => etho.tx_en,
tx_er => etho.tx_er,
mdc => etho.mdc,
mdio_o => etho.mdio_o,
mdio_oe => lmdio_oe,
--scantest
testrst => ahbmi.testrst,
testen => ahbmi.testen,
testoen => ahbmi.testoen,
edcladdr => ethi.edcladdr,
edclsepahb => ethi.edclsepahb,
edcldisable => ethi.edcldisable,
speed => etho.speed);
etho.txd(7 downto 4) <= "0000";
etho.mdio_oe <= ahbmi.testoen when (scanen = 1) and (ahbmi.testen = '1')
else lmdio_oe;
etho.gbit <= '0';
etho.tx_clk <= '0'; -- driven in rgmii component
irqdrv : process(irq)
begin
apbo.pirq <= (others => '0');
apbo.pirq(pirq) <= irq;
end process;
hrdata <= ahbreadword(ahbmi.hrdata);
ahbmo.hwdata <= ahbdrivedata(hwdata);
ahbmo.hconfig <= hconfig;
ahbmo.hindex <= hindex;
ahbmo.hirq <= (others => '0');
ehrdata <= ahbreadword(ahbmi2.hrdata);
ahbmo2.hwdata <= ahbdrivedata(ehwdata);
ahbmo2.hconfig <= ehconfig;
ahbmo2.hindex <= ehindex;
ahbmo2.hirq <= (others => '0');
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
-------------------------------------------------------------------------------
-- FIFOS ----------------------------------------------------------------------
-------------------------------------------------------------------------------
nft : if ft = 0 generate
tx_fifo0 : syncram_2p generic map(tech => memtech, abits => txfabits,
dbits => 32, sepclk => 0)
port map(clk, txrenable, txraddress(txfabits-1 downto 0), txrdata, clk,
txwrite, txwaddress(txfabits-1 downto 0), txwdata);
rx_fifo0 : syncram_2p generic map(tech => memtech, abits => fabits,
dbits => 32, sepclk => 0)
port map(clk, rxrenable, rxraddress(fabits-1 downto 0), rxrdata, clk,
rxwrite, rxwaddress(fabits-1 downto 0), rxwdata);
end generate;
ft1 : if ft /= 0 generate
tx_fifo0 : syncram_2pft generic map(tech => memtech, abits => txfabits,
dbits => 32, sepclk => 0, ft => ft)
port map(clk, txrenable, txraddress(txfabits-1 downto 0), txrdata, clk,
txwrite, txwaddress(txfabits-1 downto 0), txwdata);
rx_fifo0 : syncram_2pft generic map(tech => memtech, abits => fabits,
dbits => 32, sepclk => 0, ft => ft)
port map(clk, rxrenable, rxraddress(fabits-1 downto 0), rxrdata, clk,
rxwrite, rxwaddress(fabits-1 downto 0), rxwdata);
end generate;
-------------------------------------------------------------------------------
-- EDCL buffer ram ------------------------------------------------------------
-------------------------------------------------------------------------------
edclramnft : if (edcl /= 0) and (edclft = 0) generate
r0 : syncram_2p generic map (memtech, eabits, 16) port map(
clk, erenable, eraddress(eabits-1 downto 0), erdata(31 downto 16), clk,
ewritem, ewaddressm(eabits-1 downto 0), ewdata(31 downto 16));
r1 : syncram_2p generic map (memtech, eabits, 16) port map(
clk, erenable, eraddress(eabits-1 downto 0), erdata(15 downto 0), clk,
ewritel, ewaddressl(eabits-1 downto 0), ewdata(15 downto 0));
end generate;
edclramft1 : if (edcl /= 0) and (edclft /= 0) generate
r0 : syncram_2p generic map (memtech, eabits, 16, 0, 0, ft) port map(
clk, erenable, eraddress(eabits-1 downto 0), erdata(31 downto 16), clk,
ewritem, ewaddressm(eabits-1 downto 0), ewdata(31 downto 16));
r1 : syncram_2p generic map (memtech, eabits, 16, 0, 0, ft) port map(
clk, erenable, eraddress(eabits-1 downto 0), erdata(15 downto 0), clk,
ewritel, ewaddressl(eabits-1 downto 0), ewdata(15 downto 0));
end generate;
-- pragma translate_off
bootmsg : report_version
generic map (
"greth" & tost(hindex) & ": 10/100 Mbit Ethernet MAC rev " & tost(REVISION)
& tost(hindex) & ", EDCL " & tost(edcl) & ", buffer " &
tost(edclbufsz) & " kbyte " & tost(txfifosize) & " txfifo," &
" irq " & tost(pirq)
);
-- pragma translate_on
end architecture;
| gpl-3.0 | 96bd4914df21a26327a1d734a29ff969 | 0.536726 | 4.074899 | false | false | false | false |
pwsoft/fpga_examples | rtl/general/gen_counter.vhd | 1 | 2,487 | -- -----------------------------------------------------------------------
--
-- Syntiac's generic VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2009 by Peter Wendrich ([email protected])
-- http://www.syntiac.com/fpga64.html
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
--
-- gen_counter.vhd
--
-- -----------------------------------------------------------------------
--
-- Loadable Up/Down Counter
--
-- -----------------------------------------------------------------------
-- clk - clock input
-- reset - reset counter to 0
-- load - Load counter from d input
-- up - Count up
-- down - Count down
-- d - input for load
-- q - counter output
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- -----------------------------------------------------------------------
entity gen_counter is
generic (
width : integer := 8
);
port (
clk : in std_logic;
reset : in std_logic := '0';
load : in std_logic := '0';
up : in std_logic := '0';
down : in std_logic := '0';
d : in unsigned(width-1 downto 0) := (others => '0');
q : out unsigned(width-1 downto 0)
);
end entity;
-- -----------------------------------------------------------------------
architecture rtl of gen_counter is
signal qReg : unsigned(d'range) := (others => '0');
begin
q <= qReg;
process(clk) is
begin
if rising_edge(clk) then
if reset = '1' then
qReg <= (others => '0');
elsif load = '1' then
qReg <= d;
elsif (up = '1') and (down = '0') then
qReg <= qReg + 1;
elsif (up = '0') and (down = '1') then
qReg <= qReg - 1;
end if;
end if;
end process;
end architecture;
| lgpl-2.1 | fb5a4c35593d07f5c85890a2a736dc07 | 0.489747 | 3.972843 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-ahbfile/config.vhd | 1 | 4,409 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := inferred;
constant CFG_MEMTECH : integer := inferred;
constant CFG_PADTECH : integer := inferred;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 0 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (0);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 0;
constant CFG_ISETS : integer := 1;
constant CFG_ISETSZ : integer := 1;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 0;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 1;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 0*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 1 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 0;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 1;
constant CFG_AHBRSZ : integer := 64;
constant CFG_AHBRADDR : integer := 16#400#;
constant CFG_AHBRPIPE : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 1;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 0;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 0;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := 1;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-3.0 | 0ced936d9aab1c36512b03fbe606f1d4 | 0.636199 | 3.671107 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/uart/ahbuart.vhd | 1 | 2,701 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbuart
-- File: ahbuart.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: UART with AHB master interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.misc.all;
use gaisler.uart.all;
use gaisler.libdcom.all;
entity ahbuart is
generic (
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
uarti : in uart_in_type;
uarto : out uart_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type );
end;
architecture struct of ahbuart is
constant REVISION : integer := 0;
signal dmai : ahb_dma_in_type;
signal dmao : ahb_dma_out_type;
signal duarti : dcom_uart_in_type;
signal duarto : dcom_uart_out_type;
begin
ahbmst0 : ahbmst
generic map (hindex => hindex, venid => VENDOR_GAISLER, devid => GAISLER_AHBUART)
port map (rst, clk, dmai, dmao, ahbi, ahbo);
dcom_uart0 : dcom_uart generic map (pindex, paddr, pmask)
port map (rst, clk, uarti, uarto, apbi, apbo, duarti, duarto);
dcom0 : dcom port map (rst, clk, dmai, dmao, duarti, duarto, ahbi);
-- pragma translate_off
bootmsg : report_version
generic map ("ahbuart" & tost(pindex) &
": AHB Debug UART rev " & tost(REVISION));
-- pragma translate_on
end;
| gpl-3.0 | 0b551798cf5b147105227e6d97ab17ac | 0.614587 | 3.793539 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-xilinx-vc707/sgmii_vc707.vhd | 1 | 40,228 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: sgmii
-- File: sgmii.vhd
-- Author: Fredrik Ringhage - Aeroflex Gaisler
-- Description: GMII to SGMII interface
------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Description: This is the top level vhdl example design for the
-- Ethernet 1000BASE-X PCS/PMA core.
--
-- This design example instantiates IOB flip-flops
-- and input/output buffers on the GMII.
--
-- A Transmitter Elastic Buffer is instantiated on the Tx
-- GMII path to perform clock compenstation between the
-- core and the external MAC driving the Tx GMII.
--
-- This design example can be synthesised.
--
--
--
-- ----------------------------------------------------------------
-- | Example Design |
-- | |
-- | ---------------------------------------------- |
-- | | Core Block (wrapper) | |
-- | | | |
-- | | -------------- -------------- | |
-- | | | Core | | tranceiver | | |
-- | | | | | | | |
-- | --------- | | | | | | |
-- | | | | | | | | | |
-- | | Tx | | | | | | | |
-- ---->|Elastic|----->| GMII |--------->| TXP |--------->
-- | |Buffer | | | Tx | | TXN | | |
-- | | | | | | | | | |
-- | --------- | | | | | | |
-- | GMII | | | | | | |
-- | IOBs | | | | | | |
-- | | | | | | | |
-- | | | GMII | | RXP | | |
-- <-------------------| Rx |<---------| RXN |<---------
-- | | | | | | | |
-- | | -------------- -------------- | |
-- | | | |
-- | ---------------------------------------------- |
-- | |
-- ----------------------------------------------------------------
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library gaisler;
use gaisler.net.all;
use gaisler.misc.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library eth;
use eth.grethpkg.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- The entity declaration for the example design
--------------------------------------------------------------------------------
entity sgmii_vc707 is
generic(
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
abits : integer := 8;
autonegotiation : integer := 1;
pirq : integer := 0;
debugmem : integer := 0;
tech : integer := 0;
simulation : integer := 0
);
port(
-- Tranceiver Interface
sgmiii : in eth_sgmii_in_type;
sgmiio : out eth_sgmii_out_type;
-- GMII Interface (client MAC <=> PCS)
gmiii : out eth_in_type;
gmiio : in eth_out_type;
-- Asynchronous reset for entire core.
reset : in std_logic;
-- APB Status bus
apb_clk : in std_logic;
apb_rstn : in std_logic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end sgmii_vc707;
architecture top_level of sgmii_vc707 is
------------------------------------------------------------------------------
-- Component Declaration for the Core Block (core wrapper).
------------------------------------------------------------------------------
component sgmii
port(
-- Transceiver Interface
------------------------
gtrefclk : in std_logic; -- Very high quality 125MHz clock for GT transceiver
gtrefclk_bufg : in std_logic;
txp : out std_logic; -- Differential +ve of serial transmission from PMA to PMD.
txn : out std_logic; -- Differential -ve of serial transmission from PMA to PMD.
rxp : in std_logic; -- Differential +ve for serial reception from PMD to PMA.
rxn : in std_logic; -- Differential -ve for serial reception from PMD to PMA.
resetdone : out std_logic; -- The GT transceiver has completed its reset cycle
cplllock : out std_logic;
mmcm_reset : out std_logic;
txoutclk : out std_logic; -- txoutclk from GT transceiver (62.5MHz)
rxoutclk : out std_logic; -- txoutclk from GT transceiver (62.5MHz)
userclk : in std_logic; -- 62.5MHz clock.
userclk2 : in std_logic; -- 125MHz clock.
rxuserclk : in std_logic; -- 125MHz clock.
rxuserclk2 : in std_logic; -- 125MHz clock.
independent_clock_bufg : in std_logic;
pma_reset : in std_logic; -- transceiver PMA reset signal
mmcm_locked : in std_logic; -- Locked signal from MMCM
-- GMII Interface
-----------------
sgmii_clk_r : out std_logic; -- Clock for client MAC (125Mhz, 12.5MHz or 1.25MHz).
sgmii_clk_f : out std_logic; -- Clock for client MAC (125Mhz, 12.5MHz or 1.25MHz).
sgmii_clk_en : out std_logic; -- Clock enable for client MAC
gmii_txd : in std_logic_vector(7 downto 0); -- Transmit data from client MAC.
gmii_tx_en : in std_logic; -- Transmit control signal from client MAC.
gmii_tx_er : in std_logic; -- Transmit control signal from client MAC.
gmii_rxd : out std_logic_vector(7 downto 0); -- Received Data to client MAC.
gmii_rx_dv : out std_logic; -- Received control signal to client MAC.
gmii_rx_er : out std_logic; -- Received control signal to client MAC.
gmii_isolate : out std_logic; -- Tristate control to electrically isolate GMII.
-- Management: MDIO Interface
-----------------------------
configuration_vector : in std_logic_vector(4 downto 0); -- Alternative to MDIO interface.
an_interrupt : out std_logic; -- Interrupt to processor to signal that Auto-Negotiation has completed
an_adv_config_vector : in std_logic_vector(15 downto 0); -- Alternate interface to program REG4 (AN ADV)
an_restart_config : in std_logic; -- Alternate signal to modify AN restart bit in REG0
-- Speed Control
----------------
speed_is_10_100 : in std_logic; -- Core should operate at either 10Mbps or 100Mbps speeds
speed_is_100 : in std_logic; -- Core should operate at 100Mbps speed
-- General IO's
---------------
status_vector : out std_logic_vector(15 downto 0); -- Core status.
reset : in std_logic; -- Asynchronous reset for entire core.
signal_detect : in std_logic; -- Input from PMD to indicate presence of optical input.
gt0_qplloutclk_in : in std_logic; -- Input from PMD to indicate presence of optical input.
gt0_qplloutrefclk_in : in std_logic -- Input from PMD to indicate presence of optical input.
);
end component;
component MMCME2_ADV
generic (
BANDWIDTH : string := "OPTIMIZED";
CLKFBOUT_MULT_F : real := 5.000;
CLKFBOUT_PHASE : real := 0.000;
--CLKFBOUT_USE_FINE_PS : boolean := FALSE;
CLKIN1_PERIOD : real := 0.000;
CLKIN2_PERIOD : real := 0.000;
CLKOUT0_DIVIDE_F : real := 1.000;
CLKOUT0_DUTY_CYCLE : real := 0.500;
CLKOUT0_PHASE : real := 0.000;
--CLKOUT0_USE_FINE_PS : boolean := FALSE;
CLKOUT1_DIVIDE : integer := 1;
CLKOUT1_DUTY_CYCLE : real := 0.500;
CLKOUT1_PHASE : real := 0.000;
--CLKOUT1_USE_FINE_PS : boolean := FALSE;
CLKOUT2_DIVIDE : integer := 1;
CLKOUT2_DUTY_CYCLE : real := 0.500;
CLKOUT2_PHASE : real := 0.000;
--CLKOUT2_USE_FINE_PS : boolean := FALSE;
CLKOUT3_DIVIDE : integer := 1;
CLKOUT3_DUTY_CYCLE : real := 0.500;
CLKOUT3_PHASE : real := 0.000;
--CLKOUT3_USE_FINE_PS : boolean := FALSE;
--CLKOUT4_CASCADE : boolean := FALSE;
CLKOUT4_DIVIDE : integer := 1;
CLKOUT4_DUTY_CYCLE : real := 0.500;
CLKOUT4_PHASE : real := 0.000;
--CLKOUT4_USE_FINE_PS : boolean := FALSE;
CLKOUT5_DIVIDE : integer := 1;
CLKOUT5_DUTY_CYCLE : real := 0.500;
CLKOUT5_PHASE : real := 0.000;
--CLKOUT5_USE_FINE_PS : boolean := FALSE;
CLKOUT6_DIVIDE : integer := 1;
CLKOUT6_DUTY_CYCLE : real := 0.500;
CLKOUT6_PHASE : real := 0.000;
--CLKOUT6_USE_FINE_PS : boolean := FALSE;
COMPENSATION : string := "ZHOLD";
DIVCLK_DIVIDE : integer := 1;
REF_JITTER1 : real := 0.0;
REF_JITTER2 : real := 0.0;
--SS_EN : string := "FALSE";
SS_MODE : string := "CENTER_HIGH";
SS_MOD_PERIOD : integer := 10000
);
port (
CLKFBOUT : out std_ulogic := '0';
CLKFBOUTB : out std_ulogic := '0';
CLKFBSTOPPED : out std_ulogic := '0';
CLKINSTOPPED : out std_ulogic := '0';
CLKOUT0 : out std_ulogic := '0';
CLKOUT0B : out std_ulogic := '0';
CLKOUT1 : out std_ulogic := '0';
CLKOUT1B : out std_ulogic := '0';
CLKOUT2 : out std_ulogic := '0';
CLKOUT2B : out std_ulogic := '0';
CLKOUT3 : out std_ulogic := '0';
CLKOUT3B : out std_ulogic := '0';
CLKOUT4 : out std_ulogic := '0';
CLKOUT5 : out std_ulogic := '0';
CLKOUT6 : out std_ulogic := '0';
DO : out std_logic_vector (15 downto 0);
DRDY : out std_ulogic := '0';
LOCKED : out std_ulogic := '0';
PSDONE : out std_ulogic := '0';
CLKFBIN : in std_ulogic;
CLKIN1 : in std_ulogic;
CLKIN2 : in std_ulogic;
CLKINSEL : in std_ulogic;
DADDR : in std_logic_vector(6 downto 0);
DCLK : in std_ulogic;
DEN : in std_ulogic;
DI : in std_logic_vector(15 downto 0);
DWE : in std_ulogic;
PSCLK : in std_ulogic;
PSEN : in std_ulogic;
PSINCDEC : in std_ulogic;
PWRDWN : in std_ulogic;
RST : in std_ulogic
);
end component;
----- component IBUFDS_GTE2 -----
component IBUFDS_GTE2
port (
O : out std_ulogic;
ODIV2 : out std_ulogic;
CEB : in std_ulogic;
I : in std_ulogic;
IB : in std_ulogic
);
end component;
----- component BUFHCE -----
component BUFHCE
generic (
CE_TYPE : string := "SYNC";
INIT_OUT : integer := 0
);
port (
O : out std_ulogic;
CE : in std_ulogic;
I : in std_ulogic
);
end component;
----- component BUFGMUX -----
component BUFGMUX
generic (
CLK_SEL_TYPE : string := "ASYNC"
);
port (
O : out std_ulogic := '0';
I0 : in std_ulogic := '0';
I1 : in std_ulogic := '0';
S : in std_ulogic := '0'
);
end component;
----- component ODDR -----
component ODDR
generic (
DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
INIT : bit := '0';
SRTYPE : string := "SYNC"
);
port (
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic := 'L';
S : in std_ulogic := 'L'
);
end component;
constant REVISION : integer := 1;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_SGMII, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
type sgmiiregs is record
irq : std_logic_vector(31 downto 0); -- interrupt
mask : std_logic_vector(31 downto 0); -- interrupt enable
configuration_vector : std_logic_vector( 4 downto 0);
an_adv_config_vector : std_logic_vector(15 downto 0);
end record;
-- APB and RGMII control register
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RES_configuration_vector : std_logic_vector(4 downto 0) := std_logic_vector(to_unsigned(autonegotiation,1)) & "0000";
constant RES : sgmiiregs :=
( irq => (others => '0'), mask => (others => '0'),
configuration_vector => RES_configuration_vector, an_adv_config_vector => "0001100000000001");
type rxregs is record
gmii_rxd : std_logic_vector(7 downto 0);
gmii_rxd_int : std_logic_vector(7 downto 0);
gmii_rx_dv : std_logic;
gmii_rx_er : std_logic;
count : integer;
gmii_dv : std_logic;
keepalive : integer;
end record;
constant RESRX : rxregs :=
( gmii_rxd => (others => '0'), gmii_rxd_int => (others => '0'),
gmii_rx_dv => '0', gmii_rx_er => '0',
count => 0, gmii_dv => '0', keepalive => 0
);
type txregs is record
gmii_txd : std_logic_vector(7 downto 0);
gmii_txd_int : std_logic_vector(7 downto 0);
gmii_tx_en : std_logic;
gmii_tx_en_int : std_logic;
gmii_tx_er : std_logic;
count : integer;
cnt_en : std_logic;
keepalive : integer;
end record;
constant RESTX : txregs :=
( gmii_txd => (others => '0'), gmii_txd_int => (others => '0'),
gmii_tx_en => '0', gmii_tx_en_int => '0', gmii_tx_er => '0',
count => 0, cnt_en => '0', keepalive => 0
);
------------------------------------------------------------------------------
-- internal signals used in this top level example design.
------------------------------------------------------------------------------
-- clock generation signals for tranceiver
signal gtrefclk : std_logic;
signal txoutclk : std_logic;
signal rxoutclk : std_logic;
signal resetdone : std_logic;
signal mmcm_locked : std_logic;
signal mmcm_reset : std_logic;
signal clkfbout : std_logic;
signal clkout0 : std_logic;
signal clkout1 : std_logic;
signal userclk : std_logic;
signal userclk2 : std_logic;
signal rxuserclk : std_logic;
-- PMA reset generation signals for tranceiver
signal pma_reset_pipe : std_logic_vector(3 downto 0);
signal pma_reset : std_logic;
-- clock generation signals for SGMII clock
signal sgmii_clk_r : std_logic;
signal sgmii_clk_f : std_logic;
signal sgmii_clk_en : std_logic;
-- GMII signals
signal gmii_txd : std_logic_vector(7 downto 0);
signal gmii_tx_en : std_logic;
signal gmii_tx_er : std_logic;
signal gmii_rxd : std_logic_vector(7 downto 0);
signal gmii_rx_dv : std_logic;
signal gmii_rx_er : std_logic;
signal gmii_isolate : std_logic;
-- Internal GMII signals from Xilinx SGMII block
signal gmii_rxd_int : std_logic_vector(7 downto 0);
signal gmii_rx_dv_int : std_logic;
signal gmii_rx_er_int : std_logic;
-- Extra registers to ease IOB placement
signal status_vector_int : std_logic_vector(15 downto 0);
signal status_vector_apb : std_logic_vector(15 downto 0);
signal status_vector_apb1 : std_logic_vector(31 downto 0);
signal status_vector_apb2 : std_logic_vector(31 downto 0);
-- These attributes will stop timing errors being reported in back annotated
-- SDF simulation.
attribute ASYNC_REG : string;
attribute ASYNC_REG of pma_reset_pipe : signal is "TRUE";
-- Configuration register
signal speed_is_10_100 : std_logic;
signal speed_is_100 : std_logic;
signal configuration_vector : std_logic_vector(4 downto 0);
signal an_interrupt : std_logic;
signal an_adv_config_vector : std_logic_vector(15 downto 0);
signal an_restart_config : std_logic;
signal link_timer_value : std_logic_vector(8 downto 0);
signal synchronization_done : std_logic;
signal linkup : std_logic;
signal signal_detect : std_logic;
-- Route gtrefclk through an IBUFG.
signal gtrefclk_buf_i : std_logic;
signal r, rin : sgmiiregs;
signal rrx,rinrx : rxregs;
signal rtx, rintx : txregs;
signal cnt_en : std_logic;
signal usr2rstn : std_logic;
-- debug signal
signal WMemRgmiioData : std_logic_vector(15 downto 0);
signal RMemRgmiioData : std_logic_vector(15 downto 0);
signal RMemRgmiioAddr : std_logic_vector(9 downto 0);
signal WMemRgmiioAddr : std_logic_vector(9 downto 0);
signal WMemRgmiioWrEn : std_logic;
signal WMemRgmiiiData : std_logic_vector(15 downto 0);
signal RMemRgmiiiData : std_logic_vector(15 downto 0);
signal RMemRgmiiiAddr : std_logic_vector(9 downto 0);
signal WMemRgmiiiAddr : std_logic_vector(9 downto 0);
signal WMemRgmiiiWrEn : std_logic;
signal RMemRgmiiiRead : std_logic;
signal RMemRgmiioRead : std_logic;
begin
-----------------------------------------------------------------------------
-- Default for VC707
-----------------------------------------------------------------------------
-- Remove AN during simulation i.e. "00000"
configuration_vector <= "10000" when (autonegotiation = 1) else "00000";
-- Configuration for Xilinx SGMII IP. See doc for SGMII IP for more information
an_adv_config_vector <= "0001100000000001";
an_restart_config <= '0';
link_timer_value <= "000110010";
-- Core Status vector outputs
synchronization_done <= status_vector_int(1);
linkup <= status_vector_int(0);
signal_detect <= '1';
gmiii.gtx_clk <= userclk2;
gmiii.tx_clk <= userclk2;
gmiii.rx_clk <= userclk2;
gmiii.rmii_clk <= userclk2;
gmiii.rxd <= gmii_rxd;
gmiii.rx_dv <= gmii_rx_dv;
gmiii.rx_er <= gmii_rx_er;
gmiii.rx_en <= gmii_rx_dv or sgmii_clk_en;
--gmiii.tx_dv <= '1';
gmiii.tx_dv <= cnt_en when gmiio.tx_en = '1' else '1';
-- GMII output controlled via generics
gmiii.edclsepahb <= '0';
gmiii.edcldisable <= '0';
gmiii.phyrstaddr <= (others => '0');
gmiii.edcladdr <= (others => '0');
-- Not used
gmiii.rx_col <= '0';
gmiii.rx_crs <= '0';
gmiii.tx_clk_90 <= '0';
sgmiio.mdio_o <= gmiio.mdio_o;
sgmiio.mdio_oe <= gmiio.mdio_oe;
gmiii.mdio_i <= sgmiii.mdio_i;
sgmiio.mdc <= gmiio.mdc;
gmiii.mdint <= sgmiii.mdint;
sgmiio.reset <= apb_rstn;
-----------------------------------------------------------------------------
-- Transceiver Clock Management
-----------------------------------------------------------------------------
sgmii1 : if simulation = 1 generate
end generate;
sgmii0 : if simulation = 0 generate
-- Clock circuitry for the GT Transceiver uses a differential input clock.
-- gtrefclk is routed to the tranceiver.
ibufds_gtrefclk : IBUFDS_GTE2
port map (
I => sgmiii.clkp,
IB => sgmiii.clkn,
CEB => '0',
O => gtrefclk_buf_i,
ODIV2 => open
);
bufhce_gtrefclk : BUFHCE
port map (
I => gtrefclk_buf_i,
CE => '1',
O => gtrefclk
);
-- The GT transceiver provides a 62.5MHz clock to the FPGA fabrix. This is
-- routed to an MMCM module where it is used to create phase and frequency
-- related 62.5MHz and 125MHz clock sources
mmcm_adv_inst : MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
--CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
-- STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => 16.000,
CLKFBOUT_PHASE => 0.000,
--CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 8.000,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.5,
--CLKOUT0_USE_FINE_PS => FALSE,
CLKOUT1_DIVIDE => 16,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.5,
--CLKOUT1_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => 16.0,
REF_JITTER1 => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKFBOUTB => open,
CLKOUT0 => clkout0,
CLKOUT0B => open,
CLKOUT1 => clkout1,
CLKOUT1B => open,
CLKOUT2 => open,
CLKOUT2B => open,
CLKOUT3 => open,
CLKOUT3B => open,
CLKOUT4 => open,
CLKOUT5 => open,
CLKOUT6 => open,
-- Input clock control
CLKFBIN => clkfbout,
CLKIN1 => txoutclk,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => open,
DRDY => open,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => mmcm_locked,
CLKINSTOPPED => open,
CLKFBSTOPPED => open,
PWRDWN => '0',
RST => mmcm_reset);
--mmcm_reset <= reset or (not resetdone);
mmcm_reset <= reset;
-- This 62.5MHz clock is placed onto global clock routing and is then used
-- for tranceiver TXUSRCLK/RXUSRCLK.
bufg_userclk: BUFG
port map (
I => clkout1,
O => userclk
);
-- This 125MHz clock is placed onto global clock routing and is then used
-- to clock all Ethernet core logic.
bufg_userclk2: BUFG
port map (
I => clkout0,
O => userclk2
);
-- This 62.5MHz clock is placed onto global clock routing and is then used
-- for tranceiver TXUSRCLK/RXUSRCLK.
bufg_rxuserclk: BUFG
port map (
I => rxoutclk,
O => rxuserclk
);
end generate;
-----------------------------------------------------------------------------
-- Sync Reset for user clock
-----------------------------------------------------------------------------
userclk2_rst : rstgen
generic map(syncin => 1, syncrst => 1)
port map(apb_rstn, userclk2, '1', usr2rstn, open);
-----------------------------------------------------------------------------
-- Transceiver PMA reset circuitry
-----------------------------------------------------------------------------
-- Create a reset pulse of a decent length
process(reset, apb_clk)
begin
if (reset = '1') then
pma_reset_pipe <= "1111";
elsif apb_clk'event and apb_clk = '1' then
pma_reset_pipe <= pma_reset_pipe(2 downto 0) & reset;
end if;
end process;
pma_reset <= pma_reset_pipe(3);
------------------------------------------------------------------------------
-- GMII (Aeroflex Gaisler) to GMII (Xilinx) style
------------------------------------------------------------------------------
-- 10/100Mbit TX Loic
process (usr2rstn,rtx,gmiio)
variable v : txregs;
begin
v := rtx;
v.cnt_en := '0';
v.gmii_tx_en_int := gmiio.tx_en;
if (gmiio.tx_en = '1' and rtx.gmii_tx_en_int = '0') then
v.count := 0;
elsif (v.count >= 9) and gmiio.speed = '1' then
v.count := 0;
elsif (v.count >= 99) and gmiio.speed = '0' then
v.count := 0;
else
v.count := rtx.count + 1;
end if;
case v.count is
when 0 =>
v.gmii_txd_int(3 downto 0) := gmiio.txd(3 downto 0);
v.cnt_en := '1';
when 5 =>
if gmiio.speed = '1' then
v.gmii_txd_int(7 downto 4) := gmiio.txd(3 downto 0);
v.cnt_en := '1';
end if;
when 50=>
if gmiio.speed = '0' then
v.gmii_txd_int(7 downto 4) := gmiio.txd(3 downto 0);
v.cnt_en := '1';
end if;
when 9 =>
if gmiio.speed = '1' then
v.gmii_txd := v.gmii_txd_int;
v.gmii_tx_en := '1';
v.gmii_tx_er := gmiio.tx_er;
if (gmiio.tx_en = '0' and rtx.keepalive <= 1) then v.gmii_tx_en := '0'; end if;
if (rtx.keepalive > 0) then v.keepalive := rtx.keepalive - 1; end if;
end if;
when 99 =>
if gmiio.speed = '0' then
v.gmii_txd := v.gmii_txd_int;
v.gmii_tx_en := '1';
v.gmii_tx_er := gmiio.tx_er;
if (gmiio.tx_en = '0' and rtx.keepalive <= 1) then v.gmii_tx_en := '0'; end if;
if (rtx.keepalive > 0) then v.keepalive := rtx.keepalive - 1; end if;
end if;
when others =>
null;
end case;
if (gmiio.tx_en = '0' and rtx.gmii_tx_en_int = '1') then
v.keepalive := 2;
end if;
if (gmiio.tx_en = '0' and rtx.gmii_tx_en_int = '0' and rtx.keepalive = 0) then
v := RESTX;
end if;
-- reset operation
if (not RESET_ALL) and (usr2rstn = '0') then
v := RESTX;
end if;
-- update registers
rintx <= v;
end process;
txegs : process(userclk2)
begin
if rising_edge(userclk2) then
rtx <= rintx;
if RESET_ALL and usr2rstn = '0' then
rtx <= RESTX;
end if;
end if;
end process;
-- 1000Mbit TX Logic (Bypass)
-- n/a
-- TX Mux Select
cnt_en <= '1' when (gmiio.gbit = '1') else rtx.cnt_en;
gmii_txd <= gmiio.txd when (gmiio.gbit = '1') else rtx.gmii_txd;
gmii_tx_en <= gmiio.tx_en when (gmiio.gbit = '1') else rtx.gmii_tx_en;
gmii_tx_er <= gmiio.tx_er when (gmiio.gbit = '1') else rtx.gmii_tx_er;
------------------------------------------------------------------------------
-- Instantiate the Core Block (core wrapper).
------------------------------------------------------------------------------
speed_is_10_100 <= not gmiio.gbit;
speed_is_100 <= gmiio.speed;
core_wrapper : sgmii
port map (
gtrefclk => gtrefclk,
gtrefclk_bufg => gtrefclk,
txp => sgmiio.txp,
txn => sgmiio.txn,
rxp => sgmiii.rxp,
rxn => sgmiii.rxn,
resetdone => resetdone,
cplllock => OPEN ,
mmcm_reset => OPEN ,
txoutclk => txoutclk,
rxoutclk => rxoutclk ,
userclk => userclk,
userclk2 => userclk2,
rxuserclk => rxuserclk ,
rxuserclk2 => rxuserclk ,
independent_clock_bufg => apb_clk,
pma_reset => pma_reset,
mmcm_locked => mmcm_locked,
sgmii_clk_r => sgmii_clk_r,
sgmii_clk_f => sgmii_clk_f,
sgmii_clk_en => sgmii_clk_en,
gmii_txd => gmii_txd,
gmii_tx_en => gmii_tx_en,
gmii_tx_er => gmii_tx_er,
gmii_rxd => gmii_rxd_int,
gmii_rx_dv => gmii_rx_dv_int,
gmii_rx_er => gmii_rx_er_int,
gmii_isolate => gmii_isolate,
configuration_vector => configuration_vector,
an_interrupt => an_interrupt,
an_adv_config_vector => an_adv_config_vector,
an_restart_config => an_restart_config,
speed_is_10_100 => speed_is_10_100,
speed_is_100 => speed_is_100,
status_vector => status_vector_int,
reset => reset,
signal_detect => signal_detect,
gt0_qplloutclk_in => '0',
gt0_qplloutrefclk_in => '0'
);
------------------------------------------------------------------------------
-- GMII (Xilinx) to GMII (Aeroflex Gailers) style
------------------------------------------------------------------------------
---- 10/100Mbit RX Loic
process (usr2rstn,rrx,gmii_rx_dv_int,gmii_rxd_int,gmii_rx_er_int,sgmii_clk_en)
variable v : rxregs;
begin
v := rrx;
if (gmii_rx_dv_int = '1' and sgmii_clk_en = '1') then
v.count := 0;
v.gmii_rxd_int := gmii_rxd_int;
v.gmii_dv := '1';
v.keepalive := 1;
elsif (v.count >= 9) and gmiio.speed = '1' then
v.count := 0;
v.keepalive := rrx.keepalive - 1;
elsif (v.count >= 99) and gmiio.speed = '0' then
v.count := 0;
v.keepalive := rrx.keepalive - 1;
else
v.count := rrx.count + 1;
end if;
case v.count is
when 0 =>
v.gmii_rxd := v.gmii_rxd_int(3 downto 0) & v.gmii_rxd_int(3 downto 0);
v.gmii_rx_dv := v.gmii_dv;
when 5 =>
if gmiio.speed = '1' then
v.gmii_rxd := v.gmii_rxd_int(7 downto 4) & v.gmii_rxd_int(7 downto 4);
v.gmii_rx_dv := v.gmii_dv;
v.gmii_dv := '0';
end if;
when 50 =>
if gmiio.speed = '0' then
v.gmii_rxd := v.gmii_rxd_int(7 downto 4) & v.gmii_rxd_int(7 downto 4);
v.gmii_rx_dv := v.gmii_dv;
v.gmii_dv := '0';
end if;
when others =>
v.gmii_rxd := v.gmii_rxd;
v.gmii_rx_dv := '0';
end case;
v.gmii_rx_er := gmii_rx_er_int;
if (rrx.keepalive = 0 and gmii_rx_dv_int = '0') then
v := RESRX;
end if;
-- reset operation
if (not RESET_ALL) and (usr2rstn = '0') then
v := RESRX;
end if;
-- update registers
rinrx <= v;
end process;
rx100regs : process(userclk2)
begin
if rising_edge(userclk2) then
rrx <= rinrx;
if RESET_ALL and usr2rstn = '0' then
rrx <= RESRX;
end if;
end if;
end process;
---- 1000Mbit RX Logic (Bypass)
-- n/a
---- RX Mux Select
gmii_rxd <= gmii_rxd_int when (gmiio.gbit = '1') else rinrx.gmii_rxd;
gmii_rx_dv <= gmii_rx_dv_int when (gmiio.gbit = '1') else rinrx.gmii_rx_dv;
gmii_rx_er <= gmii_rx_er_int when (gmiio.gbit = '1') else rinrx.gmii_rx_er;
-----------------------------------------------------------------------------
-- Extra registers to ease CDC placement
-----------------------------------------------------------------------------
process (apb_clk)
begin
if apb_clk'event and apb_clk = '1' then
status_vector_apb <= status_vector_int;
end if;
end process;
---------------------------------------------------------------------------------------
-- APB Section
---------------------------------------------------------------------------------------
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
-- Extra registers to ease CDC placement
process (apb_clk)
begin
if apb_clk'event and apb_clk = '1' then
status_vector_apb1 <= (others => '0');
status_vector_apb2 <= (others => '0');
-- Register to detect a speed change
status_vector_apb1(15 downto 0) <= status_vector_apb;
status_vector_apb2 <= status_vector_apb1;
end if;
end process;
rgmiiapb : process(apb_rstn, r, apbi, status_vector_apb1, status_vector_apb2, RMemRgmiiiData, RMemRgmiiiRead, RMemRgmiioRead )
variable rdata : std_logic_vector(31 downto 0);
variable paddress : std_logic_vector(7 downto 2);
variable v : sgmiiregs;
begin
v := r;
paddress := (others => '0');
paddress(abits-1 downto 2) := apbi.paddr(abits-1 downto 2);
rdata := (others => '0');
-- read/write registers
if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
case paddress(7 downto 2) is
when "000000" =>
rdata(31 downto 0) := status_vector_apb2;
when "000001" =>
rdata(31 downto 0) := r.irq;
v.irq := (others => '0'); -- Interrupt is clear on read
when "000010" =>
rdata(31 downto 0) := r.mask;
when "000011" =>
rdata(4 downto 0) := r.configuration_vector;
when "000100" =>
rdata(15 downto 0) := r.an_adv_config_vector;
when "000101" =>
if (autonegotiation /= 0) then rdata(0) := '1'; else rdata(0) := '0'; end if;
if (debugmem /= 0) then rdata(1) := '1'; else rdata(1) := '0'; end if;
when others =>
null;
end case;
end if;
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case paddress(7 downto 2) is
when "000000" =>
null;
when "000001" =>
null;
when "000010" =>
v.mask := apbi.pwdata(31 downto 0);
when "000011" =>
v.configuration_vector := apbi.pwdata(4 downto 0);
when "000100" =>
v.an_adv_config_vector := apbi.pwdata(15 downto 0);
when "000101" =>
null;
when others =>
null;
end case;
end if;
-- Check interrupts
for i in 0 to status_vector_apb2'length-1 loop
if ((status_vector_apb1(i) xor status_vector_apb2(i)) and v.mask(i)) = '1' then
v.irq(i) := '1';
end if;
end loop;
-- reset operation
if (not RESET_ALL) and (apb_rstn = '0') then
v := RES;
end if;
-- update registers
rin <= v;
-- drive outputs
if apbi.psel(pindex) = '0' then
apbo.prdata <= (others => '0');
elsif RMemRgmiiiRead = '1' then
apbo.prdata(31 downto 16) <= (others => '0');
apbo.prdata(15 downto 0) <= RMemRgmiiiData;
elsif RMemRgmiioRead = '1' then
apbo.prdata(31 downto 16) <= (others => '0');
apbo.prdata(15 downto 0) <= RMemRgmiioData;
else
apbo.prdata <= rdata;
end if;
apbo.pirq <= (others => '0');
apbo.pirq(pirq) <= orv(v.irq);
end process;
regs : process(apb_clk)
begin
if rising_edge(apb_clk) then
r <= rin;
if RESET_ALL and apb_rstn = '0' then
r <= RES;
end if;
end if;
end process;
---------------------------------------------------------------------------------------
-- Debug Mem
---------------------------------------------------------------------------------------
debugmem1 : if (debugmem /= 0) generate
-- Write GMII IN data
process (userclk2)
begin -- process
if rising_edge(userclk2) then
WMemRgmiioData(15 downto 0) <= '0' & '0' & '0' & sgmii_clk_en & '0' & '0' & gmii_tx_er & gmii_tx_en & gmii_txd;
if (gmii_tx_en = '1') and ((WMemRgmiioAddr < "0111111110") or (WMemRgmiioAddr = "1111111111")) then
WMemRgmiioAddr <= WMemRgmiioAddr + 1;
WMemRgmiioWrEn <= '1';
else
if (gmii_tx_en = '0') then
WMemRgmiioAddr <= (others => '1');
else
WMemRgmiioAddr <= WMemRgmiioAddr;
end if;
WMemRgmiioWrEn <= '0';
end if;
if usr2rstn = '0' then
WMemRgmiioAddr <= (others => '0');
WMemRgmiioWrEn <= '0';
end if;
end if;
end process;
-- Read
RMemRgmiioRead <= apbi.paddr(10) and apbi.psel(pindex);
RMemRgmiioAddr <= "00" & apbi.paddr(10-1 downto 2);
gmiii0 : syncram_2p generic map (tech, 10, 16, 1, 0, 0) port map(
apb_clk, RMemRgmiioRead, RMemRgmiioAddr, RMemRgmiioData,
userclk2, WMemRgmiioWrEn, WMemRgmiioAddr(10-1 downto 0), WMemRgmiioData);
-- Write GMII IN data
process (userclk2)
begin -- process
if rising_edge(userclk2) then
if (gmii_rx_dv = '1') then
WMemRgmiiiData(15 downto 0) <= '0' & '0' & '0' &sgmii_clk_en & "00" & gmii_rx_er & gmii_rx_dv & gmii_rxd;
elsif (gmii_rx_dv_int = '0') then
WMemRgmiiiData(15 downto 0) <= (others => '0');
else
WMemRgmiiiData <= WMemRgmiiiData;
end if;
if (gmii_rx_dv = '1') and ((WMemRgmiiiAddr < "0111111110") or (WMemRgmiiiAddr = "1111111111")) then
WMemRgmiiiAddr <= WMemRgmiiiAddr + 1;
WMemRgmiiiWrEn <= '1';
else
if (gmii_rx_dv_int = '0') then
WMemRgmiiiAddr <= (others => '1');
WMemRgmiiiWrEn <= '0';
else
WMemRgmiiiAddr <= WMemRgmiiiAddr;
WMemRgmiiiWrEn <= '0';
end if;
end if;
if usr2rstn = '0' then
WMemRgmiiiAddr <= (others => '0');
WMemRgmiiiWrEn <= '0';
end if;
end if;
end process;
-- Read
RMemRgmiiiRead <= apbi.paddr(11) and apbi.psel(pindex);
RMemRgmiiiAddr <= "00" & apbi.paddr(10-1 downto 2);
rgmiii0 : syncram_2p generic map (tech, 10, 16, 1, 0, 0) port map(
apb_clk, RMemRgmiiiRead, RMemRgmiiiAddr, RMemRgmiiiData,
userclk2, WMemRgmiiiWrEn, WMemRgmiiiAddr(10-1 downto 0), WMemRgmiiiData);
end generate;
-- pragma translate_off
bootmsg : report_version
generic map ("sgmii" & tost(pindex) &
": SGMII rev " & tost(REVISION) & ", irq " & tost(pirq));
-- pragma translate_on
end top_level;
| gpl-3.0 | 003a2028c30d744e64bf4a95dba9c0d5 | 0.48163 | 3.981 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/leon3v3/cmvalidbits.vhd | 1 | 3,639 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: cmvalidbits
-- File: cmvalidbits.vhd
-- Author: Magnus Hjorth - Cobham Gaisler
-- Description: Separate valid bits for data cache implemented with registers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cmvalidbits is
generic (
abits : integer;
nways : integer range 1 to 4
);
port (
clk : in std_ulogic;
caddr: in std_logic_vector(abits-1 downto 0);
cenable: in std_logic_vector(0 to nways-1);
cwrite: in std_logic_vector(0 to nways-1);
cwdata: in std_logic_vector(0 to nways-1);
crdata: out std_logic_vector(0 to nways-1);
saddr: in std_logic_vector(abits-1 downto 0);
sclear: in std_logic_vector(0 to nways-1);
flush: in std_ulogic
);
end;
architecture rtl of cmvalidbits is
type validbits_array_type is array(0 to 2**abits-1) of std_logic_vector(0 to nways-1);
type validbits_regs is record
valid: validbits_array_type;
pcaddr: std_logic_vector(abits-1 downto 0);
pcwrite: std_logic_vector(0 to nways-1);
pcwdata: std_logic_vector(0 to nways-1);
psaddr: std_logic_vector(abits-1 downto 0);
end record;
signal r,nr: validbits_regs;
begin
comb: process(r,caddr,cenable,cwrite,cwdata,saddr,sclear,flush)
variable vrdata: std_logic_vector(0 to nways-1);
variable v: validbits_regs;
variable wv: std_logic_vector(0 to nways-1);
variable av: std_logic_vector(abits-1 downto 0);
variable amask: std_logic_vector(0 to 2**abits-1);
begin
v := r;
v.pcaddr := caddr;
v.pcwrite := cenable and cwrite;
v.pcwdata := cwdata;
v.psaddr := saddr;
-- Note: sclear is asserted one cycle after saddr so no pipeline reg on that
vrdata := r.valid(to_integer(unsigned(r.pcaddr)));
for i in 0 to 2**abits-1 loop
wv := r.valid(i);
av := std_logic_vector(to_unsigned(i,abits));
if r.pcaddr=av then
for j in 0 to nways-1 loop
if r.pcwrite(j)='1' then
wv(j) := r.pcwdata(j);
end if;
end loop;
end if;
if r.psaddr=av then
for j in 0 to nways-1 loop
if sclear(j)='1' then
wv(j) := '0';
end if;
end loop;
end if;
if flush='1' then
wv := (others => '0');
end if;
v.valid(i) := wv;
end loop;
nr <= v;
crdata <= vrdata;
end process;
regs: process(clk)
begin
if rising_edge(clk) then r <= nr; end if;
end process;
end;
| gpl-3.0 | 13127cc1ea9e791a5af5fb06ca72e769 | 0.604012 | 3.53301 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-terasic-de2-115/config.vhd | 1 | 7,426 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := cyclone3;
constant CFG_MEMTECH : integer := cyclone3;
constant CFG_PADTECH : integer := cyclone3;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := cyclone3;
constant CFG_CLKMUL : integer := (5);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 4;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 4;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 1*2 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#0d0007#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 1;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- MIL-STD-1553 controllers
constant CFG_GR1553B_ENABLE : integer := 0;
constant CFG_GR1553B_RTEN : integer := 0;
constant CFG_GR1553B_BCEN : integer := 0;
constant CFG_GR1553B_BMEN : integer := 0;
-- CAN 2.0 interface
constant CFG_CAN : integer := 0;
constant CFG_CAN_NUM : integer := 1;
constant CFG_CANIO : integer := 16#0#;
constant CFG_CANIRQ : integer := 0;
constant CFG_CANSEPIRQ: integer := 0;
constant CFG_CAN_SYNCRST : integer := 0;
constant CFG_CANFT : integer := 0;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 1;
constant CFG_SPICTRL_NUM : integer := (1);
constant CFG_SPICTRL_SLVS : integer := (1);
constant CFG_SPICTRL_FIFO : integer := (2);
constant CFG_SPICTRL_SLVREG : integer := 1;
constant CFG_SPICTRL_ODMODE : integer := 1;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 1;
constant CFG_SPICTRL_MAXWLEN : integer := (0);
constant CFG_SPICTRL_SYNCRAM : integer := 1;
constant CFG_SPICTRL_FT : integer := 0;
-- SPI to AHB bridge
constant CFG_SPI2AHB : integer := 0;
constant CFG_SPI2AHB_APB : integer := 0;
constant CFG_SPI2AHB_ADDRH : integer := 16#0#;
constant CFG_SPI2AHB_ADDRL : integer := 16#0#;
constant CFG_SPI2AHB_MASKH : integer := 16#0#;
constant CFG_SPI2AHB_MASKL : integer := 16#0#;
constant CFG_SPI2AHB_RESEN : integer := 0;
constant CFG_SPI2AHB_FILTER : integer := 2;
constant CFG_SPI2AHB_CPOL : integer := 0;
constant CFG_SPI2AHB_CPHA : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (16);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#fe#;
constant CFG_GRGPIO_WIDTH : integer := (32);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-3.0 | 57ab1a88704696310f8f71e3e9a7fcb6 | 0.649205 | 3.551411 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/pci/pcipads.vhd | 1 | 10,997 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pcipads
-- File: pcipads.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: PCI pads module
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use work.pci.all;
library grlib;
use grlib.stdlib.all;
entity pcipads is
generic (
padtech : integer := 0;
noreset : integer := 0;
oepol : integer := 0;
host : integer := 1;
int : integer := 0;
no66 : integer := 0;
onchipreqgnt : integer := 0; -- Internal req and gnt signals
drivereset : integer := 0; -- Drive PCI rst with outpad
constidsel : integer := 0; -- pci_idsel is tied to local constant
level : integer := pci33; -- input/output level
voltage : integer := x33v; -- input/output voltage
nolock : integer := 0
);
port (
pci_rst : inout std_logic;
pci_gnt : in std_ulogic;
pci_idsel : in std_ulogic;
pci_lock : inout std_ulogic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_ulogic;
pci_irdy : inout std_ulogic;
pci_trdy : inout std_ulogic;
pci_devsel : inout std_ulogic;
pci_stop : inout std_ulogic;
pci_perr : inout std_ulogic;
pci_par : inout std_ulogic;
pci_req : inout std_ulogic; -- tristate pad but never read
pci_serr : inout std_ulogic; -- open drain output
pci_host : in std_ulogic;
pci_66 : in std_ulogic;
pcii : out pci_in_type;
pcio : in pci_out_type;
pci_int : inout std_logic_vector(3 downto 0) --:= conv_std_logic_vector(16#F#, 4) -- Disable int by default
--pci_int : inout std_logic_vector(3 downto 0) :=
-- conv_std_logic_vector(16#F# - (16#F# * oepol), 4) -- Disable int by default
);
end;
architecture rtl of pcipads is
signal vcc : std_ulogic;
begin
vcc <= '1';
-- Reset
rstpad : if noreset = 0 generate
nodrive: if drivereset = 0 generate
pci_rst_pad : iodpad generic map (tech => padtech, level => level,
voltage => voltage, oepol => 0)
port map (pci_rst, pcio.rst, pcii.rst);
end generate nodrive;
drive: if drivereset /= 0 generate
pci_rst_pad : outpad generic map (tech => padtech, level => level,
voltage => voltage)
port map (pci_rst, pcio.rst);
pcii.rst <= pcio.rst;
end generate drive;
end generate;
norstpad : if noreset = 1 generate
pcii.rst <= pci_rst;
end generate;
localgnt: if onchipreqgnt = 1 generate
pcii.gnt <= pci_gnt;
pci_req <= pcio.req when pcio.reqen = conv_std_logic(oepol=1) else '1';
end generate localgnt;
extgnt: if onchipreqgnt = 0 generate
pad_pci_gnt : inpad generic map (padtech, level, voltage) port map (pci_gnt, pcii.gnt);
pad_pci_req : toutpad generic map (tech => padtech, level => level,
voltage => voltage, oepol => oepol)
port map (pci_req, pcio.req, pcio.reqen);
end generate extgnt;
idsel_pad: if constidsel = 0 generate
pad_pci_idsel : inpad generic map (padtech, level, voltage) port map (pci_idsel, pcii.idsel);
end generate idsel_pad;
idsel_local: if constidsel /= 0 generate
pcii.idsel <= pci_idsel;
end generate idsel_local;
onlyhost : if host = 2 generate
pcii.host <= '0'; -- Always host
end generate;
dohost : if host = 1 generate
pad_pci_host : inpad generic map (padtech, level, voltage) port map (pci_host, pcii.host);
end generate;
nohost : if host = 0 generate
pcii.host <= '1'; -- disable pci host functionality
end generate;
do66 : if no66 = 0 generate
pad_pci_66 : inpad generic map (padtech, level, voltage) port map (pci_66, pcii.pci66);
end generate;
dono66 : if no66 = 1 generate
pcii.pci66 <= '0';
end generate;
dolock : if nolock = 0 generate
pad_pci_lock : iopad
generic map (tech => padtech, level => level,
voltage => voltage, oepol => oepol)
port map (pci_lock, pcio.lock, pcio.locken, pcii.lock);
end generate;
donolock : if nolock = 1 generate
pcii.lock <= pci_lock;
end generate;
pad_pci_ad : iopadvv generic map (tech => padtech, level => level,
voltage => voltage, width => 32,
oepol => oepol)
port map (pci_ad, pcio.ad, pcio.vaden, pcii.ad);
pad_pci_cbe0 : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_cbe(0), pcio.cbe(0), pcio.cbeen(0), pcii.cbe(0));
pad_pci_cbe1 : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_cbe(1), pcio.cbe(1), pcio.cbeen(1), pcii.cbe(1));
pad_pci_cbe2 : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_cbe(2), pcio.cbe(2), pcio.cbeen(2), pcii.cbe(2));
pad_pci_cbe3 : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_cbe(3), pcio.cbe(3), pcio.cbeen(3), pcii.cbe(3));
pad_pci_frame : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_frame, pcio.frame, pcio.frameen, pcii.frame);
pad_pci_trdy : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_trdy, pcio.trdy, pcio.trdyen, pcii.trdy);
pad_pci_irdy : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_irdy, pcio.irdy, pcio.irdyen, pcii.irdy);
pad_pci_devsel: iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_devsel, pcio.devsel, pcio.devselen, pcii.devsel);
pad_pci_stop : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_stop, pcio.stop, pcio.stopen, pcii.stop);
pad_pci_perr : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_perr, pcio.perr, pcio.perren, pcii.perr);
pad_pci_par : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_par, pcio.par, pcio.paren, pcii.par);
pad_pci_serr : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_serr, pcio.serr, pcio.serren, pcii.serr);
-- PCI interrupt pads
-- int = 0 => no interrupt
-- int = 1 => PCI_INT[A] = out, PCI_INT[B,C,D] = Not connected
-- int = 2 => PCI_INT[B] = out, PCI_INT[A,C,D] = Not connected
-- int = 3 => PCI_INT[C] = out, PCI_INT[A,B,D] = Not connected
-- int = 4 => PCI_INT[D] = out, PCI_INT[A,B,C] = Not connected
-- int = 10 => PCI_INT[A] = inout, PCI_INT[B,C,D] = in
-- int = 11 => PCI_INT[B] = inout, PCI_INT[A,C,D] = in
-- int = 12 => PCI_INT[C] = inout, PCI_INT[A,B,D] = in
-- int = 13 => PCI_INT[D] = inout, PCI_INT[A,B,C] = in
-- int = 14 => PCI_INT[A,B,C,D] = in
-- int = 100 => PCI_INT[A] = out, PCI_INT[B,C,D] = Not connected
-- int = 101 => PCI_INT[A,B] = out, PCI_INT[C,D] = Not connected
-- int = 102 => PCI_INT[A,B,C] = out, PCI_INT[D] = Not connected
-- int = 103 => PCI_INT[A,B,C,D] = out
-- int = 110 => PCI_INT[A] = inout, PCI_INT[B,C,D] = in
-- int = 111 => PCI_INT[A,B] = inout, PCI_INT[C,D] = in
-- int = 112 => PCI_INT[A,B,C] = inout, PCI_INT[D] = in
-- int = 113 => PCI_INT[A,B,C,D] = inout
interrupt : if int /= 0 generate
x : for i in 0 to 3 generate
xo : if i = int - 1 and int < 10 generate
pad_pci_int : odpad generic map (tech => padtech, level => level,
voltage => voltage, oepol => oepol)
port map (pci_int(i), pcio.inten);
end generate;
xonon : if i /= int - 1 and int < 10 and int < 100 generate
pci_int(i) <= '1';
end generate;
xio : if i = (int - 10) and int >= 10 and int < 100 generate
pad_pci_int : iodpad generic map (tech => padtech, level => level,
voltage => voltage, oepol => oepol)
port map (pci_int(i), pcio.inten, pcii.int(i));
end generate;
xi : if i /= (int - 10) and int >= 10 and int < 100 generate
pad_pci_int : inpad generic map (tech => padtech, level => level, voltage => voltage)
port map (pci_int(i), pcii.int(i));
end generate;
x2o : if i <= (int - 100) and int < 110 and int >= 100 generate
pad_pci_int : odpad generic map (tech => padtech, level => level,
voltage => voltage, oepol => oepol)
port map (pci_int(i), pcio.vinten(i));
end generate;
x2onon : if i > (int - 100) and int < 110 and int >= 100 generate
pci_int(i) <= '1';
end generate;
x2oi : if i <= (int - 110) and int >= 110 generate
pad_pci_int : iodpad generic map (tech => padtech, level => level,
voltage => voltage, oepol => oepol)
port map (pci_int(i), pcio.vinten(i), pcii.int(i));
end generate;
x2i : if i > (int - 110) and int >= 110 generate
pad_pci_int : inpad generic map (tech => padtech, level => level, voltage => voltage)
port map (pci_int(i), pcii.int(i));
end generate;
end generate;
end generate;
nointerrupt : if int = 0 generate
pcii.int <= (others => '0');
end generate;
pcii.pme_status <= '0';
end;
| gpl-3.0 | 27ad7e8d9197b073f790531161878075 | 0.571701 | 3.511175 | false | false | false | false |
hoglet67/CoPro6502 | src/LX9Co_CoPro68000.vhd | 1 | 8,509 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity LX9CoPro68000 is
port (
-- GOP Signals
fastclk : in std_logic;
test : inout std_logic_vector(8 downto 1);
sw : in std_logic_vector(3 downto 0);
-- Tube signals (use 16 out of 22 DIL pins)
h_phi2 : in std_logic; -- 1,2,12,21,23 are global clocks
h_addr : in std_logic_vector(2 downto 0);
h_data : inout std_logic_vector(7 downto 0);
h_rdnw : in std_logic;
h_cs_b : in std_logic;
h_rst_b : in std_logic;
h_irq_b : inout std_logic;
-- Ram Signals
ram_ub_b : out std_logic;
ram_lb_b : out std_logic;
ram_cs : out std_logic;
ram_oe : out std_logic;
ram_wr : out std_logic;
ram_addr : out std_logic_vector (18 downto 0);
ram_data : inout std_logic_vector (15 downto 0)
);
end LX9CoPro68000;
architecture BEHAVIORAL of LX9CoPro68000 is
-------------------------------------------------
-- clock and reset signals
-------------------------------------------------
signal cpu_clk : std_logic;
signal cpu_clken : std_logic;
signal clken_counter : std_logic_vector (1 downto 0);
signal bootmode : std_logic;
signal RSTn : std_logic;
signal RSTn_sync : std_logic;
-------------------------------------------------
-- parasite signals
-------------------------------------------------
signal p_cs_b : std_logic;
signal p_cs_b_old : std_logic;
signal tube_cs_b : std_logic;
signal p_data_in : std_logic_vector (7 downto 0);
signal p_data_out : std_logic_vector (7 downto 0);
signal p_data_out_r : std_logic_vector (7 downto 0);
-------------------------------------------------
-- ram/rom signals
-------------------------------------------------
signal ram_cs_b : std_logic;
signal ram_oe_int : std_logic;
signal ram_wr_int : std_logic;
signal rom_cs_b : std_logic;
signal rom_data_out : std_logic_vector (15 downto 0);
-------------------------------------------------
-- cpu signals
-------------------------------------------------
signal cpu_addr : std_logic_vector (31 downto 0);
signal cpu_din : std_logic_vector (15 downto 0);
signal cpu_dout : std_logic_vector (15 downto 0);
signal cpu_IRQ_n : std_logic;
signal cpu_NMI_n : std_logic;
signal cpu_IRQ_n_sync : std_logic;
signal cpu_NMI_n_sync : std_logic;
signal cpu_as : std_logic;
signal cpu_uds : std_logic;
signal cpu_lds : std_logic;
signal cpu_R_W_n : std_logic;
signal cpu_data_drive : std_logic;
begin
---------------------------------------------------------------------
-- instantiated components
---------------------------------------------------------------------
inst_icap_config : entity work.icap_config port map (
fastclk => fastclk,
sw_in => sw,
sw_out => open,
h_addr => h_addr,
h_cs_b => h_cs_b,
h_data => h_data,
h_phi2 => h_phi2,
h_rdnw => h_rdnw,
h_rst_b => h_rst_b
);
inst_dcm_32_16 : entity work.dcm_32_16 port map (
CLKIN_IN => fastclk,
CLK0_OUT => cpu_clk,
CLK0_OUT1 => open,
CLK2X_OUT => open);
inst_tuberom : entity work.tuberom_68000 port map (
CLK => cpu_clk,
ADDR => cpu_addr(14 downto 1),
DATA => rom_data_out
);
Inst_tg68: entity work.TG68 port map (
clk => cpu_clk,
reset => RSTn_sync,
clkena_in => cpu_clken,
data_in => cpu_din,
IPL => CPU_NMI_n_sync & CPU_IRQ_n_sync & CPU_NMI_n_sync,
dtack => '0',
addr => cpu_addr,
data_out => cpu_dout,
as => cpu_as,
uds => cpu_uds,
lds => cpu_lds,
rw => cpu_R_W_n,
drive_data => cpu_data_drive
);
inst_tube: entity work.tube port map (
h_addr => h_addr,
h_cs_b => h_cs_b,
h_data => h_data,
h_phi2 => h_phi2,
h_rdnw => h_rdnw,
h_rst_b => h_rst_b,
h_irq_b => h_irq_b,
p_addr => cpu_addr(2 downto 1) & cpu_uds,
p_cs_b => tube_cs_b,
p_data_in => p_data_in,
p_data_out => p_data_out,
p_rdnw => cpu_R_W_n,
p_phi2 => cpu_clk,
p_rst_b => RSTn,
p_nmi_b => cpu_NMI_n,
p_irq_b => cpu_IRQ_n
);
p_data_in <= cpu_dout(15 downto 8) when cpu_uds = '0' else
cpu_dout(7 downto 0) when cpu_lds = '0' else
x"ff";
tube_cs_b <= not ((not p_cs_b) and cpu_clken and (not cpu_uds or not cpu_lds));
-- Tube address is $FFFExxxx, and A0..A2 go into the Tube ULA
-- Incomplete decoding as per Eelco's schenatic
p_cs_b <= '0' when (cpu_as = '0' and cpu_addr(21 downto 16) = "111110")
else '1';
-- ROM addess is $FFFFxxxx
-- In boot mode, ROM also mapped to $0000xxxx
rom_cs_b <= '0' when (cpu_as = '0' and cpu_addr(21 downto 16) = "111111") or
(cpu_as = '0' and cpu_addr(21 downto 16) = "000000" and bootmode = '1')
else '1';
-- RAM otherwise
ram_cs_b <= '0' when cpu_as = '0' and p_cs_b = '1' and rom_cs_b = '1'
else '1';
-- This is a bit of a cludge, but the 68000 asserts UDS/LDS for multiple cycles
-- which causes problems reading R3 data (address 101) because of an anomaly/bug
-- in the Tube implementation of R3. To get around this, we latch the data beging read
tube_data_latch : process(cpu_clk)
begin
if rising_edge(cpu_clk) then
if (cpu_clken = '1') then
p_cs_b_old <= p_cs_b;
if (p_cs_b_old = '1' and p_cs_b = '0') then
p_data_out_r <= p_data_out;
end if;
end if;
end if;
end process;
cpu_din <=
p_data_out_r & p_data_out_r when p_cs_b = '0' else
rom_data_out when rom_cs_b = '0' else
ram_data when ram_cs_b = '0' else
x"f1f1";
ram_ub_b <= cpu_uds;
ram_lb_b <= cpu_lds;
ram_cs <= ram_cs_b;
ram_oe_int <= not ((not ram_cs_b) and cpu_R_W_n);
ram_oe <= ram_oe_int;
ram_wr_int <= not ((not ram_cs_b) and (not cpu_R_W_n) and cpu_clken);
ram_wr <= ram_wr_int;
ram_addr <= cpu_addr(19 downto 1);
ram_data <= cpu_dout when cpu_data_drive = '1' else "ZZZZZZZZZZZZZZZZ";
--------------------------------------------------------
-- test signals
--------------------------------------------------------
-- default to hi-impedence, to avoid conflicts with
-- a Raspberry Pi connected to the test connector
test <= (others => 'Z');
--------------------------------------------------------
-- boot mode generator
--------------------------------------------------------
boot_gen : process(cpu_clk, RSTn_sync)
begin
if RSTn_sync = '0' then
bootmode <= '1';
elsif rising_edge(cpu_clk) then
if cpu_as = '0' and cpu_addr(21 downto 19) = "111" then
bootmode <= '0';
end if;
end if;
end process;
--------------------------------------------------------
-- synchronize interrupts etc into 68000 core
--------------------------------------------------------
sync_gen : process(cpu_clk, RSTn_sync)
begin
if RSTn_sync = '0' then
cpu_NMI_n_sync <= '1';
cpu_IRQ_n_sync <= '1';
elsif rising_edge(cpu_clk) then
cpu_NMI_n_sync <= cpu_NMI_n;
cpu_IRQ_n_sync <= cpu_IRQ_n;
end if;
end process;
--------------------------------------------------------
-- clock enable generator
--------------------------------------------------------
clk_gen : process(cpu_clk)
begin
if rising_edge(cpu_clk) then
clken_counter <= clken_counter + 1;
cpu_clken <= clken_counter(0);
RSTn_sync <= RSTn;
end if;
end process;
end BEHAVIORAL;
| gpl-3.0 | ee07b78ed2a58932a396ab84699a915b | 0.447879 | 3.516116 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-altera-ep3c25-eek/config.vhd | 1 | 7,273 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := cyclone3;
constant CFG_MEMTECH : integer := cyclone3;
constant CFG_PADTECH : integer := cyclone3;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := cyclone3;
constant CFG_CLKMUL : integer := (5);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 1;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 1;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0039#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000011#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- SSRAM controller
constant CFG_SSCTRL : integer := 0;
constant CFG_SSCTRLP16 : integer := 0;
-- DDR controller
constant CFG_DDRSP : integer := 1;
constant CFG_DDRSP_INIT : integer := 1;
constant CFG_DDRSP_FREQ : integer := (100);
constant CFG_DDRSP_COL : integer := (9);
constant CFG_DDRSP_SIZE : integer := (32);
constant CFG_DDRSP_RSKEW : integer := (2500);
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 64;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0#;
constant CFG_GRGPIO_WIDTH : integer := (5);
-- I2C master
constant CFG_I2C_ENABLE : integer := 1;
-- PS/2 interface
constant CFG_PS2_ENABLE : integer := 1;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 1;
constant CFG_SPICTRL_NUM : integer := (1);
constant CFG_SPICTRL_SLVS : integer := (1);
constant CFG_SPICTRL_FIFO : integer := (2);
constant CFG_SPICTRL_SLVREG : integer := 1;
constant CFG_SPICTRL_ODMODE : integer := 0;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 0;
constant CFG_SPICTRL_MAXWLEN : integer := (0);
constant CFG_SPICTRL_SYNCRAM : integer := 0;
constant CFG_SPICTRL_FT : integer := 0;
-- LCD SVGA controller
constant CFG_LCD_ENABLE : integer := 1;
-- LCD 3-wire serial interface
constant CFG_LCD3T_ENABLE : integer := 1;
-- SVGA controller
constant CFG_SVGA_ENABLE : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-3.0 | c6a9824e7a8e1069dc70d92872f014a2 | 0.647601 | 3.604063 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/leon3v3/dsu3x.vhd | 1 | 40,314 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: dsu
-- File: dsu.vhd
-- Author: Jiri Gaisler, Edvin Catovic - Gaisler Research
-- Description: Combined LEON3 debug support and AHB trace unit
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.config_types.all;
use grlib.config.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.leon3.all;
library techmap;
use techmap.gencomp.all;
entity dsu3x is
generic (
hindex : integer := 0;
haddr : integer := 16#900#;
hmask : integer := 16#f00#;
ncpu : integer := 1;
tbits : integer := 30; -- timer bits (instruction trace time tag)
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 0;
clk2x : integer range 0 to 1 := 0;
testen : integer := 0;
bwidth : integer := 32;
ahbpf : integer := 0
);
port (
rst : in std_ulogic;
hclk : in std_ulogic;
cpuclk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
tahbsi : in ahb_slv_in_type;
dbgi : in l3_debug_out_vector(0 to NCPU-1);
dbgo : out l3_debug_in_vector(0 to NCPU-1);
dsui : in dsu_in_type;
dsuo : out dsu_out_type;
hclken : in std_ulogic
);
attribute sync_set_reset of rst : signal is "true";
end;
architecture rtl of dsu3x is
constant TBUFABITS : integer := log2(kbytes) + 6;
constant NBITS : integer := log2x(ncpu);
constant PROC_H : integer := 24+NBITS-1;
constant PROC_L : integer := 24;
constant AREA_H : integer := 23;
constant AREA_L : integer := 20;
constant HBITS : integer := 28;
constant DSU3_VERSION : integer := 2;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_LEON3DSU, 0, DSU3_VERSION, 0),
4 => ahb_membar(haddr, '0', '0', hmask),
others => zero32);
type slv_reg_type is record
hsel : std_ulogic;
haddr : std_logic_vector(PROC_H downto 0);
hwrite : std_ulogic;
hwdata : std_logic_vector(31 downto 0);
hrdata : std_logic_vector(31 downto 0);
hready : std_ulogic;
hready2 : std_ulogic;
end record;
constant slv_reg_none : slv_reg_type := (
hsel => '0',
haddr => (others => '0'),
hwrite => '0',
hwdata => (others => '0'),
hrdata => (others => '0'),
hready => '1',
hready2 => '1'
);
type reg_type is record
slv : slv_reg_type;
en : std_logic_vector(0 to NCPU-1);
te : std_logic_vector(0 to NCPU-1);
be : std_logic_vector(0 to NCPU-1);
bw : std_logic_vector(0 to NCPU-1);
bs : std_logic_vector(0 to NCPU-1);
bx : std_logic_vector(0 to NCPU-1);
bz : std_logic_vector(0 to NCPU-1);
halt : std_logic_vector(0 to NCPU-1);
reset : std_logic_vector(0 to NCPU-1);
bn : std_logic_vector(NCPU-1 downto 0);
ss : std_logic_vector(NCPU-1 downto 0);
bmsk : std_logic_vector(NCPU-1 downto 0);
dmsk : std_logic_vector(NCPU-1 downto 0);
cnt : std_logic_vector(2 downto 0);
dsubre : std_logic_vector(2 downto 0);
dsuen : std_logic_vector(2 downto 0);
act : std_ulogic;
timer : std_logic_vector(tbits-1 downto 0);
pwd : std_logic_vector(NCPU-1 downto 0);
tstop : std_ulogic;
end record;
constant RRES : reg_type := (
slv => slv_reg_none,
en => (others => '0'),
te => (others => '0'),
be => (others => '0'),
bw => (others => '0'),
bs => (others => '0'),
bx => (others => '0'),
bz => (others => '0'),
halt => (others => '0'),
reset => (others => '0'),
bn => (others => '0'),
ss => (others => '0'),
bmsk => (others => '0'),
dmsk => (others => '0'),
cnt => (others => '0'),
dsubre => (others => '0'),
dsuen => (others => '0'),
act => '0',
timer => (others => '0'),
pwd => (others => '0'),
tstop => '0'
);
type trace_break_reg is record
addr : std_logic_vector(31 downto 2);
mask : std_logic_vector(31 downto 2);
read : std_logic;
write : std_logic;
end record;
constant trace_break_none : trace_break_reg := (
addr => (others => '0'),
mask => (others => '0'),
read => '0',
write => '0'
);
type tregtype is record
haddr : std_logic_vector(31 downto 0);
hwrite : std_logic;
htrans : std_logic_vector(1 downto 0);
hsize : std_logic_vector(2 downto 0);
hburst : std_logic_vector(2 downto 0);
hwdata : std_logic_vector(31 downto 0);
hmaster : std_logic_vector(3 downto 0);
hmastlock : std_logic;
ahbactive : std_logic;
aindex : std_logic_vector(TBUFABITS - 1 downto 0); -- buffer index
enable : std_logic; -- trace enable
bphit : std_logic; -- AHB breakpoint hit
bphit2 : std_logic; -- delayed bphit
dcnten : std_logic; -- delay counter enable
delaycnt : std_logic_vector(TBUFABITS - 1 downto 0); -- delay counter
tbreg1 : trace_break_reg;
tbreg2 : trace_break_reg;
tbwr : std_logic; -- trace buffer write enable
break : std_logic; -- break CPU when AHB tracing stops
tforce : std_logic; -- Force AHB trace
timeren : std_logic; -- Keep timer enabled
sample : std_logic; -- Force sample
end record;
constant TRES : tregtype := (
haddr => (others => '0'),
hwrite => '0',
htrans => (others => '0'),
hsize => (others => '0'),
hburst => (others => '0'),
hwdata => (others => '0'),
hmaster => (others => '0'),
hmastlock => '0',
ahbactive => '0',
aindex => (others => '0'),
enable => '0',
bphit => '0',
bphit2 => '0',
dcnten => '0',
delaycnt => (others => '0'),
tbreg1 => trace_break_none,
tbreg2 => trace_break_none,
tbwr => '0',
break => '0',
tforce => '0',
timeren => '0',
sample => '0'
);
type tfregtype is record
shsel : std_logic_vector(0 to NAHBSLV-1);
pf : std_ulogic; -- Filter perf outputs
af : std_ulogic; -- Address filtering
fr : std_ulogic; -- Filter reads
fw : std_ulogic; -- Filter writes
smask : std_logic_vector(15 downto 0);
mmask : std_logic_vector(15 downto 0);
bpfilt : std_logic_vector(1 downto 0);
end record;
type pregtype is record
stat : dsu_astat_type;
split : std_ulogic;
splmst : std_logic_vector(3 downto 0);
hready : std_ulogic;
hresp : std_logic_vector(1 downto 0);
end record;
constant PRES : pregtype := (
stat => dsu_astat_none, split => '0', splmst => "0000", hready => '1', hresp => "00");
constant TFRES : tfregtype :=
(shsel => (others => '0'), pf => '0', af => '0', fr => '0', fw => '0',
smask => (others => '0'), mmask => (others => '0'),
bpfilt => (others => '0'));
type hclk_reg_type is record
irq : std_ulogic;
oen : std_ulogic;
end record;
constant hclk_reg_none : hclk_reg_type := (
irq => '0', oen => '0'
);
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant TRACEN : boolean := (kbytes /= 0);
constant FILTEN : boolean := TRACEN and (ahbpf > 0);
constant PERFEN : boolean := (ahbpf > 1);
function ahb_filt_hit (
tr : tregtype;
tfr : tfregtype) return boolean is
variable hit : boolean;
begin
-- filter hit -> inhibit
hit := false;
-- Filter on read/write
if ((tfr.fw and tr.hwrite) or (tfr.fr and not tr.hwrite)) = '1' then
hit := true;
end if;
-- Filter on address range
if (((tr.tbreg2.addr xor tr.haddr(31 downto 2)) and tr.tbreg2.mask) /= zero32(29 downto 0)) then
if tfr.af = '1' then hit := true; end if;
end if;
-- Filter on master mask
for i in tfr.mmask'range loop
if i > NAHBMST-1 then exit; end if;
if i = conv_integer(tr.hmaster) and tfr.mmask(i) = '1' then
hit := true;
end if;
end loop;
-- Filter on slave mask
for i in tfr.smask'range loop
if i > NAHBSLV-1 then exit; end if;
if (tfr.shsel(i) and tfr.smask(i)) /= '0' then
hit := true;
end if;
end loop;
return hit;
end function ahb_filt_hit;
signal tbi : tracebuf_in_type;
signal tbo : tracebuf_out_type;
signal pr, prin : pregtype;
signal tfr, tfrin : tfregtype;
signal tr, trin : tregtype;
signal r, rin : reg_type;
signal rh, rhin : hclk_reg_type;
signal ahbsi2, tahbsi2 : ahb_slv_in_type;
signal hrdata2x : std_logic_vector(31 downto 0);
begin
comb: process(rst, r, ahbsi, ahbsi2, tahbsi2, dbgi, dsui, ahbmi, tr, tbo, hclken, rh, hrdata2x, tfr, pr)
variable v : reg_type;
variable iuacc : std_ulogic;
variable dbgmode, tstop : std_ulogic;
variable rawindex : integer range 0 to (2**NBITS)-1;
variable index : natural range 0 to NCPU-1;
variable hasel1 : std_logic_vector(AREA_H-1 downto AREA_L);
variable hasel2 : std_logic_vector(6 downto 2);
variable tv : tregtype;
variable vabufi : tracebuf_in_type;
variable aindex : std_logic_vector(TBUFABITS - 1 downto 0); -- buffer index
variable hirq : std_logic_vector(NAHBIRQ-1 downto 0);
variable cpwd : std_logic_vector(15 downto 0);
variable hrdata : std_logic_vector(31 downto 0);
variable hwdata : std_logic_vector(31 downto 0);
variable rdata, wdata : std_logic_vector(127 downto 0);
variable bphit : std_logic_vector(1 to 2);
variable vh : hclk_reg_type;
variable atact : std_ulogic; -- ahb trace active
variable tfv : tfregtype;
variable pv : pregtype;
variable slvhaddr : std_logic_vector(2 downto 0);
begin
v := r;
iuacc := '0'; --v.slv.hready := '0';
dbgmode := '0'; tstop := '1';
v.dsubre := r.dsubre(1 downto 0) & dsui.break;
v.dsuen := r.dsuen(1 downto 0) & dsui.enable;
hrdata := r.slv.hrdata; hwdata := ahbreadword(ahbsi2.hwdata, r.slv.haddr(4 downto 2));
wdata := (others => '0'); rdata := (others => '0');
tv := tr; vabufi.enable := '0'; tv.bphit := '0'; tv.tbwr := '0'; tv.sample := '0';
if (clk2x /= 0) then tv.bphit2 := tr.bphit; else tv.bphit2 := '0'; end if;
vabufi.data := (others => '0'); vabufi.addr := (others => '0');
vabufi.write := (others => '0'); aindex := (others => '0');
hirq := (others => '0'); v.reset := (others => '0');
tfv := tfr; pv := pr;
if TRACEN then
aindex := tr.aindex + 1;
if (clk2x /= 0) then vh.irq := tr.bphit or tr.bphit2; hirq(irq) := rh.irq;
else hirq(irq) := tr.bphit; end if;
end if;
if hclken = '1' then
v.slv.hready := '0'; v.act := '0';
end if;
atact := tr.enable and ((not r.act) or tr.tforce);
-- check for AHB watchpoints
bphit := (others => '0');
if TRACEN and ((tahbsi2.hready and tr.ahbactive) = '1') then
if ((((tr.tbreg1.addr xor tr.haddr(31 downto 2)) and tr.tbreg1.mask) = zero32(29 downto 0)) and
(((tr.tbreg1.read and not tr.hwrite) or (tr.tbreg1.write and tr.hwrite)) = '1'))
then bphit(1) := '1'; end if;
if ((((tr.tbreg2.addr xor tr.haddr(31 downto 2)) and tr.tbreg2.mask) = zero32(29 downto 0)) and
(((tr.tbreg2.read and not tr.hwrite) or (tr.tbreg2.write and tr.hwrite)) = '1'))
then bphit(2) := '1'; end if;
end if;
-- generate AHB buffer inputs
vabufi.write := (others => '0');
if TRACEN then
wdata(AHBDW-1 downto 0) := tahbsi2.hwdata;
rdata(AHBDW-1 downto 0) := ahbmi.hrdata;
if atact = '1' then
vabufi.addr(TBUFABITS-1 downto 0) := tr.aindex;
vabufi.data(127) := orv(bphit);
vabufi.data(96+tbits-1 downto 96) := r.timer;
vabufi.data(94 downto 80) := (others => '0'); --ahbmi.hirq(15 downto 1);
vabufi.data(79) := tr.hwrite;
vabufi.data(78 downto 77) := tr.htrans;
vabufi.data(76 downto 74) := tr.hsize;
vabufi.data(73 downto 71) := tr.hburst;
vabufi.data(70 downto 67) := tr.hmaster;
vabufi.data(66) := tr.hmastlock;
vabufi.data(65 downto 64) := ahbmi.hresp;
if tr.hwrite = '1' then
vabufi.data(63 downto 32) := wdata(31 downto 0);
vabufi.data(223 downto 128) := wdata(127 downto 32);
else
vabufi.data(63 downto 32) := rdata(31 downto 0);
vabufi.data(223 downto 128) := rdata(127 downto 32);
end if;
vabufi.data(31 downto 0) := tr.haddr;
else
if bwidth = 32 then
vabufi.addr(TBUFABITS-1 downto 0) := r.slv.haddr(TBUFABITS+3 downto 4); --tr.haddr(TBUFABITS+3 downto 4);
else
vabufi.addr(TBUFABITS-1 downto 0) := r.slv.haddr(TBUFABITS+4 downto 5); --tr.haddr(TBUFABITS+4 downto 5);
end if;
-- Note: HWDATA from register i/f
vabufi.data(255 downto 0) := hwdata & hwdata & hwdata & hwdata & hwdata & hwdata & hwdata & hwdata;
end if;
-- filter and write trace buffer
if atact = '1' then
if ((tr.ahbactive and tahbsi2.hready) or tr.sample) = '1' then
if not (FILTEN and ahb_filt_hit(tr, tfr)) then
tv.aindex := aindex; tv.tbwr := '1';
vabufi.enable := '1'; vabufi.write := (others => '1');
elsif FILTEN then
for i in 1 to 2 loop
if tfr.bpfilt(i-1) = '1' then bphit(i) := '0'; end if;
end loop;
end if;
end if;
end if;
-- trigger AHB break/watchpoints
if orv(bphit) = '1' then
if (atact = '1') and (tr.dcnten = '0') and
(tr.delaycnt /= zero32(TBUFABITS-1 downto 0))
then tv.dcnten := '1';
else tv.enable := '0'; tv.tforce := '0'; tv.timeren := '0'; tv.bphit := tr.break; end if;
end if;
-- trace buffer delay counter handling
if (tr.dcnten = '1') then
if (tr.delaycnt = zero32(TBUFABITS-1 downto 0)) then
tv.enable := '0'; tv.dcnten := '0'; tv.bphit := tr.break;
end if;
if tr.tbwr = '1' then tv.delaycnt := tr.delaycnt - 1; end if;
end if;
-- AHB statistics
if PERFEN then
pv.hready := tahbsi2.hready;
pv.hresp := ahbmi.hresp;
pv.stat := dsu_astat_none;
if pr.hready = '1' then
case tr.htrans is
when HTRANS_IDLE => pv.stat.idle := '1';
when HTRANS_BUSY => pv.stat.busy := '1';
when HTRANS_NONSEQ => pv.stat.nseq := '1';
when others => pv.stat.seq := '1';
end case;
if tr.ahbactive = '1' then
pv.stat.read := not tr.hwrite;
pv.stat.write := tr.hwrite;
case tr.hsize is
when HSIZE_BYTE => pv.stat.hsize(0) := '1';
when HSIZE_HWORD => pv.stat.hsize(1) := '1';
when HSIZE_WORD => pv.stat.hsize(2) := '1';
when HSIZE_DWORD => pv.stat.hsize(3) := '1';
when HSIZE_4WORD => pv.stat.hsize(4) := '1';
when others => pv.stat.hsize(5) := '1';
end case;
end if;
pv.stat.hmaster := tr.hmaster;
end if;
if pr.hresp = HRESP_OKAY then
pv.stat.ws := not pr.hready;
end if;
-- It may also be interesting to count the maximum grant latency. That
-- is; the delay between asserting hbusreq and receiving hgrant. This
-- would require that all bus request signals were present in this
-- entity. This has been left as a possible future extension.
if pr.hready = '1' then
if pr.hresp = HRESP_SPLIT then
pv.stat.split := '1';
pv.split := '1';
if pr.split = '0' then
pv.splmst := tr.hmaster;
end if;
end if;
if pr.hresp = HRESP_RETRY then
pv.stat.retry := '1';
end if;
end if;
pv.stat.locked := tr.hmastlock;
if tfr.pf = '1' and ahb_filt_hit(tr, tfr) then
pv.stat := dsu_astat_none;
pv.split := pr.split; pv.splmst := pr.splmst;
end if;
-- Count cycles where master is in SPLIT
if pr.split = '1' then
for i in ahbmi.hgrant'range loop
if i = conv_integer(pr.splmst) and ahbmi.hgrant(i) = '1' then
pv.split := '0';
end if;
end loop;
pv.stat.spdel := pv.split;
end if;
end if;
-- save AHB transfer parameters
if (tahbsi2.hready or tr.sample) = '1' then
tv.haddr := tahbsi2.haddr; tv.hwrite := tahbsi2.hwrite; tv.htrans := tahbsi2.htrans;
tv.hsize := tahbsi2.hsize; tv.hburst := tahbsi2.hburst;
tv.hmaster := tahbsi2.hmaster; tv.hmastlock := tahbsi2.hmastlock;
tv.ahbactive := tahbsi2.htrans(1);
if FILTEN then tfv.shsel := tahbsi2.hsel; end if;
end if;
end if;
if r.slv.hsel = '1' then
if (clk2x = 0) then
v.cnt := r.cnt - 1;
else
if (r.cnt /= "111") or (hclken = '1') then v.cnt := r.cnt - 1; end if;
end if;
end if;
if (r.slv.hready and hclken) = '1' then
v.slv.hsel := '0'; --v.slv.act := '0';
end if;
for i in 0 to NCPU-1 loop
if dbgi(i).dsumode = '1' then
if r.dmsk(i) = '0' then
dbgmode := '1';
if hclken = '1' then v.act := '1'; end if;
end if;
v.bn(i) := '1';
else
tstop := '0';
end if;
end loop;
if ((r.dsuen(2) and not tstop) or tr.timeren) = '1' then v.timer := r.timer + 1; end if;
if (clk2x /= 0) then
if hclken = '1' then v.tstop := tstop; end if;
tstop := r.tstop;
end if;
cpwd := (others => '0');
for i in 0 to NCPU-1 loop
v.bn(i) := v.bn(i) or (dbgmode and r.bmsk(i)) or (r.dsubre(1) and not r.dsubre(2));
if TRACEN then v.bn(i) := v.bn(i) or (tr.bphit and not r.ss(i) and not r.act); end if;
v.pwd(i) := dbgi(i).idle and (not dbgi(i).ipend) and not v.bn(i);
end loop;
cpwd(NCPU-1 downto 0) := r.pwd;
if (ahbsi2.hready and ahbsi2.hsel(hindex)) = '1' then
if (ahbsi2.htrans(1) = '1') then
v.slv.hsel := '1';
v.slv.haddr := ahbsi2.haddr(PROC_H downto 0);
v.slv.hwrite := ahbsi2.hwrite;
v.cnt := "111";
end if;
end if;
for i in 0 to NCPU-1 loop
v.en(i) := r.dsuen(2) and dbgi(i).dsu;
end loop;
rawindex := conv_integer(r.slv.haddr(PROC_H downto PROC_L));
if ncpu = 1 then index := 0; else
if rawindex > ncpu then index := ncpu-1; else index := rawindex; end if;
end if;
hasel1 := r.slv.haddr(AREA_H-1 downto AREA_L);
hasel2 := r.slv.haddr(6 downto 2);
if r.slv.hsel = '1' then
case hasel1 is
when "000" => -- DSU registers
if r.cnt(2 downto 0) = "110" then
if hclken = '1' then v.slv.hready := '1'; else v.slv.hready2 := '1'; end if;
end if;
hrdata := (others => '0');
case hasel2 is
when "00000" =>
if r.slv.hwrite = '1' then
if hclken = '1' then
v.te(index) := hwdata(0);
v.be(index) := hwdata(1);
v.bw(index) := hwdata(2);
v.bs(index) := hwdata(3);
v.bx(index) := hwdata(4);
v.bz(index) := hwdata(5);
v.reset(index) := hwdata(9);
v.halt(index) := hwdata(10);
else v.reset := r.reset; end if;
end if;
hrdata(0) := r.te(index);
hrdata(1) := r.be(index);
hrdata(2) := r.bw(index);
hrdata(3) := r.bs(index);
hrdata(4) := r.bx(index);
hrdata(5) := r.bz(index);
hrdata(6) := dbgi(index).dsumode;
hrdata(7) := r.dsuen(2);
hrdata(8) := r.dsubre(2);
hrdata(9) := not dbgi(index).error;
hrdata(10) := dbgi(index).halt;
hrdata(11) := dbgi(index).pwd;
when "00010" => -- timer
if r.slv.hwrite = '1' then
if hclken = '1' then
v.timer := hwdata(tbits-1 downto 0);
else v.timer := r.timer; end if;
end if;
hrdata(tbits-1 downto 0) := r.timer;
when "01000" =>
if r.slv.hwrite = '1' then
if hclken = '1' then
v.bn := hwdata(NCPU-1 downto 0);
v.ss := hwdata(16+NCPU-1 downto 16);
else v.bn := r.bn; v.ss := r.ss; end if;
end if;
hrdata(NCPU-1 downto 0) := r.bn;
hrdata(16+NCPU-1 downto 16) := r.ss;
when "01001" =>
if (r.slv.hwrite and hclken) = '1' then
v.bmsk(NCPU-1 downto 0) := hwdata(NCPU-1 downto 0);
v.dmsk(NCPU-1 downto 0) := hwdata(NCPU-1+16 downto 16);
end if;
hrdata(NCPU-1 downto 0) := r.bmsk;
hrdata(NCPU-1+16 downto 16) := r.dmsk;
when "10000" =>
if TRACEN then
hrdata((TBUFABITS + 15) downto 16) := tr.delaycnt;
hrdata(6 downto 5) := tr.timeren & tr.tforce;
hrdata(4 downto 0) := conv_std_logic_vector(log2(bwidth/32), 2) & tr.break & tr.dcnten & tr.enable;
if r.slv.hwrite = '1' then
if hclken = '1' then
tv.delaycnt := hwdata((TBUFABITS+ 15) downto 16);
tv.sample := hwdata(7);
tv.timeren := hwdata(6);
tv.tforce := hwdata(5);
tv.break := hwdata(2);
tv.dcnten := hwdata(1);
tv.enable := hwdata(0);
else
tv.delaycnt := tr.delaycnt;
tv.sample := tr.sample; tv.timeren := tr.timeren;
tv.tforce := tr.tforce; tv.break := tr.break;
tv.dcnten := tr.dcnten; tv.enable := tr.enable;
end if;
end if;
end if;
when "10001" =>
if TRACEN then
hrdata((TBUFABITS - 1 + 4) downto 4) := tr.aindex;
if r.slv.hwrite = '1' then
if hclken = '1' then
tv.aindex := hwdata((TBUFABITS - 1 + 4) downto 4);
else tv.aindex := tr.aindex; end if;
end if;
end if;
when "10010" =>
if FILTEN then
hrdata(9 downto 8) := tfr.bpfilt;
hrdata(3 downto 0) := tfr.pf & tfr.af & tfr.fr & tfr.fw;
if r.slv.hwrite = '1' then
if hclken = '1' then
tfv.bpfilt := hwdata(9 downto 8);
tfv.pf := hwdata(3);
tfv.af := hwdata(2);
tfv.fr := hwdata(1);
tfv.fw := hwdata(0);
else
tfv.bpfilt := tfr.bpfilt;
tfv.pf := tfr.pf;
tfv.af := tfr.af;
tfv.fr := tfr.fr;
tfv.fw := tfr.fw;
end if;
end if;
end if;
when "10011" =>
if FILTEN then
hrdata := tfr.smask & tfr.mmask;
if r.slv.hwrite = '1' then
if hclken = '1' then
tfv.smask := hwdata(31 downto 16);
tfv.mmask := hwdata(15 downto 0);
else
tfv.smask := tfr.smask;
tfv.mmask := tfr.mmask;
end if;
end if;
end if;
when "10100" =>
if TRACEN then
hrdata(31 downto 2) := tr.tbreg1.addr;
if (r.slv.hwrite and hclken) = '1' then
tv.tbreg1.addr := hwdata(31 downto 2);
end if;
end if;
when "10101" =>
if TRACEN then
hrdata := tr.tbreg1.mask & tr.tbreg1.read & tr.tbreg1.write;
if (r.slv.hwrite and hclken) = '1' then
tv.tbreg1.mask := hwdata(31 downto 2);
tv.tbreg1.read := hwdata(1);
tv.tbreg1.write := hwdata(0);
end if;
end if;
when "10110" =>
if TRACEN then
hrdata(31 downto 2) := tr.tbreg2.addr;
if (r.slv.hwrite and hclken) = '1' then
tv.tbreg2.addr := hwdata(31 downto 2);
end if;
end if;
when "10111" =>
if TRACEN then
hrdata := tr.tbreg2.mask & tr.tbreg2.read & tr.tbreg2.write;
if (r.slv.hwrite and hclken) = '1' then
tv.tbreg2.mask := hwdata(31 downto 2);
tv.tbreg2.read := hwdata(1);
tv.tbreg2.write := hwdata(0);
end if;
end if;
when others =>
end case;
when "010" => -- AHB tbuf
if TRACEN then
if r.cnt(2 downto 0) = "101" then
if hclken = '1' then v.slv.hready := '1'; else v.slv.hready2 := '1'; end if;
end if;
vabufi.enable := not atact;
slvhaddr := r.slv.haddr(4 downto 2);
case slvhaddr is
when "000" =>
hrdata := tbo.data(127 downto 96);
if (r.slv.hwrite and hclken) = '1' then
vabufi.write(3) := vabufi.enable and v.slv.hready;
end if;
when "001" =>
hrdata := tbo.data(95 downto 64);
if (r.slv.hwrite and hclken) = '1' then
vabufi.write(2) := vabufi.enable and v.slv.hready;
end if;
when "010" =>
hrdata := tbo.data(63 downto 32);
if (r.slv.hwrite and hclken) = '1' then
vabufi.write(1) := vabufi.enable and v.slv.hready;
end if;
when "011" =>
hrdata := tbo.data(31 downto 0);
if (r.slv.hwrite and hclken) = '1' then
vabufi.write(0) := vabufi.enable and v.slv.hready;
end if;
when "100" =>
if bwidth > 32 then
hrdata := tbo.data(159 downto 128);
if (r.slv.hwrite and hclken) = '1' then
vabufi.write(7) := vabufi.enable and v.slv.hready;
end if;
else
hrdata := tbo.data(127 downto 96);
if (r.slv.hwrite and hclken) = '1' then
vabufi.write(3) := vabufi.enable and v.slv.hready;
end if;
end if;
when "101" =>
if bwidth > 32 then
if bwidth > 64 then
hrdata := tbo.data(223 downto 192);
if (r.slv.hwrite and hclken) = '1' then
vabufi.write(6) := vabufi.enable and v.slv.hready;
end if;
else hrdata := zero32; end if;
else
hrdata := tbo.data(95 downto 64);
if (r.slv.hwrite and hclken) = '1' then
vabufi.write(2) := vabufi.enable and v.slv.hready;
end if;
end if;
when "110" =>
if bwidth > 32 then
if bwidth > 64 then
hrdata := tbo.data(191 downto 160);
if (r.slv.hwrite and hclken) = '1' then
vabufi.write(5) := vabufi.enable and v.slv.hready;
end if;
else hrdata := zero32; end if;
else
hrdata := tbo.data(63 downto 32);
if (r.slv.hwrite and hclken) = '1' then
vabufi.write(1) := vabufi.enable and v.slv.hready;
end if;
end if;
when others =>
if bwidth > 32 then
hrdata := zero32;
else
hrdata := tbo.data(31 downto 0);
if (r.slv.hwrite and hclken) = '1' then
vabufi.write(0) := vabufi.enable and v.slv.hready;
end if;
end if;
end case;
else
if hclken = '1' then v.slv.hready := '1'; else v.slv.hready2 := '1'; end if;
end if;
when "011" | "001" => -- IU reg file, IU tbuf
iuacc := '1';
hrdata := dbgi(index).data;
if r.cnt(2 downto 0) = "101" then
if hclken = '1' then v.slv.hready := '1'; else v.slv.hready2 := '1'; end if;
end if;
when "100" => -- IU reg access
iuacc := '1';
hrdata := dbgi(index).data;
if r.cnt(1 downto 0) = "11" then
if hclken = '1' then v.slv.hready := '1'; else v.slv.hready2 := '1'; end if;
end if;
when "111" => -- DSU ASI
if r.cnt(2 downto 1) = "11" then iuacc := '1'; else iuacc := '0'; end if;
if (dbgi(index).crdy = '1') or (r.cnt = "000") then
if hclken = '1' then v.slv.hready := '1'; else v.slv.hready2 := '1'; end if;
end if;
hrdata := dbgi(index).data;
when others =>
if hclken = '1' then v.slv.hready := '1'; else v.slv.hready2 := '1'; end if;
end case;
if (r.slv.hready and hclken and not v.slv.hsel) = '1' then v.slv.hready := '0'; end if;
if (clk2x /= 0) and (r.slv.hready2 and hclken) = '1' then v.slv.hready := '1'; end if;
end if;
if r.slv.hsel = '1' then
if (r.slv.hwrite and hclken) = '1' then v.slv.hwdata := hwdata(31 downto 0); end if;
if (clk2x = 0) or ((r.slv.hready or r.slv.hready2) = '0') then
v.slv.hrdata := hrdata;
end if;
end if;
if ((ahbsi2.hready and ahbsi2.hsel(hindex)) = '1') and (ahbsi2.htrans(1) = '0') then
if (clk2x = 0) or (r.slv.hsel = '0') then
v.slv.hready := '1';
end if;
end if;
if (clk2x /= 0) and (r.slv.hready = '1') then v.slv.hready2 := '0'; end if;
if v.slv.hsel = '0' then v.slv.hready := '1'; end if;
vh.oen := '0';
if (clk2x /= 0) then
if (hclken and r.slv.hsel and (r.slv.hready2 or v.slv.hready)) = '1'
then vh.oen := '1'; end if;
if (r.slv.hsel = '1') and (r.cnt = "111") and (hclken = '0') then iuacc := '0'; end if;
end if;
if (not RESET_ALL) and (rst = '0') then
v.bn := (others => r.dsubre(2)); v.bmsk := (others => '0');
v.dmsk := (others => '0');
v.ss := (others => '0'); v.timer := (others => '0'); v.slv.hsel := '0';
for i in 0 to NCPU-1 loop
v.bw(i) := r.dsubre(2); v.be(i) := r.dsubre(2);
v.bx(i) := r.dsubre(2); v.bz(i) := r.dsubre(2);
v.bs(i) := '0'; v.te(i) := '0';
end loop;
tv.ahbactive := '0'; tv.enable := '0'; tv.tforce := '0'; tv.timeren := '0';
tv.dcnten := '0';
tv.tbreg1.read := '0'; tv.tbreg1.write := '0';
tv.tbreg2.read := '0'; tv.tbreg2.write := '0';
v.slv.hready := '1'; v.halt := (others => '0');
v.act := '0'; v.tstop := '0';
if FILTEN then
tfv.pf := '0'; tfv.af := '0'; tfv.fr := '0'; tfv.fw := '0';
tfv.smask := (others => '0'); tfv.mmask := (others => '0');
tfv.bpfilt := (others => '0');
end if;
if PERFEN then
pv.split := '0'; pv.splmst := (others => '0');
end if;
end if;
rin <= v; trin <= tv; tbi <= vabufi; tfrin <= tfv; prin <= pv;
for i in 0 to NCPU-1 loop
dbgo(i).tenable <= r.te(i);
dbgo(i).dsuen <= r.en(i);
dbgo(i).dbreak <= r.bn(i); -- or (dbgmode and r.bmsk(i));
if conv_integer(r.slv.haddr(PROC_H downto PROC_L)) = i then
dbgo(i).denable <= iuacc;
else
dbgo(i).denable <= '0';
end if;
dbgo(i).step <= r.ss(i);
dbgo(i).berror <= r.be(i);
dbgo(i).bsoft <= r.bs(i);
dbgo(i).bwatch <= r.bw(i);
dbgo(i).btrapa <= r.bx(i);
dbgo(i).btrape <= r.bz(i);
dbgo(i).daddr <= r.slv.haddr(PROC_L-1 downto 2);
dbgo(i).ddata <= r.slv.hwdata(31 downto 0);
dbgo(i).dwrite <= r.slv.hwrite;
dbgo(i).halt <= r.halt(i);
dbgo(i).reset <= r.reset(i);
dbgo(i).timer(tbits-1 downto 0) <= r.timer;
dbgo(i).timer(30 downto tbits) <= (others => '0');
end loop;
ahbso.hconfig <= hconfig;
ahbso.hresp <= HRESP_OKAY;
ahbso.hready <= r.slv.hready;
if (clk2x = 0) then
ahbso.hrdata <= ahbdrivedata(r.slv.hrdata);
else
ahbso.hrdata <= ahbdrivedata(hrdata2x);
end if;
ahbso.hsplit <= (others => '0');
ahbso.hirq <= hirq;
ahbso.hindex <= hindex;
dsuo.active <= r.act;
dsuo.tstop <= tstop;
dsuo.pwd <= cpwd;
if PERFEN then dsuo.astat <= pr.stat; else dsuo.astat <= dsu_astat_none; end if;
rhin <= vh;
end process;
comb2gen0 : if (clk2x /= 0) generate
-- register i/f
gen0 : for i in ahbsi.hsel'range generate
ag0 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.hsel(i), hclken, ahbsi2.hsel(i));
end generate;
gen1 : for i in ahbsi.haddr'range generate
ag1 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.haddr(i), hclken, ahbsi2.haddr(i));
end generate;
ag2 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.hwrite, hclken, ahbsi2.hwrite);
gen3 : for i in ahbsi.htrans'range generate
ag3 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.htrans(i), hclken, ahbsi2.htrans(i));
end generate;
gen4 : for i in ahbsi.hwdata'range generate
ag4 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.hwdata(i), hclken, ahbsi2.hwdata(i));
end generate;
ag5 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.hready, hclken, ahbsi2.hready);
-- not used by register i/f:
ahbsi2.hsize <= (others => '0');
ahbsi2.hburst <= (others => '0');
ahbsi2.hprot <= (others => '0');
ahbsi2.hmaster <= (others => '0');
ahbsi2.hmastlock <= '0';
ahbsi2.hmbsel <= (others => '0');
ahbsi2.hirq <= (others => '0');
ahbsi2.testen <= '0';
ahbsi2.testrst <= '0';
ahbsi2.scanen <= '0';
ahbsi2.testoen <= '0';
-- trace buffer:
gen6 : for i in tahbsi.haddr'range generate
ag6 : clkand generic map (tech => 0, ren => 0) port map (tahbsi.haddr(i), hclken, tahbsi2.haddr(i));
end generate;
ag7 : clkand generic map (tech => 0, ren => 0) port map (tahbsi.hwrite, hclken, tahbsi2.hwrite);
gen8 : for i in tahbsi.htrans'range generate
ag8 : clkand generic map (tech => 0, ren => 0) port map (tahbsi.htrans(i), hclken, tahbsi2.htrans(i));
end generate;
gen9 : for i in tahbsi.hsize'range generate
ag9 : clkand generic map (tech => 0, ren => 0) port map (tahbsi.hsize(i), hclken, tahbsi2.hsize(i));
end generate;
gen10 : for i in tahbsi.hburst'range generate
a10 : clkand generic map (tech => 0, ren => 0) port map (tahbsi.hburst(i), hclken, tahbsi2.hburst(i));
end generate;
gen11 : for i in tahbsi.hwdata'range generate
ag11 : clkand generic map (tech => 0, ren => 0) port map (tahbsi.hwdata(i), hclken, tahbsi2.hwdata(i));
end generate;
ag12 : clkand generic map (tech => 0, ren => 0) port map (tahbsi.hready, hclken, tahbsi2.hready);
gen12 : for i in tahbsi.hmaster'range generate
ag12 : clkand generic map (tech => 0, ren => 0) port map (tahbsi.hmaster(i), hclken, tahbsi2.hmaster(i));
end generate;
ag13 : clkand generic map (tech => 0, ren => 0) port map (tahbsi.hmastlock, hclken, tahbsi2.hmastlock);
gen14 : for i in tahbsi.hsel'range generate
ag14 : clkand generic map (tech => 0, ren => 0) port map (tahbsi.hsel(i), hclken, tahbsi2.hsel(i));
end generate;
-- not used by trace buffer:
tahbsi2.hprot <= (others => '0');
tahbsi2.hmbsel <= (others => '0');
tahbsi2.hirq <= (others => '0');
tahbsi2.testen <= '0';
tahbsi2.testrst <= '0';
tahbsi2.scanen <= '0';
tahbsi2.testoen <= '0';
gen15 : for i in hrdata2x'range generate
ag15 : clkand generic map (tech => 0, ren => 0) port map (r.slv.hrdata(i), rh.oen, hrdata2x(i));
end generate;
reg2 : process(hclk)
begin
if rising_edge(hclk) then rh <= rhin; end if;
end process;
end generate;
comb2gen1 : if (clk2x = 0) generate
ahbsi2 <= ahbsi; rh.irq <= '0'; rh.oen <= '0'; hrdata2x <= (others => '0');
tahbsi2 <= tahbsi;
end generate;
reg : process(cpuclk)
begin
if rising_edge(cpuclk) then
r <= rin;
if RESET_ALL and (rst = '0') then
r <= RRES;
for i in 0 to NCPU-1 loop
r.bn(i) <= r.dsubre(2); r.bw(i) <= r.dsubre(2);
r.be(i) <= r.dsubre(2); r.bx(i) <= r.dsubre(2);
r.bz(i) <= r.dsubre(2);
end loop;
r.dsubre <= rin.dsubre; -- Sync. regs.
r.dsuen <= rin.dsuen;
r.en <= rin.en;
end if;
end if;
end process;
tb0 : if TRACEN generate
treg : process(cpuclk)
begin
if rising_edge(cpuclk) then
tr <= trin;
if RESET_ALL and (rst = '0') then tr <= TRES; end if;
end if;
end process;
tpf : if FILTEN generate
pfreg : process(cpuclk)
begin
if rising_edge(cpuclk) then
tfr <= tfrin;
if RESET_ALL and (rst = '0') then tfr <= TFRES; end if;
end if;
end process;
end generate;
perf : if PERFEN generate
preg : process(cpuclk)
begin
if rising_edge(cpuclk) then
pr <= prin;
if RESET_ALL and (rst = '0') then pr <= PRES; end if;
end if;
end process;
end generate;
mem0 : tbufmem
generic map (tech => tech, tbuf => kbytes, dwidth => bwidth, testen => testen)
port map (cpuclk, tbi, tbo, ahbsi.testin
);
-- pragma translate_off
bootmsg : report_version
generic map ("dsu3_" & tost(hindex) &
": LEON3 Debug support unit + AHB Trace Buffer, " & tost(kbytes) & " kbytes");
-- pragma translate_on
end generate;
notb : if not TRACEN generate
tbo.data <= (others => '0');
tr <= TRES;
-- pragma translate_off
bootmsg : report_version
generic map ("dsu3_" & tost(hindex) &
": LEON3 Debug support unit");
-- pragma translate_on
end generate;
notpf : if not FILTEN generate
tfr.shsel <= (others => '0');
tfr.pf <= '0';
tfr.af <= '0';
tfr.fr <= '0';
tfr.fw <= '0';
tfr.smask <= (others => '0');
tfr.mmask <= (others => '0');
tfr.bpfilt <= (others => '0');
end generate;
noperf : if not PERFEN generate
pr.stat <= dsu_astat_none;
pr.split <= '0';
pr.splmst <= (others => '0');
pr.hready <= '0';
pr.hresp <= (others => '0');
end generate;
end;
| gpl-3.0 | 9b24cd8c8f28c7ea77e2000e0ada0315 | 0.512551 | 3.431271 | false | false | false | false |
hoglet67/CoPro6502 | src/DCM/dcm_32_64.vhd | 1 | 2,187 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity dcm_32_64 is
port (CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic);
end dcm_32_64;
architecture BEHAVIORAL of dcm_32_64 is
signal CLKFX_BUF : std_logic;
signal CLK2X_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKFX_BUFG_INST : BUFG
port map (I => CLKFX_BUF, O => CLK0_OUT);
CLK2X_BUFG_INST : BUFG
port map (I => CLK2X_BUF, O => CLK2X_OUT);
DCM_INST : DCM
generic map(CLK_FEEDBACK => "NONE",
CLKDV_DIVIDE => 4.0, -- 64.00 = 32.000 * 24/12
CLKFX_MULTIPLY => 24,
CLKFX_DIVIDE => 12,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => 31.25,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => true,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => false)
port map (CLKFB => GND_BIT,
CLKIN => CLKIN_IN,
DSSEN => GND_BIT,
PSCLK => GND_BIT,
PSEN => GND_BIT,
PSINCDEC => GND_BIT,
RST => GND_BIT,
CLKDV => open,
CLKFX => CLKFX_BUF,
CLKFX180 => open,
CLK0 => open,
CLK2X => CLK2X_BUF,
CLK2X180 => open,
CLK90 => open,
CLK180 => open,
CLK270 => open,
LOCKED => open,
PSDONE => open,
STATUS => open);
end BEHAVIORAL;
| gpl-3.0 | 594aad2b69cdfea3ad97b406a251f655 | 0.413809 | 4.08785 | false | false | false | false |
techee/geany | tests/ctags/vhdl-local.vhd | 5 | 6,133 | --
-- Taken from rtl/commonlib/types_util.vhd of https://github.com/sergeykhbr/riscv_vhdl
--
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Package for common testbenches implementation.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
package types_util is
function strlen(s: in string) return integer;
function StringToUVector(inStr: string) return std_ulogic_vector;
function StringToSVector(inStr: string) return std_logic_vector;
function UnsignedToSigned(inUnsigned: std_ulogic_vector) return std_logic_vector;
function SignalFromString(inStr: string; ind : integer ) return std_logic;
function SymbolToSVector(inStr: string; idx: integer) return std_logic_vector;
function tost(v:std_logic_vector) return string;
function tost(v:std_logic) return string;
function tost(i : integer) return string;
procedure print(s : string);
end;
package body types_util is
function strlen(s: in string) return integer is
variable n: integer:=0; variable sj: integer:=s'left;
begin
loop
if sj>s'right then exit;
elsif s(sj)=NUL then exit; --sequential if protects sj > length
else sj:=sj+1; n:=n+1;
end if;
end loop;
return n;
end strlen;
function SignalFromString(inStr: string; ind : integer ) return std_logic is
variable temp: std_logic := 'X';
begin
if(inStr(inStr'high-ind)='1') then temp := '1';
elsif(inStr(inStr'high-ind)='0') then temp := '0';
end if;
return temp;
end function SignalFromString;
function StringToUVector(inStr: string) return std_ulogic_vector is
variable temp: std_ulogic_vector(inStr'range) := (others => 'X');
begin
for i in inStr'range loop --
if(inStr(inStr'high-i+1)='1') then temp(i) := '1';
elsif(inStr(inStr'high-i+1)='0') then temp(i) := '0';
end if;
end loop;
return temp(inStr'high downto 1);
end function StringToUVector;
-- conversion function
function StringToSVector(inStr: string) return std_logic_vector is
variable temp: std_logic_vector(inStr'range) := (others => 'X');
begin
for i in inStr'range loop --
if(inStr(inStr'high-i+1)='1') then temp(i) := '1';
elsif(inStr(inStr'high-i+1)='0') then temp(i) := '0';
end if;
end loop;
return temp(inStr'high downto 1);
end function StringToSVector;
function SymbolToSVector(inStr: string; idx: integer) return std_logic_vector is
constant ss: string(1 to inStr'length) := inStr;
variable c : integer;
variable temp: std_logic_vector(7 downto 0) := (others => 'X');
begin
c := character'pos(ss(idx+1));
for i in 0 to 7 loop --
temp(i) := to_unsigned(c,8)(i);
end loop;
return temp;
end function SymbolToSVector;
function UnsignedToSigned(inUnsigned: std_ulogic_vector)
return std_logic_vector is
variable temp: std_logic_vector(inUnsigned'length-1 downto 0) := (others => 'X');
variable i: integer:=0;
begin
while i < inUnsigned'length loop
if(inUnsigned(i)='1') then temp(i) := '1';
elsif(inUnsigned(i)='0') then temp(i) := '0';
end if;
i := i+1;
end loop;
return temp;
end function UnsignedToSigned;
subtype nibble is std_logic_vector(3 downto 0);
function todec(i:integer) return character is
begin
case i is
when 0 => return('0');
when 1 => return('1');
when 2 => return('2');
when 3 => return('3');
when 4 => return('4');
when 5 => return('5');
when 6 => return('6');
when 7 => return('7');
when 8 => return('8');
when 9 => return('9');
when others => return('0');
end case;
end;
function tohex(n:nibble) return character is
begin
case n is
when "0000" => return('0');
when "0001" => return('1');
when "0010" => return('2');
when "0011" => return('3');
when "0100" => return('4');
when "0101" => return('5');
when "0110" => return('6');
when "0111" => return('7');
when "1000" => return('8');
when "1001" => return('9');
when "1010" => return('a');
when "1011" => return('b');
when "1100" => return('c');
when "1101" => return('d');
when "1110" => return('e');
when "1111" => return('f');
when others => return('X');
end case;
end;
function tost(v:std_logic_vector) return string is
constant vlen : natural := v'length; --'
constant slen : natural := (vlen+3)/4;
variable vv : std_logic_vector(0 to slen*4-1) := (others => '0');
variable s : string(1 to slen);
variable nz : boolean := false;
variable index : integer := -1;
variable vector : bit_vector(0 TO 7);
alias reverse_vector : bit_vector
( vector'length DOWNTO 1 )
IS vector ;
begin
vv(slen*4-vlen to slen*4-1) := v;
for i in 0 to slen-1 loop
if (vv(i*4 to i*4+3) = "0000") and nz and (i /= (slen-1)) then
index := i;
else
nz := false;
s(i+1) := tohex(vv(i*4 to i*4+3));
end if;
end loop;
if ((index +2) = slen) then return(s(slen to slen));
else return(string'("0x") & s(index+2 to slen)); end if; --'
end;
function tost(v:std_logic) return string is
begin
if to_x01(v) = '1' then return("1"); else return("0"); end if;
end;
function tost(i : integer) return string is
variable L : line;
variable s, x : string(1 to 128);
variable n, tmp : integer := 0;
begin
tmp := i;
if i < 0 then tmp := -i; end if;
loop
s(128-n) := todec(tmp mod 10);
tmp := tmp / 10;
n := n+1;
if tmp = 0 then exit; end if;
end loop;
x(1 to n) := s(129-n to 128);
if i < 0 then return "-" & x(1 to n); end if;
return(x(1 to n));
end;
procedure print(s : string) is
variable L : line;
begin
L := new string'(s); writeline(output, L);
end;
end;
| gpl-2.0 | 3b02d7e5769e4e947413df36f1acaeaa | 0.591391 | 3.43778 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/unisim/memory_unisim.vhd | 1 | 44,505 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: memory_unisim.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Memory generators for Xilinx RAMs
------------------------------------------------------------------------------
-- parametrisable sync ram generator using UNISIM RAMB16 block rams
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
--pragma translate_off
library unisim;
use unisim.RAMB16_S36_S36;
use unisim.RAMB16_S36;
use unisim.RAMB16_S18;
use unisim.RAMB16_S9;
use unisim.RAMB16_S4;
use unisim.RAMB16_S2;
use unisim.RAMB16_S1;
--pragma translate_on
entity unisim_syncram is
generic ( abits : integer := 9; dbits : integer := 32);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (dbits -1 downto 0);
dataout : out std_logic_vector (dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end;
architecture behav of unisim_syncram is
component RAMB16_S36_S36
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
DOA : out std_logic_vector (31 downto 0);
DOB : out std_logic_vector (31 downto 0);
DOPA : out std_logic_vector (3 downto 0);
DOPB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (8 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (31 downto 0);
DIB : in std_logic_vector (31 downto 0);
DIPA : in std_logic_vector (3 downto 0);
DIPB : in std_logic_vector (3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic);
end component;
component RAMB16_S1
port (
DO : out std_logic_vector (0 downto 0);
ADDR : in std_logic_vector (13 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (0 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S2
port (
DO : out std_logic_vector (1 downto 0);
ADDR : in std_logic_vector (12 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (1 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S4
port (
DO : out std_logic_vector (3 downto 0);
ADDR : in std_logic_vector (11 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (3 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S9
port (
DO : out std_logic_vector (7 downto 0);
DOP : out std_logic_vector (0 downto 0);
ADDR : in std_logic_vector (10 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (7 downto 0);
DIP : in std_logic_vector (0 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S18
port (
DO : out std_logic_vector (15 downto 0);
DOP : out std_logic_vector (1 downto 0);
ADDR : in std_logic_vector (9 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (15 downto 0);
DIP : in std_logic_vector (1 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S36
port (
DO : out std_logic_vector (31 downto 0);
DOP : out std_logic_vector (3 downto 0);
ADDR : in std_logic_vector (8 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (31 downto 0);
DIP : in std_logic_vector (3 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component generic_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
write : in std_ulogic);
end component;
signal gnd : std_ulogic;
signal do, di : std_logic_vector(dbits+72 downto 0);
signal xa, ya : std_logic_vector(19 downto 0);
begin
gnd <= '0'; dataout <= do(dbits-1 downto 0); di(dbits-1 downto 0) <= datain;
di(dbits+72 downto dbits) <= (others => '0'); xa(abits-1 downto 0) <= address;
xa(19 downto abits) <= (others => '0'); ya(abits-1 downto 0) <= address;
ya(19 downto abits) <= (others => '1');
a0 : if (abits <= 5) and (GRLIB_CONFIG_ARRAY(grlib_techmap_strict_ram) = 0) generate
r0 : generic_syncram generic map (abits, dbits)
port map (clk, address, datain, do(dbits-1 downto 0), write);
do(dbits+72 downto dbits) <= (others => '0');
end generate;
a8 : if ((abits > 5 or GRLIB_CONFIG_ARRAY(grlib_techmap_strict_ram) /= 0) and
(abits <= 8)) generate
x : for i in 0 to ((dbits-1)/72) generate
r0 : RAMB16_S36_S36
generic map (SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
do(i*72+36+31 downto i*72+36), do(i*72+31 downto i*72),
do(i*72+36+32+3 downto i*72+36+32), do(i*72+32+3 downto i*72+32),
xa(8 downto 0), ya(8 downto 0), clk, clk,
di(i*72+36+31 downto i*72+36), di(i*72+31 downto i*72),
di(i*72+36+32+3 downto i*72+36+32), di(i*72+32+3 downto i*72+32),
enable, enable, gnd, gnd, write, write);
end generate;
do(dbits+72 downto 72*(((dbits-1)/72)+1)) <= (others => '0');
end generate;
a9 : if (abits = 9) generate
x : for i in 0 to ((dbits-1)/36) generate
r : RAMB16_S36 port map ( do(((i+1)*36)-5 downto i*36),
do(((i+1)*36)-1 downto i*36+32), xa(8 downto 0), clk,
di(((i+1)*36)-5 downto i*36), di(((i+1)*36)-1 downto i*36+32),
enable, gnd, write);
end generate;
do(dbits+72 downto 36*(((dbits-1)/36)+1)) <= (others => '0');
end generate;
a10 : if (abits = 10) generate
x : for i in 0 to ((dbits-1)/18) generate
r : RAMB16_S18 port map ( do(((i+1)*18)-3 downto i*18),
do(((i+1)*18)-1 downto i*18+16), xa(9 downto 0), clk,
di(((i+1)*18)-3 downto i*18), di(((i+1)*18)-1 downto i*18+16),
enable, gnd, write);
end generate;
do(dbits+72 downto 18*(((dbits-1)/18)+1)) <= (others => '0');
end generate;
a11 : if abits = 11 generate
x : for i in 0 to ((dbits-1)/9) generate
r : RAMB16_S9 port map ( do(((i+1)*9)-2 downto i*9),
do(((i+1)*9)-1 downto i*9+8), xa(10 downto 0), clk,
di(((i+1)*9)-2 downto i*9), di(((i+1)*9)-1 downto i*9+8),
enable, gnd, write);
end generate;
do(dbits+72 downto 9*(((dbits-1)/9)+1)) <= (others => '0');
end generate;
a12 : if abits = 12 generate
x : for i in 0 to ((dbits-1)/4) generate
r : RAMB16_S4 port map ( do(((i+1)*4)-1 downto i*4), xa(11 downto 0),
clk, di(((i+1)*4)-1 downto i*4), enable, gnd, write);
end generate;
do(dbits+72 downto 4*(((dbits-1)/4)+1)) <= (others => '0');
end generate;
a13 : if abits = 13 generate
x : for i in 0 to ((dbits-1)/2) generate
r : RAMB16_S2 port map ( do(((i+1)*2)-1 downto i*2), xa(12 downto 0),
clk, di(((i+1)*2)-1 downto i*2), enable, gnd, write);
end generate;
do(dbits+72 downto 2*(((dbits-1)/2)+1)) <= (others => '0');
end generate;
a14 : if abits = 14 generate
x : for i in 0 to (dbits-1) generate
r : RAMB16_S1 port map ( do((i+1)-1 downto i), xa(13 downto 0),
clk, di((i+1)-1 downto i), enable, gnd, write);
end generate;
do(dbits+72 downto dbits) <= (others => '0');
end generate;
a15 : if abits > 14 generate
x: generic_syncram generic map (abits, dbits)
port map (clk, address, datain, do(dbits-1 downto 0), write);
do(dbits+72 downto dbits) <= (others => '0');
end generate;
-- pragma translate_off
-- a_to_high : if abits > 14 generate
-- x : process
-- begin
-- assert false
-- report "Address depth larger than 14 not supported for unisim_syncram"
-- severity failure;
-- wait;
-- end process;
-- end generate;
-- pragma translate_on
end;
LIBRARY ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.conv_integer;
--pragma translate_off
library unisim;
use unisim.RAMB16_S36_S36;
use unisim.RAMB16_S18_S18;
use unisim.RAMB16_S9_S9;
use unisim.RAMB16_S4_S4;
use unisim.RAMB16_S2_S2;
use unisim.RAMB16_S1_S1;
--pragma translate_on
entity unisim_syncram_dp is
generic (
abits : integer := 4; dbits : integer := 32
);
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic);
end;
architecture behav of unisim_syncram_dp is
component RAMB16_S4_S4
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (11 downto 0);
ADDRB : in std_logic_vector (11 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
component RAMB16_S1_S1
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (0 downto 0);
ADDRA : in std_logic_vector (13 downto 0);
ADDRB : in std_logic_vector (13 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (0 downto 0);
DIB : in std_logic_vector (0 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
component RAMB16_S2_S2
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0);
ADDRA : in std_logic_vector (12 downto 0);
ADDRB : in std_logic_vector (12 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
component RAMB16_S9_S9
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0);
DOPA : out std_logic_vector (0 downto 0);
DOPB : out std_logic_vector (0 downto 0);
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
DIPA : in std_logic_vector (0 downto 0);
DIPB : in std_logic_vector (0 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
component RAMB16_S18_S18
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
DOA : out std_logic_vector (15 downto 0);
DOB : out std_logic_vector (15 downto 0);
DOPA : out std_logic_vector (1 downto 0);
DOPB : out std_logic_vector (1 downto 0);
ADDRA : in std_logic_vector (9 downto 0);
ADDRB : in std_logic_vector (9 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (15 downto 0);
DIB : in std_logic_vector (15 downto 0);
DIPA : in std_logic_vector (1 downto 0);
DIPB : in std_logic_vector (1 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic);
end component;
component RAMB16_S36_S36
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
DOA : out std_logic_vector (31 downto 0);
DOB : out std_logic_vector (31 downto 0);
DOPA : out std_logic_vector (3 downto 0);
DOPB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (8 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (31 downto 0);
DIB : in std_logic_vector (31 downto 0);
DIPA : in std_logic_vector (3 downto 0);
DIPB : in std_logic_vector (3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic);
end component;
signal gnd, vcc : std_ulogic;
signal do1, do2, di1, di2 : std_logic_vector(dbits+36 downto 0);
signal addr1, addr2 : std_logic_vector(19 downto 0);
subtype qword is std_logic_vector(dbits+36 downto 0);
type qqtype is array (0 to 3) of qword;
signal qq1 : qqtype;
signal qq2 : qqtype;
signal enable1_t, write1_t : std_logic_vector(3 downto 0);
signal enable2_t, write2_t : std_logic_vector(3 downto 0);
signal ra1, ra2 : std_logic_vector(15 downto 14);
begin
gnd <= '0'; vcc <= '1';
dataout1 <= do1(dbits-1 downto 0); dataout2 <= do2(dbits-1 downto 0);
di1(dbits-1 downto 0) <= datain1; di1(dbits+36 downto dbits) <= (others => '0');
di2(dbits-1 downto 0) <= datain2; di2(dbits+36 downto dbits) <= (others => '0');
addr1(abits-1 downto 0) <= address1; addr1(19 downto abits) <= (others => '0');
addr2(abits-1 downto 0) <= address2; addr2(19 downto abits) <= (others => '0');
a9 : if abits <= 9 generate
x : for i in 0 to ((dbits-1)/36) generate
r0 : RAMB16_S36_S36
generic map(SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
do1(((i+1)*36)-5 downto i*36), do2(((i+1)*36)-5 downto i*36),
do1(((i+1)*36)-1 downto i*36+32), do2(((i+1)*36)-1 downto i*36+32),
addr1(8 downto 0), addr2(8 downto 0), clk1, clk2,
di1(((i+1)*36)-5 downto i*36), di2(((i+1)*36)-5 downto i*36),
di1(((i+1)*36)-1 downto i*36+32), di2(((i+1)*36)-1 downto i*36+32),
enable1, enable2, gnd, gnd, write1, write2);
-- vcc, vcc, gnd, gnd, write1, write2);
end generate;
do1(dbits+36 downto 36*(((dbits-1)/36)+1)) <= (others => '0');
do2(dbits+36 downto 36*(((dbits-1)/36)+1)) <= (others => '0');
end generate;
a10 : if abits = 10 generate
x : for i in 0 to ((dbits-1)/18) generate
r0 : RAMB16_S18_S18
generic map(SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
do1(((i+1)*18)-3 downto i*18), do2(((i+1)*18)-3 downto i*18),
do1(((i+1)*18)-1 downto i*18+16), do2(((i+1)*18)-1 downto i*18+16),
addr1(9 downto 0), addr2(9 downto 0), clk1, clk2,
di1(((i+1)*18)-3 downto i*18), di2(((i+1)*18)-3 downto i*18),
di1(((i+1)*18)-1 downto i*18+16), di2(((i+1)*18)-1 downto i*18+16),
-- vcc, vcc, gnd, gnd, write1, write2);
enable1, enable2, gnd, gnd, write1, write2);
end generate;
do1(dbits+36 downto 18*(((dbits-1)/18)+1)) <= (others => '0');
do2(dbits+36 downto 18*(((dbits-1)/18)+1)) <= (others => '0');
end generate;
a11 : if abits = 11 generate
x : for i in 0 to ((dbits-1)/9) generate
r0 : RAMB16_S9_S9
generic map(SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
do1(((i+1)*9)-2 downto i*9), do2(((i+1)*9)-2 downto i*9),
do1(((i+1)*9)-1 downto i*9+8), do2(((i+1)*9)-1 downto i*9+8),
addr1(10 downto 0), addr2(10 downto 0), clk1, clk2,
di1(((i+1)*9)-2 downto i*9), di2(((i+1)*9)-2 downto i*9),
di1(((i+1)*9)-1 downto i*9+8), di2(((i+1)*9)-1 downto i*9+8),
-- vcc, vcc, gnd, gnd, write1, write2);
enable1, enable2, gnd, gnd, write1, write2);
end generate;
do1(dbits+36 downto 9*(((dbits-1)/9)+1)) <= (others => '0');
do2(dbits+36 downto 9*(((dbits-1)/9)+1)) <= (others => '0');
end generate;
a12 : if abits = 12 generate
x : for i in 0 to ((dbits-1)/4) generate
r0 : RAMB16_S4_S4
generic map(SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
do1(((i+1)*4)-1 downto i*4), do2(((i+1)*4)-1 downto i*4),
addr1(11 downto 0), addr2(11 downto 0), clk1, clk2,
di1(((i+1)*4)-1 downto i*4), di2(((i+1)*4)-1 downto i*4),
-- vcc, vcc, gnd, gnd, write1, write2);
enable1, enable2, gnd, gnd, write1, write2);
end generate;
do1(dbits+36 downto 4*(((dbits-1)/4)+1)) <= (others => '0');
do2(dbits+36 downto 4*(((dbits-1)/4)+1)) <= (others => '0');
end generate;
a13 : if abits = 13 generate
x : for i in 0 to ((dbits-1)/2) generate
r0 : RAMB16_S2_S2
generic map(SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
do1(((i+1)*2)-1 downto i*2), do2(((i+1)*2)-1 downto i*2),
addr1(12 downto 0), addr2(12 downto 0), clk1, clk2,
di1(((i+1)*2)-1 downto i*2), di2(((i+1)*2)-1 downto i*2),
-- vcc, vcc, gnd, gnd, write1, write2);
enable1, enable2, gnd, gnd, write1, write2);
end generate;
do1(dbits+36 downto 2*(((dbits-1)/2)+1)) <= (others => '0');
do2(dbits+36 downto 2*(((dbits-1)/2)+1)) <= (others => '0');
end generate;
a14 : if abits = 14 generate
x : for i in 0 to ((dbits-1)/1) generate
r0 : RAMB16_S1_S1
generic map(SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
do1(((i+1)*1)-1 downto i*1), do2(((i+1)*1)-1 downto i*1),
addr1(13 downto 0), addr2(13 downto 0), clk1, clk2,
di1(((i+1)*1)-1 downto i*1), di2(((i+1)*1)-1 downto i*1),
-- vcc, vcc, gnd, gnd, write1, write2);
enable1, enable2, gnd, gnd, write1, write2);
end generate;
do1(dbits+36 downto dbits) <= (others => '0');
do2(dbits+36 downto dbits) <= (others => '0');
end generate;
a15a16 : if abits >= 15 and abits <= 16 generate
y : for j in 0 to (2**(abits-14))-1 generate
enable1_t(j) <= '1' when ((enable1 = '1') and (conv_integer(addr1(15 downto 14)) = j)) else '0';
write1_t(j) <= '1' when ((write1 = '1') and (conv_integer(addr1(15 downto 14)) = j)) else '0';
enable2_t(j) <= '1' when ((enable2 = '1') and (conv_integer(addr2(15 downto 14)) = j)) else '0';
write2_t(j) <= '1' when ((write2 = '1') and (conv_integer(addr2(15 downto 14)) = j)) else '0';
x : for i in 0 to ((dbits-1)/1) generate
r0 : RAMB16_S1_S1
generic map(SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
qq1(j)(((i+1)*1)-1 downto i*1), qq2(j)(((i+1)*1)-1 downto i*1),
addr1(13 downto 0), addr2(13 downto 0), clk1, clk2,
di1(((i+1)*1)-1 downto i*1), di2(((i+1)*1)-1 downto i*1),
enable1_t(j), enable2_t(j), gnd, gnd, write1_t(j), write2_t(j));
end generate;
end generate;
do1(dbits-1 downto 0) <= qq1(conv_integer(ra1(15 downto 14)))(dbits-1 downto 0);
do2(dbits-1 downto 0) <= qq2(conv_integer(ra2(15 downto 14)))(dbits-1 downto 0);
regs1 : process(clk1)
begin
if rising_edge(clk1) then
ra1(15 downto 14) <= addr1(15 downto 14);
end if;
end process;
regs2 : process(clk2)
begin
if rising_edge(clk2) then
ra2(15 downto 14) <= addr2(15 downto 14);
end if;
end process;
do1(dbits+36 downto dbits) <= (others => '0');
do2(dbits+36 downto dbits) <= (others => '0');
end generate;
-- pragma translate_off
a_to_high : if abits > 16 generate
x : process
begin
assert false
report "Address depth larger than 16 not supported for unisim_syncram_dp"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
entity unisim_syncram_2p is
generic (abits : integer := 6; dbits : integer := 8; sepclk : integer := 0;
wrfst : integer := 0);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0));
end;
architecture behav of unisim_syncram_2p is
component unisim_syncram_dp
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end component;
component generic_syncram_2p
generic (abits : integer := 8; dbits : integer := 32; sepclk : integer := 0);
port (
rclk : in std_ulogic;
wclk : in std_ulogic;
rdaddress: in std_logic_vector (abits -1 downto 0);
wraddress: in std_logic_vector (abits -1 downto 0);
data: in std_logic_vector (dbits -1 downto 0);
wren : in std_ulogic;
q: out std_logic_vector (dbits -1 downto 0)
);
end component;
signal write2, renable2 : std_ulogic;
signal datain2 : std_logic_vector((dbits-1) downto 0);
begin
-- nowf: if wrfst = 0 generate
write2 <= '0'; renable2 <= renable; datain2 <= (others => '0');
-- end generate;
-- wf : if wrfst = 1 generate
-- write2 <= '0' when (waddress /= raddress) else write;
-- renable2 <= renable or write2; datain2 <= datain;
-- end generate;
a0 : if abits <= 5 and GRLIB_CONFIG_ARRAY(grlib_techmap_strict_ram) = 0 generate
x0 : generic_syncram_2p generic map (abits, dbits, sepclk)
port map (rclk, wclk, raddress, waddress, datain, write, dataout);
end generate;
a6 : if abits > 5 or GRLIB_CONFIG_ARRAY(grlib_techmap_strict_ram) /= 0 generate
x0 : unisim_syncram_dp generic map (abits, dbits)
port map (wclk, waddress, datain, open, write, write,
rclk, raddress, datain2, dataout, renable2, write2);
end generate;
end;
-- parametrisable sync ram generator using unisim block rams
library ieee;
use ieee.std_logic_1164.all;
--pragma translate_off
library unisim;
use unisim.RAMB16_S36_S36;
--pragma translate_on
entity unisim_syncram64 is
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (63 downto 0);
dataout : out std_logic_vector (63 downto 0);
enable : in std_logic_vector (1 downto 0);
write : in std_logic_vector (1 downto 0)
);
end;
architecture behav of unisim_syncram64 is
component unisim_syncram
generic ( abits : integer := 9; dbits : integer := 32);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (dbits -1 downto 0);
dataout : out std_logic_vector (dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end component;
component RAMB16_S36_S36
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
DOA : out std_logic_vector (31 downto 0);
DOB : out std_logic_vector (31 downto 0);
DOPA : out std_logic_vector (3 downto 0);
DOPB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (8 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (31 downto 0);
DIB : in std_logic_vector (31 downto 0);
DIPA : in std_logic_vector (3 downto 0);
DIPB : in std_logic_vector (3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic);
end component;
signal gnd : std_logic_vector(3 downto 0);
signal xa, ya : std_logic_vector(19 downto 0);
begin
gnd <= "0000";
xa(abits-1 downto 0) <= address; xa(19 downto abits) <= (others => '0');
ya(abits-1 downto 0) <= address; ya(19 downto abits) <= (others => '1');
a8 : if abits <= 8 generate
r0 : RAMB16_S36_S36
generic map(SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
dataout(63 downto 32), dataout(31 downto 0), open, open,
xa(8 downto 0), ya(8 downto 0), clk, clk,
datain(63 downto 32), datain(31 downto 0), gnd, gnd,
enable(1), enable(0), gnd(0), gnd(0), write(1), write(0));
end generate;
a9 : if abits > 8 generate
x1 : unisim_syncram generic map ( abits, 32)
port map (clk, address, datain(63 downto 32), dataout(63 downto 32),
enable(1), write(1));
x2 : unisim_syncram generic map ( abits, 32)
port map (clk, address, datain(31 downto 0), dataout(31 downto 0),
enable(0), write(0));
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
entity unisim_syncram128 is
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (127 downto 0);
dataout : out std_logic_vector (127 downto 0);
enable : in std_logic_vector (3 downto 0);
write : in std_logic_vector (3 downto 0)
);
end;
architecture behav of unisim_syncram128 is
component unisim_syncram64 is
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (63 downto 0);
dataout : out std_logic_vector (63 downto 0);
enable : in std_logic_vector (1 downto 0);
write : in std_logic_vector (1 downto 0)
);
end component;
begin
x0 : unisim_syncram64 generic map (abits)
port map (clk, address, datain(127 downto 64), dataout(127 downto 64),
enable(3 downto 2), write(3 downto 2));
x1 : unisim_syncram64 generic map (abits)
port map (clk, address, datain(63 downto 0), dataout(63 downto 0),
enable(1 downto 0), write(1 downto 0));
end;
library ieee;
use ieee.std_logic_1164.all;
--pragma translate_off
library unisim;
use unisim.RAMB16_S36_S36;
--pragma translate_on
entity unisim_syncram128bw is
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (127 downto 0);
dataout : out std_logic_vector (127 downto 0);
enable : in std_logic_vector (15 downto 0);
write : in std_logic_vector (15 downto 0)
);
end;
architecture behav of unisim_syncram128bw is
component unisim_syncram
generic ( abits : integer := 9; dbits : integer := 32);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (dbits -1 downto 0);
dataout : out std_logic_vector (dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end component;
component RAMB16_S9_S9
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0);
DOPA : out std_logic_vector (0 downto 0);
DOPB : out std_logic_vector (0 downto 0);
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
DIPA : in std_logic_vector (0 downto 0);
DIPB : in std_logic_vector (0 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
signal gnd : std_logic_vector(3 downto 0);
signal xa, ya : std_logic_vector(19 downto 0);
begin
gnd <= "0000";
xa(abits-1 downto 0) <= address; xa(19 downto abits) <= (others => '0');
ya(abits-1 downto 0) <= address; ya(19 downto abits) <= (others => '1');
a11 : if abits <= 10 generate
x0 : for i in 0 to 7 generate
r0 : RAMB16_S9_S9
generic map(SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
dataout(i*8+7+64 downto i*8+64), dataout(i*8+7 downto i*8), open, open,
xa(10 downto 0), ya(10 downto 0), clk, clk,
datain(i*8+7+64 downto i*8+64), datain(i*8+7 downto i*8), gnd(0 downto 0), gnd(0 downto 0),
enable(i+8), enable(i), gnd(0), gnd(0), write(i+8), write(i));
end generate;
end generate;
a12 : if abits > 10 generate
x0 : for i in 0 to 15 generate
x2 : unisim_syncram generic map ( abits, 8)
port map (clk, address, datain(i*8+7 downto i*8),
dataout(i*8+7 downto i*8), enable(i), write(i));
end generate;
end generate;
end;
-------------------------
-- unisim_syncram with byte enable
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.orv;
use grlib.config_types.all;
use grlib.config.all;
--pragma translate_off
library unisim;
use unisim.RAMB36;
use unisim.RAMB18;
use unisim.RAMB18SDP;
--pragma translate_on
entity unisim_syncram_be is
generic ( abits : integer := 9; dbits : integer := 32; tech : integer := 0);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (dbits -1 downto 0);
dataout : out std_logic_vector (dbits -1 downto 0);
enable : in std_logic_vector (dbits/8-1 downto 0);
write : in std_logic_vector(dbits/8-1 downto 0)
);
end;
architecture behav of unisim_syncram_be is
-- Virtex5 primitives --
component RAMB36
generic (
READ_WIDTH_A : integer := 0;
READ_WIDTH_B : integer := 0;
SIM_COLLISION_CHECK : string := "ALL";
WRITE_WIDTH_A : integer := 0;
WRITE_WIDTH_B : integer := 0
);
port (
CASCADEOUTLATA : out std_ulogic;
CASCADEOUTLATB : out std_ulogic;
CASCADEOUTREGA : out std_ulogic;
CASCADEOUTREGB : out std_ulogic;
DOA : out std_logic_vector(31 downto 0);
DOB : out std_logic_vector(31 downto 0);
DOPA : out std_logic_vector(3 downto 0);
DOPB : out std_logic_vector(3 downto 0);
ADDRA : in std_logic_vector(15 downto 0);
ADDRB : in std_logic_vector(15 downto 0);
CASCADEINLATA : in std_ulogic;
CASCADEINLATB : in std_ulogic;
CASCADEINREGA : in std_ulogic;
CASCADEINREGB : in std_ulogic;
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector(31 downto 0);
DIB : in std_logic_vector(31 downto 0);
DIPA : in std_logic_vector(3 downto 0);
DIPB : in std_logic_vector(3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
REGCEA : in std_ulogic;
REGCEB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_logic_vector(3 downto 0);
WEB : in std_logic_vector(3 downto 0)
);
end component;
component RAMB18
generic (
READ_WIDTH_A : integer := 0;
READ_WIDTH_B : integer := 0;
SIM_COLLISION_CHECK : string := "ALL";
WRITE_WIDTH_A : integer := 0;
WRITE_WIDTH_B : integer := 0
);
port (
DOA : out std_logic_vector(15 downto 0);
DOB : out std_logic_vector(15 downto 0);
DOPA : out std_logic_vector(1 downto 0);
DOPB : out std_logic_vector(1 downto 0);
ADDRA : in std_logic_vector(13 downto 0);
ADDRB : in std_logic_vector(13 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector(15 downto 0);
DIB : in std_logic_vector(15 downto 0);
DIPA : in std_logic_vector(1 downto 0);
DIPB : in std_logic_vector(1 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
REGCEA : in std_ulogic;
REGCEB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_logic_vector(1 downto 0);
WEB : in std_logic_vector(1 downto 0)
);
end component;
component RAMB18SDP
generic (
DO_REG : integer := 0;
SIM_COLLISION_CHECK : string := "ALL";
SIM_MODE : string := "SAFE");
port (
DO : out std_logic_vector(31 downto 0);
DOP : out std_logic_vector(3 downto 0);
DI : in std_logic_vector(31 downto 0);
DIP : in std_logic_vector(3 downto 0);
RDADDR : in std_logic_vector(8 downto 0);
RDCLK : in std_ulogic;
RDEN : in std_ulogic;
REGCE : in std_ulogic;
SSR : in std_ulogic;
WE : in std_logic_vector(3 downto 0);
WRADDR : in std_logic_vector(8 downto 0);
WRCLK : in std_ulogic;
WREN : in std_ulogic
);
end component;
-----------------------
component generic_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
write : in std_ulogic);
end component;
signal gnd, xenable : std_ulogic;
signal do, di : std_logic_vector(dbits+32 downto 0);
signal xa : std_logic_vector(19 downto 0);
type xd_type is array (0 to 255) of std_logic_vector(15 downto 0);
signal xdi, xdo : xd_type;
type xd36_type is array (0 to 255) of std_logic_vector(31 downto 0);
signal xdi36, xdo36 : xd36_type;
signal xwen : std_logic;
type xwen_type is array (0 to 255) of std_logic_vector(1 downto 0);
signal xwen18 : xwen_type;
type xwen36_type is array (0 to 255) of std_logic_vector(3 downto 0);
signal xwen36 : xwen36_type;
begin
gnd <= '0';
dataout <= do(dbits-1 downto 0);
di(dbits-1 downto 0) <= datain;
di(dbits+32 downto dbits) <= (others => '0');
a0 : if (abits <= 5) and (GRLIB_CONFIG_ARRAY(grlib_techmap_strict_ram) = 0) generate
x : for i in 0 to ((dbits-1)/8) generate
r : generic_syncram generic map (abits, 8)
port map (clk, address, di(i*8+8-1 downto i*8), do(i*8+8-1 downto i*8), write(i));
end generate;
do(dbits+32 downto 8*(((dbits-1)/8)+1)) <= (others => '0');
end generate;
a8 : if ((abits > 5 or GRLIB_CONFIG_ARRAY(grlib_techmap_strict_ram) /= 0) and
(abits <= 9)) generate
xa(19 downto abits) <= (others => '0');
xa(abits-1 downto 0) <= address;
xenable <= orv(enable);
xwen <= orv(write);
x : for i in 0 to ((dbits-1)/32) generate
r0 : RAMB18SDP
generic map (SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
DO => do(i*32+32-1 downto i*32),
DOP => open,
DI => di(i*32+32-1 downto i*32),
DIP => x"F",
RDADDR => xa(8 downto 0),
WRADDR => xa(8 downto 0),
RDCLK => clk,
WRCLK => clk,
RDEN => xenable,
REGCE => gnd,
SSR => gnd,
WE => write(i*4+4-1 downto i*4),
WREN => xwen);
end generate;
do(dbits+32 downto 32*(((dbits-1)/32)+1)) <= (others => '0');
end generate;
a10 : if (abits = 10) generate
xa(19 downto 14) <= (others => '0');
xa(3 downto 0) <= (others => '0');
xa(13 downto 4) <= address;
xenable <= orv(enable);
x : for i in 0 to ((dbits-1)/16) generate
r : RAMB18 generic map (READ_WIDTH_A => 18, READ_WIDTH_B => 18,
SIM_COLLISION_CHECK => "GENERATE_X_ONLY",
WRITE_WIDTH_A => 18, WRITE_WIDTH_B => 18)
port map(
DOA => open,
DOB => do(i*16+16-1 downto i*16),
DOPA => open,
DOPB => open,
ADDRA => xa(13 downto 0),
ADDRB => xa(13 downto 0),
CLKA => clk,
CLKB => clk,
DIA => di(i*16+16-1 downto i*16),
DIB => x"FFFF",
DIPA => "11",
DIPB => "11",
ENA => xenable,
ENB => xenable,
REGCEA => '0',
REGCEB => '0',
SSRA => '0',
SSRB => '0',
WEA => write(i*2+2-1 downto i*2),
WEB => "00");
end generate;
do(dbits+32 downto 16*(((dbits-1)/16)+1)) <= (others => '0');
end generate;
a11 : if abits = 11 generate
xa(19 downto 14) <= (others => '0');
xa(2 downto 0) <= (others => '0');
xa(13 downto 3) <= address;
xenable <= orv(enable);
x : for i in 0 to ((dbits-1)/8) generate
xwen18(i) <= '0'&write(i);
xdi(i) <= x"00"&di(i*8+8-1 downto i*8);
do(i*8+8-1 downto i*8) <= xdo(i)(7 downto 0);
r : RAMB18 generic map (READ_WIDTH_A => 9, READ_WIDTH_B => 9,
SIM_COLLISION_CHECK => "GENERATE_X_ONLY",
WRITE_WIDTH_A => 9, WRITE_WIDTH_B => 9)
port map(
DOA => open,
DOB => xdo(i),
DOPA => open,
DOPB => open,
ADDRA => xa(13 downto 0),
ADDRB => xa(13 downto 0),
CLKA => clk,
CLKB => clk,
DIA => xdi(i),
DIB => x"FFFF",
DIPA => "11",
DIPB => "11",
ENA => xenable,
ENB => xenable,
REGCEA => '0',
REGCEB => '0',
SSRA => '0',
SSRB => '0',
WEA => xwen18(i),
WEB => "00");
end generate;
do(dbits+32 downto 8*(((dbits-1)/8)+1)) <= (others => '0');
end generate;
a12 : if abits = 12 generate
xa(19 downto 14) <= (others => '0');
xa(1 downto 0) <= (others => '0');
xa(13 downto 2) <= address;
xenable <= orv(enable);
x : for i in 0 to ((dbits-1)/4) generate
xwen18(i) <= '0'&write(i/2);
xdi(i) <= x"000"&di(i*4+4-1 downto i*4);
do(i*4+4-1 downto i*4) <= xdo(i)(3 downto 0);
r : RAMB18 generic map (READ_WIDTH_A => 4, READ_WIDTH_B => 4,
SIM_COLLISION_CHECK => "GENERATE_X_ONLY",
WRITE_WIDTH_A => 4, WRITE_WIDTH_B => 4)
port map(
DOA => open,
DOB => xdo(i),
DOPA => open,
DOPB => open,
ADDRA => xa(13 downto 0),
ADDRB => xa(13 downto 0),
CLKA => clk,
CLKB => clk,
DIA => xdi(i),
DIB => x"FFFF",
DIPA => "11",
DIPB => "11",
ENA => xenable,
ENB => xenable,
REGCEA => '0',
REGCEB => '0',
SSRA => '0',
SSRB => '0',
WEA => xwen18(i),
WEB => "00");
end generate;
do(dbits+32 downto 4*(((dbits-1)/4)+1)) <= (others => '0');
end generate;
a13 : if abits = 13 generate
xa(19 downto 14) <= (others => '0');
xa(0) <= '0';
xa(13 downto 1) <= address;
xenable <= orv(enable);
x : for i in 0 to ((dbits-1)/2) generate
xwen18(i) <= '0'&write(i/4);
xdi(i)(15 downto 2) <= (others=>'0');
xdi(i)(1 downto 0) <= di(i*2+2-1 downto i*2);
do(i*2+2-1 downto i*2) <= xdo(i)(1 downto 0);
r : RAMB18 generic map (READ_WIDTH_A => 2, READ_WIDTH_B => 2,
SIM_COLLISION_CHECK => "GENERATE_X_ONLY",
WRITE_WIDTH_A => 2, WRITE_WIDTH_B => 2)
port map(
DOA => open,
DOB => xdo(i),
DOPA => open,
DOPB => open,
ADDRA => xa(13 downto 0),
ADDRB => xa(13 downto 0),
CLKA => clk,
CLKB => clk,
DIA => xdi(i),
DIB => x"FFFF",
DIPA => "11",
DIPB => "11",
ENA => xenable,
ENB => xenable,
REGCEA => '0',
REGCEB => '0',
SSRA => '0',
SSRB => '0',
WEA => xwen18(i),
WEB => "00");
end generate;
do(dbits+32 downto 2*(((dbits-1)/2)+1)) <= (others => '0');
end generate;
a14 : if abits = 14 generate
xa(19 downto 14) <= (others => '0');
xa(13 downto 0) <= address;
xenable <= orv(enable);
x : for i in 0 to (dbits-1) generate
xwen18(i) <= '0'&write(i/8);
xdi(i)(15 downto 1) <= (others=>'0');
xdi(i)(0) <= di(i);
do(i) <= xdo(i)(0);
r : RAMB18 generic map (READ_WIDTH_A => 1, READ_WIDTH_B => 1,
SIM_COLLISION_CHECK => "GENERATE_X_ONLY",
WRITE_WIDTH_A => 1, WRITE_WIDTH_B => 1)
port map(
DOA => open,
DOB => xdo(i),
DOPA => open,
DOPB => open,
ADDRA => xa(13 downto 0),
ADDRB => xa(13 downto 0),
CLKA => clk,
CLKB => clk,
DIA => xdi(i),
DIB => x"FFFF",
DIPA => "11",
DIPB => "11",
ENA => xenable,
ENB => xenable,
REGCEA => '0',
REGCEB => '0',
SSRA => '0',
SSRB => '0',
WEA => xwen18(i),
WEB => "00");
end generate;
do(dbits+32 downto dbits) <= (others => '0');
end generate;
a15 : if abits = 15 generate
xa(19 downto 15) <= (others => '0');
xa(14 downto 0) <= address;
xenable <= orv(enable);
x : for i in 0 to (dbits-1) generate
xwen36(i) <= "000"&write(i/8);
xdi36(i)(31 downto 1) <= (others=>'0');
xdi36(i)(0) <= di(i);
do(i) <= xdo36(i)(0);
r : RAMB36 generic map(READ_WIDTH_A => 1, READ_WIDTH_B => 1,
SIM_COLLISION_CHECK => "GENERATE_X_ONLY",
WRITE_WIDTH_A => 1, WRITE_WIDTH_B => 1)
port map(
CASCADEOUTLATA => open,
CASCADEOUTLATB => open,
CASCADEOUTREGA => open,
CASCADEOUTREGB => open,
CASCADEINLATA => '0',
CASCADEINLATB => '0',
CASCADEINREGA => '0',
CASCADEINREGB => '0',
DOA => open,
DOB => xdo36(i),
DOPA => open,
DOPB => open,
ADDRA => xa(15 downto 0),
ADDRB => xa(15 downto 0),
CLKA => clk,
CLKB => clk,
DIA => xdi36(i),
DIB => x"FFFFFFFF",
DIPA => "1111",
DIPB => "1111",
ENA => xenable,
ENB => xenable,
REGCEA => '0',
REGCEB => '0',
SSRA => '0',
SSRB => '0',
WEA => xwen36(i),
WEB => "0000");
end generate;
do(dbits+32 downto dbits) <= (others => '0');
end generate;
a16 : if (abits > 15) generate
x : for i in 0 to ((dbits-1)/8) generate
r : generic_syncram generic map (abits, 8)
port map (clk, address, di(i*8+8-1 downto i*8), do(i*8+8-1 downto i*8), write(i));
end generate;
do(dbits+32 downto 8*(((dbits-1)/8)+1)) <= (others => '0');
end generate;
--pragma translate_off
gen_sram : if abits > 15 generate
x : process
begin
report "Address depth larger than 15 not supported for unisim_syncram_be. It will be implemented using inferred syncram.";
wait;
end process;
end generate;
--pragma translate_on
end;
| gpl-3.0 | 68e2499c4e5bbb3a3a46e7a0f7d84f94 | 0.572835 | 3.178475 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-ztex-ufm-111/ahb2mig_ztex.vhd | 1 | 15,312 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: ahb2mig_ztex
-- File: ahb2mig_ztex.vhd
-- Author: Jiri Gaisler - Aeroflex Gaisler AB
--
-- This is a AHB-2.0 interface for the Xilinx Spartan-6 MIG.
-- One bidir 32-bit port is used for the main AHB bus.
-------------------------------------------------------------------------------
-- Patched for ZTEX: Oleg Belousov <[email protected]>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahb2mig_ztex is
generic(
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#
);
port(
mcb3_dram_dq : inout std_logic_vector(15 downto 0);
mcb3_rzq : inout std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_a : out std_logic_vector(12 downto 0);
mcb3_dram_ba : out std_logic_vector(1 downto 0);
mcb3_dram_cke : out std_logic;
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
calib_done : out std_logic;
test_error : out std_logic;
rst_n_syn : in std_logic;
rst_n_async : in std_logic;
clk_amba : in std_logic;
clk_mem : in std_logic
);
end ;
architecture rtl of ahb2mig_ztex is
component mig_37
generic(
C3_P0_MASK_SIZE : integer := 4;
C3_P0_DATA_PORT_SIZE : integer := 32;
C3_P1_MASK_SIZE : integer := 4;
C3_P1_DATA_PORT_SIZE : integer := 32;
C3_MEMCLK_PERIOD : integer := 5000;
C3_RST_ACT_LOW : integer := 0;
C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
C3_CALIB_SOFT_IP : string := "TRUE";
C3_SIMULATION : string := "FALSE";
DEBUG_EN : integer := 0;
C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
C3_NUM_DQ_PINS : integer := 16;
C3_MEM_ADDR_WIDTH : integer := 13;
C3_MEM_BANKADDR_WIDTH : integer := 2
);
port (
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_cke : out std_logic;
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_dram_udm : out std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_n : in std_logic;
c3_calib_done : out std_logic;
c3_clk0 : out std_logic;
c3_rst0 : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
c3_p0_cmd_clk : in std_logic;
c3_p0_cmd_en : in std_logic;
c3_p0_cmd_instr : in std_logic_vector(2 downto 0);
c3_p0_cmd_bl : in std_logic_vector(5 downto 0);
c3_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p0_cmd_empty : out std_logic;
c3_p0_cmd_full : out std_logic;
c3_p0_wr_clk : in std_logic;
c3_p0_wr_en : in std_logic;
c3_p0_wr_mask : in std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
c3_p0_wr_data : in std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_wr_full : out std_logic;
c3_p0_wr_empty : out std_logic;
c3_p0_wr_count : out std_logic_vector(6 downto 0);
c3_p0_wr_underrun : out std_logic;
c3_p0_wr_error : out std_logic;
c3_p0_rd_clk : in std_logic;
c3_p0_rd_en : in std_logic;
c3_p0_rd_data : out std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_rd_full : out std_logic;
c3_p0_rd_empty : out std_logic;
c3_p0_rd_count : out std_logic_vector(6 downto 0);
c3_p0_rd_overflow : out std_logic;
c3_p0_rd_error : out std_logic
);
end component;
type bstate_type is (idle, start, read1);
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
-- 5 => ahb_iobar(ioaddr, iomask),
others => zero32);
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, 0, 0),
1 => apb_iobar(paddr, pmask));
type reg_type is record
bstate : bstate_type;
cmd_bl : std_logic_vector(5 downto 0);
wr_count : std_logic_vector(6 downto 0);
rd_cnt : std_logic_vector(5 downto 0);
hready : std_logic;
hsel : std_logic;
hwrite : std_logic;
htrans : std_logic_vector(1 downto 0);
hburst : std_logic_vector(2 downto 0);
hsize : std_logic_vector(2 downto 0);
hrdata : std_logic_vector(31 downto 0);
haddr : std_logic_vector(31 downto 0);
hmaster : std_logic_vector(3 downto 0);
end record;
type mcb_type is record
cmd_en : std_logic;
cmd_instr : std_logic_vector(2 downto 0);
cmd_empty : std_logic;
cmd_full : std_logic;
cmd_bl : std_logic_vector(5 downto 0);
cmd_byte_addr : std_logic_vector(29 downto 0);
wr_full : std_logic;
wr_empty : std_logic;
wr_underrun : std_logic;
wr_error : std_logic;
wr_mask : std_logic_vector(3 downto 0);
wr_en : std_logic;
wr_data : std_logic_vector(31 downto 0);
wr_count : std_logic_vector(6 downto 0);
rd_data : std_logic_vector(31 downto 0);
rd_full : std_logic;
rd_empty : std_logic;
rd_count : std_logic_vector(6 downto 0);
rd_overflow : std_logic;
rd_error : std_logic;
rd_en : std_logic;
end record;
signal r, rin : reg_type;
signal i : mcb_type;
begin
comb: process( rst_n_syn, r, ahbsi, i )
variable v : reg_type;
variable wmask : std_logic_vector(3 downto 0);
variable wr_en : std_logic;
variable cmd_en : std_logic;
variable cmd_instr : std_logic_vector(2 downto 0);
variable rd_en : std_logic;
variable cmd_bl : std_logic_vector(5 downto 0);
variable hwdata : std_logic_vector(31 downto 0);
variable readdata : std_logic_vector(31 downto 0);
begin
v := r; wr_en := '0'; cmd_en := '0'; cmd_instr := "000";
rd_en := '0';
if (ahbsi.hready = '1') then
if (ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '1' then
v.hsel := '1'; v.hburst := ahbsi.hburst;
v.hwrite := ahbsi.hwrite; v.hsize := ahbsi.hsize;
v.hmaster := ahbsi.hmaster;
v.hready := '0';
if ahbsi.htrans(0) = '0' then v.haddr := ahbsi.haddr; end if;
else
v.hsel := '0'; v.hready := '1';
end if;
v.htrans := ahbsi.htrans;
end if;
hwdata := ahbsi.hwdata(15 downto 0) & ahbsi.hwdata(31 downto 16);
case r.hsize(1 downto 0) is
when "00" => wmask := not decode(r.haddr(1 downto 0));
case r.haddr(1 downto 0) is
when "00" => wmask := "1101";
when "01" => wmask := "1110";
when "10" => wmask := "0111";
when others => wmask := "1011";
end case;
when "01" => wmask := not decode(r.haddr(1 downto 0));
wmask(3) := wmask(2); wmask(1) := wmask(0);
when others => wmask := "0000";
end case;
i.wr_mask <= wmask;
cmd_bl := r.cmd_bl;
case r.bstate is
when idle =>
if v.hsel = '1' then
v.bstate := start;
v.hready := ahbsi.hwrite and not i.cmd_full and not i.wr_full;
v.haddr := ahbsi.haddr;
end if;
v.cmd_bl := (others => '0');
when start =>
if r.hwrite = '1' then
v.haddr := r.haddr;
if r.hready = '1' then
v.cmd_bl := r.cmd_bl + 1; v.hready := '1'; wr_en := '1';
if (ahbsi.htrans /= "11") then
if v.hsel = '1' then
if (ahbsi.hwrite = '0') or (i.wr_count >= "0000100") then
v.hready := '0';
else v.hready := '1'; end if;
else v.bstate := idle; end if;
v.cmd_bl := (others => '0'); v.haddr := ahbsi.haddr;
cmd_en := '1';
elsif (i.cmd_full = '1') then
v.hready := '0';
elsif (i.wr_count >= "0101111") then
v.hready := '0'; cmd_en := '1';
v.cmd_bl := (others => '0'); v.haddr := ahbsi.haddr;
end if;
else
if (i.cmd_full = '0') and (i.wr_count <= "0001111") then
v.hready := '1';
end if;
end if;
else
if i.cmd_full = '0' then
cmd_en := '1'; cmd_instr(0) := '1';
v.cmd_bl := "000" & not r.haddr(4 downto 2);
cmd_bl := v.cmd_bl;
v.bstate := read1;
end if;
end if;
when read1 =>
v.hready := '0';
if (r.rd_cnt = "000000") then -- flush data from previous line
if (i.rd_empty = '0') or ((r.hready = '1') and (ahbsi.htrans /= "11")) then
v.hrdata(31 downto 0) := i.rd_data(15 downto 0) & i.rd_data(31 downto 16);
v.hready := '1';
if (i.rd_empty = '0') then v.cmd_bl := r.cmd_bl - 1; rd_en := '1'; end if;
if (r.cmd_bl = "000000") or (ahbsi.htrans /= "11") then
if (ahbsi.hsel(hindex) = '1') and (ahbsi.htrans = "10") and (r.hready = '1') then
v.bstate := start; v.hready := ahbsi.hwrite and not i.cmd_full and not i.wr_full;
v.cmd_bl := (others => '0');
else
v.bstate := idle;
end if;
if (i.rd_empty = '1') then v.rd_cnt := r.cmd_bl + 1;
else v.rd_cnt := r.cmd_bl; end if;
end if;
end if;
end if;
when others =>
end case;
readdata := (others => '0');
-- case apbi.paddr(5 downto 2) is
-- when "0000" => readdata(nbits-1 downto 0) := r.din2;
-- when "0001" => readdata(nbits-1 downto 0) := r.dout;
-- when others =>
-- end case;
readdata(20 downto 0) :=
i.rd_error & i.rd_overflow & i.wr_error & i.wr_underrun &
i.cmd_full & i.rd_full & i.rd_empty & i.wr_full & i.wr_empty &
r.rd_cnt & r.cmd_bl;
if (r.rd_cnt /= "000000") and (i.rd_empty = '0') then
rd_en := '1'; v.rd_cnt := r.rd_cnt - 1;
end if;
if rst_n_syn = '0' then
v.rd_cnt := "000000"; v.bstate := idle; v.hready := '1';
end if;
rin <= v;
apbo.prdata <= readdata;
i.rd_en <= rd_en;
i.wr_en <= wr_en;
i.cmd_bl <= cmd_bl;
i.cmd_en <= cmd_en;
i.cmd_instr <= cmd_instr;
i.wr_data <= hwdata;
end process;
i.cmd_byte_addr <= r.haddr(29 downto 2) & "00";
ahbso.hready <= r.hready;
ahbso.hresp <= "00"; --r.hresp;
ahbso.hrdata <= r.hrdata;
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
apbo.pirq <= (others => '0');
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
regs : process(clk_amba)
begin
if rising_edge(clk_amba) then
r <= rin;
end if;
end process;
MCB_inst : entity work.mig_37 generic map(
C3_RST_ACT_LOW => 1,
-- pragma translate_off
C3_SIMULATION => "TRUE",
-- pragma translate_on
C3_MEM_ADDR_ORDER => "BANK_ROW_COLUMN"
)
port map (
mcb3_dram_dq => mcb3_dram_dq,
mcb3_rzq => mcb3_rzq,
mcb3_dram_udqs => mcb3_dram_udqs,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_dm => mcb3_dram_dm,
mcb3_dram_udm => mcb3_dram_udm,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
c3_sys_clk => clk_mem,
c3_sys_rst_n => rst_n_async,
c3_calib_done => calib_done,
c3_clk0 => open,
c3_rst0 => open,
c3_p0_cmd_clk => clk_amba,
c3_p0_cmd_en => i.cmd_en,
c3_p0_cmd_instr => i.cmd_instr,
c3_p0_cmd_bl => i.cmd_bl,
c3_p0_cmd_byte_addr => i.cmd_byte_addr,
c3_p0_cmd_empty => i.cmd_empty,
c3_p0_cmd_full => i.cmd_full,
c3_p0_wr_clk => clk_amba,
c3_p0_wr_en => i.wr_en,
c3_p0_wr_mask => i.wr_mask,
c3_p0_wr_data => i.wr_data,
c3_p0_wr_full => i.wr_full,
c3_p0_wr_empty => i.wr_empty,
c3_p0_wr_count => i.wr_count,
c3_p0_wr_underrun => i.wr_underrun,
c3_p0_wr_error => i.wr_error,
c3_p0_rd_clk => clk_amba,
c3_p0_rd_en => i.rd_en,
c3_p0_rd_data => i.rd_data,
c3_p0_rd_full => i.rd_full,
c3_p0_rd_empty => i.rd_empty,
c3_p0_rd_count => i.rd_count,
c3_p0_rd_overflow => i.rd_overflow,
c3_p0_rd_error => i.rd_error
);
end;
| gpl-3.0 | 7487917484fa8cf59f80824debb87eab | 0.507772 | 3.047164 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/leon3v3/l3stat.vhd | 1 | 19,909 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: l3stat
-- File: l3stat.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Jan Andersson - Aeroflex Gaisler
-- Description: LEON3 statistic counters
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
library gaisler;
use gaisler.leon3.all;
entity l3stat is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ncnt : integer range 1 to 64 := 4;
ncpu : integer := 1;
nmax : integer := 0;
lahben : integer := 0;
dsuen : integer := 0;
nextev : integer range 0 to 16 := 0;
apb2en : integer := 0;
pindex2 : integer := 0;
paddr2 : integer := 0;
pmask2 : integer := 16#fff#;
astaten : integer := 0;
selreq : integer := 0;
clatch : integer := 0;
forcer0 : integer range 0 to 1 := 0
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbsi : in ahb_slv_in_type;
dbgo : in l3_debug_out_vector(0 to NCPU-1);
dsuo : in dsu_out_type := dsu_out_none;
stati : in l3stat_in_type := l3stat_in_none;
apb2i : in apb_slv_in_type := apb_slv_in_none;
apb2o : out apb_slv_out_type;
astat : in amba_stat_type := amba_stat_none
);
end;
architecture rtl of l3stat is
constant REVISION : integer := 1 - forcer0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg (VENDOR_GAISLER, GAISLER_L3STAT, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
constant pconfig2 : apb_config_type := (
0 => ahb_device_reg (VENDOR_GAISLER, GAISLER_L3STAT, 0, REVISION, 0),
1 => apb_iobar(paddr2, pmask2));
constant MAX_CNT : natural := 64 - 32*forcer0; -- Maximum number of counters
constant MADDR : natural := log2(MAX_CNT) + 2;
function op_len return integer is
begin
if selreq /= 0 then return 8; end if;
return 7;
end function op_len;
constant LATCH_CNT : boolean := clatch /= 0;
type cnt_type is record
cpu : std_logic_vector(3 downto 0);
op : std_logic_vector(op_len-1 downto 0);
en : std_logic;
clr : std_logic;
inc : std_logic;
cnt : std_logic_vector(31 downto 0);
suen : std_logic_vector(1 downto 0);
end record;
type mcnt_type is record
el : std_ulogic;
cd : std_ulogic;
max : std_logic_vector(31 downto 0);
end record;
type reg_type is record
hmaster : std_logic_vector(3 downto 0);
active : std_logic;
latcnt : std_logic;
timer : std_logic_vector(31 downto 0);
end record;
constant cnt_none : cnt_type := ("0000", zero32(op_len-1 downto 0),
'0', '0', '0', zero32, "00");
constant mcnt_none : mcnt_type := ('0', '0', zero32);
type cnt_type_vector is array (natural range <>) of cnt_type;
type mcnt_type_vector is array (natural range <>) of mcnt_type;
function calc_inc(
cnt : cnt_type;
dbgox : l3_debug_out_vector(0 to 15);
r : reg_type;
dastat : dsu_astat_type;
ev : std_logic_vector(15 downto 0);
esource: l3stat_src_array;
astat : amba_stat_type;
req : std_logic_vector(15 downto 0);
sel : std_logic_vector(15 downto 0)) return std_logic is
variable wbhold, inc, icnt, fcnt, bpmiss, dsumode : std_logic;
variable istat, dstat : l3_cstat_type;
variable cpu : natural range 0 to 15;
variable inst : std_logic_vector(5 downto 0);
variable su : std_logic;
variable op : std_logic_vector(5 downto 0);
begin
cpu := conv_integer(cnt.cpu); wbhold := dbgox(cpu).wbhold;
istat := dbgox(cpu).istat; dstat := dbgox(cpu).dstat;
icnt := dbgox(cpu).icnt; fcnt := dbgox(cpu).fcnt;
inst := dbgox(cpu).optype; bpmiss := dbgox(cpu).bpmiss;
dsumode := dbgox(cpu).dsumode;
su := dbgox(cpu).su;
inc := '0';
op := cnt.op(5 downto 0);
if selreq = 0 or cnt.op(cnt.op'left) = '0' then
if (nextev = 0 and dsuen = 0 and astaten = 0) or cnt.op(6) = '0' then
case op is
when "000000" => inc := istat.cmiss; -- icache miss
when "000001" => inc := istat.tmiss; -- icache tlb miss
when "000010" => inc := istat.chold; -- icache total hold
when "000011" => inc := istat.mhold; -- icache MMU hold
when "001000" => inc := dstat.cmiss;
when "001001" => inc := dstat.tmiss;
when "001010" => inc := dstat.chold;
when "001011" => inc := dstat.mhold;
when "010000" => inc := wbhold; -- dcache write buffer hold
when "010001" => inc := icnt; -- total number of instructions
when "010010" => inc := icnt and not fcnt; -- integer instructions
when "010011" => inc := fcnt; -- FPU instructions
when "010100" => inc := bpmiss; -- branch prediction miss
when "010101" => inc := not dsumode; -- total cycles
when "010111" => -- AHB utilization per master
if lahben /= 0 then
if (r.active = '1') and (r.hmaster = cnt.cpu) then inc := '1'; end if;
end if;
when "011000" => -- Total AHB utilization
if lahben /= 0 then
if (r.active = '1') then inc := '1'; end if;
end if;
when "100010" => -- integer branches
if inst(5 downto 1) = "00010" then inc := icnt; end if;
when "101000" => -- CALL
if inst(5 downto 4) = "01" then inc := icnt; end if;
when "110000" => -- Normal instructions
if inst(5 downto 4) = "10" then inc := icnt; end if;
when "111000" => -- load & store
if inst(5 downto 4) = "11" then inc := icnt; end if;
when "111001" => -- load
if (inst(5 downto 4) = "11") and ((inst(0) = '0') or inst(1) = '1') then inc := icnt; end if;
when "111010" => -- store
if (inst(5 downto 4) = "11") and (inst(0) = '1') then inc := icnt; end if;
when others => null;
end case;
case cnt.suen is
when "01" => if su = '0' then inc := '0'; end if;
when "10" => if su = '1' then inc := '0'; end if;
when others => null;
end case;
elsif dsuen /= 0 and cnt.op(6 downto 5) = "10" then
case op(4 downto 0) is
when "00000" => inc := dastat.idle;
when "00001" => inc := dastat.busy;
when "00010" => inc := dastat.nseq;
when "00011" => inc := dastat.seq;
when "00100" => inc := dastat.read;
when "00101" => inc := dastat.write;
when "00110" => inc := dastat.hsize(0);
when "00111" => inc := dastat.hsize(1);
when "01000" => inc := dastat.hsize(2);
when "01001" => inc := dastat.hsize(3);
when "01010" => inc := dastat.hsize(4);
when "01011" => inc := dastat.hsize(5);
when "01100" => inc := dastat.ws;
when "01101" => inc := dastat.retry;
when "01110" => inc := dastat.split;
when "01111" => inc := dastat.spdel;
when "10000" => inc := dastat.locked;
when others => null;
end case;
if cnt.suen(1) = '1' and cnt.cpu /= dastat.hmaster then
inc := '0';
end if;
elsif astaten /= 0 and cnt.op(6 downto 4) = "111" then -- 0x70 - 0x7F
case op(3 downto 0) is
when "0000" => inc := astat.idle;
when "0001" => inc := astat.busy;
when "0010" => inc := astat.nseq;
when "0011" => inc := astat.seq;
when "0100" => inc := astat.read;
when "0101" => inc := astat.write;
when "0110" => inc := astat.hsize(0);
when "0111" => inc := astat.hsize(1);
when "1000" => inc := astat.hsize(2);
when "1001" => inc := astat.hsize(3);
when "1010" => inc := astat.hsize(4);
when "1011" => inc := astat.hsize(5);
when "1100" => inc := astat.ws;
when "1101" => inc := astat.retry;
when "1110" => inc := astat.split;
when "1111" => inc := astat.spdel;
when others => null;
end case;
if cnt.suen(1) = '1' and cnt.cpu /= astat.hmaster then
inc := '0';
end if;
elsif nextev /= 0 then -- 0x60 - 0x6F
-- External event 0 to 15
for i in 0 to 15 loop
if i >= nextev then
exit;
end if;
if i = conv_integer(cnt.op(3 downto 0)) then
if cnt.suen(1) = '0' or cnt.cpu = esource(i) then
inc := ev(i);
end if;
end if;
end loop;
end if;
end if;
if selreq /= 0 and cnt.op(cnt.op'left) = '1' then
-- Possible extensions to the below:
-- - add check for when OP(3:0).hbusreq and AHBM.hbusreq is asserted at
-- the same time
-- - also take supervisor/usermode into account
-- - do not only check on bus master but also/instead on MMU context ID
for i in 0 to selreq loop
for j in 0 to selreq loop
if (i = conv_integer(cnt.op(3 downto 0)) and
j = conv_integer(cnt.cpu)) then
inc := req(j) and (sel(i) xor cnt.op(4));
end if;
end loop;
end loop;
end if;
return(inc);
end;
function nmax_right return integer is
begin
if nmax /= 0 then return nmax-1; end if;
return 0;
end function;
function latch_cnt_addr (paddr : std_logic_vector(31 downto 0)) return boolean is
begin
return LATCH_CNT and paddr(MADDR+1) = '1';
end function;
signal rc, rcin : cnt_type_vector(0 to ncnt-1);
signal mrc, mrcin : mcnt_type_vector(0 to nmax_right);
signal r, rin : reg_type;
begin
comb : process(r, rc, mrc, rstn, apbi, dbgo, stati, astat)
variable rdata : std_logic_vector(31 downto 0);
variable rdata2 : std_logic_vector(31 downto 0);
variable rv : cnt_type_vector(0 to MAX_CNT-1);
variable mrv : mcnt_type_vector(0 to MAX_CNT-1);
variable lrc : cnt_type_vector(0 to MAX_CNT-1);
variable lmrc : mcnt_type_vector(0 to MAX_CNT-1);
variable v : reg_type;
variable addr : natural;
variable addr2 : natural;
variable dbgol : l3_debug_out_vector(0 to 15);
begin
for i in 0 to MAX_CNT-1 loop
rv(i) := cnt_none; mrv(i) := mcnt_none;
lrc(i) := cnt_none; lmrc(i) := mcnt_none;
end loop;
rv(0 to ncnt-1) := rc; mrv(0 to nmax_right) := mrc; v := r;
lrc(0 to ncnt-1) := rc; lmrc(0 to nmax_right) := mrc;
addr := conv_integer(apbi.paddr(MADDR-1 downto 2));
rdata := zero32; rdata2 := zero32; v.latcnt := '0'; v.timer := (others => '0');
if LATCH_CNT then
v.latcnt := stati.latcnt;
if r.latcnt = '1' then v.timer := stati.timer; end if;
end if;
for i in 0 to ncpu-1 loop dbgol(i) := dbgo(i); end loop;
for i in ncpu to 15 loop dbgol(i) := l3_dbgo_none; end loop;
for i in 0 to ncnt-1 loop
rv(i).inc := calc_inc(rc(i), dbgol, r, dsuo.astat, stati.event, stati.esource,
astat, stati.req, stati.sel) and rc(i).en;
if nmax = 0 or i >= nmax or mrc(i).cd = '0' then
if rc(i).inc = '1' then rv(i).cnt := rc(i).cnt + 1; end if;
elsif nmax /= 0 and i < nmax then
-- count maximum duration
if (rc(i).en = '1') then
if rc(i).inc = mrc(i).el then
rv(i).cnt := rc(i).cnt + 1;
else
rv(i).cnt := zero32;
end if;
if rc(i).cnt > mrc(i).max then
mrv(i).max := rc(i).cnt;
end if;
end if;
end if;
if LATCH_CNT and r.latcnt = '1' and nmax /= 0 and i < nmax then
if mrc(i).cd = '0' then
mrv(i).max := rv(i).cnt;
if rc(i).clr = '1' then rv(i).cnt := (others => '0'); end if;
end if;
end if;
end loop;
if apb2en /= 0 then -- 2nd APB interface
addr2 := conv_integer(apb2i.paddr(MADDR-1 downto 2));
if (apb2i.psel(pindex2) and apb2i.penable) = '1' and (not latch_cnt_addr(apb2i.paddr)) then
if apb2i.pwrite = '0' then
if apb2i.paddr(MADDR) = '0' then
rdata2 := lrc(addr2).cnt;
if nmax = 0 or lmrc(addr2).cd = '0' then
rdata2 := lrc(addr2).cnt;
else
rdata2 := lmrc(addr2).max;
end if;
if rv(addr2).clr = '1' then
rv(addr2).cnt := zero32;
if nmax /= 0 and nmax > addr2 then mrv(addr2).max := zero32; end if;
end if;
else
if REVISION = 0 then
rdata2(31 downto 28) := conv_std_logic_vector(ncpu-1, 4);
rdata2(27 downto 23) := conv_std_logic_vector(ncnt-1, 5);
else
rdata2(31 downto 23) := conv_std_logic_vector(ncnt-1, 9);
end if;
rdata2(22) := conv_std_logic(nmax > addr2);
rdata2(21) := conv_std_logic(lahben /= 0);
rdata2(20) := conv_std_logic(dsuen /= 0);
rdata2(19) := conv_std_logic(nextev /= 0);
rdata2(18) := conv_std_logic(astaten /= 0);
if nmax /= 0 and nmax > addr2 then
rdata2(17) := lmrc(addr2).el;
rdata2(16) := lmrc(addr2).cd;
end if;
rdata2(15 downto 14) := lrc(addr2).suen;
rdata2(13) := lrc(addr2).clr;
rdata2(12) := lrc(addr2).en;
rdata2(11 downto 4) := (others => '0');
rdata2(4+op_len-1 downto 4) := lrc(addr2).op;
rdata2(3 downto 0) := lrc(addr2).cpu;
end if;
else
if apb2i.paddr(MADDR) = '0' then
rv(addr2).cnt := apb2i.pwdata;
if nmax /= 0 and nmax > addr2 then mrv(addr2).max := apbi.pwdata; end if;
else
if nmax /= 0 and nmax > addr2 then
mrv(addr2).el := apb2i.pwdata(17);
mrv(addr2).cd := apb2i.pwdata(16);
end if;
rv(addr2).suen := apb2i.pwdata(15 downto 14);
rv(addr2).clr := apb2i.pwdata(13);
rv(addr2).en := apb2i.pwdata(12);
rv(addr2).op := apb2i.pwdata(4+op_len-1 downto 4);
rv(addr2).cpu := apb2i.pwdata(3 downto 0);
end if;
end if;
end if;
if latch_cnt_addr(apb2i.paddr) and (apb2i.psel(pindex2) and apb2i.penable) = '1' then
if apb2i.paddr(7) = '0' then
rdata2 := lmrc(addr2).max;
else
rdata := r.timer;
end if;
v.latcnt := v.latcnt or apb2i.pwrite;
end if;
else
addr2 := 0;
end if;
if (apbi.psel(pindex) and apbi.penable) = '1' and (not latch_cnt_addr(apbi.paddr)) then
if apbi.pwrite = '0' then
if apbi.paddr(MADDR) = '0' then
if nmax = 0 or lmrc(addr).cd = '0' then
rdata := lrc(addr).cnt;
else
rdata := lmrc(addr).max;
end if;
if rv(addr).clr = '1' then
rv(addr).cnt := zero32;
if nmax /= 0 and nmax > addr then mrv(addr).max := zero32; end if;
end if;
else
if REVISION = 0 then
rdata(31 downto 28) := conv_std_logic_vector(ncpu-1, 4);
rdata(27 downto 23) := conv_std_logic_vector(ncnt-1, 5);
else
rdata(31 downto 23) := conv_std_logic_vector(ncnt-1, 9);
end if;
rdata(22) := conv_std_logic(nmax > addr);
rdata(21) := conv_std_logic(lahben /= 0);
rdata(20) := conv_std_logic(dsuen /= 0);
rdata(19) := conv_std_logic(nextev /= 0);
rdata(18) := conv_std_logic(astaten /= 0);
if nmax /= 0 and nmax > addr then
rdata(17) := lmrc(addr).el;
rdata(16) := lmrc(addr).cd;
end if;
rdata(15 downto 14) := lrc(addr).suen;
rdata(13) := lrc(addr).clr;
rdata(12) := lrc(addr).en;
rdata(11 downto 4) := (others => '0');
rdata(4+op_len-1 downto 4) := lrc(addr).op;
rdata(3 downto 0) := lrc(addr).cpu;
end if;
else
if apbi.paddr(MADDR) = '0' then
rv(addr).cnt := apbi.pwdata;
if nmax /= 0 and nmax > addr then mrv(addr).max := apbi.pwdata; end if;
else
if nmax /= 0 and nmax > addr then
mrv(addr).el := apbi.pwdata(17);
mrv(addr).cd := apbi.pwdata(16);
end if;
rv(addr).suen := apbi.pwdata(15 downto 14);
rv(addr).clr := apbi.pwdata(13);
rv(addr).en := apbi.pwdata(12);
rv(addr).op := apbi.pwdata(4+op_len-1 downto 4);
rv(addr).cpu := apbi.pwdata(3 downto 0);
end if;
end if;
if latch_cnt_addr(apbi.paddr) and (apbi.psel(pindex) and apbi.penable) = '1' then
if apbi.paddr(MADDR) = '0' then
rdata:= lmrc(addr).max;
else
rdata := r.timer;
end if;
v.latcnt := v.latcnt or apbi.pwrite;
end if;
end if;
if lahben /= 0 then
if ahbsi.hready = '1' then
if ahbsi.htrans(1) = '1' then v.active := '1'; v.hmaster := ahbsi.hmaster;
else v.active := '0'; end if;
end if;
else
v.active := '0'; v.hmaster := (others => '0');
end if;
if rstn = '0' then
for i in 0 to ncnt-1 loop rv(i).en := '0'; rv(i).inc := '0'; end loop;
if lahben /= 0 then v.active := '0'; end if;
end if;
if nextev = 0 and dsuen = 0 and astaten = 0 then
for i in 0 to ncnt-1 loop rv(i).op(6) := '0'; end loop;
end if;
rcin <= rv(0 to ncnt-1); mrcin <= mrv(0 to nmax_right); rin <= v;
apbo.prdata <= rdata; -- drive apb read bus
apbo.pirq <= (others => '0');
apb2o.prdata <= rdata2;
apb2o.pirq <= (others => '0');
end process;
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
apb2o.pindex <= pindex2;
apb2o.pconfig <= pconfig2;
regs : process(clk)
begin
if rising_edge(clk) then
rc <= rcin;
end if;
end process;
mregs : if nmax /= 0 generate
regs : process(clk)
begin
if rising_edge(clk) then
mrc <= mrcin;
end if;
end process;
end generate;
nomregs : if nmax = 0 generate
mrc(0) <= mcnt_none;
end generate;
ahbregs : if lahben /= 0 or LATCH_CNT generate
regs : process(clk)
begin if rising_edge(clk) then r <= rin; end if; end process;
end generate;
noahbregs : if lahben = 0 and not LATCH_CNT generate
r <= ((others => '0'), '0', '0', (others => '0'));
end generate;
-- pragma translate_off
bootmsg : report_version
generic map ("lstat_" & tost(pindex) & ": " &
"LEON Statistics Unit, " & "ncpu : " & tost(ncpu) &
", ncnt : " & tost(ncnt) & ", rev " & tost(REVISION));
-- pragma translate_on
-- pragma translate_off
cproc : process
begin
assert (clatch = 0) or (pmask /= 16#fff# and nmax /= 0)
report "LSTAT: clatch /= 0 requires pmask /= 16#fff# and nmax /= 0"
severity failure;
wait;
assert (REVISION = 1 and pmask <= 16#ffc#) or (REVISION = 0)
report "LSTAT: REVISION 1 of core requires pmask = 16#ffc# or larger area"
severity failure;
wait;
end process;
-- pragma translate_on
end;
| gpl-3.0 | 8a00f502279c718b81457e8e7c605f8e | 0.54724 | 3.260029 | false | false | false | false |
hterkelsen/mal | vhdl/step6_file.vhdl | 13 | 10,297 | entity step6_file is
end entity step6_file;
library STD;
use STD.textio.all;
library WORK;
use WORK.pkg_readline.all;
use WORK.types.all;
use WORK.printer.all;
use WORK.reader.all;
use WORK.env.all;
use WORK.core.all;
architecture test of step6_file is
shared variable repl_env: env_ptr;
procedure mal_READ(str: in string; ast: out mal_val_ptr; err: out mal_val_ptr) is
begin
read_str(str, ast, err);
end procedure mal_READ;
-- Forward declaration
procedure EVAL(in_ast: inout mal_val_ptr; in_env: inout env_ptr; result: out mal_val_ptr; err: out mal_val_ptr);
procedure apply_func(fn: inout mal_val_ptr; args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr);
procedure fn_eval(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
EVAL(args.seq_val(0), repl_env, result, err);
end procedure fn_eval;
procedure fn_swap(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable atom: mal_val_ptr := args.seq_val(0);
variable fn: mal_val_ptr := args.seq_val(1);
variable call_args_seq: mal_seq_ptr;
variable call_args, eval_res, sub_err: mal_val_ptr;
begin
call_args_seq := new mal_seq(0 to args.seq_val'length - 2);
call_args_seq(0) := atom.seq_val(0);
call_args_seq(1 to call_args_seq'length - 1) := args.seq_val(2 to args.seq_val'length - 1);
new_seq_obj(mal_list, call_args_seq, call_args);
apply_func(fn, call_args, eval_res, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
atom.seq_val(0) := eval_res;
result := eval_res;
end procedure fn_swap;
procedure apply_native_func(func_sym: inout mal_val_ptr; args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
if func_sym.string_val.all = "eval" then
fn_eval(args, result, err);
elsif func_sym.string_val.all = "swap!" then
fn_swap(args, result, err);
else
eval_native_func(func_sym, args, result, err);
end if;
end procedure apply_native_func;
procedure apply_func(fn: inout mal_val_ptr; args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable fn_env: env_ptr;
begin
case fn.val_type is
when mal_nativefn =>
apply_native_func(fn, args, result, err);
when mal_fn =>
new_env(fn_env, fn.func_val.f_env, fn.func_val.f_args, args);
EVAL(fn.func_val.f_body, fn_env, result, err);
when others =>
new_string("not a function", err);
return;
end case;
end procedure apply_func;
procedure eval_ast_seq(ast_seq: inout mal_seq_ptr; env: inout env_ptr; result: inout mal_seq_ptr; err: out mal_val_ptr) is
variable eval_err: mal_val_ptr;
begin
result := new mal_seq(0 to ast_seq'length - 1);
for i in result'range loop
EVAL(ast_seq(i), env, result(i), eval_err);
if eval_err /= null then
err := eval_err;
return;
end if;
end loop;
end procedure eval_ast_seq;
procedure eval_ast(ast: inout mal_val_ptr; env: inout env_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable key, val, eval_err, env_err: mal_val_ptr;
variable new_seq: mal_seq_ptr;
variable i: integer;
begin
case ast.val_type is
when mal_symbol =>
env_get(env, ast, val, env_err);
if env_err /= null then
err := env_err;
return;
end if;
result := val;
return;
when mal_list | mal_vector | mal_hashmap =>
eval_ast_seq(ast.seq_val, env, new_seq, eval_err);
if eval_err /= null then
err := eval_err;
return;
end if;
new_seq_obj(ast.val_type, new_seq, result);
return;
when others =>
result := ast;
return;
end case;
end procedure eval_ast;
procedure EVAL(in_ast: inout mal_val_ptr; in_env: inout env_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable i: integer;
variable ast, evaled_ast, a0, call_args, val, vars, sub_err, fn: mal_val_ptr;
variable env, let_env, fn_env: env_ptr;
begin
ast := in_ast;
env := in_env;
loop
if ast.val_type /= mal_list then
eval_ast(ast, env, result, err);
return;
end if;
if ast.seq_val'length = 0 then
result := ast;
return;
end if;
a0 := ast.seq_val(0);
if a0.val_type = mal_symbol then
if a0.string_val.all = "def!" then
EVAL(ast.seq_val(2), env, val, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
env_set(env, ast.seq_val(1), val);
result := val;
return;
elsif a0.string_val.all = "let*" then
vars := ast.seq_val(1);
new_env(let_env, env);
i := 0;
while i < vars.seq_val'length loop
EVAL(vars.seq_val(i + 1), let_env, val, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
env_set(let_env, vars.seq_val(i), val);
i := i + 2;
end loop;
env := let_env;
ast := ast.seq_val(2);
next; -- TCO
elsif a0.string_val.all = "do" then
for i in 1 to ast.seq_val'high - 1 loop
EVAL(ast.seq_val(i), env, result, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
end loop;
ast := ast.seq_val(ast.seq_val'high);
next; -- TCO
elsif a0.string_val.all = "if" then
EVAL(ast.seq_val(1), env, val, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
if val.val_type = mal_nil or val.val_type = mal_false then
if ast.seq_val'length > 3 then
ast := ast.seq_val(3);
else
new_nil(result);
return;
end if;
else
ast := ast.seq_val(2);
end if;
next; -- TCO
elsif a0.string_val.all = "fn*" then
new_fn(ast.seq_val(2), ast.seq_val(1), env, result);
return;
end if;
end if;
eval_ast(ast, env, evaled_ast, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
seq_drop_prefix(evaled_ast, 1, call_args);
fn := evaled_ast.seq_val(0);
case fn.val_type is
when mal_nativefn =>
apply_native_func(fn, call_args, result, err);
return;
when mal_fn =>
new_env(fn_env, fn.func_val.f_env, fn.func_val.f_args, call_args);
env := fn_env;
ast := fn.func_val.f_body;
next; -- TCO
when others =>
new_string("not a function", err);
return;
end case;
end loop;
end procedure EVAL;
procedure mal_PRINT(exp: inout mal_val_ptr; result: out line) is
begin
pr_str(exp, true, result);
end procedure mal_PRINT;
procedure RE(str: in string; env: inout env_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable ast, read_err: mal_val_ptr;
begin
mal_READ(str, ast, read_err);
if read_err /= null then
err := read_err;
result := null;
return;
end if;
if ast = null then
result := null;
return;
end if;
EVAL(ast, env, result, err);
end procedure RE;
procedure REP(str: in string; env: inout env_ptr; result: out line; err: out mal_val_ptr) is
variable eval_res, eval_err: mal_val_ptr;
begin
RE(str, env, eval_res, eval_err);
if eval_err /= null then
err := eval_err;
result := null;
return;
end if;
mal_PRINT(eval_res, result);
end procedure REP;
procedure set_argv(e: inout env_ptr; program_file: inout line) is
variable argv_var_name: string(1 to 6) := "*ARGV*";
variable argv_sym, argv_list: mal_val_ptr;
file f: text;
variable status: file_open_status;
variable one_line: line;
variable seq: mal_seq_ptr;
variable element: mal_val_ptr;
begin
program_file := null;
seq := new mal_seq(0 to -1);
file_open(status, f, external_name => "vhdl_argv.tmp", open_kind => read_mode);
if status = open_ok then
if not endfile(f) then
readline(f, program_file);
while not endfile(f) loop
readline(f, one_line);
new_string(one_line.all, element);
seq := new mal_seq'(seq.all & element);
end loop;
end if;
file_close(f);
end if;
new_seq_obj(mal_list, seq, argv_list);
new_symbol(argv_var_name, argv_sym);
env_set(e, argv_sym, argv_list);
end procedure set_argv;
procedure repl is
variable is_eof: boolean;
variable program_file, input_line, result: line;
variable eval_sym, eval_fn, dummy_val, err: mal_val_ptr;
variable outer: env_ptr;
variable eval_func_name: string(1 to 4) := "eval";
begin
outer := null;
new_env(repl_env, outer);
-- core.EXT: defined using VHDL (see core.vhdl)
define_core_functions(repl_env);
new_symbol(eval_func_name, eval_sym);
new_nativefn(eval_func_name, eval_fn);
env_set(repl_env, eval_sym, eval_fn);
set_argv(repl_env, program_file);
-- core.mal: defined using the language itself
RE("(def! not (fn* (a) (if a false true)))", repl_env, dummy_val, err);
RE("(def! load-file (fn* (f) (eval (read-string (str " & '"' & "(do " & '"' & " (slurp f) " & '"' & ")" & '"' & ")))))", repl_env, dummy_val, err);
if program_file /= null then
REP("(load-file " & '"' & program_file.all & '"' & ")", repl_env, result, err);
return;
end if;
loop
mal_readline("user> ", is_eof, input_line);
exit when is_eof;
next when input_line'length = 0;
REP(input_line.all, repl_env, result, err);
if err /= null then
pr_str(err, false, result);
result := new string'("Error: " & result.all);
end if;
if result /= null then
mal_printline(result.all);
end if;
deallocate(result);
deallocate(err);
end loop;
mal_printline("");
end procedure repl;
begin
repl;
end architecture test;
| mpl-2.0 | 1a4590ad112fe5dacaea587f926ea51b | 0.57036 | 3.208788 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-xilinx-vc707/config.vhd | 1 | 11,956 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex7;
constant CFG_MEMTECH : integer := virtex7;
constant CFG_PADTECH : integer := virtex7;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex7;
constant CFG_CLKMUL : integer := (4);
constant CFG_CLKDIV : integer := (8);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON processor core
constant CFG_LEON : integer := 3;
constant CFG_NCPU : integer := (4);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 4;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 4;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_BWMASK : integer := 16#0#;
constant CFG_CACHEBW : integer := 128;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 4 + 64*1;
constant CFG_ATBSZ : integer := 4;
constant CFG_AHBPF : integer := 2;
constant CFG_AHBWP : integer := 2;
constant CFG_LEONFT_EN : integer := 0 + 0*8;
constant CFG_LEON_NETLIST : integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 1;
constant CFG_STAT_CNT : integer := (4);
constant CFG_STAT_NMAX : integer := (0);
constant CFG_STAT_DSUEN : integer := 1;
constant CFG_NP_ASI : integer := 1;
constant CFG_WRPSR : integer := 1;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- L2 Cache
constant CFG_L2_EN : integer := 0;
constant CFG_L2_SIZE : integer := 64;
constant CFG_L2_WAYS : integer := 1;
constant CFG_L2_HPROT : integer := 0;
constant CFG_L2_PEN : integer := 0;
constant CFG_L2_WT : integer := 0;
constant CFG_L2_RAN : integer := 0;
constant CFG_L2_SHARE : integer := 0;
constant CFG_L2_LSZ : integer := 32;
constant CFG_L2_MAP : integer := 16#00F0#;
constant CFG_L2_MTRR : integer := (0);
constant CFG_L2_EDAC : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 1;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- USB DSU
constant CFG_GRUSB_DCL : integer := 0;
constant CFG_GRUSB_DCL_UIFACE : integer := 1;
constant CFG_GRUSB_DCL_DW : integer := 8;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 16;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000000#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- Xilinx MIG 7-Series
constant CFG_MIG_7SERIES : integer := 1;
constant CFG_MIG_7SERIES_MODEL : integer := 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 0;
constant CFG_AHBSTATN : integer := (1);
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 1;
constant CFG_AHBRSZ : integer := 4;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 8;
constant CFG_GRETH_FT : integer := 0;
constant CFG_GRETH_EDCLFT : integer := 0;
-- USB Host Controller
constant CFG_GRUSBHC : integer := 0;
constant CFG_GRUSBHC_NPORTS : integer := (1);
constant CFG_GRUSBHC_EHC : integer := 0;
constant CFG_GRUSBHC_UHC : integer := 0;
constant CFG_GRUSBHC_NCC : integer := 1;
constant CFG_GRUSBHC_NPCC : integer := (1);
constant CFG_GRUSBHC_PRR : integer := 0;
constant CFG_GRUSBHC_PR1 : integer := 0*2**26 + 0*2**22 + 0*2**18 + 0*2**14 + 0*2**10 + 0*2**6 + 0*2**2 + (1/4);
constant CFG_GRUSBHC_PR2 : integer := 0*2**26 + 0*2**22 + 0*2**18 + 0*2**14 + 0*2**10 + 0*2**6 + 0*2**2 + (1 mod 4);
constant CFG_GRUSBHC_ENDIAN : integer := 1;
constant CFG_GRUSBHC_BEREGS : integer := 0;
constant CFG_GRUSBHC_BEDESC : integer := 0;
constant CFG_GRUSBHC_BLO : integer := 3;
constant CFG_GRUSBHC_BWRD : integer := (16);
constant CFG_GRUSBHC_UTM : integer := 2;
constant CFG_GRUSBHC_VBUSCONF : integer := 3;
-- GR USB 2.0 Device Controller
constant CFG_GRUSBDC : integer := 0;
constant CFG_GRUSBDC_AIFACE : integer := 0;
constant CFG_GRUSBDC_UIFACE : integer := 1;
constant CFG_GRUSBDC_DW : integer := 8;
constant CFG_GRUSBDC_NEPI : integer := (1);
constant CFG_GRUSBDC_NEPO : integer := (1);
constant CFG_GRUSBDC_I0 : integer := (1024);
constant CFG_GRUSBDC_I1 : integer := (1024);
constant CFG_GRUSBDC_I2 : integer := (1024);
constant CFG_GRUSBDC_I3 : integer := (1024);
constant CFG_GRUSBDC_I4 : integer := (1024);
constant CFG_GRUSBDC_I5 : integer := (1024);
constant CFG_GRUSBDC_I6 : integer := (1024);
constant CFG_GRUSBDC_I7 : integer := (1024);
constant CFG_GRUSBDC_I8 : integer := (1024);
constant CFG_GRUSBDC_I9 : integer := (1024);
constant CFG_GRUSBDC_I10 : integer := (1024);
constant CFG_GRUSBDC_I11 : integer := (1024);
constant CFG_GRUSBDC_I12 : integer := (1024);
constant CFG_GRUSBDC_I13 : integer := (1024);
constant CFG_GRUSBDC_I14 : integer := (1024);
constant CFG_GRUSBDC_I15 : integer := (1024);
constant CFG_GRUSBDC_O0 : integer := (1024);
constant CFG_GRUSBDC_O1 : integer := (1024);
constant CFG_GRUSBDC_O2 : integer := (1024);
constant CFG_GRUSBDC_O3 : integer := (1024);
constant CFG_GRUSBDC_O4 : integer := (1024);
constant CFG_GRUSBDC_O5 : integer := (1024);
constant CFG_GRUSBDC_O6 : integer := (1024);
constant CFG_GRUSBDC_O7 : integer := (1024);
constant CFG_GRUSBDC_O8 : integer := (1024);
constant CFG_GRUSBDC_O9 : integer := (1024);
constant CFG_GRUSBDC_O10 : integer := (1024);
constant CFG_GRUSBDC_O11 : integer := (1024);
constant CFG_GRUSBDC_O12 : integer := (1024);
constant CFG_GRUSBDC_O13 : integer := (1024);
constant CFG_GRUSBDC_O14 : integer := (1024);
constant CFG_GRUSBDC_O15 : integer := (1024);
-- CAN 2.0 interface
constant CFG_CAN : integer := 0;
constant CFG_CAN_NUM : integer := (1);
constant CFG_CANIO : integer := 16#C00#;
constant CFG_CANIRQ : integer := (13);
constant CFG_CANSEPIRQ: integer := 0;
constant CFG_CAN_SYNCRST : integer := 0;
constant CFG_CANFT : integer := 0;
-- Spacewire interface
constant CFG_SPW_EN : integer := 0;
constant CFG_SPW_NUM : integer := (1);
constant CFG_SPW_AHBFIFO : integer := 16;
constant CFG_SPW_RXFIFO : integer := 16;
constant CFG_SPW_RMAP : integer := 0;
constant CFG_SPW_RMAPBUF : integer := 4;
constant CFG_SPW_RMAPCRC : integer := 0;
constant CFG_SPW_NETLIST : integer := 0;
constant CFG_SPW_FT : integer := 0;
constant CFG_SPW_GRSPW : integer := 2;
constant CFG_SPW_RXUNAL : integer := 0;
constant CFG_SPW_DMACHAN : integer := (1);
constant CFG_SPW_PORTS : integer := (1);
constant CFG_SPW_INPUT : integer := 3;
constant CFG_SPW_OUTPUT : integer := 0;
constant CFG_SPW_RTSAME : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 32;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- I2C master
constant CFG_I2C_ENABLE : integer := 1;
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 0;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 0;
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 0;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#0B#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 0;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := (1);
constant CFG_SPIMCTRL_ASCALER : integer := (8);
constant CFG_SPIMCTRL_PWRUPCNT : integer := (0);
constant CFG_SPIMCTRL_OFFSET : integer := 16#0#;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 1;
constant CFG_SPICTRL_NUM : integer := (1);
constant CFG_SPICTRL_SLVS : integer := (1);
constant CFG_SPICTRL_FIFO : integer := (1);
constant CFG_SPICTRL_SLVREG : integer := 0;
constant CFG_SPICTRL_ODMODE : integer := 0;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 0;
constant CFG_SPICTRL_MAXWLEN : integer := (0);
constant CFG_SPICTRL_SYNCRAM : integer := 0;
constant CFG_SPICTRL_FT : integer := 0;
-- Dynamic Partial Reconfiguration
constant CFG_PRC : integer := 0;
constant CFG_CRC_EN : integer := 0;
constant CFG_EDAC_EN : integer := 0;
constant CFG_WORDS_BLOCK : integer := 100;
constant CFG_DCM_FIFO : integer := 0;
constant CFG_DPR_FIFO : integer := 9;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-3.0 | f3c0ecaa89f1aa6d4bc77406cc43d563 | 0.65097 | 3.481654 | false | false | false | false |
yishinli/emc2 | src/hal/drivers/mesa-hostmot2/firmware/src/hostmot2.vhd | 1 | 56,150 | library IEEE;
use IEEE.std_logic_1164.all; -- defines std_logic types
use IEEE.std_logic_ARITH.ALL;
use IEEE.std_logic_UNSIGNED.ALL;
--
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
-- http://www.mesanet.com
--
-- This program is is licensed under a disjunctive dual license giving you
-- the choice of one of the two following sets of free software/open source
-- licensing terms:
--
-- * GNU General Public License (GPL), version 2.0 or later
-- * 3-clause BSD License
--
--
-- The GNU GPL License:
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- The 3-clause BSD License:
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- * Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- * Neither the name of Mesa Electronics nor the names of its
-- contributors may be used to endorse or promote products
-- derived from this software without specific prior written
-- permission.
--
--
-- Disclaimer:
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
use work.IDROMConst.all;
library UNISIM;
use UNISIM.VComponents.all;
entity HostMot2 is
generic
(
ThePinDesc: PinDescType;
TheModuleID: ModuleIDType;
StepGens: integer;
QCounters: integer;
MuxedQCounters: integer;
MuxedQCountersMIM: integer;
PWMGens: integer;
SPIs: integer;
BSPIs: integer;
DBSPIs: integer;
SSSIs: integer;
UARTs: integer;
PWMRefWidth: integer;
StepGenTableWidth: integer;
BSPICSWidth : integer;
DBSPICSWidth : integer;
IDROMType: integer;
SepClocks: boolean;
OneWS: boolean;
UseStepGenPrescaler : boolean;
UseIRQLogic: boolean;
UseWatchDog: boolean;
OffsetToModules: integer;
OffsetToPinDesc: integer;
ClockHigh: integer;
ClockLow: integer;
BoardNameLow : std_Logic_Vector(31 downto 0);
BoardNameHigh : std_Logic_Vector(31 downto 0);
FPGASize: integer;
FPGAPins: integer;
IOPorts: integer;
IOWidth: integer;
PortWidth: integer;
BusWidth: integer;
AddrWidth: integer;
InstStride0: integer;
InstStride1: integer;
RegStride0: integer;
RegStride1: integer;
LEDCount: integer
);
port
(
-- Generic 32 bit bus interface signals --
ibus: in std_logic_vector(buswidth -1 downto 0);
obus: out std_logic_vector(buswidth -1 downto 0);
addr: in std_logic_vector(addrwidth -1 downto 2);
read: in std_logic;
write: in std_logic;
clklow: in std_logic;
clkhigh: in std_logic;
int: out std_logic;
iobits: inout std_logic_vector (iowidth -1 downto 0);
leds: out std_logic_vector(ledcount-1 downto 0)
);
end HostMot2;
architecture dataflow of HostMot2 is
-- decodes --
-- IDROM related signals
signal A : std_logic_vector(addrwidth -1 downto 2);
signal LoadIDROM: std_logic;
signal ReadIDROM: std_logic;
signal LoadIDROMWEn: std_logic;
signal ReadIDROMWEn: std_logic;
signal IDROMWEn: std_logic_vector(0 downto 0);
signal ROMAdd: std_logic_vector(7 downto 0);
-- I/O port related signals
signal AltData : std_logic_vector(IOWidth-1 downto 0);
signal PortSel: std_logic;
signal LoadPortCmd: std_logic_vector(IOPorts -1 downto 0);
signal ReadPortCmd: std_logic_vector(IOPorts -1 downto 0);
signal DDRSel: std_logic;
signal LoadDDRCmd: std_logic_vector(IOPorts -1 downto 0);
signal ReadDDRCmd: std_logic_vector(IOPorts -1 downto 0);
signal AltDataSrcSel: std_logic;
signal LoadAltDataSrcCmd: std_logic_vector(IOPorts -1 downto 0);
signal OpenDrainModeSel: std_logic;
signal LoadOpenDrainModeCmd: std_logic_vector(IOPorts -1 downto 0);
signal OutputInvSel: std_logic;
signal LoadOutputInvCmd: std_logic_vector(IOPorts -1 downto 0);
-- Step generator related signals
signal StepGenRateSel: std_logic;
signal LoadStepGenRate: std_logic_vector(StepGens -1 downto 0);
signal ReadStepGenRate: std_logic_vector(StepGens -1 downto 0);
signal StepGenAccumSel: std_logic;
signal LoadStepGenAccum: std_logic_vector(StepGens -1 downto 0);
signal ReadStepGenAccum: std_logic_vector(StepGens -1 downto 0);
signal StepGenModeSel: std_logic;
signal LoadStepGenMode: std_logic_vector(StepGens -1 downto 0);
signal ReadStepGenMode: std_logic_vector(StepGens -1 downto 0);
signal StepGenDSUTimeSel: std_logic;
signal LoadStepGenDSUTime: std_logic_vector(StepGens -1 downto 0);
signal ReadStepGenDSUTime: std_logic_vector(StepGens -1 downto 0);
signal StepGenDHLDTimeSel: std_logic;
signal LoadStepGenDHLDTime: std_logic_vector(StepGens -1 downto 0);
signal ReadStepGenDHLDTime: std_logic_vector(StepGens -1 downto 0);
signal StepGenPulseATimeSel: std_logic;
signal LoadStepGenPulseATime: std_logic_vector(StepGens -1 downto 0);
signal ReadStepGenPulseATime: std_logic_vector(StepGens -1 downto 0);
signal StepGenPulseITimeSel: std_logic;
signal LoadStepGenPulseITime: std_logic_vector(StepGens -1 downto 0);
signal ReadStepGenPulseITime: std_logic_vector(StepGens -1 downto 0);
signal StepGenTableMaxSel: std_logic;
signal LoadStepGenTableMax: std_logic_vector(StepGens -1 downto 0);
signal ReadStepGenTableMax: std_logic_vector(StepGens -1 downto 0);
signal StepGenTableSel: std_logic;
signal LoadStepGenTable: std_logic_vector(StepGens -1 downto 0);
signal ReadStepGenTable: std_logic_vector(StepGens -1 downto 0);
type StepGenOutType is array(StepGens-1 downto 0) of std_logic_vector(StepGenTableWidth-1 downto 0);
signal StepGenOut : StepGenOutType;
-- Step generators master rate related signals
signal LoadStepGenBasicRate: std_logic;
signal ReadStepGenBasicRate: std_logic;
signal StepGenBasicRate: std_logic;
-- Quadrature counter related signals
signal QCounterSel : std_logic;
signal LoadQCounter: std_logic_vector(QCounters-1 downto 0);
signal ReadQCounter: std_logic_vector(QCounters-1 downto 0);
signal QCounterCCRSel : std_logic;
signal LoadQCounterCCR: std_logic_vector(QCounters-1 downto 0);
signal ReadQCounterCCR: std_logic_vector(QCounters-1 downto 0);
-- Quadrature counter timestamp reference counter
signal LoadTSDiv : std_logic;
signal ReadTSDiv : std_logic;
signal ReadTS : std_logic;
signal TimeStampBus: std_logic_vector(15 downto 0);
-- Quadrature counter filter rate signals
signal LoadQCountRate : std_logic;
signal QCountFilterRate : std_logic;
-- Quadrature counter input signals
signal QuadA: std_logic_vector(QCounters-1 downto 0);
signal QuadB: std_logic_vector(QCounters-1 downto 0);
signal Index: std_logic_vector(QCounters -1 downto 0);
signal IndexMask: std_logic_vector(QCounters -1 downto 0);
--- Multiplexed Encoder related signals
signal MuxedQCounterSel : std_logic;
signal LoadMuxedQCounter: std_logic_vector(MuxedQCounters-1 downto 0);
signal ReadMuxedQCounter: std_logic_vector(MuxedQCounters-1 downto 0);
signal MuxedQCounterCCRSel : std_logic;
signal LoadMuxedQCounterCCR: std_logic_vector(MuxedQCounters-1 downto 0);
signal ReadMuxedQCounterCCR: std_logic_vector(MuxedQCounters-1 downto 0);
-- Muxed Quadrature counter timestamp reference counter
signal LoadMuxedTSDiv : std_logic;
signal ReadMuxedTSDiv : std_logic;
signal ReadMuxedTS : std_logic;
signal MuxedTimeStampBus: std_logic_vector(15 downto 0);
-- Muxed Quadrature counter filter rate signals
signal LoadMuxedQCountRate : std_logic;
signal MuxedQCountFilterRate : std_logic;
signal PreMuxedQctrSel : std_logic_vector(1 downto 0);
signal MuxedQCtrSel : std_logic_vector(1 downto 0);
signal MuxedQuadA: std_logic_vector(MuxedQCounters/2 -1 downto 0); -- 2 should be muxdepth constant?
signal MuxedQuadB: std_logic_vector(MuxedQCounters/2 -1 downto 0);
signal MuxedIndex: std_logic_vector(MuxedQCounters/2 -1 downto 0);
signal MuxedIndexMask: std_logic_vector(MuxedQCounters -1 downto 0);
signal MuxedIndexMaskMIM: std_logic_vector(MuxedQCountersMIM/2 -1 downto 0);
signal DemuxedIndexMask: std_logic_vector(MuxedQCountersMIM -1 downto 0);
signal DeMuxedQuadA: std_logic_vector(MuxedQCounters -1 downto 0);
signal DeMuxedQuadB: std_logic_vector(MuxedQCounters -1 downto 0);
signal DeMuxedIndex: std_logic_vector(MuxedQCounters -1 downto 0);
-- PWM generator related signals
signal NumberOfPWMS : integer;
signal PWMGenOutA: std_logic_vector(PWMGens -1 downto 0);
signal PWMGenOutB: std_logic_vector(PWMGens -1 downto 0);
signal PWMGenOutC: std_logic_vector(PWMGens -1 downto 0);
signal LoadPWMRate : std_logic;
signal LoadPDMRate : std_logic;
signal RefCountBus : std_logic_vector(PWMRefWidth-1 downto 0);
signal PDMRate : std_logic;
signal PWMValSel : std_logic;
signal PWMCRSel : std_logic;
signal LoadPWMVal: std_logic_vector(PWMGens -1 downto 0);
signal LoadPWMCR: std_logic_vector(PWMGens -1 downto 0);
signal LoadPWMEnas: std_logic;
signal ReadPWMEnas: std_logic;
--- SPI interface related signals
signal SPIBitCountSel : std_logic;
signal SPIBitrateSel : std_logic;
signal SPIDataSel : std_logic;
signal LoadSPIBitCount: std_logic_vector(SPIs -1 downto 0);
signal LoadSPIBitRate: std_logic_vector(SPIs -1 downto 0);
signal LoadSPIData: std_logic_vector(SPIs -1 downto 0);
signal ReadSPIData: std_logic_vector(SPIs -1 downto 0);
signal ReadSPIBitCOunt: std_logic_vector(SPIs -1 downto 0);
signal ReadSPIBitRate: std_logic_vector(SPIs -1 downto 0);
signal SPIClk: std_logic_vector(SPIs -1 downto 0);
signal SPIIn: std_logic_vector(SPIs -1 downto 0);
signal SPIOut: std_logic_vector(SPIs -1 downto 0);
signal SPIFrame: std_logic_vector(SPIs -1 downto 0);
signal SPIDAV: std_logic_vector(SPIs -1 downto 0);
--- BSPI interface related signals
signal BSPIDataSel : std_logic;
signal BSPIFIFOCountSel : std_logic;
signal BSPIDescriptorSel : std_logic;
signal LoadBSPIData: std_logic_vector(BSPIs -1 downto 0);
signal ReadBSPIData: std_logic_vector(BSPIs -1 downto 0);
signal LoadBSPIDescriptor: std_logic_vector(BSPIs -1 downto 0);
signal ReadBSPIFIFOCOunt: std_logic_vector(BSPIs -1 downto 0);
signal ClearBSPIFIFO: std_logic_vector(BSPIs -1 downto 0);
signal BSPIClk: std_logic_vector(BSPIs -1 downto 0);
signal BSPIIn: std_logic_vector(BSPIs -1 downto 0);
signal BSPIOut: std_logic_vector(BSPIs -1 downto 0);
signal BSPIFrame: std_logic_vector(BSPIs -1 downto 0);
type BSPICSType is array(BSPIs-1 downto 0) of std_logic_vector(BSPICSWidth-1 downto 0);
signal BSPICS : BSPICSType;
--- DBSPI interface related signals
signal DBSPIDataSel : std_logic;
signal DBSPIFIFOCountSel : std_logic;
signal DBSPIDescriptorSel : std_logic;
signal LoadDBSPIData: std_logic_vector(DBSPIs -1 downto 0);
signal ReadDBSPIData: std_logic_vector(DBSPIs -1 downto 0);
signal LoadDBSPIDescriptor: std_logic_vector(DBSPIs -1 downto 0);
signal ReadDBSPIFIFOCOunt: std_logic_vector(DBSPIs -1 downto 0);
signal ClearDBSPIFIFO: std_logic_vector(DBSPIs -1 downto 0);
signal DBSPIClk: std_logic_vector(DBSPIs -1 downto 0);
signal DBSPIIn: std_logic_vector(DBSPIs -1 downto 0);
signal DBSPIOut: std_logic_vector(DBSPIs -1 downto 0);
type DBSPICSType is array(DBSPIs-1 downto 0) of std_logic_vector(DBSPICSWidth-1 downto 0);
signal DBSPICS : DBSPICSType;
--- SSSI interface related signals
signal SSSIDataSel : std_logic;
signal SSSIBitCountSel : std_logic;
signal SSSIBitRateSel : std_logic;
signal LoadSSSIData: std_logic_vector(SSSIs -1 downto 0);
signal ReadSSSIData: std_logic_vector(SSSIs -1 downto 0);
signal LoadSSSIBitCount: std_logic_vector(SSSIs -1 downto 0);
signal ReadSSSIBitCOunt: std_logic_vector(SSSIs -1 downto 0);
signal LoadSSSIBitRate: std_logic_vector(SSSIs -1 downto 0);
signal ReadSSSIBitRate: std_logic_vector(SSSIs -1 downto 0);
signal GlobalPStartSSSI : std_logic;
signal GlobalTStartSSSI : std_logic;
signal SSSIClk: std_logic_vector(SSSIs -1 downto 0);
signal SSSIIn: std_logic_vector(SSSIs -1 downto 0);
--- UARTX interface related signals
signal UARTTDataSel : std_logic;
signal UARTTBitrateSel : std_logic;
signal UARTTFIFOCountSel : std_logic;
signal UARTTModeRegSel : std_logic;
signal LoadUARTTData: std_logic_vector(UARTs -1 downto 0);
signal LoadUARTTBitRate: std_logic_vector(UARTs -1 downto 0);
signal LoadUARTTModeReg: std_logic_vector(UARTs -1 downto 0);
signal CLearUARTTFIFO: std_logic_vector(UARTs -1 downto 0);
signal ReadUARTTFIFOCount: std_logic_vector(UARTs -1 downto 0);
signal ReadUARTTBitrate: std_logic_vector(UARTs -1 downto 0);
signal ReadUARTTModeReg: std_logic_vector(UARTs -1 downto 0);
signal UARTTFIFOEmpty: std_logic_vector(UARTs -1 downto 0);
signal UTDrvEn: std_logic_vector(UARTs -1 downto 0);
signal UTData: std_logic_vector(UARTs -1 downto 0);
--- UARTR interface related signals
signal UARTRDataSel : std_logic;
signal UARTRBitrateSel : std_logic;
signal UARTRFIFOCountSel : std_logic;
signal UARTRModeRegSel : std_logic;
signal LoadUARTRData: std_logic_vector(UARTs -1 downto 0);
signal LoadUARTRBitRate: std_logic_vector(UARTs -1 downto 0);
signal ReadUARTRBitrate: std_logic_vector(UARTs -1 downto 0);
signal ClearUARTRFIFO: std_logic_vector(UARTs -1 downto 0);
signal ReadUARTRFIFOCount: std_logic_vector(UARTs -1 downto 0);
signal ReadUARTRModeReg: std_logic_vector(UARTs -1 downto 0);
signal LoadUARTRModeReg: std_logic_vector(UARTs -1 downto 0);
signal UARTRFIFOHasData: std_logic_vector(UARTs -1 downto 0);
signal URData: std_logic_vector(UARTs -1 downto 0);
--- Watchdog related signals
signal LoadWDTime : std_logic;
signal ReadWDTime : std_logic;
signal LoadWDStatus : std_logic;
signal ReadWDStatus : std_logic;
signal WDCookie: std_logic;
signal WDBite : std_logic;
signal WDLatchedBite : std_logic;
--- IRQ related signals
signal LoadIRQDiv : std_logic;
signal ReadIRQDiv : std_logic;
signal LoadIRQStatus : std_logic;
signal ReadIrqStatus : std_logic;
signal ClearIRQ : std_logic;
--- ID related signals
signal ReadID : std_logic;
--- LED related signals
signal LoadLEDS : std_logic;
function OneOfNdecode(width : integer;ena1 : std_logic;ena2 : std_logic; dec : std_logic_vector) return std_logic_vector is
variable result : std_logic_vector(width-1 downto 0);
begin
if ena1 = '1' and ena2 = '1' then
for i in 0 to width -1 loop
if CONV_INTEGER(dec) = i then
result(i) := '1';
else
result(i) := '0';
end if;
end loop;
else
result := (others => '0');
end if;
return result;
end OneOfNDecode;
function bitreverse(v: in std_logic_vector) -- Thanks: J. Bromley
return std_logic_vector is
variable result: std_logic_vector(v'RANGE);
alias tv: std_logic_vector(v'REVERSE_RANGE) is v;
begin
for i in tv'RANGE loop
result(i) := tv(i);
end loop;
return result;
end;
begin
ahosmotid : entity hostmotid
generic map (
buswidth => BusWidth,
cookie => Cookie,
namelow => HostMotNameLow ,
namehigh => HostMotNameHigh,
idromoffset => IDROMOffset
)
port map (
readid => ReadID,
addr => A(3 downto 2),
obus => obus
);
makeoports: for i in 0 to IOPorts -1 generate
oportx: entity WordPR
generic map (
size => PortWidth,
buswidth => BusWidth
)
port map (
clear => WDBite,
clk => clklow,
ibus => ibus,
obus => obus,
loadport => LoadPortCmd(i),
loadddr => LoadDDRCmd(i),
loadaltdatasrc => LoadAltDataSrcCmd(i),
loadopendrainmode => LoadOpenDrainModeCmd(i),
loadinvert => LoadOutputInvCmd(i),
readddr => ReadDDRCmd(i),
portdata => IOBits((((i+1)*PortWidth) -1) downto (i*PortWidth)),
altdata => Altdata((((i+1)*PortWidth) -1) downto (i*PortWidth))
);
end generate;
makeiports: for i in 0 to IOPorts -1 generate
iportx: entity WordRB
generic map (size => PortWidth,
buswidth => BusWidth)
port map (
obus => obus,
readport => ReadPortCmd(i),
portdata => IOBits((((i+1)*PortWidth) -1) downto (i*PortWidth))
);
end generate;
makewatchdog: if UseWatchDog generate
wdogabittus: entity watchdog
generic map ( buswidth => BusWidth)
port map (
clk => clklow,
ibus => ibus,
obus => obus,
loadtime => LoadWDTime,
readtime => ReadWDTime,
loadstatus=> LoadWDStatus,
readstatus=> ReadWDStatus,
cookie => WDCookie,
wdbite => WDBite,
wdlatchedbite => WDLatchedBite
);
end generate;
makeirqlogic: if UseIRQlogic generate
somoldirqlogic: entity irqlogic
generic map(
buswidth => BusWidth,
dividerwidth => 16
)
port map (
clk => clklow,
ibus => ibus,
obus => obus,
loaddiv => LoadIRQDiv,
readdiv => ReadIRQDiv,
loadstatus => LoadIRQStatus,
readstatus => ReadIrqStatus,
clear => ClearIRQ,
ratesource => RefCountBus(PWMRefWidth-1 downto PWMRefWidth-8), -- from toggle bit all the way to 8X PWM rate
int => INT);
end generate;
makestepgens: if StepGens >0 generate
makeStepGenPreScaler: if UseStepGenPreScaler generate
StepRategen : entity RateGen port map(
ibus => ibus,
obus => obus,
loadbasicrate => LoadStepGenBasicRate,
readbasicrate => ReadStepGenBasicRate,
hold => '0',
basicrate => StepGenBasicRate,
clk => clklow);
end generate;
generatestepgens: for i in 0 to StepGens-1 generate
usg: if UseStepGenPreScaler generate
stepgenx: entity stepgen
generic map (
buswidth => BusWidth,
timersize => 14, -- = ~480 usec at 33 MHz, ~320 at 50 Mhz
tablewidth => StepGenTableWidth,
asize => 48,
rsize => 32
)
port map (
clk => clklow,
ibus => ibus,
obus => obus,
loadsteprate => LoadStepGenRate(i),
loadaccum => LoadStepGenAccum(i),
loadstepmode => LoadStepGenMode(i),
loaddirsetuptime => LoadStepGenDSUTime(i),
loaddirholdtime => LoadStepGenDHLDTime(i),
loadpulseactivetime => LoadStepGenPulseATime(i),
loadpulseidletime => LoadStepGenPulseITime(i),
loadtable => LoadStepGenTable(i),
loadtablemax => LoadStepGenTableMax(i),
readsteprate => ReadStepGenRate(i),
readaccum => ReadStepGenAccum(i),
readstepmode => ReadStepGenMode(i),
readdirsetuptime => ReadStepGenDSUTime(i),
readdirholdtime => ReadStepGenDHLDTime(i),
readpulseactivetime => ReadStepGenPulseATime(i),
readpulseidletime => ReadStepGenPulseITime(i),
readtable => ReadStepGenTable(i),
readtablemax => ReadStepGenTableMax(i),
basicrate => StepGenBasicRate,
hold => '0',
stout => StepGenOut(i)
);
end generate usg;
nusg: if not UseStepGenPreScaler generate
stepgenx: entity stepgen
generic map (
buswidth => BusWidth,
timersize => 14, -- = ~480 usec at 33 MHz, ~320 at 50 Mhz
tablewidth => StepGenTableWidth,
asize => 48,
rsize => 32
)
port map (
clk => clklow,
ibus => ibus,
obus => obus,
loadsteprate => LoadStepGenRate(i),
loadaccum => LoadStepGenAccum(i),
loadstepmode => LoadStepGenMode(i),
loaddirsetuptime => LoadStepGenDSUTime(i),
loaddirholdtime => LoadStepGenDHLDTime(i),
loadpulseactivetime => LoadStepGenPulseATime(i),
loadpulseidletime => LoadStepGenPulseITime(i),
loadtable => LoadStepGenTable(i),
loadtablemax => LoadStepGenTableMax(i),
readsteprate => ReadStepGenRate(i),
readaccum => ReadStepGenAccum(i),
readstepmode => ReadStepGenMode(i),
readdirsetuptime => ReadStepGenDSUTime(i),
readdirholdtime => ReadStepGenDHLDTime(i),
readpulseactivetime => ReadStepGenPulseATime(i),
readpulseidletime => ReadStepGenPulseITime(i),
readtable => ReadStepGenTable(i),
readtablemax => ReadStepGenTableMax(i),
basicrate => '1',
hold => '0',
stout => StepGenOut(i) -- densely packed starting with I/O bit 0
);
end generate nusg;
end generate generatestepgens;
end generate makestepgens;
makequadcounters: for i in 0 to QCounters-1 generate
qcounterx: entity qcounter
generic map (
buswidth => BusWidth
)
port map (
obus => obus,
ibus => ibus,
quada => QuadA(i),
quadb => QuadB(i),
index => Index(i),
loadccr => LoadQcounterCCR(i),
readccr => ReadQcounterCCR(i),
readcount => ReadQcounter(i),
countclear => LoadQcounter(i),
timestamp => TimeStampBus,
indexmask => IndexMask(i),
filterrate => QCountFilterRate,
clk => clklow
);
end generate makequadcounters;
makemuxedquadcounters: for i in 0 to MuxedQCounters-1 generate
qcounterx: entity qcounter
generic map (
buswidth => BusWidth
)
port map (
obus => obus,
ibus => ibus,
quada => DemuxedQuadA(i),
quadb => DemuxedQuadB(i),
index => DemuxedIndex(i),
loadccr => LoadMuxedQcounterCCR(i),
readccr => ReadMuxedQcounterCCR(i),
readcount => ReadMuxedQcounter(i),
countclear => LoadMuxedQcounter(i),
timestamp => MuxedTimeStampBus,
indexmask => MuxedIndexMask(i),
filterrate => MuxedQCountFilterRate,
clk => clklow
);
end generate makemuxedquadcounters;
makemuxedquadcountersmim: for i in 0 to MuxedQCountersMIM-1 generate
qcounterx: entity qcounter
generic map (
buswidth => BusWidth
)
port map (
obus => obus,
ibus => ibus,
quada => DemuxedQuadA(i),
quadb => DemuxedQuadB(i),
index => DemuxedIndex(i),
loadccr => LoadMuxedQcounterCCR(i),
readccr => ReadMuxedQcounterCCR(i),
readcount => ReadMuxedQcounter(i),
countclear => LoadMuxedQcounter(i),
timestamp => MuxedTimeStampBus,
indexmask => DeMuxedIndexMask(i),
filterrate => MuxedQCountFilterRate,
clk => clklow
);
end generate makemuxedquadcountersmim;
makeqcounterglobals: if (QCounters >0) generate
timestampx: entity timestamp
port map(
ibus => ibus(15 downto 0),
obus => obus(15 downto 0),
loadtsdiv => LoadTSDiv ,
readts => ReadTS,
readtsdiv =>ReadTSDiv,
tscount => TimeStampBus,
clk => clklow
);
qcountratex: entity qcounterate
generic map (defaultrate => x"800") -- default is clklow divided by 1 for normal counters
port map(
ibus => ibus(11 downto 0),
loadRate => LoadQCountRate,
rateout => QcountFilterRate,
clk => clklow
);
end generate;
makemuxedqcounterglobals: if (MuxedQCounters >0) generate
timestampx: entity timestamp
port map(
ibus => ibus(15 downto 0),
obus => obus(15 downto 0),
loadtsdiv => LoadTSDiv ,
readts => ReadMuxedTS,
readtsdiv =>ReadMuxedTSDiv,
tscount => MuxedTimeStampBus,
clk => clklow
);
qcountratex: entity qcounterate
generic map (defaultrate => x"002") -- default is clklow divided by 4 (N+2) for muxed counters
port map(
ibus => ibus(11 downto 0),
loadRate => LoadMuxedQCountRate,
rateout => MuxedQcountFilterRate,
clk => clklow
);
end generate;
makepwmref: if ((PWMGens > 0) or UseIRQLogic) generate
pwmref : entity pwmrefh
generic map (
buswidth => 16,
refwidth => PWMRefWidth -- Normally 13 for 12,11,10, and 9 bit PWM resolutions = 25KHz,50KHz,100KHz,200KHz max. Freq
)
port map (
clk => clklow,
hclk => clkhigh,
refcount => RefCountBus,
ibus => ibus(15 downto 0),
pdmrate => PDMRate,
pwmrateload => LoadPWMRate,
pdmrateload => LoadPDMRate
);
end generate;
makepwmgens : for i in 0 to PWMGens-1 generate
pwmgenx: entity pwmpdmgenh
generic map (
buswidth => BusWidth,
refwidth => PWMRefWidth -- Normally 13 for 12,11,10, and 9 bit PWM resolutions = 25KHz,50KHz,100KHz,200KHz max. Freq
)
port map (
clk => clklow,
hclk => clkhigh,
refcount => RefCountBus,
ibus => ibus,
loadpwmval => LoadPWMVal(i),
pcrloadcmd => LoadPWMCR(i),
pdmrate => PDMRate,
pwmouta => PWMGenOutA(i),
pwmoutb => PWMGenOutB(i)
);
end generate;
makePWMEna: if (PWMGens >0) generate
PWMEnaReg : entity boutreg
generic map (
size => PWMGens,
buswidth => BusWidth,
invert => true -- Must be true! got changed to false somehow
)
port map (
clk => clklow,
ibus => ibus,
obus => obus,
load => LoadPWMEnas,
read => ReadPWMEnas,
clear => '0',
dout => PWMGenOutC
);
end generate;
makeSPIs: for i in 0 to SPIs -1 generate
aspi: entity SimpleSPI
generic map (
buswidth => BusWidth)
port map (
clk => clklow,
ibus => ibus,
obus => obus,
loadbitcount => LoadSPIBitCount(i),
loadbitrate => LoadSPIBitRate(i),
loaddata => LoadSPIData(i),
readdata => ReadSPIData(i),
readbitcount => ReadSPIBitCOunt(i),
readbitrate => ReadSPIBitRate(i),
spiclk => SPIClk(i),
spiin => SPIIn(i),
spiout => SPIOut(i),
spiframe => SPIFrame(i),
davout => SPIDAV(i)
);
end generate;
makeBSPIs: for i in 0 to BSPIs -1 generate
bspi: entity BufferedSPI
generic map (
cswidth => BSPICSWidth,
gatedcs => false)
port map (
clk => clklow,
ibus => ibus,
obus => obus,
addr => A(5 downto 2),
hostpush => LoadBSPIData(i),
hostpop => ReadBSPIData(i),
loaddesc => LoadBSPIDescriptor(i),
loadasend => '0',
clear => ClearBSPIFIFO(i),
readcount => ReadBSPIFIFOCount(i),
spiclk => BSPIClk(i),
spiin => BSPIIn(i),
spiout => BSPIOut(i),
spiframe => BSPIFrame(i),
spicsout => BSPICS(i)
);
end generate;
makeDBSPIs: for i in 0 to DBSPIs -1 generate
bspi: entity BufferedSPI
generic map (
cswidth => DBSPICSWidth,
gatedcs => true
)
port map (
clk => clklow,
ibus => ibus,
obus => obus,
addr => A(5 downto 2),
hostpush => LoadDBSPIData(i),
hostpop => ReadDBSPIData(i),
loaddesc => LoadDBSPIDescriptor(i),
loadasend => '0',
clear => ClearDBSPIFIFO(i),
readcount => ReadDBSPIFIFOCount(i),
spiclk => DBSPIClk(i),
spiin => DBSPIIn(i),
spiout => DBSPIOut(i),
spicsout => DBSPICS(i)
);
end generate;
MakeSSSIs: for i in 0 to SSSIs -1 generate
sssi: entity SimpleSSI
Port map (
clk => clklow,
ibus => ibus,
obus => obus,
loadbitcount => LoadSSSIBitCount(i),
loadbitrate => LoadSSSIBitRate(i),
lstart => LoadSSSIData(i),
tstart => GlobalTStartSSSI,
pstart => GlobalPstartSSSI,
readdata => ReadSSSIData(i),
readbitcount => ReadSSSIBitCount(i),
readbitrate => ReadSSSIBitRate(i),
ssiclk => SSSIClk(i),
ssiin => SSSIIn(i)
);
end generate;
makeUARTRs: for i in 0 to UARTs -1 generate
auarrx: entity uartr
port map (
clk => clklow,
ibus => ibus,
obus => obus,
addr => A(3 downto 2),
popfifo => LoadUARTRData(i),
loadbitrate => LoadUARTRBitRate(i),
readbitrate => ReadUARTRBitrate(i),
clrfifo => ClearUARTRFIFO(i),
readfifocount => ReadUARTRFIFOCount(i),
loadmode => LoadUARTRModeReg(i),
readmode => ReadUARTRModeReg(i),
fifohasdata => UARTRFIFOHasData(i),
rxmask => UTDrvEn(i), -- for half duplex rx mask
rxdata => URData(i)
);
end generate;
makeUARTTXs: for i in 0 to UARTs -1 generate
auartx: entity uartx
port map (
clk => clklow,
ibus => ibus,
obus => obus,
addr => A(3 downto 2),
pushfifo => LoadUARTTData(i),
loadbitrate => LoadUARTTBitRate(i),
readbitrate => ReadUARTTBitrate(i),
clrfifo => ClearUARTTFIFO(i),
readfifocount => ReadUARTTFIFOCount(i),
loadmode => LoadUARTTModeReg(i),
readmode => ReadUARTTModeReg(i),
fifoempty => UARTTFIFOEmpty(i),
txen => '1',
drven => UTDrvEn(i),
txdata => UTData(i)
);
end generate;
LEDReg : entity boutreg
generic map (
size => LEDCount,
buswidth => LEDCount,
invert => true)
port map (
clk => clklow,
ibus => ibus(BusWidth-1 downto BusWidth-LEDCount),
obus => obus(BusWidth-1 downto BusWidth-LEDCount),
load => LoadLEDs,
read => '0',
clear => '0',
dout => LEDS
);
IDROMWP : entity boutreg
generic map (
size => 1,
buswidth => BusWidth,
invert => false
)
port map (
clk => clklow,
ibus => ibus,
obus => obus,
load => LoadIDROMWEn,
read => ReadIDROMWEn,
clear => '0',
dout => IDROMWen
);
IDROM : entity IDROM
generic map (
idromtype => IDROMType,
offsettomodules => OffsetToModules,
offsettopindesc => OffsetToPinDesc,
boardnamelow => BoardNameLow,
boardnameHigh => BoardNameHigh,
fpgasize => FPGASize,
fpgapins => FPGAPins,
ioports => IOPorts,
iowidth => IOWidth,
portwidth => PortWidth,
clocklow => ClockLow,
clockhigh => ClockHigh,
inststride0 => InstStride0,
inststride1 => InstStride1,
regstride0 => RegStride0,
regstride1 => RegStride1,
pindesc => ThePinDesc,
moduleid => TheModuleID)
port map (
clk => clklow,
we => LoadIDROM,
re => ReadIDROM,
radd => addr(9 downto 2),
wadd => A(9 downto 2),
din => ibus,
dout => obus
);
DoPinout: process(PWMGenOutA,PWMGenOutB,PWMGenOutC,StepGenOut,SPIFrame,SPIOut,SPIClk,
UTData,UTDrvEn,BSPIFrame,BSPIOut,BSPIClk,BSPICS,DBSPIOut,DBSPIClk,
DBSPICS,IOBits)
begin
Altdata <= (others => '0');
for i in 0 to IOWidth -1 loop
case ThePinDesc(i)(15 downto 8) is -- GTag
-- all these nasty subranges will go away when pindescs are changed to records
when QCountTag =>
case (ThePinDesc(i)(7 downto 0)) is --secondary pin function
when QCountQAPin =>
QuadA(conv_integer(ThePinDesc(i)(23 downto 16))) <= IOBits(i);
when QCountQBPin =>
QuadB(conv_integer(ThePinDesc(i)(23 downto 16))) <= IOBits(i);
when QCountIdxPin =>
Index(conv_integer(ThePinDesc(i)(23 downto 16))) <= IOBits(i);
when QCountIdxMaskPin =>
IndexMask(conv_integer(ThePinDesc(i)(23 downto 16))) <= IOBits(i);
when others => null;
end case;
when MuxedQCountTag =>
case (ThePinDesc(i)(7 downto 0)) is --secondary pin function
when MuxedQCountQAPin =>
MuxedQuadA(conv_integer(ThePinDesc(i)(23 downto 16))) <= IOBits(i);
when MuxedQCountQBPin =>
MuxedQuadB(conv_integer(ThePinDesc(i)(23 downto 16))) <= IOBits(i);
when MuxedQCountIdxPin =>
MuxedIndex(conv_integer(ThePinDesc(i)(23 downto 16))) <= IOBits(i);
when MuxedQCountIdxMaskPin =>
MuxedIndexMask(conv_integer(ThePinDesc(i)(23 downto 16))) <= IOBits(i);
when others => null;
end case;
when MuxedQCountSelTag =>
case(ThePinDesc(i)(7 downto 0)) is --secondary pin function
when MuxedQCountSel0Pin =>
AltData(i) <= MuxedQCtrSel(0);
when MuxedQCountSel1Pin =>
AltData(i) <= MuxedQCtrSel(1);
when others => null;
end case;
when PWMTag =>
case (ThePinDesc(i)(7 downto 0)) is --secondary pin function
when PWMAOutPin =>
AltData(i) <= PWMGENOutA(conv_integer(ThePinDesc(i)(23 downto 16)));
when PWMBDirPin =>
AltData(i) <= PWMGENOutB(conv_integer(ThePinDesc(i)(23 downto 16)));
when PWMCEnaPin =>
AltData(i) <= PWMGENOutC(conv_integer(ThePinDesc(i)(23 downto 16)));
when others => null;
end case;
when StepGenTag =>
AltData(i) <= StepGenOut(conv_integer(ThePinDesc(i)(23 downto 16)))(conv_integer(ThePinDesc(i)(6 downto 0))-1);
when UARTTTag =>
case (ThePinDesc(i)(7 downto 0)) is --secondary pin function
when UTDataPin =>
AltData(i) <= UTData(conv_integer(ThePinDesc(i)(23 downto 16)));
when UTDrvEnPin =>
AltData(i) <= UTDrvEn(conv_integer(ThePinDesc(i)(23 downto 16)));
when others => null;
end case;
when UARTRTag =>
if (ThePinDesc(i)(7 downto 0)) = URDataPin then
URData(conv_integer(ThePinDesc(i)(23 downto 16))) <= IOBits(i);
end if;
when SPITag =>
case (ThePinDesc(i)(7 downto 0)) is --secondary pin function, drop MSB
when SPIFramePin =>
AltData(i) <= SPIFrame(conv_integer(ThePinDesc(i)(23 downto 16)));
when SPIOutPin =>
AltData(i) <= SPIOut(conv_integer(ThePinDesc(i)(23 downto 16)));
when SPIClkPin =>
AltData(i) <= SPIClk(conv_integer(ThePinDesc(i)(23 downto 16)));
when SPIInPin =>
SPIIn(conv_integer(ThePinDesc(i)(23 downto 16))) <= IOBits(i);
when others => null;
end case;
when BSPITag =>
case (ThePinDesc(i)(7 downto 0)) is --secondary pin function, drop MSB
when BSPIFramePin =>
AltData(i) <= BSPIFrame(conv_integer(ThePinDesc(i)(23 downto 16)));
when BSPIOutPin =>
AltData(i) <= BSPIOut(conv_integer(ThePinDesc(i)(23 downto 16)));
when BSPIClkPin =>
AltData(i) <= BSPIClk(conv_integer(ThePinDesc(i)(23 downto 16)));
when BSPIInPin =>
BSPIIn(conv_integer(ThePinDesc(i)(23 downto 16))) <= IOBits(i);
when others => AltData(i) <= BSPICS(conv_integer(ThePinDesc(i)(23 downto 16)))(conv_integer(ThePinDesc(i)(6 downto 0))-5);
-- magic foo, magic foo, what on earth does it do?
-- (this needs to written more clearly!)
end case;
when DBSPITag =>
case (ThePinDesc(i)(7 downto 0)) is --secondary pin function, drop MSB
when DBSPIOutPin =>
AltData(i) <= DBSPIOut(conv_integer(ThePinDesc(i)(23 downto 16)));
when DBSPIClkPin =>
AltData(i) <= DBSPIClk(conv_integer(ThePinDesc(i)(23 downto 16)));
when DBSPIInPin =>
DBSPIIn(conv_integer(ThePinDesc(i)(23 downto 16))) <= IOBits(i);
when others => AltData(i) <= DBSPICS(conv_integer(ThePinDesc(i)(23 downto 16)))(conv_integer(ThePinDesc(i)(6 downto 0))-5);
-- magic foo, magic foo, what on earth does it do?
-- (this needs to written more clearly!)
end case;
when SSSITag =>
case (ThePinDesc(i)(7 downto 0)) is --secondary pin function, drop MSB
when SSSIClkPin =>
AltData(i) <= SSSIClk(conv_integer(ThePinDesc(i)(23 downto 16)));
when SSSIInPin =>
SSSIIn(conv_integer(ThePinDesc(i)(23 downto 16))) <= IOBits(i);
when others => null;
end case;
when others => null;
end case;
end loop;
end process;
LooseEnds: process(A,clklow)
begin
if rising_edge(clklow) then
A <= addr;
end if;
end process;
MuxedEnc: if MuxedQCounters > 0 generate
EncoderDeMux: process(clklow)
begin
if rising_edge(clklow) then
if MuxedQCountFilterRate = '1' then
PreMuxedQCtrSel <= PreMuxedQCtrSel + 1;
end if;
MuxedQCtrSel <= PreMuxedQCtrSel;
for i in 0 to ((MuxedQCounters/2) -1) loop -- just 2 deep for now
if PreMuxedQCtrSel(0) = '1' and MuxedQCtrSel(0) = '0' then -- latch the even inputs
DeMuxedQuadA(2*i) <= MuxedQuadA(i);
DeMuxedQuadB(2*i) <= MuxedQuadB(i);
DeMuxedIndex(2*i) <= MuxedIndex(i);
end if;
if PreMuxedQCtrSel(0) = '0' and MuxedQCtrSel(0) = '1' then -- latch the odd inputs
DeMuxedQuadA(2*i+1) <= MuxedQuadA(i);
DeMuxedQuadB(2*i+1) <= MuxedQuadB(i);
DeMuxedIndex(2*i+1) <= MuxedIndex(i);
end if;
end loop;
end if; -- clk
end process;
end generate;
MuxedEncMIM: if MuxedQCountersMIM > 0 generate
EncoderDeMuxMIM: process(clklow)
begin
if rising_edge(clklow) then
if MuxedQCountFilterRate = '1' then
PreMuxedQCtrSel <= PreMuxedQCtrSel + 1;
end if;
MuxedQCtrSel <= PreMuxedQCtrSel;
for i in 0 to ((MuxedQCounters/2) -1) loop -- just 2 deep for now
if PreMuxedQCtrSel(0) = '1' and MuxedQCtrSel(0) = '0' then -- latch the even inputs
DeMuxedQuadA(2*i) <= MuxedQuadA(i);
DeMuxedQuadB(2*i) <= MuxedQuadB(i);
DeMuxedIndex(2*i) <= MuxedIndex(i);
DeMuxedIndexMask(2*i) <= MuxedIndexMask(i);
end if;
if PreMuxedQCtrSel(0) = '0' and MuxedQCtrSel(0) = '1' then -- latch the odd inputs
DeMuxedQuadA(2*i+1) <= MuxedQuadA(i);
DeMuxedQuadB(2*i+1) <= MuxedQuadB(i);
DeMuxedIndex(2*i+1) <= MuxedIndex(i);
DeMuxedIndexMask(2*i+1) <= MuxedIndexMask(i);
end if;
end loop;
end if; -- clk
end process;
end generate;
Decode: process(A,write, IDROMWEn, read)
begin
-- basic multi decodes are at 256 byte increments (64 longs)
-- first decode is 256 x 32 ID ROM
if (A(15 downto 10) = IDROMAddr(7 downto 2)) and Write = '1' and IDROMWEn = "1" then -- 400 Hex
LoadIDROM <= '1';
else
LoadIDROM <= '0';
end if;
if (A(15 downto 10) = IDROMAddr(7 downto 2)) and Read = '1' then --
ReadIDROM <= '1';
else
ReadIDROM <= '0';
end if;
if A(15 downto 8) = PortAddr then -- basic I/O port select
PortSel <= '1';
else
PortSel <= '0';
end if;
if A(15 downto 8) = DDRAddr then -- DDR register select
DDRSel <= '1';
else
DDRSel <= '0';
end if;
if A(15 downto 8) = AltDataSrcAddr then -- Alt data source register select
AltDataSrcSel <= '1';
else
AltDataSrcSel <= '0';
end if;
if A(15 downto 8) = OpenDrainModeAddr then -- OpenDrain register select
OpendrainModeSel <= '1';
else
OpenDrainModeSel <= '0';
end if;
if A(15 downto 8) = OutputInvAddr then -- IO invert register select
OutputInvSel <= '1';
else
OutputInvSel <= '0';
end if;
if A(15 downto 8) = StepGenRateAddr then -- stepgen rate register select
StepGenRateSel <= '1';
else
StepGenRateSel <= '0';
end if;
if A(15 downto 8) = StepGenAccumAddr then -- stepgen Accumumlator low select
StepGenAccumSel <= '1';
else
StepGenAccumSel <= '0';
end if;
if A(15 downto 8) = StepGenModeAddr then -- stepgen mode register select
StepGenModeSel <= '1';
else
StepGenModeSel <= '0';
end if;
if A(15 downto 8) = StepGenDSUTimeAddr then -- stepgen Dir setup time register select
StepGenDSUTimeSel <= '1';
else
StepGenDSUTimeSel <= '0';
end if;
if A(15 downto 8) =StepGenDHLDTimeAddr then -- stepgen Dir hold time register select
StepGenDHLDTimeSel <= '1';
else
StepGenDHLDTimeSel <= '0';
end if;
if A(15 downto 8) = StepGenPulseATimeAddr then -- stepgen pulse width register select
StepGenPulseATimeSel <= '1';
else
StepGenPulseATimeSel <= '0';
end if;
if A(15 downto 8) = StepGenPulseITimeAddr then -- stepgen pulse width register select
StepGenPulseITimeSel <= '1';
else
StepGenPulseITimeSel <= '0';
end if;
if A(15 downto 8) = StepGenTableAddr then -- stepgen pulse width register select
StepGenTableSel <= '1';
else
StepGenTableSel <= '0';
end if;
if A(15 downto 8) = StepGenTableMaxAddr then -- stepgen pulse width register select
StepGenTableMaxSel <= '1';
else
StepGenTableMaxSel <= '0';
end if;
if A(15 downto 8) = QCounterAddr then -- QCounter select
QCounterSel <= '1';
else
QCounterSel <= '0';
end if;
if A(15 downto 8) = QCounterCCRAddr then -- QCounter CCR register select
QCounterCCRSel <= '1';
else
QCounterCCRSel <= '0';
end if;
if A(15 downto 8) = MuxedQCounterAddr then -- QCounter select
MuxedQCounterSel <= '1';
else
MuxedQCounterSel <= '0';
end if;
if A(15 downto 8) = MuxedQCounterCCRAddr then -- QCounter CCR register select
MuxedQCounterCCRSel <= '1';
else
MuxedQCounterCCRSel <= '0';
end if;
if A(15 downto 8) = PWMValAddr then -- PWMVal select
PWMValSel <= '1';
else
PWMValSel <= '0';
end if;
if A(15 downto 8) = PWMCRAddr then -- PWM mode register select
PWMCRSel <= '1';
else
PWMCRSel <= '0';
end if;
if A(15 downto 8) = SPIDataAddr then -- SPI data register select
SPIDataSel <= '1';
else
SPIDataSel <= '0';
end if;
if A(15 downto 8) = SPIBitCountAddr then -- SPI bit count register select
SPIBitCountSel <= '1';
else
SPIBitCountSel <= '0';
end if;
if A(15 downto 8) = SPIBitrateAddr then -- SPI bit rate register select
SPIBitrateSel <= '1';
else
SPIBitrateSel <= '0';
end if;
if A(15 downto 8) = SSSIDataAddr then -- SSSI data register select
SSSIDataSel <= '1';
else
SSSIDataSel <= '0';
end if;
if A(15 downto 8) = SSSIBitCountAddr then -- SSSI bit count register select
SSSIBitCountSel <= '1';
else
SSSIBitCountSel <= '0';
end if;
if A(15 downto 8) = SSSIBitrateAddr then -- SSSI bit rate register select
SSSIBitrateSel <= '1';
else
SSSIBitrateSel <= '0';
end if;
if A(15 downto 8) = BSPIDataAddr then -- BSPI data register select
BSPIDataSel <= '1';
else
BSPIDataSel <= '0';
end if;
if A(15 downto 8) = BSPIFIFOCountAddr then -- BSPI FIFO count register select
BSPIFIFOCountSel <= '1';
else
BSPIFIFOCountSel <= '0';
end if;
if A(15 downto 8) = BSPIDescriptorAddr then -- BSPI channel descriptor register select
BSPIDescriptorSel <= '1';
else
BSPIDescriptorSel <= '0';
end if;
if A(15 downto 8) = DBSPIDataAddr then -- DBSPI data register select
DBSPIDataSel <= '1';
else
DBSPIDataSel <= '0';
end if;
if A(15 downto 8) = DBSPIFIFOCountAddr then -- DBSPI FIFO count register select
DBSPIFIFOCountSel <= '1';
else
DBSPIFIFOCountSel <= '0';
end if;
if A(15 downto 8) = DBSPIDescriptorAddr then -- DBSPI channel descriptor register select
DBSPIDescriptorSel <= '1';
else
DBSPIDescriptorSel <= '0';
end if;
if A(15 downto 8) = UARTTDataAddr then -- UART TX data register select
UARTTDataSel <= '1';
else
UARTTDataSel <= '0';
end if;
if A(15 downto 8) = UARTTFIFOCountAddr then -- UART TX FIFO count register select
UARTTFIFOCountSel <= '1';
else
UARTTFIFOCountSel <= '0';
end if;
if A(15 downto 8) = UARTTBitrateAddr then -- UART TX bit rate register select
UARTTBitrateSel <= '1';
else
UARTTBitrateSel <= '0';
end if;
if A(15 downto 8) = UARTTModeRegAddr then -- UART TX bit mode register select
UARTTModeRegSel <= '1';
else
UARTTModeRegSel <= '0';
end if;
if A(15 downto 8) = UARTRDataAddr then -- UART RX data register select
UARTRDataSel <= '1';
else
UARTRDataSel <= '0';
end if;
if A(15 downto 8) = UARTRFIFOCountAddr then -- UART RX FIFO count register select
UARTRFIFOCountSel <= '1';
else
UARTRFIFOCountSel <= '0';
end if;
if A(15 downto 8) = UARTRBitrateAddr then -- UART RX bit rate register select
UARTRBitrateSel <= '1';
else
UARTRBitrateSel <= '0';
end if;
if A(15 downto 8) = UARTRModeRegAddr then -- UART RX status register select
UARTRModeRegSel <= '1';
else
UARTRModeRegSel <= '0';
end if;
if A(15 downto 8) = ReadIDAddr and Read = '1' then --
ReadID <= '1';
else
ReadID <= '0';
end if;
if A(15 downto 8) = WatchdogTimeAddr and Read = '1' then --
ReadWDTime <= '1';
else
ReadWDTime <= '0';
end if;
if A(15 downto 8) = WatchdogTimeAddr and Write = '1' then --
LoadWDTime <= '1';
else
LoadWDTime <= '0';
end if;
if A(15 downto 8) = WatchdogStatusAddr and Read = '1' then --
ReadWDStatus <= '1';
else
ReadWDStatus <= '0';
end if;
if A(15 downto 8) = WatchdogStatusAddr and Write = '1' then --
LoadWDStatus <= '1';
else
LoadWDStatus <= '0';
end if;
if A(15 downto 8) = WatchdogCookieAddr and Write = '1' then --
WDCookie <= '1';
else
WDCookie <= '0';
end if;
if A(15 downto 8) = IRQDivAddr and Write = '1' then --
LoadIRQDiv <= '1';
else
LoadIRQDiv <= '0';
end if;
if A(15 downto 8) = IRQDivAddr and Read = '1' then --
ReadIRQDiv <= '1';
else
ReadIRQDiv <= '0';
end if;
if A(15 downto 8) = IRQStatusAddr and Write = '1' then --
LoadIRQStatus <= '1';
else
LoadIRQStatus <= '0';
end if;
if A(15 downto 8) = IRQStatusAddr and Read = '1' then --
ReadIrqStatus <= '1';
else
ReadIrqStatus <= '0';
end if;
if A(15 downto 8) = ClearIRQAddr and Write = '1' then --
ClearIRQ <= '1';
else
ClearIRQ <= '0';
end if;
if A(15 downto 8) = StepGenBasicRateAddr and Write = '1' then --
LoadStepGenBasicRate <= '1';
else
LoadStepGenBasicRate <= '0';
end if;
if A(15 downto 8) = StepGenBasicRateAddr and Read = '1' then --
ReadStepGenBasicRate <= '1';
else
ReadStepGenBasicRate <= '0';
end if;
if A(15 downto 8) = TSDivAddr and Write = '1' then --
LoadTSDiv <= '1';
else
LoadTSDiv <= '0';
end if;
if A(15 downto 8) = TSDivAddr and Read = '1' then --
ReadTSDiv <= '1';
else
ReadTSDiv <= '0';
end if;
if A(15 downto 8) = TSAddr and Read = '1' then --
ReadTS <= '1';
else
ReadTS <= '0';
end if;
if A(15 downto 8) = QCRateAddr and Write = '1' then --
LoadQCountRate <= '1';
else
LoadQCountRate <= '0';
end if;
if A(15 downto 8) = MuxedTSDivAddr and Write = '1' then --
LoadMuxedTSDiv <= '1';
else
LoadMuxedTSDiv <= '0';
end if;
if A(15 downto 8) = MuxedTSDivAddr and Read = '1' then --
ReadMuxedTSDiv <= '1';
else
ReadMuxedTSDiv <= '0';
end if;
if A(15 downto 8) = MuxedTSAddr and Read = '1' then --
ReadMuxedTS <= '1';
else
ReadMuxedTS <= '0';
end if;
if A(15 downto 8) = MuxedQCRateAddr and Write = '1' then --
LoadMuxedQCountRate <= '1';
else
LoadMuxedQCountRate <= '0';
end if;
if A(15 downto 8) = PWMRateAddr and Write = '1' then --
LoadPWMRate <= '1';
else
LoadPWMRate <= '0';
end if;
if A(15 downto 8) = PDMRateAddr and Write = '1' then --
LoadPDMRate <= '1';
else
LoadPDMRate <= '0';
end if;
if A(15 downto 8) = PWMEnasAddr and Write = '1' then --
LoadPWMEnas <= '1';
else
LoadPWMEnas <= '0';
end if;
if A(15 downto 8) = PWMEnasAddr and Read = '1' then --
ReadPWMEnas <= '1';
else
ReadPWMEnas <= '0';
end if;
if A(15 downto 8) = SSSIGlobalPStartAddr and Write = '1' then --
GlobalPStartSSSI <= '1';
else
GlobalPStartSSSI <= '0';
end if;
if A(15 downto 8) = IDROMWEnAddr and Write = '1' then --
LoadIDROMWEn <= '1';
else
LoadIDROMWEn <= '0';
end if;
if A(15 downto 8) = IDROMWEnAddr and Read = '1' then --
ReadIDROMWEn <= '1';
else
ReadIDROMWEn <= '0';
end if;
if A(15 downto 8) = LEDAddr and Write = '1' then --
LoadLEDs <= '1';
else
LoadLEDs <= '0';
end if;
end process;
PortDecode: process (A,Read,Write,PortSel, DDRSel, AltDataSrcSel, OpenDrainModeSel, OutputInvSel)
begin
LoadPortCMD <= OneOfNDecode(IOPorts,PortSel,Write,A(3 downto 2)); -- 4 max
ReadPortCMD <= OneOfNDecode(IOPorts,PortSel,Read,A(3 downto 2));
LoadDDRCMD <= OneOfNDecode(IOPorts,DDRSel,Write,A(3 downto 2));
ReadDDRCMD <= OneOfNDecode(IOPorts,DDRSel,Read,A(3 downto 2));
LoadAltDataSrcCMD <= OneOfNDecode(IOPorts,AltDataSrcSel,Write,A(3 downto 2));
LoadOpenDrainModeCMD <= OneOfNDecode(IOPorts,OpenDrainModeSel,Write,A(3 downto 2));
LoadOutputInvCMD <= OneOfNDecode(IOPorts,OutputInvSel,Write,A(3 downto 2));
end process PortDecode;
StepGenDecode: if (STEPGENs > 0) generate
StepGenDecodeProcess : process (A,Read,write,StepGenRateSel, StepGenAccumSel, StepGenModeSel,
StepGenDSUTimeSel, StepGenDHLDTimeSel, StepGenPulseATimeSel,
StepGenPulseITimeSel, StepGenTableSel, StepGenTableMaxSel)
begin
LoadStepGenRate <= OneOfNDecode(STEPGENs,StepGenRateSel,Write,A(6 downto 2)); -- 32 max
ReadStepGenRate <= OneOfNDecode(STEPGENs,StepGenRateSel,Read,A(6 downto 2));
LoadStepGenAccum <= OneOfNDecode(STEPGENs,StepGenAccumSel,Write,A(6 downto 2));
ReadStepGenAccum <= OneOfNDecode(STEPGENs,StepGenAccumSel,Read,A(6 downto 2));
LoadStepGenMode <= OneOfNDecode(STEPGENs,StepGenModeSel,Write,A(6 downto 2));
ReadStepGenMode <= OneOfNDecode(STEPGENs,StepGenModeSel,Read,A(6 downto 2));
LoadStepGenDSUTime <= OneOfNDecode(STEPGENs,StepGenDSUTimeSel,Write,A(6 downto 2));
ReadStepGenDSUTime <= OneOfNDecode(STEPGENs,StepGenDSUTimeSel,Read,A(6 downto 2));
LoadStepGenDHLDTime <= OneOfNDecode(STEPGENs,StepGenDHLDTimeSel,Write,A(6 downto 2));
ReadStepGenDHLDTime <= OneOfNDecode(STEPGENs,StepGenDHLDTimeSel,Read,A(6 downto 2));
LoadStepGenPulseATime <= OneOfNDecode(STEPGENs,StepGenPulseATimeSel,Write,A(6 downto 2));
ReadStepGenPulseATime <= OneOfNDecode(STEPGENs,StepGenPulseATimeSel,Read,A(6 downto 2));
LoadStepGenPulseITime <= OneOfNDecode(STEPGENs,StepGenPulseITimeSel,Write,A(6 downto 2));
ReadStepGenPulseITime <= OneOfNDecode(STEPGENs,StepGenPulseITimeSel,Read,A(6 downto 2));
LoadStepGenTable <= OneOfNDecode(STEPGENs,StepGenTableSel,Write,A(6 downto 2));
ReadStepGenTable <= OneOfNDecode(STEPGENs,StepGenTableSel,Read,A(6 downto 2));
LoadStepGenTableMax <= OneOfNDecode(STEPGENs,StepGenTableMaxSel,Write,A(6 downto 2));
ReadStepGenTableMax <= OneOfNDecode(STEPGENs,StepGenTableMaxSel,Read,A(6 downto 2));
end process StepGenDecodeProcess;
end generate;
QCounterDecode: if (QCounters > 0) generate
QCounterDecodeProcess : process (A,Read,write,QCounterSel, QCounterCCRSel)
begin
LoadQCounter <= OneOfNDecode(QCounters,QCounterSel,Write,A(6 downto 2)); -- 32 max
ReadQCounter <= OneOfNDecode(QCounters,QCounterSel,Read,A(6 downto 2));
LoadQCounterCCR <= OneOfNDecode(QCounters,QCounterCCRSel,Write,A(6 downto 2));
ReadQCounterCCR <= OneOfNDecode(QCounters,QCounterCCRSel,Read,A(6 downto 2));
end process QCounterDecodeProcess;
end generate;
MuxedQCounterDecode: if (MuxedQcounters > 0) generate
MuxedQCounterDecodeProcess : process (A,Read,write,MuxedQCounterSel, MuxedQCounterCCRSel)
begin
LoadMuxedQCounter <= OneOfNDecode(MuxedQCounters,MuxedQCounterSel,Write,A(6 downto 2)); -- 32 max
ReadMuxedQCounter <= OneOfNDecode(MuxedQCounters,MuxedQCounterSel,Read,A(6 downto 2));
LoadMuxedQCounterCCR <= OneOfNDecode(MuxedQCounters,MuxedQCounterCCRSel,Write,A(6 downto 2));
ReadMuxedQCounterCCR <= OneOfNDecode(MuxedQCounters,MuxedQCounterCCRSel,Read,A(6 downto 2));
end process MuxedQCounterDecodeProcess;
end generate;
PWMDecode: if (PWMGENs > 0) generate
PWMDecodeProcess : process (A,Read,write,PWMValSel, PWMCRSel)
begin
LoadPWMVal <= OneOfNDecode(PWMGENs,PWMValSel,Write,A(6 downto 2)); -- 32 max
LoadPWMCR <= OneOfNDecode(PWMGENs, PWMCRSel,Write,A(6 downto 2));
end process PWMDecodeProcess;
end generate;
SPIDecode: if (SPIs > 0) generate
SPIDecodeProcess : process (A,Read,write,SPIDataSel,SPIBitCountSel,SPIBitRateSel)
begin
LoadSPIData <= OneOfNDecode(SPIs,SPIDataSel,Write,A(5 downto 2)); -- 16 max
ReadSPIData <= OneOfNDecode(SPIs,SPIDataSel,Read,A(5 downto 2));
LoadSPIBitCount <= OneOfNDecode(SPIs,SPIBitCountSel,Write,A(5 downto 2));
ReadSPIBitCount <= OneOfNDecode(SPIs,SPIBitCountSel,Read,A(5 downto 2));
LoadSPIBitRate <= OneOfNDecode(SPIs,SPIBitRateSel,Write,A(5 downto 2));
ReadSPIBitRate <= OneOfNDecode(SPIs,SPIBitRateSel,Read,A(5 downto 2));
end process SPIDecodeProcess;
end generate;
BSPIDecode: if (BSPIs > 0) generate
BSPIDecodeProcess : process (A,Read,write,BSPIDataSel,BSPIFIFOCountSel,BSPIDescriptorSel)
begin
LoadBSPIData <= OneOfNDecode(BSPIs,BSPIDataSel,Write,A(7 downto 6)); -- 4 max
ReadBSPIData <= OneOfNDecode(BSPIs,BSPIDataSel,Read,A(7 downto 6));
LoadBSPIDescriptor<= OneOfNDecode(BSPIs,BSPIDescriptorSel,Write,A(5 downto 2));
ReadBSPIFIFOCOunt <= OneOfNDecode(BSPIs,BSPIFIFOCountSel,Read,A(5 downto 2));
ClearBSPIFIFO <= OneOfNDecode(BSPIs,BSPIFIFOCountSel,Write,A(5 downto 2));
end process BSPIDecodeProcess;
end generate;
DBSPIDecode: if (DBSPIs > 0) generate
DBSPIDecodeProcess : process (A,Read,write,DBSPIDataSel,DBSPIFIFOCountSel,DBSPIDescriptorSel)
begin
LoadDBSPIData <= OneOfNDecode(DBSPIs,DBSPIDataSel,Write,A(7 downto 6)); -- 4 max
ReadDBSPIData <= OneOfNDecode(DBSPIs,DBSPIDataSel,Read,A(7 downto 6));
LoadDBSPIDescriptor<= OneOfNDecode(DBSPIs,DBSPIDescriptorSel,Write,A(5 downto 2));
ReadDBSPIFIFOCOunt <= OneOfNDecode(DBSPIs,DBSPIFIFOCountSel,Read,A(5 downto 2));
ClearDBSPIFIFO <= OneOfNDecode(DBSPIs,DBSPIFIFOCountSel,Write,A(5 downto 2));
end process DBSPIDecodeProcess;
end generate;
SSSIDecode: if (SSSIs > 0) generate
SSSIDecodeProcess : process (A,Read,write,SSSIDataSel,SSSIBitCountSel,SSSIBitRateSel)
begin
LoadSSSIData <= OneOfNDecode(SSSIs,SSSIDataSel,Write,A(5 downto 2));
ReadSSSIData <= OneOfNDecode(SSSIs,SSSIDataSel,Read,A(5 downto 2));
LoadSSSIBitCount <= OneOfNDecode(SSSIs,SSSIBitCountSel,Write,A(5 downto 2));
ReadSSSIBitCount <= OneOfNDecode(SSSIs,SSSIBitCountSel,Read,A(5 downto 2));
LoadSSSIBitRate <= OneOfNDecode(SSSIs,SSSIBitRateSel,Write,A(5 downto 2));
ReadSSSIBitRate <= OneOfNDecode(SSSIs,SSSIBitRateSel,Read,A(5 downto 2));
end process SSSIDecodeProcess;
end generate;
UARTDecode: if (UARTs > 0) generate
UARTDecodeProcess : process (A,Read,write,UARTTDataSel,UARTTBitRateSel,UARTTModeRegSel,UARTTFIFOCountSel,
UARTRDataSel,UARTRBitRateSel,UARTRFIFOCountSel,UARTRModeRegSel)
begin
LoadUARTTData <= OneOfNDecode(UARTs,UARTTDataSel,Write,A(6 downto 4));
LoadUARTTBitRate <= OneOfNDecode(UARTs,UARTTBitRateSel,Write,A(4 downto 2));
ReadUARTTBitrate <= OneOfNDecode(UARTs,UARTTBitRateSel,Read,A(4 downto 2));
LoadUARTTModeReg <= OneOfNDecode(UARTs,UARTTModeRegSel,Write,A(4 downto 2));
ReadUARTTModeReg <= OneOfNDecode(UARTs,UARTTModeRegSel,Read,A(4 downto 2));
ClearUARTTFIFO <= OneOfNDecode(UARTs,UARTTFIFOCountSel,Write,A(4 downto 2));
ReadUARTTFIFOCount <= OneOfNDecode(UARTs,UARTTFIFOCountSel,Read,A(4 downto 2));
LoadUARTRData <= OneOfNDecode(UARTs,UARTRDataSel,Read,A(6 downto 4));
LoadUARTRBitRate <= OneOfNDecode(UARTs,UARTRBitRateSel,Write,A(4 downto 2));
ReadUARTRBitrate <= OneOfNDecode(UARTs,UARTRBitRateSel,Read,A(4 downto 2));
ClearUARTRFIFO <= OneOfNDecode(UARTs,UARTRFIFOCountSel,Write,A(4 downto 2));
ReadUARTRFIFOCount <= OneOfNDecode(UARTs,UARTRFIFOCountSel,Read,A(4 downto 2));
LoadUARTRModeReg <= OneOfNDecode(UARTs,UARTRModeRegSel,Write,A(4 downto 2));
ReadUARTRModeReg <= OneOfNDecode(UARTs,UARTRModeRegSel,Read,A(4 downto 2));
end process UARTDecodeProcess;
end generate;
dotieupint: if not UseIRQLogic generate
tieupint : process(clklow)
begin
INT <= '1';
end process;
end generate;
end dataflow;
| lgpl-2.1 | ecd88b1bcf3c21b1983a049c856fda4f | 0.678272 | 2.95573 | false | false | false | false |
EliasLuiz/TCC | Teste/MemoTableTOutput.vhd | 1 | 1,256 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
use work.Constants.all;
use work.DefTypes.all;
ENTITY MemoTableTOutput IS
--ENTITY TraceMemory IS
PORT
(
Clock : IN STD_LOGIC := '1';
WAddress : IN STD_LOGIC_VECTOR (MemoTableTWayAddressLenght-1 DOWNTO 0);
WData : IN MemoTableTOutputBus;
WEnable : IN STD_LOGIC := '0';
RAddress : IN STD_LOGIC_VECTOR (MemoTableTWayAddressLenght-1 DOWNTO 0);
RData : OUT MemoTableTOutputBus
);
END MemoTableTOutput;
--END TraceMemory;
ARCHITECTURE SYN OF MemoTableTOutput IS
--ARCHITECTURE SYN OF TraceMemory IS
COMPONENT MemoTableTOutputWay
PORT (
Clock : IN STD_LOGIC := '1';
WAddress : IN STD_LOGIC_VECTOR (MemoTableTWayAddressLenght-1 DOWNTO 0);
WData : IN MemoTableTOutputEntry;
WEnable : IN STD_LOGIC := '0';
RAddress : IN STD_LOGIC_VECTOR (MemoTableTWayAddressLenght-1 DOWNTO 0);
RData : OUT MemoTableTOutputEntry
);
END COMPONENT;
BEGIN
mem: FOR i IN 0 TO MemoTableTAssociativity-1 GENERATE
MemoTableTOutputWay_cmp : MemoTableTOutputWay
PORT MAP (
WAddress => WAddress,
Clock => Clock,
WData => WData(i),
WEnable => WEnable,
RAddress => RAddress,
RData => RData(i)
);
END GENERATE mem;
END SYN;
| gpl-3.0 | 9d01c1f513e2bdc1fbc4fc59c01ca940 | 0.710987 | 2.633124 | false | false | false | false |
ggaray/nicsim-vhd | test_nicctrl.vhd | 1 | 9,686 | -- NICSim-vhd: A VHDL-based modelling and simulation of NIC's buffers
-- Copyright (C) 2013 Godofredo R. Garay <godofredo.garay (-at-) gmail.com>
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all;
entity test_nicctrl is
end;
architecture BENCH of test_nicctrl is
component clkgen is
port (
pciclk : out bit;
nicclk : out bit;
ethclk : out bit
);
end component;
component traffgen is
port (
pktarrival : out bit;
pktsize : out integer;
ethclk : in bit
);
end component;
component buffmngr is
port (
pktarrival : in bit;
pktsize : in integer;
transfer_start_req : out bit;
transfer_end : in bit;
ethclk : in bit;
pciclk : in bit;
pktreceived : out bit;
payload_size_in_data_blocks : out integer;
buffer_fill_level_in_bytes : out integer;
buffer_fill_level_in_data_units : out integer;
max_buffer_fill_level : out integer;
dropped_packets_count : out integer;
buffer_size_in_data_units : out integer
);
end component;
component nicctrl is
port (
transfer_start_req : in bit;
transfer_end : out bit;
req : out bit;
gnt : in bit;
frame : inout std_logic;
irdy : out bit;
trdy : in bit;
AD : out bit;
payload_size_in_data_blocks : in integer;
payload_transfer_req : out bit;
descriptor_transfer_req : out bit;
payload_transfer_end : in bit;
descriptor_transfer_end : in bit;
payload_transfer_aborted : in bit;
resume_aborted_payload_transfer : out bit;
descriptor_transfer_aborted : in bit;
resume_aborted_descriptor_transfer : out bit;
acq_latency_cycles_counter_out : out integer;
nic_proc_latency_cycles_counter_out : out integer;
nicclk : in bit;
pciclk : in bit
);
end component;
component dmactrl is
port (
payload_transfer_req : in bit;
descriptor_transfer_req : in bit;
payload_transfer_end : out bit;
descriptor_transfer_end : out bit;
payload_transfer_aborted : out bit;
descriptor_transfer_aborted : out bit;
resume_aborted_payload_transfer : in bit;
resume_aborted_descriptor_transfer : in bit;
irdy : in bit;
trdy : in bit;
gnt : in bit;
payload_size_in_data_blocks : in integer;
dma_cycles_counter_out : out integer;
burst_cycles_counter_out : out integer;
pciclk : in bit
);
end component;
component arbiter is
port (
req : in bit;
gnt : out bit;
-- burst_cycles_counter_out : out integer;
arb_latency_cycles_counter_out : out integer;
pciclk : in bit
);
end component;
component memsub is
port (
irdy : in bit;
trdy : out bit;
frame : inout std_logic;
AD : in bit;
target_latency_cycles_counter_out : out integer; -- Always is 1 cycle
pciclk : in bit
);
end component;
component othermaster is
port (
frame : inout std_logic;
pciclk : in bit
);
end component;
component statsgen is
port (
pciclk : in bit;
ethclk : in bit;
pktreceived : in bit;
pktsize : in integer;
transfer_start_req : in bit;
--payload_transfer_req : in bit;
--payload_transfer_aborted : in bit;
--resume_aborted_payload_transfer : in bit;
--descriptor_transfer_req : in bit;
--descriptor_transfer_aborted : in bit;
--resume_aborted_descriptor_transfer : in bit;
transfer_end : in bit;
buffer_fill_level_in_bytes : in integer;
buffer_fill_level_in_data_units : in integer;
max_buffer_fill_level : in integer;
dropped_packets_count : in integer;
nic_proc_latency_cycles_counter_out : in integer;
acq_latency_cycles_counter_out : in integer;
arb_latency_cycles_counter_out : in integer;
target_latency_cycles_counter_out : in integer;
burst_cycles_counter_out : in integer;
dma_cycles_counter_out : in integer;
clock_counter_out : out integer
);
end component;
signal sig_pciclk, sig_nicclk, sig_ethclk : bit;
signal sig_frame : std_logic;
signal sig_pktarrival, sig_transfer_start_req, sig_transfer_end, sig_req, sig_gnt, sig_irdy, sig_payload_transfer_req, sig_descriptor_transfer_req, sig_payload_transfer_end, sig_descriptor_transfer_end, sig_payload_transfer_aborted, sig_descriptor_transfer_aborted, sig_resume_aborted_payload_transfer, sig_resume_aborted_descriptor_transfer, sig_trdy, sig_AD, sig_pktreceived : bit;
signal sig_payload_size_in_data_blocks, sig_dma_cycles_counter_out, sig_buffer_fill_level_in_bytes, sig_buffer_fill_level_in_data_units, sig_burst_cycles_counter_out, sig_arb_latency_cycles_counter_out, sig_pktsize, sig_acq_latency_cycles_counter_out, sig_nic_proc_latency_cycles_counter_out, sig_target_latency_cycles_counter_out, sig_clock_counter_out, sig_max_buffer_fill_level, sig_dropped_packets_count, sig_buffer_size_in_data_units : integer;
begin
-- Components Port Map
clkgen_comp: clkgen port map (pciclk => sig_pciclk, nicclk => sig_nicclk, ethclk => sig_ethclk);
traffgen_comp : traffgen port map (pktarrival => sig_pktarrival, pktsize => sig_pktsize, ethclk => sig_ethclk);
buffmngr_comp: buffmngr port map (pktarrival => sig_pktarrival, pktsize => sig_pktsize, transfer_start_req => sig_transfer_start_req, transfer_end => sig_transfer_end, ethclk => sig_ethclk, pciclk => sig_pciclk, pktreceived => sig_pktreceived, payload_size_in_data_blocks => sig_payload_size_in_data_blocks, buffer_fill_level_in_bytes => sig_buffer_fill_level_in_bytes, buffer_fill_level_in_data_units => sig_buffer_fill_level_in_data_units, max_buffer_fill_level => sig_max_buffer_fill_level, dropped_packets_count => sig_dropped_packets_count, buffer_size_in_data_units => sig_buffer_size_in_data_units);
nicctrl_comp: nicctrl port map (transfer_start_req => sig_transfer_start_req, transfer_end => sig_transfer_end, req => sig_req, gnt => sig_gnt, frame => sig_frame, irdy => sig_irdy, trdy => sig_trdy, AD => sig_AD, payload_size_in_data_blocks => sig_payload_size_in_data_blocks, payload_transfer_req => sig_payload_transfer_req, descriptor_transfer_req => sig_descriptor_transfer_req, payload_transfer_end => sig_payload_transfer_end, descriptor_transfer_end => sig_descriptor_transfer_end, payload_transfer_aborted => sig_payload_transfer_aborted, resume_aborted_payload_transfer => sig_resume_aborted_payload_transfer, descriptor_transfer_aborted => sig_descriptor_transfer_aborted, resume_aborted_descriptor_transfer => sig_resume_aborted_descriptor_transfer, acq_latency_cycles_counter_out => sig_acq_latency_cycles_counter_out, nic_proc_latency_cycles_counter_out => sig_nic_proc_latency_cycles_counter_out, nicclk => sig_nicclk, pciclk => sig_pciclk);
dmactrl_comp: dmactrl port map (payload_transfer_req => sig_payload_transfer_req, descriptor_transfer_req => sig_descriptor_transfer_req, payload_transfer_end => sig_payload_transfer_end, descriptor_transfer_end => sig_descriptor_transfer_end, payload_transfer_aborted => sig_payload_transfer_aborted, descriptor_transfer_aborted => sig_descriptor_transfer_aborted, resume_aborted_payload_transfer => sig_resume_aborted_payload_transfer, resume_aborted_descriptor_transfer => sig_resume_aborted_descriptor_transfer, irdy => sig_irdy, trdy => sig_trdy, gnt => sig_gnt, payload_size_in_data_blocks => sig_payload_size_in_data_blocks, dma_cycles_counter_out => sig_dma_cycles_counter_out, burst_cycles_counter_out => sig_burst_cycles_counter_out, pciclk => sig_pciclk);
arbiter_comp: arbiter port map (req => sig_req, gnt => sig_gnt, arb_latency_cycles_counter_out => sig_arb_latency_cycles_counter_out, pciclk => sig_pciclk);
memsub_comp: memsub port map (irdy => sig_irdy, trdy => sig_trdy, frame => sig_frame, AD => sig_AD, target_latency_cycles_counter_out => sig_target_latency_cycles_counter_out, pciclk => sig_pciclk);
statsgen_comp: statsgen port map (pciclk => sig_pciclk, ethclk => sig_ethclk, pktreceived => sig_pktreceived, pktsize => sig_pktsize,transfer_start_req => sig_transfer_start_req, transfer_end => sig_transfer_end, buffer_fill_level_in_bytes => sig_buffer_fill_level_in_bytes, buffer_fill_level_in_data_units => sig_buffer_fill_level_in_data_units, max_buffer_fill_level => sig_max_buffer_fill_level, dropped_packets_count => sig_dropped_packets_count, nic_proc_latency_cycles_counter_out => sig_nic_proc_latency_cycles_counter_out, acq_latency_cycles_counter_out => sig_acq_latency_cycles_counter_out, arb_latency_cycles_counter_out => sig_arb_latency_cycles_counter_out, target_latency_cycles_counter_out => sig_target_latency_cycles_counter_out, burst_cycles_counter_out => sig_burst_cycles_counter_out, dma_cycles_counter_out => sig_dma_cycles_counter_out, clock_counter_out => sig_clock_counter_out);
othermaster_comp: othermaster port map (frame => sig_frame, pciclk => sig_pciclk);
end BENCH;
| gpl-3.0 | 223d74f07c45441858c1186e7e0275e2 | 0.69523 | 3.005275 | false | false | false | false |
hoglet67/CoPro6502 | src/LX9Co_CoProPDP11.vhd | 1 | 14,159 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity LX9CoProPDP11 is
port (
-- GOP Signals
fastclk : in std_logic;
test : inout std_logic_vector(8 downto 1);
sw : in std_logic_vector(3 downto 0);
-- Tube signals
h_phi2 : in std_logic;
h_addr : in std_logic_vector(2 downto 0);
h_data : inout std_logic_vector(7 downto 0);
h_rdnw : in std_logic;
h_cs_b : in std_logic;
h_rst_b : in std_logic;
h_irq_b : inout std_logic;
-- Ram Signals
ram_ub_b : out std_logic;
ram_lb_b : out std_logic;
ram_cs : out std_logic;
ram_oe : out std_logic;
ram_wr : out std_logic;
ram_addr : out std_logic_vector (18 downto 0);
ram_data : inout std_logic_vector (7 downto 0)
);
end LX9CoProPDP11;
architecture BEHAVIORAL of LX9CoProPDP11 is
-------------------------------------------------
-- clock and reset signals
-------------------------------------------------
signal clk_cpu : std_logic;
signal clk_ram : std_logic;
signal clk_tube : std_logic;
signal RSTn : std_logic;
signal RST_sync : std_logic;
signal clken_counter : std_logic_vector (3 downto 0);
signal reset_counter : std_logic_vector (8 downto 0);
-------------------------------------------------
-- parasite signals
-------------------------------------------------
signal p_cs_b : std_logic;
signal p_data_out : std_logic_vector (7 downto 0);
-------------------------------------------------
-- ram/rom signals
-------------------------------------------------
signal ram_cs_b : std_logic;
signal ram_wr_lo : std_logic;
signal ram_wr_hi : std_logic;
signal rom_cs_b : std_logic;
signal rom_data_out : std_logic_vector (15 downto 0);
signal ram_data_in : std_logic_vector (15 downto 0);
signal ram_data_out : std_logic_vector (15 downto 0);
-------------------------------------------------
-- cpu signals
-------------------------------------------------
signal cpu_rd : std_logic;
signal cpu_wr : std_logic;
signal cpu_dw8 : std_logic;
signal cpu_addr : std_logic_vector (15 downto 0);
signal cpu_addr2 : std_logic_vector (15 downto 0);
signal cpu_din : std_logic_vector (15 downto 0);
signal cpu_dout : std_logic_vector (15 downto 0);
signal cpu_IRQ_n : std_logic;
signal cpu_NMI_n : std_logic;
signal cpu_IRQ_n1 : std_logic;
signal cpu_NMI_n1 : std_logic;
signal cpu_IRQ_n2 : std_logic;
signal cpu_NMI_n2 : std_logic;
signal cpu_IRQ_req : std_logic;
signal cpu_NMI_req : std_logic;
signal cpu_IRQ_ack : std_logic;
signal cpu_NMI_ack : std_logic;
signal cpu_PSW : std_logic_vector (15 downto 0);
signal cpu_cp : std_logic;
signal ifetch : std_logic;
signal bg6 : std_logic;
begin
---------------------------------------------------------------------
-- instantiated components
---------------------------------------------------------------------
inst_ICAP_config : entity work.ICAP_config port map (
fastclk => fastclk,
sw_in => sw,
sw_out => open,
h_addr => h_addr,
h_cs_b => h_cs_b,
h_data => h_data,
h_phi2 => h_phi2,
h_rdnw => h_rdnw,
h_rst_b => h_rst_b
);
inst_tuberom : entity work.tuberom_pdp11 port map (
CLK => clk_ram,
ADDR => cpu_addr(10 downto 1),
DATA => rom_data_out
);
inst_pdp11 : entity work.pdp2011_cpu port map (
clk => clk_cpu, -- input clock
reset => RST_sync, -- reset cpu, also causes init signal to devices on the bus to be asserted
addr_v => cpu_addr, -- the virtual address that the cpu drives out to the bus for the current read or write
datain => cpu_din, -- when doing a read, the data input to the cpu
dataout => cpu_dout, -- when doing a write, the data output from the cpu
wr => cpu_wr, -- if '1', the cpu is doing a write to the bus and drives addr_v and dataout
rd => cpu_rd, -- if '1', the cpu is doing a read from the bus, drives addr_v and reads datain
dw8 => cpu_dw8, -- if '1', the read or write initiated by the cpu is 8 bits wide
cp => cpu_cp, -- if '1', the read or write should use the previous cpu mode
ifetch => ifetch, -- if '1', this read is for an instruction fetch
id => open, -- if '1', the read or write should use data space
init => open, -- if '1', the devices on the bus should reset
iwait => open, -- if '1', the cpu is waiting for an interrupt
br7 => cpu_NMI_req, -- interrupt request, 7
bg7 => cpu_NMI_ack, -- interrupt grant, 7
int_vector7 => "0" & x"80", -- interrupt vector, 7
br6 => cpu_IRQ_req, -- interrupt request, 6
bg6 => cpu_IRQ_ack, -- interrupt grant, 6
int_vector6 => "0" & x"84", -- interrupt vector, 6
br5 => '0', -- interrupt request, 5
bg5 => open, -- interrupt grant, 5
int_vector5 => (others => '0'), -- interrupt vector, 5
br4 => '0', -- interrupt request, 4
bg4 => open, -- interrupt grant, 4
int_vector4 => (others => '0'), -- interrupt vector, 4
mmutrap => '0', -- if '1', the mmu requests a trap to be serviced after the current instruction completes
ack_mmutrap => open, -- if '1', the mmu trap request is being acknowledged
mmuabort => '0', -- if '1', the mmu requests that the current instruction is aborted because of a mmu fault
ack_mmuabort => open, -- if '1', the mmu abort request is being acknowledged
npr => '0', -- non-processor request
npg => open, -- non-processor grant
nxmabort => '0', -- nxm abort - a memory access cycle by the cpu refers to an address that does not exist
oddabort => '0', -- odd abort - a memory access cycle by the cpu is for a full word, but uses an odd address
illhalt => open, -- a halt instruction was not executed because it was illegal in the current mode; for use in the cer cpu error register
ysv => open, -- a yellow stack trap is in progress - for use in the cer cpu error register
rsv => open, -- a red stack trap is in progress - for use in the cer cpu error register
cpu_stack_limit => x"0100", -- the cpu stack limit control register value
cpu_kmillhalt => '0', -- the control register setting for kernel mode illegal halt
sr0_ic => open, -- sr0/mmr0 instruction complete flag
sr1 => open, -- sr1/mmr1, address of the current instruction
sr2 => open, -- sr2, register autoincrement/autodecrement information for instruction restart
dstfreference => open, -- if '1', the destination reference is the final reference for this addressing mode
sr3csmenable => '0', -- if '1', the enable csm instruction flag in sr3/mmr3 is set
psw_in => x"0000", -- psw input from the control register address @ 177776
psw_in_we_even => '0', -- psw input from the control register address @ 177776, write enable for the even address part
psw_in_we_odd => '0', -- psw input from the control register address @ 177776, write enable for the odd address part
psw_out => cpu_PSW, -- psw output, current psw that the cpu uses
pir_in => x"0000", -- pirq value input from the control register
modelcode => 40, -- cpu model code
init_r7 => x"f800", -- start address after reset = o'173000' = m9312 hi rom
init_psw => x"00a0" -- initial psw sets interrupt priority 5, allowing BR6 and BR7
);
inst_tube: entity work.tube port map (
h_addr => h_addr,
h_cs_b => h_cs_b,
h_data => h_data,
h_phi2 => h_phi2,
h_rdnw => h_rdnw,
h_rst_b => h_rst_b,
h_irq_b => h_irq_b,
p_addr => cpu_addr(3 downto 1),
p_cs_b => p_cs_b,
p_data_in => cpu_dout(7 downto 0),
p_data_out => p_data_out,
p_rdnw => not cpu_wr,
p_phi2 => clk_tube,
p_rst_b => RSTn,
p_nmi_b => cpu_NMI_n,
p_irq_b => cpu_IRQ_n
);
Inst_RAM_lo: entity work.RAM_32K PORT MAP(
clk => clk_ram,
we_uP => ram_wr_lo,
ce => '1',
addr_uP => cpu_addr2(15 downto 1),
D_uP => ram_data_in(7 downto 0),
Q_uP => ram_data_out(7 downto 0)
);
Inst_RAM_hi: entity work.RAM_32K PORT MAP(
clk => clk_ram,
we_uP => ram_wr_hi,
ce => '1',
addr_uP => cpu_addr2(15 downto 1),
D_uP => ram_data_in(15 downto 8),
Q_uP => ram_data_out(15 downto 8)
);
-- provide a seperare page 0 for Kernel mode ("00") vs user mode ("11")
cpu_addr2 <= cpu_addr when cpu_addr >= x"0100" else
cpu_addr when cpu_PSW(15 downto 14) = "00" and cpu_cp = '0' else
cpu_addr when cpu_PSW(13 downto 12) = "00" and cpu_cp = '1' else
"11111" & cpu_addr(10 downto 0);
p_cs_b <= '0' when (cpu_rd = '1' or cpu_wr = '1') and cpu_addr(15 downto 4) = x"FFF" else '1';
rom_cs_b <= '0' when (cpu_rd = '1' or cpu_wr = '1') and p_cs_b = '1' and cpu_addr(15 downto 11) = "11111" else '1';
ram_cs_b <= '0' when (cpu_rd = '1' or cpu_wr = '1') and p_cs_b = '1' and rom_cs_b = '1' else '1';
-- TODO implement fault for non-aligned word access
ram_wr_lo <= '1' when ram_cs_b = '0' and cpu_wr = '1' and (cpu_dw8 = '0' or cpu_addr(0) = '0') else '0';
ram_wr_hi <= '1' when ram_cs_b = '0' and cpu_wr = '1' and (cpu_dw8 = '0' or cpu_addr(0) = '1') else '0';
cpu_din <=
x"ff" & p_data_out when p_cs_b = '0' else
rom_data_out when rom_cs_b = '0' and cpu_dw8 = '0' else
x"ff" & rom_data_out(7 downto 0) when rom_cs_b = '0' and cpu_dw8 = '1' and cpu_addr(0) = '0' else
x"ff" & rom_data_out(15 downto 8) when rom_cs_b = '0' and cpu_dw8 = '1' and cpu_addr(0) = '1' else
ram_data_out when ram_cs_b = '0' and cpu_dw8 = '0' else
x"ff" & ram_data_out(7 downto 0) when ram_cs_b = '0' and cpu_dw8 = '1' and cpu_addr(0) = '0' else
x"ff" & ram_data_out(15 downto 8) when ram_cs_b = '0' and cpu_dw8 = '1' and cpu_addr(0) = '1' else
x"f1f1";
ram_data_in <= x"ff" & cpu_dout(7 downto 0) when cpu_dw8 = '1' and cpu_addr(0) = '0' else
cpu_dout(7 downto 0) & x"ff" when cpu_dw8 = '1' and cpu_addr(0) = '1' else
cpu_dout;
--------------------------------------------------------
-- external Ram unused
--------------------------------------------------------
ram_ub_b <= '1';
ram_lb_b <= '1';
ram_cs <= '1';
ram_oe <= '1';
ram_wr <= '1';
ram_addr <= (others => '1');
ram_data <= (others => '1');
--------------------------------------------------------
-- test signals
--------------------------------------------------------
-- default to hi-impedence, to avoid conflicts with
-- a Raspberry Pi connected to the test connector
test <= (others => 'Z');
--------------------------------------------------------
-- clock enable generator
--------------------------------------------------------
clk_cpu <= fastclk;
clk_tube <= fastclk;
clk_ram <= not fastclk;
--------------------------------------------------------
-- power up reset
--------------------------------------------------------
reset_gen : process(clk_cpu)
begin
if rising_edge(clk_cpu) then
if (reset_counter(8) = '0') then
reset_counter <= reset_counter + 1;
end if;
RST_sync <= not (RSTn AND reset_counter(8));
end if;
end process;
--------------------------------------------------------
-- interrupt synchronization
--------------------------------------------------------
sync_gen : process(clk_cpu, RST_sync)
begin
if RST_sync = '1' then
cpu_NMI_req <= '0';
cpu_IRQ_req <= '0';
cpu_NMI_n1 <= '1';
cpu_NMI_n2 <= '1';
cpu_IRQ_n1 <= '1';
cpu_IRQ_n2 <= '1';
elsif rising_edge(clk_cpu) then
cpu_NMI_n1 <= cpu_NMI_n;
cpu_NMI_n2 <= cpu_NMI_n1;
cpu_IRQ_n1 <= cpu_IRQ_n;
cpu_IRQ_n2 <= cpu_IRQ_n1;
if (CPU_NMI_ack = '1') then
cpu_NMI_req <= '0';
elsif (CPU_NMI_n1 = '0' and CPU_NMI_n2 = '1') then
cpu_NMI_req <= '1';
end if;
if (CPU_IRQ_ack = '1') then
cpu_IRQ_req <= '0';
elsif (CPU_IRQ_n1 = '0' and CPU_IRQ_n2 = '1') then
cpu_IRQ_req <= '1';
end if;
end if;
end process;
end BEHAVIORAL;
| gpl-3.0 | 87b972837b71ef4cde2b738ca3252978 | 0.46338 | 3.647347 | false | false | false | false |
hoglet67/CoPro6502 | test/SRAM.vhd | 1 | 916 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--library UNISIM;
--use UNISIM.VComponents.all;
entity SRAM is
Port ( ADDR : in std_logic_vector(15 downto 0);
DATA : inout std_logic_vector(7 downto 0);
OE : in std_logic;
WE : in std_logic;
CS : in std_logic);
end SRAM;
architecture Behavioral of SRAM is
subtype byte is std_logic_vector( 7 downto 0 );
type mem_matrix is array (0 to 65535) of byte;
shared variable matrix:mem_matrix;
begin
read:process (CS,OE,ADDR) is
begin
if (CS ='1') OR (OE = '1') then
DATA <= "ZZZZZZZZ";
else
DATA <= matrix(conv_integer(ADDR));
end if;
end process;
write:process (CS,WE) is
begin
if (CS='0') then
if WE = '0' then
matrix (conv_integer(ADDR)):= DATA;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | 839194761ccf54845a1d43940a6a41bf | 0.616812 | 3.283154 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/maps/skew_outpad.vhd | 1 | 2,128 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: skew_outpad
-- File: skew_outpad.vhd
-- Author: Nils-Johan Wessman - Gaisler Research
-- Description: output pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity skew_outpad is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; skew : integer := 0);
port (pad : out std_ulogic; i : in std_ulogic; rst : in std_ulogic;
o : out std_ulogic);
end;
architecture rtl of skew_outpad is
signal padx, gnd, vcc : std_ulogic;
begin
gnd <= '0'; vcc <= '1';
gen0 : if has_pads(tech) = 0 generate
pad <= i
-- pragma translate_off
after 2 ns
-- pragma translate_on
when slew = 0 else i;
end generate;
xcv : if (is_unisim(tech) = 1) generate
x0 : unisim_skew_outpad generic map (level, slew, voltage, strength, skew) port map (pad, i, rst, o);
end generate;
end;
| gpl-3.0 | 20f6070fcdf86dcd02976280e7928df8 | 0.618891 | 3.962756 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/maps/alltap.vhd | 1 | 12,632 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: alltap
-- File: alltap.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: JTAG Test Access Port (TAP) Controller component declaration
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package alltap is
component tap_gen
generic (
irlen : integer range 2 to 8 := 2;
idcode : integer range 0 to 255 := 9;
manf : integer range 0 to 2047 := 804;
part : integer range 0 to 65535 := 0;
ver : integer range 0 to 15 := 0;
trsten : integer range 0 to 1 := 1;
scantest : integer := 0;
oepol : integer := 1);
port (
trst : in std_ulogic;
tckp : in std_ulogic;
tckn : in std_ulogic;
tms : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
tapi_en1 : in std_ulogic;
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_inst : out std_logic_vector(7 downto 0);
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic;
tapo_ninst : out std_logic_vector(7 downto 0);
tapo_iupd : out std_ulogic;
testen : in std_ulogic := '0';
testrst : in std_ulogic := '1';
testoen : in std_ulogic := '0';
tdoen : out std_ulogic
);
end component;
component virtex_tap
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end component;
component virtex2_tap
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end component;
component virtex4_tap
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end component;
component virtex5_tap
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end component;
component spartan3_tap
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end component;
component altera_tap
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_inst : out std_logic_vector(7 downto 0);
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end component;
component fusion_tap
port (
tck : in std_ulogic;
tms : in std_ulogic;
tdi : in std_ulogic;
trst : in std_ulogic;
tdo : out std_ulogic;
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapi_en1 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_inst : out std_logic_vector(7 downto 0)
);
end component;
component proasic3_tap
port (
tck : in std_ulogic;
tms : in std_ulogic;
tdi : in std_ulogic;
trst : in std_ulogic;
tdo : out std_ulogic;
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapi_en1 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_inst : out std_logic_vector(7 downto 0)
);
end component;
component proasic3e_tap
port (
tck : in std_ulogic;
tms : in std_ulogic;
tdi : in std_ulogic;
trst : in std_ulogic;
tdo : out std_ulogic;
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapi_en1 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_inst : out std_logic_vector(7 downto 0)
);
end component;
component proasic3l_tap
port (
tck : in std_ulogic;
tms : in std_ulogic;
tdi : in std_ulogic;
trst : in std_ulogic;
tdo : out std_ulogic;
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapi_en1 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_inst : out std_logic_vector(7 downto 0)
);
end component;
component virtex6_tap
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end component;
component spartan6_tap
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end component;
component virtex7_tap
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end component;
component kintex7_tap
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end component;
component artix7_tap
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end component;
component zynq_tap
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end component;
component igloo2_tap is
port (
tck : in std_ulogic;
tms : in std_ulogic;
tdi : in std_ulogic;
trst : in std_ulogic;
tdo : out std_ulogic;
tapi_tdo : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_inst : out std_logic_vector(7 downto 0));
end component;
-------------------------------------------------------------------------------
component scanregi_inf
generic (
intesten : integer := 1
);
port (
pad : in std_ulogic;
core : out std_ulogic;
tck : in std_ulogic;
tckn : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
bsshft : in std_ulogic;
bscapt : in std_ulogic; -- capture signal to scan reg on next tck edge
bsupd : in std_ulogic; -- update data reg from scan reg on next tck edge
bsdrive : in std_ulogic; -- drive data reg to core
bshighz : in std_ulogic
);
end component;
component scanrego_inf
port (
pad : out std_ulogic;
core : in std_ulogic;
samp : in std_ulogic; -- normally same as core unless outpad has feedback
tck : in std_ulogic;
tckn : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
bsshft : in std_ulogic;
bscapt : in std_ulogic; -- capture signal to scan reg on next tck edge
bsupd : in std_ulogic; -- update data reg from scan reg on next tck edge
bsdrive : in std_ulogic -- drive data reg to pad
);
end component;
component scanregio_inf -- 3 scan registers: tdo<--input<--output<--outputen<--tdi
generic (
hzsup : integer range 0 to 1 := 1;
intesten: integer := 1
);
port (
pado : out std_ulogic;
padoen : out std_ulogic;
padi : in std_ulogic;
coreo : in std_ulogic;
coreoen : in std_ulogic;
corei : out std_ulogic;
tck : in std_ulogic;
tckn : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
bsshft : in std_ulogic;
bscapt : in std_ulogic; -- capture signals to scan regs on next tck edge
bsupdi : in std_ulogic; -- update indata reg from scan reg on next tck edge
bsupdo : in std_ulogic; -- update outdata reg from scan reg on next tck edge
bsdrive : in std_ulogic; -- drive outdata regs to pad,
-- drive datareg(coreoen=0) or coreo(coreoen=1) to corei
bshighz : in std_ulogic
);
end component;
end;
| gpl-3.0 | 9e4358e98850f11dd412e7ba3f05bf9c | 0.559373 | 3.414977 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/ddr/ddr1spax.vhd | 1 | 8,673 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr1spax
-- File: ddr1spax.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: DDR1 memory controller with asynch AHB interface
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
library gaisler;
use gaisler.ddrpkg.all;
use gaisler.ddrintpkg.all;
library techmap;
use techmap.gencomp.ddrphy_has_datavalid;
use techmap.gencomp.ddrphy_latency;
use techmap.gencomp.ddrphy_ptctrl;
entity ddr1spax is
generic (
memtech : integer := 0;
phytech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
ddrbits : integer := 32;
burstlen : integer := 8;
MHz : integer := 100;
col : integer := 9;
Mbyte : integer := 8;
pwron : integer := 0;
oepol : integer := 0;
nosync : integer := 1;
ddr_syncrst: integer range 0 to 1 := 0;
ahbbits : integer := ahbdw;
mobile : integer := 0;
confapi : integer := 0;
conf0 : integer := 0;
conf1 : integer := 0;
regoutput : integer := 0;
ft : integer := 0;
ddr400 : integer := 1;
rstdel : integer := 200;
scantest : integer := 0
);
port (
ddr_rst : in std_ulogic;
ahb_rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in ddrctrl_in_type;
sdo : out ddrctrl_out_type
);
end ddr1spax;
architecture rtl of ddr1spax is
constant REVISION : integer := 0;
constant ramwt: integer := 0;
constant l2blen: integer := log2(burstlen)+log2(32);
constant l2ddrw: integer := log2(ddrbits*2);
function pick(choice: boolean; t,f: integer) return integer is
begin
if choice then return t; else return f; end if;
end;
constant xahbw: integer := pick(ft/=0 and ahbbits<64, 64, ahbbits);
constant l2ahbw: integer := log2(xahbw);
-- For non-FT, write buffer has room for two write bursts and is addressable
-- down to 32-bit level on write (AHB) side.
-- For FT, the write buffer has room for one write burst and is addressable
-- down to 64-bit level on write side.
-- Write buffer dimensions
constant wbuf_rabits_s: integer := 1+l2blen-l2ddrw;
constant wbuf_rabits_r: integer := wbuf_rabits_s-FT;
constant wbuf_rdbits: integer := pick(ft/=0, 3*ddrbits, 2*ddrbits);
constant wbuf_wabits: integer := pick(ft/=0, l2blen-6, 1+l2blen-5);
constant wbuf_wdbits: integer := pick(ft/=0, xahbw+xahbw/2, xahbw);
-- Read buffer dimensions
constant rbuf_rabits: integer := l2blen-l2ahbw;
constant rbuf_rdbits: integer := wbuf_wdbits;
constant rbuf_wabits: integer := l2blen-l2ddrw; -- log2((burstlen*32)/(2*ddrbits));
constant rbuf_wdbits: integer := pick(ft/=0, 3*ddrbits, 2*ddrbits);
signal request : ddr_request_type;
signal start_tog : std_logic;
signal response : ddr_response_type;
signal wbwaddr: std_logic_vector(wbuf_wabits-1 downto 0);
signal wbwdata: std_logic_vector(wbuf_wdbits-1 downto 0);
signal wbraddr: std_logic_vector(wbuf_rabits_s-1 downto 0);
signal wbrdata: std_logic_vector(wbuf_rdbits-1 downto 0);
signal rbwaddr: std_logic_vector(rbuf_wabits-1 downto 0);
signal rbwdata: std_logic_vector(rbuf_wdbits-1 downto 0);
signal rbraddr: std_logic_vector(rbuf_rabits-1 downto 0);
signal rbrdata: std_logic_vector(rbuf_rdbits-1 downto 0);
signal wbwrite,wbwritebig,rbwrite: std_logic;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute keep of rbwdata : signal is true;
attribute syn_keep of rbwdata : signal is true;
attribute syn_preserve of rbwdata : signal is true;
signal vcc: std_ulogic;
signal sdox: ddrctrl_out_type;
signal ce: std_logic;
begin
vcc <= '1';
gft0: if ft=0 generate
ahbc : ddr2spax_ahb
generic map (hindex => hindex, haddr => haddr, hmask => hmask, ioaddr => ioaddr, iomask => iomask,
nosync => nosync, burstlen => burstlen, ahbbits => xahbw, revision => revision,
devid => GAISLER_DDRSP, regarea => 0)
port map (ahb_rst, clk_ahb, ahbsi, ahbso, request, start_tog, response,
wbwaddr, wbwdata, wbwrite, wbwritebig, rbraddr, rbrdata, '0', FTFE_BEID_DDR1);
ce <= '0';
end generate;
gft1: if ft/=0 generate
ftc: ft_ddr2spax_ahb
generic map (hindex => hindex, haddr => haddr, hmask => hmask, ioaddr => ioaddr, iomask => iomask,
nosync => nosync, burstlen => burstlen, ahbbits => xahbw, bufbits => xahbw+xahbw/2,
ddrbits => ddrbits, hwidthen => 0, revision => revision, devid => GAISLER_DDRSP)
port map (ahb_rst, clk_ahb, ahbsi, ahbso, ce, request, start_tog, response,
wbwaddr, wbwdata, wbwrite, wbwritebig, rbraddr, rbrdata, '0', '0', open, open, FTFE_BEID_DDR1);
end generate;
ddrc : ddr1spax_ddr
generic map (ddrbits => ddrbits,
pwron => pwron, MHz => MHz, col => col, Mbyte => Mbyte,
nosync => nosync, burstlen => burstlen,
chkbits => ft*ddrbits/2, oepol => oepol, mobile => mobile,
confapi => confapi, conf0 => conf0, conf1 => conf1,
hasdqvalid => ddrphy_has_datavalid(phytech),
ddr_syncrst => ddr_syncrst, regoutput => regoutput,
readdly => ddrphy_latency(phytech)+regoutput, ddr400 => ddr400,
rstdel => rstdel, phyptctrl => ddrphy_ptctrl(phytech), scantest => scantest)
port map (ddr_rst, clk_ddr, request, start_tog, response, sdi, sdox,
wbraddr, wbrdata, rbwaddr, rbwdata, rbwrite,
'0', ddr_request_none, open, ahbsi.testen, ahbsi.testrst, ahbsi.testoen);
sdoproc: process(sdox,ce)
variable o: ddrctrl_out_type;
begin
o := sdox;
o.ce := ce;
sdo <= o;
end process;
wbuf: ddr2buf
generic map (tech => memtech, wabits => wbuf_wabits, wdbits => wbuf_wdbits,
rabits => wbuf_rabits_r, rdbits => wbuf_rdbits,
sepclk => 1, wrfst => ramwt, testen => scantest)
port map ( rclk => clk_ddr, renable => vcc, raddress => wbraddr(wbuf_rabits_r-1 downto 0),
dataout => wbrdata, wclk => clk_ahb, write => wbwrite,
writebig => wbwritebig, waddress => wbwaddr, datain => wbwdata, testin => ahbsi.testin);
rbuf: ddr2buf
generic map (tech => memtech, wabits => rbuf_wabits, wdbits => rbuf_wdbits,
rabits => rbuf_rabits, rdbits => rbuf_rdbits,
sepclk => 1, wrfst => ramwt, testen => scantest)
port map ( rclk => clk_ahb, renable => vcc, raddress => rbraddr,
dataout => rbrdata,
wclk => clk_ddr, write => rbwrite,
writebig => '0', waddress => rbwaddr, datain => rbwdata, testin => ahbsi.testin);
-- pragma translate_off
bootmsg : report_version
generic map (
msg1 => "ddrspa: DDR controller rev " &
tost(REVISION) & ", " & tost(ddrbits) & " bit width, " & tost(Mbyte) & " Mbyte, " & tost(MHz) &
" MHz DDR clock");
-- pragma translate_on
end;
| gpl-3.0 | 9ede86d731fa9ac9c64422e746927971 | 0.6006 | 3.885753 | false | true | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/pci/grpci2/wrapper/grpci2_gen.vhd | 1 | 22,028 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grpci2_gen
-- File: grpci2_gen.vhd
-- Author: Nils-Johan Wessman - Aeroflex Gaisler
-- Description: Std_logic wrapper for GRPCI2
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
--use grlib.stdlib.all;
--use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.pci.all;
entity grpci2_gen is
generic (
memtech : integer := DEFMEMTECH;
tbmemtech : integer := DEFMEMTECH; -- For trace buffers
oepol : integer := 0;
hmask : integer := 0; -- Need to set according to the size of the decoded AHB address range
irqmode : integer range 0 to 3 := 0;
master : integer range 0 to 1 := 1;
target : integer range 0 to 1 := 1;
dma : integer range 0 to 1 := 1;
tracebuffer : integer range 0 to 16384 := 0;
confspace : integer range 0 to 1 := 1;
vendorid : integer := 16#0000#;
deviceid : integer := 16#0000#;
classcode : integer := 16#000000#;
revisionid : integer := 16#00#;
cap_pointer : integer := 16#40#;
ext_cap_pointer : integer := 16#00#;
iobase : integer := 16#FFF#;
extcfg : integer := 16#0000000#;
bar0 : integer range 0 to 31 := 28;
bar1 : integer range 0 to 31 := 0;
bar2 : integer range 0 to 31 := 0;
bar3 : integer range 0 to 31 := 0;
bar4 : integer range 0 to 31 := 0;
bar5 : integer range 0 to 31 := 0;
bar0_map : integer := 16#000000#;
bar1_map : integer := 16#000000#;
bar2_map : integer := 16#000000#;
bar3_map : integer := 16#000000#;
bar4_map : integer := 16#000000#;
bar5_map : integer := 16#000000#;
bartype : integer range 0 to 65535 := 16#0000#;
barminsize : integer range 5 to 31 := 12;
fifo_depth : integer range 3 to 7 := 3;
fifo_count : integer range 2 to 4 := 2;
conv_endian : integer range 0 to 1 := 1; -- 1: little (PCI) <~> big (AHB), 0: big (PCI) <=> big (AHB)
deviceirq : integer range 0 to 1 := 1;
deviceirqmask : integer range 0 to 15 := 16#0#;
hostirq : integer range 0 to 1 := 1;
hostirqmask : integer range 0 to 15 := 16#0#;
nsync : integer range 0 to 2 := 2; -- with nsync = 0, wrfst needed on syncram...
hostrst : integer range 0 to 2 := 0;-- 0: PCI reset is never driven, 1: PCI reset is driven from AHB reset if host, 2: PCI reset is always driven from AHB reset
bypass : integer range 0 to 1 := 1;
ft : integer range 0 to 1 := 0;
scantest : integer range 0 to 1 := 0;
debug : integer range 0 to 1 := 0;
tbapben : integer range 0 to 1 := 0;
netlist : integer range 0 to 1 := 0; -- Use PHY netlist
multifunc : integer range 0 to 1 := 0; -- Enables Multi-function support
multiint : integer range 0 to 1 := 0;
masters : integer := 16#FFFF#;
mf1_deviceid : integer := 16#0000#;
mf1_classcode : integer := 16#000000#;
mf1_revisionid : integer := 16#00#;
mf1_bar0 : integer range 0 to 31 := 0;
mf1_bar1 : integer range 0 to 31 := 0;
mf1_bar2 : integer range 0 to 31 := 0;
mf1_bar3 : integer range 0 to 31 := 0;
mf1_bar4 : integer range 0 to 31 := 0;
mf1_bar5 : integer range 0 to 31 := 0;
mf1_bartype : integer range 0 to 65535 := 16#0000#;
mf1_bar0_map : integer := 16#000000#;
mf1_bar1_map : integer := 16#000000#;
mf1_bar2_map : integer := 16#000000#;
mf1_bar3_map : integer := 16#000000#;
mf1_bar4_map : integer := 16#000000#;
mf1_bar5_map : integer := 16#000000#;
mf1_cap_pointer : integer := 16#40#;
mf1_ext_cap_pointer : integer := 16#00#;
mf1_extcfg : integer := 16#0000000#;
mf1_masters : integer := 16#0000#
);
port(
rst : in std_logic; -- AMBA reset
clk : in std_logic; -- AMBA clock
pciclk : in std_logic; -- PCI clock
--
dirq : in std_logic_vector(3 downto 0); -- From interrupt controller to PCI interrupt
--
pci_rst_i : in std_logic; -- PCI reset in
pci_rst_o : out std_logic; -- PCI reset out
pci_gnt : in std_logic; -- PCI grant
pci_req_o : out std_logic; -- PCI request out
pci_req_oe : out std_logic; -- PCI request output enable
pci_idsel : in std_logic; -- PCI IDSEL
pci_ad_i : in std_logic_vector(31 downto 0); -- PCI AD in
pci_ad_o : out std_logic_vector(31 downto 0); -- PCI AD out
pci_ad_oe : out std_logic_vector(31 downto 0); -- PCI AD output enable
pci_cbe_i : in std_logic_vector(3 downto 0); -- PCI CBE in
pci_cbe_o : out std_logic_vector(3 downto 0); -- PCI CBE out
pci_cbe_oe : out std_logic_vector(3 downto 0); -- PCI CBE output enable
pci_frame_i : in std_logic; -- PCI FRAME in
pci_frame_o : out std_logic; -- PCI FRAME out
pci_frame_oe : out std_logic; -- PCI FRAME output enable
pci_irdy_i : in std_logic; -- PCI IRDY in
pci_irdy_o : out std_logic; -- PCI IRDY out
pci_irdy_oe : out std_logic; -- PCI IRDY output enable
pci_trdy_i : in std_logic; -- PCI TRDY in
pci_trdy_o : out std_logic; -- PCI TRDY out
pci_trdy_oe : out std_logic; -- PCI TRDY output enable
pci_stop_i : in std_logic; -- PCI STOP in
pci_stop_o : out std_logic; -- PCI STOP out
pci_stop_oe : out std_logic; -- PCI STOP output enable
pci_devsel_i : in std_logic; -- PCI DEVSEL in
pci_devsel_o : out std_logic; -- PCI DEVSEL out
pci_devsel_oe : out std_logic; -- PCI DEVSEL output enable
pci_perr_i : in std_logic; -- PCI PERR in
pci_perr_o : out std_logic; -- PCI PERR out
pci_perr_oe : out std_logic; -- PCI PERR output enable
pci_serr_i : in std_logic; -- PCI SERR in
pci_serr_o : out std_logic; -- PCI SERR out
pci_serr_oe : out std_logic; -- PCI SERR output enable
pci_par_i : in std_logic; -- PCI PAR in
pci_par_o : out std_logic; -- PCI PAR out
pci_par_oe : out std_logic; -- PCI PAR output enable
pci_int_i : in std_logic_vector(3 downto 0); -- PCI INT[D..A] in
pci_int_oe : out std_logic_vector(3 downto 0); -- PCI INT[D..A] output enable
pci_host : in std_logic; -- GRPCI2 specific, determine host/peripheral mode
pci_pci66 : in std_logic; -- PCI M66EN
--
apb_psel : in std_logic; -- slave select
apb_penable : in std_ulogic; -- strobe
apb_paddr : in std_logic_vector(31 downto 0); -- address bus (byte)
apb_pwrite : in std_ulogic; -- write
apb_pwdata : in std_logic_vector(31 downto 0); -- write data bus
apb_prdata : out std_logic_vector(31 downto 0); -- read data bus
--
apb_pirq : out std_logic_vector(4 downto 0); -- interrupt bus (GRLIB specific)
--
ahbsi_hsel : in std_logic; -- slave select
ahbsi_haddr : in std_logic_vector(31 downto 0); -- address bus (byte)
ahbsi_hwrite : in std_ulogic; -- read/write
ahbsi_htrans : in std_logic_vector(1 downto 0); -- transfer type
ahbsi_hsize : in std_logic_vector(2 downto 0); -- transfer size
ahbsi_hburst : in std_logic_vector(2 downto 0); -- burst type
ahbsi_hwdata : in std_logic_vector(AHBDW-1 downto 0); -- write data bus
ahbsi_hprot : in std_logic_vector(3 downto 0); -- protection control
ahbsi_hready : in std_ulogic; -- transfer done
ahbsi_hmaster : in std_logic_vector(3 downto 0); -- current master
ahbsi_hmastlock : in std_ulogic; -- locked access
--
ahbsi_hmbsel : in std_logic_vector(0 to NAHBAMR-1); -- memory bank select (GRLIB specific, need to be
-- decoded for the two address ranges the PCI core
-- occupies in the AHB address range.
--
ahbso_hready : out std_ulogic; -- transfer done
ahbso_hresp : out std_logic_vector(1 downto 0); -- response type
ahbso_hrdata : out std_logic_vector(AHBDW-1 downto 0); -- read data bus
ahbso_hsplit : out std_logic_vector(NAHBMST-1 downto 0); -- split completion
--
testen : in std_ulogic; -- scan test enable
testrst : in std_ulogic; -- scan test reset
scanen : in std_ulogic; -- scan enable
testoen : in std_ulogic; -- test output enable
testin : in std_logic_vector(NTESTINBITS-1 downto 0); -- test vector for syncrams
--
ahbmi_hgrant : in std_logic; -- bus grant
ahbmi_hready : in std_ulogic; -- transfer done
ahbmi_hresp : in std_logic_vector(1 downto 0); -- response type
ahbmi_hrdata : in std_logic_vector(AHBDW-1 downto 0); -- read data bus
--
ahbmo_hbusreq : out std_ulogic; -- bus request
ahbmo_hlock : out std_ulogic; -- lock request
ahbmo_htrans : out std_logic_vector(1 downto 0); -- transfer type
ahbmo_haddr : out std_logic_vector(31 downto 0); -- address bus (byte)
ahbmo_hwrite : out std_ulogic; -- read/write
ahbmo_hsize : out std_logic_vector(2 downto 0); -- transfer size
ahbmo_hburst : out std_logic_vector(2 downto 0); -- burst type
ahbmo_hprot : out std_logic_vector(3 downto 0); -- protection control
ahbmo_hwdata : out std_logic_vector(AHBDW-1 downto 0); -- write data bus
--
ahbdmo_hbusreq : out std_ulogic; -- bus request
ahbdmo_hlock : out std_ulogic; -- lock request
ahbdmo_htrans : out std_logic_vector(1 downto 0); -- transfer type
ahbdmo_haddr : out std_logic_vector(31 downto 0); -- address bus (byte)
ahbdmo_hwrite : out std_ulogic; -- read/write
ahbdmo_hsize : out std_logic_vector(2 downto 0); -- transfer size
ahbdmo_hburst : out std_logic_vector(2 downto 0); -- burst type
ahbdmo_hprot : out std_logic_vector(3 downto 0); -- protection control
ahbdmo_hwdata : out std_logic_vector(AHBDW-1 downto 0); -- write data bus
--
ptarst : out std_logic; -- PCI reset to connect to AMBA reset
--
tbapb_psel : in std_logic; -- slave select
tbapb_penable : in std_ulogic; -- strobe
tbapb_paddr : in std_logic_vector(31 downto 0); -- address bus (byte)
tbapb_pwrite : in std_ulogic; -- write
tbapb_pwdata : in std_logic_vector(31 downto 0); -- write data bus
tbapb_prdata : out std_logic_vector(31 downto 0); -- read data bus
--
debugo : out std_logic_vector(debug*255 downto 0) -- DEBUG output
);
end;
architecture rtl of grpci2_gen is
signal pcii : pci_in_type;
signal pcio : pci_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_type;
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_type;
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_type;
signal ahbdmo : ahb_mst_out_type;
signal tbapbi : apb_slv_in_type;
signal tbapbo : apb_slv_out_type;
begin
pcii.rst <= pci_rst_i;
pcii.gnt <= pci_gnt;
pcii.idsel <= pci_idsel;
pcii.ad <= pci_ad_i;
pcii.cbe <= pci_cbe_i;
pcii.frame <= pci_frame_i;
pcii.irdy <= pci_irdy_i;
pcii.trdy <= pci_trdy_i;
pcii.devsel <= pci_devsel_i;
pcii.stop <= pci_stop_i;
pcii.lock <= '0';
pcii.perr <= pci_perr_i;
pcii.serr <= pci_serr_i;
pcii.par <= pci_par_i;
pcii.host <= pci_host;
pcii.pci66 <= pci_pci66;
pcii.pme_status <= '0';
pcii.int <= pci_int_i;
pci_ad_oe <= pcio.vaden;
--pci_vad_oe <= pcio.vaden;
pci_cbe_oe <= pcio.cbeen;
pci_frame_oe <= pcio.frameen;
pci_irdy_oe <= pcio.irdyen;
pci_trdy_oe <= pcio.trdyen;
pci_devsel_oe <= pcio.devselen;
pci_stop_oe <= pcio.stopen;
--pci_ctrl_oe <= pcio.ctrlen;
pci_perr_oe <= pcio.perren;
pci_par_oe <= pcio.paren;
pci_req_oe <= pcio.reqen;
--pci_lock_oe <= pcio.locken;
pci_serr_oe <= pcio.serren;
--pci_int_oe <= pcio.inten;
pci_int_oe <= pcio.vinten;
pci_req_o <= pcio.req;
pci_ad_o <= pcio.ad;
pci_cbe_o <= pcio.cbe;
pci_frame_o <= pcio.frame;
pci_irdy_o <= pcio.irdy;
pci_trdy_o <= pcio.trdy;
pci_devsel_o <= pcio.devsel;
pci_stop_o <= pcio.stop;
pci_perr_o <= pcio.perr;
pci_serr_o <= pcio.serr;
pci_par_o <= pcio.par;
--pci_lock_o <= pcio.lock;
--pci_power_state <= pcio.power_state;
--pci_pme_enable <= pcio.pme_enable;
--pci_pme_clear <= pcio.pme_clear;
--pci_int_o <= pcio.int;
pci_rst_o <= pcio.rst;
apbi.psel(0) <= apb_psel;
apbi.penable <= apb_penable;
apbi.paddr <= apb_paddr;
apbi.pwrite <= apb_pwrite;
apbi.pwdata <= apb_pwdata;
apb_prdata <= apbo.prdata;
--
apb_pirq <= apbo.pirq(4 downto 0);
--
apbi.pirq <= (others => '0');
apbi.testen <= '0';
apbi.testrst <= '0';
apbi.scanen <= '0';
apbi.testoen <= '0';
apbi.testin <= (others => '0');
tbapbi.psel(0) <= tbapb_psel;
tbapbi.penable <= tbapb_penable;
tbapbi.paddr <= tbapb_paddr;
tbapbi.pwrite <= tbapb_pwrite;
tbapbi.pwdata <= tbapb_pwdata;
tbapb_prdata <= tbapbo.prdata;
--
tbapbi.pirq <= (others => '0');
tbapbi.testen <= '0';
tbapbi.testrst <= '0';
tbapbi.scanen <= '0';
tbapbi.testoen <= '0';
tbapbi.testin <= (others => '0');
ahbmi.hgrant(0) <= ahbmi_hgrant;
ahbmi.hready <= ahbmi_hready;
ahbmi.hresp <= ahbmi_hresp;
ahbmi.hrdata <= ahbmi_hrdata;
--
ahbmi.hirq <= (others => '0');
ahbmi.testen <= '0';
ahbmi.testrst <= '0';
ahbmi.scanen <= '0';
ahbmi.testoen <= '0';
ahbmi.testin <= (others => '0');
ahbmo_hbusreq <= ahbmo.hbusreq;
ahbmo_hlock <= ahbmo.hlock;
ahbmo_htrans <= ahbmo.htrans;
ahbmo_haddr <= ahbmo.haddr;
ahbmo_hwrite <= ahbmo.hwrite;
ahbmo_hsize <= ahbmo.hsize;
ahbmo_hburst <= ahbmo.hburst;
ahbmo_hprot <= ahbmo.hprot;
ahbmo_hwdata <= ahbmo.hwdata;
ahbdmo_hbusreq <= ahbdmo.hbusreq;
ahbdmo_hlock <= ahbdmo.hlock;
ahbdmo_htrans <= ahbdmo.htrans;
ahbdmo_haddr <= ahbdmo.haddr;
ahbdmo_hwrite <= ahbdmo.hwrite;
ahbdmo_hsize <= ahbdmo.hsize;
ahbdmo_hburst <= ahbdmo.hburst;
ahbdmo_hprot <= ahbdmo.hprot;
ahbdmo_hwdata <= ahbdmo.hwdata;
ahbsi.hsel(0) <= ahbsi_hsel;
ahbsi.haddr <= ahbsi_haddr;
ahbsi.hwrite <= ahbsi_hwrite;
ahbsi.htrans <= ahbsi_htrans;
ahbsi.hsize <= ahbsi_hsize;
ahbsi.hburst <= ahbsi_hburst;
ahbsi.hwdata <= ahbsi_hwdata;
ahbsi.hprot <= ahbsi_hprot;
ahbsi.hready <= ahbsi_hready;
ahbsi.hmaster <= ahbsi_hmaster;
ahbsi.hmastlock <= ahbsi_hmastlock;
--
ahbsi.hmbsel <= ahbsi_hmbsel;
--
ahbsi.hirq <= (others => '0');
ahbsi.testen <= testen;
ahbsi.testrst <= testrst;
ahbsi.scanen <= scanen;
ahbsi.testoen <= testoen;
ahbsi.testin <= testin;
ahbso_hready <= ahbso.hready;
ahbso_hresp <= ahbso.hresp;
ahbso_hrdata <= ahbso.hrdata;
ahbso_hsplit <= ahbso.hsplit;
gen : grpci2
generic map(
memtech => memtech,
tbmemtech => tbmemtech,
oepol => oepol,
hmindex => 0,
hdmindex => 0,
hsindex => 0,
haddr => 0,
hmask => hmask,
ioaddr => 0,
pindex => 0,
paddr => 0,
pmask => 0,
irq => 0,
irqmode => irqmode,
master => master,
target => target,
dma => dma,
tracebuffer => tracebuffer,
confspace => confspace,
vendorid => vendorid,
deviceid => deviceid,
classcode => classcode,
revisionid => revisionid,
cap_pointer => cap_pointer,
ext_cap_pointer => ext_cap_pointer,
iobase => iobase,
extcfg => extcfg,
bar0 => bar0,
bar1 => bar1,
bar2 => bar2,
bar3 => bar3,
bar4 => bar4,
bar5 => bar5,
bar0_map => bar0_map,
bar1_map => bar1_map,
bar2_map => bar2_map,
bar3_map => bar3_map,
bar4_map => bar4_map,
bar5_map => bar5_map,
bartype => bartype,
barminsize => barminsize,
fifo_depth => fifo_depth,
fifo_count => fifo_count,
conv_endian => conv_endian,
deviceirq => deviceirq,
deviceirqmask => deviceirqmask,
hostirq => hostirq,
hostirqmask => hostirqmask,
nsync => nsync,
hostrst => hostrst,
bypass => bypass,
ft => ft,
scantest => scantest,
debug => debug,
tbapben => tbapben,
tbpindex => 0,
tbpaddr => 0,
tbpmask => 0,
netlist => netlist,
multifunc => multifunc,
multiint => multiint,
masters => masters,
mf1_deviceid => mf1_deviceid,
mf1_classcode => mf1_classcode,
mf1_revisionid => mf1_revisionid,
mf1_bar0 => mf1_bar0,
mf1_bar1 => mf1_bar1,
mf1_bar2 => mf1_bar2,
mf1_bar3 => mf1_bar3,
mf1_bar4 => mf1_bar4,
mf1_bar5 => mf1_bar5,
mf1_bartype => mf1_bartype,
mf1_bar0_map => mf1_bar0_map,
mf1_bar1_map => mf1_bar1_map,
mf1_bar2_map => mf1_bar2_map,
mf1_bar3_map => mf1_bar3_map,
mf1_bar4_map => mf1_bar4_map,
mf1_bar5_map => mf1_bar5_map,
mf1_cap_pointer => mf1_cap_pointer,
mf1_ext_cap_pointer => mf1_ext_cap_pointer,
mf1_extcfg => mf1_extcfg,
mf1_masters => mf1_masters)
port map(
rst => rst,
clk => clk,
pciclk => pciclk,
dirq => dirq,
pcii => pcii,
pcio => pcio,
apbi => apbi,
apbo => apbo,
ahbsi => ahbsi,
ahbso => ahbso,
ahbmi => ahbmi,
ahbmo => ahbmo,
ahbdmi => ahbmi,
ahbdmo => ahbdmo,
ptarst => ptarst,
tbapbi => tbapbi,
tbapbo => tbapbo,
debugo => debugo);
end;
| gpl-3.0 | 1ab702e40290424f016838c8e215c927 | 0.499455 | 3.767402 | false | true | false | false |
yishinli/emc2 | src/hal/drivers/mesa-hostmot2/firmware/src/ubrategen.vhd | 1 | 4,102 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
-- http://www.mesanet.com
--
-- This program is is licensed under a disjunctive dual license giving you
-- the choice of one of the two following sets of free software/open source
-- licensing terms:
--
-- * GNU General Public License (GPL), version 2.0 or later
-- * 3-clause BSD License
--
--
-- The GNU GPL License:
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- The 3-clause BSD License:
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- * Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- * Neither the name of Mesa Electronics nor the names of its
-- contributors may be used to endorse or promote products
-- derived from this software without specific prior written
-- permission.
--
--
-- Disclaimer:
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
entity rategen is
Port ( ibus : in std_logic_vector(31 downto 0);
obus : out std_logic_vector(31 downto 0);
loadbasicrate : in std_logic;
readbasicrate : in std_logic;
hold : in std_logic;
basicrate : out std_logic;
clk : in std_logic);
end rategen;
architecture Behavioral of rategen is
signal rateaccum: std_logic_vector (32 downto 0);
alias ratemsb: std_logic is rateaccum(32);
signal oldratemsb: std_logic;
signal ratelatch: std_logic_vector (31 downto 0);
signal rateout: std_logic;
begin
rategen: process (clk,readbasicrate, ratelatch, rateout)
begin
if rising_edge(clk) then
if hold = '0' then
rateaccum <= rateaccum + ratelatch;
end if;
if oldratemsb /= ratemsb then
rateout <= '1';
else
rateout <= '0';
end if;
oldratemsb <= ratemsb;
if loadbasicrate = '1' then
ratelatch <= ibus;
rateaccum <= (others => '0');
end if;
end if; -- clk
obus <= (others => 'Z');
if readbasicrate = '1' then
obus <= ratelatch;
end if;
basicrate <= rateout;
end process;
end Behavioral;
| lgpl-2.1 | 142870fdbd1e7f14a6d797c6c51272d9 | 0.678206 | 3.90295 | false | false | false | false |
pwsoft/fpga_examples | rtl/general/gen_fifo.vhd | 1 | 3,597 | -- -----------------------------------------------------------------------
--
-- Syntiac's generic VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2010 by Peter Wendrich ([email protected])
-- http://www.syntiac.com/fpga64.html
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
--
-- gen_fifo.vhd
--
-- -----------------------------------------------------------------------
--
-- FIFO (first in is first out) buffer for single clock domain.
-- Build with logic so can be used on any FPGA architecture.
--
--
-- -----------------------------------------------------------------------
-- width - width of data stored in the FIFO
-- depth - fifo depth in elements
-- -----------------------------------------------------------------------
-- clk - clock input
-- d_ena - when high data on d input is writen into FIFO
-- d - data input into the FIFO
-- q_ena - when high removed first item from the FIFO
-- q - first item in the FIFO
-- empty - signal is high when there is nothing in the FIFO
-- full - signal is high when there is no space left in the FIFO
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- -----------------------------------------------------------------------
entity gen_fifo is
generic (
width : integer := 8;
depth : integer := 4
);
port (
clk : in std_logic;
d_ena : in std_logic;
d : in unsigned(width-1 downto 0);
q_ena : in std_logic;
q : out unsigned(width-1 downto 0);
empty : out std_logic;
full : out std_logic
);
end entity;
-- -----------------------------------------------------------------------
architecture rtl of gen_fifo is
type fifo_t is array(0 to depth-1) of unsigned(width-1 downto 0);
signal fifo_reg : fifo_t := (others => (others => '0'));
signal d_cnt_reg : integer range 0 to depth-1 := 0;
signal d_tgl_reg : std_logic := '0';
signal q_cnt_reg : integer range 0 to depth-1 := 0;
signal q_tgl_reg : std_logic := '0';
signal empty_loc : std_logic;
signal full_loc : std_logic;
begin
q <= fifo_reg(q_cnt_reg);
empty <= empty_loc;
full <= full_loc;
empty_loc <= '1' when (d_cnt_reg = q_cnt_reg) and (d_tgl_reg = q_tgl_reg) else '0';
full_loc <= '1' when (d_cnt_reg = q_cnt_reg) and (d_tgl_reg /= q_tgl_reg) else '0';
process(clk)
begin
if rising_edge(clk) then
if (d_ena = '1') and (full_loc = '0') then
fifo_reg(d_cnt_reg) <= d;
if d_cnt_reg = depth-1 then
d_cnt_reg <= 0;
d_tgl_reg <= not d_tgl_reg;
else
d_cnt_reg <= d_cnt_reg + 1;
end if;
end if;
if (q_ena = '1') and (empty_loc = '0') then
if q_cnt_reg = depth-1 then
q_cnt_reg <= 0;
q_tgl_reg <= not q_tgl_reg;
else
q_cnt_reg <= q_cnt_reg + 1;
end if;
end if;
end if;
end process;
end architecture;
| lgpl-2.1 | d91e0db8aed5e8d03edae36ce21245eb | 0.526272 | 3.536873 | false | false | false | false |
richjyoung/lfsr-package | src/LFSR/pulse_shreg.vhd | 1 | 1,095 | library IEEE, LFSR;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
--------------------------------------------------------------------------------
entity pulse_shreg is
generic (
G_period : natural := 10000
);
port(
CLK : in std_logic;
RESET : in std_logic;
PULSE : out std_logic
);
end pulse_shreg;
--------------------------------------------------------------------------------
architecture rtl of pulse_shreg is
subtype T_SHIFTREG is std_logic_vector(G_period-1 downto 0);
constant C_ZERO : T_SHIFTREG := (0 => '1', others => '0');
signal SHIFTREG : T_SHIFTREG;
begin
PULSE <= '1' when SHIFTREG = C_ZERO else '0';
shreg_proc: process (CLK) is
begin
if rising_edge(CLK) then
if RESET = '1' then
SHIFTREG <= C_ZERO;
else
SHIFTREG <= SHIFTREG(G_period-2 downto 0) & SHIFTREG(G_period-1);
end if;
end if;
end process shreg_proc;
end rtl; | mit | cd2fd0febc6352e17a154025e663964b | 0.439269 | 4.2607 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/grlib/amba/apbctrldp.vhd | 1 | 3,599 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: apbctrl
-- File: apbctrl.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AMBA AHB/APB bridge with plug&play support
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
entity apbctrldp is
generic (
hindex0 : integer := 0;
haddr0 : integer := 0;
hmask0 : integer := 16#fff#;
hindex1 : integer := 0;
haddr1 : integer := 0;
hmask1 : integer := 16#fff#;
nslaves : integer range 1 to NAPBSLV := NAPBSLV;
wprot : integer range 0 to 1 := 0;
debug : integer range 0 to 2 := 2;
icheck : integer range 0 to 1 := 1;
enbusmon : integer range 0 to 1 := 0;
asserterr : integer range 0 to 1 := 0;
assertwarn : integer range 0 to 1 := 0;
pslvdisable : integer := 0;
mcheck : integer range 0 to 1 := 1;
ccheck : integer range 0 to 1 := 1
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahb0i : in ahb_slv_in_type;
ahb0o : out ahb_slv_out_type;
ahb1i : in ahb_slv_in_type;
ahb1o : out ahb_slv_out_type;
apbi : out apb_slv_in_vector;
apbo : in apb_slv_out_vector;
wp : in std_logic_vector(0 to 1) := (others => '0');
wpv : in std_logic_vector((256*2)-1 downto 0) := (others => '0')
);
end;
architecture struct of apbctrldp is
signal lahbi : ahb_slv_in_vector_type(0 to 1);
signal lahbo : ahb_slv_out_vector_type(0 to 1);
begin
lahbi(0) <= ahb0i;
lahbi(1) <= ahb1i;
ahb0o <= lahbo(0);
ahb1o <= lahbo(1);
apbx : apbctrlx
generic map(
hindex0 => hindex0,
haddr0 => haddr0,
hmask0 => hmask0,
hindex1 => hindex1,
haddr1 => haddr1,
hmask1 => hmask1,
nslaves => nslaves,
nports => 2,
wprot => wprot,
debug => debug,
icheck => icheck,
enbusmon => enbusmon,
asserterr => asserterr,
assertwarn => assertwarn,
pslvdisable => pslvdisable,
mcheck => mcheck,
ccheck => ccheck)
port map(
rst => rst,
clk => clk,
ahbi => lahbi,
ahbo => lahbo,
apbi => apbi,
apbo => apbo,
wp => wp,
wpv => wpv);
end;
| gpl-3.0 | fb8b54a8a49157e60fa8c0bac0502350 | 0.540706 | 3.741164 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/pci/grpci2/grpci2_phy.vhd | 1 | 25,495 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grpci2_phy
-- File: grpci2_phy.vhd
-- Author: Nils-Johan Wessman - Aeroflex Gaisler
-- Description: Logic controlled by the PCI control signals in the GRPCI2 core
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use grlib.config.all;
use grlib.config_types.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.pci.all;
use work.pcilib2.all;
entity grpci2_phy is
generic(
tech : integer := DEFMEMTECH;
oepol : integer := 0;
bypass : integer range 0 to 1 := 1;
netlist : integer := 0;
scantest: integer := 0;
iotest : integer := 0
);
port(
pciclk : in std_logic;
pcii : in pci_in_type;
phyi : in grpci2_phy_in_type;
pcio : out pci_out_type;
phyo : out grpci2_phy_out_type;
iotmact : in std_ulogic;
iotmoe : in std_ulogic;
iotdout : in std_logic_vector(44 downto 0);
iotdin : out std_logic_vector(45 downto 0)
);
end;
architecture rtl of grpci2_phy is
constant oeon : std_logic := conv_std_logic_vector(oepol,1)(0);
constant oeoff : std_logic := not conv_std_logic_vector(oepol,1)(0);
constant ones32 : std_logic_vector(31 downto 0) := (others => '1');
type phy_m_reg_type is record
state : pci_master_state_type;
cfi : integer range 0 to 2;
pi_irdy_or_trdy : std_logic;
last : std_logic_vector(1 downto 0);
hold : std_logic_vector(1 downto 0);
term : std_logic_vector(1 downto 0);
end record;
type phy_t_reg_type is record
cfi : integer range 0 to 2;
pi_irdy_or_trdy : std_logic;
hold : std_logic_vector(0 downto 0);
stop : std_logic;
abort : std_logic;
diswithout : std_logic;
addr_perr : std_logic;
end record;
type phy_reg_type is record
po : pci_reg_out_type;
m : phy_m_reg_type;
t : phy_t_reg_type;
end record;
signal pr, prin : phy_reg_type;
signal pi, piin, piin_buf : pci_in_type; -- Registered PCI signals.
signal po, poin, po_keep : pci_reg_out_type; -- PCI output signals (to drive pads)
signal poin_keep : std_logic_vector(90 downto 0);
signal raden, rinaden, rinaden_tmp : std_logic_vector(31 downto 0);
signal pcirst : std_logic_vector(2 downto 0); -- PCI reset
signal xarst : std_ulogic;
signal pcisynrst : std_ulogic;
attribute sync_set_reset of pcisynrst : signal is "true";
attribute syn_keep : boolean;
attribute syn_keep of poin_keep : signal is true;
begin
phycomb : process(pcii, pr, pi, po, phyi, pcisynrst, rinaden)
variable pv : phy_reg_type;
variable pci : pci_in_type;
begin
-- defaults ---------------------------------------------------------------------
pv := pr;
pv.po.frame := '1'; pv.po.irdy := '1'; pv.po.req := '1';
pv.po.trdy := '1'; pv.po.stop := '1';
pv.po.perr := '1'; pv.po.lock := '1'; pv.po.devsel := '1';
pv.po.serr := '1';
pv.po.devselen := oeoff; pv.po.trdyen := oeoff; pv.po.stopen := oeoff;
pv.po.aden := (others => oeoff); pv.po.cbeen := (others => oeoff);
pv.po.frameen := oeoff; pv.po.irdyen := oeoff;
pv.po.perren := oeoff; pv.po.serren := oeoff;
pv.po.reqen := oeon; -- Always on (point-to-point signal, tri-state during reset)
-- PCI input mux ----------------------------------------------------------------
pci := pcii;
if bypass /= 0 then
if pr.po.aden(0) = oeon then pci.ad := pr.po.ad; end if;
if pr.po.cbeen(0) = oeon then pci.cbe := pr.po.cbe; end if;
if pr.po.frameen = oeon then pci.frame := pr.po.frame; end if;
if pr.po.irdyen = oeon then pci.irdy := pr.po.irdy; end if;
if pr.po.trdyen = oeon then pci.trdy := pr.po.trdy; end if;
if pr.po.stopen = oeon then pci.stop := pr.po.stop; end if;
if pr.po.paren = oeon then pci.par := pr.po.par; end if;
if pr.po.devselen = oeon then pci.devsel := pr.po.devsel; end if;
if pr.po.perren = oeon then pci.perr := pr.po.perr; end if;
if pr.po.serren = oeon then pci.serr := pr.po.serren; end if;
end if;
-- Master -----------------------------------------------------------------------
pv.m.pi_irdy_or_trdy := pi.irdy or pi.trdy;
if ((not (pr.po.irdy or pci.trdy)) and pr.m.pi_irdy_or_trdy) = '1' then
if pr.m.state = pm_m_data or pr.m.state = pm_turn_ar then
--pv.m.cfi := pr.m.cfi + 1;
case pr.m.cfi is
when 0 => pv.m.cfi := 1;
when 1 => pv.m.cfi := 2;
when others => pv.m.cfi := 0;
end case;
end if;
elsif ((pr.po.irdy or pci.trdy) and (not pr.m.pi_irdy_or_trdy)) = '1' then
if pr.m.state = pm_m_data or pr.m.state = pm_turn_ar then
--pv.m.cfi := pr.m.cfi - 1;
case pr.m.cfi is
when 2 => pv.m.cfi := 1;
when 1 => pv.m.cfi := 0;
when others => pv.m.cfi := 0;
end case;
end if;
end if;
-- PCI state machine
case pr.m.state is
when pm_idle =>
if pci.gnt = '0' and (pci.frame and pci.irdy) = '1' then
if phyi.m_request = '1' then pv.m.state := pm_addr;
else pv.m.state := pm_dr_bus; end if;
end if;
pv.m.cfi := 0;
when pm_addr =>
pv.m.state := pm_m_data;
when pm_m_data =>
if pr.po.frame = '0' or (pr.po.frame and pci.trdy and pci.stop and not phyi.m_mabort) = '1' then
pv.m.state := pm_m_data;
elsif (pr.po.frame and (phyi.m_mabort or not pci.stop)) = '1' then
pv.m.state := pm_s_tar;
else
pv.m.state := pm_turn_ar;
end if;
when pm_turn_ar =>
if pci.gnt = '0' then
if phyi.m_request = '1' then pv.m.state := pm_addr; -- remove if no back-to-back
else pv.m.state := pm_dr_bus; end if;
else
pv.m.state := pm_idle;
end if;
when pm_s_tar =>
if pci.gnt = '0' then pv.m.state := pm_dr_bus;
else pv.m.state := pm_idle; end if;
when pm_dr_bus =>
if pci.gnt = '1' then pv.m.state := pm_idle;
elsif phyi.m_request = '1' then pv.m.state := pm_addr; end if;
pv.m.cfi := 0;
when others =>
end case;
if phyi.pr_m_fstate = pmf_fifo then
if (phyi.pv_m_cfifo(0).valid = '1' and phyi.pv_m_cfifo(1).valid = '1' and phyi.pv_m_cfifo(2).valid = '1')
or (phyi.pv_m_cfifo(0).valid = '1' and phyi.pr_m_done_fifo = '1' and not (phyi.pv_m_cfifo(1).valid = '0' and phyi.pv_m_cfifo(2).valid = '1')) then
pv.m.hold(0) := '0';
end if;
if ((pi.trdy or pi.irdy) = '0' and (pr.m.state = pm_m_data or pr.m.state = pm_turn_ar or pr.m.state = pm_s_tar))
or (phyi.pr_m_abort(0)) = '1' then
if phyi.pr_m_cfifo(pv.m.cfi).last = '1' and pr.m.last(0) = '0' then pv.m.last(0) := '1'; end if; -- This is the last data phase
pv.m.last(1) := pr.m.last(0);
if phyi.pr_m_done_fifo = '1' and phyi.pr_m_cfifo(pv.m.cfi).valid = '0' then pv.m.last(1) := '1'; end if; -- This is the last data phase
pv.m.hold(1) := pr.m.hold(0);
end if;
if (pr.m.state = pm_m_data or pr.m.state = pm_addr) and phyi.pr_m_cfifo(pv.m.cfi).hold = '1' then pv.m.hold(0) := '1'; end if; -- Transfer not done but no avalible fifo => deassert IRDY#
if (pr.m.state = pm_s_tar or pr.m.state = pm_turn_ar) then
pv.m.last := (others => '0');
pv.m.hold(0) := '0';
end if;
if phyi.pr_m_cfifo(0).last = '1' and phyi.pr_m_first(0) = '1' and pr.m.state = pm_addr and (phyi.pr_m_cbe_cmd = MEM_WRITE or phyi.pr_m_cbe_cmd = CONF_WRITE or phyi.pr_m_cbe_cmd = IO_WRITE) then pv.m.last := "11"; end if; -- Single data phase
if phyi.pr_m_first(1) = '1' and pr.m.state = pm_m_data and phyi.pr_m_cfifo(pv.m.cfi).last = '1' then pv.m.last(0) := '1'; end if; -- This is the last data phase
end if;
if phyi.pr_m_fstate = pmf_idle then
pv.m.last := (others => '0');
pv.m.hold := (others => '0');
end if;
-- PCI master latency timer timeout
pv.m.term := phyi.pv_m_term;
if pci.gnt = '1' then
if phyi.pr_m_ltimer = x"00" and pr.m.state = pm_m_data and phyi.pr_m_burst = '1' and phyi.pr_m_fstate /= pmf_idle then
pv.m.term(0) := '1';
end if;
end if;
-- FRAME#
if (pci.frame and pci.irdy and not pci.gnt and phyi.m_request) = '1' -- Address phase
or (pr.po.frame = '0' and phyi.m_mabort = '0' -- Not Master abort
and (pr.po.irdy or pci.stop) = '1' -- Not Disconnect
and ((phyi.pr_m_first(0) or not (pr.po.irdy or pci.trdy)) and (phyi.pr_m_cfifo(pv.m.cfi).last or pv.m.term(0))) = '0') then -- Not last data phase
pv.po.frame := '0';
end if;
-- IRDY#
if (pr.po.frame = '0' and phyi.m_mabort = '0' and (pr.m.hold(0) = '0' or (not pr.po.irdy and (pci.trdy and pci.stop)) = '1')) -- Access ongoing, not Master abort, not hold (no data available)
or (pr.po.frame and not phyi.m_mabort and not pr.po.irdy and (pci.trdy and pci.stop)) = '1' then -- Last data phase, not Master abort (if first access, can get master abort)
pv.po.irdy := '0';
end if;
-- Output enable ctrl signals
if (pci.frame and pci.irdy and not pci.gnt) = '1' -- Address phase
or pr.po.frame = '0' -- Access ongoing
or (not pr.po.irdy and (pci.stop and pci.trdy)) = '1' then -- Last data phase
pv.po.frameen := oeon;
pv.po.cbeen := (others => oeon);
end if;
pv.po.irdyen := pr.po.frameen;
-- REQ#
if (phyi.m_request) = '1' and (phyi.m_mabort or phyi.pr_m_abort(0)) = '0' then
pv.po.req := '0';
end if;
-- Output enable req
--pv.po.reqen := oeon; -- always on if not in reset
-- CBE#
if pr.po.irdy = '0' or pr.po.req = '0' or phyi.m_request = '1' then
if pr.m.state /= pm_idle and (pr.m.state /= pm_dr_bus) then pv.po.cbe := phyi.pr_m_cbe_data;
else pv.po.cbe := phyi.pr_m_cbe_cmd; end if;
else
pv.po.cbe := (others => '0');
end if;
-- Target -----------------------------------------------------------------------
pv.t.pi_irdy_or_trdy := pi.irdy or pi.trdy;
if (pr.t.pi_irdy_or_trdy and (not (pci.irdy or pr.po.trdy))) = '1' then
if phyi.pr_t_state = pt_s_data or phyi.pr_t_state = pt_turn_ar or phyi.pr_t_state = pt_backoff then
--pv.t.cfi := pr.t.cfi + 1;
case pr.t.cfi is
when 0 => pv.t.cfi := 1;
when 1 => pv.t.cfi := 2;
when others => pv.t.cfi := 0;
end case;
end if;
elsif ((not pr.t.pi_irdy_or_trdy) and (pci.irdy or pr.po.trdy)) = '1' then
if phyi.pr_t_state = pt_s_data or phyi.pr_t_state = pt_turn_ar or phyi.pr_t_state = pt_backoff then
--pv.t.cfi := pr.t.cfi - 1;
case pr.t.cfi is
when 2 => pv.t.cfi := 1;
when 1 => pv.t.cfi := 0;
when others => pv.t.cfi := 0;
end case;
end if;
end if;
pv.t.hold(0) := (phyi.pr_t_cfifo(pv.t.cfi).hold or pr.t.hold(0) or phyi.pv_t_hold_write) and phyi.pv_t_hold_reset;
pv.t.stop := (phyi.pr_t_cfifo(pv.t.cfi).stlast or pr.t.stop) and phyi.pv_t_hold_reset;
if phyi.pr_t_state = pt_s_data and phyi.pr_t_cfifo(pv.t.cfi).err = '1' and (phyi.pr_t_stoped = '0' or pr.t.abort = '1') and phyi.t_retry = '0' then pv.t.abort := '1';
else pv.t.abort := '0'; end if;
pv.t.diswithout := phyi.pv_t_diswithout;
-- Disconnect without data if CBE change in burst
if pci.cbe /= pi.cbe and (phyi.pr_t_state = pt_s_data and phyi.pr_t_fstate = ptf_write) then pv.t.diswithout := '1'; end if;
-- Parity error detected on address phase
if (phyi.pr_t_state = pt_idle or phyi.pr_t_state = pt_turn_ar) and pi.frame = '0' then
pv.t.addr_perr := (pci.par xor xorv(pi.ad & pi.cbe));
else
pv.t.addr_perr := '0';
end if;
-- TRDY#
if (phyi.pr_t_state = pt_s_data and ((phyi.t_ready and not phyi.t_retry) = '1' and pv.t.diswithout = '0' and
pv.t.abort = '0') and (pr.po.stop and not phyi.pr_t_stoped) = '1' and (phyi.pr_t_first_word or not pci.frame) = '1') -- Target accessed, data/fifo available, not stoped
or (not pr.po.trdy and pci.irdy) = '1' then -- During master waitstates
pv.po.trdy := '0';
end if;
-- STOP#
if
(pr.po.stop = '1' and phyi.pr_t_stoped = '0' and phyi.pr_t_lcount = "111" and pr.po.trdy = '1') -- latency timerout
or ((
((phyi.t_abort = '1' or pv.t.diswithout = '1') and (pci.irdy or pr.po.trdy) = '0' and pci.frame = '0') -- transfer done or disconnect without data (when cbe has changed during write to target)
or (pv.t.abort = '1' and (((pci.irdy or pr.po.trdy) = '0' and pci.frame = '0') or phyi.pr_t_first_word = '1')) -- To signal target abort
or ((phyi.pr_t_cfifo(0).valid and phyi.pr_t_cfifo(0).hold and phyi.pr_t_cfifo(0).stlast and phyi.pr_t_first_word) = '1') -- When first word in this access is the last word in the transfer
) and pr.po.stop = '1' and phyi.pr_t_stoped = '0') -- Only stop when master is ready (and target ready)
or (pr.po.stop = '0' and pci.frame = '0') -- When stop and frame are asserted
or (phyi.t_retry = '1' and pr.po.stop = '1' and phyi.pr_t_stoped = '0') then -- To signal retry
pv.po.stop := '0';
end if;
-- DEVSEL#
if (phyi.pr_t_state /= pt_s_data and phyi.pv_t_state = pt_s_data)
or (pr.po.devsel = '0' and (pci.frame and not pci.irdy and not (pr.po.trdy and pr.po.stop)) = '0'
and pv.t.abort = '0' -- To signal target abort
) then
pv.po.devsel := '0';
end if;
-- Output enable ctrl signals
if phyi.pv_t_state = pt_s_data or phyi.pv_t_state = pt_backoff then
pv.po.devselen := oeon; pv.po.trdyen := oeon; pv.po.stopen := oeon;
end if;
-- Master & Target --------------------------------------------------------------
-- AD
if (pr.m.state /= pm_idle and pr.m.state /= pm_dr_bus and phyi.pr_m_fstate = pmf_fifo) then
pv.po.ad := phyi.pr_m_cfifo(pv.m.cfi).data; -- PCI master data
elsif (phyi.pr_t_state = pt_s_data and phyi.pv_t_state /= pt_turn_ar) then
pv.po.ad := phyi.pr_t_cfifo(pv.t.cfi).data; -- PCI target data
else
pv.po.ad := phyi.pr_m_addr; -- Address
end if;
-- Output enable AD [target]
if phyi.pr_t_state = pt_s_data and phyi.pv_t_state /= pt_turn_ar and phyi.pr_t_cur_acc_0_read = '1'
and (pci.frame and (not pr.po.stop or not pr.po.trdy)) = '0' then
pv.po.aden := (others => oeon);
end if;
-- Output enable AD [master]
if (pcii.frame and pcii.irdy and not pcii.gnt) = '1'
or ((pr.m.state = pm_addr or pr.m.state = pm_m_data) and phyi.pr_m_fstate /= pmf_read and (pr.po.frame and (not pci.stop or not pci.trdy)) = '0') then
pv.po.aden := (others => oeon);
end if;
-- PAR
pv.po.par := xorv(pr.po.ad & pci.cbe);
-- Output enable PAR
pv.po.paren := pr.po.aden(15); -- AD[15] should be closest to PAR
-- PERR
pv.po.perr := pi.irdy or pi.trdy or not (pci.par xor xorv(pi.ad & pi.cbe)); -- Signal perr two cycles after data phase is completed
-- Output enable PERR
if phyi.pr_conf_comm_perren = '1' and -- Parity error response enable bit[6] = 1
(phyi.pr_m_perren(0) = '1' -- During master read
or (phyi.pr_t_state = pt_s_data and phyi.pr_t_cur_acc_0_read = '0') -- Write to target
or (pr.po.perr = '0' and pr.po.perren = oeon)) then -- Parity error on last phase
pv.po.perren := oeon;
end if;
-- SERR & Output enable for SERR
if phyi.pr_conf_comm_perren = '1' and phyi.pr_conf_comm_serren = '1' and pv.t.addr_perr = '1' then
pv.po.serren := oeon;
end if;
-- PCI reset --------------------------------------------------------------------
-- soft reset
if (pcisynrst and not phyi.pcisoftrst(2) and not phyi.pcisoftrst(1)) = '0' then -- Master reset
-- Master
pv.m.state := pm_idle;
pv.m.cfi := 0;
pv.m.hold := (others => '0');
pv.m.term := (others => '0');
end if;
if (pcisynrst and not phyi.pcisoftrst(2) and not phyi.pcisoftrst(0)) = '0' then -- Target reset
-- Target
pv.t.cfi := 0;
pv.t.hold := (others => '0');
pv.t.stop := '0';
pv.t.addr_perr := '0';
end if;
if (pcisynrst and not phyi.pcisoftrst(2)) = '0' then -- Hard reset
-- PCI signals
pv.po.frame := '1'; pv.po.irdy := '1'; pv.po.req := '1';
pv.po.trdy := '1'; pv.po.stop := '1';
pv.po.perr := '1'; pv.po.devsel := '1';
end if;
---------------------------------------------------------------------------------
piin <= pci;
prin <= pv;
poin <= pv.po;
phyo.pciv <= pci;
phyo.pr_m_state <= pr.m.state;
phyo.pr_m_last <= pr.m.last;
phyo.pr_m_hold <= pr.m.hold;
phyo.pr_m_term <= pr.m.term;
phyo.pr_t_hold <= pr.t.hold;
phyo.pr_t_stop <= pr.t.stop;
phyo.pr_t_abort <= pr.t.abort;
phyo.pr_t_diswithout <= pr.t.diswithout;
phyo.pr_t_addr_perr <= pr.t.addr_perr;
phyo.pcirsto(0) <= pcisynrst;
phyo.pr_po <= pr.po;
phyo.pio <= pi;
phyo.poo <= po;
-- PCI output signals
pcio.ad <= po.ad; pcio.vaden <= po.aden;
pcio.cbe <= po.cbe; pcio.cbeen <= po.cbeen;
pcio.frame <= po.frame; pcio.frameen <= po.frameen;
pcio.irdy <= po.irdy; pcio.irdyen <= po.irdyen;
pcio.trdy <= po.trdy; pcio.trdyen <= po.trdyen;
pcio.stop <= po.stop; pcio.stopen <= po.stopen;
pcio.devsel <= po.devsel; pcio.devselen <= po.devselen;
pcio.par <= po.par; pcio.paren <= po.paren;
pcio.perr <= po.perr; pcio.perren <= po.perren;
pcio.req <= po.req; pcio.reqen <= po.reqen;
pcio.int <= '0'; pcio.inten <= phyi.pciinten(0);
pcio.vinten <= phyi.pciinten;
pcio.rst <= phyi.pcirstout;
pcio.serr <= po.serr; pcio.serren <= po.serren;
if SCANTEST/=0 and GRLIB_CONFIG_ARRAY(GRLIB_EXTERNAL_TESTOEN)=0 then
if phyi.testen='1' then
pcio.vaden <= (others => phyi.testoen);
pcio.cbeen <= (others => phyi.testoen);
pcio.frameen <= phyi.testoen;
pcio.irdyen <= phyi.testoen;
pcio.trdyen <= phyi.testoen;
pcio.stopen <= phyi.testoen;
pcio.devselen <= phyi.testoen;
pcio.paren <= phyi.testoen;
pcio.perren <= phyi.testoen;
pcio.reqen <= phyi.testoen;
pcio.inten <= phyi.testoen;
pcio.vinten <= (others => phyi.testoen);
pcio.rst <= phyi.testoen xor oeon;
pcio.serren <= phyi.testoen;
end if;
end if;
-- Unused signals
pcio.lock <= oeoff; pcio.locken <= oeoff;
pcio.aden <= oeoff; pcio.ctrlen <= oeoff;
pcio.pme_enable <= oeoff; pcio.pme_clear <= oeoff;
pcio.power_state <= (others => oeoff);
end process;
-- po_keep <= poin_keep;
poin_keep(31 downto 0) <= poin.ad; po_keep.ad <= poin_keep(31 downto 0);
poin_keep(63 downto 32) <= poin.aden; po_keep.aden <= poin_keep(63 downto 32);
poin_keep(67 downto 64) <= poin.cbe; po_keep.cbe <= poin_keep(67 downto 64);
poin_keep(71 downto 68) <= poin.cbeen; po_keep.cbeen <= poin_keep(71 downto 68);
poin_keep( 72) <= poin.frame; po_keep.frame <= poin_keep( 72);
poin_keep( 73) <= poin.frameen; po_keep.frameen <= poin_keep( 73);
poin_keep( 74) <= poin.irdy; po_keep.irdy <= poin_keep( 74);
poin_keep( 75) <= poin.irdyen; po_keep.irdyen <= poin_keep( 75);
poin_keep( 76) <= poin.trdy; po_keep.trdy <= poin_keep( 76);
poin_keep( 77) <= poin.trdyen; po_keep.trdyen <= poin_keep( 77);
poin_keep( 78) <= poin.stop; po_keep.stop <= poin_keep( 78);
poin_keep( 79) <= poin.stopen; po_keep.stopen <= poin_keep( 79);
poin_keep( 80) <= poin.devsel; po_keep.devsel <= poin_keep( 80);
poin_keep( 81) <= poin.devselen; po_keep.devselen <= poin_keep( 81);
poin_keep( 82) <= poin.par; po_keep.par <= poin_keep( 82);
poin_keep( 83) <= poin.paren; po_keep.paren <= poin_keep( 83);
poin_keep( 84) <= poin.perr; po_keep.perr <= poin_keep( 84);
poin_keep( 85) <= poin.perren; po_keep.perren <= poin_keep( 85);
poin_keep( 86) <= poin.lock; po_keep.lock <= poin_keep( 86);
poin_keep( 87) <= poin.locken; po_keep.locken <= poin_keep( 87);
poin_keep( 88) <= poin.req; po_keep.req <= poin_keep( 88);
poin_keep( 89) <= poin.reqen; po_keep.reqen <= poin_keep( 89);
poin_keep( 90) <= poin.serren; po_keep.serren <= poin_keep( 90);
po_keep.inten <= phyi.pciinten(0);
po_keep.vinten <= phyi.pciinten;
xarst <= phyi.testrst when scantest/=0 and phyi.testen='1' else pcirst(0);
phyreg : process(pciclk, phyi.pciasyncrst, pcirst, xarst)
begin
if rising_edge(pciclk) then
pr <= prin;
pi <= piin;
po <= po_keep;
if iotmact /= '0' then
po.ad <= iotdout(31 downto 0);
po.cbe <= iotdout(35 downto 32);
po.frame <= iotdout(36);
po.irdy <= iotdout(37);
po.trdy <= iotdout(38);
po.par <= iotdout(39);
po.perr <= iotdout(40);
po.serr <= iotdout(41);
po.devsel <= iotdout(42);
po.stop <= iotdout(43);
po.req <= iotdout(44);
po.reqen <= oeon;
if iotmoe /= '0' then
po.aden <= (others => oeon); po.cbeen <= (others => oeon); po.frameen <= oeon;
po.devselen <= oeon; po.trdyen <= oeon; po.irdyen <= oeon; po.stopen <= oeon;
po.paren <= oeon; po.perren <= oeon; po.locken <= oeon;
po.inten <= oeon; po.vinten <= (others => oeon); po.serren <= oeon;
else
po.aden <= (others => oeoff); po.cbeen <= (others => oeoff); po.frameen <= oeoff;
po.devselen <= oeoff; po.trdyen <= oeoff; po.irdyen <= oeoff; po.stopen <= oeoff;
po.paren <= oeoff; po.perren <= oeoff; po.locken <= oeoff;
po.inten <= oeoff; po.vinten <= (others => oeoff); po.serren <= oeoff;
end if;
end if;
pcisynrst <= pcirst(1) and pcirst(2);
pcirst(0) <= pcirst(1) and pcirst(2);
pcirst(1) <= pcirst(2); pcirst(2) <= '1';
end if;
if phyi.pciasyncrst = '0' then pcirst <= (others => '0'); end if;
if xarst = '0' then -- asynch reset required
po.ad <= (others => '1'); pi.ad <= (others => '1'); -- for virtex-4 all registers in IOB need to have same reset
po.trdy <= '1'; pi.trdy <= '1'; po.stop <= '1'; pi.stop <= '1';
po.irdy <= '1'; pi.irdy <= '1'; po.frame <= '1'; pi.frame <= '1';
po.cbe <= (others => '1'); pi.cbe <= (others => '1');
po.par <= '1'; pi.par <= '1';
po.perr <= '1'; pi.perr <= '1';
po.devsel <= '1'; pi.devsel <= '1';
pi.serr <= '1';
po.aden <= (others => oeoff); po.cbeen <= (others => oeoff); po.frameen <= oeoff;
po.devselen <= oeoff; po.trdyen <= oeoff; po.irdyen <= oeoff; po.stopen <= oeoff;
po.paren <= oeoff; po.perren <= oeoff; po.locken <= oeoff; po.reqen <= oeoff;
po.inten <= oeoff; po.vinten <= (others => oeoff); po.serren <= oeoff;
end if;
end process;
iotdin(45) <= pi.idsel;
iotdin(44) <= pi.gnt;
iotdin(43) <= pi.stop;
iotdin(42) <= pi.devsel;
iotdin(41) <= pi.serr;
iotdin(40) <= pi.perr;
iotdin(39) <= pi.par;
iotdin(38) <= pi.trdy;
iotdin(37) <= pi.irdy;
iotdin(36) <= pi.frame;
iotdin(35 downto 32) <= pi.cbe;
iotdin(31 downto 0) <= pi.ad;
end;
| gpl-3.0 | 7242d969f93c1d41b2af5073b12217a7 | 0.536027 | 3.09706 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/misc/ahbram.vhd | 1 | 9,220 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbram
-- File: ahbram.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Jan Andersson - Aeroflex Gaisler
-- Description: AHB ram. 0-waitstate read, 0/1-waitstate write.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
entity ahbram is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := DEFMEMTECH;
kbytes : integer := 1;
pipe : integer := 0;
maccsz : integer := AHBDW;
scantest: integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbram is
constant abits : integer := log2ext(kbytes) + 8 - maccsz/64;
constant dw : integer := maccsz;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBRAM, 0, abits+2+maccsz/64, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
others => zero32);
type reg_type is record
hwrite : std_ulogic;
hready : std_ulogic;
hsel : std_ulogic;
addr : std_logic_vector(abits-1+log2(dw/8) downto 0);
size : std_logic_vector(2 downto 0);
prdata : std_logic_vector((dw-1)*pipe downto 0);
pwrite : std_ulogic;
pready : std_ulogic;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RES : reg_type :=
(hwrite => '0', hready => '1', hsel => '0', addr => (others => '0'),
size => (others => '0'), prdata => (others => '0'), pwrite => '0',
pready => '1');
signal r, c : reg_type;
signal ramsel : std_logic_vector(dw/8-1 downto 0);
signal write : std_logic_vector(dw/8-1 downto 0);
signal ramaddr : std_logic_vector(abits-1 downto 0);
signal ramdata : std_logic_vector(dw-1 downto 0);
signal hwdata : std_logic_vector(dw-1 downto 0);
begin
comb : process (ahbsi, r, rst, ramdata)
variable bs : std_logic_vector(dw/8-1 downto 0);
variable v : reg_type;
variable haddr : std_logic_vector(abits-1 downto 0);
variable hrdata : std_logic_vector(dw-1 downto 0);
variable seldata : std_logic_vector(dw-1 downto 0);
variable raddr : std_logic_vector(3 downto 2);
variable adsel : std_logic;
begin
v := r; v.hready := '1'; bs := (others => '0');
v.pready := r.hready;
if pipe=0 then
adsel := r.hwrite or not r.hready;
else
adsel := r.hwrite or r.pwrite;
v.hready := r.hready or not r.pwrite;
end if;
if adsel = '1' then
haddr := r.addr(abits-1+log2(dw/8) downto log2(dw/8));
else
haddr := ahbsi.haddr(abits-1+log2(dw/8) downto log2(dw/8));
bs := (others => '0');
end if;
raddr := (others => '0');
v.pwrite := '0';
if pipe/=0 and (r.hready='1' or r.pwrite='0') then
v.addr := ahbsi.haddr(abits-1+log2(dw/8) downto 0);
end if;
if ahbsi.hready = '1' then
if pipe=0 then
v.addr := ahbsi.haddr(abits-1+log2(dw/8) downto 0);
end if;
v.hsel := ahbsi.hsel(hindex) and ahbsi.htrans(1);
v.size := ahbsi.hsize(2 downto 0);
v.hwrite := ahbsi.hwrite and v.hsel;
if pipe = 1 and v.hsel = '1' and ahbsi.hwrite = '0' and (r.pready='1' or ahbsi.htrans(0)='0') then
v.hready := '0';
v.pwrite := r.hwrite;
end if;
end if;
if r.hwrite = '1' then
case r.size is
when HSIZE_BYTE =>
bs(bs'left-conv_integer(r.addr(log2(dw/16) downto 0))) := '1';
when HSIZE_HWORD =>
for i in 0 to dw/16-1 loop
if i = conv_integer(r.addr(log2(dw/16) downto 1)) then
bs(bs'left-i*2 downto bs'left-i*2-1) := (others => '1');
end if;
end loop; -- i
when HSIZE_WORD =>
if dw = 32 then bs := (others => '1');
else
for i in 0 to dw/32-1 loop
if i = conv_integer(r.addr(log2(dw/8)-1 downto 2)) then
bs(bs'left-i*4 downto bs'left-i*4-3) := (others => '1');
end if;
end loop; -- i
end if;
when HSIZE_DWORD =>
if dw = 32 then null;
elsif dw = 64 then bs := (others => '1');
else
for i in 0 to dw/64-1 loop
if i = conv_integer(r.addr(3)) then
bs(bs'left-i*8 downto bs'left-i*8-7) := (others => '1');
end if;
end loop; -- i
end if;
when HSIZE_4WORD =>
if dw < 128 then null;
elsif dw = 128 then bs := (others => '1');
else
for i in 0 to dw/64-1 loop
if i = conv_integer(r.addr(3)) then
bs(bs'left-i*8 downto bs'left-i*8-7) := (others => '1');
end if;
end loop; -- i
end if;
when others => --HSIZE_8WORD
if dw < 256 then null;
else bs := (others => '1'); end if;
end case;
v.hready := not (v.hsel and not ahbsi.hwrite);
v.hwrite := v.hwrite and v.hready;
end if;
-- Duplicate read data on word basis, unless CORE_ACDM is enabled
if CORE_ACDM = 0 then
if dw = 32 then
seldata := ramdata;
elsif dw = 64 then
if r.size = HSIZE_DWORD then seldata := ramdata; else
if r.addr(2) = '0' then
seldata(dw/2-1 downto 0) := ramdata(dw-1 downto dw/2);
else
seldata(dw/2-1 downto 0) := ramdata(dw/2-1 downto 0);
end if;
seldata(dw-1 downto dw/2) := seldata(dw/2-1 downto 0);
end if;
elsif dw = 128 then
if r.size = HSIZE_4WORD then
seldata := ramdata;
elsif r.size = HSIZE_DWORD then
if r.addr(3) = '0' then seldata(dw/2-1 downto 0) := ramdata(dw-1 downto dw/2);
else seldata(dw/2-1 downto 0) := ramdata(dw/2-1 downto 0); end if;
seldata(dw-1 downto dw/2) := seldata(dw/2-1 downto 0);
else
raddr := r.addr(3 downto 2);
case raddr is
when "00" => seldata(dw/4-1 downto 0) := ramdata(4*dw/4-1 downto 3*dw/4);
when "01" => seldata(dw/4-1 downto 0) := ramdata(3*dw/4-1 downto 2*dw/4);
when "10" => seldata(dw/4-1 downto 0) := ramdata(2*dw/4-1 downto 1*dw/4);
when others => seldata(dw/4-1 downto 0) := ramdata(dw/4-1 downto 0);
end case;
seldata(dw-1 downto dw/4) := seldata(dw/4-1 downto 0) &
seldata(dw/4-1 downto 0) &
seldata(dw/4-1 downto 0);
end if;
else
seldata := ahbselectdata(ramdata, r.addr(4 downto 2), r.size);
end if;
else
seldata := ramdata;
end if;
if pipe = 0 then
v.prdata := (others => '0');
hrdata := seldata;
else
v.prdata := seldata;
hrdata := r.prdata;
end if;
if (not RESET_ALL) and (rst = '0') then
v.hwrite := RES.hwrite; v.hready := RES.hready;
end if;
write <= bs; for i in 0 to dw/8-1 loop ramsel(i) <= v.hsel or r.hwrite; end loop;
ramaddr <= haddr; c <= v;
ahbso.hrdata <= ahbdrivedata(hrdata);
ahbso.hready <= r.hready;
end process;
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
-- Select correct write data
hwdata <= ahbreaddata(ahbsi.hwdata, r.addr(4 downto 2),
conv_std_logic_vector(log2(dw/8), 3));
aram : syncrambw generic map (tech, abits, dw, scantest) port map (
clk, ramaddr, hwdata, ramdata, ramsel, write, ahbsi.testin);
reg : process (clk)
begin
if rising_edge(clk) then
r <= c;
if RESET_ALL and rst = '0' then
r <= RES;
end if;
end if;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbram" & tost(hindex) &
": AHB SRAM Module rev 1, " & tost(kbytes) & " kbytes");
-- pragma translate_on
end;
| gpl-3.0 | 01a4cd133d53945a025e9a679bf5db8f | 0.555748 | 3.364964 | false | false | false | false |
yishinli/emc2 | src/hal/drivers/mesa-hostmot2/firmware/src/usbram.vhd | 1 | 18,614 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
--
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
-- http://www.mesanet.com
--
-- This program is is licensed under a disjunctive dual license giving you
-- the choice of one of the two following sets of free software/open source
-- licensing terms:
--
-- * GNU General Public License (GPL), version 2.0 or later
-- * 3-clause BSD License
--
--
-- The GNU GPL License:
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- The 3-clause BSD License:
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- * Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- * Neither the name of Mesa Electronics nor the names of its
-- contributors may be used to endorse or promote products
-- derived from this software without specific prior written
-- permission.
--
--
-- Disclaimer:
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Created from usbram.obj
-- On 6/ 5/2008
entity usbram is
port (
addra: in std_logic_vector(10 downto 0);
addrb: in std_logic_vector(10 downto 0);
clk: in std_logic;
dina: in std_logic_vector(7 downto 0);
douta: out std_logic_vector(7 downto 0);
doutb: out std_logic_vector(7 downto 0);
wea: in std_logic);
end usbram;
architecture syn of usbram is
type ram_type is array (0 to 2047) of std_logic_vector(7 downto 0);
signal RAM : ram_type :=
(
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
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x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00");
signal daddra: std_logic_vector(10 downto 0);
signal daddrb: std_logic_vector(10 downto 0);
begin
ausbram: process (clk)
begin
if (clk'event and clk = '1') then
if (wea = '1') then
RAM(conv_integer(addra)) <= dina;
end if;
daddra <= addra;
daddrb <= addrb;
end if; -- clk
end process;
douta <= RAM(conv_integer(daddra));
doutb <= RAM(conv_integer(daddrb));
end;
| lgpl-2.1 | 7aae2236a632efe9f73adc9d84db6c51 | 0.472386 | 1.998711 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/misc/gptimer.vhd | 1 | 21,915 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: gptimer
-- File: gptimer.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: This unit implemets a set of general-purpose timers with a
-- common prescaler. Then number of timers and the width of
-- the timers is propgrammable through generics
--
-- Revision 1 of this core merges functionality of the GRTIMET unit:
--
-- This unit also implements the use of an external clock source for the
-- timers.
--
-- This unit also implements a latching register for each timer, latching the
-- timer value on the occurence of an interrupt on the apbi.priq input. The
-- interrupt selection in possible via a mask register.
--
-- This unit also implements loading of all timers on the event of a selected
-- incoming interrupt.
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.misc.all;
--pragma translate_off
use std.textio.all;
--pragma translate_on
entity gptimer is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
sepirq : integer := 0; -- use separate interrupts for each timer
sbits : integer := 16; -- scaler bits
ntimers : integer range 1 to 7 := 1; -- number of timers
nbits : integer := 32; -- timer bits
wdog : integer := 0;
ewdogen : integer := 0;
glatch : integer := 0;
gextclk : integer := 0;
gset : integer := 0;
gelatch : integer range 0 to 2 := 0;
wdogwin : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gpti : in gptimer_in_type;
gpto : out gptimer_out_type
);
end;
architecture rtl of gptimer is
constant REVISION : integer := 1;
constant pconfig : apb_config_type := (
0 => ahb_device_reg (VENDOR_GAISLER, GAISLER_GPTIMER, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
type timer_reg is record
enable : std_ulogic; -- enable counter
load : std_ulogic; -- load counter
restart : std_ulogic; -- restart counter
irqpen : std_ulogic; -- interrupt pending
irqen : std_ulogic; -- interrupt enable
irq : std_ulogic; -- interrupt pulse
chain : std_ulogic; -- chain with previous timer
value : std_logic_vector(nbits-1 downto 0);
reload : std_logic_vector(nbits-1 downto 0);
latch : std_logic_vector(glatch*(nbits-1) downto 0);
end record;
type timer_reg_vector is array (Natural range <> ) of timer_reg;
constant TBITS : integer := log2x(ntimers+1);
type registers is record
scaler : std_logic_vector(sbits-1 downto 0);
reload : std_logic_vector(sbits-1 downto 0);
tick : std_ulogic;
tsel : integer range 0 to ntimers;
timers : timer_reg_vector(1 to ntimers);
dishlt : std_ulogic;
wdogn : std_ulogic;
wdog : std_ulogic;
wdogdis : std_ulogic;
wdognmi : std_ulogic;
wdogwc : std_logic_vector(15 downto 0);
wdogwcr : std_logic_vector(15 downto 0);
end record;
type registers2 is record
setdis : std_ulogic;
latchdis : std_ulogic;
elatchen : std_ulogic;
latchsel : std_logic_vector(NAHBIRQ-1 downto 0);
latchen : std_ulogic;
latchdel : std_ulogic;
extclken : std_ulogic;
extclk : std_logic_vector(2 downto 0);
seten : std_ulogic;
setdel : std_ulogic;
end record;
constant NMI : integer := 15;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
function RESVAL_FUNC return registers is
variable vres : registers;
begin
vres.scaler := (others => '1');
vres.reload := (others => '1');
vres.tick := '0';
vres.tsel := 0;
for i in 1 to ntimers loop
vres.timers(i).enable := '0';
vres.timers(i).load := '0';
vres.timers(i).restart := '0';
vres.timers(i).irqpen := '0';
vres.timers(i).irqen := '0';
vres.timers(i).irq := '0';
vres.timers(i).chain := '0';
vres.timers(i).value := (others => '0');
vres.timers(i).reload := (others => '0');
vres.timers(i).latch := (others => '0');
end loop;
if wdog /= 0 then
vres.timers(ntimers).enable := '1'; -- May be overriden by ewdogen
vres.timers(ntimers).load := '1';
vres.timers(ntimers).reload := conv_std_logic_vector(wdog, nbits);
vres.timers(ntimers).irqen := '1';
end if;
vres.dishlt := '0';
vres.wdogn := '1';
vres.wdog := '0';
vres.wdogdis := '0';
vres.wdognmi := '0';
vres.wdogwc := (others => '0');
vres.wdogwcr := (others => '0');
return vres;
end function RESVAL_FUNC;
constant RESVAL : registers := RESVAL_FUNC;
constant RESVAL2 : registers2 := (
setdis => '0',
latchdis => '0',
elatchen => '0',
latchsel => (others => '0'),
latchen => '0',
latchdel => '0',
extclken => '0',
extclk => (others => '0'),
seten => '0',
setdel => '0');
signal r, rin : registers;
signal r2, rin2 : registers2;
begin
comb : process(rst, r, r2, apbi, gpti)
variable scaler : std_logic_vector(sbits downto 0);
variable readdata, timer1 : std_logic_vector(31 downto 0);
variable res, addin : std_logic_vector(nbits-1 downto 0);
variable v : registers;
variable z : std_ulogic;
variable vtimers : timer_reg_vector(0 to ntimers);
variable xirq : std_logic_vector(NAHBIRQ-1 downto 0);
variable nirq : std_logic_vector(0 to ntimers-1);
variable tick : std_logic_vector(1 to 7);
variable latch : std_ulogic;
variable latchval : std_logic_vector(NAHBIRQ-1 downto 0);
variable latchd : std_ulogic;
variable v2 : registers2;
variable wdogwc : std_logic_vector(r.wdogwc'left+1 downto 0);
variable timeren : std_logic;
begin
v := r; v2 := r2; v.tick := '0'; tick := (others => '0'); latch := '0';
latchval := apbi.pirq; latchd := '0';
vtimers(0) := ('0', '0', '0', '0', '0', '0', '0',
zero32(nbits-1 downto 0), zero32(nbits-1 downto 0),
zero32(glatch*(nbits-1) downto 0));
vtimers(1 to ntimers) := r.timers; xirq := (others => '0');
for i in 1 to ntimers loop
v.timers(i).irq := '0'; v.timers(i).load := '0';
tick(i) := r.timers(i).irq;
end loop;
v.wdog := r.timers(ntimers).irqpen and not r.wdogdis;
v.wdogn := not v.wdog;
-- wdog timer window counter
if wdogwin /= 0 and wdog /= 0 then
wdogwc := ('0' & r.wdogwc) - 1; -- decrement scaler
if wdogwc(wdogwc'left) = '0' then
v.wdogwc := wdogwc(v.wdogwc'range);
end if;
else
wdogwc := (others => '0');
end if;
-- scaler operation
timeren := '0'; -- set if any of the timers are enabled
for i in 1 to ntimers loop timeren := timeren or r.timers(i).enable; end loop;
scaler := ('0' & r.scaler) - 1; -- decrement scaler
if gextclk = 1 then -- optional external timer clock
v2.extclk := r2.extclk(1 downto 0) & gpti.extclk;
end if;
if ((gextclk=0) or (gextclk=1 and r2.extclken='0') or
(gextclk=1 and r2.extclken='1' and r2.extclk(2 downto 1) = "01")) then
if (not gpti.dhalt or r.dishlt) = '1' -- halt timers in debug mode.
and timeren = '1' then -- scaler is halted when all timers are disabled
if (scaler(sbits) = '1') then
v.scaler := r.reload; v.tick := '1'; -- reload scaler
else v.scaler := scaler(sbits-1 downto 0); end if;
end if;
end if;
-- timer operation
if (r.tick = '1') or (r.tsel /= 0) then
if r.tsel = ntimers then v.tsel := 0;
else v.tsel := r.tsel + 1; end if;
end if;
res := vtimers(r.tsel).value - 1; -- decrement selected timer
if (res(nbits-1) = '1') and ((vtimers(r.tsel).value(nbits-1) = '0'))
then z := '1'; else z := '0'; end if; -- undeflow detect
-- update corresponding register and generate irq
for i in 1 to ntimers-1 loop nirq(i) := r.timers(i).irq; end loop;
nirq(0) := r.timers(ntimers).irq;
for i in 1 to ntimers loop
if i = r.tsel then
if (r.timers(i).enable = '1') and
(((r.timers(i).chain and nirq(i-1)) or not (r.timers(i).chain)) = '1')
then
v.timers(i).irq := z and not r.timers(i).load;
if (v.timers(i).irq and r.timers(i).irqen) = '1' then
v.timers(i).irqpen := '1';
end if;
v.timers(i).value := res;
if (z and not r.timers(i).load) = '1' then
v.timers(i).enable := r.timers(i).restart;
if r.timers(i).restart = '1' then
v.timers(i).value := r.timers(i).reload;
end if;
end if;
end if;
end if;
if r.timers(i).load = '1' then
v.timers(i).value := r.timers(i).reload;
if (i = ntimers) and wdogwin /= 0 and wdog /= 0 then
v.wdogwc := r.wdogwcr;
if wdogwc(wdogwc'left) = '0' then
v.timers(i).irq := '1';
v.timers(i).irqpen := '1';
end if;
end if;
end if;
end loop;
-- timer external set
if gset = 1 then
if gelatch /= 0 and r2.elatchen = '1' then
latchval := gpti.latchv;
end if;
if NAHBIRQ <= 32 then
for i in NAHBIRQ-1 downto 0 loop
latch := latch or (v2.latchsel(i) and latchval(i));
if gelatch = 2 then latchd := latchd or (v2.latchsel(i) and gpti.latchd(i)); end if;
end loop;
else
for i in 31 downto 0 loop
latch := latch or (v2.latchsel(i) and latchval(i));
if gelatch = 2 then latchd := latchd or (v2.latchsel(i) and gpti.latchd(i)); end if;
end loop;
end if;
if gelatch = 2 and (r2.seten = '1' and r2.elatchen = '1') then
if latchd = '1' then
v2.setdis := '1';
end if;
if r2.setdis = '1' and r.tsel = 0 then
v2.setdis := '0'; v2.seten := '0'; v2.setdel := '0';
end if;
end if;
if (latch='1' and r2.seten='1' and r.tsel = 0) or
(r2.setdel = '1' and r2.seten='1' and r.tsel = 0) then
for i in 1 to ntimers loop
v.timers(i).value := r.timers(i).reload;
end loop;
v2.setdel := '0';
if gelatch < 2 or (gelatch = 2 and (r2.elatchen = '0' or v2.setdis = '1')) then
v2.seten := '0';
if gelatch = 2 then v2.setdis := '0'; end if;
end if;
elsif latch='1' and r2.seten='1' and r.tsel /= 0 then
v2.setdel := '1';
end if;
end if;
if sepirq /= 0 then
for i in 1 to ntimers loop
xirq(i-1+pirq) := r.timers(i).irq and r.timers(i).irqen;
end loop;
else
for i in 1 to ntimers loop
xirq(pirq) := xirq(pirq) or (r.timers(i).irq and r.timers(i).irqen);
end loop;
end if;
if wdog /= 0 then
if (r.wdognmi and r.timers(ntimers).irq and r.timers(ntimers).irqen) = '1' then
xirq(NMI) := '1';
end if;
end if;
-- read registers
readdata := (others => '0');
case apbi.paddr(6 downto 2) is
when "00000" => readdata(sbits-1 downto 0) := r.scaler;
when "00001" => readdata(sbits-1 downto 0) := r.reload;
when "00010" =>
readdata(2 downto 0) := conv_std_logic_vector(ntimers, 3) ;
readdata(7 downto 3) := conv_std_logic_vector(pirq, 5) ;
if (sepirq /= 0) then readdata(8) := '1'; end if;
readdata(9) := r.dishlt;
if gextclk = 1 then readdata(10) := r2.extclken; end if;
if glatch = 1 then readdata(11) := r2.latchen; end if;
if gset = 1 then readdata(12) := r2.seten; end if;
if gelatch /= 0 then readdata(13) := r2.elatchen; end if;
when "00011" =>
if glatch = 1 then
if NAHBIRQ <= 32 then
for i in NAHBIRQ-1 downto 0 loop
readdata(i) := r2.latchsel(i);
end loop;
else
for i in 31 downto 0 loop
readdata(i) := r2.latchsel(i);
end loop;
end if;
end if;
when others =>
for i in 1 to ntimers loop
if conv_integer(apbi.paddr(6 downto 4)) = i then
case apbi.paddr(3 downto 2) is
when "00" => readdata(nbits-1 downto 0) := r.timers(i).value;
when "01" => readdata(nbits-1 downto 0) := r.timers(i).reload;
when "10" =>
if wdog /= 0 and i = ntimers then
if wdogwin /= 0 then
readdata(31 downto 16) := r.wdogwcr;
end if;
readdata(8 downto 7) := r.wdogdis & r.wdognmi;
end if;
readdata(6 downto 0) :=
gpti.dhalt & r.timers(i).chain &
r.timers(i).irqpen & r.timers(i).irqen & r.timers(i).load &
r.timers(i).restart & r.timers(i).enable;
when "11" =>
if glatch = 1 then
readdata(glatch*(nbits-1) downto 0) := r.timers(i).latch;
end if;
when others =>
end case;
end if;
end loop;
end case;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(6 downto 2) is
when "00000" => v.scaler := apbi.pwdata(sbits-1 downto 0);
when "00001" => v.reload := apbi.pwdata(sbits-1 downto 0);
v.scaler := apbi.pwdata(sbits-1 downto 0);
when "00010" => v.dishlt := apbi.pwdata(9);
if gextclk = 1 then v2.extclken := apbi.pwdata(10); end if;
if glatch = 1 then v2.latchen := apbi.pwdata(11); end if;
if gset = 1 then v2.seten := apbi.pwdata(12); end if;
if gelatch /= 0 then v2.elatchen := apbi.pwdata(13); end if;
for i in 1 to ntimers loop
v.timers(i).enable := r.timers(i).enable or apbi.pwdata(15+i);
end loop;
when "00011" =>
if glatch=1 then
if NAHBIRQ <= 32 then
for i in NAHBIRQ-1 downto 0 loop
v2.latchsel(i) := apbi.pwdata(i);
end loop;
else
for i in 31 downto 0 loop
v2.latchsel(i) := apbi.pwdata(i);
end loop;
end if;
end if;
when others =>
for i in 1 to ntimers loop
if conv_integer(apbi.paddr(6 downto 4)) = i then
case apbi.paddr(3 downto 2) is
when "00" => v.timers(i).value := apbi.pwdata(nbits-1 downto 0);
when "01" => v.timers(i).reload := apbi.pwdata(nbits-1 downto 0);
when "10" => if wdog /= 0 and i = ntimers then
if wdogwin /= 0 then
v.wdogwcr := apbi.pwdata(31 downto 16);
end if;
v.wdogdis := apbi.pwdata(8);
v.wdognmi := apbi.pwdata(7);
end if;
v.timers(i).chain := apbi.pwdata(5);
v.timers(i).irqpen := v.timers(i).irqpen and not apbi.pwdata(4);
v.timers(i).irqen := apbi.pwdata(3);
v.timers(i).load := apbi.pwdata(2);
v.timers(i).restart := apbi.pwdata(1);
v.timers(i).enable := apbi.pwdata(0);
when others =>
end case;
end if;
end loop;
end case;
end if;
-- timer latches
if glatch=1 then
latch := '0'; latchd := '0';
if gelatch /= 0 and r2.elatchen = '1' then
latchval := gpti.latchv;
end if;
if NAHBIRQ <= 32 then
for i in NAHBIRQ-1 downto 0 loop
latch := latch or (v2.latchsel(i) and latchval(i));
if gelatch = 2 then latchd := latchd or (v2.latchsel(i) and gpti.latchd(i)); end if;
end loop;
else
for i in 31 downto 0 loop
latch := latch or (v2.latchsel(i) and latchval(i));
if gelatch = 2 then latchd := latchd or (v2.latchsel(i) and gpti.latchd(i)); end if;
end loop;
end if;
if gelatch /= 0 and (r2.latchen = '1' and r2.elatchen = '1') then
if latchd = '1' then
v2.latchdis := '1';
end if;
if r2.latchdis = '1' and r.tsel = 0 then
v2.latchdis := '0'; v2.latchen := '0'; v2.latchdel := '0';
end if;
end if;
if ((latch='1' and r2.latchen='1' and r.tsel = 0) or
(r2.latchdel = '1' and r2.latchen='1' and r.tsel = 0)) then
for i in 1 to ntimers loop
v.timers(i).latch := r.timers(i).value(glatch*(nbits-1) downto 0);
end loop;
v2.latchdel := '0';
if gelatch < 2 or (gelatch = 2 and (r2.elatchen = '0' or v2.latchdis = '1')) then
v2.latchen := '0';
if gelatch = 2 then v2.latchdis := '0'; end if;
end if;
elsif latch='1' and r2.latchen='1' and r.tsel /= 0 then
v2.latchdel := '1';
end if;
end if;
-- reset operation
if (not RESET_ALL) and (rst = '0') then
for i in 1 to ntimers loop
v.timers(i).enable := RESVAL.timers(i).enable;
v.timers(i).irqen := RESVAL.timers(i).irqen;
v.timers(i).irqpen := RESVAL.timers(i).irqpen;
v.timers(i).irq := RESVAL.timers(i).irq;
end loop;
v.scaler := RESVAL.scaler; v.reload := RESVAL.reload;
v.tsel := RESVAL.tsel; v.dishlt := RESVAL.dishlt;
v.timers(ntimers).irq := RESVAL.timers(ntimers).irq;
if (wdog /= 0) then
if ewdogen /= 0 then v.timers(ntimers).enable := gpti.wdogen;
else v.timers(ntimers).enable := RESVAL.timers(ntimers).enable; end if;
v.timers(ntimers).load := RESVAL.timers(ntimers).load;
v.timers(ntimers).reload := RESVAL.timers(ntimers).reload;
v.timers(ntimers).chain := RESVAL.timers(ntimers).chain;
v.timers(ntimers).irqen := RESVAL.timers(ntimers).irqen;
v.timers(ntimers).irqpen := RESVAL.timers(ntimers).irqpen;
v.timers(ntimers).restart := RESVAL.timers(ntimers).restart;
end if;
v.wdogdis := RESVAL.wdogdis; v.wdognmi := RESVAL.wdognmi;
v.wdogwcr := RESVAL.wdogwcr;
if glatch = 1 then
for i in 1 to ntimers loop v.timers(i).latch := RESVAL.timers(i).latch; end loop;
if gelatch /= 0 then v2.elatchen := RESVAL2.elatchen; end if;
if gelatch = 2 then v2.setdis := '0'; v2.latchdis := '0'; end if;
v2.latchen := RESVAL2.latchen; v2.latchdel := RESVAL2.latchdel;
v2.latchsel := RESVAL2.latchsel;
end if;
if gextclk = 1 then
v2.extclken := RESVAL2.extclken;
v2.extclk := RESVAL2.extclk;
end if;
if gset = 1 then v2.seten := RESVAL2.seten; v2.setdel := RESVAL2.setdel; end if;
end if;
if wdog = 0 then v.wdogdis := '0'; v.wdognmi := '0'; end if;
if wdogwin = 0 then v.wdogwc := (others => '0'); v.wdogwcr := (others => '0'); end if;
if glatch = 0 then
for i in 1 to ntimers loop v.timers(i).latch := (others => '0'); end loop;
v2.latchen := '0'; v2.latchdel := '0'; v2.latchsel := (others => '0');
end if;
if glatch = 0 or gelatch = 0 then v2.elatchen := '0'; end if;
if glatch = 0 or gelatch < 2 then v2.latchdis := '0'; v2.setdis := '0'; end if;
if gextclk = 0 then v2.extclken := '0'; v2.extclk := (others => '0'); end if;
if gset = 0 then v2.seten := '0'; v2.setdel := '0'; end if;
timer1 := (others => '0'); timer1(nbits-1 downto 0) := r.timers(1).value;
rin <= v; rin2 <= v2;
apbo.prdata <= readdata; -- drive apb read bus
apbo.pirq <= xirq;
apbo.pindex <= pindex;
gpto.tick <= r.tick & tick;
gpto.timer1 <= timer1; -- output timer1 value for debugging
gpto.wdogn <= r.wdogn;
gpto.wdog <= r.wdog;
end process;
apbo.pconfig <= pconfig;
-- registers
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin; r2 <= rin2;
if RESET_ALL and rst = '0' then
r <= RESVAL; r2 <= RESVAL2;
if wdog /= 0 and ewdogen /= 0 then
r.timers(ntimers).enable <= gpti.wdogen;
end if;
end if;
end if;
end process;
-- boot message
-- pragma translate_off
bootmsg : report_version
generic map ("gptimer" & tost(pindex) &
": Timer Unit rev " & tost(REVISION) &
", " & tost(sbits) & "-bit scaler, " & tost(ntimers) &
" " & tost(nbits) & "-bit timers" & ", irq " & tost(pirq));
-- pragma translate_on
end;
| gpl-3.0 | 185f62b3340ff3d3231ba00f2c29a0fe | 0.549989 | 3.417277 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-avnet-3s1500/config.vhd | 1 | 7,557 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- board options
constant CFG_ADS_DAU_MEZZ : integer := 1;
-- Technology and synthesis options
constant CFG_FABTECH : integer := spartan3;
constant CFG_MEMTECH : integer := spartan3;
constant CFG_PADTECH : integer := spartan3;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := spartan3;
constant CFG_CLKMUL : integer := (3);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 1;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 1;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 1;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 4 + 64*0;
constant CFG_ATBSZ : integer := 4;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000013#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- CAN 2.0 interface
constant CFG_CAN : integer := 1;
constant CFG_CANIO : integer := 16#C00#;
constant CFG_CANIRQ : integer := (13);
constant CFG_CANLOOP : integer := 0;
constant CFG_CAN_SYNCRST : integer := 0;
constant CFG_CANFT : integer := 0;
-- GRPCI2 interface
constant CFG_GRPCI2_MASTER : integer := 1;
constant CFG_GRPCI2_TARGET : integer := 1;
constant CFG_GRPCI2_DMA : integer := 0;
constant CFG_GRPCI2_VID : integer := 16#1AC8#;
constant CFG_GRPCI2_DID : integer := 16#0054#;
constant CFG_GRPCI2_CLASS : integer := 16#000000#;
constant CFG_GRPCI2_RID : integer := 16#00#;
constant CFG_GRPCI2_CAP : integer := 16#40#;
constant CFG_GRPCI2_NCAP : integer := 16#00#;
constant CFG_GRPCI2_BAR0 : integer := (26);
constant CFG_GRPCI2_BAR1 : integer := (0);
constant CFG_GRPCI2_BAR2 : integer := (0);
constant CFG_GRPCI2_BAR3 : integer := (0);
constant CFG_GRPCI2_BAR4 : integer := (0);
constant CFG_GRPCI2_BAR5 : integer := (0);
constant CFG_GRPCI2_FDEPTH : integer := 3;
constant CFG_GRPCI2_FCOUNT : integer := 2;
constant CFG_GRPCI2_ENDIAN : integer := 0;
constant CFG_GRPCI2_DEVINT : integer := 0;
constant CFG_GRPCI2_DEVINTMSK : integer := 16#0#;
constant CFG_GRPCI2_HOSTINT : integer := 0;
constant CFG_GRPCI2_HOSTINTMSK: integer := 16#0#;
constant CFG_GRPCI2_TRACE : integer := 0;
constant CFG_GRPCI2_TRACEAPB : integer := 0;
constant CFG_GRPCI2_BYPASS : integer := 0;
constant CFG_GRPCI2_EXTCFG : integer := (0);
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 1;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 1;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-3.0 | bab0f6d0a6578fdbda880f9e57924dbf | 0.648935 | 3.541237 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/grlib/amba/defmst.vhd | 1 | 1,967 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
----------------------------------------------------------------------------
-- Entity: defmst
-- File: defmst.vhd
-- Author: Edvin Catovic, Gaisler Research
-- Description: Default AHB master
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
entity ahbdefmst is
generic ( hindex : integer range 0 to NAHBMST-1 := 0);
port ( ahbmo : out ahb_mst_out_type);
end;
architecture rtl of ahbdefmst is
begin
ahbmo.hbusreq <= '0';
ahbmo.hlock <= '0';
ahbmo.htrans <= HTRANS_IDLE;
ahbmo.haddr <= (others => '0');
ahbmo.hwrite <= '0';
ahbmo.hsize <= (others => '0');
ahbmo.hburst <= (others => '0');
ahbmo.hprot <= (others => '0');
ahbmo.hwdata <= (others => '0');
ahbmo.hirq <= (others => '0');
ahbmo.hconfig <= (others => (others => '0'));
ahbmo.hindex <= hindex;
end;
| gpl-3.0 | 68207140739b0d4ed47b4e7d239af462 | 0.587189 | 4.030738 | false | false | false | false |
GLADICOS/SPACEWIRESYSTEMC | rtl/RTL_SL/spwstream.vhd | 1 | 21,187 | --
-- SpaceWire core with character-stream interface.
--
-- This entity provides a SpaceWire core with a character-stream interface.
-- The interface provides means for connection initiation, sending and
-- receiving of N-Chars and TimeCodes, and error reporting.
--
-- This entity instantiates spwlink, spwrecv, spwxmit and one of the
-- spwrecvfront implementations. It also implements a receive FIFO and
-- a transmit FIFO.
--
-- The SpaceWire standard requires that each transceiver use an initial
-- signalling rate of 10 Mbit/s. This implies that the system clock frequency
-- must be a multiple of 10 MHz. See the manual for further details on
-- bitrates and clocking.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.spwpkg.all;
entity spwstream is
generic (
-- System clock frequency in Hz.
-- This must be set to the frequency of "clk". It is used to setup
-- counters for reset timing, disconnect timeout and to transmit
-- at 10 Mbit/s during the link handshake.
sysfreq: real := 200000000.0;
-- Transmit clock frequency in Hz (only if tximpl = impl_fast).
-- This must be set to the frequency of "txclk". It is used to
-- transmit at 10 Mbit/s during the link handshake.
txclkfreq: real := 0.0;
-- Selection of a receiver front-end implementation.
rximpl: spw_implementation_type := impl_generic;
-- Maximum number of bits received per system clock
-- (must be 1 in case of impl_generic).
rxchunk: integer range 1 to 4 := 1;
-- Selection of a transmitter implementation.
tximpl: spw_implementation_type := impl_generic;
-- Size of the receive FIFO as the 2-logarithm of the number of bytes.
-- Must be at least 6 (64 bytes).
rxfifosize_bits: integer range 6 to 14 := 11;
-- Size of the transmit FIFO as the 2-logarithm of the number of bytes.
txfifosize_bits: integer range 2 to 14 := 11
);
port (
-- System clock.
clk: in std_logic;
-- Receiver sample clock (only for impl_fast)
rxclk: in std_logic;
-- Transmit clock (only for impl_fast)
txclk: in std_logic;
-- Synchronous reset (active-high).
rst: in std_logic;
-- Enables automatic link start on receipt of a NULL character.
autostart: in std_logic;
-- Enables link start once the Ready state is reached.
-- Without autostart or linkstart, the link remains in state Ready.
linkstart: in std_logic;
-- Do not start link (overrides linkstart and autostart) and/or
-- disconnect a running link.
linkdis: in std_logic;
-- Scaling factor minus 1, used to scale the transmit base clock into
-- the transmission bit rate. The system clock (for impl_generic) or
-- the txclk (for impl_fast) is divided by (unsigned(txdivcnt) + 1).
-- Changing this signal will immediately change the transmission rate.
-- During link setup, the transmission rate is always 10 Mbit/s.
txdivcnt: in std_logic_vector(7 downto 0);
-- High for one clock cycle to request transmission of a TimeCode.
-- The request is registered inside the entity until it can be processed.
tick_in: in std_logic;
-- Control bits of the TimeCode to be sent. Must be valid while tick_in is high.
ctrl_in: in std_logic_vector(1 downto 0);
-- Counter value of the TimeCode to be sent. Must be valid while tick_in is high.
time_in: in std_logic_vector(5 downto 0);
-- Pulled high by the application to write an N-Char to the transmit
-- queue. If "txwrite" and "txrdy" are both high on the rising edge
-- of "clk", a character is added to the transmit queue.
-- This signal has no effect if "txrdy" is low.
txwrite: in std_logic;
-- Control flag to be sent with the next N_Char.
-- Must be valid while txwrite is high.
txflag: in std_logic;
-- Byte to be sent, or "00000000" for EOP or "00000001" for EEP.
-- Must be valid while txwrite is high.
txdata: in std_logic_vector(7 downto 0);
-- High if the entity is ready to accept an N-Char for transmission.
txrdy: out std_logic;
-- High if the transmission queue is at least half full.
txhalff: out std_logic;
-- High for one clock cycle if a TimeCode was just received.
tick_out: out std_logic;
-- Control bits of the last received TimeCode.
ctrl_out: out std_logic_vector(1 downto 0);
-- Counter value of the last received TimeCode.
time_out: out std_logic_vector(5 downto 0);
-- High if "rxflag" and "rxdata" contain valid data.
-- This signal is high unless the receive FIFO is empty.
rxvalid: out std_logic;
-- High if the receive FIFO is at least half full.
rxhalff: out std_logic;
-- High if the received character is EOP or EEP; low if the received
-- character is a data byte. Valid if "rxvalid" is high.
rxflag: out std_logic;
-- Received byte, or "00000000" for EOP or "00000001" for EEP.
-- Valid if "rxvalid" is high.
rxdata: out std_logic_vector(7 downto 0);
-- Pulled high by the application to accept a received character.
-- If "rxvalid" and "rxread" are both high on the rising edge of "clk",
-- a character is removed from the receive FIFO and "rxvalid", "rxflag"
-- and "rxdata" are updated.
-- This signal has no effect if "rxvalid" is low.
rxread: in std_logic;
-- High if the link state machine is currently in the Started state.
started: out std_logic;
-- High if the link state machine is currently in the Connecting state.
connecting: out std_logic;
-- High if the link state machine is currently in the Run state, indicating
-- that the link is fully operational. If none of started, connecting or running
-- is high, the link is in an initial state and the transmitter is not yet enabled.
running: out std_logic;
-- Disconnect detected in state Run. Triggers a reset and reconnect of the link.
-- This indication is auto-clearing.
errdisc: out std_logic;
-- Parity error detected in state Run. Triggers a reset and reconnect of the link.
-- This indication is auto-clearing.
errpar: out std_logic;
-- Invalid escape sequence detected in state Run. Triggers a reset and reconnect of
-- the link. This indication is auto-clearing.
erresc: out std_logic;
-- Credit error detected. Triggers a reset and reconnect of the link.
-- This indication is auto-clearing.
errcred: out std_logic;
-- Data In signal from SpaceWire bus.
spw_di: in std_logic;
-- Strobe In signal from SpaceWire bus.
spw_si: in std_logic;
-- Data Out signal to SpaceWire bus.
spw_do: out std_logic;
-- Strobe Out signal to SpaceWire bus.
spw_so: out std_logic
);
end entity spwstream;
architecture spwstream_arch of spwstream is
-- Convert boolean to std_logic.
type bool_to_logic_type is array(boolean) of std_ulogic;
constant bool_to_logic: bool_to_logic_type := (false => '0', true => '1');
-- Reset time (6.4 us) in system clocks
constant reset_time: integer := integer(sysfreq * 6.4e-6);
-- Disconnect time (850 ns) in system clocks
constant disconnect_time: integer := integer(sysfreq * 850.0e-9);
-- Initial tx clock scaler (10 Mbit).
type impl_to_real_type is array(spw_implementation_type) of real;
constant tximpl_to_txclk_freq: impl_to_real_type :=
(impl_generic => sysfreq, impl_fast => txclkfreq);
constant effective_txclk_freq: real := tximpl_to_txclk_freq(tximpl);
constant default_divcnt: std_logic_vector(7 downto 0) :=
std_logic_vector(to_unsigned(integer(effective_txclk_freq / 10.0e6 - 1.0), 8));
-- Registers.
type regs_type is record
-- packet state
rxpacket: std_logic; -- '1' when receiving a packet
rxeep: std_logic; -- '1' when rx EEP character pending
txpacket: std_logic; -- '1' when transmitting a packet
txdiscard: std_logic; -- '1' when discarding a tx packet
-- FIFO pointers
rxfifo_raddr: std_logic_vector(rxfifosize_bits-1 downto 0);
rxfifo_waddr: std_logic_vector(rxfifosize_bits-1 downto 0);
txfifo_raddr: std_logic_vector(txfifosize_bits-1 downto 0);
txfifo_waddr: std_logic_vector(txfifosize_bits-1 downto 0);
-- FIFO state
rxfifo_rvalid: std_logic; -- '1' if s_rxfifo_rdata is valid
txfifo_rvalid: std_logic; -- '1' if s_txfifo_rdata is valid
rxfull: std_logic; -- '1' if RX fifo is full
rxhalff: std_logic; -- '1' if RX fifo is at least half full
txfull: std_logic; -- '1' if TX fifo is full
txhalff: std_logic; -- '1' if TX fifo is at least half full
rxroom: std_logic_vector(5 downto 0);
end record;
constant regs_reset: regs_type := (
rxpacket => '0',
rxeep => '0',
txpacket => '0',
txdiscard => '0',
rxfifo_raddr => (others => '0'),
rxfifo_waddr => (others => '0'),
txfifo_raddr => (others => '0'),
txfifo_waddr => (others => '0'),
rxfifo_rvalid => '0',
txfifo_rvalid => '0',
rxfull => '0',
rxhalff => '0',
txfull => '0',
txhalff => '0',
rxroom => (others => '0') );
signal r: regs_type := regs_reset;
signal rin: regs_type;
-- Interface signals to components.
signal recv_rxen: std_logic;
signal recvo: spw_recv_out_type;
signal recv_inact: std_logic;
signal recv_inbvalid: std_logic;
signal recv_inbits: std_logic_vector(rxchunk-1 downto 0);
signal xmiti: spw_xmit_in_type;
signal xmito: spw_xmit_out_type;
signal xmit_divcnt: std_logic_vector(7 downto 0);
signal linki: spw_link_in_type;
signal linko: spw_link_out_type;
-- Memory interface signals.
signal s_rxfifo_raddr: std_logic_vector(rxfifosize_bits-1 downto 0);
signal s_rxfifo_rdata: std_logic_vector(8 downto 0);
signal s_rxfifo_wen: std_logic;
signal s_rxfifo_waddr: std_logic_vector(rxfifosize_bits-1 downto 0);
signal s_rxfifo_wdata: std_logic_vector(8 downto 0);
signal s_txfifo_raddr: std_logic_vector(txfifosize_bits-1 downto 0);
signal s_txfifo_rdata: std_logic_vector(8 downto 0);
signal s_txfifo_wen: std_logic;
signal s_txfifo_waddr: std_logic_vector(txfifosize_bits-1 downto 0);
signal s_txfifo_wdata: std_logic_vector(8 downto 0);
begin
-- Instantiate link controller.
link_inst: spwlink
generic map (
reset_time => reset_time )
port map (
clk => clk,
rst => rst,
linki => linki,
linko => linko,
rxen => recv_rxen,
recvo => recvo,
xmiti => xmiti,
xmito => xmito );
-- Instantiate receiver.
recv_inst: spwrecv
generic map(
disconnect_time => disconnect_time,
rxchunk => rxchunk )
port map (
clk => clk,
rxen => recv_rxen,
recvo => recvo,
inact => recv_inact,
inbvalid => recv_inbvalid,
inbits => recv_inbits );
-- Instantiate transmitter.
xmit_sel0: if tximpl = impl_generic generate
xmit_inst: spwxmit
port map (
clk => clk,
rst => rst,
divcnt => xmit_divcnt,
xmiti => xmiti,
xmito => xmito,
spw_do => spw_do,
spw_so => spw_so );
end generate;
xmit_sel1: if tximpl = impl_fast generate
xmit_fast_inst: spwxmit_fast
port map (
clk => clk,
txclk => txclk,
rst => rst,
divcnt => xmit_divcnt,
xmiti => xmiti,
xmito => xmito,
spw_do => spw_do,
spw_so => spw_so );
end generate;
-- Instantiate receiver front-end.
recvfront_sel0: if rximpl = impl_generic generate
recvfront_generic_inst: spwrecvfront_generic
port map (
clk => clk,
rxen => recv_rxen,
inact => recv_inact,
inbvalid => recv_inbvalid,
inbits => recv_inbits,
spw_di => spw_di,
spw_si => spw_si );
end generate;
recvfront_sel1: if rximpl = impl_fast generate
recvfront_fast_inst: spwrecvfront_fast
generic map (
rxchunk => rxchunk )
port map (
clk => clk,
rxclk => rxclk,
rxen => recv_rxen,
inact => recv_inact,
inbvalid => recv_inbvalid,
inbits => recv_inbits,
spw_di => spw_di,
spw_si => spw_si );
end generate;
-- Instantiate RX memory.
rxmem: spwram
generic map (
abits => rxfifosize_bits,
dbits => 9 )
port map (
rclk => clk,
wclk => clk,
ren => '1',
raddr => s_rxfifo_raddr,
rdata => s_rxfifo_rdata,
wen => s_rxfifo_wen,
waddr => s_rxfifo_waddr,
wdata => s_rxfifo_wdata );
-- Instantiate TX memory.
txmem: spwram
generic map (
abits => txfifosize_bits,
dbits => 9 )
port map (
rclk => clk,
wclk => clk,
ren => '1',
raddr => s_txfifo_raddr,
rdata => s_txfifo_rdata,
wen => s_txfifo_wen,
waddr => s_txfifo_waddr,
wdata => s_txfifo_wdata );
-- Combinatorial process
process (r, linko, s_rxfifo_rdata, s_txfifo_rdata, rst, autostart, linkstart, linkdis, txdivcnt, tick_in, ctrl_in, time_in, txwrite, txflag, txdata, rxread) is
variable v: regs_type;
variable v_tmprxroom: unsigned(rxfifosize_bits-1 downto 0);
variable v_tmptxroom: unsigned(txfifosize_bits-1 downto 0);
begin
v := r;
v_tmprxroom := to_unsigned(0, v_tmprxroom'length);
v_tmptxroom := to_unsigned(0, v_tmptxroom'length);
-- Keep track of whether we are sending and/or receiving a packet.
if linko.rxchar = '1' then
-- got character
v.rxpacket := not linko.rxflag;
end if;
if linko.txack = '1' then
-- send character
v.txpacket := not s_txfifo_rdata(8);
end if;
-- Update RX fifo pointers.
if (rxread = '1') and (r.rxfifo_rvalid = '1') then
-- read from fifo
v.rxfifo_raddr := std_logic_vector(unsigned(r.rxfifo_raddr) + 1);
end if;
if r.rxfull = '0' then
if (linko.rxchar = '1') or (r.rxeep = '1') then
-- write to fifo (received char or pending EEP)
v.rxfifo_waddr := std_logic_vector(unsigned(r.rxfifo_waddr) + 1);
end if;
v.rxeep := '0';
end if;
-- Keep track of whether the RX fifo contains valid data.
-- (use new value of rxfifo_raddr)
v.rxfifo_rvalid := bool_to_logic(v.rxfifo_raddr /= r.rxfifo_waddr);
-- Update room in RX fifo (use new value of rxfifo_waddr).
v_tmprxroom := unsigned(r.rxfifo_raddr) - unsigned(v.rxfifo_waddr) - 1;
v.rxfull := bool_to_logic(v_tmprxroom = 0);
v.rxhalff := not v_tmprxroom(v_tmprxroom'high);
if v_tmprxroom > 63 then
v.rxroom := (others => '1');
else
v.rxroom := std_logic_vector(v_tmprxroom(5 downto 0));
end if;
-- Update TX fifo pointers.
if (r.txfifo_rvalid = '1') and ((linko.txack = '1') or (r.txdiscard = '1')) then
-- read from fifo
v.txfifo_raddr := std_logic_vector(unsigned(r.txfifo_raddr) + 1);
if s_txfifo_rdata(8) = '1' then
v.txdiscard := '0'; -- got EOP/EEP, stop discarding data
end if;
end if;
if (r.txfull = '0') and (txwrite = '1') then
-- write to fifo
v.txfifo_waddr := std_logic_vector(unsigned(r.txfifo_waddr) + 1);
end if;
-- Keep track of whether the TX fifo contains valid data.
-- (use new value of txfifo_raddr)
v.txfifo_rvalid := bool_to_logic(v.txfifo_raddr /= r.txfifo_waddr);
-- Update room in TX fifo (use new value of txfifo_waddr).
v_tmptxroom := unsigned(r.txfifo_raddr) - unsigned(v.txfifo_waddr) - 1;
v.txfull := bool_to_logic(v_tmptxroom = 0);
v.txhalff := not v_tmptxroom(v_tmptxroom'high);
-- If the link is lost, set a flag to discard the current packet.
if linko.running = '0' then
v.rxeep := v.rxeep or v.rxpacket; -- use new value of rxpacket
v.txdiscard := v.txdiscard or v.txpacket; -- use new value of txpacket
v.rxpacket := '0';
v.txpacket := '0';
end if;
-- Clear the discard flag when the link is explicitly disabled.
if linkdis = '1' then
v.txdiscard := '0';
end if;
-- Drive control signals to RX fifo.
s_rxfifo_raddr <= v.rxfifo_raddr; -- using new value of rxfifo_raddr
s_rxfifo_wen <= (not r.rxfull) and (linko.rxchar or r.rxeep);
s_rxfifo_waddr <= r.rxfifo_waddr;
if r.rxeep = '1' then
s_rxfifo_wdata <= "100000001";
else
s_rxfifo_wdata <= linko.rxflag & linko.rxdata;
end if;
-- Drive control signals to TX fifo.
s_txfifo_raddr <= v.txfifo_raddr; -- using new value of txfifo_raddr
s_txfifo_wen <= (not r.txfull) and txwrite;
s_txfifo_waddr <= r.txfifo_waddr;
s_txfifo_wdata <= txflag & txdata;
-- Drive inputs to spwlink.
linki.autostart <= autostart;
linki.linkstart <= linkstart;
linki.linkdis <= linkdis;
linki.rxroom <= r.rxroom;
linki.tick_in <= tick_in;
linki.ctrl_in <= ctrl_in;
linki.time_in <= time_in;
linki.txwrite <= r.txfifo_rvalid and not r.txdiscard;
linki.txflag <= s_txfifo_rdata(8);
linki.txdata <= s_txfifo_rdata(7 downto 0);
-- Drive divcnt input to spwxmit.
if linko.running = '1' then
xmit_divcnt <= txdivcnt;
else
xmit_divcnt <= default_divcnt;
end if;
-- Drive outputs.
txrdy <= not r.txfull;
txhalff <= r.txhalff;
tick_out <= linko.tick_out;
ctrl_out <= linko.ctrl_out;
time_out <= linko.time_out;
rxvalid <= r.rxfifo_rvalid;
rxhalff <= r.rxhalff;
rxflag <= s_rxfifo_rdata(8);
rxdata <= s_rxfifo_rdata(7 downto 0);
started <= linko.started;
connecting <= linko.connecting;
running <= linko.running;
errdisc <= linko.errdisc;
errpar <= linko.errpar;
erresc <= linko.erresc;
errcred <= linko.errcred;
-- Reset.
if rst = '1' then
v.rxpacket := '0';
v.rxeep := '0';
v.txpacket := '0';
v.txdiscard := '0';
v.rxfifo_raddr := (others => '0');
v.rxfifo_waddr := (others => '0');
v.txfifo_raddr := (others => '0');
v.txfifo_waddr := (others => '0');
v.rxfifo_rvalid := '0';
v.txfifo_rvalid := '0';
end if;
-- Update registers.
rin <= v;
end process;
-- Update registers.
process (clk) is
begin
if rising_edge(clk) then
r <= rin;
end if;
end process;
end architecture spwstream_arch;
| gpl-3.0 | 34087409e07beba3ad6724553029c8b7 | 0.546939 | 3.852182 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/arith/div32.vhd | 1 | 7,149 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: div32
-- File: div32.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: This unit implemets a divide unit to execute 64-bit by 32-bit
-- division. The divider leaves no remainder.
-- Overflow detection is performed according to the
-- SPARC V8 manual, method B (page 116)
-- Division is made using the non-restoring algorithm,
-- and takes 36 clocks. The operands must be stable during
-- the calculations. The result is available one clock after
-- the ready signal is asserted.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.arith.all;
entity div32 is
generic (scantest : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
holdn : in std_ulogic;
divi : in div32_in_type;
divo : out div32_out_type;
testen : in std_ulogic := '0';
testrst : in std_ulogic := '1'
);
end;
architecture rtl of div32 is
type div_regtype is record
x : std_logic_vector(64 downto 0);
state : std_logic_vector(2 downto 0);
zero : std_logic;
zero2 : std_logic;
qcorr : std_logic;
zcorr : std_logic;
qzero : std_logic;
qmsb : std_logic;
ovf : std_logic;
neg : std_logic;
cnt : std_logic_vector(4 downto 0);
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant ASYNC_RESET : boolean := GRLIB_CONFIG_ARRAY(grlib_async_reset_enable) = 1;
constant RRES : div_regtype := (
x => (others => '0'),
state => (others => '0'),
zero => '0',
zero2 => '0',
qcorr => '0',
zcorr => '0',
qzero => '0',
qmsb => '0',
ovf => '0',
neg => '0',
cnt => (others => '0'));
signal arst : std_ulogic;
signal r, rin : div_regtype;
signal addin1, addin2, addout: std_logic_vector(32 downto 0);
signal addsub : std_logic;
begin
arst <= testrst when (ASYNC_RESET and scantest/=0 and testen/='0') else
rst when ASYNC_RESET else
'1';
divcomb : process (r, rst, divi, addout)
variable v : div_regtype;
variable vready, vnready : std_logic;
variable vaddin1, vaddin2 : std_logic_vector(32 downto 0);
variable vaddsub, ymsb : std_logic;
constant zero33: std_logic_vector(32 downto 0) := "000000000000000000000000000000000";
begin
vready := '0'; vnready := '0'; v := r;
if addout = zero33 then v.zero := '1'; else v.zero := '0'; end if;
vaddin1 := r.x(63 downto 31); vaddin2 := divi.op2;
vaddsub := not (divi.op2(32) xor r.x(64));
v.zero2 := r.zero;
case r.state is
when "000" =>
v.cnt := "00000";
if (divi.start = '1') then
v.x(64) := divi.y(32); v.state := "001";
end if;
when "001" =>
v.x := divi.y & divi.op1(31 downto 0);
v.neg := divi.op2(32) xor divi.y(32);
if divi.signed = '1' then
vaddin1 := divi.y(31 downto 0) & divi.op1(31);
v.ovf := not (addout(32) xor divi.y(32));
else
vaddin1 := divi.y; vaddsub := '1';
v.ovf := not addout(32);
end if;
v.state := "010";
when "010" =>
if ((divi.signed and r.neg and r.zero) = '1') and (divi.op1 = zero33) then v.ovf := '0'; end if;
v.qmsb := vaddsub; v.qzero := '1';
v.x(64 downto 32) := addout;
v.x(31 downto 0) := r.x(30 downto 0) & vaddsub;
v.state := "011"; v.zcorr := v.zero;
v.cnt := r.cnt + 1;
when "011" =>
v.qzero := r.qzero and (vaddsub xor r.qmsb);
v.zcorr := r.zcorr or v.zero;
v.x(64 downto 32) := addout;
v.x(31 downto 0) := r.x(30 downto 0) & vaddsub;
if (r.cnt = "11111") then v.state := "100"; vnready := '1';
else v.cnt := r.cnt + 1; end if;
v.qcorr := v.x(64) xor divi.y(32);
when "100" =>
vaddin1 := r.x(64 downto 32);
v.state := "101";
when others =>
vaddin1 := ((not r.x(31)) & r.x(30 downto 0) & '1');
vaddin2 := (others => '0'); vaddin2(0) := '1';
vaddsub := (not r.neg);-- or (r.zcorr and not r.qcorr);
if ((r.qcorr = '1') or (r.zero = '1')) and (r.zero2 = '0') then
if (r.zero = '1') and ((r.qcorr = '0') and (r.zcorr = '1')) then
vaddsub := r.neg; v.qzero := '0';
end if;
v.x(64 downto 32) := addout;
else
v.x(64 downto 32) := vaddin1; v.qzero := '0';
end if;
if (r.ovf = '1') then
v.qzero := '0';
v.x(63 downto 32) := (others => '1');
if divi.signed = '1' then
if r.neg = '1' then v.x(62 downto 32) := (others => '0');
else v.x(63) := '0'; end if;
end if;
end if;
vready := '1';
v.state := "000";
end case;
divo.icc <= r.x(63) & r.qzero & r.ovf & '0';
if (divi.flush = '1') then v.state := "000"; end if;
if (not ASYNC_RESET) and (not RESET_ALL) and (rst = '0') then
v.state := RRES.state; v.cnt := RRES.cnt;
end if;
rin <= v;
divo.ready <= vready; divo.nready <= vnready;
divo.result(31 downto 0) <= r.x(63 downto 32);
addin1 <= vaddin1; addin2 <= vaddin2; addsub <= vaddsub;
end process;
divadd : process(addin1, addin2, addsub)
variable b : std_logic_vector(32 downto 0);
begin
if addsub = '1' then b := not addin2; else b := addin2; end if;
addout <= addin1 + b + addsub;
end process;
syncrregs : if not ASYNC_RESET generate
reg : process(clk)
begin
if rising_edge(clk) then
if (holdn = '1') then r <= rin; end if;
if (rst = '0') then
if RESET_ALL then
r <= RRES;
else
r.state <= RRES.state; r.cnt <= RRES.cnt;
end if;
end if;
end if;
end process;
end generate syncrregs;
asyncrregs : if ASYNC_RESET generate
reg : process(clk, arst)
begin
if (arst = '0') then
r <= RRES;
elsif rising_edge(clk) then
if (holdn = '1') then r <= rin; end if;
end if;
end process;
end generate asyncrregs;
end;
| gpl-3.0 | 2da46576a159fd1517fc6cd6f156c5bc | 0.562876 | 3.207268 | false | false | false | false |
pwsoft/fpga_examples | rtl/chameleon/chameleon_old_sdram.vhd | 1 | 22,691 | -- -----------------------------------------------------------------------
--
-- Turbo Chameleon
--
-- Multi purpose FPGA expansion for the Commodore 64 computer
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2014 by Peter Wendrich ([email protected])
-- http://www.syntiac.com
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
--
-- SDRAM controller
--
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
-- -----------------------------------------------------------------------
entity chameleon_sdram is
generic (
-- SDRAM cols/rows 8/12 = 8 Mbyte, 9/12 = 16 Mbyte, 9/13 = 32 Mbyte
colAddrBits : integer := 9;
rowAddrBits : integer := 12;
-- Port settings
enable_cpu6510_port : boolean := false;
enable_cache1_port : boolean := false;
enable_cache2_port : boolean := false;
enable_vid0_port : boolean := false;
enable_vid1_port : boolean := false;
-- Controller settings
initTimeout : integer := 10000;
readAutoPrecharge : boolean := true;
-- SDRAM timing
casLatency : integer := 3;
ras_cycles : integer := 2;
precharge_cycles : integer := 2;
t_refresh_ms : real := 64.0;
t_refresh_ns : real := 60.0;
t_clk_ns : real := 10.0 -- Clock cycle time
);
port (
-- System
clk : in std_logic;
reserve : in std_logic := '0';
delay_refresh : in std_logic := '0';
-- SDRAM interface
sd_data : inout unsigned(15 downto 0);
sd_addr : out unsigned((rowAddrBits-1) downto 0);
sd_we_n : out std_logic;
sd_ras_n : out std_logic;
sd_cas_n : out std_logic;
sd_ba_0 : out std_logic;
sd_ba_1 : out std_logic;
sd_ldqm : out std_logic;
sd_udqm : out std_logic;
-- first cache port
cache_req : in std_logic := '0';
cache_ack : out std_logic;
cache_we : in std_logic := '0';
cache_burst : in std_logic := '0';
cache_a : in unsigned((colAddrBits+rowAddrBits+2) downto 0) := (others => '0');
cache_d : in unsigned(63 downto 0) := (others => '0');
cache_q : out unsigned(63 downto 0);
-- second cache port
cache2_req : in std_logic := '0';
cache2_ack : out std_logic;
cache2_we : in std_logic := '0';
cache2_burst : in std_logic := '0';
cache2_a : in unsigned((colAddrBits+rowAddrBits+2) downto 0) := (others => '0');
cache2_d : in unsigned(63 downto 0) := (others => '0');
cache2_q : out unsigned(63 downto 0);
-- VGA Video read ports
vid0_req : in std_logic := '0'; -- Toggle for request
vid0_ack : out std_logic; -- Ack follows req when done
vid0_addr : unsigned((colAddrBits+rowAddrBits+2) downto 3) := (others => '0');
vid0_do : out unsigned(63 downto 0);
vid1_req : in std_logic := '0'; -- Toggle for request
vid1_ack : out std_logic; -- Ack follows req when done
vid1_addr : unsigned((colAddrBits+rowAddrBits+2) downto 3) := (others => '0');
vid1_do : out unsigned(63 downto 0);
-- 6510 port (8 bit port)
cpu6510_req : in std_logic := '0'; -- toggle to start memory request
cpu6510_ack : out std_logic; -- will follow 'request' after transfer
cpu6510_we : in std_logic := '0'; -- 1 write action, 0 read action
cpu6510_a : in unsigned((colAddrBits+rowAddrBits+2) downto 0) := (others => '0');
cpu6510_d : in unsigned(7 downto 0) := (others => '0');
cpu6510_q : out unsigned(7 downto 0);
-- Debug ports
debugIdle : out std_logic; -- '1' memory is idle
debugRefresh : out std_logic -- '1' memory is being refreshed
);
end entity;
-- -----------------------------------------------------------------------
architecture rtl of chameleon_sdram is
constant refresh_clocks : integer := integer((t_refresh_ns / t_clk_ns) + 0.5);
constant refresh_interval : integer := integer((t_refresh_ms*1000000.0) / (t_clk_ns * 2.0**rowAddrBits));
constant refresh_timer_range : integer := refresh_interval*3;
-- ram state machine
type ramStates is (
RAM_INIT,
RAM_INIT_PRECHARGE,
RAM_SETMODE,
RAM_IDLE,
RAM_ACTIVE,
RAM_READ_1,
RAM_READ_2,
RAM_READ_3,
RAM_READ_4,
RAM_READ_5,
RAM_WRITE_1,
RAM_WRITE_2,
RAM_WRITE_3,
RAM_WRITE_4,
RAM_WRITE_ABORT,
RAM_WRITE_DLY,
RAM_PRECHARGE,
RAM_PRECHARGE_ALL,
RAM_AUTOREFRESH
);
type ramPorts is (
PORT_NONE,
PORT_CACHE_1,
PORT_CACHE_2,
PORT_VID0,
PORT_VID1,
PORT_CPU6510
);
type timer_t is record
cnt : integer range 0 to 32767;
run : std_logic;
end record;
subtype row_t is unsigned((rowAddrBits-1) downto 0);
subtype col_t is unsigned((colAddrBits-1) downto 0);
signal ramState : ramStates := RAM_INIT;
signal timer : timer_t := (cnt => 0, run => '0');
signal ram_data_reg : unsigned(sd_data'range);
-- Registered sdram signals
signal sd_data_reg : unsigned(15 downto 0);
signal sd_data_ena : std_logic := '0';
signal sd_addr_reg : unsigned((rowAddrBits-1) downto 0);
signal sd_we_n_reg : std_logic;
signal sd_ras_n_reg : std_logic;
signal sd_cas_n_reg : std_logic;
signal sd_ba_0_reg : std_logic;
signal sd_ba_1_reg : std_logic;
signal sd_ldqm_reg : std_logic;
signal sd_udqm_reg : std_logic;
-- ram acknowledge signals
signal cache1_ack_reg : std_logic := '0';
signal cache2_ack_reg : std_logic := '0';
signal vid0_ack_reg : std_logic := '0';
signal vid1_ack_reg : std_logic := '0';
signal cpu6510_ack_reg : std_logic := '0';
-- Active rows in SDRAM
type bankRowDef is array(0 to 3) of row_t;
signal bankActive : std_logic_vector(0 to 3) := (others => '0');
signal bankRow : bankRowDef;
-- Memory auto refresh
signal refreshTimer : integer range 0 to refresh_timer_range := 0;
signal refresh_active_reg : std_logic := '0';
signal refresh_subtract_reg : std_logic := '0';
signal refresh_required_reg : std_logic := '0';
signal currentPort : ramPorts;
signal currentBank : unsigned(1 downto 0);
signal currentRow : row_t;
signal currentCol : col_t;
signal currentWrData : unsigned(63 downto 0);
signal currentLdqm : std_logic;
signal currentUdqm : std_logic;
signal currentWe : std_logic;
signal nextRamBank : unsigned(1 downto 0);
signal nextRamRow : row_t;
signal nextRamCol : col_t;
signal nextRamPort : ramPorts;
signal nextWrData : unsigned(63 downto 0);
signal nextLdqm : std_logic;
signal nextUdqm : std_logic;
signal nextWe : std_logic;
procedure set_timer(signal timer : inout timer_t; constant timeout : in integer) is
begin
if timeout > 0 then
timer.run <= '1';
timer.cnt <= timeout-1;
else
timer.run <= '0';
end if;
end procedure;
begin
ram_data_reg <= sd_data;
sd_data <= sd_data_reg when sd_data_ena = '1' else (others => 'Z');
sd_addr <= sd_addr_reg;
sd_ras_n <= sd_ras_n_reg;
sd_cas_n <= sd_cas_n_reg;
sd_we_n <= sd_we_n_reg;
sd_ba_0 <= sd_ba_0_reg;
sd_ba_1 <= sd_ba_1_reg;
sd_ldqm <= sd_ldqm_reg;
sd_udqm <= sd_udqm_reg;
cache_ack <= cache1_ack_reg;
cache2_ack <= cache2_ack_reg;
vid0_ack <= vid0_ack_reg;
vid1_ack <= vid1_ack_reg;
cpu6510_ack <= cpu6510_ack_reg;
-- -----------------------------------------------------------------------
-- Refresh timer
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if refreshTimer < refresh_timer_range-1 then
refreshTimer <= refreshTimer + 1;
end if;
if refresh_subtract_reg = '1' then
refreshTimer <= refreshTimer - refresh_interval;
end if;
refresh_required_reg <= '0';
if refreshTimer >= refresh_interval then
-- Suppress refreshes when "reserve" pin is high.
refresh_required_reg <= not reserve;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- State machine
-- -----------------------------------------------------------------------
process(currentPort, cpu6510_req, cpu6510_ack_reg, cache_req, cache1_ack_reg,
reserve, cache_a, cache_d, cache_burst, cache_we, vid0_req,
vid0_ack_reg, vid0_addr)
begin
nextRamPort <= PORT_NONE;
nextRamBank <= "00";
nextRamRow <= ( others => '0');
nextRamCol <= ( others => '0');
nextLdqm <= '0';
nextUdqm <= '0';
nextWe <= '0';
nextWrData <= (others => '-');
if enable_cpu6510_port and (cpu6510_req /= cpu6510_ack_reg) and (currentPort /= PORT_CPU6510) then
if cpu6510_we = '1' then
nextWe <= '1';
nextLdqm <= cpu6510_a(0);
nextUdqm <= not cpu6510_a(0);
end if;
nextRamPort <= PORT_CPU6510;
nextRamBank <= cpu6510_a((colAddrBits+rowAddrBits+2) downto (colAddrBits+rowAddrBits+1));
nextRamRow <= cpu6510_a((colAddrBits+rowAddrBits) downto (colAddrBits+1));
nextRamCol <= cpu6510_a(colAddrBits downto 1);
nextWrData(15 downto 0) <= cpu6510_d & cpu6510_d;
elsif enable_cache1_port and (cache_req /= cache1_ack_reg) and (currentPort /= PORT_CACHE_1) then
nextRamPort <= PORT_CACHE_1;
nextRamBank <= cache_a((colAddrBits+rowAddrBits+2) downto (colAddrBits+rowAddrBits+1));
nextRamRow <= cache_a((colAddrBits+rowAddrBits) downto (colAddrBits+1));
nextRamCol <= cache_a(colAddrBits downto 1);
nextWrData <= cache_d;
if cache_burst = '1' then
nextRamCol(1 downto 0) <= "00";
end if;
if cache_we = '1' then
nextWe <= '1';
if cache_burst = '0' then
nextLdqm <= cache_a(0);
nextUdqm <= not cache_a(0);
end if;
end if;
elsif enable_cache2_port and (cache2_req /= cache2_ack_reg) and (currentPort /= PORT_CACHE_2) then
nextRamPort <= PORT_CACHE_2;
nextRamBank <= cache2_a((colAddrBits+rowAddrBits+2) downto (colAddrBits+rowAddrBits+1));
nextRamRow <= cache2_a((colAddrBits+rowAddrBits) downto (colAddrBits+1));
nextRamCol <= cache2_a(colAddrBits downto 1);
nextWrData <= cache2_d;
if cache2_burst = '1' then
nextRamCol(1 downto 0) <= "00";
end if;
if cache2_we = '1' then
nextWe <= '1';
if cache2_burst = '0' then
nextLdqm <= cache2_a(0);
nextUdqm <= not cache2_a(0);
end if;
end if;
elsif reserve = '0' then
if enable_vid0_port and (vid0_req /= vid0_ack_reg) and (currentPort /= PORT_VID0) then
nextRamPort <= PORT_VID0;
nextRamBank <= vid0_addr((colAddrBits+rowAddrBits+2) downto (colAddrBits+rowAddrBits+1));
nextRamRow <= vid0_addr((colAddrBits+rowAddrBits) downto (colAddrBits+1));
nextRamCol <= vid0_addr(colAddrBits downto 3) & "00";
elsif enable_vid1_port and (vid1_req /= vid1_ack_reg) and (currentPort /= PORT_VID1) then
nextRamPort <= PORT_VID1;
nextRamBank <= vid1_addr((colAddrBits+rowAddrBits+2) downto (colAddrBits+rowAddrBits+1));
nextRamRow <= vid1_addr((colAddrBits+rowAddrBits) downto (colAddrBits+1));
nextRamCol <= vid1_addr(colAddrBits downto 3) & "00";
end if;
end if;
end process;
process(clk)
variable done_cache1 : std_logic;
variable done_cache2 : std_logic;
variable done_vid0 : std_logic;
variable done_vid1 : std_logic;
variable done_cpu6510 : std_logic;
begin
done_cache1 := '0';
done_cache2 := '0';
done_vid0 := '0';
done_vid1 := '0';
done_cpu6510 := '0';
if rising_edge(clk) then
refresh_subtract_reg <= '0';
sd_data_ena <= '0';
sd_addr_reg <= (others => '0');
sd_ras_n_reg <= '1';
sd_cas_n_reg <= '1';
sd_we_n_reg <= '1';
sd_ldqm_reg <= '0';
sd_udqm_reg <= '0';
sd_ba_0_reg <= currentBank(0);
sd_ba_1_reg <= currentBank(1);
if timer.run = '1' then
if timer.cnt = 0 then
timer.run <= '0';
else
timer.cnt <= timer.cnt - 1;
end if;
else
case ramState is
when RAM_INIT =>
-- Wait for clock to stabilise and PLL locks
-- Then follow init steps in datasheet:
-- precharge all banks
-- perform a few autorefresh cycles (we do 2 of them)
-- setmode (burst and CAS latency)
-- after a few clocks ram is ready for use (we wait 10 just to be sure).
currentWrData <= (others => '-');
currentBank <= (others => '-');
currentRow <= (others => '-');
currentCol <= (others => '-');
currentLdqm <= '-';
currentUdqm <= '-';
currentWe <= '-';
set_timer(timer, 20000);
ramState <= RAM_INIT_PRECHARGE;
when RAM_INIT_PRECHARGE =>
-- Precharge all banks, part of initialisation sequence.
currentWrData <= (others => '-');
currentBank <= (others => '-');
currentRow <= (others => '-');
currentCol <= (others => '-');
currentLdqm <= '-';
currentUdqm <= '-';
currentWe <= '-';
set_timer(timer, 100);
ramState <= RAM_SETMODE;
sd_ras_n_reg <= '0';
sd_we_n_reg <= '0';
sd_addr_reg(10) <= '1'; -- precharge all banks
when RAM_SETMODE =>
-- Set mode bits of RAM, part of initialisation sequence.
currentWrData <= (others => '-');
currentBank <= (others => '-');
currentRow <= (others => '-');
currentCol <= (others => '-');
currentLdqm <= '-';
currentUdqm <= '-';
currentWe <= '-';
set_timer(timer, 10);
ramState <= RAM_IDLE; -- ram is ready for commands after set-mode
sd_addr_reg <= resize("000000100010", sd_addr'length); -- CAS2, Burstlength 4 (8 bytes, 64 bits)
if casLatency = 3 then
sd_addr_reg(6 downto 4) <= "011";
end if;
sd_we_n_reg <= '0';
sd_ras_n_reg <= '0';
sd_cas_n_reg <= '0';
when RAM_IDLE =>
currentPort <= nextRamPort;
currentBank <= nextRamBank;
currentRow <= nextRamRow;
currentCol <= nextRamCol;
currentLdqm <= nextLdqm;
currentUdqm <= nextUdqm;
currentWe <= nextWe;
currentWrData <= nextWrData;
refresh_active_reg <= '0';
if nextRamPort /= PORT_NONE then
ramState <= RAM_READ_1;
if nextWe = '1' then
ramState <= RAM_WRITE_1;
end if;
if bankActive(to_integer(nextRamBank)) = '0' then
-- Current bank not active. Activate a row first
ramState <= RAM_ACTIVE;
elsif bankRow(to_integer(nextRamBank)) /= nextRamRow then
-- Wrong row active in bank, do precharge then activate a row.
ramState <= RAM_PRECHARGE;
end if;
elsif (delay_refresh = '0') and (refresh_required_reg = '1') then
-- Refresh timeout, perform auto-refresh cycle
refresh_active_reg <= '1';
refresh_subtract_reg <= '1';
if bankActive /= "0000" then
-- There are still rows active, so we precharge them first
ramState <= RAM_PRECHARGE_ALL;
else
ramState <= RAM_AUTOREFRESH;
end if;
end if;
when RAM_ACTIVE =>
set_timer(timer, ras_cycles);
ramState <= RAM_READ_1;
if currentWe = '1' then
ramState <= RAM_WRITE_1;
end if;
sd_addr_reg <= currentRow;
sd_ras_n_reg <= '0';
bankRow(to_integer(currentBank)) <= currentRow;
bankActive(to_integer(currentBank)) <= '1';
when RAM_READ_1 =>
currentWrData <= (others => '-');
currentBank <= (others => '-');
currentRow <= (others => '-');
currentCol <= (others => '-');
set_timer(timer, casLatency);
ramState <= RAM_READ_2;
sd_addr_reg <= resize(currentCol, sd_addr'length);
sd_cas_n_reg <= '0';
if readAutoPrecharge then
sd_addr_reg(10) <= '1';
bankActive(to_integer(currentBank)) <= '0';
end if;
when RAM_READ_2 =>
currentWrData <= (others => '-');
currentBank <= (others => '-');
currentRow <= (others => '-');
currentCol <= (others => '-');
ramState <= RAM_READ_3;
case currentPort is
when PORT_CACHE_1 =>
cache_q(15 downto 0) <= ram_data_reg;
when PORT_CACHE_2 =>
cache2_q(15 downto 0) <= ram_data_reg;
when PORT_VID0 =>
vid0_do(15 downto 0) <= ram_data_reg;
when PORT_VID1 =>
vid1_do(15 downto 0) <= ram_data_reg;
when PORT_CPU6510 =>
if enable_cpu6510_port then
cpu6510_q <= ram_data_reg(7 downto 0);
if cpu6510_a(0) = '1' then
cpu6510_q <= ram_data_reg(15 downto 8);
end if;
done_cpu6510 := '1';
end if;
when others =>
null;
end case;
when RAM_READ_3 =>
currentWrData <= (others => '-');
currentBank <= (others => '-');
currentRow <= (others => '-');
currentCol <= (others => '-');
ramState <= RAM_READ_4;
case currentPort is
when PORT_CACHE_1 =>
cache_q(31 downto 16) <= ram_data_reg;
when PORT_CACHE_2 =>
cache2_q(31 downto 16) <= ram_data_reg;
when PORT_VID0 =>
vid0_do(31 downto 16) <= ram_data_reg;
when PORT_VID1 =>
vid1_do(31 downto 16) <= ram_data_reg;
when others =>
null;
end case;
when RAM_READ_4 =>
currentWrData <= (others => '-');
currentBank <= (others => '-');
currentRow <= (others => '-');
currentCol <= (others => '-');
ramState <= RAM_READ_5;
case currentPort is
when PORT_CACHE_1 =>
cache_q(47 downto 32) <= ram_data_reg;
when PORT_CACHE_2 =>
cache2_q(47 downto 32) <= ram_data_reg;
when PORT_VID0 =>
vid0_do(47 downto 32) <= ram_data_reg;
when PORT_VID1 =>
vid1_do(47 downto 32) <= ram_data_reg;
when others =>
null;
end case;
when RAM_READ_5 =>
currentWrData <= (others => '-');
currentBank <= (others => '-');
currentRow <= (others => '-');
currentCol <= (others => '-');
ramState <= RAM_IDLE;
case currentPort is
when PORT_CACHE_1 =>
cache_q(63 downto 48) <= ram_data_reg;
done_cache1 := '1';
when PORT_CACHE_2 =>
cache2_q(63 downto 48) <= ram_data_reg;
done_cache2 := '1';
when PORT_VID0 =>
vid0_do(63 downto 48) <= ram_data_reg;
done_vid0 := '1';
when PORT_VID1 =>
vid1_do(63 downto 48) <= ram_data_reg;
done_vid1 := '1';
when PORT_CPU6510 =>
null;
when others =>
null;
end case;
when RAM_WRITE_1 =>
currentBank <= (others => '-');
currentRow <= (others => '-');
currentCol <= (others => '-');
ramState <= RAM_WRITE_2;
sd_data_ena <= '1';
sd_we_n_reg <= '0';
sd_cas_n_reg <= '0';
sd_addr_reg <= resize(currentCol, sd_addr'length);
sd_data_reg <= currentWrData(15 downto 0);
sd_ldqm_reg <= currentLdqm;
sd_udqm_reg <= currentUdqm;
if currentLdqm = '1'
or currentUdqm = '1' then
-- This is a partial write, abort burst.
ramState <= RAM_WRITE_ABORT;
-- ramDone := '1';
end if;
currentWrData(47 downto 0) <= currentWrData(63 downto 16);
when RAM_WRITE_2 =>
currentBank <= (others => '-');
currentRow <= (others => '-');
currentCol <= (others => '-');
ramState <= RAM_WRITE_3;
sd_data_ena <= '1';
sd_data_reg <= currentWrData(15 downto 0);
currentWrData(47 downto 0) <= currentWrData(63 downto 16);
when RAM_WRITE_3 =>
currentBank <= (others => '-');
currentRow <= (others => '-');
currentCol <= (others => '-');
ramState <= RAM_WRITE_4;
sd_data_ena <= '1';
sd_data_reg <= currentWrData(15 downto 0);
currentWrData(47 downto 0) <= currentWrData(63 downto 16);
when RAM_WRITE_4 =>
currentWrData <= (others => '-');
currentBank <= (others => '-');
currentRow <= (others => '-');
currentCol <= (others => '-');
ramState <= RAM_WRITE_DLY;
sd_data_ena <= '1';
sd_data_reg <= currentWrData(15 downto 0);
-- currentWrData(47 downto 0) <= currentWrData(63 downto 16);
case currentPort is
when PORT_CACHE_1 =>
done_cache1 := '1';
when PORT_CACHE_2 =>
done_cache2 := '1';
when PORT_VID0 =>
done_vid0 := '1';
when PORT_VID1 =>
done_vid1 := '1';
when PORT_CPU6510 =>
done_cpu6510 := '1';
when others =>
null;
end case;
when RAM_WRITE_ABORT =>
currentWrData <= (others => '-');
currentBank <= (others => '-');
currentRow <= (others => '-');
currentCol <= (others => '-');
--currentPort <= PORT_NONE;
ramState <= RAM_WRITE_DLY;
sd_we_n_reg <= '0';
case currentPort is
when PORT_CACHE_1 =>
done_cache1 := '1';
when PORT_CACHE_2 =>
done_cache2 := '1';
when PORT_VID0 =>
done_vid0 := '1';
when PORT_VID1 =>
done_vid1 := '1';
when PORT_CPU6510 =>
done_cpu6510 := '1';
when others =>
null;
end case;
when RAM_WRITE_DLY =>
currentWrData <= (others => '-');
currentBank <= (others => '-');
currentRow <= (others => '-');
currentCol <= (others => '-');
currentPort <= PORT_NONE;
ramState <= RAM_IDLE;
when RAM_PRECHARGE =>
set_timer(timer, precharge_cycles);
ramState <= RAM_ACTIVE;
sd_we_n_reg <= '0';
sd_ras_n_reg <= '0';
bankActive(to_integer(currentBank)) <= '0';
when RAM_PRECHARGE_ALL =>
set_timer(timer, precharge_cycles);
ramState <= RAM_IDLE;
if refresh_active_reg = '1' then
set_timer(timer, 1);
ramState <= RAM_AUTOREFRESH;
end if;
sd_addr_reg(10) <= '1'; -- All banks
sd_we_n_reg <= '0';
sd_ras_n_reg <= '0';
bankActive <= "0000";
when RAM_AUTOREFRESH =>
set_timer(timer, refresh_clocks);
ramState <= RAM_IDLE;
sd_we_n_reg <= '1';
sd_ras_n_reg <= '0';
sd_cas_n_reg <= '0';
end case;
end if;
if enable_cache1_port and (done_cache1 = '1') then
cache1_ack_reg <= cache_req;
end if;
if enable_cache2_port and (done_cache2 = '1') then
cache2_ack_reg <= cache2_req;
end if;
if enable_vid0_port and (done_vid0 = '1') then
vid0_ack_reg <= vid0_req;
end if;
if enable_vid1_port and (done_vid1 = '1') then
vid1_ack_reg <= vid1_req;
end if;
if enable_cpu6510_port and (done_cpu6510 = '1') then
cpu6510_ack_reg <= cpu6510_req;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Debug and measurement signals
-- -----------------------------------------------------------------------
debugIdle <= '1' when ((refresh_active_reg = '0') and (ramState = RAM_IDLE)) else '0';
debugRefresh <= refresh_active_reg;
end architecture;
| lgpl-2.1 | 7db6d4b75e4ce13872c388f93ae4572c | 0.579216 | 3.066766 | false | false | false | false |
ARC-Lab-UF/UAA | src/add_tree_flt.vhd | 1 | 7,943 | -- Copyright (c) 2015 University of Florida
--
-- This file is part of uaa.
--
-- uaa is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- uaa is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with uaa. If not, see <http://www.gnu.org/licenses/>.
-- Greg Stitt
-- University of Florida
-- Entity: add_tree_flt
-- Description : A pipelined single-precision floating-point adder tree with
-- a generic number of inputs. To use the add tree, the inputs must be
-- converted from an array into a std_logic_vector to avoid limitations of
-- arrays of unconstrained types.
-- INSTRUCTIONS: use add_tree_flt_latency in add_tree_flt_pkg to calculate
-- cycle latency, which determines when output is valid.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.flt_pkg.all;
-------------------------------------------------------------------------------
-- Generic Descriptions
-- num_inputs : The number of inputs in the adder tree
-- opt : A string defining the optimization type to use for the floating-point
-- cores.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Port Descriptions
-- clk : clock
-- rst : reset
-- en : enable (active high), '0' stalls the pipeline
-- inputs : The inputs to the adder tree
-- output : The sum of all inputs
-------------------------------------------------------------------------------
entity add_tree_flt is
generic (
num_inputs : positive;
add_core_name : string := "";
width : positive);
port (
clk : in std_logic;
rst : in std_logic;
en : in std_logic;
input : in std_logic_vector(num_inputs*width-1 downto 0);
output : out std_logic_vector(width-1 downto 0));
end add_tree_flt;
architecture default of add_tree_flt is
type input_array is array(integer range<>) of std_logic_vector(width-1 downto 0);
-- calculates depth of the right subtree
function getRightDepth(numInputs : natural)
return natural is
variable return_val : natural;
begin
if (numInputs = 0) then
return_val := 0;
else
return_val := integer(ceil(log2(real(numInputs))));
end if;
return return_val;
end getRightDepth;
-- converts from input_array to std_logic_vector
function vectorize(input : input_array;
arraySize : natural;
elementWidth : positive) return std_logic_vector is
variable temp : std_logic_vector(arraySize*elementWidth-1 downto 0);
begin
for i in 0 to arraySize-1 loop
temp((i+1)*elementWidth-1 downto i*elementWidth) := input(input'left+i);
end loop;
return temp;
end function;
-- converts from std_logic_vector to input_array
function devectorize(input : std_logic_vector;
arraySize : natural;
elementWidth : positive) return input_array is
variable temp : input_array(0 to arraySize-1);
begin
for i in 0 to arraySize-1 loop
temp(i) := input((i+1)*elementWidth-1 downto i*elementWidth);
end loop;
return temp;
end function;
constant LEFT_TREE_INPUTS : natural := num_inputs - num_inputs/2;
constant RIGHT_TREE_INPUTS : natural := num_inputs/2;
constant LEFT_TREE_DEPTH : natural := integer(ceil(log2(real(LEFT_TREE_INPUTS))));
constant RIGHT_TREE_DEPTH : natural := getRightDepth(RIGHT_TREE_INPUTS);
constant TREE_DEPTH_DIFFERENCE : natural := LEFT_TREE_DEPTH-RIGHT_TREE_DEPTH;
signal left_tree_out : std_logic_vector(width-1 downto 0);
signal right_tree_out : std_logic_vector(width-1 downto 0);
signal right_tree_out_unaligned : std_logic_vector(width-1 downto 0);
signal inputs : input_array(0 to num_inputs-1);
signal left_temp : std_logic_vector(LEFT_TREE_INPUTS*width-1 downto 0);
signal right_temp : std_logic_vector(RIGHT_TREE_INPUTS*width-1 downto 0);
begin
-- convert big input vector into array of data
inputs <= devectorize(input, num_inputs, width);
-- recursion base cases
U_END1 : if (num_inputs = 1) generate
output <= inputs(0);
end generate U_END1;
U_END2 : if (num_inputs = 2) generate
U_ADD : entity work.add_flt
generic map (
core_name => add_core_name)
port map (
clk => clk,
en => en,
input1 => inputs(0),
input2 => inputs(1),
output => output);
end generate U_END2;
-- recursion to create tree
U_RECURSE : if (num_inputs > 2) generate
-- put left array inputs into a big vector
left_temp <= vectorize(inputs(num_inputs/2 to num_inputs-1), LEFT_TREE_INPUTS, width);
-- left adder sub tree. In the case of odd inputs, this tree gets one more
-- than the right tree
U_LEFT_TREE : entity work.add_tree_flt
generic map (
num_inputs => LEFT_TREE_INPUTS,
add_core_name => add_core_name,
width => width)
port map (
clk => clk,
rst => rst,
en => en,
input => left_temp,
output => left_tree_out);
-- put right array inputs into a big vector
right_temp <= vectorize(inputs(0 to num_inputs/2-1), RIGHT_TREE_INPUTS, width);
-- right adder tree
U_RIGHT_TREE : entity work.add_tree_flt
generic map (
num_inputs => RIGHT_TREE_INPUTS,
add_core_name => add_core_name,
width => width)
port map (
clk => clk,
rst => rst,
en => en,
input => right_temp,
output => right_tree_out_unaligned);
-- if there are an odd number of inputs, we need to delay the right
-- subtree by the difference in the depth of the left and right
U_ALIGN_ODD : if num_inputs mod 2 /= 0 generate
U_DELAY : entity work.delay
generic map (
cycles => add_flt_latency(add_core_name)*TREE_DEPTH_DIFFERENCE,
width => right_tree_out_unaligned'length,
init => std_logic_vector(to_unsigned(0, right_tree_out_unaligned'length)))
port map (
clk => clk,
rst => rst,
en => en,
input => right_tree_out_unaligned,
output => right_tree_out);
end generate U_ALIGN_ODD;
-- no alignment needed for even inputs
U_ALIGN_EVEN : if num_inputs mod 2 = 0 generate
right_tree_out <= right_tree_out_unaligned;
end generate U_ALIGN_EVEN;
-- add the two sub tree results
U_ADD_TREES : entity work.add_flt
generic map (
core_name => add_core_name)
port map (
clk => clk,
en => en,
input1 => left_tree_out,
input2 => right_tree_out,
output => output);
end generate U_RECURSE;
end default;
| gpl-3.0 | 45bb1239455847f08eb001d56f09a0b0 | 0.556339 | 4.160817 | false | false | false | false |
hoglet67/CoPro6502 | test/TestBench.vhd | 1 | 8,096 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:24:00 10/29/2014
-- Design Name:
-- Module Name: /home/dmb/atom/CoPro6502/TestBench.vhd
-- Project Name: CoPro6502
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: CoPro6502
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE std.textio.all;
USE ieee.std_logic_textio.all;
use work.txt_util.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY TestBench IS
END TestBench;
ARCHITECTURE behavior OF TestBench IS
--task para_write;
-- input [2:0] addr;
-- input [7:0] data;
-- begin
-- @ (negedge HO2);
-- PA = addr;
-- PDIN = data;
-- PNWDS = 0;
-- PCS = 0;
-- @ (negedge HO2);
-- PCS = 1;
-- PA = "000;
-- PDIN = "00000000;
-- PNWDS = 1;
-- end
-- endtask
-- task para_read;
-- input [2:0] addr;
-- input [7:0] expected_mask;
-- input [7:0] expected_data;
-- begin
-- @ (negedge HO2);
-- PA = addr;
-- PNRDS = 0;
-- PCS = 0;
-- @ (posedge HO2);
-- if ((PDOUT & expected_mask) != expected_data)
-- $display("%0dns: para addr %0d data error detected; expected_mask = %b; expected_data = %b; actual_data = %b", $time, PA, expected_mask, expected_data, PDOUT);
-- @ (negedge HO2);
-- PCS = 1;
-- PA = "000;
-- PNRDS = 1;
-- end
-- endtask
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT CoPro6502
PORT(
fastclk : IN std_logic;
tp : OUT std_logic_vector(8 downto 2);
sw : IN std_logic_vector(2 downto 1);
fcs : OUT std_logic;
h_phi2 : IN std_logic;
h_addr : IN std_logic_vector(2 downto 0);
h_data : INOUT std_logic_vector(7 downto 0);
h_rdnw : IN std_logic;
h_cs_b : IN std_logic;
h_rst_b : IN std_logic;
h_irq_b : INOUT std_logic;
ram_cs : OUT std_logic;
ram_oe : OUT std_logic;
ram_wr : OUT std_logic;
ram_addr : OUT std_logic_vector(18 downto 0);
ram_data : INOUT std_logic_vector(7 downto 0)
);
END COMPONENT;
COMPONENT SRAM
PORT(
ADDR : in std_logic_vector(15 downto 0);
DATA : inout std_logic_vector(7 downto 0);
OE : in std_logic;
WE : in std_logic;
CS : in std_logic
);
END COMPONENT;
--Inputs
signal fastclk : std_logic := '0';
signal sw : std_logic_vector(2 downto 1) := (others => '0');
signal h_phi2 : std_logic := '0';
signal h_addr : std_logic_vector(2 downto 0) := (others => '0');
signal h_rdnw : std_logic := '1';
signal h_cs_b : std_logic := '1';
signal h_rst_b : std_logic := '1';
--BiDirs
signal h_data : std_logic_vector(7 downto 0);
signal h_irq_b : std_logic;
signal ram_data : std_logic_vector(7 downto 0);
--Outputs
signal tp : std_logic_vector(8 downto 2);
signal fcs : std_logic;
signal ram_cs : std_logic;
signal ram_oe : std_logic;
signal ram_wr : std_logic;
signal ram_addr : std_logic_vector(18 downto 0);
-- Clock period definitions
constant fastclk_period : time := 10 ns;
constant phi2_period : time := 250 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: CoPro6502 PORT MAP (
fastclk => fastclk,
tp => tp,
sw => sw,
fcs => fcs,
h_phi2 => h_phi2,
h_addr => h_addr,
h_data => h_data,
h_rdnw => h_rdnw,
h_cs_b => h_cs_b,
h_rst_b => h_rst_b,
h_irq_b => h_irq_b,
ram_cs => ram_cs,
ram_oe => ram_oe,
ram_wr => ram_wr,
ram_addr => ram_addr,
ram_data => ram_data
);
inst_sram: SRAM PORT MAP (
ADDR => ram_addr(15 downto 0),
DATA => ram_data,
OE => ram_oe,
WE => ram_wr,
CS => ram_cs
);
-- Clock process definitions
fastclk_process :process
begin
fastclk <= '0';
wait for fastclk_period/2;
fastclk <= '1';
wait for fastclk_period/2;
end process;
phi2_process :process
begin
h_phi2 <= '0';
wait for phi2_period/2;
h_phi2 <= '1';
wait for phi2_period/2;
end process;
-- Stimulus process
stim_proc: process
procedure host_write (
addr : in std_logic_vector(2 downto 0);
data : in std_logic_vector(7 downto 0)
) is
begin
wait until falling_edge(h_phi2);
h_addr <= addr;
h_data <= data;
h_rdnw <= '0';
h_cs_b <= '0';
wait until falling_edge(h_phi2);
h_cs_b <= '1';
h_addr <= "000";
h_data <= "ZZZZZZZZ";
h_rdnw <= '1';
end host_write;
procedure delay (
n : in integer
) is
begin
for i in 0 to n loop
wait until falling_edge(h_phi2);
end loop;
end delay;
procedure host_read (
addr : in std_logic_vector(2 downto 0);
expected_mask : in std_logic_vector(7 downto 0);
expected_data : in std_logic_vector(7 downto 0)
) is
begin
wait until falling_edge(h_phi2);
h_addr <= addr;
h_rdnw <= '1';
h_cs_b <= '0';
wait until falling_edge(h_phi2);
if ((h_data and expected_mask) /= expected_data) then
report " data error detected: host addr" & str(h_addr) severity note;
report " expected_mask = " & str(expected_mask) severity note;
report " expected_data = " & str(expected_data) severity note;
report " actual_data = " & str(h_data) severity note;
end if;
wait until falling_edge(h_phi2);
h_cs_b <= '1';
h_addr <= "000";
h_rdnw <= '1';
end host_read;
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait until falling_edge(h_phi2);
h_rst_b <= '0';
for i in 0 to 99 loop
wait until falling_edge(h_phi2);
end loop;
h_rst_b <= '1';
wait for 1 ms;
delay(10);
-- Take PRST high, low, high
host_write("000", "00100000");
host_write("000", "10100000");
host_write("000", "00100000");
host_read("000", "00000000", "00000000");
delay(10);
-- De-Assert soft reset (up until this point it will be X)
host_write("000", "01000000");
delay(10);
-- Assert soft reset for atleast 24 clocks to flush the 24 byte FIFO
host_write("000", "11000000");
delay(50);
-- De-Assert soft reset
host_write("000", "01000000");
delay(10);
-- Disable all interrupts
host_write("000", "00001111");
-- Set two byte mode for register 3
host_write("000", "00010000");
-- Enable NMI (M=1)
host_write("000", "10001000");
-- Check the control bits are as expected
host_read("000", "11111111", "01001000");
-- Read the junk byte out of register 3
-- para_read("100", "11000000", "00000000"); -- N=0 _F=0
host_read("101", "00000000", "00000000");
-- para_read("100", "11000000", "11000000"); -- N=1 _F=1
delay(10);
wait for 1000 ms;
end process;
END;
| gpl-3.0 | a4b9211285dc08edb72a917dddf4f868 | 0.525568 | 3.443641 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-nuhorizons-3s1500/testbench.vhd | 1 | 13,679 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.config.all; -- configuration
use work.debug.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 8+8*CFG_MCTRL_RAM16BIT; -- rom data width (8/16)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 18; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
component leon3mp
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
pb_sw : in std_logic_vector (4 downto 1); -- push buttons
pll_clk : in std_ulogic; -- PLL clock
led : out std_logic_vector(8 downto 1);
flash_a : out std_logic_vector(20 downto 0);
flash_d : inout std_logic_vector(15 downto 0);
sdram_a : out std_logic_vector(11 downto 0);
sdram_d : inout std_logic_vector(31 downto 0);
sdram_ba : out std_logic_vector(3 downto 0);
sdram_dqm : out std_logic_vector(3 downto 0);
sdram_clk : inout std_ulogic;
sdram_cke : out std_ulogic; -- sdram clock enable
sdram_csn : out std_ulogic; -- sdram chip select
sdram_wen : out std_ulogic; -- sdram write enable
sdram_rasn : out std_ulogic; -- sdram ras
sdram_casn : out std_ulogic; -- sdram cas
uart1_txd : out std_ulogic;
uart1_rxd : in std_ulogic;
uart1_rts : out std_ulogic;
uart1_cts : in std_ulogic;
uart2_txd : out std_ulogic;
uart2_rxd : in std_ulogic;
uart2_rts : out std_ulogic;
uart2_cts : in std_ulogic;
flash_oen : out std_ulogic;
flash_wen : out std_ulogic;
flash_cen : out std_ulogic;
flash_byte : out std_ulogic;
flash_ready : in std_ulogic;
flash_rpn : out std_ulogic;
flash_wpn : out std_ulogic;
phy_mii_data: inout std_logic; -- ethernet PHY interface
phy_tx_clk : in std_ulogic;
phy_rx_clk : in std_ulogic;
phy_rx_data : in std_logic_vector(3 downto 0);
phy_dv : in std_ulogic;
phy_rx_er : in std_ulogic;
phy_col : in std_ulogic;
phy_crs : in std_ulogic;
phy_tx_data : out std_logic_vector(3 downto 0);
phy_tx_en : out std_ulogic;
phy_mii_clk : out std_ulogic;
phy_100 : in std_ulogic; -- 100 Mbit indicator
phy_rst_n : out std_ulogic;
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
-- lcd_data : inout std_logic_vector(7 downto 0);
-- lcd_rs : out std_ulogic;
-- lcd_rw : out std_ulogic;
-- lcd_en : out std_ulogic;
-- lcd_backl : out std_ulogic;
can_txd : out std_ulogic;
can_rxd : in std_ulogic;
smsc_addr : out std_logic_vector(14 downto 0);
smsc_data : inout std_logic_vector(31 downto 0);
smsc_nbe : out std_logic_vector(3 downto 0);
smsc_resetn : out std_ulogic;
smsc_ardy : in std_ulogic;
-- smsc_intr : in std_ulogic;
smsc_nldev : in std_ulogic;
smsc_nrd : out std_ulogic;
smsc_nwr : out std_ulogic;
smsc_ncs : out std_ulogic;
smsc_aen : out std_ulogic;
smsc_lclk : out std_ulogic;
smsc_wnr : out std_ulogic;
smsc_rdyrtn : out std_ulogic;
smsc_cycle : out std_ulogic;
smsc_nads : out std_ulogic
);
end component;
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(21 downto 0);
signal flash_d : std_logic_vector(15 downto 0);
signal romsn : std_ulogic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal error : std_logic;
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal sdcke : std_ulogic; -- clk en
signal sdcsn : std_ulogic; -- chip sel
signal sdwen : std_ulogic; -- write en
signal sdrasn : std_ulogic; -- row addr stb
signal sdcasn : std_ulogic; -- col addr stb
signal sddqm : std_logic_vector ( 3 downto 0); -- data i/o mask
signal sdclk : std_ulogic;
signal txd1, rxd1 : std_ulogic;
signal txd2, rxd2 : std_ulogic;
signal etx_clk, erx_clk, erx_dv, erx_er, erx_col, erx_crs, etx_en, etx_er : std_logic:='0';
signal erxd, etxd: std_logic_vector(3 downto 0):=(others=>'0');
signal erxdt, etxdt: std_logic_vector(7 downto 0):=(others=>'0');
signal emdc, emdio: std_logic;
signal gtx_clk : std_ulogic;
signal ereset : std_logic;
signal led : std_logic_vector(8 downto 1);
constant lresp : boolean := false;
signal sa : std_logic_vector(14 downto 0);
signal ba : std_logic_vector(3 downto 0);
signal sd : std_logic_vector(31 downto 0);
signal pb_sw : std_logic_vector(4 downto 1);
signal lcd_data : std_logic_vector(7 downto 0);
signal lcd_rs : std_ulogic;
signal lcd_rw : std_ulogic;
signal lcd_en : std_ulogic;
signal lcd_backl: std_ulogic;
signal can_txd : std_ulogic;
signal can_rxd : std_ulogic;
signal gpio : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal smsc_addr : std_logic_vector(21 downto 0);
signal smsc_data : std_logic_vector(31 downto 0);
signal smsc_nbe : std_logic_vector(3 downto 0);
signal smsc_resetn : std_ulogic;
signal smsc_ardy : std_ulogic;
signal smsc_intr : std_ulogic;
signal smsc_nldev : std_ulogic;
signal smsc_nrd : std_ulogic;
signal smsc_nwr : std_ulogic;
signal smsc_ncs : std_ulogic;
signal smsc_aen : std_ulogic;
signal smsc_lclk : std_ulogic;
signal smsc_wnr : std_ulogic;
signal smsc_rdyrtn : std_ulogic;
signal smsc_cycle : std_ulogic;
signal smsc_nads : std_ulogic;
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
rst <= dsurst;
dsuen <= '1'; dsubre <= '0'; rxd1 <= '1';
can_rxd <= '1'; error <= led(8); sa(14 downto 12) <= "000";
pb_sw <= rst & "00" & dsubre;
cpu : leon3mp
generic map ( fabtech, memtech, padtech, clktech,
disas, dbguart, pclow )
port map (pb_sw, clk, led, address(21 downto 1), flash_d,
sa(11 downto 0), sd, ba, sddqm, sdclk, sdcke, sdcsn, sdwen, sdrasn,
sdcasn, txd1, rxd1, open, gnd, dsutx, dsurx, open, gnd,
oen, writen, romsn, open, vcc, open, open,
emdio, etx_clk, erx_clk, erxd, erx_dv, erx_er, erx_col, erx_crs,
etxd, etx_en, emdc, gnd, ereset, gpio,
-- lcd_data, lcd_rs, lcd_rw, lcd_en, lcd_backl,
can_txd, can_rxd,
smsc_addr(14 downto 0), smsc_data, smsc_nbe, smsc_resetn, smsc_ardy,-- smsc_intr,
smsc_nldev, smsc_nrd, smsc_nwr, smsc_ncs, smsc_aen, smsc_lclk,
smsc_wnr, smsc_rdyrtn, smsc_cycle, smsc_nads);
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => ba(1 downto 0), Clk => sdclk, Cke => sdcke,
Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => ba(3 downto 2), Clk => sdclk, Cke => sdcke,
Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
rom8 : if romwidth /= 16 generate
prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile)
port map (address(romdepth downto 1), flash_d(15 downto 0), gnd, gnd,
romsn, writen, oen);
address(0) <= flash_d(15);
end generate;
rom16 : if romwidth = 16 generate
prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile)
port map (address(romdepth downto 1), flash_d(15 downto 0), gnd, gnd,
romsn, writen, oen);
address(0) <= '0';
end generate;
emdio <= 'H';
erxd <= erxdt(3 downto 0);
etxdt <= "0000" & etxd;
p0: phy
generic map(base1000_t_fd => 0, base1000_t_hd => 0)
port map(rst, emdio, etx_clk, erx_clk, erxdt, erx_dv,
erx_er, erx_col, erx_crs, etxdt, etx_en, etx_er, emdc, gtx_clk);
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2000 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
flash_d <= buskeep(flash_d) after 5 ns;
sd <= buskeep(sd) after 5 ns;
smsc_data <= buskeep(smsc_data) after 5 ns;
smsc_addr(21 downto 15) <= (others => '0');
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), smsc_data,
smsc_ncs, oen, writen, open);
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#00#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
wait;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#aa#, txp);
txa(dsutx, 16#00#, 16#55#, 16#00#, 16#55#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#a0#, txp);
txa(dsutx, 16#01#, 16#02#, 16#09#, 16#33#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#80#, 16#00#, 16#02#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
| gpl-3.0 | 61f5ed912337192c01a55351dabba489 | 0.592222 | 3.046548 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/maps/leon4_net.vhd | 1 | 22,996 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use work.gencomp.all;
entity leon4_net is
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 31 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
cached : integer := 0;
scantest : integer := 0
);
port (
clk : in std_ulogic;
gclk : in std_ulogic;
hclken : in std_ulogic;
rstn : in std_ulogic;
ahbix : in ahb_mst_in_type;
ahbox : out ahb_mst_out_type;
ahbsix : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi_irl: in std_logic_vector(3 downto 0);
irqi_rst: in std_ulogic;
irqi_run: in std_ulogic;
irqi_rstvec: in std_logic_vector(31 downto 12);
irqi_iact: in std_ulogic;
irqi_index: in std_logic_vector(3 downto 0);
irqi_hrdrst: in std_ulogic;
irqo_intack: out std_ulogic;
irqo_irl: out std_logic_vector(3 downto 0);
irqo_pwd: out std_ulogic;
irqo_fpen: out std_ulogic;
irqo_idle: out std_ulogic;
dbgi_dsuen: in std_ulogic; -- DSU enable
dbgi_denable: in std_ulogic; -- diagnostic register access enable
dbgi_dbreak: in std_ulogic; -- debug break-in
dbgi_step: in std_ulogic; -- single step
dbgi_halt: in std_ulogic; -- halt processor
dbgi_reset: in std_ulogic; -- reset processor
dbgi_dwrite: in std_ulogic; -- read/write
dbgi_daddr: in std_logic_vector(23 downto 2); -- diagnostic address
dbgi_ddata: in std_logic_vector(31 downto 0); -- diagnostic data
dbgi_btrapa: in std_ulogic; -- break on IU trap
dbgi_btrape: in std_ulogic; -- break on IU trap
dbgi_berror: in std_ulogic; -- break on IU error mode
dbgi_bwatch: in std_ulogic; -- break on IU watchpoint
dbgi_bsoft: in std_ulogic; -- break on software breakpoint (TA 1)
dbgi_tenable: in std_ulogic;
dbgi_timer: in std_logic_vector(63 downto 0);
dbgo_data: out std_logic_vector(31 downto 0);
dbgo_crdy: out std_ulogic;
dbgo_dsu: out std_ulogic;
dbgo_dsumode: out std_ulogic;
dbgo_error: out std_ulogic;
dbgo_halt: out std_ulogic;
dbgo_pwd: out std_ulogic;
dbgo_idle: out std_ulogic;
dbgo_ipend: out std_ulogic;
dbgo_icnt: out std_ulogic;
dbgo_fcnt : out std_ulogic;
dbgo_optype : out std_logic_vector(5 downto 0); -- instruction type
dbgo_bpmiss : out std_ulogic; -- branch predict miss
dbgo_istat_cmiss: out std_ulogic;
dbgo_istat_tmiss: out std_ulogic;
dbgo_istat_chold: out std_ulogic;
dbgo_istat_mhold: out std_ulogic;
dbgo_dstat_cmiss: out std_ulogic;
dbgo_dstat_tmiss: out std_ulogic;
dbgo_dstat_chold: out std_ulogic;
dbgo_dstat_mhold: out std_ulogic;
dbgo_wbhold : out std_ulogic; -- write buffer hold
dbgo_su : out std_ulogic;
dbgo_ducnt : out std_ulogic);
end ;
architecture rtl of leon4_net is
signal disasen : std_ulogic;
component leon4_ut90nhbd
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 1 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 1 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 31 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
cached : integer := 0;
scantest : integer := 0
);
port (
clk: in std_ulogic;
gclk: in std_ulogic;
hclken: in std_ulogic;
rstn: in std_ulogic;
ahbi_hgrant: in std_logic_vector(0 to NAHBMST-1); -- bus grant
ahbi_hready: in std_ulogic; -- transfer done
ahbi_hresp: in std_logic_vector(1 downto 0); -- response type
ahbi_hrdata: in std_logic_vector(127 downto 0); -- read data bus
ahbi_hirq: in std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
ahbi_testen: in std_ulogic;
ahbi_testrst: in std_ulogic;
ahbi_scanen: in std_ulogic;
ahbi_testoen: in std_ulogic;
ahbo_hbusreq: out std_ulogic; -- bus request
ahbo_hlock: out std_ulogic; -- lock request
ahbo_htrans: out std_logic_vector(1 downto 0); -- transfer type
ahbo_haddr: out std_logic_vector(31 downto 0); -- address bus (byte)
ahbo_hwrite: out std_ulogic; -- read/write
ahbo_hsize: out std_logic_vector(2 downto 0); -- transfer size
ahbo_hburst: out std_logic_vector(2 downto 0); -- burst type
ahbo_hprot: out std_logic_vector(3 downto 0); -- protection control
ahbo_hwdata: out std_logic_vector(127 downto 0); -- write data bus
ahbo_hirq: out std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt bus
ahbsi_hsel: in std_logic_vector(0 to NAHBSLV-1); -- slave select
ahbsi_haddr: in std_logic_vector(31 downto 0); -- address bus (byte)
ahbsi_hwrite: in std_ulogic; -- read/write
ahbsi_htrans: in std_logic_vector(1 downto 0); -- transfer type
ahbsi_hsize: in std_logic_vector(2 downto 0); -- transfer size
ahbsi_hburst: in std_logic_vector(2 downto 0); -- burst type
ahbsi_hwdata: in std_logic_vector(127 downto 0); -- write data bus
ahbsi_hprot: in std_logic_vector(3 downto 0); -- protection control
ahbsi_hready: in std_ulogic; -- transfer done
ahbsi_hmaster: in std_logic_vector(3 downto 0); -- current master
ahbsi_hmastlock: in std_ulogic; -- locked access
ahbsi_hmbsel: in std_logic_vector(0 to NAHBAMR-1); -- memory bank select
ahbsi_hirq: in std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
irqi_irl: in std_logic_vector(3 downto 0);
irqi_rst: in std_ulogic;
irqi_run: in std_ulogic;
irqi_rstvec: in std_logic_vector(31 downto 12);
irqi_iact: in std_ulogic;
irqi_index: in std_logic_vector(3 downto 0);
irqo_intack: out std_ulogic;
irqo_irl: out std_logic_vector(3 downto 0);
irqo_pwd: out std_ulogic;
irqo_fpen: out std_ulogic;
irqo_idle: out std_ulogic;
dbgi_dsuen: in std_ulogic; -- DSU enable
dbgi_denable: in std_ulogic; -- diagnostic register access enable
dbgi_dbreak: in std_ulogic; -- debug break-in
dbgi_step: in std_ulogic; -- single step
dbgi_halt: in std_ulogic; -- halt processor
dbgi_reset: in std_ulogic; -- reset processor
dbgi_dwrite: in std_ulogic; -- read/write
dbgi_daddr: in std_logic_vector(23 downto 2); -- diagnostic address
dbgi_ddata: in std_logic_vector(31 downto 0); -- diagnostic data
dbgi_btrapa: in std_ulogic; -- break on IU trap
dbgi_btrape: in std_ulogic; -- break on IU trap
dbgi_berror: in std_ulogic; -- break on IU error mode
dbgi_bwatch: in std_ulogic; -- break on IU watchpoint
dbgi_bsoft: in std_ulogic; -- break on software breakpoint (TA 1)
dbgi_tenable: in std_ulogic;
dbgi_timer: in std_logic_vector(30 downto 0);
dbgo_data: out std_logic_vector(31 downto 0);
dbgo_crdy: out std_ulogic;
dbgo_dsu: out std_ulogic;
dbgo_dsumode: out std_ulogic;
dbgo_error: out std_ulogic;
dbgo_halt: out std_ulogic;
dbgo_pwd: out std_ulogic;
dbgo_idle: out std_ulogic;
dbgo_ipend: out std_ulogic;
dbgo_icnt: out std_ulogic;
dbgo_fcnt : out std_ulogic;
dbgo_optype : out std_logic_vector(5 downto 0); -- instruction type
dbgo_bpmiss : out std_ulogic; -- branch predict miss
dbgo_istat_cmiss: out std_ulogic;
dbgo_istat_tmiss: out std_ulogic;
dbgo_istat_chold: out std_ulogic;
dbgo_istat_mhold: out std_ulogic;
dbgo_dstat_cmiss: out std_ulogic;
dbgo_dstat_tmiss: out std_ulogic;
dbgo_dstat_chold: out std_ulogic;
dbgo_dstat_mhold: out std_ulogic;
dbgo_wbhold : out std_ulogic; -- write buffer hold
dbgo_su : out std_ulogic;
disasen : in std_ulogic);
end component;
signal ahbi_hgrant: std_logic_vector(0 to NAHBMST-1);
signal ahbi_hready: std_ulogic;
signal ahbi_hresp: std_logic_vector(1 downto 0);
signal ahbi_hrdata: std_logic_vector(127 downto 0);
signal ahbi_hirq: std_logic_vector(NAHBIRQ-1 downto 0);
signal ahbi_testen: std_ulogic;
signal ahbi_testrst: std_ulogic;
signal ahbi_scanen: std_ulogic;
signal ahbi_testoen: std_ulogic;
signal ahbo_hbusreq: std_ulogic;
signal ahbo_hlock: std_ulogic;
signal ahbo_htrans: std_logic_vector(1 downto 0);
signal ahbo_haddr: std_logic_vector(31 downto 0);
signal ahbo_hwrite: std_ulogic;
signal ahbo_hsize: std_logic_vector(2 downto 0);
signal ahbo_hburst: std_logic_vector(2 downto 0);
signal ahbo_hprot: std_logic_vector(3 downto 0);
signal ahbo_hwdata: std_logic_vector(127 downto 0);
signal ahbo_hirq: std_logic_vector(NAHBIRQ-1 downto 0);
signal ahbsi_hsel: std_logic_vector(0 to NAHBSLV-1);
signal ahbsi_haddr: std_logic_vector(31 downto 0);
signal ahbsi_hwrite: std_ulogic;
signal ahbsi_htrans: std_logic_vector(1 downto 0);
signal ahbsi_hsize: std_logic_vector(2 downto 0);
signal ahbsi_hburst: std_logic_vector(2 downto 0);
signal ahbsi_hwdata: std_logic_vector(127 downto 0);
signal ahbsi_hprot: std_logic_vector(3 downto 0);
signal ahbsi_hready: std_ulogic;
signal ahbsi_hmaster: std_logic_vector(3 downto 0);
signal ahbsi_hmastlock: std_ulogic;
signal ahbsi_hmbsel: std_logic_vector(0 to NAHBAMR-1);
signal ahbsi_hirq: std_logic_vector(NAHBIRQ-1 downto 0);
constant hconfig: ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_LEON4, 0, 0, 0),
others => zero32);
begin
disasen <= '1' when disas /= 0 else '0';
-- Plug&Play information
ahbox.hconfig <= hconfig;
ahbox.hindex <= hindex;
ut09 : if fabtech = ut90 generate
wrp: leon4_ut90nhbd
generic map (fpu => fpu, v8 => v8, mmuen => mmuen, isets => isets, isetsize => isetsize, smp => smp)
port map(
clk => clk,
gclk => gclk,
hclken => hclken,
rstn => rstn,
ahbi_hgrant => ahbi_hgrant,
ahbi_hready => ahbi_hready,
ahbi_hresp => ahbi_hresp,
ahbi_hrdata => ahbi_hrdata,
ahbi_hirq => ahbi_hirq,
ahbi_testen => ahbi_testen,
ahbi_testrst => ahbi_testrst,
ahbi_scanen => ahbi_scanen,
ahbi_testoen => ahbi_testoen,
ahbo_hbusreq => ahbo_hbusreq,
ahbo_hlock => ahbo_hlock,
ahbo_htrans => ahbo_htrans,
ahbo_haddr => ahbo_haddr,
ahbo_hwrite => ahbo_hwrite,
ahbo_hsize => ahbo_hsize,
ahbo_hburst => ahbo_hburst,
ahbo_hprot => ahbo_hprot,
ahbo_hwdata => ahbo_hwdata,
ahbo_hirq => ahbo_hirq,
ahbsi_hsel => ahbsi_hsel,
ahbsi_haddr => ahbsi_haddr,
ahbsi_hwrite => ahbsi_hwrite,
ahbsi_htrans => ahbsi_htrans,
ahbsi_hsize => ahbsi_hsize,
ahbsi_hburst => ahbsi_hburst,
ahbsi_hwdata => ahbsi_hwdata,
ahbsi_hprot => ahbsi_hprot,
ahbsi_hready => ahbsi_hready,
ahbsi_hmaster => ahbsi_hmaster,
ahbsi_hmastlock => ahbsi_hmastlock,
ahbsi_hmbsel => ahbsi_hmbsel,
ahbsi_hirq => ahbsi_hirq,
irqi_irl => irqi_irl,
irqi_rst => irqi_rst,
irqi_run => irqi_run,
irqi_rstvec => irqi_rstvec,
irqi_iact => irqi_iact,
irqi_index => irqi_index,
irqo_intack => irqo_intack,
irqo_irl => irqo_irl,
irqo_pwd => irqo_pwd,
irqo_fpen => irqo_fpen,
irqo_idle => irqo_idle,
dbgi_dsuen => dbgi_dsuen,
dbgi_denable => dbgi_denable,
dbgi_dbreak => dbgi_dbreak,
dbgi_step => dbgi_step,
dbgi_halt => dbgi_halt,
dbgi_reset => dbgi_reset,
dbgi_dwrite => dbgi_dwrite,
dbgi_daddr => dbgi_daddr,
dbgi_ddata => dbgi_ddata,
dbgi_btrapa => dbgi_btrapa,
dbgi_btrape => dbgi_btrape,
dbgi_berror => dbgi_berror,
dbgi_bwatch => dbgi_bwatch,
dbgi_bsoft => dbgi_bsoft,
dbgi_tenable => dbgi_tenable,
dbgi_timer => dbgi_timer(30 downto 0),
dbgo_data => dbgo_data,
dbgo_crdy => dbgo_crdy,
dbgo_dsu => dbgo_dsu,
dbgo_dsumode => dbgo_dsumode,
dbgo_error => dbgo_error,
dbgo_halt => dbgo_halt,
dbgo_pwd => dbgo_pwd,
dbgo_idle => dbgo_idle,
dbgo_ipend => dbgo_ipend,
dbgo_icnt => dbgo_icnt,
dbgo_fcnt => dbgo_fcnt,
dbgo_optype => dbgo_optype,
dbgo_bpmiss => dbgo_bpmiss,
dbgo_istat_cmiss => dbgo_istat_cmiss,
dbgo_istat_tmiss => dbgo_istat_tmiss,
dbgo_istat_chold => dbgo_istat_chold,
dbgo_istat_mhold => dbgo_istat_mhold,
dbgo_dstat_cmiss => dbgo_dstat_cmiss,
dbgo_dstat_tmiss => dbgo_dstat_tmiss,
dbgo_dstat_chold => dbgo_dstat_chold,
dbgo_dstat_mhold => dbgo_dstat_mhold,
dbgo_wbhold => dbgo_wbhold,
dbgo_su => dbgo_su,
disasen => disasen);
dbgo_ducnt <= '1';
end generate;
ahbi_hgrant(0) <= ahbix.hgrant(hindex);
ahbi_hgrant(1 to NAHBMST-1) <= (others => '0');
ahbi_hready <= ahbix.hready;
ahbi_hresp <= ahbix.hresp;
ahbi_hrdata(127 mod AHBDW downto 0) <= ahbix.hrdata(127 mod AHBDW downto 0);
ahbi_hirq <= ahbix.hirq;
ahbi_testen <= ahbix.testen;
ahbi_testrst <= ahbix.testrst;
ahbi_scanen <= ahbix.scanen;
ahbi_testoen <= ahbix.testoen;
ahbox.hbusreq <= ahbo_hbusreq;
ahbox.hlock <= ahbo_hlock;
ahbox.htrans <= ahbo_htrans;
ahbox.haddr <= ahbo_haddr;
ahbox.hwrite <= ahbo_hwrite;
ahbox.hsize <= ahbo_hsize(2 downto 0);
ahbox.hburst <= "00" & ahbo_hburst(0);
ahbox.hprot <= ahbo_hprot;
ahbox.hwdata(127 mod AHBDW downto 0) <= ahbo_hwdata(127 mod AHBDW downto 0);
ahbox.hirq <= (others => '0'); --ahbo_hirq;
ahbsi_hsel <= ahbsix.hsel;
ahbsi_haddr <= ahbsix.haddr;
ahbsi_hwrite <= ahbsix.hwrite;
ahbsi_htrans <= ahbsix.htrans;
ahbsi_hsize <= ahbsix.hsize;
ahbsi_hburst <= ahbsix.hburst;
ahbsi_hwdata(127 mod AHBDW downto 0) <= ahbsix.hwdata(127 mod AHBDW downto 0);
ahbsi_hprot <= ahbsix.hprot;
ahbsi_hready <= ahbsix.hready;
ahbsi_hmaster <= ahbsix.hmaster;
ahbsi_hmastlock <= ahbsix.hmastlock;
ahbsi_hmbsel <= ahbsix.hmbsel;
ahbsi_hirq <= ahbsix.hirq;
-- pragma translate_off
assert NAHBSLV=16
report "LEON4FT netlist: Only NAHBSLV=16 supported by wrapper"
severity Failure;
-- pragma translate_on
end architecture;
| gpl-3.0 | ad6f8ab09c53c25c0633d94b4e942868 | 0.511176 | 3.873337 | false | false | false | false |
kdgwill/VHDL_Framer_Example | VHDL_Framer_Example/Example1/generator.vhd | 2 | 2,215 | ---------------------------------------------------------------------------------
--Generator------------------------------------------------------------
--By Kyle Williams, 04/07/2011--------------------------------------------------
--PROJECT DESCRIPTION------------------------------------------------------------
--1--Input Serial data stream----------------------------------------------------
----------------Define Libraries to be used--------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
-----------------ENTITY FOR GENERATOR------------------------------------------
ENTITY generator IS
Generic(N : Integer := 8);
PORT(
clock, reset, load: OUT std_logic;
D : OUT std_logic_vector(n-1 downto 0);
vec : OUT std_logic_vector(N-1 downto 0);
sin : OUT STD_Logic
);
END generator;
-----------------BEHAVIOR OF GENERATOR-----------------------------------------
ARCHITECTURE behavior OF generator IS
-------------------VARIABLE DECLARATION----------------------------------------
signal S_clock: std_logic := '0';
signal S_D: std_logic_vector(n-1 downto 0) := (others =>'0');
signal S_reset: std_logic := '0';
signal S_load: std_logic :='0';
signal tap: std_logic;
signal ssr: std_logic_vector(n-1 downto 0);
-------------------PROCEDUREE------------------------------
BEGIN
S_clock <= not S_clock after 5 ns;
S_D <= "10101011" after 250 ns;
S_reset <= '1' after 10 ns;
process
begin
S_load <= '1';
wait for 10 ns;
S_load <= '0';
wait for 10 ns;
end process;
clock <= S_clock;
reset <= S_reset;
load <= S_load;
D <= S_D;
Process(S_Clock,S_Reset,S_Load)
Begin
If(S_reset='0') then
SSR <= (others => '0');
elsif rising_edge(S_Clock) Then
IF S_Load = '1' AND (SSR="00000000" OR SSR="11111111") Then
SSR <= S_D;
ELSE
SSR<= SSR(6 downTo 0)&tap;
END If;
End If;
tap<=SSR(1) XOR SSR(2) XOR SSR(3) XOR SSR(7);
sin<= SSR(7);
vec<= SSR;
End Process;
END behavior;
| gpl-3.0 | ca29947061807b43abe61079f73eb74f | 0.422573 | 4.179245 | false | false | false | false |
pwsoft/fpga_examples | rtl/chameleon/chameleon_spi_flash.vhd | 1 | 7,394 | -- -----------------------------------------------------------------------
--
-- Turbo Chameleon
--
-- Multi purpose FPGA expansion for the Commodore 64 computer
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2013 by Peter Wendrich ([email protected])
-- http://www.syntiac.com/chameleon.html
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
--
-- Read data from SPI boot flash
-- The Chaco tool can upload additional binary data (.bin file) after
-- the actual FPGA core (.rbf file). This entity can be used to read
-- this extra data from the flash. For this it needs the "slot" where
-- the core is started. This is obtained from the USB microcontroller
-- (use the chameleon_usb).
-- Additionally a flash_offset and amount can be given to only
-- read selected parts of the data.
--
-- On a start trigger pulse it will read the first 3 bytes in the given
-- slot to obtain the location of the data. Then it adds the flash_offset
-- to that value and reads "amount" of data. The data is given on the "q"
-- output together with a address count on "a". The start value of the
-- "a" address can be set with the input on "start_addr".
--
-- Make sure that the start trigger is given after the chameleon_usb entity
-- has had time to read the slot number. There is a valid signal output
-- on that entity to check this. Otherwise it will still read data, but
-- from the wrong slot.
--
-- -----------------------------------------------------------------------
-- clk - system clock
-- slot - slot number to use for reading data from the flash
-- start - trigger to start reading the data. "slot" must be valid
-- start_addr - start value of "a"
-- flash_offset - additional offset within the data
-- amount - amount of bytes to read from flash
-- busy - Becomes high one clock after start is given.
-- Stays high as long as reads are pending.
-- Can be used to halt or reset a soft CPU while it is
-- waiting for data from flash.
-- cs_n - Chipselect for the flash. There is a 256 cycle delay
-- after a change of this signal to give the mux-multiplexer
-- time to transfer the signal and the flash time to initialize.
-- spi_req - Toggles to request a SPI transfer of 8 bits.
-- spi_ack - Acknowlege on the spi_req (should toggle when request is complete)
-- spi_d - Byte to send over SPI bus
-- spi_q - Byte received from SPI bus
-- req - Toggles to request a byte write into memory
-- ack - Acknowledge for req. It should toggle to current req's value when write is complete.
-- a - Address counter to write consecutive bytes to memory
-- q - Current byte to write to memory.
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
-- -----------------------------------------------------------------------
entity chameleon_spi_flash is
generic (
a_bits : integer := 25
);
port (
clk : in std_logic;
slot : in unsigned(3 downto 0);
start : in std_logic;
start_addr : in unsigned((a_bits-1) downto 0);
flash_offset : in unsigned(23 downto 0);
amount : in unsigned(23 downto 0);
busy : out std_logic;
cs_n : out std_logic;
spi_req : out std_logic;
spi_ack : in std_logic;
spi_d : out unsigned(7 downto 0);
spi_q : in unsigned(7 downto 0);
req : out std_logic;
ack : in std_logic;
a : out unsigned((a_bits-1) downto 0);
q : out unsigned(7 downto 0)
);
end entity;
-- -----------------------------------------------------------------------
architecture rtl of chameleon_spi_flash is
type state_t is (STATE_IDLE,
STATE_CS, STATE_CMD, STATE_AH, STATE_AM, STATE_AL, STATE_DUMMY,
STATE_OFFSH, STATE_OFFSM, STATE_OFFSL, STATE_END, STATE_DATA, STATE_INC);
signal state : state_t := STATE_IDLE;
signal header : std_logic := '1'; -- 1=reading header, 0=reading data
signal timer : unsigned(7 downto 0) := (others => '0');
signal flash_a : unsigned(23 downto 0);
signal cs_n_reg : std_logic := '1';
signal spi_req_reg : std_logic := '0';
signal req_reg : std_logic := '0';
signal a_reg : unsigned(a'range);
signal amount_cnt : unsigned(amount'range);
begin
busy <= '0' when state = STATE_IDLE else '1';
cs_n <= cs_n_reg;
spi_req <= spi_req_reg;
req <= req_reg;
a <= a_reg;
q <= spi_q;
process(clk)
begin
if rising_edge(clk) then
if (timer = 0) and (spi_req_reg = spi_ack) and (req_reg = ack) then
case state is
when STATE_IDLE =>
cs_n_reg <= '1';
when STATE_CS =>
cs_n_reg <= '0';
timer <= (others => '1');
state <= STATE_CMD;
when STATE_CMD =>
spi_d <= X"03"; -- Read command
spi_req_reg <= not spi_req_reg;
state <= STATE_AH;
when STATE_AH =>
spi_d <= flash_a(23 downto 16);
spi_req_reg <= not spi_req_reg;
state <= STATE_AM;
when STATE_AM =>
spi_d <= flash_a(15 downto 8);
spi_req_reg <= not spi_req_reg;
state <= STATE_AL;
when STATE_AL =>
spi_d <= flash_a(7 downto 0);
spi_req_reg <= not spi_req_reg;
state <= STATE_DUMMY;
when STATE_DUMMY =>
-- Dummy access to get first byte out of the flash
spi_d <= (others => '1');
spi_req_reg <= not spi_req_reg;
if header = '0' then
state <= STATE_DATA;
else
-- Read the offset of the data in the slot from the flash
state <= STATE_OFFSH;
end if;
when STATE_OFFSH =>
spi_d <= (others => '1');
spi_req_reg <= not spi_req_reg;
flash_a(19 downto 16) <= spi_q(3 downto 0);
state <= STATE_OFFSM;
when STATE_OFFSM =>
spi_d <= (others => '1');
spi_req_reg <= not spi_req_reg;
flash_a(15 downto 8) <= spi_q;
state <= STATE_OFFSL;
when STATE_OFFSL =>
flash_a(7 downto 0) <= spi_q;
state <= STATE_END;
when STATE_END =>
flash_a <= flash_a + flash_offset;
cs_n_reg <= '1';
timer <= (others => '1');
header <= '0';
state <= STATE_CS;
when STATE_DATA =>
state <= STATE_IDLE;
if amount_cnt /= 0 then
req_reg <= not req_reg;
amount_cnt <= amount_cnt - 1;
state <= STATE_INC;
end if;
when STATE_INC =>
spi_d <= (others => '1');
spi_req_reg <= not spi_req_reg;
a_reg <= a_reg + 1;
state <= STATE_DATA;
end case;
else
timer <= timer - 1;
end if;
if start = '1' then
header <= '1';
flash_a <= slot & X"00000";
a_reg <= start_addr;
amount_cnt <= amount;
state <= STATE_CS;
end if;
end if;
end process;
end architecture;
| lgpl-2.1 | aaf2339bb19bbd5f6b1b7eddea800e76 | 0.582229 | 3.456755 | false | false | false | false |
GLADICOS/SPACEWIRESYSTEMC | rtl/RTL_SL/spwrecvfront_fast.vhd | 2 | 15,262 | --
-- Front-end for SpaceWire Receiver
--
-- This entity samples the input signals DataIn and StrobeIn to detect
-- valid bit transitions. Received bits are handed to the application
-- in groups of "rxchunk" bits at a time, synchronous to the system clock.
--
-- This receiver is based on synchronous oversampling of the input signals.
-- Inputs are sampled on the rising and falling edges of an externally
-- supplied sample clock "rxclk". Therefore the maximum bitrate of the
-- incoming signal must be significantly lower than two times the "rxclk"
-- clock frequency. The maximum incoming bitrate must also be strictly
-- lower than rxchunk times the system clock frequency.
--
-- This code is tuned for implementation on Xilinx Spartan-3.
--
-- Details
-- -------
--
-- Stage A: The inputs "spw_di" and "spw_si" are handled as DDR signals,
-- synchronously sampled on both edges of "rxclk".
--
-- Stage B: The input signals are re-registered on the rising edge of "rxclk"
-- for further processing. This implies that every rising edge of "rxclk"
-- produces two new samples of "spw_di" and two new samples of "spw_si".
--
-- Stage C: Transitions in input signals are detected by comparing the XOR
-- of data and strobe to the XOR of the previous data and strobe samples.
-- If there is a difference, we know that either data or strobe has changed
-- and the new value of data is a valid new bit. Every rising edge of "rxclk"
-- thus produces either zero, or one or two new data bits.
--
-- Stage D: Received bits are collected in groups of "rxchunk" bits
-- (unless rxchunk=1, in which case groups of 2 bits are used). Complete
-- groups are pushed into an 8-deep cyclic buffer. A 3-bit counter "headptr"
-- indicates the current position in the cyclic buffer.
--
-- The system clock domain reads bit groups from the cyclic buffer. A tail
-- pointer indicates the next location to read from the buffer. A comparison
-- between the "tailptr" and a re-synchronized copy of the "headptr" determines
-- whether valid bits are available in the buffer.
--
-- Activity detection is based on a 3-bit counter "bitcnt". This counter is
-- incremented whenever the rxclk domain receives 1 or 2 new bits. The system
-- clock domain monitors a re-synchronized copy of the activity counter to
-- determine whether it has been updated since the previous system clock cycle.
--
-- Implementation guidelines
-- -------------------------
--
-- IOB flip-flops must be used to sample spw_di and spw_si.
-- Clock skew between the IOBs for spw_di and spw_si must be minimized.
--
-- "rxclk" must be at least as fast as the system clock;
-- "rxclk" does not need to be phase-related to the system clock;
-- it is allowed for "rxclk" to be equal to the system clock.
--
-- The following timing constraints are needed:
-- * PERIOD constraint on the system clock;
-- * PERIOD constraint on "rxclk";
-- * FROM-TO constraint from "rxclk" to system clock, equal to one "rxclk" period;
-- * FROM-TO constraint from system clock to "rxclk", equal to one "rxclk" period.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.spwpkg.all;
entity spwrecvfront_fast is
generic (
-- Number of bits to pass to the application per system clock.
rxchunk: integer range 1 to 4 );
port (
-- System clock.
clk: in std_logic;
-- Sample clock.
rxclk: in std_logic;
-- High to enable receiver; low to disable and reset receiver.
rxen: in std_logic;
-- High if there has been recent activity on the input lines.
inact: out std_logic;
-- High if inbits contains a valid group of received bits.
-- If inbvalid='1', the application must sample inbits on
-- the rising edge of clk.
inbvalid: out std_logic;
-- Received bits (bit 0 is the earliest received bit).
inbits: out std_logic_vector(rxchunk-1 downto 0);
-- Data In signal from SpaceWire bus.
spw_di: in std_logic;
-- Strobe In signal from SpaceWire bus.
spw_si: in std_logic );
-- Turn off FSM extraction.
-- Without this, XST will happily apply one-hot encoding to rrx.headptr.
attribute FSM_EXTRACT: string;
attribute FSM_EXTRACT of spwrecvfront_fast: entity is "NO";
end entity spwrecvfront_fast;
architecture spwrecvfront_arch of spwrecvfront_fast is
-- width of bit groups in cyclic buffer;
-- typically equal to rxchunk, except when rxchunk = 1
type memwidth_array_type is array(1 to 4) of integer;
constant chunk_to_memwidth: memwidth_array_type := ( 2, 2, 3, 4 );
constant memwidth: integer := chunk_to_memwidth(rxchunk);
-- registers in rxclk domain
type rxregs_type is record
-- stage B: re-register input samples
b_di0: std_ulogic;
b_si0: std_ulogic;
b_di1: std_ulogic;
b_si1: std_ulogic;
-- stage C: data/strobe decoding
c_bit: std_logic_vector(1 downto 0);
c_val: std_logic_vector(1 downto 0);
c_xor1: std_ulogic;
-- stage D: collect groups of memwidth bits
d_shift: std_logic_vector(memwidth-1 downto 0);
d_count: std_logic_vector(memwidth-1 downto 0);
-- cyclic buffer access
bufdata: std_logic_vector(memwidth-1 downto 0);
bufwrite: std_ulogic;
headptr: std_logic_vector(2 downto 0);
-- activity detection
bitcnt: std_logic_vector(2 downto 0);
end record;
-- registers in system clock domain
type regs_type is record
-- data path from buffer to output
tailptr: std_logic_vector(2 downto 0);
inbvalid: std_ulogic;
-- split 2-bit groups if rxchunk=1
splitbit: std_ulogic;
splitinx: std_ulogic;
splitvalid: std_ulogic;
-- activity detection
bitcntp: std_logic_vector(2 downto 0);
inact: std_ulogic;
-- reset signal towards rxclk domain
rxdis: std_ulogic;
end record;
constant regs_reset: regs_type := (
tailptr => "000",
inbvalid => '0',
splitbit => '0',
splitinx => '0',
splitvalid => '0',
bitcntp => "000",
inact => '0',
rxdis => '1' );
-- Signals that are re-synchronized from rxclk to system clock domain.
type syncsys_type is record
headptr: std_logic_vector(2 downto 0); -- pointer in cyclic buffer
bitcnt: std_logic_vector(2 downto 0); -- activity detection
end record;
-- Registers.
signal r: regs_type := regs_reset;
signal rin: regs_type;
signal rrx, rrxin: rxregs_type;
-- Synchronized signals after crossing clock domains.
signal syncrx_rstn: std_logic;
signal syncsys: syncsys_type;
-- Output data from cyclic buffer.
signal s_bufdout: std_logic_vector(memwidth-1 downto 0);
-- stage A: input flip-flops for rising/falling rxclk
signal s_a_di0: std_logic;
signal s_a_si0: std_logic;
signal s_a_di1: std_logic;
signal s_a_si1: std_logic;
signal s_a_di2: std_logic;
signal s_a_si2: std_logic;
-- force use of IOB flip-flops
attribute IOB: string;
attribute IOB of s_a_di1: signal is "TRUE";
attribute IOB of s_a_si1: signal is "TRUE";
attribute IOB of s_a_di2: signal is "TRUE";
attribute IOB of s_a_si2: signal is "TRUE";
begin
-- Cyclic data buffer.
bufmem: spwram
generic map (
abits => 3,
dbits => memwidth )
port map (
rclk => clk,
wclk => rxclk,
ren => '1',
raddr => r.tailptr,
rdata => s_bufdout,
wen => rrx.bufwrite,
waddr => rrx.headptr,
wdata => rrx.bufdata );
-- Synchronize reset signal for rxclk domain.
syncrx_reset: syncdff
port map ( clk => rxclk, rst => r.rxdis, di => '1', do => syncrx_rstn );
-- Synchronize signals from rxclk domain to system clock domain.
syncsys_headptr0: syncdff
port map ( clk => clk, rst => r.rxdis, di => rrx.headptr(0), do => syncsys.headptr(0) );
syncsys_headptr1: syncdff
port map ( clk => clk, rst => r.rxdis, di => rrx.headptr(1), do => syncsys.headptr(1) );
syncsys_headptr2: syncdff
port map ( clk => clk, rst => r.rxdis, di => rrx.headptr(2), do => syncsys.headptr(2) );
syncsys_bitcnt0: syncdff
port map ( clk => clk, rst => r.rxdis, di => rrx.bitcnt(0), do => syncsys.bitcnt(0) );
syncsys_bitcnt1: syncdff
port map ( clk => clk, rst => r.rxdis, di => rrx.bitcnt(1), do => syncsys.bitcnt(1) );
syncsys_bitcnt2: syncdff
port map ( clk => clk, rst => r.rxdis, di => rrx.bitcnt(2), do => syncsys.bitcnt(2) );
-- sample inputs on rising edge of rxclk
process (rxclk) is
begin
if rising_edge(rxclk) then
s_a_di1 <= spw_di;
s_a_si1 <= spw_si;
end if;
end process;
-- sample inputs on falling edge of rxclk
process (rxclk) is
begin
if falling_edge(rxclk) then
s_a_di2 <= spw_di;
s_a_si2 <= spw_si;
-- reregister inputs in fabric flip-flops
s_a_di0 <= s_a_di2;
s_a_si0 <= s_a_si2;
end if;
end process;
-- combinatorial process
process (r, rrx, rxen, syncrx_rstn, syncsys, s_bufdout, s_a_di0, s_a_si0, s_a_di1, s_a_si1)
variable v: regs_type;
variable vrx: rxregs_type;
begin
v := r;
vrx := rrx;
-- ---- SAMPLE CLOCK DOMAIN ----
-- stage B: re-register input samples
vrx.b_di0 := s_a_di0;
vrx.b_si0 := s_a_si0;
vrx.b_di1 := s_a_di1;
vrx.b_si1 := s_a_si1;
-- stage C: decode data/strobe and detect valid bits
if (rrx.b_di0 xor rrx.b_si0 xor rrx.c_xor1) = '1' then
vrx.c_bit(0) := rrx.b_di0;
else
vrx.c_bit(0) := rrx.b_di1;
end if;
vrx.c_bit(1) := rrx.b_di1;
vrx.c_val(0) := (rrx.b_di0 xor rrx.b_si0 xor rrx.c_xor1) or
(rrx.b_di0 xor rrx.b_si0 xor rrx.b_di1 xor rrx.b_si1);
vrx.c_val(1) := (rrx.b_di0 xor rrx.b_si0 xor rrx.c_xor1) and
(rrx.b_di0 xor rrx.b_si0 xor rrx.b_di1 xor rrx.b_si1);
vrx.c_xor1 := rrx.b_di1 xor rrx.b_si1;
-- Note:
-- c_val = "00" if no new bits are received
-- c_val = "01" if one new bit is received; the new bit is in c_bit(0)
-- c_val = "11" if two new bits are received
-- stage D: collect groups of memwidth bits
if rrx.c_val(0) = '1' then
-- shift incoming bits into register
if rrx.c_val(1) = '1' then
vrx.d_shift := rrx.c_bit & rrx.d_shift(memwidth-1 downto 2);
else
vrx.d_shift := rrx.c_bit(0) & rrx.d_shift(memwidth-1 downto 1);
end if;
-- prepare to store a group of memwidth bits
if rrx.d_count(0) = '1' then
-- only one more bit needed
vrx.bufdata := rrx.c_bit(0) & rrx.d_shift(memwidth-1 downto 1);
else
vrx.bufdata := rrx.c_bit & rrx.d_shift(memwidth-1 downto 2);
end if;
-- countdown nr of needed bits (one-hot counter)
if rrx.c_val(1) = '1' then
vrx.d_count := rrx.d_count(1 downto 0) & rrx.d_count(memwidth-1 downto 2);
else
vrx.d_count := rrx.d_count(0 downto 0) & rrx.d_count(memwidth-1 downto 1);
end if;
end if;
-- stage D: store groups of memwidth bits
vrx.bufwrite := rrx.c_val(0) and (rrx.d_count(0) or (rrx.c_val(1) and rrx.d_count(1)));
-- Increment head pointer.
if rrx.bufwrite = '1' then
vrx.headptr := std_logic_vector(unsigned(rrx.headptr) + 1);
end if;
-- Activity detection.
if rrx.c_val(0) = '1' then
vrx.bitcnt := std_logic_vector(unsigned(rrx.bitcnt) + 1);
end if;
-- Synchronous reset of rxclk domain.
if syncrx_rstn = '0' then
vrx.c_val := "00";
vrx.c_xor1 := '0';
vrx.d_count := (others => '0');
vrx.d_count(memwidth-1) := '1';
vrx.bufwrite := '0';
vrx.headptr := "000";
vrx.bitcnt := "000";
end if;
-- ---- SYSTEM CLOCK DOMAIN ----
-- Compare tailptr to headptr to decide whether there is new data.
-- If the values are equal, we are about to read a location which has
-- not yet been written by the rxclk domain.
if r.tailptr = syncsys.headptr then
-- No more data in cyclic buffer.
v.inbvalid := '0';
else
-- Reading valid data from cyclic buffer.
v.inbvalid := '1';
-- Increment tail pointer.
if rxchunk /= 1 then
v.tailptr := std_logic_vector(unsigned(r.tailptr) + 1);
end if;
end if;
-- If rxchunk=1, split 2-bit groups into separate bits.
if rxchunk = 1 then
-- Select one of the two bits.
if r.splitinx = '0' then
v.splitbit := s_bufdout(0);
else
v.splitbit := s_bufdout(1);
end if;
-- Indicate valid bit.
v.splitvalid := r.inbvalid;
-- Increment tail pointer.
if r.inbvalid = '1' then
v.splitinx := not r.splitinx;
if r.splitinx = '0' then
v.tailptr := std_logic_vector(unsigned(r.tailptr) + 1);
end if;
end if;
end if;
-- Activity detection.
v.bitcntp := syncsys.bitcnt;
if r.bitcntp = syncsys.bitcnt then
v.inact := '0';
else
v.inact := '1';
end if;
-- Synchronous reset of system clock domain.
if rxen = '0' then
v := regs_reset;
end if;
-- Register rxen to ensure glitch-free signal to rxclk domain
v.rxdis := not rxen;
-- drive outputs
inact <= r.inact;
if rxchunk = 1 then
inbvalid <= r.splitvalid;
inbits(0) <= r.splitbit;
else
inbvalid <= r.inbvalid;
inbits <= s_bufdout;
end if;
-- update registers
rrxin <= vrx;
rin <= v;
end process;
-- update registers on rising edge of rxclk
process (rxclk) is
begin
if rising_edge(rxclk) then
rrx <= rrxin;
end if;
end process;
-- update registers on rising edge of system clock
process (clk) is
begin
if rising_edge(clk) then
r <= rin;
end if;
end process;
end architecture spwrecvfront_arch;
| gpl-3.0 | 075312bfdb20630ac02aea36104e2fb1 | 0.56965 | 3.585154 | false | false | false | false |
yishinli/emc2 | src/hal/drivers/mesa-hostmot2/firmware/src/uartr.vhd | 1 | 11,105 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
-- http://www.mesanet.com
--
-- This program is is licensed under a disjunctive dual license giving you
-- the choice of one of the two following sets of free software/open source
-- licensing terms:
--
-- * GNU General Public License (GPL), version 2.0 or later
-- * 3-clause BSD License
--
--
-- The GNU GPL License:
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- The 3-clause BSD License:
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- * Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- * Neither the name of Mesa Electronics nor the names of its
-- contributors may be used to endorse or promote products
-- derived from this software without specific prior written
-- permission.
--
--
-- Disclaimer:
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Simple UART with 32 bit bus interface
-- 16 byte deep receive FIFO
-- Can read 4,3,2,1 bytes from FIFO depending on data register read offset
-- Base Address = 1 byte
-- Base Address +1 = 2 bytes
-- Base Address +2 = 3 bytes
-- Base Address +3 = 4 bytes
entity uartr is
port (
clk : in std_logic;
ibus : in std_logic_vector(31 downto 0);
obus : out std_logic_vector(31 downto 0);
addr : in std_logic_vector(1 downto 0);
popfifo : in std_logic;
loadbitrate : in std_logic;
readbitrate : in std_logic;
clrfifo : in std_logic;
readfifocount : in std_logic;
loadmode : in std_logic;
readmode : in std_logic;
fifohasdata : out std_logic;
rxmask : in std_logic;
rxdata : in std_logic
);
end uartr;
architecture Behavioral of uartr is
-- FIFO related signals
signal pushdata: std_logic_vector(7 downto 0);
signal popadd0: std_logic_vector(3 downto 0) := x"f";
signal popadd1: std_logic_vector(3 downto 0) := x"f";
signal popadd2: std_logic_vector(3 downto 0) := x"f";
signal popadd3: std_logic_vector(3 downto 0) := x"f";
signal popdata: std_logic_vector(31 downto 0);
signal datacounter: std_logic_vector(4 downto 0);
signal push: std_logic;
signal pop: std_logic;
signal popsize: std_logic_vector(2 downto 0);
signal clear: std_logic;
signal lfifoempty: std_logic;
signal lfifohasdata: std_logic;
-- uart interface related signals
constant DDSWidth : integer := 16;
signal BitrateDDSReg : std_logic_vector(DDSWidth-1 downto 0);
signal BitrateDDSAccum : std_logic_vector(DDSWidth-1 downto 0);
alias DDSMSB : std_logic is BitrateDDSAccum(15);
signal OldDDSMSB: std_logic;
signal SampleTime: std_logic;
signal BitCount : std_logic_vector(3 downto 0);
signal BytePointer : std_logic_vector(2 downto 0) := "000";
signal SReg: std_logic_vector(9 downto 0);
alias SregData: std_logic_vector(7 downto 0)is SReg(8 downto 1);
alias StartBit: std_logic is Sreg(0);
alias StopBit: std_logic is Sreg(9);
signal RXPipe : std_logic_vector(1 downto 0);
signal Go: std_logic;
signal DAV: std_logic;
signal ModeReg: std_logic_vector(5 downto 0);
alias FalseStart: std_logic is ModeReg(0);
alias OverRun: std_logic is ModeReg(1);
alias RXMaskEn: std_logic is ModeReg(3);
alias FIFOError: std_logic is ModeReg(4);
alias LostData: std_logic is ModeReg(5);
component SRL16E
--
generic (INIT : bit_vector);
--
port (D : in std_logic;
CE : in std_logic;
CLK : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component;
begin
fifosrl0: for i in 0 to 7 generate
asr16e: SRL16E generic map (x"0000") port map(
D => pushdata(i),
CE => push,
CLK => clk,
A0 => popadd0(0),
A1 => popadd0(1),
A2 => popadd0(2),
A3 => popadd0(3),
Q => popdata(i)
);
end generate;
fifosrl1: for i in 0 to 7 generate
asr16e: SRL16E generic map (x"0000") port map(
D => pushdata(i),
CE => push,
CLK => clk,
A0 => popadd1(0),
A1 => popadd1(1),
A2 => popadd1(2),
A3 => popadd1(3),
Q => popdata(8+i)
);
end generate;
fifosrl2: for i in 0 to 7 generate
asr16e: SRL16E generic map (x"0000") port map(
D => pushdata(i),
CE => push,
CLK => clk,
A0 => popadd2(0),
A1 => popadd2(1),
A2 => popadd2(2),
A3 => popadd2(3),
Q => popdata(16+i)
);
end generate;
fifosrl3: for i in 0 to 7 generate
asr16e: SRL16E generic map (x"0000") port map(
D => pushdata(i),
CE => push,
CLK => clk,
A0 => popadd3(0),
A1 => popadd3(1),
A2 => popadd3(2),
A3 => popadd3(3),
Q => popdata(24+i)
);
end generate;
afifo: process (clk,popdata,datacounter)
begin
if rising_edge(clk) then
if push = '1' and pop = '0' then
if datacounter /= 16 then -- a push
-- always increment the data counter if not full
datacounter <= datacounter +1;
popadd0 <= popadd0 +1; -- popadd must follow data down shiftreg
else
LostData <= '1';
end if;
end if;
if (pop = '1') and (push = '0') then -- a pop
if datacounter >= popsize then
datacounter <= datacounter - popsize;
popadd0 <= popadd0 - popsize;
else
FIFOError <= '1';
end if;
end if;
if (pop = '1') and (push = '1') then -- simultaneaous pop and push
if datacounter >= popsize then -- note pushdata was not available
-- when read occured so compare datacounter with popsize
datacounter <= datacounter - (addr);
popadd0 <= popadd0 - (addr);
else -- if pop is not valid, just do push part
datacounter <= datacounter +1;
popadd0 <= popadd0 +1;
FIFOError <= '1';
end if;
end if;
if clear = '1' then -- a clear fifo
popadd0 <= (others => '1');
datacounter <= (others => '0');
LostData <= '0';
FIFOError <= '0';
end if;
end if; -- clk rise
-- The way this mess works is that we have 4 byte wide FIFOs with duplicated data
-- but the readout point is shifted by one byte for each succeeding FIFO so we can read up to
-- 32 bits (4 bytes) at once. Wasteful, but SRL16s are cheap
popadd1 <= popadd0 -1; -- note that these are not forced to 0 on underflow
popadd2 <= popadd0 -2; -- so unused bytes of a less than 4 byte read
popadd3 <= popadd0 -3; -- will be stale recv data - not good for security reasons!
-- if this matters, force to 0 on underflow will result in duplicated
-- current data on unused bytes.
popsize <= ('0'&addr) +1;
if datacounter = 0 then
lfifoempty <= '1';
else
lfifoempty <= '0';
end if;
fifohasdata <= not lfifoempty;
end process afifo;
asimpleuartrx: process (clk)
begin
if rising_edge(clk) then
RXPipe <= RXPipe(0) & rxdata; -- Two stage rx data pipeline to compensate for
-- two clock delay from start bit detection to acquire loop startup
if Go = '1' then
BitRateDDSAccum <= BitRateDDSAccum + BitRateDDSReg;
if SampleTime = '1' then
if BitCount = 0 then
Go <= '0';
DAV <= '1';
if RXPipe(1) = '0' then
OverRun <= '1';
end if;
end if;
if BitCount = "1001" then -- false start bit check
if RXPipe(1) = '1' then
Go <= '0';
FalseStart <= '1';
end if;
end if;
SReg <= RXPipe(1) & SReg(9 downto 1); -- right shift = LSb first
BitCount <= BitCount -1;
end if;
else
BitRateDDSAccum <= (others => '0');
BitCount <= "1001";
end if;
if Go = '0' and rxdata = '0' and (rxmask and RXMaskEn) = '0' then -- start bit detection
Go <= '1';
end if;
if DAV = '1' then -- DAV is just one clock wide
DAV <= '0';
end if;
OldDDSMSB <= DDSMSB; -- for Phase accumulator MSB edge detection
if loadbitrate = '1' then
BitRateDDSReg <= ibus(DDSWidth-1 downto 0);
end if;
if loadmode= '1' then
ModeReg(3 downto 0) <= ibus(3 downto 0);
end if;
end if; -- clk
SampleTime <= (not OldDDSMSB) and DDSMSB; -- sample on rising edge of DDS MSB
pushdata <= SRegData;
push <= DAV;
pop <= popfifo;
clear <= clrfifo;
obus <= (others => 'Z');
if readfifocount = '1' then
obus(4 downto 0) <= datacounter;
-- obus(31 downto 5) <= (others => '0');
end if;
if readbitrate = '1' then
obus(DDSWidth-1 downto 0) <= BitRateDDSReg;
end if;
if popfifo = '1' then
obus <= popdata;
end if;
if readmode = '1' then
obus(5 downto 0) <= ModeReg;
obus(6) <= rxmask;
obus(7) <= not lfifoempty;
end if;
fifohasdata <= not lfifoempty;
end process asimpleuartrx;
end Behavioral;
| lgpl-2.1 | 03c39c946e4bf74ea5ef7d7e8ebba951 | 0.613057 | 3.287448 | false | false | false | false |
kdgwill/VHDL_Framer_Example | VHDL_Framer_Example/Example2/Framer.vhd | 1 | 2,445 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY framer is
generic(N : integer := 16);
port(clk : in std_ulogic;
sin : in std_ulogic;
resetb : in std_ulogic;
SOUT : out std_ulogic;
clk_div_8 : out std_ulogic;
decode_F628_out : out std_ulogic);
end framer;
architecture behavior of framer is
signal shiftreg_16 : std_ulogic_vector(15 downto 0);
constant F628 : std_ulogic_vector (15 downto 0) := x"F628";
signal decode_F628 : std_ulogic;
signal parallel_reg : std_ulogic_vector (7 downto 0);
signal parallel_clk : std_ulogic;
signal count_4bit : std_ulogic_vector (3 downto 0);
signal count_4bit_int : natural;
signal bit_counter : integer;
begin
shiftin: process (clk, resetb)
begin
if (resetb = '0') then
SOUT <= '0';
shiftreg_16 <= (others => '0');
elsif rising_edge(CLK) then
shiftreg_16 <= shiftreg_16(14 downto 0) & SIN;
SOUT <= shiftreg_16(N-1);
end if;
end process shiftin;
decode_A1A2: process (shiftreg_16)
begin
if (shiftreg_16 = F628) then
decode_F628 <= '1';
else
decode_F628 <= '0';
end if;
end process;
decode_F628_out <= decode_F628;
par_load: process (clk, resetb)
begin
if (resetb = '0') then
bit_counter <= 0;
elsif rising_edge (clk) then
if (decode_F628 = '1') then
bit_counter <= 0;
elsif (bit_counter = 7)then
bit_counter <= 0;
else
bit_counter <= bit_counter + 1 mod 8;
end if;
end if;
end process;
count_4bit <= std_ulogic_vector(to_unsigned (count_4bit_int,4));
clk_div_8 <= count_4bit(2);
process (clk, resetb)
begin
if (resetb = '0') then
count_4bit_int <= 0;
elsif rising_edge (clk) then
if (decode_F628 = '1') then
count_4bit_int <= 0;
elsif (count_4bit_int = 15) then
count_4bit_int <= 0;
else
count_4bit_int <= count_4bit_int + 1;
end if;
end if;
end process;
process (clk, resetb)
begin
if (resetb = '0') then
parallel_reg <= (others => '0');
elsif rising_edge (clk) then
if (decode_F628= '1') then
parallel_reg <= (shiftreg_16 (15 downto 8));
elsif (bit_counter = 7) then
parallel_reg <= (shiftreg_16 (15 downto 8));
end if;
end if;
end process;
end behavior;
| gpl-3.0 | cf2352c9f7c9d86506cd674903c61c0a | 0.571779 | 3.130602 | false | false | false | false |
yishinli/emc2 | src/hal/drivers/m5i20/hostmot5_src/countere.vhd | 1 | 8,938 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
port (
obus: out STD_LOGIC_VECTOR (31 downto 0);
ibus: in STD_LOGIC_VECTOR (31 downto 0);
quada: in STD_LOGIC;
quadb: in STD_LOGIC;
index: in STD_LOGIC;
ccrloadcmd: in STD_LOGIC;
ccrreadcmd: in STD_LOGIC;
countoutreadcmd: in STD_LOGIC;
countlatchcmd: in STD_LOGIC;
countclearcmd: in STD_LOGIC;
countenable: in STD_LOGIC;
indexmask: in STD_LOGIC;
nads: in STD_LOGIC;
clk: in STD_LOGIC
);
end counter;
architecture behavioral of counter is
signal count: STD_LOGIC_VECTOR (31 downto 0);
signal up: STD_LOGIC;
signal down: STD_LOGIC;
signal countoutlatch: STD_LOGIC_VECTOR (31 downto 0);
signal outlatchdel1: STD_LOGIC;
signal outlatchdel2: STD_LOGIC;
signal quada1: STD_LOGIC;
signal quada2: STD_LOGIC;
signal quadacnt: STD_LOGIC_VECTOR (3 downto 0);
signal quadafilt: STD_LOGIC;
signal quadb1: STD_LOGIC;
signal quadb2: STD_LOGIC;
signal quadbcnt: STD_LOGIC_VECTOR (3 downto 0);
signal quadbfilt: STD_LOGIC;
signal index1: STD_LOGIC;
signal index2: STD_LOGIC;
signal indexcnt: STD_LOGIC_VECTOR (3 downto 0);
signal indexfilt: STD_LOGIC;
signal qcountup: STD_LOGIC;
signal qcountdown: STD_LOGIC;
signal udcountup: STD_LOGIC;
signal udcountdown: STD_LOGIC;
signal autocount: STD_LOGIC;
signal doclear: STD_LOGIC;
signal clearonindex: STD_LOGIC; -- ccr register bits...
signal clearonce: STD_LOGIC;
signal indexgate: STD_LOGIC;
signal indexsrc: STD_LOGIC;
signal latchonread: STD_LOGIC;
signal quadfilter: STD_LOGIC;
signal countermode: STD_LOGIC;
signal indexpol: STD_LOGIC;
signal ccrloadcmd1: STD_LOGIC;
signal ccrloadcmd2: STD_LOGIC;
signal localhold: STD_LOGIC;
signal localclear: STD_LOGIC;
signal indexmaskenable: STD_LOGIC;
signal indexmaskpol: STD_LOGIC;
signal fixedindexmask: STD_LOGIC;
signal latchonce: STD_LOGIC;
signal latchonindex: STD_LOGIC;
signal flimit: STD_LOGIC_VECTOR (3 downto 0);
begin
acounter: process (clk, countoutlatch)
begin
if clk'event and clk = '1' then
outlatchdel1 <= countlatchcmd;
outlatchdel2 <= outlatchdel1;
if indexgate = '0' then
indexsrc <= index;
else
if indexpol = '1' then
indexsrc <= not quada and not quadb and index;
else
indexsrc <= (quada or quadb) and index;
end if;
end if;
if indexmaskpol = '1' then
fixedindexmask <= indexmask;
else
fixedindexmask <= not indexmask;
end if;
if quadfilter = '1' then
flimit <= "1111";
else
flimit <= "0011";
end if;
quada1 <= quadafilt;
quada2 <= quada1;
quadb1 <= quadbfilt;
quadb2 <= quadb1;
index1 <= indexfilt;
index2 <= index1;
-- deadended counter for A input filter --
if (quada = '1') and (quadacnt < flimit) then
quadacnt <= quadacnt + 1;
end if;
if (quada = '0') and (quadacnt /= 0) then
quadacnt <= quadacnt -1;
end if;
if quadacnt >= flimit then
quadafilt<= '1';
end if;
if quadacnt = 0 then
quadafilt<= '0';
end if;
-- deadended counter for B input filter --
if (quadb = '1') and (quadbcnt < flimit ) then
quadbcnt <= quadbcnt + 1;
end if;
if (quadb = '0') and (quadbcnt /= 0) then
quadbcnt <= quadbcnt -1;
end if;
if quadbcnt >= flimit then
quadbfilt<= '1';
end if;
if quadbcnt = 0 then
quadbfilt <= '0';
end if;
-- deadended counter for index input filter --
if (indexsrc = '1') and (indexcnt < flimit ) then
indexcnt <= indexcnt + 1;
end if;
if (indexsrc = '0') and (indexcnt /= 0) then
indexcnt <= indexcnt -1;
end if;
if indexcnt >= flimit then
indexfilt<= '1';
end if;
if indexcnt = 0 then
indexfilt<= '0';
end if;
if (countclearcmd = '1') or (localclear = '1') or
((clearonindex = '1') and (index1 = '1') and (index2 = '0') and (indexpol = '1') and (indexmaskenable = '0')) or -- rising edge of index
((clearonindex = '1') and (index1 = '0') and (index2 = '1') and (indexpol = '0') and (indexmaskenable = '0')) or -- falling edge of index
((clearonindex = '1') and (index1 = '1') and (index2 = '0') and (indexpol = '1') and (indexmaskenable = '1') and (fixedindexmask = '1')) or -- rising edge of index when masked
((clearonindex = '1') and (index1 = '0') and (index2 = '1') and (indexpol = '0') and (indexmaskenable = '1') and (fixedindexmask = '1')) then -- falling edge of index when masked
doclear <= '1';
if clearonce = '1' then
clearonindex <= '0';
end if;
else
doclear <= '0';
end if;
if ((latchonread = '1') and (nads = '0')) or -- (let the synthesizer factor this out...)
((outlatchdel2 = '0') and (outlatchdel1 = '1') and (latchonindex = '0')) or
((latchonindex = '1') and (index1 = '1') and (index2 = '0') and (indexpol = '1') and (indexmaskenable = '0')) or -- rising edge of index
((latchonindex = '1') and (index1 = '0') and (index2 = '1') and (indexpol = '0') and (indexmaskenable = '0')) or -- falling edge of index
((latchonindex = '1') and (index1 = '1') and (index2 = '0') and (indexpol = '1') and (indexmaskenable = '1') and (fixedindexmask = '1')) or -- rising edge of index when masked
((latchonindex = '1') and (index1 = '0') and (index2 = '1') and (indexpol = '0') and (indexmaskenable = '1') and (fixedindexmask = '1')) then -- falling edge of index when masked
countoutlatch <= count;
if latchonce = '1' then
latchonindex <= '0';
end if;
end if;
if countermode = '0' and countenable = '1' and localhold ='0' and doclear = '0' and (
(quada2 = '0' and quada1 = '1' and quadb2 = '0' and quadb1 = '0') or
(quada2 = '0' and quada1 = '0' and quadb2 = '1' and quadb1 = '0') or
(quada2 = '1' and quada1 = '1' and quadb2 = '0' and quadb1 = '1') or
(quada2 = '1' and quada1 = '0' and quadb2 = '1' and quadb1 = '1')) then
qcountup <= '1';
else
qcountup <= '0';
end if;
if (countermode = '1' and countenable = '1' and localhold ='0' and doclear = '0' and
quadb2 = '1' and quada2 = '0' and quada1 = '1') then
udcountup <= '1';
else
udcountup <= '0';
end if;
if countermode = '0' and countenable = '1' and localhold ='0' and doclear = '0' and (
(quada2 = '0' and quada1 = '0' and quadb2 = '0' and quadb1 = '1') or
(quada2 = '0' and quada1 = '1' and quadb2 = '1' and quadb1 = '1') or
(quada2 = '1' and quada1 = '0' and quadb2 = '0' and quadb1 = '0') or
(quada2 = '1' and quada1 = '1' and quadb2 = '1' and quadb1 = '0')) then
qcountdown <= '1';
else
qcountdown <= '0';
end if;
if (countermode = '1' and countenable = '1' and localhold ='0' and doclear = '0' and
quadb2 = '0' and quada2 = '0' and quada1 = '1') then
udcountdown <= '1';
else
udcountdown <= '0';
end if;
if up /= down then
if up = '1' then
count <= count + 1;
else
count <= count - 1;
end if;
end if;
if doclear = '1' then
count <= x"00000000";
end if;
if ccrloadcmd = '1' then -- load ccr
indexmaskpol <= ibus(15);
indexmaskenable <= ibus(14);
latchonce <= ibus(13);
latchonindex <= ibus(12);
autocount <= ibus(11);
countermode <= ibus(10);
quadfilter <= ibus(9);
localhold <= ibus(8);
indexgate <= ibus(7);
clearonce <= ibus(6);
clearonindex <= ibus(5);
indexpol <= ibus(4);
latchonread <= ibus(3);
localclear <= ibus(2);
end if;
if localclear = '1' then -- once were done clearing,, dont stick around
localclear <= '0';
end if;
end if; --(clock edge)
if (qcountup = '1' or udcountup = '1' or Autocount = '1') and localhold= '0' and doclear = '0' then
up <= '1';
else
up <= '0';
end if;
if (qcountdown = '1' or udcountdown = '1' ) and Autocount = '0' and localhold ='0' and doclear = '0' then
down <= '1';
else
down <= '0';
end if;
obus <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
if (countoutreadcmd = '1') and (ccrreadcmd = '0') then
obus <= countoutlatch;
end if;
if (ccrreadcmd = '1') and (countoutreadcmd = '0') then
obus(15) <= indexmaskpol;
obus(14) <= indexmask;
obus(13) <= latchonce;
obus(12) <= latchonindex;
obus(11) <= autocount;
obus(10) <= countermode;
obus(9) <= quadfilter;
obus(8) <= localhold;
obus(7) <= indexgate;
obus(6) <= clearonce;
obus(5) <= clearonindex;
obus(4) <= indexpol;
obus(3) <= latchonread;
obus(2) <= index1;
obus(1) <= quadb1;
obus(0) <= quada1;
end if;
end process;
end behavioral;
| lgpl-2.1 | 97ad1c8a4677fa62522019229f812e24 | 0.587827 | 2.798372 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-xilinx-ml605/leon3mp.vhd | 1 | 36,776 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2006 - 2015 Cobham Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.i2c.all;
use gaisler.net.all;
use gaisler.jtag.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
use work.ml605.all;
use work.pcie.all;
-- pragma translate_off
use gaisler.sim.all;
-- pragma translate_on
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
SIM_BYPASS_INIT_CAL : string := "OFF"
);
port (
reset : in std_ulogic;
errorn : out std_ulogic;
clk_ref_p : in std_logic;
clk_ref_n : in std_logic;
-- PROM interface
address : out std_logic_vector(23 downto 0);
data : inout std_logic_vector(15 downto 0);
romsn : out std_ulogic;
oen : out std_ulogic;
writen : out std_ulogic;
alatch : out std_ulogic;
-- DDR3 memory
ddr3_dq : inout std_logic_vector(DQ_WIDTH-1 downto 0);
ddr3_dm : out std_logic_vector(DM_WIDTH-1 downto 0);
ddr3_addr : out std_logic_vector(ROW_WIDTH-1 downto 0);
ddr3_ba : out std_logic_vector(BANK_WIDTH-1 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_cs_n : out std_logic_vector((CS_WIDTH*nCS_PER_RANK)-1 downto 0);
ddr3_odt : out std_logic_vector((CS_WIDTH*nCS_PER_RANK)-1 downto 0);
ddr3_cke : out std_logic_vector(CKE_WIDTH-1 downto 0);
ddr3_dqs_p : inout std_logic_vector(DQS_WIDTH-1 downto 0);
ddr3_dqs_n : inout std_logic_vector(DQS_WIDTH-1 downto 0);
ddr3_ck_p : out std_logic_vector(CK_WIDTH-1 downto 0);
ddr3_ck_n : out std_logic_vector(CK_WIDTH-1 downto 0);
-- Debug support unit
dsubre : in std_ulogic; -- Debug Unit break (connect to button)
-- AHB Uart
dsurx : in std_ulogic;
dsutx : out std_ulogic;
-- Ethernet signals
gmiiclk_p : in std_ulogic;
gmiiclk_n : in std_ulogic;
egtx_clk : out std_ulogic;
etx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(7 downto 0);
erx_dv : in std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
emdint : in std_ulogic;
etxd : out std_logic_vector(7 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
emdc : out std_ulogic;
emdio : inout std_logic;
erstn : out std_ulogic;
iic_scl_main : inout std_ulogic;
iic_sda_main : inout std_ulogic;
dvi_iic_scl : inout std_logic;
dvi_iic_sda : inout std_logic;
tft_lcd_data : out std_logic_vector(11 downto 0);
tft_lcd_clk_p : out std_ulogic;
tft_lcd_clk_n : out std_ulogic;
tft_lcd_hsync : out std_ulogic;
tft_lcd_vsync : out std_ulogic;
tft_lcd_de : out std_ulogic;
tft_lcd_reset_b : out std_ulogic;
clk_33 : in std_ulogic; -- SYSACE clock
sysace_mpa : out std_logic_vector(6 downto 0);
sysace_mpce : out std_ulogic;
sysace_mpirq : in std_ulogic;
sysace_mpoe : out std_ulogic;
sysace_mpwe : out std_ulogic;
sysace_d : inout std_logic_vector(7 downto 0);
pci_exp_txp : out std_logic_vector(CFG_NO_OF_LANES-1 downto 0);
pci_exp_txn : out std_logic_vector(CFG_NO_OF_LANES-1 downto 0);
pci_exp_rxp : in std_logic_vector(CFG_NO_OF_LANES-1 downto 0);
pci_exp_rxn : in std_logic_vector(CFG_NO_OF_LANES-1 downto 0);
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_reset_n : in std_logic;
-- Output signals to LEDs
led : out std_logic_vector(6 downto 0)
);
end;
architecture rtl of leon3mp is
signal vcc : std_logic;
signal gnd : std_logic;
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal fpi : grfpu_in_vector_type;
signal fpo : grfpu_out_vector_type;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal gpti : gptimer_in_type;
signal lclk, clk_ddr, lclk200 : std_ulogic;
signal clkm, rstn : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal tck, tms, tdi, tdo : std_ulogic;
signal rstraw : std_logic;
signal lock : std_logic;
signal tb_rst : std_logic;
signal tb_clk : std_logic;
signal phy_init_done : std_logic;
signal lerrorn : std_logic;
-- RS232 APB Uart
signal rxd1 : std_logic;
signal txd1 : std_logic;
-- VGA
signal vgao : apbvga_out_type;
signal lcd_datal : std_logic_vector(11 downto 0);
signal lcd_hsyncl, lcd_vsyncl, lcd_del, lcd_reset_bl : std_ulogic;
signal clk_sel : std_logic_vector(1 downto 0);
signal clk100 : std_ulogic;
signal clkvga, clkvga_p, clkvga_n : std_ulogic;
-- IIC
signal i2ci, dvi_i2ci : i2c_in_type;
signal i2co, dvi_i2co : i2c_out_type;
-- SYSACE
signal clkace : std_ulogic;
signal acei : gracectrl_in_type;
signal aceo : gracectrl_out_type;
-- Used for connecting input/output signals to the DDR3 controller
signal migi : mig_app_in_type;
signal migo : mig_app_out_type;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of lock : signal is true;
attribute syn_keep of clk_ddr : signal is true;
attribute syn_keep of clkm : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute syn_preserve of clk_ddr : signal is true;
attribute keep of lock : signal is true;
attribute keep of clkm : signal is true;
attribute keep of clk_ddr : signal is true;
constant BOARD_FREQ : integer := 100000; -- Board frequency in KHz
constant VCO_FREQ : integer := 1200000; -- MMCM VCO frequency in KHz
constant CPU_FREQ : integer := VCO_FREQ / CFG_MIG_CLK4; -- cpu frequency in KHz
constant I2C_FILTER : integer := (CPU_FREQ*5+50000)/100000+1;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1';
gnd <= '0';
alatch <= '0';
erstn <= rstn;
-- Glitch free reset that can be used for the Eth Phy and flash memory
rst0 : rstgen generic map (acthigh => 1)
port map (reset, clkm, lock, rstn, rstraw);
clkgennomig : if CFG_MIG_DDR2 = 0 generate
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
clkpad : inpad_ds
generic map (tech => CFG_PADTECH, level => lvds, voltage => x25v)
port map(clk_ref_p, clk_ref_n, lclk200);
clkgen0 : clkgen -- clock generator
generic map (CFG_CLKTECH, CFG_CLKMUL, CFG_CLKDIV, 0,
0, 0, CFG_PCIDLL, CFG_PCISYSCLK, BOARD_FREQ)
port map (lclk200, gnd, clkm, open, open, open, open, cgi, cgo);
-- FIXME:
clk100 <= '0';
end generate;
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE+CFG_PCIEXP,
nahbs => 9, devid => XILINX_ML605)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
-- LEON3 processor
nosh : if CFG_GRFPUSH = 0 generate
cpu : for i in 0 to CFG_NCPU-1 generate
l3ft : if CFG_LEON3FT_EN /= 0 generate
leon3ft0 : leon3ft -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ,
CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE,
CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clkm);
end generate;
l3s : if CFG_LEON3FT_EN = 0 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
end generate;
end generate;
sh : if CFG_GRFPUSH = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
l3ft : if CFG_LEON3FT_EN /= 0 generate
leon3ft0 : leon3ftsh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ,
CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE,
CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clkm, fpi(i), fpo(i));
end generate;
l3s : if CFG_LEON3FT_EN = 0 generate
u0 : leon3sh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), fpi(i), fpo(i));
end generate;
end generate;
grfpush0 : grfpushwx generic map ((CFG_FPU-1), CFG_NCPU, fabtech)
port map (clkm, rstn, fpi, fpo);
end generate;
lerrorn <= dbgo(0).error and rstn;
error_pad : odpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (errorn, lerrorn);
dsugen : if CFG_DSU = 1 generate
-- LEON3 Debug Support Unit
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsubre_pad : inpad generic map (level => cmos, voltage => x15v, tech => padtech) port map (dsubre, dsui.break);
dsui.enable <= '1';
led(2) <= dsuo.active;
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
-- Debug UART
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (dsutx, duo.txd);
led(0) <= not dui.rxd;
led(1) <= not duo.txd;
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd);
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 5, pindex => 0, paddr => 0,
ram8 => CFG_MCTRL_RAM8BIT, ram16 => CFG_MCTRL_RAM16BIT, iomask => 0, rammask => 0)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(5), apbi, apbo(0), wpo, open);
end generate;
memi.brdyn <= '1';
memi.bexcn <= '1';
memi.writen <= '1';
memi.wrn <= "1111";
memi.bwidth <= "01";
mg0 : if (CFG_MCTRL_LEON2 = 0) generate
apbo(0) <= apb_none;
ahbso(5) <= ahbs_none;
roms_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (romsn, vcc);
memo.bdrive(0) <= '1';
end generate;
mgpads : if (CFG_MCTRL_LEON2 /= 0) generate
addr_pad : outpadv generic map (level => cmos, voltage => x25v, tech => padtech, width => 24)
port map (address, memo.address(24 downto 1));
roms_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (oen, memo.oen);
wri_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (writen, memo.writen);
end generate;
bdr : iopadvv generic map (level => cmos, voltage => x25v, tech => padtech, width => 16)
port map (data(15 downto 0), memo.data(31 downto 16),
memo.vbdrive(31 downto 16), memi.data(31 downto 16));
----------------------------------------------------------------------
--- DDR3 memory controller ------------------------------------------
----------------------------------------------------------------------
mig_gen : if CFG_MIG_DDR2 = 1 generate
ahb2mig0 : ahb2mig_ml605
generic map ( hindex => 0, haddr => 16#400#, hmask => 16#E00#,
MHz => 400, Mbyte => 512, nosync => boolean'pos(CFG_MIG_CLK4=12)) --CFG_CLKDIV/12)
port map (
rst => rstn, clk_ahb => clkm, clk_ddr => clk_ddr,
ahbsi => ahbsi, ahbso => ahbso(0), migi => migi, migo => migo);
ddr3ctrl : entity work.mig_37
generic map (SIM_BYPASS_INIT_CAL => SIM_BYPASS_INIT_CAL,CLKOUT_DIVIDE4 => work.config.CFG_MIG_CLK4)
port map(
clk_ref_p => clk_ref_p,
clk_ref_n => clk_ref_n,
ddr3_dq => ddr3_dq,
ddr3_addr => ddr3_addr,
ddr3_ba => ddr3_ba,
ddr3_ras_n => ddr3_ras_n,
ddr3_cas_n => ddr3_cas_n,
ddr3_we_n => ddr3_we_n,
ddr3_reset_n => ddr3_reset_n,
ddr3_cs_n => ddr3_cs_n,
ddr3_odt => ddr3_odt,
ddr3_cke => ddr3_cke,
ddr3_dm => ddr3_dm,
ddr3_dqs_p => ddr3_dqs_p,
ddr3_dqs_n => ddr3_dqs_n,
ddr3_ck_p => ddr3_ck_p,
ddr3_ck_n => ddr3_ck_n,
app_wdf_wren => migi.app_wdf_wren,
app_wdf_data => migi.app_wdf_data,
app_wdf_mask => migi.app_wdf_mask,
app_wdf_end => migi.app_wdf_end,
app_addr => migi.app_addr,
app_cmd => migi.app_cmd,
app_en => migi.app_en,
app_rdy => migo.app_rdy,
app_wdf_rdy => migo.app_wdf_rdy,
app_rd_data => migo.app_rd_data,
app_rd_data_valid => migo.app_rd_data_valid,
tb_rst => open,
tb_clk => clk_ddr,
clk_ahb => clkm,
clk100 => clk100,
phy_init_done => phy_init_done,
sys_rst_13 => reset,
sys_rst_14 => rstraw
);
lock <= phy_init_done;
end generate;
led(3) <= lock;
led(4) <= rstn;
led(5) <= reset;
led(6) <= '0';
noddr : if CFG_MIG_DDR2 = 0 generate
ahbso(0) <= ahbs_none;
lock <= cgo.clklock;
clk_ddr <= '0';
end generate;
----------------------------------------------------------------------
--- System ACE I/F Controller ---------------------------------------
----------------------------------------------------------------------
grace: if CFG_GRACECTRL = 1 generate
grace0 : gracectrl generic map (hindex => 7, hirq => 10, mode => 2,
haddr => 16#002#, hmask => 16#fff#, split => CFG_SPLIT)
port map (rstn, clkm, clkace, ahbsi, ahbso(7), acei, aceo);
end generate;
nograce: if CFG_GRACECTRL /= 1 generate
aceo <= gracectrl_none;
end generate;
clk_33_pad : clkpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (clk_33, clkace);
sysace_mpa_pads : outpadv generic map (level => cmos, voltage => x25v, width => 7, tech => padtech)
port map (sysace_mpa, aceo.addr);
sysace_mpce_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (sysace_mpce, aceo.cen);
sysace_d_pads : iopadv generic map (level => cmos, voltage => x25v, tech => padtech, width => 8)
port map (sysace_d(7 downto 0), aceo.do(7 downto 0), aceo.doen, acei.di(7 downto 0));
acei.di(15 downto 8) <= (others => '0');
sysace_mpoe_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (sysace_mpoe, aceo.oen);
sysace_mpwe_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (sysace_mpwe, aceo.wen);
sysace_mpirq_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (sysace_mpirq, acei.irq);
-----------------PCI-EXPRESS-Master-Target------------------------------------------
pcie_mt : if CFG_PCIE_TYPE = 1 generate -- master/target without fifo
EP: pcie_master_target_virtex
generic map (
fabtech => fabtech,
hmstndx => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE,
hslvndx => 8,
abits => 21,
device_id => CFG_PCIEXPDID, -- PCIE device ID
vendor_id => CFG_PCIEXPVID, -- PCIE vendor ID
pcie_bar_mask => 16#FFE#,
nsync => 2, -- 1 or 2 sync regs between clocks
haddr => 16#a00#,
hmask => 16#fff#,
pindex => 5,
paddr => 5,
pmask => 16#fff#,
Master => CFG_PCIE_SIM_MAS,
lane_width => CFG_NO_OF_LANES
)
port map(
rst => rstn,
clk => clkm,
-- System Interface
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
sys_reset_n => sys_reset_n,
-- PCI Express Fabric Interface
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
ahbso => ahbso(8),
ahbsi => ahbsi,
apbi => apbi,
apbo => apbo(5),
ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE)
);
end generate;
------------------PCI-EXPRESS-Master-FIFO------------------------------------------
pcie_mf : if CFG_PCIE_TYPE = 3 generate -- master with fifo and DMA
dma:pciedma
generic map (fabtech => fabtech, memtech => memtech, dmstndx =>(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE),
dapbndx => 8, dapbaddr => 8,dapbirq => 8, blength => 12, abits => 21,
device_id => CFG_PCIEXPDID, vendor_id => CFG_PCIEXPVID, pcie_bar_mask => 16#FFE#,
slvndx => 8, apbndx => 5, apbaddr => 5, haddr => 16#A00#,hmask=> 16#FFF#,
nsync => 2,lane_width => CFG_NO_OF_LANES)
port map(
rst => rstn,
clk => clkm,
-- System Interface
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
sys_reset_n => sys_reset_n,
-- PCI Express Fabric Interface
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
dapbo => apbo(8),
dahbmo => ahbmo((CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE)),
apbi => apbi,
apbo => apbo(5),
ahbmi => ahbmi,
ahbsi => ahbsi,
ahbso => ahbso(8)
);
end generate;
----------------------------------------------------------------------
pcie_mf_no_dma: if CFG_PCIE_TYPE = 2 generate -- master with fifo
EP:pcie_master_fifo_virtex
generic map (fabtech => fabtech, memtech => memtech,
hslvndx => 8, abits => 21, device_id => CFG_PCIEXPDID, vendor_id => CFG_PCIEXPVID,
pcie_bar_mask => 16#FFE#, pindex => 5, paddr => 5,
haddr => 16#A00#, hmask => 16#FFF#, nsync => 2, lane_width => CFG_NO_OF_LANES)
port map(
rst => rstn,
clk => clkm,
-- System Interface
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
sys_reset_n => sys_reset_n,
-- PCI Express Fabric Interface
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
ahbso => ahbso(8),
ahbsi => ahbsi,
apbi => apbi,
apbo => apbo(5)
);
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
-- APB Bridge
apb0 : apbctrl
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
-- Interrupt controller
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
-- Time Unit
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW,
ntimers => CFG_GPT_NTIM, nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti <= gpti_dhalt_drive(dsuo.tstop);
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
-- GPIO Unit
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate
grgpio0: grgpio
generic map(pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 12)
port map(rstn, clkm, apbi, apbo(11), gpioi, gpioo);
end generate;
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1;
u1i.ctsn <= '0';
u1i.extclk <= '0';
txd1 <= u1o.txd;
serrx_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (dsurx, rxd1);
sertx_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (dsutx, txd1);
led(0) <= not rxd1;
led(1) <= not txd1;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master
i2c0 : i2cmst
generic map (pindex => 12, paddr => 12, pmask => 16#FFF#,
pirq => 11, filter => I2C_FILTER)
port map (rstn, clkm, apbi, apbo(12), i2ci, i2co);
i2c_scl_pad : iopad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (iic_scl_main, i2co.scl, i2co.scloen, i2ci.scl);
i2c_sda_pad : iopad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (iic_sda_main, i2co.sda, i2co.sdaoen, i2ci.sda);
end generate i2cm;
l4sgen : if CFG_STAT_ENABLE /= 0 generate
l4s : l3stat
generic map (pindex => 7, paddr => 16#100#, pmask => 16#ffc#,
ncnt => CFG_STAT_CNT, ncpu => CFG_NCPU,
nmax => CFG_STAT_NMAX, lahben => 1, dsuen => CFG_DSU)
port map (rstn => rstn, clk => clkm, apbi => apbi, apbo => apbo(7),
ahbsi => ahbsi, dbgo => dbgo);
end generate;
nol4s : if CFG_STAT_ENABLE = 0 generate
apbo(7) <= apb_none;
end generate;
-----------------------------------------------------------------------
--- VGA + IIC --------------------------------------------------------
-----------------------------------------------------------------------
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, clkvga, apbi, apbo(6), vgao);
clk_sel <= "00";
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG, clk0 => 40000,
clk1 => 24000, clk2 => 20000, clk3 => 16000, burstlen => 4,
ahbaccsz => CFG_AHBDW)
port map(rstn, clkm, clkvga, apbi, apbo(6), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), clk_sel);
end generate;
vgadvi : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) /= 0 generate
dvi0 : entity work.svga2ch7301c generic map (tech => fabtech, idf => 2)
port map (clk100, ethi.gtx_clk, lock, clk_sel, vgao, clkvga, clkvga_p, clkvga_n,
lcd_datal, lcd_hsyncl, lcd_vsyncl, lcd_del);
i2cdvi : i2cmst
generic map (pindex => 9, paddr => 9, pmask => 16#FFF#,
pirq => 7, filter => I2C_FILTER)
port map (rstn, clkm, apbi, apbo(9), dvi_i2ci, dvi_i2co);
end generate;
novga : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) = 0 generate
apbo(6) <= apb_none;
lcd_datal <= (others => '0'); clkvga_p <= '0'; clkvga_n <= '0';
lcd_hsyncl <= '0'; lcd_vsyncl <= '0'; lcd_del <= '0';
dvi_i2co.scloen <= '1'; dvi_i2co.sdaoen <= '1';
end generate;
tft_lcd_data_pad : outpadv generic map (level => cmos, voltage => x25v, width => 12, tech => padtech)
port map (tft_lcd_data, lcd_datal);
tft_lcd_clkp_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (tft_lcd_clk_p, clkvga_p);
tft_lcd_clkn_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (tft_lcd_clk_n, clkvga_n);
tft_lcd_hsync_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (tft_lcd_hsync, lcd_hsyncl);
tft_lcd_vsync_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (tft_lcd_vsync, lcd_vsyncl);
tft_lcd_de_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (tft_lcd_de, lcd_del);
tft_lcd_reset_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (tft_lcd_reset_b, rstn);
dvi_i2c_scl_pad : iopad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (dvi_iic_scl, dvi_i2co.scl, dvi_i2co.scloen, dvi_i2ci.scl);
dvi_i2c_sda_pad : iopad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (dvi_iic_sda, dvi_i2co.sda, dvi_i2co.sdaoen, dvi_i2ci.sda);
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm
generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 15, paddr => 15, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 7,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G,
enable_mdint => 1)
port map(rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
apbi => apbi, apbo => apbo(15), ethi => ethi, etho => etho);
end generate;
-- greth1g: if CFG_GRETH1G = 1 generate
gtxclk0 : entity work.gtxclk port map (
clk_p => gmiiclk_p, clk_n => gmiiclk_n, clkint => ethi.gtx_clk,
clkout => egtx_clk);
-- end generate;
ethpads : if (CFG_GRETH = 1) generate -- eth pads
emdio_pad : iopad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (level => cmos, voltage => x25v, tech => padtech, arch => 2)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (level => cmos, voltage => x25v, tech => padtech, arch => 2)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (level => cmos, voltage => x25v, tech => padtech, width => 8)
port map (erxd, ethi.rxd(7 downto 0));
erxdv_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (erx_crs, ethi.rx_crs);
emdint_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (emdint, ethi.mdint);
etxd_pad : outpadv generic map (level => cmos, voltage => x25v, tech => padtech, width => 8)
port map (etxd, etho.txd(7 downto 0));
etxen_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (etx_en, etho.tx_en);
etxer_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (emdc, etho.mdc);
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram
generic map (hindex => 3, haddr => CFG_AHBRADDR, tech => CFG_MEMTECH,
kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0 : ahbrep generic map (hindex => 4, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(4));
-- pragma translate_on
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+1+CFG_PCIEXP) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Demonstration design for Xilinx Virtex6 ML605 board",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end rtl;
| gpl-3.0 | e6ae5965322fb1aa7b0c2804ee342793 | 0.544567 | 3.466817 | false | false | false | false |
NeuroML/org.neuroml.export | src/main/resources/vhdl/ParamExp_TB.vhd | 1 | 3,344 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee_proposed.fixed_float_types.ALL;
use std.textio.all;
use ieee.std_logic_textio.all; -- if you're saving this type of signal
entity paramexp_tb is
end paramexp_tb;
architecture tb of paramexp_tb is
component ParamExp is
generic(
BIT_TOP : integer := 20;
BIT_BOTTOM : integer := -20);
port(
clk : In Std_logic;
rst : In Std_logic;
Start : In Std_logic;
Done : Out Std_logic;
X : In sfixed(BIT_TOP downto BIT_BOTTOM);
Output : Out sfixed(BIT_TOP downto BIT_BOTTOM)
);
end component;
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal Start : std_logic := '0';
signal Done : std_logic := '0';
signal X : sfixed(20 downto -20);
signal Output : sfixed(20 downto -20);
begin
ParamExp_uut : ParamExp
generic map(
BIT_TOP => 20,
BIT_BOTTOM => -20)
port map ( clk => clk,
rst => rst,
Start => Start,
Done => Done,
X => X,
Output => Output
);
process
begin
wait for 10ns;
clk <= not(clk);
wait for 10ns;
clk <= not(clk);
end process;
process (Done)
begin
if Done'event and Done = '1' then
report "The value of exp( " & real'image(to_real(X)) & " ) = " & real'image(to_real(Output));
end if;
end process;
process
begin
-- wait for Reset to complete
-- wait until rst='1';
rst<='1';
wait for 40 ns;
rst<='0';
wait for 40 ns;
X <= to_sfixed(0.01,20,-20);
wait for 20 ns;
Start <= '1';
wait for 20 ns;
Start <= '0';
wait for 1000 ns;
X <= to_sfixed(0.1,20,-20);
wait for 20 ns;
Start <= '1';
wait for 20 ns;
Start <= '0';
wait for 1000 ns;
X <= to_sfixed(1,20,-20);
wait for 20 ns;
Start <= '1';
wait for 20 ns;
Start <= '0';
wait for 1000 ns;
X <= to_sfixed(6.4,20,-20);
wait for 20 ns;
Start <= '1';
wait for 20 ns;
Start <= '0';
wait for 1000 ns;
X <= to_sfixed(12.9,20,-20);
wait for 20 ns;
Start <= '1';
wait for 20 ns;
Start <= '0';
wait for 1000 ns;
X <= to_sfixed(4.6,20,-20);
wait for 20 ns;
Start <= '1';
wait for 20 ns;
Start <= '0';
wait for 1000 ns;
X <= to_sfixed(4.5,20,-20);
wait for 20 ns;
Start <= '1';
wait for 20 ns;
Start <= '0';
wait for 1000 ns;
X <= to_sfixed(4.49,20,-20);
wait for 20 ns;
Start <= '1';
wait for 20 ns;
Start <= '0';
wait for 1000 ns;
X <= to_sfixed(-0.001,20,-20);
wait for 20 ns;
Start <= '1';
wait for 20 ns;
Start <= '0';
wait for 1000 ns;
X <= to_sfixed(-0.01,20,-20);
wait for 20 ns;
Start <= '1';
wait for 20 ns;
Start <= '0';
wait for 1000 ns;
X <= to_sfixed(-1.567,20,-20);
wait for 20 ns;
Start <= '1';
wait for 20 ns;
Start <= '0';
wait for 1000 ns;
X <= to_sfixed(-6,20,-20);
wait for 20 ns;
Start <= '1';
wait for 20 ns;
Start <= '0';
wait for 1000 ns;
X <= to_sfixed(-10.4,20,-20);
wait for 20 ns;
Start <= '1';
wait for 20 ns;
Start <= '0';
wait for 1000 ns;
X <= to_sfixed(-14,20,-20);
wait for 20 ns;
Start <= '1';
wait for 20 ns;
Start <= '0';
wait for 1000 ns;
end process;
end tb;
| lgpl-3.0 | ea720a129b248deae2e39339eb2816e7 | 0.547249 | 2.73426 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-altera-ep2s60-sdr/config.vhd | 1 | 5,990 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := stratix2;
constant CFG_MEMTECH : integer := stratix2;
constant CFG_PADTECH : integer := stratix2;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := stratix2;
constant CFG_CLKMUL : integer := (8);
constant CFG_CLKDIV : integer := (10);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- PROM/SRAM controller
constant CFG_SRCTRL : integer := 0;
constant CFG_SRCTRL_PROMWS : integer := 0;
constant CFG_SRCTRL_RAMWS : integer := 0;
constant CFG_SRCTRL_IOWS : integer := 0;
constant CFG_SRCTRL_RMW : integer := 0;
constant CFG_SRCTRL_8BIT : integer := 0;
constant CFG_SRCTRL_SRBANKS : integer := 1;
constant CFG_SRCTRL_BANKSZ : integer := 0;
constant CFG_SRCTRL_ROMASEL : integer := 0;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 1;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 1 + 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#FFFF#;
constant CFG_GRGPIO_WIDTH : integer := (32);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-3.0 | 68d806707218d370feafb098533ab5b0 | 0.645743 | 3.643552 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-clock-gate/clkgate.vhd | 1 | 2,522 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity clkgate is
generic (tech : integer := 0; ncpu : integer := 1; dsuen : integer := 1);
port (
rst : in std_ulogic;
clkin : in std_ulogic;
pwd : in std_logic_vector(ncpu-1 downto 0);
clkahb : out std_ulogic;
clkcpu : out std_logic_vector(ncpu-1 downto 0)
);
end;
architecture rtl of clkgate is
signal npwd, xpwd, ypwd : std_logic_vector(ncpu-1 downto 0);
signal vrst, wrst : std_logic_vector(ncpu-1 downto 0);
signal clken: std_logic_vector(ncpu-1 downto 0);
signal xrst, vcc : std_ulogic;
begin
vcc <= '1';
cand : for i in 0 to ncpu-1 generate
clken(i) <= not npwd(i);
clkand0 : clkand generic map (tech) port map (clkin, clken(i), clkcpu(i));
end generate;
cand0 : clkand generic map (tech) port map (clkin, vcc, clkahb);
vrst <= (others => rst);
r1 : if dsuen = 1 generate
nreg : process(clkin)
begin
if falling_edge(clkin) then
npwd <= pwd and vrst;
end if;
end process;
end generate;
r2 : if dsuen = 0 generate
reg : process(clkin)
begin
if rising_edge(clkin) then
xrst <= rst;
xpwd <= pwd and wrst;
end if;
end process;
wrst <= (others => xrst);
nreg : process(clkin)
begin
if falling_edge(clkin) then
npwd <= xpwd;
end if;
end process;
end generate;
end;
| gpl-3.0 | 11bfc7f7d6718bd54dbc843714ec369b | 0.614592 | 3.725258 | false | false | false | false |
hoglet67/CoPro6502 | src/DCM/dcm_32_24.vhd | 1 | 2,067 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity dcm_32_24 is
port (CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic);
end dcm_32_24;
architecture BEHAVIORAL of dcm_32_24 is
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKFX_BUFG_INST : BUFG
port map (I => CLKFX_BUF, O => CLK0_OUT);
DCM_INST : DCM
generic map(CLK_FEEDBACK => "NONE",
CLKDV_DIVIDE => 4.0, -- 24.000 = 32.000 * 15/20
CLKFX_DIVIDE => 20,
CLKFX_MULTIPLY => 15,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => 31.25,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => true,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => false)
port map (CLKFB => GND_BIT,
CLKIN => CLKIN_IN,
DSSEN => GND_BIT,
PSCLK => GND_BIT,
PSEN => GND_BIT,
PSINCDEC => GND_BIT,
RST => GND_BIT,
CLKDV => open,
CLKFX => CLKFX_BUF,
CLKFX180 => open,
CLK0 => open,
CLK2X => open,
CLK2X180 => open,
CLK90 => open,
CLK180 => open,
CLK270 => open,
LOCKED => open,
PSDONE => open,
STATUS => open);
end BEHAVIORAL;
| gpl-3.0 | f0aaa49ff2bc50c261c6969026751da6 | 0.405418 | 4.235656 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/testgrouppolito/pr/sync_dprc.vhd | 1 | 10,231 | ------------------------------------------------------------------------------
-- Copyright (c) 2014, Pascal Trotta - Testgroup (Politecnico di Torino)
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright notice, this
-- list of conditions and the following disclaimer in the documentation and/or other
-- materials provided with the distribution.
--
-- THIS SOURCE CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-- OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
-----------------------------------------------------------------------------
-- Entity: sync_dprc
-- File: sync_dprc.vhd
-- Author: Pascal Trotta (TestGroup research group - Politecnico di Torino)
-- Contacts: [email protected] www.testgroup.polito.it
-- Description: dprc sync mode (see the DPR IP-core user manual for operations details).
-- Last revision: 08/10/2014
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.DMA2AHB_Package.all;
library testgrouppolito;
use testgrouppolito.dprc_pkg.all;
entity sync_dprc is
port (
rstn : in std_ulogic; -- Asynchronous Reset input (active low)
clkm : in std_ulogic; -- Clock input
dmai : out DMA_In_Type; -- dma signals input
dmao : in DMA_Out_Type; -- dma signals output
icapi : out icap_in_type; -- icap input signals
icapo : in icap_out_type; -- icap output signals
apbregi : in dprc_apbregin_type; -- values from apb registers (control, address, rm_reset)
apbcontrol : out dprc_apbcontrol_type; -- control signals for apb register
rm_reset : out std_logic_vector(31 downto 0)); -- Reconfigurable modules reset (1 bit for each different reconfigurable partition);
end sync_dprc;
architecture syncdprc_rtl of sync_dprc is
type dprc_state is (IDLE, START, GRANTED, GRANTED_VERIFY, WAIT_WRITE_END, END_STATE, BUS_CNTL_ERROR, ICAP_ERROR_STATE, ABORT, ICAP_ERROR_LATENCY);
signal present_state, next_state : dprc_state;
type regs is record
c_grant : std_logic_vector(19 downto 0);
c_ready : std_logic_vector(19 downto 0);
c_latency : std_logic_vector(2 downto 0);
rm_reset : std_logic_vector(31 downto 0);
address : std_logic_vector(31 downto 0);
rst_persist : std_ulogic;
end record;
signal reg, regin : regs;
signal rstact : std_ulogic;
begin
-- fixed signals
dmai.Data <= (others => '0');
dmai.Beat <= HINCR;
dmai.Size <= HSIZE32;
dmai.Store <= '0'; --Only read transfer requests
dmai.Reset <= not(rstn);
dmai.Address <= reg.address;
rm_reset <= reg.rm_reset;
icapi.idata <= dmao.Data;
comb: process(dmao, icapo, apbregi, rstn, present_state, rstact, reg)
variable regv : regs;
begin
apbcontrol.timer_clear <= '0';
apbcontrol.status_clr <= '0';
dmai.Request <= '0';
dmai.Burst <= '0';
dmai.Lock <= '0';
apbcontrol.status_value <= (others=>'0');
apbcontrol.status_en <= '0';
apbcontrol.control_clr <= '0';
apbcontrol.timer_en <= '0';
icapi.cen <= '1';
icapi.wen <= '1';
rstact <= '0';
regv := reg;
case present_state is
when IDLE =>
if (apbregi.control(19 downto 0)/=X"00000") then
next_state <= START;
apbcontrol.timer_clear <= '1'; -- clear timer register
apbcontrol.status_clr <= '1'; -- clear status register
regv.c_grant := apbregi.control(19 downto 0);
regv.c_ready := apbregi.control(19 downto 0);
regv.address := apbregi.address;
else
next_state <= IDLE;
end if;
when START =>
if (dmao.Grant and dmao.Ready)='1' then
next_state <= GRANTED;
else
next_state <= START;
end if;
dmai.Request <= '1'; -- Request data
dmai.Burst <= '1'; -- Burst transfer
dmai.Lock <= '1'; -- Locked transfer
icapi.wen <= '0'; -- assert icap write enable
when GRANTED =>
if (icapo.odata(7) = '1') then -- if the ICAP is correctly initialized, then monitor ICAP status
next_state <= GRANTED_VERIFY;
dmai.Request <= '1'; -- Request data
dmai.Burst <= '1'; -- Burst transfer
dmai.Lock <= '1'; -- Locked transfer
elsif (regv.c_grant=0) then -- if the number of granted requests is equal to the bitstream words, no more requests are needed
next_state <= WAIT_WRITE_END; -- This line is inserted to cover the case of Virtex-4 ICAP incorrect initialization during device programming with Impact
else
next_state <= GRANTED;
dmai.Request <= '1'; -- Request data
dmai.Burst <= '1'; -- Burst transfer
dmai.Lock <= '1'; -- Locked transfer
end if;
icapi.wen <= '0'; -- assert icap write enable
icapi.cen <= not(dmao.Ready); --if valid data, write it into ICAP
when GRANTED_VERIFY =>
if (icapo.odata(7) = '0') then -- verify ICAP status for configuration errors
next_state <= ICAP_ERROR_STATE;
elsif (regv.c_grant=0) then -- if the number of granted requests is equal to the bitstream words, no more requests are needed
next_state <= WAIT_WRITE_END;
else
next_state <= GRANTED_VERIFY;
dmai.Request <= '1'; -- Request data
dmai.Burst <= '1'; -- Burst transfer
dmai.Lock <= '1'; -- Locked transfer
end if;
icapi.wen <= '0'; -- assert icap write enable
icapi.cen <= not(dmao.Ready); --if valid data, write it into ICAP
when WAIT_WRITE_END =>
if (icapo.odata(7) = '0') then -- verify ICAP status for configuration errors
next_state <= ICAP_ERROR_STATE;
elsif (regv.c_ready=0) then
next_state <= ICAP_ERROR_LATENCY;
else
next_state <= WAIT_WRITE_END;
end if;
icapi.wen <= '0'; -- assert icap write enable
icapi.cen <= not(dmao.Ready); --if valid data, write it into ICAP
when ICAP_ERROR_LATENCY =>
if (icapo.odata(7) = '0') then -- verify ICAP status for configuration errors
next_state <= ICAP_ERROR_STATE;
regv.c_latency := (others=>'0');
elsif (regv.c_latency=4) then
next_state <= END_STATE;
regv.c_latency := (others=>'0');
else
next_state <= ICAP_ERROR_LATENCY;
regv.c_latency := regv.c_latency+1;
end if;
icapi.wen <= '0';
when END_STATE =>
next_state <= IDLE;
apbcontrol.status_value(3 downto 0) <= "1111";
apbcontrol.status_en <= '1'; -- Write Status Register
apbcontrol.control_clr <= '1'; -- Clear Control Register
regv.rst_persist := '0';
when BUS_CNTL_ERROR =>
next_state <= ABORT;
apbcontrol.status_value(3 downto 0) <= "0100";
apbcontrol.status_en <= '1'; -- Write Status Register
apbcontrol.control_clr <= '1'; -- Clear Control Register
icapi.cen <= '0'; -- Start an 'abort configuration' sequence
regv.c_latency := (others=>'0');
when ICAP_ERROR_STATE =>
next_state <= ABORT;
apbcontrol.status_value(3 downto 0) <= "1000";
apbcontrol.status_en <= '1'; -- Write Status Register
apbcontrol.control_clr <= '1'; -- Clear Control Register
icapi.cen <= '0'; -- Start an 'abort configuration' sequence
regv.c_latency := (others=>'0');
when ABORT =>
if (regv.c_latency=4) then
next_state <= IDLE;
regv.c_latency := (others=>'0');
regv.rst_persist := '1';
else
next_state <= ABORT;
regv.c_latency := regv.c_latency+1;
end if;
icapi.cen <= '0'; -- continue abort sequence
end case;
if (present_state/=IDLE) then
apbcontrol.timer_en <= '1'; -- Enable timer
rstact <= '1';
if dmao.Ready='1' then
regv.c_ready:=regv.c_ready-1;
end if;
if dmao.Grant='1' then
regv.c_grant:=regv.c_grant-1;
regv.address:=regv.address+4;
end if;
end if;
if (dmao.Fault or dmao.Retry)='1' then
next_state <= BUS_CNTL_ERROR;
end if;
-- reconfigurable modules synchrounous reset generation (active high)
for i in 0 to 31 loop
regv.rm_reset(i) := not(rstn) or (apbregi.rm_reset(i) and (rstact or regv.rst_persist));
end loop;
-- registers assignment
regin <= regv;
end process;
reg_proc: process(rstn, clkm)
begin
if rstn='0' then
present_state <= IDLE;
reg.rm_reset <= (others=>'0');
reg.c_grant <= (others=>'0');
reg.c_ready <= (others=>'0');
reg.c_latency <= (others=>'0');
reg.address <= (others=>'0');
reg.rst_persist <= '0';
elsif rising_edge(clkm) then
present_state <= next_state;
reg <= regin;
end if;
end process;
end syncdprc_rtl;
| gpl-3.0 | f0afb7862af1361132832f80be7a0425 | 0.589385 | 3.980934 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/memctrl/sdctrl64.vhd | 1 | 29,787 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: sdctrl
-- File: sdctrl.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Jan Andersson - Aeroflex Gaisler
-- Description: 64-bit SDRAM memory controller.
-- Supports HSIZE_DWORD AMBA accesses when connected to
-- AHB data bus wider than 32 bits.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.memctrl.all;
entity sdctrl64 is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
pwron : integer := 0;
oepol : integer := 0;
pageburst : integer := 0;
mobile : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end;
architecture rtl of sdctrl64 is
constant WPROTEN : boolean := wprot = 1;
constant SDINVCLK : boolean := invclk = 1;
constant REVISION : integer := 0;
constant PM_PD : std_logic_vector(2 downto 0) := "001";
constant PM_SR : std_logic_vector(2 downto 0) := "010";
constant PM_DPD : std_logic_vector(2 downto 0) := "101";
constant std_rammask: Std_Logic_Vector(31 downto 20) :=
Conv_Std_Logic_Vector(hmask, 12);
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_SDCTRL64, 0, REVISION, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
5 => ahb_iobar(ioaddr, iomask),
others => zero32);
type mcycletype is (midle, active, leadout);
type sdcycletype is (act1, act2, act3, rd1, rd2, rd3, rd4, rd5, rd6, rd7, rd8,
wr1, wr2, wr3, wr4, wr5, sidle,
sref, pd, dpd);
type icycletype is (iidle, pre, ref, lmode, emode, finish);
-- sdram configuration register
type sdram_cfg_type is record
command : std_logic_vector(2 downto 0);
csize : std_logic_vector(1 downto 0);
bsize : std_logic_vector(2 downto 0);
casdel : std_ulogic; -- CAS to data delay: 2/3 clock cycles
trfc : std_logic_vector(2 downto 0);
trp : std_ulogic; -- precharge to activate: 2/3 clock cycles
refresh : std_logic_vector(14 downto 0);
renable : std_ulogic;
mobileen : std_logic_vector(1 downto 0); -- Mobile SD support, Mobile SD enabled
ds : std_logic_vector(3 downto 0); -- ds(1:0) (ds(3:2) used to detect update)
tcsr : std_logic_vector(3 downto 0); -- tcrs(1:0) (tcrs(3:2) used to detect update)
pasr : std_logic_vector(5 downto 0); -- pasr(2:0) (pasr(5:3) used to detect update)
pmode : std_logic_vector(2 downto 0); -- Power-Saving mode
txsr : std_logic_vector(3 downto 0); -- Exit Self Refresh timing
cke : std_ulogic; -- Clock enable
end record;
-- local registers
type reg_type is record
hready : std_ulogic;
hsel : std_ulogic;
bdrive : std_ulogic;
nbdrive : std_ulogic;
burst : std_ulogic;
wprothit : std_ulogic;
hio : std_ulogic;
startsd : std_ulogic;
mstate : mcycletype;
sdstate : sdcycletype;
cmstate : mcycletype;
istate : icycletype;
icnt : std_logic_vector(2 downto 0);
haddr : std_logic_vector(31 downto 0);
hrdata : std_logic_vector(63 downto 0);
hwdata : std_logic_vector(63 downto 0);
hwrite : std_ulogic;
htrans : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
size : std_logic_vector(1 downto 0);
cfg : sdram_cfg_type;
trfc : std_logic_vector(3 downto 0);
refresh : std_logic_vector(14 downto 0);
sdcsn : std_logic_vector(3 downto 0);
sdwen : std_ulogic;
rasn : std_ulogic;
casn : std_ulogic;
dqm : std_logic_vector(7 downto 0);
address : std_logic_vector(16 downto 1); -- memory address
idlecnt : std_logic_vector(3 downto 0); -- Counter, 16 idle clock sycles before entering Power-Saving mode
sref_tmpcom : std_logic_vector(2 downto 0); -- Save SD command when exit sref
pwron : std_ulogic;
end record;
signal r, ri : reg_type;
signal rbdrive, ribdrive : std_logic_vector(63 downto 0);
attribute syn_preserve : boolean;
attribute syn_preserve of rbdrive : signal is true;
begin
ctrl : process(rst, ahbsi, r, sdi, rbdrive)
variable v : reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable dataout : std_logic_vector(31 downto 0); -- data from memory
variable regsd : std_logic_vector(31 downto 0); -- data from registers
variable dqm : std_logic_vector(7 downto 0);
variable raddr : std_logic_vector(12 downto 0);
variable adec0 : std_ulogic;
variable adec1 : std_ulogic;
variable rams : std_logic_vector(3 downto 0);
variable ba : std_logic_vector(1 downto 0);
variable haddr : std_logic_vector(31 downto 0);
variable dout : std_logic_vector(63 downto 0);
variable hwrite : std_ulogic;
variable htrans : std_logic_vector(1 downto 0);
variable hready : std_ulogic;
variable vbdrive : std_logic_vector(63 downto 0);
variable bdrive : std_ulogic;
variable lline : std_logic_vector(2 downto 0);
variable haddr_tmp : std_logic_vector(31 downto 0);
variable arefresh : std_logic;
variable hwdata : std_logic_vector(63 downto 0);
begin
-- Variable default settings to avoid latches
v := r; startsd := '0'; v.hresp := HRESP_OKAY; vbdrive := rbdrive; arefresh := '0';
-- lline := not r.cfg.casdel & r.cfg.casdel & r.cfg.casdel;
lline := '1' & not r.cfg.casdel & '1';
v.hrdata(63 downto 0) := sdi.data(63 downto 0);
-- Select input data depending on AHB DW and AMBA data mux settings
if AHBDW = 32 then
hwdata := ahbreadword(ahbsi.hwdata, r.haddr(4 downto 2)) &
ahbreadword(ahbsi.hwdata, r.haddr(4 downto 2));
else
hwdata := ahbreaddword(ahbsi.hwdata, r.haddr(4 downto 2));
end if;
v.hwdata := hwdata;
-- AHB access
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
v.size := ahbsi.hsize(1 downto 0); v.hwrite := ahbsi.hwrite;
v.htrans := ahbsi.htrans;
if ahbsi.htrans(1) = '1' then
v.hio := ahbsi.hmbsel(1);
v.hsel := '1'; v.hready := v.hio;
end if;
v.haddr := ahbsi.haddr;
-- addr must be masked since address range can be smaller than
-- total banksize. this can result in wrong chip select being
-- asserted
for i in 31 downto 20 loop
v.haddr(i) := ahbsi.haddr(i) and not std_rammask(i);
end loop;
end if;
if (r.hsel = '1') and (ahbsi.hready = '0') then
haddr := r.haddr;
htrans := r.htrans; hwrite := r.hwrite;
else
haddr := ahbsi.haddr;
htrans := ahbsi.htrans; hwrite := ahbsi.hwrite;
-- addr must be masked since address range can be smaller than
-- total banksize. this can result in wrong chip select being
-- asserted
for i in 31 downto 20 loop
haddr(i) := ahbsi.haddr(i) and not std_rammask(i);
end loop;
end if;
if fast = 1 then haddr := r.haddr; end if;
if ahbsi.hready = '1' then v.hsel := ahbsi.hsel(hindex); end if;
-- main state
case r.size is
when "00" =>
case r.haddr(2 downto 0) is
when "000" => dqm := "01111111";
when "001" => dqm := "10111111";
when "010" => dqm := "11011111";
when "011" => dqm := "11101111";
when "100" => dqm := "11110111";
when "101" => dqm := "11111011";
when "110" => dqm := "11111101";
when others => dqm := "11111110";
end case;
when "01" =>
case r.haddr(2 downto 1) is
when "00" => dqm := "00111111";
when "01" => dqm := "11001111";
when "10" => dqm := "11110011";
when others => dqm := "11111100";
end case;
when "10" =>
if r.hwrite = '0' then dqm := "00000000";
elsif r.haddr(2) = '0' then dqm := "00001111";
else dqm := "11110000"; end if;
when others => dqm := "00000000";
end case;
-- main FSM
case r.mstate is
when midle =>
if ((v.hsel and htrans(1) and not v.hio) = '1') then
if (r.sdstate = sidle) and (r.cfg.command = "000")
and (r.cmstate = midle) and (v.hio = '0')
then
if fast = 0 then startsd := '1'; else v.startsd := '1'; end if;
v.mstate := active;
elsif ((r.sdstate = sref) or (r.sdstate = pd) or (r.sdstate = dpd))
and (r.cfg.command = "000") and (r.cmstate = midle) and (v.hio = '0')
then
v.startsd := '1';
if r.sdstate = dpd then -- Error response when on Deep Power-Down mode
v.hresp := HRESP_ERROR;
else
v.mstate := active;
end if;
end if;
end if;
when others => null;
end case;
startsd := startsd or r.startsd;
-- generate row and column address size
case r.cfg.csize is
when "00" => raddr := haddr(23 downto 11);
when "01" => raddr := haddr(24 downto 12);
when "10" => raddr := haddr(25 downto 13);
when others =>
if r.cfg.bsize = "111" then raddr := haddr(27 downto 15);
else raddr := haddr(26 downto 14); end if;
end case;
-- generate bank address
ba := genmux(r.cfg.bsize, haddr(29 downto 21)) &
genmux(r.cfg.bsize, haddr(28 downto 20));
-- generate chip select
adec0 := genmux(r.cfg.bsize, haddr(29 downto 22));
adec1 := genmux(r.cfg.bsize, haddr(30 downto 23));
rams := (adec1 and adec0) & (adec1 and not adec0) & (not adec1 and adec0) & (not adec1 and not adec0);
-- sdram access FSM
if r.trfc /= "0000" then v.trfc := r.trfc - 1; end if;
if r.idlecnt /= "0000" then v.idlecnt := r.idlecnt - 1; end if;
case r.sdstate is
when sidle =>
if (startsd = '1') and (r.cfg.command = "000") and (r.cmstate = midle) then
v.address(16 downto 1) := ba & raddr & '0';
v.sdcsn := not rams(3 downto 0); v.rasn := '0'; v.sdstate := act1;
v.startsd := '0';
elsif (r.idlecnt = "0000") and (r.cfg.command = "000")
and (r.cmstate = midle) and (r.cfg.mobileen(1) = '1') then
case r.cfg.pmode is
when PM_SR =>
v.cfg.cke := '0'; v.sdstate := sref;
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc; -- Control minimum duration of Self Refresh mode (= tRAS)
when PM_PD => v.cfg.cke := '0'; v.sdstate := pd;
when PM_DPD =>
v.cfg.cke := '0'; v.sdstate := dpd;
v.sdcsn := (others => '0'); v.sdwen := '0'; v.rasn := '1'; v.casn := '1';
when others =>
end case;
end if;
when act1 =>
v.rasn := '1'; v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc;
if r.cfg.casdel = '1' then v.sdstate := act2; else
v.sdstate := act3;
v.hready := r.hwrite and ahbsi.htrans(0) and ahbsi.htrans(1);
end if;
if WPROTEN then
v.wprothit := sdi.wprot;
if sdi.wprot = '1' then v.hresp := HRESP_ERROR; end if;
end if;
when act2 =>
v.sdstate := act3;
v.hready := r.hwrite and ahbsi.htrans(0) and ahbsi.htrans(1);
if WPROTEN and (r.wprothit = '1') then
v.hresp := HRESP_ERROR; v.hready := '0';
end if;
when act3 =>
v.casn := '0';
v.address(14 downto 1) := r.haddr(14 downto 13) & '0' & r.haddr(12 downto 2);
v.dqm := dqm; v.burst := r.hready;
if r.hwrite = '1' then
v.sdstate := wr1; v.sdwen := '0'; v.bdrive := '0';
if ahbsi.htrans = "11" or (r.hready = '0') then v.hready := '1'; end if;
if WPROTEN and (r.wprothit = '1') then
v.hresp := HRESP_ERROR; v.hready := '1';
v.sdstate := wr1; v.sdwen := '1'; v.bdrive := '1'; v.casn := '1';
end if;
else v.sdstate := rd1; end if;
when wr1 =>
v.dqm := dqm;
v.address(14 downto 2) := r.haddr(14 downto 13) & '0' & r.haddr(12 downto 3);
if ((((r.burst and r.hready) = '1') and (r.htrans = "11"))
and not (WPROTEN and (r.wprothit = '1'))) then
v.hready := ahbsi.htrans(0) and ahbsi.htrans(1) and r.hready;
if ((r.haddr(5 downto 2) = "1111") and (r.cfg.command = "100")) then -- exit on refresh
v.hready := '0';
end if;
else
v.sdstate := wr2; v.bdrive := '1'; v.casn := '1'; v.sdwen := '1';
v.dqm := (others => '1');
end if;
when wr2 =>
if (r.trfc(2 downto 1) = "00") then
if (r.cfg.trp = '0') then v.rasn := '0'; v.sdwen := '0'; end if;
v.sdstate := wr3;
end if;
when wr3 =>
if (r.cfg.trp = '1') then
v.rasn := '0'; v.sdwen := '0'; v.sdstate := wr4;
else
v.sdcsn := "1111"; v.rasn := '1'; v.sdwen := '1'; v.sdstate := sidle;
v.idlecnt := (others => '1');
end if;
when wr4 =>
v.sdcsn := "1111"; v.rasn := '1'; v.sdwen := '1';
if (r.cfg.trp = '1') then v.sdstate := wr5;
else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
when wr5 =>
v.sdstate := sidle; v.idlecnt := (others => '1');
when rd1 =>
v.casn := '1'; v.sdstate := rd7;
if (ahbsi.htrans = "11") then
if r.size = "11" then v.address(9 downto 1) := r.address(9 downto 1) + 2;
else v.address(9 downto 1) := r.address(9 downto 1) + 1; end if;
v.casn := '0';
end if;
when rd7 =>
v.casn := '1';
if r.cfg.casdel = '1' then
v.sdstate := rd2;
if (ahbsi.htrans = "11") then
if r.size = "11" then v.address(9 downto 1) := r.address(9 downto 1) + 2;
else v.address(9 downto 1) := r.address(9 downto 1) + 1; end if;
v.casn := '0';
end if;
else
v.sdstate := rd3;
if ahbsi.htrans /= "11" then
if (r.trfc(3 downto 1) = "000") then v.rasn := '0'; v.sdwen := '0'; end if;
else
if r.size = "11" then v.address(9 downto 1) := r.address(9 downto 1) + 2;
else v.address(9 downto 1) := r.address(9 downto 1) + 1; end if;
v.casn := '0';
end if;
end if;
when rd2 =>
v.casn := '1'; v.sdstate := rd3;
if ahbsi.htrans /= "11" then
if (r.trfc(3 downto 1) = "000") then v.rasn := '0'; v.sdwen := '0'; end if;
else
if r.size = "11" then v.address(9 downto 1) := r.address(9 downto 1) + 2;
else v.address(9 downto 1) := r.address(9 downto 1) + 1; end if;
v.casn := '0';
end if;
if v.sdwen = '0' then v.dqm := (others => '1'); end if;
when rd3 =>
v.sdstate := rd4; v.hready := '1'; v.casn := '1';
if r.sdwen = '0' then
v.rasn := '1'; v.sdwen := '1'; v.sdcsn := "1111"; v.dqm := (others => '1');
else
if (ahbsi.htrans = "11") then
if r.size = "11" then v.address(9 downto 1) := r.address(9 downto 1) + 2;
else v.address(9 downto 1) := r.address(9 downto 1) + 1; end if;
v.casn := '0';
end if;
end if;
when rd4 =>
v.hready := '1'; v.casn := '1';
if (ahbsi.htrans /= "11") or (r.sdcsn = "1111") or
((r.haddr(5 downto 2) = ("111" & not r.size(0))) and (r.cfg.command = "100")) -- exit on refresh
then
v.hready := '0'; v.dqm := (others => '1');
if (r.sdcsn /= "1111") then
v.rasn := '0'; v.sdwen := '0'; v.sdstate := rd5;
else
if r.cfg.trp = '1' then v.sdstate := rd6;
else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
end if;
else
if r.size = "11" then v.address(9 downto 1) := r.address(9 downto 1) + 2;
else v.address(9 downto 1) := r.address(9 downto 1) + 1; end if;
v.casn := '0';
end if;
when rd5 =>
if r.cfg.trp = '1' then v.sdstate := rd6; else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1'; v.dqm := (others => '1');
v.casn := '1';
when rd6 =>
v.sdstate := sidle; v.idlecnt := (others => '1'); v.dqm := (others => '1');
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1';
when sref =>
if (startsd = '1' and (r.hio = '0'))
or (r.cfg.command /= "000") or r.cfg.pmode /= PM_SR then
if r.trfc = "0000" then -- Minimum duration (= tRAS)
v.cfg.cke := '1';
v.sdcsn := (others => '0'); v.rasn := '1'; v.casn := '1';
end if;
if r.cfg.cke = '1' then
if (r.idlecnt = "0000") then -- tXSR ns with NOP
v.sdstate := sidle;
v.idlecnt := (others => '1');
v.sref_tmpcom := r.cfg.command;
v.cfg.command := "100";
end if;
else
v.idlecnt := r.cfg.txsr;
end if;
end if;
when pd =>
if (startsd = '1' and (r.hio = '0'))
or (r.cfg.command /= "000") or r.cfg.pmode /= PM_PD then
v.cfg.cke := '1';
v.sdstate := sidle;
v.idlecnt := (others => '1');
end if;
when dpd =>
v.sdcsn := (others => '1'); v.sdwen := '1'; v.rasn := '1'; v.casn := '1';
v.cfg.renable := '0';
if (startsd = '1' and r.hio = '0') then
v.hready := '1'; -- ack all accesses with Error response
v.startsd := '0';
v.hresp := HRESP_ERROR;
elsif r.cfg.pmode /= PM_DPD then
v.cfg.cke := '1';
if r.cfg.cke = '1' then
v.sdstate := sidle;
v.idlecnt := (others => '1');
v.cfg.renable := '1';
end if;
end if;
when others =>
v.sdstate := sidle; v.idlecnt := (others => '1');
end case;
-- sdram commands
case r.cmstate is
when midle =>
if r.sdstate = sidle then
case r.cfg.command is
when "010" => -- precharge
v.sdcsn := (others => '0'); v.rasn := '0'; v.sdwen := '0';
v.address(12) := '1'; v.cmstate := active;
when "100" => -- auto-refresh
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.cmstate := active;
when "110" => -- Lodad Mode Reg
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active;
v.address(16 downto 2) := "0000010001" & r.cfg.casdel & "0000";
when "111" => -- Load Ext-Mode Reg
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active;
v.address(16 downto 2) := "10000000" & r.cfg.ds(1 downto 0) & r.cfg.tcsr(1 downto 0)
& r.cfg.pasr(2 downto 0);
when others => null;
end case;
end if;
when active =>
v.sdcsn := (others => '1'); v.rasn := '1'; v.casn := '1';
v.sdwen := '1'; --v.cfg.command := "000";
v.cfg.command := r.sref_tmpcom; v.sref_tmpcom := "000";
v.cmstate := leadout; v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc;
when leadout =>
if r.trfc = "0000" then v.cmstate := midle; end if;
end case;
-- sdram init
case r.istate is
when iidle =>
v.cfg.cke := '1';
if (r.cfg.renable = '1' or (pwron /= 0 and r.pwron = '1')) and r.cfg.cke = '1' then
v.cfg.command := "010"; v.istate := pre;
end if;
when pre =>
if r.cfg.command = "000" then
v.cfg.command := "100"; v.istate := ref; v.icnt := "111";
end if;
when ref =>
if r.cfg.command = "000" then
v.cfg.command := "100"; v.icnt := r.icnt - 1;
if r.icnt = "000" then v.istate := lmode; v.cfg.command := "110"; end if;
end if;
when lmode =>
if r.cfg.command = "000" then
if r.cfg.mobileen = "11" then
v.cfg.command := "111"; v.istate := emode;
else
v.istate := finish;
end if;
end if;
when emode =>
if r.cfg.command = "000" then
v.istate := finish;
end if;
when others =>
if pwron /= 0 then v.pwron := '0'; end if;
if r.cfg.renable = '0' and r.sdstate /= dpd then
v.istate := iidle;
end if;
end case;
if (ahbsi.hready and ahbsi.hsel(hindex) ) = '1' then
if ahbsi.htrans(1) = '0' then v.hready := '1'; end if;
end if;
if (r.hsel and r.hio and not r.hready) = '1' then v.hready := '1'; end if;
-- second part of main fsm
case r.mstate is
when active =>
if v.hready = '1' then
v.mstate := midle;
end if;
when others => null;
end case;
-- sdram refresh counter
-- pragma translate_off
if not is_x(r.cfg.refresh) then
-- pragma translate_on
if (r.cfg.renable = '1') and (r.istate = finish) and r.sdstate /= sref then
v.refresh := r.refresh - 1;
if (v.refresh(14) and not r.refresh(14)) = '1' then
v.refresh := r.cfg.refresh;
v.cfg.command := "100";
arefresh := '1';
end if;
end if;
-- pragma translate_off
end if;
-- pragma translate_on
-- AHB register access
if (r.hsel and r.hio and r.hwrite and r.htrans(1)) = '1' then
if r.haddr(3 downto 2) = "00" then
v.cfg.command := hwdata(20 downto 18);
v.cfg.csize := hwdata(22 downto 21);
v.cfg.bsize := hwdata(25 downto 23);
v.cfg.casdel := hwdata(26);
v.cfg.trfc := hwdata(29 downto 27);
v.cfg.trp := hwdata(30);
v.cfg.renable := hwdata(31);
v.cfg.refresh := hwdata(14 downto 0);
v.refresh := (others => '0');
elsif r.haddr(3 downto 2) = "01" then
if r.cfg.mobileen(1) = '1' and mobile /= 3 then v.cfg.mobileen(0) := hwdata(31); end if;
if r.cfg.pmode = "000" then
v.cfg.cke := hwdata(30);
end if;
if r.cfg.mobileen(1) = '1' then
v.cfg.txsr := hwdata(23 downto 20);
v.cfg.pmode := hwdata(18 downto 16);
v.cfg.ds(3 downto 2) := hwdata( 6 downto 5);
v.cfg.tcsr(3 downto 2) := hwdata( 4 downto 3);
v.cfg.pasr(5 downto 3) := hwdata( 2 downto 0);
end if;
end if;
end if;
-- Disable CS and DPD when Mobile SDR is Disabled
if r.cfg.mobileen(0) = '0' then v.cfg.pmode(2) := '0'; end if;
-- Update EMR when ds, tcsr or pasr change
if r.cfg.command = "000" and arefresh = '0' and r.cfg.mobileen(0) = '1' then
if r.cfg.ds(1 downto 0) /= r.cfg.ds(3 downto 2) then
v.cfg.command := "111"; v.cfg.ds(1 downto 0) := r.cfg.ds(3 downto 2);
end if;
if r.cfg.tcsr(1 downto 0) /= r.cfg.tcsr(3 downto 2) then
v.cfg.command := "111"; v.cfg.tcsr(1 downto 0) := r.cfg.tcsr(3 downto 2);
end if;
if r.cfg.pasr(2 downto 0) /= r.cfg.pasr(5 downto 3) then
v.cfg.command := "111"; v.cfg.pasr(2 downto 0) := r.cfg.pasr(5 downto 3);
end if;
end if;
regsd := (others => '0');
if r.haddr(3 downto 2) = "00" then
regsd(31 downto 18) := r.cfg.renable & r.cfg.trp & r.cfg.trfc &
r.cfg.casdel & r.cfg.bsize & r.cfg.csize & r.cfg.command;
regsd(16) := r.cfg.mobileen(1);
regsd(15) := '1'; -- 64-bit support
regsd(14 downto 0) := r.cfg.refresh;
elsif r.haddr(3 downto 2) = "01" then
regsd(31) := r.cfg.mobileen(0);
regsd(30) := r.cfg.cke;
regsd(23 downto 0) := r.cfg.txsr & '0' & r.cfg.pmode & "000000000" &
r.cfg.ds(1 downto 0) & r.cfg.tcsr(1 downto 0) & r.cfg.pasr(2 downto 0);
end if;
if (r.hsel and r.hio) = '1' then dout := regsd & regsd;
else
dout := r.hrdata;
-- Possibly duplicate data for reads < HSIZE_DWORD since the system may
-- not be fully AMBA compliant and other cores may expect that the valid
-- WORD is present on 31:0 of AMBA HRDATA.
if andv(r.size) /= '1' and r.haddr(2) = '0' then
dout(31 downto 0) := r.hrdata(63 downto 32);
if r.hready = '1' then v.hrdata := r.hrdata; end if;
end if;
end if;
v.nbdrive := not v.bdrive;
if oepol = 1 then bdrive := r.nbdrive; vbdrive := (others => v.nbdrive);
else bdrive := r.bdrive; vbdrive := (others => v.bdrive);end if;
-- reset
if rst = '0' then
v.sdstate := sidle;
v.mstate := midle;
v.istate := iidle;
v.cmstate := midle;
v.hsel := '0';
v.cfg.command := "000";
v.cfg.csize := "10";
v.cfg.bsize := "000";
v.cfg.casdel := '1';
v.cfg.trfc := "111";
v.cfg.renable := '0';
v.cfg.trp := '1';
v.dqm := (others => '1');
v.sdwen := '1';
v.rasn := '1';
v.casn := '1';
v.hready := '1';
v.startsd := '0';
if pwron /= 0 then v.pwron := '1'; end if;
if mobile >= 2 then v.cfg.mobileen := "11";
elsif mobile = 1 then v.cfg.mobileen := "10";
else v.cfg.mobileen := "00"; end if;
v.cfg.txsr := (others => '1');
v.cfg.pmode := (others => '0');
v.cfg.ds := (others => '0');
v.cfg.tcsr := (others => '0');
v.cfg.pasr := (others => '0');
if mobile >= 2 then v.cfg.cke := '0';
else v.cfg.cke := '1'; end if;
v.sref_tmpcom := "000";
v.idlecnt := (others => '1');
v.hio := '0';
end if;
if pwron = 0 then v.pwron := '0'; end if;
if not WPROTEN then v.wprothit := '0'; end if;
ri <= v;
ribdrive <= vbdrive;
ahbso.hready <= r.hready;
ahbso.hresp <= r.hresp;
ahbso.hrdata <= ahbdrivedata(dout);
end process;
--sdo.sdcke <= (others => '1');
sdo.sdcke <= (others => r.cfg.cke);
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
sdo.cb <= (others => '0'); sdo.ba <= (others => '0');
sdo.cal_en <= (others => '0'); sdo.sdck <= (others => '0');
sdo.cal_pll <= (others => '0'); sdo.cal_inc <= (others => '0');
sdo.conf <= (others => '0'); sdo.odt <= (others => '0');
sdo.oct <= '0';
sdo.qdrive <= '0';
sdo.ce <= '0';
sdo.moben <= '0';
sdo.cal_rst <= '0';
sdo.vcbdrive <= (others => '0');
sdo.cbdqm <= (others => '0');
sdo.cbcal_en <= (others => '0');
sdo.cbcal_inc <= (others => '0');
sdo.read_pend <= (others => '0');
sdo.regwdata <= (others => '0');
sdo.regwrite <= (others => '0');
sdo.dqs_gate <= '0';
sdo.nbdrive <= '0';
regs : process(clk, rst) begin
if rising_edge(clk) then
r <= ri; rbdrive <= ribdrive;
if rst = '0' then r.icnt <= (others => '0'); end if;
end if;
if (rst = '0') then
r.sdcsn <= (others => '1'); r.bdrive <= '1'; r.nbdrive <= '0';
if oepol = 0 then rbdrive <= (others => '1');
else rbdrive <= (others => '0'); end if;
end if;
end process;
rgen : if not SDINVCLK generate
sdo.address <= r.address(16 downto 2);
sdo.bdrive <= r.nbdrive when oepol = 1 else r.bdrive;
sdo.vbdrive <= rbdrive;
sdo.sdcsn <= r.sdcsn(1 downto 0);
sdo.xsdcsn <= "1111" & r.sdcsn;
sdo.sdwen <= r.sdwen;
sdo.dqm <= "11111111" & r.dqm;
sdo.rasn <= r.rasn;
sdo.casn <= r.casn;
sdo.data <= zero64 & r.hwdata;
end generate;
ngen : if SDINVCLK generate
nregs : process(clk, rst) begin
if falling_edge(clk) then
sdo.address <= r.address(16 downto 2);
if oepol = 1 then sdo.bdrive <= r.nbdrive;
else sdo.bdrive <= r.bdrive; end if;
sdo.vbdrive <= rbdrive;
sdo.sdcsn <= r.sdcsn(1 downto 0);
sdo.xsdcsn <= "1111" & r.sdcsn;
sdo.sdwen <= r.sdwen;
sdo.dqm <= "11111111" & r.dqm;
sdo.rasn <= r.rasn;
sdo.casn <= r.casn;
sdo.data(63 downto 0) <= r.hwdata;
end if;
if rst = '0' then sdo.sdcsn <= (others => '1'); end if;
end process;
end generate;
-- pragma translate_off
bootmsg : report_version
generic map ("sdctrl64" & tost(hindex) &
": 64-bit PC133 SDRAM controller rev " & tost(REVISION));
-- pragma translate_on
end;
| gpl-3.0 | 7d48d51375040bc055c065e3c6a1516f | 0.525498 | 3.240888 | false | false | false | false |
pwsoft/fpga_examples | rtl/ttl/ttl_74139.vhd | 1 | 3,223 | -- -----------------------------------------------------------------------
--
-- Syntiac VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2018 by Peter Wendrich ([email protected])
-- http://www.syntiac.com
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
-- Dual 2 to 4 line demultiplexer
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.ttl_pkg.all;
-- -----------------------------------------------------------------------
entity ttl_74139 is
generic (
latency : integer := 1
);
port (
emuclk : in std_logic;
p1 : in ttl_t;
p2 : in ttl_t;
p3 : in ttl_t;
p4 : out ttl_t;
p5 : out ttl_t;
p6 : out ttl_t;
p7 : out ttl_t;
p9 : out ttl_t;
p10 : out ttl_t;
p11 : out ttl_t;
p12 : out ttl_t;
p13 : in ttl_t;
p14 : in ttl_t;
p15 : in ttl_t
);
end entity;
architecture rtl of ttl_74139 is
signal p4_loc : ttl_t;
signal p5_loc : ttl_t;
signal p6_loc : ttl_t;
signal p7_loc : ttl_t;
signal p9_loc : ttl_t;
signal p10_loc : ttl_t;
signal p11_loc : ttl_t;
signal p12_loc : ttl_t;
begin
p4_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p4_loc, q => p4);
p5_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p5_loc, q => p5);
p6_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p6_loc, q => p6);
p7_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p7_loc, q => p7);
p9_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p9_loc, q => p9);
p10_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p10_loc, q => p10);
p11_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p11_loc, q => p11);
p12_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p12_loc, q => p12);
p4_loc <= p1 or p2 or p3;
p5_loc <= p1 or (not p2) or p3;
p6_loc <= p1 or p2 or (not p3);
p7_loc <= p1 or (not p2) or (not p3);
p9_loc <= p15 or (not p13) or (not p14);
p10_loc <= p15 or (not p13) or p14;
p11_loc <= p15 or p13 or (not p14);
p12_loc <= p15 or p13 or p14;
end architecture;
| lgpl-2.1 | aa469152274ed795ba7307eb18fa2bd1 | 0.579274 | 3.003728 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-altera-ep2sgx90-av/leon3mp.vhd | 1 | 22,520 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.net.all;
use gaisler.jtag.all;
library esa;
use esa.memoryctrl.all;
use work.ft245.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
-- RESET, CLK, ERROR
resetn : in std_ulogic;
clk : in std_ulogic;
errorn : out std_ulogic;
-- combined flash/SSRAM/IO bus (fs_...)
fs_addr : out std_logic_vector(24 downto 0);
fs_data : inout std_logic_vector(31 downto 0);
-- IO chip enable
io_cen : out std_logic;
io_wen : out std_logic;
-- separate flash signals (flash_...)
flash_cen : out std_ulogic;
flash_oen : out std_logic;
flash_wen : out std_logic;
-- separate SSRAM signals (ssram_...)
ssram_cen : out std_logic;
ssram_wen : out std_logic;
ssram_bw : out std_logic_vector (3 downto 0);
ssram_oen : out std_ulogic;
ssram_clk : out std_ulogic;
ssram_adscn : out std_ulogic;
ssram_adspn : out std_ulogic;
ssram_advn : out std_ulogic;
-- DDR2
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_odt : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (7 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (7 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (63 downto 0); -- ddr data
-- ETHERNET PHY
phy_gtx_clk : out std_logic;
phy_mii_data: inout std_logic; -- ethernet PHY interface
phy_tx_clk : in std_ulogic;
phy_rx_clk : in std_ulogic;
phy_rx_data : in std_logic_vector(7 downto 0);
phy_dv : in std_ulogic;
phy_rx_er : in std_ulogic;
phy_col : in std_ulogic;
phy_crs : in std_ulogic;
phy_tx_data : out std_logic_vector(7 downto 0);
phy_tx_en : out std_ulogic;
phy_tx_er : out std_ulogic;
phy_mii_clk : out std_ulogic;
-- debug support unit
dsuact : out std_ulogic;
-- console/debug UART
rxd1 : in std_logic;
txd1 : out std_logic;
-- FT245 UART
ft245_data : inout std_logic_vector (7 downto 0);
ft245_rdn : out std_logic;
ft245_wr : out std_logic;
ft245_rxfn : in std_logic;
ft245_txen : in std_logic;
ft245_pwrenn : in std_logic;
-- GPIO
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0)
);
end;
architecture rtl of leon3mp is
constant maxahbm : integer := NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH;
signal vcc, gnd : std_logic_vector(7 downto 0);
signal memi, smemi : memory_in_type;
signal memo, smemo : memory_out_type;
signal wpo : wprot_out_type;
signal ddrclkfb, ssrclkfb, ddr_clkl, ddr_clk90l, ddr_clknl, ddr_clk270l : std_ulogic;
signal ddr_clkv : std_logic_vector(2 downto 0);
signal ddr_clkbv : std_logic_vector(2 downto 0);
signal ddr_ckev : std_logic_vector(1 downto 0);
signal ddr_csbv : std_logic_vector(1 downto 0);
signal ddr_adl : std_logic_vector (13 downto 0);
signal clklock, lock, clkml, rst, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal ddrclk, ddrrst : std_ulogic;
-- attribute syn_keep : boolean;
-- attribute syn_preserve : boolean;
-- attribute syn_keep of clkml : signal is true;
-- attribute syn_preserve of clkml : signal is true;
signal extd : std_logic_vector(31 downto 0);
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector;
signal clkm, rstn, ssram_clkl : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal ft245i : ft245_in_type;
signal ft245o : ft245_out_type;
signal ft245_vbdrive : std_logic_vector(7 downto 0);
constant IOAEN : integer := 1;
constant BOARD_FREQ : integer := 100000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= not resetn; cgi.pllref <= '0';
clklock <= cgo.clklock and lock;
clkgen0 : clkgen -- clock generator for main clock
generic map (tech => CFG_CLKTECH, clk_mul => CFG_CLKMUL, clk_div => CFG_CLKDIV,
sdramen => CFG_MCTRL_SDEN, pcien => 0, pcidll => 0,
freq => BOARD_FREQ, clk2xen => 0, clksel => 0, clk_odiv => 0)
port map (clkin => clk, pciclkin => gnd(0), clk => clkm, clkn => ssram_clkl,
clk2x => open, sdclk => open, pciclk => open,
cgi => cgi, cgo => cgo);
-- ssram_clkl <= not clkm;
ssrclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (ssram_clk, ssram_clkl);
rst0 : rstgen -- reset generator
port map (resetn, clkm, clklock, rstn);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsui.break <= '0';
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (rxd1, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (txd1, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mctrl0 : if CFG_MCTRL_LEON2 = 1 generate
mctrl0 : mctrl generic map (hindex => 0, pindex => 0,
romaddr => 16#000#, rommask => 16#E00#,
ioaddr => 16#200#, iomask => 16#E00#,
ramaddr => 16#C00#, rammask => 16#F00#,
paddr => 0, pmask => 16#FFF#,
srbanks => 1, wprot => 0,
ram8 => CFG_MCTRL_RAM8BIT, ram16 => CFG_MCTRL_RAM16BIT,
sden => CFG_MCTRL_SDEN,
invclk => CFG_MCTRL_INVCLK, sepbus => CFG_MCTRL_SEPBUS)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, open);
end generate;
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
mg0 : if CFG_MCTRL_LEON2 = 0 generate -- no prom/sram pads
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
rom_sel_pad : outpad generic map (tech => padtech)
port map (flash_cen, vcc(0));
ssram_sel_pad : outpad generic map (tech => padtech)
port map (ssram_cen, vcc(0));
io_sel_pad : outpad generic map (tech => padtech)
port map (io_cen, vcc(0));
end generate;
mgpads : if CFG_MCTRL_LEON2 = 1 generate
-- flash/ssram data/address pads
fsaddr_pad : outpadv generic map (width => 25, tech => padtech)
port map (fs_addr, memo.address(25 downto 1));
fsdata_pad : iopadvv generic map (width => 32, tech => padtech)
port map (fs_data, memo.data, memo.vbdrive, memi.data);
-- flash only pads
rom_sel_pad : outpad generic map (tech => padtech)
port map (flash_cen, memo.romsn(0));
rom_oen_pad : outpad generic map (tech => padtech)
port map (flash_oen, memo.oen);
rom_wri_pad : outpad generic map (tech => padtech)
port map (flash_wen, memo.writen);
-- ssram only pads
ssram_adv_n_pad : outpad generic map (tech => padtech)
port map (ssram_advn, vcc(0));
ssram_adsp_n_pad : outpad generic map (tech => padtech)
port map (ssram_adspn, vcc(0));
ssram_adscn_pad : outpad generic map (tech => padtech)
port map (ssram_adscn, gnd(0));
ssram_sel_pad : outpad generic map ( tech => padtech)
port map (ssram_cen, memo.ramsn(0));
ssram_oen_pad : outpad generic map (tech => padtech)
port map (ssram_oen, memo.ramoen(0));
ssram_wen_pad : outpad generic map (tech => padtech)
port map (ssram_wen, memo.wrn(0));
ssram_bw_pad : outpadv generic map (width => 4, tech => padtech)
port map (ssram_bw, memo.mben);
-- io data
io_sel_pad : outpad generic map (tech => padtech)
port map (io_cen, memo.iosn);
io_wri_pad : outpad generic map (tech => padtech)
port map (io_wen, memo.writen);
end generate;
ddrsp0 : if (CFG_DDR2SP /= 0) generate
ddrc0 : ddr2spa generic map ( fabtech => fabtech, memtech => memtech,
hindex => 3, haddr => 16#400#, hmask => 16#C00#, ioaddr => 1,
pwron => CFG_DDR2SP_INIT, MHz => BOARD_FREQ/1000,
clkmul => CFG_DDR2SP_FREQ/10, clkdiv => BOARD_FREQ/10000,
ahbfreq => CPU_FREQ/1000, col => CFG_DDR2SP_COL,
Mbyte => CFG_DDR2SP_SIZE, ddrbits => 64, readdly => 1,
ddelayb0 => CFG_DDR2SP_DELAY0, ddelayb1 => CFG_DDR2SP_DELAY1,
ddelayb2 => CFG_DDR2SP_DELAY2, ddelayb3 => CFG_DDR2SP_DELAY3,
ddelayb4 => CFG_DDR2SP_DELAY4, ddelayb5 => CFG_DDR2SP_DELAY5,
ddelayb6 => CFG_DDR2SP_DELAY6, ddelayb7 => CFG_DDR2SP_DELAY7,
numidelctrl => 3, norefclk => 1, odten => 1, dqsse => 1)
port map ( rst_ddr => resetn, rst_ahb => rstn, clk_ddr => clk, clk_ahb => clkm, clkref200 => gnd(0),
lock => lock, clkddro => clkml, clkddri => clkml, ahbsi => ahbsi, ahbso => ahbso(3),
ddr_clk => ddr_clkv, ddr_clkb => ddr_clkbv, ddr_clk_fb => gnd(0), ddr_cke => ddr_ckev,
ddr_csb => ddr_csbv, ddr_web => ddr_web, ddr_rasb => ddr_rasb, ddr_casb => ddr_casb,
ddr_dm => ddr_dm, ddr_dqs => ddr_dqs, ddr_dqsn => open, ddr_ad => ddr_ad, ddr_ba => ddr_ba,
ddr_dq => ddr_dq, ddr_odt => ddr_odt);
ddr_clk <= ddr_clkv(2 downto 0); ddr_clkb <= ddr_clkbv(2 downto 0);
ddr_cke <= ddr_ckev(1 downto 0); ddr_csb <= ddr_csbv(1 downto 0);
end generate;
noddr : if (CFG_DDR2SP = 0) generate
ddr_cke <= (others => '0'); ddr_csb <= (others => '1'); lock <= '1';
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth1 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(hindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 11, paddr => 11, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 18,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
apbi => apbi, apbo => apbo(11), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (phy_mii_data, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : inpad generic map (tech => padtech)
port map (phy_tx_clk, ethi.tx_clk);
erxc_pad : inpad generic map (tech => padtech)
port map (phy_rx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 8)
port map (phy_rx_data, ethi.rxd(7 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (phy_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (phy_rx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (phy_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (phy_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 8)
port map (phy_tx_data, etho.txd(7 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( phy_tx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (phy_tx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (phy_mii_clk, etho.mdc);
end generate;
----------------------------------------------------------------------
--- APB Bridge and various peripherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
ua1 : if CFG_UART1_ENABLE = 1 generate
uart1 : ft245uart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart)
port map (rstn, clkm, apbi, apbo(1), ft245i, ft245o);
ft245_vbdrive <= (others => ft245o.oen);
ft245_data_pad : iopadvv generic map (width => 8, tech => padtech)
port map (ft245_data, ft245o.wrdata, ft245_vbdrive, ft245i.rddata);
ft245_rdn_pad : outpad generic map (tech => padtech)
port map (ft245_rdn, ft245o.rdn);
ft245_wr_pad : outpad generic map (tech => padtech)
port map (ft245_wr, ft245o.wr);
ft245_rxfn_pad : inpad generic map (tech => padtech)
port map (ft245_rxfn, ft245i.rxfn);
ft245_txen_pad : inpad generic map (tech => padtech)
port map (ft245_txen, ft245i.txen);
ft245_pwrenn_pad : inpad generic map (tech => padtech)
port map (ft245_pwrenn, ft245i.pwrenn);
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti <= gpti_dhalt_drive(dsuo.tstop);
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 5, paddr => 5, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(5),
gpioi => gpioi, gpioo => gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ,
pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(7));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-- nap0 : for i in 6 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 7 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Altera EP2SGX90 SSRAM/DDR Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-3.0 | c238751b2d8ac37b3cd641858c85927b | 0.549822 | 3.657032 | false | false | false | false |
yishinli/emc2 | src/hal/drivers/m5i20/hostmot5_src/hostmot5-8e.vhd | 1 | 25,600 | library IEEE;
use IEEE.std_logic_1164.all; -- defines std_logic types
-- 8 axis version with 24 I/O bits
entity HostMot5_8 is
port
(
LRD: in STD_LOGIC;
LWR: in STD_LOGIC;
LW_R: in STD_LOGIC;
ALE: in STD_LOGIC;
ADS: in STD_LOGIC;
BLAST: in STD_LOGIC;
WAITO: in STD_LOGIC;
LOCKO: in STD_LOGIC;
CS0: in STD_LOGIC;
CS1: in STD_LOGIC;
READY: out STD_LOGIC;
INT: out STD_LOGIC;
LAD: inout STD_LOGIC_VECTOR (31 downto 0); -- data/address bus
LA: in STD_LOGIC_VECTOR (8 downto 2); -- non-muxed address bus
lBE: in STD_LOGIC_VECTOR (3 downto 0); -- byte enables
SYNCLK: in STD_LOGIC;
LCLK: in STD_LOGIC;
-- I/O signals
A: in STD_LOGIC_VECTOR (7 downto 0);
B: in STD_LOGIC_VECTOR (7 downto 0);
IDX: in STD_LOGIC_VECTOR (7 downto 0);
PWM: inout STD_LOGIC_VECTOR (7 downto 0);
ENA: out STD_LOGIC_VECTOR (7 downto 0);
DIR: inout STD_LOGIC_VECTOR (7 downto 0);
IOBITSA: inout STD_LOGIC_VECTOR (23 downto 0);
-- IOBITSB: inout STD_LOGIC_VECTOR (23 downto 0);
-- led bits
LEDS: out STD_LOGIC_VECTOR(7 downto 0)
);
end HostMot5_8; -- for 5I20 or 4I65
architecture dataflow of Hostmot5_8 is
alias BLE: STD_LOGIC is LBE(0); -- 16 bit mode
alias BHE: STD_LOGIC is LBE(3); -- 16 bit mode
alias LA1: STD_LOGIC is LBE(1); -- 8/16 bit mode
alias LA0: STD_LOGIC is LBE(0); -- 8 bit mode
-- misc global signals --
signal D: STD_LOGIC_VECTOR (31 downto 0); -- internal data bus
signal LatchedA: STD_LOGIC_VECTOR (15 downto 0);
signal LatchedLBE: STD_LOGIC_VECTOR (3 downto 0);
signal PreFastRead: STD_LOGIC;
signal FastRead: STD_LOGIC;
-- Version specific constants --
constant counters :integer := 8;
constant HMID : STD_LOGIC_VECTOR (31 downto 0) := x"AA010008"; -- MSW = rev 1, LSW = 4 axis
constant MasterClock : STD_LOGIC_VECTOR (31 downto 0) := x"01FCA055"; -- = 33.3333 MHz
-- misc global signals --
signal CardSelect: STD_LOGIC; -- card select decode
signal LEDView: STD_LOGIC_VECTOR (7 downto 0); -- index register
-- irq related signals
signal IRQSource: STD_LOGIC;
signal IRQLatch: STD_LOGIC;
signal IRQMask: STD_LOGIC;
signal MissedIRQ: STD_LOGIC;
signal StopOnMissedIRQ: STD_LOGIC;
signal ClearMissedIRQ: STD_LOGIC;
signal LatchOnInterrupt: STD_LOGIC;
-- timeout related signals
signal ReloadWDCmd: STD_LOGIC;
signal StopOnTimeout: STD_LOGIC;
signal WDTimeOut: STD_LOGIC;
-- LEDView and id reg signals
signal LoadLEDViewCmd: STD_LOGIC;
signal ReadLEDViewCmd: STD_LOGIC;
signal Enasigs :STD_LOGIC_VECTOR (counters-1 downto 0);
signal IDSel: STD_LOGIC;
signal ReadIDCmd: STD_LOGIC;
signal MCSel: STD_LOGIC;
signal ReadMCCmd: STD_LOGIC;
-- irqdiv reg signals
signal ReadIRQDivCmd: STD_LOGIC;
signal LoadIRQDivCmd: STD_LOGIC;
signal ClearIRQCmd: STD_LOGIC;
-- irq sel reg signals
signal loadGCRCmd: STD_LOGIC;
signal LoadGMRCmd: STD_LOGIC;
signal ReadGMRCmd: STD_LOGIC;
-- timeout reg signals
signal loadTimeoutCmd: STD_LOGIC;
signal ReadTimeoutCmd: STD_LOGIC;
signal ReadTimerCmd: STD_LOGIC;
-- phase accumulator signals
signal ReadPhaseCmd: STD_LOGIC;
signal LoadPhaseCmd: STD_LOGIC;
-- counter signals --
signal CounterRead: STD_LOGIC_VECTOR (counters-1 downto 0); -- read counter
signal GlobalCounterEnable: STD_LOGIC; -- enable counting
signal GlobalCountLatchcmd: STD_LOGIC; -- command to latch counter value
signal GlobalCountLatch: STD_LOGIC; -- command + irq generated latch count
signal CountLatchEdge1: STD_LOGIC;
signal CountLatchEdge2: STD_LOGIC;
signal CCRLoadCmds: STD_LOGIC_VECTOR (counters-1 downto 0); -- counter control reg loads
signal CCRReadCmds: STD_LOGIC_VECTOR (counters-1 downto 0); -- counter control reg reads
signal GlobalCounterClear: STD_LOGIC; -- clear counter
-- secondary counter signals --
signal SCounterRead: STD_LOGIC_VECTOR (counters-1 downto 0); -- read counter
signal SCCRLoadCmds: STD_LOGIC_VECTOR (counters-1 downto 0); -- counter control reg loads
signal SCCRReadCmds: STD_LOGIC_VECTOR (counters-1 downto 0); -- counter control reg reads
-- pwm generator signals --
signal RefCountBus: STD_LOGIC_VECTOR (9 downto 0);
signal LoadPWM: STD_LOGIC_VECTOR (counters-1 downto 0);
signal ReadPWM: STD_LOGIC_VECTOR (counters-1 downto 0);
signal PCRLoadCmds: STD_LOGIC_VECTOR (counters-1 downto 0);
signal PCRReadCmds: STD_LOGIC_VECTOR (counters-1 downto 0);
signal GlobalPWMEnable: STD_LOGIC;
signal GlobalClearPWM: STD_LOGIC;
signal GlobalClearPWMCmd: STD_LOGIC;
signal StopPWM: STD_LOGIC;
-- misc i/o signals
signal PortASel: STD_LOGIC;
signal DDRASel: STD_LOGIC;
signal LoadPortA: STD_LOGIC;
signal LoadDDRA: STD_LOGIC;
signal ReadDDRA: STD_LOGIC;
signal ReadPortA: STD_LOGIC;
signal PortBSel: STD_LOGIC;
signal DDRBSel: STD_LOGIC;
signal LoadPortB: STD_LOGIC;
signal LoadDDRB: STD_LOGIC;
signal ReadDDRB: STD_LOGIC;
signal ReadPortB: STD_LOGIC;
-- decodes --
signal LEDViewSel: STD_LOGIC;
signal IndexSel: STD_LOGIC;
signal GCRSel: STD_LOGIC;
signal GMRSel: STD_LOGIC;
signal CCRSel: STD_LOGIC;
signal SCCRSel: STD_LOGIC;
signal PCRSel: STD_LOGIC;
signal TimeOutSel: STD_LOGIC;
signal TimerSel: STD_LOGIC;
signal IRQDIVSel: STD_LOGIC;
signal PWMValSel: STD_LOGIC;
signal PhaseSel: STD_LOGIC;
signal CounterSel: STD_LOGIC;
signal SCounterSel: STD_LOGIC;
function OneOfEightDecode(ena : std_logic; dec : std_logic_vector(2 downto 0)) return std_logic_vector is
variable result : std_logic_vector(counters-1 downto 0);
begin
if ena = '1' then
case dec is
when "000" => result := "00000001";
when "001" => result := "00000010";
when "010" => result := "00000100";
when "011" => result := "00001000";
when "100" => result := "00010000";
when "101" => result := "00100000";
when "110" => result := "01000000";
when "111" => result := "10000000";
when others => result := "00000000";
end case;
else
result := "00000000";
end if;
return result;
end OneOfEightDecode;
function OneOfEightMux(sel: std_logic_vector (2 downto 0); input: std_logic_vector(counters-1 downto 0)) return std_logic is
variable result : std_logic;
begin
case sel is
when "000" => result := input(0);
when "001" => result := input(1);
when "010" => result := input(2);
when "011" => result := input(3);
when "100" => result := input(4);
when "101" => result := input(5);
when "110" => result := input(6);
when "111" => result := input(7);
when others => result := '0';
end case;
return result;
end OneOfEightMux;
component indexreg
port (
clk: in STD_LOGIC;
ibus: in STD_LOGIC_VECTOR (15 downto 0);
obus: out STD_LOGIC_VECTOR (15 downto 0);
loadindex: in STD_LOGIC;
readindex: in STD_LOGIC;
index: out STD_LOGIC_VECTOR (7 downto 0)
);
end component;
component counter
port (
obus: out STD_LOGIC_VECTOR (31 downto 0);
ibus: in STD_LOGIC_VECTOR (31 downto 0);
quada: in STD_LOGIC;
quadb: in STD_LOGIC;
index: in STD_LOGIC;
ccrloadcmd: in STD_LOGIC;
ccrreadcmd: in STD_LOGIC;
countoutreadcmd: in STD_LOGIC;
countlatchcmd: in STD_LOGIC;
countclearcmd: in STD_LOGIC;
countenable: in STD_LOGIC;
indexmask: in STD_LOGIC;
nads: in STD_LOGIC;
clk: in STD_LOGIC
);
end component;
component pwmgen
port (
clk: in STD_LOGIC;
refcount: in STD_LOGIC_VECTOR (9 downto 0);
ibus: in STD_LOGIC_VECTOR (15 downto 0);
obus: out STD_LOGIC_VECTOR (15 downto 0);
loadpwmval: in STD_LOGIC;
readpwmval: in STD_LOGIC;
clearpwmval: in STD_LOGIC;
pcrloadcmd: STD_LOGIC;
pcrreadcmd: STD_LOGIC;
pwmout: out STD_LOGIC;
dirio: inout STD_LOGIC;
enablein: in STD_LOGIC;
enableout: out STD_LOGIC
);
end component pwmgen;
component pwmref is
port (
clk: in STD_LOGIC;
refcount: out STD_LOGIC_VECTOR (9 downto 0);
irqgen: out STD_LOGIC;
ibus: in STD_LOGIC_VECTOR (15 downto 0);
obus: out STD_LOGIC_VECTOR (15 downto 0);
irqdivload: in STD_LOGIC;
irqdivread: in STD_LOGIC;
phaseload: in STD_LOGIC;
phaseread: in STD_LOGIC
);
end component pwmref;
component globalcontrolreg is
port (
clk: in STD_LOGIC;
ibus: in STD_LOGIC_VECTOR (15 downto 0);
reset: in STD_LOGIC;
loadgcr: in STD_LOGIC;
ctrclear: out STD_LOGIC;
ctrlatch: out STD_LOGIC;
pwmclear: out STD_LOGIC;
irqclear: out STD_LOGIC;
reloadwd: out STD_LOGIC
);
end component globalcontrolreg;
component globalmodereg is
port (
clk: in STD_LOGIC;
ibus: in STD_LOGIC_VECTOR (15 downto 0);
obus: out STD_LOGIC_VECTOR (15 downto 0);
reset: in STD_LOGIC;
loadglobalmode: in STD_LOGIC;
readglobalmode: in STD_LOGIC;
ctrena: out STD_LOGIC;
pwmena: out STD_LOGIC;
clearpwmena: in STD_LOGIC;
loi: out STD_LOGIC;
som: out STD_LOGIC;
sot: out STD_LOGIC;
miout: out STD_LOGIC;
miin: in STD_LOGIC;
irqmask: out STD_LOGIC;
irqstatus: in STD_LOGIC
);
end component globalmodereg;
component WordPR24 is
port (
clear: in STD_LOGIC;
clk: in STD_LOGIC;
ibus: in STD_LOGIC_VECTOR (23 downto 0);
obus: out STD_LOGIC_VECTOR (23 downto 0);
loadport: in STD_LOGIC;
loadddr: in STD_LOGIC;
readddr: in STD_LOGIC;
portdata: out STD_LOGIC_VECTOR (23 downto 0)
);
end component WordPR24;
component Word24RB is
Port (
obus: out STD_LOGIC_VECTOR (23 downto 0);
readport: in STD_LOGIC;
portdata: in STD_LOGIC_VECTOR (23 downto 0) );
end component Word24RB;
component Timeout is
Port ( clk : in std_logic;
ibus : in std_logic_vector(15 downto 0);
obus : out std_logic_vector(15 downto 0);
timeoutload : in std_logic;
timeoutread : in std_logic;
timerread : in std_logic;
reload : in std_logic;
timerz : out std_logic);
end component Timeout;
component idreadback is
Generic ( id : std_logic_vector(31 downto 0);
mc : std_logic_vector(31 downto 0));
Port ( readid : in std_logic;
readmc : in std_logic;
obus : out std_logic_vector(31 downto 0));
end component idreadback;
begin
makecounters: for i in 0 to (counters -1) generate
counterx: counter port map (
obus => D,
ibus => LAD,
quada => A(i),
quadb => B(i),
index => Idx(i),
ccrloadcmd => CCRLoadCmds(i),
ccrreadcmd => CCRReadCmds(i),
countoutreadcmd => CounterRead(i),
countlatchcmd => GlobalCountLatch,
countclearcmd => GlobalCounterClear,
countenable => GlobalCounterEnable,
indexmask => IOBITSA(16+i),
nads => ADS,
clk => LClk
);
end generate;
makescounters: for i in 0 to 3 generate
counterx: counter port map (
obus => D,
ibus => LAD,
quada => IOBITSA((i*4)),
quadb => IOBITSA((i*4)+1),
index => IOBITSA((i*4)+2),
ccrloadcmd => SCCRLoadCmds(i),
ccrreadcmd => SCCRReadCmds(i),
countoutreadcmd => SCounterRead(i),
countlatchcmd => GlobalCountLatch,
countclearcmd => GlobalCounterClear,
countenable => GlobalCounterEnable,
indexmask => IOBITSA((i*4)+3),
nads => ADS,
clk => LClk
);
end generate;
makepwmgen: for i in 0 to (counters -1) generate
pwmgenx: pwmgen port map (
clk => LClk,
refcount => RefCountBus,
ibus => LAD(15 downto 0),
obus => D(15 downto 0),
loadpwmval => LoadPWM(i),
readpwmval => ReadPWM(i),
clearpwmval => GlobalClearPWM,
pcrloadcmd => PCRLoadCmds(i),
pcrreadcmd => PCRReadCmds(i),
pwmout => PWM(i),
dirio => Dir(i),
enablein => GlobalPWMEnable,
enableout =>EnaSigs(i)
);
end generate;
oporta: WordPR24 port map (
clear => '0',
clk => LClk,
ibus => LAD(23 downto 0),
obus => D(23 downto 0),
loadport => LoadPortA,
loadddr => LoadDDRA,
readddr => ReadDDRA,
portdata => IOBITSA
);
iporta: Word24RB port map (
obus => D(23 downto 0),
readport => ReadPortA,
portdata => IOBITSA
);
-- oportb: WordPR24 port map (
-- clear => '0',
-- clk => LClk,
-- ibus => LAD(23 downto 0),
-- obus => D(23 downto 0),
-- loadport => LoadPortB,
-- loadddr => LoadDDRB,
-- readddr => ReadDDRB,
-- portdata => IOBITSB
-- );
-- iportb: Word24RB port map (
-- obus => D(23 downto 0),
-- readport => ReadPortB,
-- portdata => IOBitsB
-- );
pwmrefcount: pwmref port map (
clk => LClk,
refcount => RefCountBus,
irqgen => IRQSource,
ibus => LAD(15 downto 0),
obus => D(15 downto 0),
irqdivload => LoadIRQDivCmd,
irqdivread => ReadIRQDivCmd,
phaseload => LoadPhaseCmd,
phaseread => ReadPhaseCmd
);
gLedreg: indexreg port map (
clk => LClk,
ibus => LAD(15 downto 0),
obus => D(15 downto 0),
loadindex => LoadLEDViewCmd,
readindex => ReadLEDViewCmd,
index => LEDView
);
ggcontrolreg: globalcontrolreg port map (
clk => LClk,
ibus => LAD(15 downto 0),
reset => '0',
loadgcr => LoadGCRCmd,
ctrclear => GlobalCounterClear,
ctrlatch => GlobalCountLatchCmd,
pwmclear => GlobalClearPWMCmd,
irqclear => ClearIRQCmd,
reloadwd => ReloadWDCmd
);
gglobalmodereg: globalmodereg port map (
clk => LClk,
ibus => LAD(15 downto 0),
obus => D(15 downto 0),
reset => '0',
loadglobalmode => loadGMRCmd,
readglobalmode => ReadGMRCmd,
ctrena => GlobalCounterEnable,
pwmena => GlobalPWMEnable,
clearpwmena => StopPWM,
loi => LatchOnInterrupt,
som => StopOnMissedIRQ,
sot => StopOnTimeout,
miout => ClearMissedIRQ,
miin => MissedIRQ,
irqmask => IRQMask,
irqstatus => IRQLatch
);
atimeout: timeout port map (
clk => LClk,
ibus => LAD(15 downto 0),
obus => D(15 downto 0),
timeoutload => loadTimeOutCmd,
timeoutread => ReadTimeOutCmd,
timerread => ReadTimerCmd,
reload => ReLoadWDCmd,
timerz => WDTimeout
);
aidreadback: idreadback
generic map (
id => HMID,
mc => MasterClock
)
port map(
readid => ReadIDCmd,
readmc => ReadMCCmd,
obus => D
);
LADDrivers: process (D,FastRead)
begin
if FastRead ='1' then
LAD <= D;
else
LAD <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
end if;
end process LADDrivers;
AddressLatch: process (lclk)
begin
if lclk'event and LClk = '1' then
if ADS = '0' then
LatchedA <= LAD(15 downto 0);
LatchedLBE <= LBE;
end if;
end if;
end process AddressLatch;
-- we generate an early read from ADS and LR_W
-- since the 10 nS LRD delay and 5 nS setup time
-- only give us 15 nS to provide data to the PLX chip
MakeFastRead: process (lclk,PreFastread,LRD)
begin
if lclk'event and LClk = '1' then
if ADS = '0' and LW_R = '0'then
PreFastRead <= '1';
else
PreFastRead <= '0';
end if;
end if;
FastRead <= PreFastRead or (not LRD);
end process MakeFastRead;
Decode: process (LatchedA)
begin
if LatchedA(7 downto 5) = "000" then -- 32 bit access
CounterSel <= '1';
else
CounterSel <= '0';
end if;
if LatchedA(7 downto 5) = "001" then -- 32 bit access
SCounterSel <= '1';
else
SCounterSel <= '0';
end if;
if LatchedA(7 downto 4) = "0100" then -- 16 bit access
CCRSel <= '1';
else
CCRSel <= '0';
end if;
if LatchedA(7 downto 4) = "0101" then -- 16 bit access
SCCRSel <= '1';
else
SCCRSel <= '0';
end if;
if LatchedA(7 downto 5) = "011" then -- 16 bit access
PWMValSel <= '1';
else
PWMValSel <= '0';
end if;
if LatchedA(7 downto 5) = "100" then -- 16 bit access
PCRSel <= '1';
else
PCRSel <= '0';
end if;
if LatchedA(7 downto 2) = "101000" then -- 32 bit access
PortASel <= '1';
else
PortASel <= '0';
end if;
if LatchedA(7 downto 2) = "101001" then -- 32 bit access
DDRASel <= '1';
else
DDRASel <= '0';
end if;
-- if LatchedA(7 downto 2) = "101010" then -- 32 bit access
-- PortBSel <= '1';
-- else
-- PortBSel <= '0';
-- end if;
-- if LatchedA(7 downto 2) = "101011" then -- 32 bit access
-- DDRBSel <= '1';
-- else
-- DDRBSel <= '0';
-- end if;
if LatchedA(7 downto 2) = "110100" then -- 32 bit access D0
IDSel <= '1';
else
IDSel <= '0';
end if;
if LatchedA(7 downto 2) = "110101" then -- 32 bit access D4
MCSel <= '1';
else
MCSel <= '0';
end if;
if LatchedA(7 downto 1) = "1100000" then -- 16 bit access
GCRSel <= '1';
else
GCRSel <= '0';
end if;
if LatchedA(7 downto 1) = "1100001" then -- 16 bit access
GMRSel <= '1';
else
GMRSel <= '0';
end if;
if LatchedA(7 downto 1) = "1100010"then -- 16 bit access
IRQDivSel <= '1';
else
IRQDivSel <= '0';
end if;
if LatchedA(7 downto 1) = "1100011"then -- 16 bit access
PhaseSel <= '1';
else
PhaseSel <= '0';
end if;
if LatchedA(7 downto 1) = "1100100" then -- 16 bit access
TimeOutSel <= '1';
else
TimeOutSel <= '0';
end if;
if LatchedA(7 downto 1) = "1100101" then -- 16 bit access
TimerSel <= '1';
else
TimerSel <= '0';
end if;
if LatchedA(7 downto 1) = "1100110" then -- 16 bit access
LEDViewSel <= '1';
else
LEDViewSel <= '0';
end if;
end process;
SigsOut: process (EnaSigs)
begin
Ena <= EnaSigs;
end process;
CounterDecode: process (CounterSel, Fastread, LatchedA)
begin
if FastRead = '1' then
CounterRead <= OneOfEightDecode(CounterSel,LatchedA(4 downto 2));
else
CounterRead <= (others => '0');
end if;
end process;
SCounterDecode: process (SCounterSel, Fastread, LatchedA)
begin
if FastRead = '1' then
SCounterRead <= OneOfEightDecode(SCounterSel,LatchedA(4 downto 2));
else
SCounterRead <= (others => '0');
end if;
end process;
CCRegs: process (CCRSel, FastRead, LWR, LatchedA)
begin
if FastRead = '1' then
CCRReadCmds <= OneOfEightDecode(CCRSel,LatchedA(3 downto 1));
else
CCRReadCmds <= (others => '0');
end if;
if LWR = '0' then
CCRLoadCmds <= OneOfEightDecode(CCRSel,LatchedA(3 downto 1));
else
CCRLoadCmds <= (others => '0');
end if;
end process;
SCCRegs: process (SCCRSel, FastRead, LWR, LatchedA)
begin
if FastRead = '1' then
SCCRReadCmds <= OneOfEightDecode(SCCRSel,LatchedA(3 downto 1));
else
SCCRReadCmds <= (others => '0');
end if;
if LWR = '0' then
SCCRLoadCmds <= OneOfEightDecode(SCCRSel,LatchedA(3 downto 1));
else
SCCRLoadCmds <= (others => '0');
end if;
end process;
PWMdecode: process (PWMValSel,Fastread, LWR, LatchedA)
begin
if FastRead = '1' then
ReadPWM <= OneOfEightDecode(PWMValSel,LatchedA(3 downto 1));
else
ReadPWM <= (others => '0');
end if;
if LWR = '0' then
LoadPWM <= OneOfEightDecode(PWMValSel,LatchedA(3 downto 1));
else
LoadPWM <= (others => '0');
end if;
end process;
PCRegs: process (PCRSel,Fastread, LWR, LatchedA)
begin
if FastRead = '1' then
PCRReadCmds <= OneOfEightDecode(PCRSel,LatchedA(3 downto 1));
else
PCRReadCmds <= (others => '0');
end if;
if LWR = '0' then
PCRLoadCmds <= OneOfEightDecode(PCRSel,LatchedA(3 downto 1));
else
PCRLoadCmds <= (others => '0');
end if;
end process;
PortADecode: process (PortASel,FastRead,LWR)
begin
if PortASel = '1' and LWR = '0' then
LoadPortA <= '1';
else
LoadPortA <= '0';
end if;
if PortASel = '1' and FastRead = '1' then
ReadPortA <= '1';
else
ReadPortA <= '0';
end if;
end process PortADecode;
DDRADecode: process (DDRASel,FastRead,LWR)
begin
if DDRASel = '1' and LWR = '0' then
LoadDDRA <= '1';
else
LoadDDRA <= '0';
end if;
if DDRASel = '1' and FastRead = '1' then
ReadDDRA <= '1';
else
ReadDDRA <= '0';
end if;
end process DDRADecode;
-- PortBDecode: process (PortBSel,FastRead,LWR)
-- begin
-- if PortBSel = '1' and LWR = '0' then
-- LoadPortB <= '1';
-- else
-- LoadPortB <= '0';
-- end if;
-- if PortBSel = '1' and FastRead = '1' then
-- ReadPortB <= '1';
-- else
-- ReadPortB <= '0';
-- end if;
-- end process PortBDecode;
-- DDRBDecode: process (DDRBSel,FastRead,LWR)
-- begin
-- if DDRBSel = '1' and LWR = '0' then
-- LoadDDRB <= '1';
-- else
-- LoadDDRB <= '0';
-- end if;
-- if DDRBSel = '1' and FastRead = '1' then
-- ReadDDRB <= '1';
-- else
-- ReadDDRB <= '0';
-- end if;
-- end process DDRBDecode;
GCRDecode: process (GCRSel,LWR)
begin
if GCRSel = '1' and LWR = '0' then
LoadGCRCmd <= '1';
else
LoadGCRCmd <= '0';
end if;
end process GCRDecode;
GMRDecode: process (GMRSel,FastRead,LWR)
begin
if GMRSel = '1' and LWR = '0' then
LoadGMRCmd <= '1';
else
LoadGMRCmd <= '0';
end if;
if GMRSel = '1' and FastRead = '1' then
ReadGMRCmd <= '1';
else
ReadGMRCmd <= '0';
end if;
end process GMRDecode;
TimeOutDecode: process (TimeOutSel,FastRead,LWR)
begin
if TimeoutSel = '1' and LWR = '0' then
LoadTimeOutCmd <= '1';
else
LoadTimeOutCmd <= '0';
end if;
if TimeOutSel = '1' and FastRead = '1' then
ReadTimeOutCmd <= '1';
else
ReadTimeOutCmd <= '0';
end if;
end process TimeOutDecode;
TimerDecode: process (TimerSel,FastRead,LWR)
begin
if TimerSel = '1' and FastRead = '1' then
ReadTimerCmd <= '1';
else
ReadTimerCmd <= '0';
end if;
end process TimerDecode;
LEDViewDecode: process (LedViewSel,FastRead,LWR)
begin
if LEDViewSel = '1' and LWR = '0' then
LoadLEDViewCmd <= '1';
else
LoadLEDViewCmd <= '0';
end if;
if LEDViewSel = '1' and FastRead= '1' then
ReadLEDViewCmd <= '1';
else
ReadLEDViewCmd <= '0';
end if;
end process LEDViewDecode;
IRQDivDecode: process (IRQDivSel,FastRead,LWR)
begin
if IRQDivSel = '1' and LWR = '0' then
LoadIRQDivCmd <= '1';
else
LoadIRQDivCmd <= '0';
end if;
if IRQDivSel = '1' and FastRead = '1' then
ReadIRQDivCmd <= '1';
else
ReadIRQDivCmd <= '0';
end if;
end process IrqDivDecode;
PhaseDecode: process (PhaseSel,FastRead,LWR)
begin
if PhaseSel = '1' and LWR = '0' then
LoadPhaseCmd <= '1';
else
LoadPhaseCmd <= '0';
end if;
if PhaseSel = '1' and FastRead = '1' then
ReadPhaseCmd <= '1';
else
ReadPhaseCmd <= '0';
end if;
end process PhaseDecode;
IDDecode: process (IDSel,FastRead)
begin
if IDSel = '1' and FastRead = '1' then
ReadIDCmd <= '1';
else
ReadIDCmd <= '0';
end if;
end process IDDecode;
MCDecode: process (MCSel,FastRead)
begin
if MCSel = '1' and FastRead = '1' then
ReadMCCmd <= '1';
else
ReadMCCmd <= '0';
end if;
end process MCDecode;
irqlogic: process (CardSelect,
IRQSource,
IrqLatch,
ClearMissedIRQ,
MissedIRQ,
StopOnMissedIRQ,
LatchOnInterrupt,
GlobalCountLatchCmd,
GlobalClearPWMCmd,
ClearIRQCmd)
begin
if IrqSource'event and IRQsource = '1' then
IRQLatch <= '1';
if IRQLatch = '1' then -- if IRQLatch is set and we get the next interrupt
MissedIRQ <= '1'; -- set Missed IRQ latch
end if;
end if;
if LClk'event and LClk = '1' then
if ((IRQLatch = '1') and (LatchOnInterrupt = '1')) or (GlobalCountLatchCmd = '1') then
CountLatchEdge1 <= '1';
else
CountLatchEdge1 <= '0';
end if;
CountLatchEdge2 <= CountLatchEdge1;
if CountLatchEdge2 = '0' and CountLatchEdge1 = '1' then
GlobalCountLatch <= '1';
else
GlobalCountLatch <= '0';
end if;
end if;
if ClearMissedIRQ = '1' then
MissedIRQ <= '0';
end if;
if ((MissedIRQ = '1') and (StopOnMissedIRQ = '1')) or
((WDTimeOut = '1') and (StopOnTimeout = '1')) then
StopPWM <= '1';
else
StopPWM <= '0';
end if;
if (StopPWM = '1') or (GlobalClearPWMCmd = '1') then -- either stop on pwm or global clear reset pwm gens
GlobalClearPWM <= '1';
else
GlobalClearPWM <= '0';
end if;
if ClearIRQCmd = '1' then -- clear IRQ
IRQLatch <= '0';
end if;
Int <= not (IRQLatch and IRQMask); -- drive our (active low) interrupt pin
Ready <= '0'; -- We're always ready
end process;
LEDDrive: process (A,B,Idx,Dir,PWM,IRQLatch,LedView)
begin
LEDS(7) <= not IRQLatch;
LEDS(6) <= not OneOfEightMux(LEDView(2 downto 0),A);
LEDS(5) <= not OneOfEightMux(LEDView(2 downto 0),B);
LEDS(4) <= not OneOfEightMux(LEDView(2 downto 0),Idx);
LEDS(3) <= not OneOfEightMux(LEDView(2 downto 0),Dir);
LEDS(2) <= not OneOfEightMux(LEDView(2 downto 0),PWM);
LEDS(1) <= OneOfEightMux(LEDView(2 downto 0),EnaSigs);
LEDS(0) <= not WDTimeout;
end process leddrive;
end dataflow;
| lgpl-2.1 | 8b689a9ebef263deab86c518ef108fc7 | 0.60875 | 2.932417 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/eth/core/greth_rx.vhd | 1 | 11,685 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: greth_rx
-- File: greth_rx.vhd
-- Author: Marko Isomaki
-- Description: Ethernet receiver
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
library eth;
use eth.grethpkg.all;
entity greth_rx is
generic(
nsync : integer range 1 to 2 := 2;
rmii : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
maxsize : integer := 1500;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxi : in host_rx_type;
rxo : out rx_host_type
);
attribute sync_set_reset of rst : signal is "true";
end entity;
architecture rtl of greth_rx is
-- constant maxsize : integer := 1518;
constant maxsizerx : unsigned(15 downto 0) :=
to_unsigned(maxsize + 18, 16);
constant minsize : integer := 64;
--receiver types
type rx_state_type is (idle, wait_sfd, data1, data2, errorst, report_status,
wait_report, check_crc, discard_packet);
type rx_reg_type is record
er : std_ulogic;
en : std_ulogic;
rxd : std_logic_vector(3 downto 0);
rxdp : std_logic_vector(3 downto 0);
crc : std_logic_vector(31 downto 0);
sync_start : std_ulogic;
gotframe : std_ulogic;
start : std_ulogic;
write : std_ulogic;
done : std_ulogic;
odd_nibble : std_ulogic;
lentype : std_logic_vector(15 downto 0);
ltfound : std_ulogic;
byte_count : std_logic_vector(10 downto 0);
data : std_logic_vector(31 downto 0);
dataout : std_logic_vector(31 downto 0);
rx_state : rx_state_type;
status : std_logic_vector(3 downto 0);
write_ack : std_logic_vector(nsync-1 downto 0);
done_ack : std_logic_vector(nsync downto 0);
rxen : std_logic_vector(1 downto 0);
got4b : std_ulogic;
mcasthash : std_logic_vector(5 downto 0);
hashlock : std_ulogic;
--rmii
enold : std_ulogic;
act : std_ulogic;
dv : std_ulogic;
cnt : std_logic_vector(3 downto 0);
rxd2 : std_logic_vector(1 downto 0);
speed : std_logic_vector(1 downto 0);
zero : std_ulogic;
end record;
--receiver signals
signal r, rin : rx_reg_type;
signal rxrst : std_ulogic;
signal vcc : std_ulogic;
-- attribute sync_set_reset : string;
attribute sync_set_reset of rxrst : signal is "true";
begin
vcc <= '1';
rx_rst : eth_rstgen
port map(rst, clk, vcc, rxrst, open);
rx : process(rxrst, r, rxi) is
variable v : rx_reg_type;
variable index : integer range 0 to 3;
variable crc_en : std_ulogic;
variable write_req : std_ulogic;
variable write_ack : std_ulogic;
variable done_ack : std_ulogic;
variable er : std_ulogic;
variable dv : std_ulogic;
variable act : std_ulogic;
variable rxd : std_logic_vector(3 downto 0);
begin
v := r; v.rxd := rxi.rxd(3 downto 0);
if rmii = 0 then
v.en := rxi.rx_dv;
else
v.en := rxi.rx_crs;
end if;
v.er := rxi.rx_er; write_req := '0'; crc_en := '0';
index := conv_integer(r.byte_count(1 downto 0));
--synchronization
v.rxen(1) := r.rxen(0); v.rxen(0) := rxi.enable;
v.write_ack(0) := rxi.writeack;
v.done_ack(0) := rxi.doneack;
if nsync = 2 then
v.write_ack(1) := r.write_ack(0);
v.done_ack(1) := r.done_ack(0);
end if;
write_ack := not (r.write xor r.write_ack(nsync-1));
done_ack := not (r.done xor r.done_ack(nsync-1));
--rmii/mii
if rmii = 0 then
er := r.er; dv := r.en; act := r.en; rxd := r.rxd;
else
--sync
v.speed(1) := r.speed(0); v.speed(0) := rxi.speed;
rxd := r.rxd(1 downto 0) & r.rxd2;
if r.cnt = "0000" then
v.cnt := "1001";
else
v.cnt := r.cnt - 1;
end if;
if v.cnt = "0000" then
v.zero := '1';
else
v.zero := '0';
end if;
act := r.act; er := '0';
if r.speed(1) = '0' then
if r.zero = '1' then
v.enold := r.en;
dv := r.en and r.dv;
v.dv := r.act and not r.dv;
if r.dv = '0' then
v.rxd2 := r.rxd(1 downto 0);
end if;
if (r.enold or r.en) = '0' then
v.act := '0';
end if;
else
dv := '0';
end if;
else
v.enold := r.en;
dv := r.en and r.dv;
v.dv := r.act and not r.dv;
v.rxd2 := r.rxd(1 downto 0);
if (r.enold or r.en) = '0' then
v.act := '0';
end if;
end if;
end if;
if (r.en and not r.act) = '1' then
if (rxd = "0101") and (r.speed(1) or
(not r.speed(1) and r.zero)) = '1' then
v.act := '1'; v.dv := '0'; v.rxdp := rxd;
end if;
end if;
if (dv = '1') then
v.rxdp := rxd;
end if;
if multicast = 1 then
if (r.byte_count(2 downto 0) = "110") and (r.hashlock = '0') then
v.mcasthash := r.crc(5 downto 0); v.hashlock := '1';
end if;
end if;
--fsm
case r.rx_state is
when idle =>
v.gotframe := '0'; v.status := (others => '0'); v.got4b := '0';
v.byte_count := (others => '0'); v.odd_nibble := '0';
v.ltfound := '0';
if multicast = 1 then
v.hashlock := '0';
end if;
if (dv and r.rxen(1)) = '1' then
if (rxd = "1101") and (r.rxdp = "0101") then
v.rx_state := data1; v.sync_start := not r.sync_start;
end if;
v.start := '0'; v.crc := (others => '1');
if er = '1' then v.status(2) := '1'; end if;
elsif dv = '1' then
v.rx_state := discard_packet;
end if;
when discard_packet =>
if act = '0' then v.rx_state := idle; end if;
when data1 =>
if (act and dv) = '1' then
crc_en := '1';
v.odd_nibble := not r.odd_nibble; v.rx_state := data2;
case index is
when 0 => v.data(27 downto 24) := rxd;
when 1 => v.data(19 downto 16) := rxd;
when 2 => v.data(11 downto 8) := rxd;
when 3 => v.data(3 downto 0) := rxd;
end case;
elsif act = '0' then
v.rx_state := check_crc;
end if;
if (r.byte_count(1 downto 0) = "00" and (r.start and act and dv) = '1') then
write_req := '1';
end if;
if er = '1' then v.status(2) := '1'; end if;
if conv_integer(r.byte_count) > maxsizerx then
v.rx_state := errorst; v.status(1) := '1';
v.byte_count := r.byte_count - 4;
end if;
v.got4b := v.byte_count(2) or r.got4b;
when data2 =>
if (act and dv) = '1' then
crc_en := '1';
v.odd_nibble := not r.odd_nibble; v.rx_state := data1;
v.byte_count := r.byte_count + 1; v.start := '1';
case index is
when 0 => v.data(31 downto 28) := rxd;
when 1 => v.data(23 downto 20) := rxd;
when 2 => v.data(15 downto 12) := rxd;
when 3 => v.data(7 downto 4) := rxd;
end case;
elsif act = '0' then
v.rx_state := check_crc;
end if;
if er = '1' then v.status(2) := '1'; end if;
v.got4b := v.byte_count(2) or r.got4b;
when check_crc =>
if r.crc /= X"C704DD7B" then
if r.odd_nibble = '1' then v.status(0) := '1';
else v.status(2) := '1'; end if;
end if;
if write_ack = '1' then
if r.got4b = '1' then
v.byte_count := r.byte_count - 4;
else
v.byte_count := (others => '0');
end if;
v.rx_state := report_status;
if conv_integer(r.byte_count) < minsize then
v.rx_state := wait_report; v.done := not r.done;
end if;
end if;
when errorst =>
if act = '0' then
v.rx_state := wait_report; v.done := not r.done;
v.gotframe := '1';
end if;
when report_status =>
v.done := not r.done; v.rx_state := wait_report;
v.gotframe := '1';
when wait_report =>
if done_ack = '1' then
if act = '1' then
v.rx_state := discard_packet;
else
v.rx_state := idle;
end if;
end if;
when others => null;
end case;
--write to fifo
if write_req = '1' then
if (r.status(3) or not write_ack) = '1' then
v.status(3) := '1';
else
v.dataout := r.data; v.write := not r.write;
end if;
if (r.byte_count(4 downto 2) = "100") and (r.ltfound = '0') then
v.lentype := r.data(31 downto 16) + 14; v.ltfound := '1';
end if;
end if;
if write_ack = '1' then
if rxi.writeok = '0' then v.status(3) := '1'; end if;
end if;
--crc generation
if crc_en = '1' then
v.crc := calccrc(rxd, r.crc);
end if;
if rxrst = '0' then
v.rx_state := idle; v.write := '0'; v.done := '0'; v.sync_start := '0';
v.done_ack := (others => '0');
v.gotframe := '0'; v.write_ack := (others => '0');
v.dv := '0'; v.cnt := (others => '0'); v.zero := '0';
v.byte_count := (others => '0'); v.lentype := (others => '0');
v.status := (others => '0'); v.got4b := '0'; v.odd_nibble := '0';
v.ltfound := '0';
if multicast = 1 then
v.hashlock := '0';
end if;
end if;
if rmii = 0 then
v.cnt := (others => '0'); v.zero := '0';
end if;
rin <= v;
rxo.dataout <= r.dataout;
rxo.start <= r.sync_start;
rxo.done <= r.done;
rxo.write <= r.write;
rxo.status <= r.status;
rxo.gotframe <= r.gotframe;
rxo.byte_count <= r.byte_count;
rxo.lentype <= r.lentype;
rxo.mcasthash <= r.mcasthash;
end process;
gmiimode0 : if gmiimode = 0 generate
rxregs0 : process(clk) is
begin
if rising_edge(clk) then
r <= rin;
end if;
end process;
end generate;
gmiimode1 : if gmiimode = 1 generate
rxregs1 : process(clk) is
begin
if rising_edge(clk) then
if (rxi.rx_en = '1' or rxrst = '0') then r <= rin; end if;
end if;
end process;
end generate;
end architecture;
| gpl-3.0 | cb5b552c590bcedfa16103fcc9229527 | 0.50184 | 3.249444 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/memctrl/sdmctrl.vhd | 1 | 25,539 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: sdmctrl
-- File: sdmctrl.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: SDRAM memory controller to fit with LEON2 memory controller.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.memctrl.all;
entity sdmctrl is
generic (
pindex : integer := 0;
invclk : integer := 0;
fast : integer := 0;
wprot : integer := 0;
sdbits : integer := 32;
pageburst : integer := 0;
mobile : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
sdi : in sdram_in_type;
sdo : out sdram_out_type;
apbi : in apb_slv_in_type;
wpo : in wprot_out_type;
sdmo : out sdram_mctrl_out_type
);
end;
architecture rtl of sdmctrl is
constant WPROTEN : boolean := (wprot /= 0);
constant SDINVCLK : boolean := (invclk /= 0);
constant BUS64 : boolean := (sdbits = 64);
constant PM_PD : std_logic_vector(2 downto 0) := "001";
constant PM_SR : std_logic_vector(2 downto 0) := "010";
constant PM_DPD : std_logic_vector(2 downto 0) := "101";
type mcycletype is (midle, active, leadout);
type sdcycletype is (act1, act2, act3, rd1, rd2, rd3, rd4, rd5, rd6, rd7, rd8,
wr1, wr2, wr3, wr4, wr5, sidle, sref, pd, dpd);
type icycletype is (iidle, pre, ref, lmode, emode, finish);
-- sdram configuration register
type sdram_cfg_type is record
command : std_logic_vector(2 downto 0);
csize : std_logic_vector(1 downto 0);
bsize : std_logic_vector(2 downto 0);
casdel : std_ulogic; -- CAS to data delay: 2/3 clock cycles
trfc : std_logic_vector(2 downto 0);
trp : std_ulogic; -- precharge to activate: 2/3 clock cycles
refresh : std_logic_vector(14 downto 0);
renable : std_ulogic;
pageburst : std_ulogic;
mobileen : std_logic_vector(1 downto 0); -- Mobile SD support, Mobile SD enabled
ds : std_logic_vector(3 downto 0); -- ds(1:0) (ds(3:2) used to detect update)
tcsr : std_logic_vector(3 downto 0); -- tcrs(1:0) (tcrs(3:2) used to detect update)
pasr : std_logic_vector(5 downto 0); -- pasr(2:0) (pasr(5:3) used to detect update)
pmode : std_logic_vector(2 downto 0); -- Power-Saving mode
txsr : std_logic_vector(3 downto 0); -- Exit Self Refresh timing
cke : std_ulogic; -- Clock enable
end record;
-- local registers
type reg_type is record
hready : std_ulogic;
hsel : std_ulogic;
bdrive : std_ulogic;
burst : std_ulogic;
busy : std_ulogic;
bdelay : std_ulogic;
wprothit : std_ulogic;
startsd : std_ulogic;
aload : std_ulogic;
mstate : mcycletype;
sdstate : sdcycletype;
cmstate : mcycletype;
istate : icycletype;
icnt : std_logic_vector(2 downto 0);
cfg : sdram_cfg_type;
trfc : std_logic_vector(3 downto 0);
refresh : std_logic_vector(14 downto 0);
sdcsn : std_logic_vector(1 downto 0);
sdwen : std_ulogic;
rasn : std_ulogic;
casn : std_ulogic;
dqm : std_logic_vector(7 downto 0);
bsel : std_ulogic;
haddr : std_logic_vector(31 downto 10);
-- only needed to keep address lines from switch too much
address : std_logic_vector(16 downto 2); -- memory address
idlecnt : std_logic_vector(3 downto 0); -- Counter, 16 idle clock sycles before entering Power-Saving mode
sref_tmpcom : std_logic_vector(2 downto 0); -- Save SD command when exit sref
end record;
signal r, ri : reg_type;
begin
ctrl : process(rst, apbi, sdi, wpo, r)
variable v : reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable dataout : std_logic_vector(31 downto 0); -- data from memory
variable haddr : std_logic_vector(31 downto 0);
variable regsd : std_logic_vector(31 downto 0); -- data from registers
variable dqm : std_logic_vector(7 downto 0);
variable raddr : std_logic_vector(12 downto 0);
variable adec : std_ulogic;
variable busy : std_ulogic;
variable aload : std_ulogic;
variable rams : std_logic_vector(1 downto 0);
variable hresp : std_logic_vector(1 downto 0);
variable ba : std_logic_vector(1 downto 0);
variable lline : std_logic_vector(2 downto 0);
variable rline : std_logic_vector(2 downto 0);
variable lineburst : boolean;
variable arefresh : std_logic;
begin
-- Variable default settings to avoid latches
v := r; startsd := '0'; v.busy := '0'; hresp := HRESP_OKAY;
lline := not r.cfg.casdel & r.cfg.casdel & r.cfg.casdel;
rline := not r.cfg.casdel & r.cfg.casdel & r.cfg.casdel;
arefresh := '0';
if sdi.hready = '1' then v.hsel := sdi.hsel; end if;
if (sdi.hready and sdi.hsel ) = '1' then
if sdi.htrans(1) = '1' then v.hready := '0'; end if;
end if;
if fast = 1 then haddr := sdi.rhaddr; else haddr := sdi.haddr; end if;
if (pageburst = 0) or ((pageburst = 2) and r.cfg.pageburst = '0') then
lineburst := true;
else lineburst := false; end if;
-- main state
case sdi.hsize is
when "00" =>
case sdi.rhaddr(1 downto 0) is
when "00" => dqm := "11110111";
when "01" => dqm := "11111011";
when "10" => dqm := "11111101";
when others => dqm := "11111110";
end case;
when "01" =>
if sdi.rhaddr(1) = '0' then dqm := "11110011"; else dqm := "11111100"; end if;
when others => dqm := "11110000";
end case;
if BUS64 and (r.bsel = '1') then
dqm := dqm(3 downto 0) & "1111";
end if;
-- main FSM
case r.mstate is
when midle =>
if (v.hsel and sdi.nhtrans(1)) = '1' then
if (r.sdstate = sidle) and (r.cfg.command = "000") and
(r.cmstate = midle) and (sdi.idle = '1')
then
if fast = 1 then v.startsd := '1'; else startsd := '1'; end if;
v.mstate := active;
elsif ((r.sdstate = sref) or (r.sdstate = pd) or (r.sdstate = dpd))
and (r.cfg.command = "000") and (r.cmstate = midle) --and (v.hio = '0')
then
v.startsd := '1';
if r.sdstate = dpd then -- Error response when on Deep Power-Down mode
hresp := HRESP_ERROR;
else
v.mstate := active;
end if;
end if;
end if;
when others => null;
end case;
startsd := r.startsd or startsd;
-- generate row and column address size
case r.cfg.csize is
when "00" => raddr := haddr(22 downto 10);
when "01" => raddr := haddr(23 downto 11);
when "10" => raddr := haddr(24 downto 12);
when others =>
if r.cfg.bsize = "111" then raddr := haddr(26 downto 14);
else raddr := haddr(25 downto 13); end if;
end case;
-- generate bank address
ba := genmux(r.cfg.bsize, haddr(28 downto 21)) &
genmux(r.cfg.bsize, haddr(27 downto 20));
-- generate chip select
if BUS64 then
adec := genmux(r.cfg.bsize, haddr(30 downto 23));
v.bsel := genmux(r.cfg.bsize, sdi.rhaddr(29 downto 22));
else
adec := genmux(r.cfg.bsize, haddr(29 downto 22)); v.bsel := '0';
end if;
if (sdi.srdis = '0') and (r.cfg.bsize = "111") then adec := not adec; end if;
rams := adec & not adec;
if r.trfc /= "0000" then v.trfc := r.trfc - 1; end if;
if r.idlecnt /= "0000" then v.idlecnt := r.idlecnt - 1; end if;
-- sdram access FSM
case r.sdstate is
when sidle =>
v.bdelay := '0';
if (startsd = '1') and (r.cfg.command = "000") and (r.cmstate = midle) then
v.address(16 downto 2) := ba & raddr;
v.sdcsn := not rams(1 downto 0); v.rasn := '0'; v.sdstate := act1;
v.startsd := '0';
elsif (r.idlecnt = "0000") and (r.cfg.command = "000")
and (r.cmstate = midle) and (r.cfg.mobileen(1) = '1') then
case r.cfg.pmode is
when PM_SR =>
v.cfg.cke := '0'; v.sdstate := sref;
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc; -- Control minimum duration of Self Refresh mode (= tRAS)
when PM_PD => v.cfg.cke := '0'; v.sdstate := pd;
when PM_DPD =>
v.cfg.cke := '0'; v.sdstate := dpd;
v.sdcsn := (others => '0'); v.sdwen := '0'; v.rasn := '1'; v.casn := '1';
when others =>
end case;
end if;
when act1 =>
v.rasn := '1'; v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc; v.haddr := sdi.rhaddr(31 downto 10);
if r.cfg.casdel = '1' then v.sdstate := act2; else
v.sdstate := act3;
v.hready := sdi.hwrite and sdi.htrans(0) and sdi.htrans(1);
end if;
if WPROTEN then
v.wprothit := wpo.wprothit;
if wpo.wprothit = '1' then hresp := HRESP_ERROR; end if;
end if;
when act2 =>
v.sdstate := act3;
v.hready := sdi.hwrite and sdi.htrans(0) and sdi.htrans(1);
if WPROTEN and (r.wprothit = '1') then
hresp := HRESP_ERROR; v.hready := '0';
end if;
when act3 =>
v.casn := '0';
v.address(14 downto 2) := sdi.rhaddr(13 downto 12) & '0' & sdi.rhaddr(11 downto 2);
v.dqm := dqm; v.burst := r.hready;
if sdi.hwrite = '1' then
v.sdstate := wr1; v.sdwen := '0'; v.bdrive := '1';
if sdi.htrans = "11" or (r.hready = '0') then v.hready := '1'; end if;
if WPROTEN and (r.wprothit = '1') then
hresp := HRESP_ERROR; v.hready := '1';
v.sdstate := wr1; v.sdwen := '1'; v.bdrive := '0'; v.casn := '1';
end if;
else v.sdstate := rd1; end if;
when wr1 =>
v.address(14 downto 2) := sdi.rhaddr(13 downto 12) & '0' & sdi.rhaddr(11 downto 2);
if (((r.burst and r.hready) = '1') and (sdi.rhtrans = "11"))
and not (WPROTEN and (r.wprothit = '1'))
then
v.hready := sdi.htrans(0) and sdi.htrans(1) and r.hready;
if ((sdi.rhaddr(5 downto 2) = "1111") and (r.cfg.command = "100")) then -- exit on refresh
v.hready := '0';
end if;
else
v.sdstate := wr2; v.bdrive := '0'; v.casn := '1'; v.sdwen := '1';
v.dqm := (others => '1');
end if;
when wr2 =>
if (sdi.rhtrans = "10") and (sdi.rhaddr(31 downto 10) = r.haddr) and (r.hsel = '1') then
if sdi.hwrite = '1' then v.hready := '1'; end if; v.sdstate := act3;
elsif (r.trfc(2 downto 1) = "00") then
if (r.cfg.trp = '0') then v.rasn := '0'; v.sdwen := '0'; end if;
v.sdstate := wr3;
end if;
when wr3 =>
if (sdi.rhtrans = "10") and (sdi.rhaddr(31 downto 10) = r.haddr) and (r.sdwen = '1') and (r.hsel = '1') then
if sdi.hwrite = '1' then v.hready := '1'; end if; v.sdstate := act3;
elsif (r.cfg.trp = '1') then
v.rasn := '0'; v.sdwen := '0'; v.sdstate := wr4;
else
v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1';
if r.trfc = "0000" then v.sdstate := sidle; end if;
end if;
when wr4 =>
v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1';
if (r.cfg.trp = '1') then v.sdstate := wr5;
else
if r.trfc = "0000" then v.sdstate := sidle; end if;
end if;
when wr5 =>
if r.trfc = "0000" then v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
when rd1 =>
v.casn := '1'; v.sdstate := rd7;
if lineburst and (sdi.htrans = "11") then
if sdi.rhaddr(4 downto 2) = "111" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
when rd7 =>
v.casn := '1';
if r.cfg.casdel = '1' then
v.sdstate := rd2;
if lineburst and (sdi.htrans = "11") then
if sdi.rhaddr(4 downto 2) = "110" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
else
v.sdstate := rd3;
if sdi.htrans /= "11" then
if (r.trfc(2 downto 1) = "00") then v.rasn := '0'; v.sdwen := '0'; end if;
elsif lineburst then
if sdi.rhaddr(4 downto 2) = "110" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
end if;
when rd2 =>
v.casn := '1'; v.sdstate := rd3;
if sdi.htrans /= "11" then -- v.rasn := '0'; v.sdwen := '0';
if (r.trfc(2 downto 1) = "00") then v.rasn := '0'; v.sdwen := '0'; end if;
elsif lineburst then
if sdi.rhaddr(4 downto 2) = "101" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
if v.sdwen = '0' then v.dqm := (others => '1'); end if;
when rd3 =>
v.sdstate := rd4; v.hready := '1'; v.casn := '1';
if r.sdwen = '0' then
v.rasn := '1'; v.sdwen := '1'; v.sdcsn := "11"; v.dqm := (others => '1');
elsif lineburst and (sdi.htrans = "11") and (r.casn = '1') then
if sdi.rhaddr(4 downto 2) = ("10" & not r.cfg.casdel) then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
when rd4 =>
v.hready := '1'; v.casn := '1';
if (sdi.htrans /= "11") or (r.sdcsn = "11") or
((sdi.rhaddr(5 downto 2) = "1111") and (r.cfg.command = "100")) -- exit on refresh
then
v.hready := '0'; v.dqm := (others => '1');
if (r.sdcsn /= "11") then
v.rasn := '0'; v.sdwen := '0'; v.sdstate := rd5;
else
if r.cfg.trp = '1' then v.sdstate := rd6;
else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
end if;
elsif lineburst then
if (sdi.rhaddr(4 downto 2) = lline) and (r.casn = '1') then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
when rd5 =>
if r.cfg.trp = '1' then v.sdstate := rd6; else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1'; v.dqm := (others => '1');
v.casn := '1';
when rd6 =>
v.sdstate := sidle; v.idlecnt := (others => '1'); v.dqm := (others => '1');
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1';
when sref =>
if (startsd = '1') -- and (r.hio = '0'))
or (r.cfg.command /= "000") or r.cfg.pmode /= PM_SR then
if r.trfc = "0000" then -- Minimum duration (= tRAS)
v.cfg.cke := '1';
v.sdcsn := (others => '0'); v.rasn := '1'; v.casn := '1';
end if;
if r.cfg.cke = '1' then
if (r.idlecnt = "0000") then -- tXSR ns with NOP
v.sdstate := sidle;
v.idlecnt := (others => '1');
v.sref_tmpcom := r.cfg.command;
v.cfg.command := "100";
end if;
else
v.idlecnt := r.cfg.txsr;
end if;
end if;
when pd =>
if (startsd = '1') -- and (r.hio = '0'))
or (r.cfg.command /= "000") or r.cfg.pmode /= PM_PD then
v.cfg.cke := '1';
v.sdstate := sidle;
v.idlecnt := (others => '1');
end if;
when dpd =>
v.sdcsn := (others => '1'); v.sdwen := '1'; v.rasn := '1'; v.casn := '1';
v.cfg.renable := '0';
if (startsd = '1') then -- and r.hio = '0') then
v.hready := '1'; -- ack all accesses with Error response
v.startsd := '0';
hresp := HRESP_ERROR;
elsif r.cfg.pmode /= PM_DPD then
v.cfg.cke := '1';
if r.cfg.cke = '1' then
v.sdstate := sidle;
v.idlecnt := (others => '1');
v.cfg.renable := '1';
end if;
end if;
when others =>
v.sdstate := sidle; v.idlecnt := (others => '1');
end case;
-- sdram commands
case r.cmstate is
when midle =>
if r.sdstate = sidle then
case r.cfg.command is
when "010" => -- precharge
if (sdi.idle = '1') then
v.busy := '1';
v.sdcsn := (others => '0'); v.rasn := '0'; v.sdwen := '0';
v.address(12) := '1'; v.cmstate := active;
end if;
when "100" => -- auto-refresh
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.cmstate := active;
when "110" =>
if (sdi.idle = '1') then
v.busy := '1';
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active;
if lineburst then
v.address(16 downto 2) := "0000010001" & r.cfg.casdel & "0011";
else
v.address(16 downto 2) := "0000010001" & r.cfg.casdel & "0111";
end if;
end if;
when "111" => -- Load Ext-Mode Reg
if (sdi.idle = '1') then
v.busy := '1';
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active;
v.address(16 downto 2) := "10000000" & r.cfg.ds(1 downto 0) & r.cfg.tcsr(1 downto 0)
& r.cfg.pasr(2 downto 0);
end if;
when others => null;
end case;
end if;
when active =>
v.sdcsn := (others => '1'); v.rasn := '1'; v.casn := '1';
v.sdwen := '1'; --v.cfg.command := "000";
v.cfg.command := r.sref_tmpcom; v.sref_tmpcom := "000";
v.cmstate := leadout; v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc;
when leadout =>
if r.trfc = "0000" then v.cmstate := midle; end if;
end case;
-- sdram init
case r.istate is
when iidle =>
v.cfg.cke := '1';
if (sdi.idle and sdi.enable) = '1' and r.cfg.cke = '1' then
v.cfg.command := "010"; v.istate := pre;
end if;
when pre =>
if r.cfg.command = "000" then
v.cfg.command := "100"; v.istate := ref; v.icnt := "111";
end if;
when ref =>
if r.cfg.command = "000" then
v.cfg.command := "100"; v.icnt := r.icnt - 1;
if r.icnt = "000" then v.istate := lmode; v.cfg.command := "110"; end if;
end if;
when lmode =>
if r.cfg.command = "000" then
if r.cfg.mobileen = "11" then
v.cfg.command := "111"; v.istate := emode;
else
v.istate := finish;
end if;
end if;
when emode =>
if r.cfg.command = "000" then
v.istate := finish;
end if;
when others =>
if sdi.enable = '0' and r.sdstate /= dpd then
v.istate := iidle;
end if;
end case;
if (sdi.hready and sdi.hsel ) = '1' then
if sdi.htrans(1) = '0' then v.hready := '1'; end if;
end if;
-- second part of main fsm
case r.mstate is
when active =>
if v.hready = '1' then
v.mstate := midle;
end if;
when others => null;
end case;
-- sdram refresh counter
if (r.cfg.renable = '1') and (r.istate = finish) and r.sdstate /= sref then
v.refresh := r.refresh - 1;
if (v.refresh(14) and not r.refresh(14)) = '1' then
v.refresh := r.cfg.refresh;
v.cfg.command := "100";
arefresh := '1';
end if;
end if;
-- APB register access
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(3 downto 2) is
when "01" =>
if pageburst = 2 then v.cfg.pageburst := apbi.pwdata(17); end if;
if sdi.enable = '1' then
v.cfg.command(2 downto 1) := apbi.pwdata(20 downto 19);
end if;
v.cfg.csize := apbi.pwdata(22 downto 21);
v.cfg.bsize := apbi.pwdata(25 downto 23);
v.cfg.casdel := apbi.pwdata(26);
v.cfg.trfc := apbi.pwdata(29 downto 27);
v.cfg.trp := apbi.pwdata(30);
v.cfg.renable := apbi.pwdata(31);
when "10" =>
v.cfg.refresh := apbi.pwdata(26 downto 12);
v.refresh := (others => '0');
when "11" =>
if r.cfg.mobileen(1) = '1' and mobile /= 3 then v.cfg.mobileen(0) := apbi.pwdata(31); end if;
if r.cfg.pmode = "000" then
v.cfg.cke := apbi.pwdata(30);
end if;
if r.cfg.mobileen(1) = '1' then
if sdi.enable = '1' then
v.cfg.command(0) := apbi.pwdata(29);
end if;
v.cfg.txsr := apbi.pwdata(23 downto 20);
v.cfg.pmode := apbi.pwdata(18 downto 16);
v.cfg.ds(3 downto 2) := apbi.pwdata( 6 downto 5);
v.cfg.tcsr(3 downto 2) := apbi.pwdata( 4 downto 3);
v.cfg.pasr(5 downto 3) := apbi.pwdata( 2 downto 0);
end if;
when others =>
end case;
end if;
-- Disable CS and DPD when Mobile SDR is Disabled
if r.cfg.mobileen(0) = '0' then v.cfg.pmode(2) := '0'; end if;
-- Update EMR when ds, tcsr or pasr change
if r.cfg.command = "000" and arefresh = '0' and r.cfg.mobileen(0) = '1' then
if r.cfg.ds(1 downto 0) /= r.cfg.ds(3 downto 2) then
v.cfg.command := "111"; v.cfg.ds(1 downto 0) := r.cfg.ds(3 downto 2);
end if;
if r.cfg.tcsr(1 downto 0) /= r.cfg.tcsr(3 downto 2) then
v.cfg.command := "111"; v.cfg.tcsr(1 downto 0) := r.cfg.tcsr(3 downto 2);
end if;
if r.cfg.pasr(2 downto 0) /= r.cfg.pasr(5 downto 3) then
v.cfg.command := "111"; v.cfg.pasr(2 downto 0) := r.cfg.pasr(5 downto 3);
end if;
end if;
regsd := (others => '0');
case apbi.paddr(3 downto 2) is
when "01" =>
regsd(31 downto 19) := r.cfg.renable & r.cfg.trp & r.cfg.trfc &
r.cfg.casdel & r.cfg.bsize & r.cfg.csize & r.cfg.command(2 downto 1);
if not lineburst then regsd(17) := '1'; end if;
regsd(16) := r.cfg.mobileen(1);
when "11" =>
regsd(31) := r.cfg.mobileen(0);
regsd(30) := r.cfg.cke;
regsd(30) := r.cfg.command(0);
regsd(23 downto 0) := r.cfg.txsr & '0' & r.cfg.pmode & "000000000" &
r.cfg.ds(1 downto 0) & r.cfg.tcsr(1 downto 0) & r.cfg.pasr(2 downto 0);
when others =>
regsd(26 downto 12) := r.cfg.refresh;
end case;
sdmo.prdata <= regsd;
-- synchronise with sram/prom controller
if fast = 0 then
if (r.sdstate < wr4) or (v.hsel = '1') then v.busy := '1';end if;
else
if (r.sdstate < wr4) or (r.startsd = '1') then v.busy := '1';end if;
end if;
v.busy := v.busy or r.bdelay;
busy := v.busy or r.busy;
v.aload := r.busy and not v.busy;
aload := v.aload;
-- generate memory address
sdmo.address <= v.address;
-- reset
if rst = '0' then
v.sdstate := sidle;
v.mstate := midle;
v.istate := iidle;
v.cmstate := midle;
v.hsel := '0';
v.cfg.command := "000";
v.cfg.csize := "10";
v.cfg.bsize := "000";
v.cfg.casdel := '1';
v.cfg.trfc := "111";
v.cfg.renable := '0';
v.cfg.trp := '1';
v.dqm := (others => '1');
v.sdwen := '1';
v.rasn := '1';
v.casn := '1';
v.hready := '1';
v.startsd := '0';
if (pageburst = 2) then
v.cfg.pageburst := '0';
end if;
if mobile >= 2 then v.cfg.mobileen := "11";
elsif mobile = 1 then v.cfg.mobileen := "10";
else v.cfg.mobileen := "00"; end if;
v.cfg.txsr := (others => '1');
v.cfg.pmode := (others => '0');
v.cfg.ds := (others => '0');
v.cfg.tcsr := (others => '0');
v.cfg.pasr := (others => '0');
if mobile >= 2 then v.cfg.cke := '0';
else v.cfg.cke := '1'; end if;
v.sref_tmpcom := "000";
v.idlecnt := (others => '1');
end if;
ri <= v;
sdmo.bdrive <= v.bdrive;
--sdo.sdcke <= (others => '1');
sdo.sdcke <= (others => r.cfg.cke);
sdo.sdcsn <= r.sdcsn;
sdo.sdwen <= r.sdwen;
sdo.dqm <= r.dqm;
sdo.rasn <= r.rasn;
sdo.casn <= r.casn;
sdmo.busy <= busy;
sdmo.aload <= aload;
sdmo.hready <= r.hready;
sdmo.vhready <= v.hready;
sdmo.hresp <= hresp;
sdmo.hsel <= r.hsel;
sdmo.bsel <= r.bsel;
end process;
regs : process(clk,rst)
begin
if rising_edge(clk) then
r <= ri;
if rst = '0' then
r.icnt <= (others => '0');
end if;
end if;
if rst = '0' then
r.bdrive <= '0';
r.sdcsn <= (others => '1');
end if;
end process;
end;
| gpl-3.0 | fcf5bdef7a2fd8d2309d60e3c24774cb | 0.52551 | 3.133235 | false | false | false | false |
hoglet67/CoPro6502 | src/ROM/tuberom_pdp11.vhd | 1 | 45,768 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tuberom_pdp11 is
port (
CLK : in std_logic;
ADDR : in std_logic_vector(9 downto 0);
DATA : out std_logic_vector(15 downto 0)
);
end;
architecture RTL of tuberom_pdp11 is
signal rom_addr : std_logic_vector(11 downto 0);
begin
p_addr : process(ADDR)
begin
rom_addr <= (others => '0');
rom_addr(9 downto 0) <= ADDR;
end process;
p_rom : process
begin
wait until rising_edge(CLK);
DATA <= (others => '0');
case rom_addr is
when x"000" => DATA <= x"0077";
when x"001" => DATA <= x"0018";
when x"002" => DATA <= x"500D";
when x"003" => DATA <= x"5044";
when x"004" => DATA <= x"3131";
when x"005" => DATA <= x"5420";
when x"006" => DATA <= x"4255";
when x"007" => DATA <= x"2045";
when x"008" => DATA <= x"3436";
when x"009" => DATA <= x"204B";
when x"00a" => DATA <= x"2E30";
when x"00b" => DATA <= x"3732";
when x"00c" => DATA <= x"0D61";
when x"00d" => DATA <= x"000D";
when x"00e" => DATA <= x"15C6";
when x"00f" => DATA <= x"F5D8";
when x"010" => DATA <= x"17E6";
when x"011" => DATA <= x"F5FC";
when x"012" => DATA <= x"09F7";
when x"013" => DATA <= x"0572";
when x"014" => DATA <= x"159F";
when x"015" => DATA <= x"F5F8";
when x"016" => DATA <= x"15C1";
when x"017" => DATA <= x"F804";
when x"018" => DATA <= x"09F7";
when x"019" => DATA <= x"0084";
when x"01a" => DATA <= x"09F7";
when x"01b" => DATA <= x"048E";
when x"01c" => DATA <= x"00A1";
when x"01d" => DATA <= x"09F7";
when x"01e" => DATA <= x"0124";
when x"01f" => DATA <= x"17C6";
when x"020" => DATA <= x"F5F6";
when x"021" => DATA <= x"15DF";
when x"022" => DATA <= x"F83E";
when x"023" => DATA <= x"F5FC";
when x"024" => DATA <= x"15C1";
when x"025" => DATA <= x"F860";
when x"026" => DATA <= x"09F7";
when x"027" => DATA <= x"0068";
when x"028" => DATA <= x"09F7";
when x"029" => DATA <= x"0280";
when x"02a" => DATA <= x"870C";
when x"02b" => DATA <= x"17C0";
when x"02c" => DATA <= x"F868";
when x"02d" => DATA <= x"09F7";
when x"02e" => DATA <= x"0076";
when x"02f" => DATA <= x"01F4";
when x"030" => DATA <= x"4450";
when x"031" => DATA <= x"3150";
when x"032" => DATA <= x"3E31";
when x"033" => DATA <= x"002A";
when x"034" => DATA <= x"F500";
when x"035" => DATA <= x"20B8";
when x"036" => DATA <= x"00FF";
when x"037" => DATA <= x"15C0";
when x"038" => DATA <= x"007E";
when x"039" => DATA <= x"09F7";
when x"03a" => DATA <= x"01E0";
when x"03b" => DATA <= x"880F";
when x"03c" => DATA <= x"4511";
when x"03d" => DATA <= x"6373";
when x"03e" => DATA <= x"7061";
when x"03f" => DATA <= x"0065";
when x"040" => DATA <= x"17C6";
when x"041" => DATA <= x"F5F6";
when x"042" => DATA <= x"1001";
when x"043" => DATA <= x"0A81";
when x"044" => DATA <= x"09F7";
when x"045" => DATA <= x"042E";
when x"046" => DATA <= x"09F7";
when x"047" => DATA <= x"0028";
when x"048" => DATA <= x"09F7";
when x"049" => DATA <= x"0426";
when x"04a" => DATA <= x"01D4";
when x"04b" => DATA <= x"6000";
when x"04c" => DATA <= x"903F";
when x"04d" => DATA <= x"FD42";
when x"04e" => DATA <= x"0087";
when x"04f" => DATA <= x"E5C1";
when x"050" => DATA <= x"0002";
when x"051" => DATA <= x"9440";
when x"052" => DATA <= x"45C0";
when x"053" => DATA <= x"FF00";
when x"054" => DATA <= x"9241";
when x"055" => DATA <= x"45C1";
when x"056" => DATA <= x"FF00";
when x"057" => DATA <= x"00C1";
when x"058" => DATA <= x"5001";
when x"059" => DATA <= x"0087";
when x"05a" => DATA <= x"09F7";
when x"05b" => DATA <= x"03FC";
when x"05c" => DATA <= x"9440";
when x"05d" => DATA <= x"02FC";
when x"05e" => DATA <= x"0087";
when x"05f" => DATA <= x"A417";
when x"060" => DATA <= x"0021";
when x"061" => DATA <= x"86FD";
when x"062" => DATA <= x"0AC0";
when x"063" => DATA <= x"A417";
when x"064" => DATA <= x"0020";
when x"065" => DATA <= x"03FD";
when x"066" => DATA <= x"0AC0";
when x"067" => DATA <= x"0087";
when x"068" => DATA <= x"7572";
when x"069" => DATA <= x"006E";
when x"06a" => DATA <= x"1066";
when x"06b" => DATA <= x"10A6";
when x"06c" => DATA <= x"10E6";
when x"06d" => DATA <= x"1126";
when x"06e" => DATA <= x"1166";
when x"06f" => DATA <= x"1185";
when x"070" => DATA <= x"2157";
when x"071" => DATA <= x"F500";
when x"072" => DATA <= x"8602";
when x"073" => DATA <= x"15C6";
when x"074" => DATA <= x"F5D8";
when x"075" => DATA <= x"1166";
when x"076" => DATA <= x"17E6";
when x"077" => DATA <= x"F5F6";
when x"078" => DATA <= x"17E6";
when x"079" => DATA <= x"F5FC";
when x"07a" => DATA <= x"09F7";
when x"07b" => DATA <= x"0018";
when x"07c" => DATA <= x"159F";
when x"07d" => DATA <= x"F5FC";
when x"07e" => DATA <= x"159F";
when x"07f" => DATA <= x"F5F6";
when x"080" => DATA <= x"1386";
when x"081" => DATA <= x"1585";
when x"082" => DATA <= x"1584";
when x"083" => DATA <= x"1583";
when x"084" => DATA <= x"1582";
when x"085" => DATA <= x"1581";
when x"086" => DATA <= x"0A00";
when x"087" => DATA <= x"0087";
when x"088" => DATA <= x"09F7";
when x"089" => DATA <= x"FFB2";
when x"08a" => DATA <= x"A417";
when x"08b" => DATA <= x"002A";
when x"08c" => DATA <= x"03FB";
when x"08d" => DATA <= x"0AC0";
when x"08e" => DATA <= x"1001";
when x"08f" => DATA <= x"1004";
when x"090" => DATA <= x"A417";
when x"091" => DATA <= x"002F";
when x"092" => DATA <= x"030F";
when x"093" => DATA <= x"0AC0";
when x"094" => DATA <= x"15C2";
when x"095" => DATA <= x"F8D0";
when x"096" => DATA <= x"9403";
when x"097" => DATA <= x"55C3";
when x"098" => DATA <= x"0020";
when x"099" => DATA <= x"A483";
when x"09a" => DATA <= x"03FB";
when x"09b" => DATA <= x"0AC0";
when x"09c" => DATA <= x"0AC2";
when x"09d" => DATA <= x"A217";
when x"09e" => DATA <= x"0021";
when x"09f" => DATA <= x"8605";
when x"0a0" => DATA <= x"8BCA";
when x"0a1" => DATA <= x"0203";
when x"0a2" => DATA <= x"09F7";
when x"0a3" => DATA <= x"FF7E";
when x"0a4" => DATA <= x"1004";
when x"0a5" => DATA <= x"1100";
when x"0a6" => DATA <= x"09F7";
when x"0a7" => DATA <= x"FF6E";
when x"0a8" => DATA <= x"1037";
when x"0a9" => DATA <= x"FC9C";
when x"0aa" => DATA <= x"15C0";
when x"0ab" => DATA <= x"0002";
when x"0ac" => DATA <= x"09F7";
when x"0ad" => DATA <= x"0518";
when x"0ae" => DATA <= x"09F7";
when x"0af" => DATA <= x"04E4";
when x"0b0" => DATA <= x"00B1";
when x"0b1" => DATA <= x"09F7";
when x"0b2" => DATA <= x"032A";
when x"0b3" => DATA <= x"80D3";
when x"0b4" => DATA <= x"17C1";
when x"0b5" => DATA <= x"F5F8";
when x"0b6" => DATA <= x"15C5";
when x"0b7" => DATA <= x"0000";
when x"0b8" => DATA <= x"0C45";
when x"0b9" => DATA <= x"1066";
when x"0ba" => DATA <= x"9C42";
when x"0bb" => DATA <= x"0007";
when x"0bc" => DATA <= x"45C2";
when x"0bd" => DATA <= x"FF00";
when x"0be" => DATA <= x"6081";
when x"0bf" => DATA <= x"8BD1";
when x"0c0" => DATA <= x"0226";
when x"0c1" => DATA <= x"A457";
when x"0c2" => DATA <= x"0028";
when x"0c3" => DATA <= x"0223";
when x"0c4" => DATA <= x"A457";
when x"0c5" => DATA <= x"0043";
when x"0c6" => DATA <= x"0220";
when x"0c7" => DATA <= x"A457";
when x"0c8" => DATA <= x"0029";
when x"0c9" => DATA <= x"021D";
when x"0ca" => DATA <= x"1381";
when x"0cb" => DATA <= x"9C42";
when x"0cc" => DATA <= x"0006";
when x"0cd" => DATA <= x"45C2";
when x"0ce" => DATA <= x"FFB0";
when x"0cf" => DATA <= x"2097";
when x"0d0" => DATA <= x"0047";
when x"0d1" => DATA <= x"0246";
when x"0d2" => DATA <= x"9C42";
when x"0d3" => DATA <= x"0006";
when x"0d4" => DATA <= x"35C2";
when x"0d5" => DATA <= x"0020";
when x"0d6" => DATA <= x"030E";
when x"0d7" => DATA <= x"9C42";
when x"0d8" => DATA <= x"0007";
when x"0d9" => DATA <= x"45C2";
when x"0da" => DATA <= x"FF00";
when x"0db" => DATA <= x"6081";
when x"0dc" => DATA <= x"0A81";
when x"0dd" => DATA <= x"8BD1";
when x"0de" => DATA <= x"02FE";
when x"0df" => DATA <= x"65C1";
when x"0e0" => DATA <= x"0004";
when x"0e1" => DATA <= x"09F7";
when x"0e2" => DATA <= x"FEDC";
when x"0e3" => DATA <= x"6581";
when x"0e4" => DATA <= x"1066";
when x"0e5" => DATA <= x"55C5";
when x"0e6" => DATA <= x"0002";
when x"0e7" => DATA <= x"1581";
when x"0e8" => DATA <= x"45C1";
when x"0e9" => DATA <= x"0001";
when x"0ea" => DATA <= x"1242";
when x"0eb" => DATA <= x"2097";
when x"0ec" => DATA <= x"0105";
when x"0ed" => DATA <= x"871A";
when x"0ee" => DATA <= x"2097";
when x"0ef" => DATA <= x"0109";
when x"0f0" => DATA <= x"8617";
when x"0f1" => DATA <= x"0BD1";
when x"0f2" => DATA <= x"1443";
when x"0f3" => DATA <= x"1444";
when x"0f4" => DATA <= x"6103";
when x"0f5" => DATA <= x"1444";
when x"0f6" => DATA <= x"17C2";
when x"0f7" => DATA <= x"F5F4";
when x"0f8" => DATA <= x"65C1";
when x"0f9" => DATA <= x"0008";
when x"0fa" => DATA <= x"0C83";
when x"0fb" => DATA <= x"1452";
when x"0fc" => DATA <= x"0AC3";
when x"0fd" => DATA <= x"02FD";
when x"0fe" => DATA <= x"0C84";
when x"0ff" => DATA <= x"0303";
when x"100" => DATA <= x"0A12";
when x"101" => DATA <= x"0AC4";
when x"102" => DATA <= x"02FD";
when x"103" => DATA <= x"17C1";
when x"104" => DATA <= x"F5F4";
when x"105" => DATA <= x"0A26";
when x"106" => DATA <= x"0A26";
when x"107" => DATA <= x"0A26";
when x"108" => DATA <= x"1066";
when x"109" => DATA <= x"1140";
when x"10a" => DATA <= x"15C5";
when x"10b" => DATA <= x"0BBC";
when x"10c" => DATA <= x"0A04";
when x"10d" => DATA <= x"0A03";
when x"10e" => DATA <= x"0A02";
when x"10f" => DATA <= x"17C1";
when x"110" => DATA <= x"F5F0";
when x"111" => DATA <= x"139F";
when x"112" => DATA <= x"F5FA";
when x"113" => DATA <= x"8002";
when x"114" => DATA <= x"139F";
when x"115" => DATA <= x"F5F6";
when x"116" => DATA <= x"0C80";
when x"117" => DATA <= x"0087";
when x"118" => DATA <= x"0C85";
when x"119" => DATA <= x"860B";
when x"11a" => DATA <= x"09F7";
when x"11b" => DATA <= x"0396";
when x"11c" => DATA <= x"880F";
when x"11d" => DATA <= x"4EF9";
when x"11e" => DATA <= x"746F";
when x"11f" => DATA <= x"5020";
when x"120" => DATA <= x"5044";
when x"121" => DATA <= x"3131";
when x"122" => DATA <= x"6320";
when x"123" => DATA <= x"646F";
when x"124" => DATA <= x"0065";
when x"125" => DATA <= x"0077";
when x"126" => DATA <= x"FDF0";
when x"127" => DATA <= x"15F7";
when x"128" => DATA <= x"F804";
when x"129" => DATA <= x"FB9C";
when x"12a" => DATA <= x"0185";
when x"12b" => DATA <= x"1026";
when x"12c" => DATA <= x"8BC0";
when x"12d" => DATA <= x"810B";
when x"12e" => DATA <= x"15C0";
when x"12f" => DATA <= x"0004";
when x"130" => DATA <= x"09F7";
when x"131" => DATA <= x"040A";
when x"132" => DATA <= x"1380";
when x"133" => DATA <= x"09F7";
when x"134" => DATA <= x"040A";
when x"135" => DATA <= x"09F7";
when x"136" => DATA <= x"0222";
when x"137" => DATA <= x"1001";
when x"138" => DATA <= x"012F";
when x"139" => DATA <= x"2017";
when x"13a" => DATA <= x"0082";
when x"13b" => DATA <= x"8703";
when x"13c" => DATA <= x"2017";
when x"13d" => DATA <= x"0085";
when x"13e" => DATA <= x"8722";
when x"13f" => DATA <= x"15C0";
when x"140" => DATA <= x"0006";
when x"141" => DATA <= x"09F7";
when x"142" => DATA <= x"03E8";
when x"143" => DATA <= x"1080";
when x"144" => DATA <= x"09F7";
when x"145" => DATA <= x"03E8";
when x"146" => DATA <= x"1580";
when x"147" => DATA <= x"09F7";
when x"148" => DATA <= x"03E2";
when x"149" => DATA <= x"2017";
when x"14a" => DATA <= x"009D";
when x"14b" => DATA <= x"031D";
when x"14c" => DATA <= x"2017";
when x"14d" => DATA <= x"008E";
when x"14e" => DATA <= x"03D8";
when x"14f" => DATA <= x"1026";
when x"150" => DATA <= x"09F7";
when x"151" => DATA <= x"01EC";
when x"152" => DATA <= x"65C0";
when x"153" => DATA <= x"FF80";
when x"154" => DATA <= x"09F7";
when x"155" => DATA <= x"01E4";
when x"156" => DATA <= x"45C0";
when x"157" => DATA <= x"FF00";
when x"158" => DATA <= x"1002";
when x"159" => DATA <= x"00C0";
when x"15a" => DATA <= x"1001";
when x"15b" => DATA <= x"09F7";
when x"15c" => DATA <= x"01D6";
when x"15d" => DATA <= x"45C0";
when x"15e" => DATA <= x"FF00";
when x"15f" => DATA <= x"5001";
when x"160" => DATA <= x"0107";
when x"161" => DATA <= x"0CC0";
when x"162" => DATA <= x"1C01";
when x"163" => DATA <= x"F4EE";
when x"164" => DATA <= x"1042";
when x"165" => DATA <= x"00C2";
when x"166" => DATA <= x"45C2";
when x"167" => DATA <= x"FF00";
when x"168" => DATA <= x"1580";
when x"169" => DATA <= x"0087";
when x"16a" => DATA <= x"0BC0";
when x"16b" => DATA <= x"034D";
when x"16c" => DATA <= x"10E6";
when x"16d" => DATA <= x"10A6";
when x"16e" => DATA <= x"1026";
when x"16f" => DATA <= x"15C0";
when x"170" => DATA <= x"0008";
when x"171" => DATA <= x"09F7";
when x"172" => DATA <= x"038E";
when x"173" => DATA <= x"1380";
when x"174" => DATA <= x"09F7";
when x"175" => DATA <= x"0388";
when x"176" => DATA <= x"8BC0";
when x"177" => DATA <= x"8003";
when x"178" => DATA <= x"9442";
when x"179" => DATA <= x"9243";
when x"17a" => DATA <= x"010C";
when x"17b" => DATA <= x"15C2";
when x"17c" => DATA <= x"0010";
when x"17d" => DATA <= x"15C3";
when x"17e" => DATA <= x"0010";
when x"17f" => DATA <= x"2017";
when x"180" => DATA <= x"0015";
when x"181" => DATA <= x"8605";
when x"182" => DATA <= x"6000";
when x"183" => DATA <= x"65C0";
when x"184" => DATA <= x"FB48";
when x"185" => DATA <= x"9402";
when x"186" => DATA <= x"9203";
when x"187" => DATA <= x"1080";
when x"188" => DATA <= x"09F7";
when x"189" => DATA <= x"0360";
when x"18a" => DATA <= x"6081";
when x"18b" => DATA <= x"0AC2";
when x"18c" => DATA <= x"2097";
when x"18d" => DATA <= x"0080";
when x"18e" => DATA <= x"8605";
when x"18f" => DATA <= x"9840";
when x"190" => DATA <= x"09F7";
when x"191" => DATA <= x"0350";
when x"192" => DATA <= x"0AC2";
when x"193" => DATA <= x"80FB";
when x"194" => DATA <= x"10C0";
when x"195" => DATA <= x"09F7";
when x"196" => DATA <= x"0346";
when x"197" => DATA <= x"60C1";
when x"198" => DATA <= x"0AC3";
when x"199" => DATA <= x"20D7";
when x"19a" => DATA <= x"0080";
when x"19b" => DATA <= x"8605";
when x"19c" => DATA <= x"09F7";
when x"19d" => DATA <= x"0154";
when x"19e" => DATA <= x"9021";
when x"19f" => DATA <= x"0AC3";
when x"1a0" => DATA <= x"80FB";
when x"1a1" => DATA <= x"1580";
when x"1a2" => DATA <= x"1582";
when x"1a3" => DATA <= x"1583";
when x"1a4" => DATA <= x"0087";
when x"1a5" => DATA <= x"0500";
when x"1a6" => DATA <= x"0005";
when x"1a7" => DATA <= x"0500";
when x"1a8" => DATA <= x"0005";
when x"1a9" => DATA <= x"0504";
when x"1aa" => DATA <= x"0005";
when x"1ab" => DATA <= x"0008";
when x"1ac" => DATA <= x"000E";
when x"1ad" => DATA <= x"0504";
when x"1ae" => DATA <= x"0901";
when x"1af" => DATA <= x"0501";
when x"1b0" => DATA <= x"0005";
when x"1b1" => DATA <= x"0800";
when x"1b2" => DATA <= x"1910";
when x"1b3" => DATA <= x"0020";
when x"1b4" => DATA <= x"0110";
when x"1b5" => DATA <= x"0D0D";
when x"1b6" => DATA <= x"8000";
when x"1b7" => DATA <= x"0808";
when x"1b8" => DATA <= x"8080";
when x"1b9" => DATA <= x"15C0";
when x"1ba" => DATA <= x"000A";
when x"1bb" => DATA <= x"09F7";
when x"1bc" => DATA <= x"02FA";
when x"1bd" => DATA <= x"65C1";
when x"1be" => DATA <= x"0002";
when x"1bf" => DATA <= x"15C2";
when x"1c0" => DATA <= x"0003";
when x"1c1" => DATA <= x"09F7";
when x"1c2" => DATA <= x"02CC";
when x"1c3" => DATA <= x"15C0";
when x"1c4" => DATA <= x"0007";
when x"1c5" => DATA <= x"09F7";
when x"1c6" => DATA <= x"02E6";
when x"1c7" => DATA <= x"0A00";
when x"1c8" => DATA <= x"09F7";
when x"1c9" => DATA <= x"02E0";
when x"1ca" => DATA <= x"09F7";
when x"1cb" => DATA <= x"00F8";
when x"1cc" => DATA <= x"65C0";
when x"1cd" => DATA <= x"FF80";
when x"1ce" => DATA <= x"870B";
when x"1cf" => DATA <= x"09F7";
when x"1d0" => DATA <= x"FCFC";
when x"1d1" => DATA <= x"0A02";
when x"1d2" => DATA <= x"09F7";
when x"1d3" => DATA <= x"00E8";
when x"1d4" => DATA <= x"9011";
when x"1d5" => DATA <= x"0A82";
when x"1d6" => DATA <= x"2017";
when x"1d7" => DATA <= x"000D";
when x"1d8" => DATA <= x"02F9";
when x"1d9" => DATA <= x"0AC2";
when x"1da" => DATA <= x"0087";
when x"1db" => DATA <= x"10A6";
when x"1dc" => DATA <= x"1066";
when x"1dd" => DATA <= x"1026";
when x"1de" => DATA <= x"15C0";
when x"1df" => DATA <= x"000C";
when x"1e0" => DATA <= x"09F7";
when x"1e1" => DATA <= x"02AA";
when x"1e2" => DATA <= x"1081";
when x"1e3" => DATA <= x"15C2";
when x"1e4" => DATA <= x"0004";
when x"1e5" => DATA <= x"09F7";
when x"1e6" => DATA <= x"0284";
when x"1e7" => DATA <= x"1580";
when x"1e8" => DATA <= x"09F7";
when x"1e9" => DATA <= x"02A0";
when x"1ea" => DATA <= x"09F7";
when x"1eb" => DATA <= x"00B8";
when x"1ec" => DATA <= x"1026";
when x"1ed" => DATA <= x"15C2";
when x"1ee" => DATA <= x"0004";
when x"1ef" => DATA <= x"0133";
when x"1f0" => DATA <= x"1026";
when x"1f1" => DATA <= x"15C0";
when x"1f2" => DATA <= x"0012";
when x"1f3" => DATA <= x"09F7";
when x"1f4" => DATA <= x"028A";
when x"1f5" => DATA <= x"1580";
when x"1f6" => DATA <= x"09F7";
when x"1f7" => DATA <= x"0284";
when x"1f8" => DATA <= x"0BC0";
when x"1f9" => DATA <= x"0206";
when x"1fa" => DATA <= x"09F7";
when x"1fb" => DATA <= x"027A";
when x"1fc" => DATA <= x"09F7";
when x"1fd" => DATA <= x"0094";
when x"1fe" => DATA <= x"0A00";
when x"1ff" => DATA <= x"0087";
when x"200" => DATA <= x"1066";
when x"201" => DATA <= x"09F7";
when x"202" => DATA <= x"023E";
when x"203" => DATA <= x"09F7";
when x"204" => DATA <= x"0086";
when x"205" => DATA <= x"1581";
when x"206" => DATA <= x"0087";
when x"207" => DATA <= x"10A6";
when x"208" => DATA <= x"1066";
when x"209" => DATA <= x"1026";
when x"20a" => DATA <= x"15C0";
when x"20b" => DATA <= x"0014";
when x"20c" => DATA <= x"09F7";
when x"20d" => DATA <= x"0258";
when x"20e" => DATA <= x"65C1";
when x"20f" => DATA <= x"0002";
when x"210" => DATA <= x"15C2";
when x"211" => DATA <= x"0010";
when x"212" => DATA <= x"09F7";
when x"213" => DATA <= x"022A";
when x"214" => DATA <= x"09F7";
when x"215" => DATA <= x"FC72";
when x"216" => DATA <= x"09F7";
when x"217" => DATA <= x"0214";
when x"218" => DATA <= x"1580";
when x"219" => DATA <= x"09F7";
when x"21a" => DATA <= x"023E";
when x"21b" => DATA <= x"09F7";
when x"21c" => DATA <= x"0056";
when x"21d" => DATA <= x"1381";
when x"21e" => DATA <= x"1026";
when x"21f" => DATA <= x"65C1";
when x"220" => DATA <= x"0002";
when x"221" => DATA <= x"15C2";
when x"222" => DATA <= x"0010";
when x"223" => DATA <= x"09F7";
when x"224" => DATA <= x"0216";
when x"225" => DATA <= x"1580";
when x"226" => DATA <= x"1581";
when x"227" => DATA <= x"1582";
when x"228" => DATA <= x"0087";
when x"229" => DATA <= x"10A6";
when x"22a" => DATA <= x"1026";
when x"22b" => DATA <= x"15C0";
when x"22c" => DATA <= x"0016";
when x"22d" => DATA <= x"09F7";
when x"22e" => DATA <= x"0216";
when x"22f" => DATA <= x"15C2";
when x"230" => DATA <= x"000D";
when x"231" => DATA <= x"09F7";
when x"232" => DATA <= x"01EC";
when x"233" => DATA <= x"1580";
when x"234" => DATA <= x"09F7";
when x"235" => DATA <= x"0208";
when x"236" => DATA <= x"15C2";
when x"237" => DATA <= x"000D";
when x"238" => DATA <= x"09F7";
when x"239" => DATA <= x"01EC";
when x"23a" => DATA <= x"1582";
when x"23b" => DATA <= x"0108";
when x"23c" => DATA <= x"15C0";
when x"23d" => DATA <= x"000E";
when x"23e" => DATA <= x"09F7";
when x"23f" => DATA <= x"01EE";
when x"240" => DATA <= x"0103";
when x"241" => DATA <= x"0A00";
when x"242" => DATA <= x"09F7";
when x"243" => DATA <= x"01EC";
when x"244" => DATA <= x"09F7";
when x"245" => DATA <= x"0004";
when x"246" => DATA <= x"65C0";
when x"247" => DATA <= x"FF80";
when x"248" => DATA <= x"97C0";
when x"249" => DATA <= x"FFF4";
when x"24a" => DATA <= x"80FD";
when x"24b" => DATA <= x"97C0";
when x"24c" => DATA <= x"FFF6";
when x"24d" => DATA <= x"0087";
when x"24e" => DATA <= x"1026";
when x"24f" => DATA <= x"15C0";
when x"250" => DATA <= x"0010";
when x"251" => DATA <= x"09F7";
when x"252" => DATA <= x"01C8";
when x"253" => DATA <= x"1380";
when x"254" => DATA <= x"09F7";
when x"255" => DATA <= x"01C8";
when x"256" => DATA <= x"09F7";
when x"257" => DATA <= x"FFE0";
when x"258" => DATA <= x"1580";
when x"259" => DATA <= x"0087";
when x"25a" => DATA <= x"25C0";
when x"25b" => DATA <= x"000D";
when x"25c" => DATA <= x"0206";
when x"25d" => DATA <= x"15C0";
when x"25e" => DATA <= x"000A";
when x"25f" => DATA <= x"09F7";
when x"260" => DATA <= x"0004";
when x"261" => DATA <= x"15C0";
when x"262" => DATA <= x"000D";
when x"263" => DATA <= x"35DF";
when x"264" => DATA <= x"0040";
when x"265" => DATA <= x"FFF0";
when x"266" => DATA <= x"03FC";
when x"267" => DATA <= x"901F";
when x"268" => DATA <= x"FFF2";
when x"269" => DATA <= x"0087";
when x"26a" => DATA <= x"880F";
when x"26b" => DATA <= x"42FF";
when x"26c" => DATA <= x"6461";
when x"26d" => DATA <= x"0000";
when x"26e" => DATA <= x"45F6";
when x"26f" => DATA <= x"FFF0";
when x"270" => DATA <= x"0002";
when x"271" => DATA <= x"17E6";
when x"272" => DATA <= x"F5E0";
when x"273" => DATA <= x"17E6";
when x"274" => DATA <= x"F5EC";
when x"275" => DATA <= x"119F";
when x"276" => DATA <= x"F5EC";
when x"277" => DATA <= x"15DF";
when x"278" => DATA <= x"FD12";
when x"279" => DATA <= x"F5E0";
when x"27a" => DATA <= x"0BE6";
when x"27b" => DATA <= x"1026";
when x"27c" => DATA <= x"1D80";
when x"27d" => DATA <= x"0008";
when x"27e" => DATA <= x"1800";
when x"27f" => DATA <= x"45C0";
when x"280" => DATA <= x"FF00";
when x"281" => DATA <= x"6000";
when x"282" => DATA <= x"67C0";
when x"283" => DATA <= x"F5EE";
when x"284" => DATA <= x"1236";
when x"285" => DATA <= x"0002";
when x"286" => DATA <= x"1580";
when x"287" => DATA <= x"09DE";
when x"288" => DATA <= x"8405";
when x"289" => DATA <= x"17C6";
when x"28a" => DATA <= x"F5EC";
when x"28b" => DATA <= x"55F6";
when x"28c" => DATA <= x"0002";
when x"28d" => DATA <= x"0006";
when x"28e" => DATA <= x"8603";
when x"28f" => DATA <= x"55F6";
when x"290" => DATA <= x"0001";
when x"291" => DATA <= x"0006";
when x"292" => DATA <= x"159F";
when x"293" => DATA <= x"F5EC";
when x"294" => DATA <= x"159F";
when x"295" => DATA <= x"F5E0";
when x"296" => DATA <= x"0002";
when x"297" => DATA <= x"1D80";
when x"298" => DATA <= x"0006";
when x"299" => DATA <= x"1DB6";
when x"29a" => DATA <= x"0004";
when x"29b" => DATA <= x"0006";
when x"29c" => DATA <= x"0087";
when x"29d" => DATA <= x"0BD6";
when x"29e" => DATA <= x"159F";
when x"29f" => DATA <= x"F5EC";
when x"2a0" => DATA <= x"159F";
when x"2a1" => DATA <= x"F5E0";
when x"2a2" => DATA <= x"1026";
when x"2a3" => DATA <= x"810B";
when x"2a4" => DATA <= x"2017";
when x"2a5" => DATA <= x"0100";
when x"2a6" => DATA <= x"861B";
when x"2a7" => DATA <= x"6000";
when x"2a8" => DATA <= x"67C0";
when x"2a9" => DATA <= x"F5EE";
when x"2aa" => DATA <= x"1226";
when x"2ab" => DATA <= x"0BC1";
when x"2ac" => DATA <= x"0314";
when x"2ad" => DATA <= x"1048";
when x"2ae" => DATA <= x"0112";
when x"2af" => DATA <= x"0A40";
when x"2b0" => DATA <= x"2017";
when x"2b1" => DATA <= x"000A";
when x"2b2" => DATA <= x"860F";
when x"2b3" => DATA <= x"6000";
when x"2b4" => DATA <= x"6000";
when x"2b5" => DATA <= x"65C0";
when x"2b6" => DATA <= x"F5D8";
when x"2b7" => DATA <= x"1226";
when x"2b8" => DATA <= x"0BC1";
when x"2b9" => DATA <= x"0301";
when x"2ba" => DATA <= x"1048";
when x"2bb" => DATA <= x"0BD0";
when x"2bc" => DATA <= x"1226";
when x"2bd" => DATA <= x"0BC2";
when x"2be" => DATA <= x"0301";
when x"2bf" => DATA <= x"1088";
when x"2c0" => DATA <= x"1582";
when x"2c1" => DATA <= x"1581";
when x"2c2" => DATA <= x"1580";
when x"2c3" => DATA <= x"0002";
when x"2c4" => DATA <= x"0BC0";
when x"2c5" => DATA <= x"0304";
when x"2c6" => DATA <= x"2017";
when x"2c7" => DATA <= x"0003";
when x"2c8" => DATA <= x"871D";
when x"2c9" => DATA <= x"0303";
when x"2ca" => DATA <= x"0087";
when x"2cb" => DATA <= x"007F";
when x"2cc" => DATA <= x"F83E";
when x"2cd" => DATA <= x"0A00";
when x"2ce" => DATA <= x"15D0";
when x"2cf" => DATA <= x"FFC0";
when x"2d0" => DATA <= x"0A10";
when x"2d1" => DATA <= x"2017";
when x"2d2" => DATA <= x"0100";
when x"2d3" => DATA <= x"02FA";
when x"2d4" => DATA <= x"15DF";
when x"2d5" => DATA <= x"FCD4";
when x"2d6" => DATA <= x"001C";
when x"2d7" => DATA <= x"15DF";
when x"2d8" => DATA <= x"FCDC";
when x"2d9" => DATA <= x"0018";
when x"2da" => DATA <= x"15DF";
when x"2db" => DATA <= x"FFBC";
when x"2dc" => DATA <= x"0080";
when x"2dd" => DATA <= x"15DF";
when x"2de" => DATA <= x"00E0";
when x"2df" => DATA <= x"0082";
when x"2e0" => DATA <= x"15DF";
when x"2e1" => DATA <= x"FE9A";
when x"2e2" => DATA <= x"0084";
when x"2e3" => DATA <= x"15DF";
when x"2e4" => DATA <= x"00C0";
when x"2e5" => DATA <= x"0086";
when x"2e6" => DATA <= x"0C00";
when x"2e7" => DATA <= x"17DF";
when x"2e8" => DATA <= x"F5FA";
when x"2e9" => DATA <= x"F5FC";
when x"2ea" => DATA <= x"15C0";
when x"2eb" => DATA <= x"000C";
when x"2ec" => DATA <= x"15C1";
when x"2ed" => DATA <= x"FDFA";
when x"2ee" => DATA <= x"15C2";
when x"2ef" => DATA <= x"F5D8";
when x"2f0" => DATA <= x"8702";
when x"2f1" => DATA <= x"65C0";
when x"2f2" => DATA <= x"0018";
when x"2f3" => DATA <= x"1452";
when x"2f4" => DATA <= x"0AC0";
when x"2f5" => DATA <= x"02FD";
when x"2f6" => DATA <= x"8705";
when x"2f7" => DATA <= x"15C0";
when x"2f8" => DATA <= x"00F0";
when x"2f9" => DATA <= x"1252";
when x"2fa" => DATA <= x"0AC0";
when x"2fb" => DATA <= x"02FD";
when x"2fc" => DATA <= x"0087";
when x"2fd" => DATA <= x"F83E";
when x"2fe" => DATA <= x"0027";
when x"2ff" => DATA <= x"F896";
when x"300" => DATA <= x"F5FF";
when x"301" => DATA <= x"F880";
when x"302" => DATA <= x"F500";
when x"303" => DATA <= x"FD94";
when x"304" => DATA <= x"0000";
when x"305" => DATA <= x"FFC0";
when x"306" => DATA <= x"0000";
when x"307" => DATA <= x"0000";
when x"308" => DATA <= x"F600";
when x"309" => DATA <= x"F804";
when x"30a" => DATA <= x"0000";
when x"30b" => DATA <= x"0100";
when x"30c" => DATA <= x"F500";
when x"30d" => DATA <= x"F83E";
when x"30e" => DATA <= x"F83E";
when x"30f" => DATA <= x"F83E";
when x"310" => DATA <= x"0000";
when x"311" => DATA <= x"FD96";
when x"312" => DATA <= x"F8D4";
when x"313" => DATA <= x"FA56";
when x"314" => DATA <= x"FAD4";
when x"315" => DATA <= x"FCC6";
when x"316" => DATA <= x"FCBA";
when x"317" => DATA <= x"FC82";
when x"318" => DATA <= x"FC0E";
when x"319" => DATA <= x"FBB6";
when x"31a" => DATA <= x"FC78";
when x"31b" => DATA <= x"FC9C";
when x"31c" => DATA <= x"FC52";
when x"31d" => DATA <= x"FBE0";
when x"31e" => DATA <= x"FD88";
when x"31f" => DATA <= x"FD3A";
when x"320" => DATA <= x"FD2E";
when x"321" => DATA <= x"FD94";
when x"322" => DATA <= x"9440";
when x"323" => DATA <= x"09F7";
when x"324" => DATA <= x"002A";
when x"325" => DATA <= x"2017";
when x"326" => DATA <= x"000D";
when x"327" => DATA <= x"02FA";
when x"328" => DATA <= x"0087";
when x"329" => DATA <= x"6081";
when x"32a" => DATA <= x"9840";
when x"32b" => DATA <= x"09F7";
when x"32c" => DATA <= x"001A";
when x"32d" => DATA <= x"0AC2";
when x"32e" => DATA <= x"02FB";
when x"32f" => DATA <= x"0087";
when x"330" => DATA <= x"6081";
when x"331" => DATA <= x"09F7";
when x"332" => DATA <= x"FE2A";
when x"333" => DATA <= x"9021";
when x"334" => DATA <= x"0AC2";
when x"335" => DATA <= x"02FB";
when x"336" => DATA <= x"0087";
when x"337" => DATA <= x"09F7";
when x"338" => DATA <= x"0002";
when x"339" => DATA <= x"1040";
when x"33a" => DATA <= x"35DF";
when x"33b" => DATA <= x"0040";
when x"33c" => DATA <= x"FFF4";
when x"33d" => DATA <= x"03FC";
when x"33e" => DATA <= x"901F";
when x"33f" => DATA <= x"FFF6";
when x"340" => DATA <= x"0087";
when x"341" => DATA <= x"97C0";
when x"342" => DATA <= x"FFF0";
when x"343" => DATA <= x"80FD";
when x"344" => DATA <= x"97C0";
when x"345" => DATA <= x"FFF2";
when x"346" => DATA <= x"0087";
when x"347" => DATA <= x"97C0";
when x"348" => DATA <= x"FFFC";
when x"349" => DATA <= x"80FD";
when x"34a" => DATA <= x"97C0";
when x"34b" => DATA <= x"FFFE";
when x"34c" => DATA <= x"0087";
when x"34d" => DATA <= x"1026";
when x"34e" => DATA <= x"97C0";
when x"34f" => DATA <= x"FFFC";
when x"350" => DATA <= x"811C";
when x"351" => DATA <= x"97C0";
when x"352" => DATA <= x"FFF0";
when x"353" => DATA <= x"8103";
when x"354" => DATA <= x"1580";
when x"355" => DATA <= x"007F";
when x"356" => DATA <= x"F73A";
when x"357" => DATA <= x"97C0";
when x"358" => DATA <= x"FFF2";
when x"359" => DATA <= x"8110";
when x"35a" => DATA <= x"1066";
when x"35b" => DATA <= x"10A6";
when x"35c" => DATA <= x"09F7";
when x"35d" => DATA <= x"FFC6";
when x"35e" => DATA <= x"1002";
when x"35f" => DATA <= x"09F7";
when x"360" => DATA <= x"FFC0";
when x"361" => DATA <= x"1001";
when x"362" => DATA <= x"09F7";
when x"363" => DATA <= x"FFBA";
when x"364" => DATA <= x"09FF";
when x"365" => DATA <= x"F718";
when x"366" => DATA <= x"1582";
when x"367" => DATA <= x"1581";
when x"368" => DATA <= x"1580";
when x"369" => DATA <= x"0002";
when x"36a" => DATA <= x"09FF";
when x"36b" => DATA <= x"F704";
when x"36c" => DATA <= x"01FB";
when x"36d" => DATA <= x"1066";
when x"36e" => DATA <= x"97C0";
when x"36f" => DATA <= x"FFFE";
when x"370" => DATA <= x"8012";
when x"371" => DATA <= x"09F7";
when x"372" => DATA <= x"FDAA";
when x"373" => DATA <= x"17C1";
when x"374" => DATA <= x"F5E2";
when x"375" => DATA <= x"09F7";
when x"376" => DATA <= x"FDA2";
when x"377" => DATA <= x"9011";
when x"378" => DATA <= x"09F7";
when x"379" => DATA <= x"FD9C";
when x"37a" => DATA <= x"9011";
when x"37b" => DATA <= x"02FC";
when x"37c" => DATA <= x"1581";
when x"37d" => DATA <= x"1580";
when x"37e" => DATA <= x"17C0";
when x"37f" => DATA <= x"F5E2";
when x"380" => DATA <= x"17CE";
when x"381" => DATA <= x"F5E0";
when x"382" => DATA <= x"0002";
when x"383" => DATA <= x"1001";
when x"384" => DATA <= x"09F7";
when x"385" => DATA <= x"FF82";
when x"386" => DATA <= x"2057";
when x"387" => DATA <= x"0005";
when x"388" => DATA <= x"03DE";
when x"389" => DATA <= x"09F7";
when x"38a" => DATA <= x"FF78";
when x"38b" => DATA <= x"09F7";
when x"38c" => DATA <= x"FF74";
when x"38d" => DATA <= x"09F7";
when x"38e" => DATA <= x"FF70";
when x"38f" => DATA <= x"901F";
when x"390" => DATA <= x"F5EB";
when x"391" => DATA <= x"09F7";
when x"392" => DATA <= x"FF68";
when x"393" => DATA <= x"901F";
when x"394" => DATA <= x"F5EA";
when x"395" => DATA <= x"6041";
when x"396" => DATA <= x"1C5F";
when x"397" => DATA <= x"FFC2";
when x"398" => DATA <= x"0080";
when x"399" => DATA <= x"09F7";
when x"39a" => DATA <= x"FF58";
when x"39b" => DATA <= x"17C0";
when x"39c" => DATA <= x"F5EA";
when x"39d" => DATA <= x"2057";
when x"39e" => DATA <= x"0008";
when x"39f" => DATA <= x"031D";
when x"3a0" => DATA <= x"2057";
when x"3a1" => DATA <= x"000C";
when x"3a2" => DATA <= x"87C4";
when x"3a3" => DATA <= x"030A";
when x"3a4" => DATA <= x"15C1";
when x"3a5" => DATA <= x"0100";
when x"3a6" => DATA <= x"8BDF";
when x"3a7" => DATA <= x"FFF8";
when x"3a8" => DATA <= x"80FD";
when x"3a9" => DATA <= x"97D0";
when x"3aa" => DATA <= x"FFFA";
when x"3ab" => DATA <= x"0AC1";
when x"3ac" => DATA <= x"02F9";
when x"3ad" => DATA <= x"01B9";
when x"3ae" => DATA <= x"15C1";
when x"3af" => DATA <= x"0100";
when x"3b0" => DATA <= x"8BDF";
when x"3b1" => DATA <= x"FFF8";
when x"3b2" => DATA <= x"80FD";
when x"3b3" => DATA <= x"941F";
when x"3b4" => DATA <= x"FFFA";
when x"3b5" => DATA <= x"0AC1";
when x"3b6" => DATA <= x"02F9";
when x"3b7" => DATA <= x"8BDF";
when x"3b8" => DATA <= x"FFF8";
when x"3b9" => DATA <= x"80FD";
when x"3ba" => DATA <= x"8A1F";
when x"3bb" => DATA <= x"FFFA";
when x"3bc" => DATA <= x"01AA";
when x"3bd" => DATA <= x"101F";
when x"3be" => DATA <= x"F5F8";
when x"3bf" => DATA <= x"01A7";
when x"3c0" => DATA <= x"1026";
when x"3c1" => DATA <= x"17C0";
when x"3c2" => DATA <= x"F5EA";
when x"3c3" => DATA <= x"97D0";
when x"3c4" => DATA <= x"FFFA";
when x"3c5" => DATA <= x"97D0";
when x"3c6" => DATA <= x"FFFA";
when x"3c7" => DATA <= x"0113";
when x"3c8" => DATA <= x"1026";
when x"3c9" => DATA <= x"17C0";
when x"3ca" => DATA <= x"F5EA";
when x"3cb" => DATA <= x"941F";
when x"3cc" => DATA <= x"FFFA";
when x"3cd" => DATA <= x"941F";
when x"3ce" => DATA <= x"FFFA";
when x"3cf" => DATA <= x"010B";
when x"3d0" => DATA <= x"1026";
when x"3d1" => DATA <= x"17C0";
when x"3d2" => DATA <= x"F5EA";
when x"3d3" => DATA <= x"97D0";
when x"3d4" => DATA <= x"FFFA";
when x"3d5" => DATA <= x"0105";
when x"3d6" => DATA <= x"1026";
when x"3d7" => DATA <= x"17C0";
when x"3d8" => DATA <= x"F5EA";
when x"3d9" => DATA <= x"941F";
when x"3da" => DATA <= x"FFFA";
when x"3db" => DATA <= x"101F";
when x"3dc" => DATA <= x"F5EA";
when x"3dd" => DATA <= x"018A";
when x"3de" => DATA <= x"8A1F";
when x"3df" => DATA <= x"FFFA";
when x"3e0" => DATA <= x"0002";
when x"3e1" => DATA <= x"FFAC";
when x"3e2" => DATA <= x"FFA0";
when x"3e3" => DATA <= x"FF90";
when x"3e4" => DATA <= x"FF80";
when x"3e5" => DATA <= x"FFBC";
when x"3e6" => DATA <= x"FFBC";
when x"3e7" => DATA <= x"FFBC";
when x"3e8" => DATA <= x"FFBC";
when x"3e9" => DATA <= x"0000";
when x"3ea" => DATA <= x"0000";
when x"3eb" => DATA <= x"0000";
when x"3ec" => DATA <= x"0000";
when x"3ed" => DATA <= x"0000";
when x"3ee" => DATA <= x"0000";
when x"3ef" => DATA <= x"0000";
when x"3f0" => DATA <= x"0000";
when x"3f1" => DATA <= x"0000";
when x"3f2" => DATA <= x"0000";
when x"3f3" => DATA <= x"0000";
when x"3f4" => DATA <= x"0000";
when x"3f5" => DATA <= x"0000";
when x"3f6" => DATA <= x"0000";
when x"3f7" => DATA <= x"0000";
when x"3f8" => DATA <= x"0000";
when x"3f9" => DATA <= x"0000";
when x"3fa" => DATA <= x"0000";
when x"3fb" => DATA <= x"0000";
when x"3fc" => DATA <= x"0000";
when x"3fd" => DATA <= x"0000";
when x"3fe" => DATA <= x"0000";
when x"3ff" => DATA <= x"0000";
when others => DATA <= (others => '0');
end case;
end process;
end RTL;
| gpl-3.0 | bd19faa1c77594db3267caa4a3fcb37e | 0.38894 | 2.96617 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-avnet-eval-xc4vlx25/leon3mp.vhd | 1 | 21,946 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2006 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.net.all;
use gaisler.jtag.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
ddrfreq : integer := 100000 -- frequency of ddr clock in kHz
);
port (
resetn : in std_ulogic;
resoutn : out std_logic;
clk_100mhz : in std_ulogic;
errorn : out std_ulogic;
-- prom interface
address : out std_logic_vector(21 downto 0);
data : inout std_logic_vector(15 downto 0);
romsn : out std_ulogic;
oen : out std_ulogic;
writen : out std_ulogic;
romrstn : out std_ulogic;
-- pragma translate_off
iosn : out std_ulogic;
testdata : inout std_logic_vector(15 downto 0);
-- pragma translate_on
-- ddr memory
ddr_clk0 : out std_logic;
ddr_clk0b : out std_logic;
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke0 : out std_logic;
ddr_cs0b : out std_logic;
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (12 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (15 downto 0); -- ddr data
-- debug support unit
dsuen : in std_ulogic;
dsubre : in std_ulogic;
dsuact : out std_ulogic;
-- UART for serial DCL/console I/O
serrx : in std_ulogic;
sertx : out std_ulogic;
rtsn : out std_ulogic;
ctsn : in std_ulogic;
led_rx : out std_ulogic;
led_tx : out std_ulogic;
-- ethernet signals
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
emdc : out std_ulogic;
erstn : out std_ulogic;
-- OLED display signals
disp_dcn : out std_ulogic;
disp_csn : out std_ulogic;
disp_rdn : out std_ulogic;
disp_wrn : out std_ulogic;
disp_d : inout std_logic_vector(7 downto 0)
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdctrl_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal lclk : std_ulogic;
signal ddrclk, ddrrst, ddrclkfb : std_ulogic;
signal clkm, rstn, clkml, clk2x : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal tck, tms, tdi, tdo : std_ulogic;
-- signal dsubre : std_logic;
signal duart, ldsuen : std_logic;
signal rsertx, rserrx, rdsuen : std_logic;
signal rstraw : std_logic;
signal rstneg : std_logic;
signal rxd1 : std_logic;
signal txd1 : std_logic;
signal lock : std_logic;
signal ddr_clk : std_logic_vector(2 downto 0);
signal ddr_clkb : std_logic_vector(2 downto 0);
signal ddr_cke : std_logic_vector(1 downto 0);
signal ddr_csb : std_logic_vector(1 downto 0);
signal ddr_adl : std_logic_vector(13 downto 0); -- ddr address
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of lock : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute keep of lock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
constant BOARD_FREQ : integer := 100000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
begin
romrstn <= rstn;
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
rstneg <= not resetn;
rst0 : rstgen port map (rstneg, clkm, lock, rstn, rstraw);
clk_pad : clkpad generic map (tech => padtech) port map (clk_100mhz, lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, 0, 1, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd(0), clkm, open, open, open, open, cgi, cgo);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+1,
nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
leon3gen : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR,
CFG_NCPU-1, CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
error_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
-- dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 5, pindex => 0,
paddr => 0, srbanks => 1, ramaddr => 16#600#, rammask => 16#F00#, ram16 => 1 )
port map (rstn, clkm, memi, memo, ahbsi, ahbso(5), apbi, apbo(0), wpo, open);
end generate;
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
mg0 : if (CFG_MCTRL_LEON2 = 0) generate
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
roms_pad : outpad generic map (tech => padtech)
port map (romsn, vcc(0));
end generate;
mgpads : if (CFG_MCTRL_LEON2 /= 0) generate
addr_pad : outpadv generic map (width => 22, tech => padtech)
port map (address, memo.address(22 downto 1));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
-- pragma translate_off
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
tbdr : for i in 0 to 1 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (testdata(15-i*8 downto 8-i*8), memo.data(15-i*8 downto 8-i*8),
memo.bdrive(i+2), memi.data(15-i*8 downto 8-i*8));
end generate;
-- pragma translate_on
bdr : for i in 0 to 1 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (data(15-i*8 downto 8-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
end generate;
end generate;
----------------------------------------------------------------------
--- DDR memory controller -------------------------------------------
----------------------------------------------------------------------
ddrsp0 : if (CFG_DDRSP /= 0) generate
ddrc : ddrspa generic map ( fabtech => virtex4, memtech => memtech,
hindex => 4, haddr => 16#400#, hmask => 16#F00#, ioaddr => 1,
pwron => CFG_DDRSP_INIT, MHz => BOARD_FREQ/1000, rskew => -95
-- pragma translate_off
* 0 -- disable clock skew during simulation
-- pragma translate_on
, clkmul => CFG_DDRSP_FREQ/5, clkdiv => 20, col => CFG_DDRSP_COL,
Mbyte => CFG_DDRSP_SIZE, ahbfreq => CPU_FREQ/1000, ddrbits => 16)
port map (
rstneg, rstn, lclk, clkm, lock, clkml, clkml, ahbsi, ahbso(4),
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_adl, ddr_ba, ddr_dq);
ddr_clk0 <= ddr_clk(0); ddr_clk0b <= ddr_clkb(0);
ddr_cke0 <= ddr_cke(0); ddr_cs0b <= ddr_csb(0);
ddr_ad <= ddr_adl(12 downto 0);
end generate;
noddr : if (CFG_DDRSP = 0) generate lock <= '1'; end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti <= gpti_dhalt_drive(dsuo.tstop);
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
grgpio0: grgpio
generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK,
nbits => 12 --CFG_GRGPIO_WIDTH
)
port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo);
disp_csn_pad : outpad generic map (tech => padtech)
port map (disp_csn, gpioo.dout(8));
disp_dcn_pad : outpad generic map (tech => padtech)
port map (disp_dcn, gpioo.dout(9));
disp_rdn_pad : outpad generic map (tech => padtech)
port map (disp_rdn, gpioo.dout(10));
disp_wrn_pad : outpad generic map (tech => padtech)
port map (disp_wrn, gpioo.dout(11));
disp_d_pads : for i in 0 to 7 generate
pio_pad : iopad generic map (tech => padtech)
port map (disp_d(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 15, paddr => 15, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL,
phyrstadr => 3, giga => CFG_GRETH1G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), apbi => apbi,
apbo => apbo(15), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : inpad generic map (tech => padtech)
port map (etx_clk, ethi.tx_clk);
erxc_pad : inpad generic map (tech => padtech)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
erstn_pad : outpad generic map (tech => padtech)
port map (erstn, rstn);
end generate;
-----------------------------------------------------------------------
--- AHB DMA ----------------------------------------------------------
-----------------------------------------------------------------------
-- dma0 : ahbdma
-- generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH,
-- pindex => 12, paddr => 12, dbuf => 32)
-- port map (rstn, clkm, apbi, apbo(12), ahbmi,
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH));
--
-- at0 : ahbtrace
-- generic map ( hindex => 7, ioaddr => 16#200#, iomask => 16#E00#,
-- tech => memtech, irq => 0, kbytes => 8)
-- port map ( rstn, clkm, ahbmi, ahbsi, ahbso(7));
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 3, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+1) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-- nap0 : for i in 9 to NAPBSLV-1-CFG_GRETH generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
resoutn <= rstn;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 MP Demonstration design for Avnet Virtex4 Eval board",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
-- use switch 1 to multiplex DSU UART and UART1
dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, ldsuen);
duart <= rdsuen when CFG_AHB_UART /= 0 else '0';
rxd1 <= txd1 when duart = '1' else rserrx;
rsertx <= duo.txd when duart = '1' else txd1;
dui.rxd <= rserrx when duart = '1' else '1';
led_rx <= not rserrx;
p1 : process(clkm)
begin
if rising_edge(clkm) then
sertx <= rsertx; rserrx <= serrx; rdsuen <= ldsuen;
rtsn <= '0';
led_tx <= not rsertx;
end if;
end process;
end rtl;
| gpl-3.0 | edd3cf4017f5d881fdd5646b0cefe4db | 0.538868 | 3.733583 | false | false | false | false |
EliasLuiz/TCC | Teste/MemoTableTInputWay.vhd | 1 | 10,350 | -- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: MemoTableTInput.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any Input files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
use work.Constants.all;
use work.DefTypes.all;
ENTITY MemoTableTInputWay IS
--ENTITY TraceMemory IS
PORT
(
Clock : IN STD_LOGIC := '1';
WAddress : IN STD_LOGIC_VECTOR (MemoTableTWayAddressLenght-1 DOWNTO 0);
WData : IN MemoTableTInputEntry;
--WData : IN STD_LOGIC_VECTOR (MemoTableTInputEntryWidth-1 DOWNTO 0);
WEnable : IN STD_LOGIC := '0';
RAddress : IN STD_LOGIC_VECTOR (MemoTableTWayAddressLenght-1 DOWNTO 0);
RData : OUT MemoTableTInputEntry
--RData : OUT STD_LOGIC_VECTOR (MemoTableTInputEntryWidth-1 DOWNTO 0)
);
END MemoTableTInputWay;
--END TraceMemory;
ARCHITECTURE SYN OF MemoTableTInputWay IS
--ARCHITECTURE SYN OF TraceMemory IS
SIGNAL RAuxVector : STD_LOGIC_VECTOR (MemoTableTInputEntryWidth-1 DOWNTO 0);
SIGNAL WAuxObject : MemoTableTInputEntry;
SIGNAL WAuxVector : STD_LOGIC_VECTOR (MemoTableTInputEntryWidth-1 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_b : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_mixed_ports : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a: IN STD_LOGIC_VECTOR (MemoTableTWayAddressLenght-1 DOWNTO 0);
clock0 : IN STD_LOGIC;
data_a : IN STD_LOGIC_VECTOR (MemoTableTInputEntryWidth-1 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (MemoTableTInputEntryWidth-1 DOWNTO 0);
wren_a : IN STD_LOGIC;
address_b: IN STD_LOGIC_VECTOR (MemoTableTWayAddressLenght-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
--RData <= RAuxVector;
RData <= StdLogicToInput(RAuxVector);
--WAuxVector <= WData;
WAuxObject <= WData;
WAuxVector <= InputToStdLogic(WAuxObject);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK0",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
intended_device_family => "Cyclone II",
lpm_type => "altsyncram",
numwords_a => MemoTableTWayLenght,
numwords_b => MemoTableTWayLenght,
operation_mode => "DUAL_PORT",
outdata_aclr_b => "NONE",
outdata_reg_b => "CLOCK0",
power_up_uninitialized => "FALSE",
read_during_write_mode_mixed_ports => "DONT_CARE",
widthad_a => MemoTableTWayAddressLenght,
widthad_b => MemoTableTWayAddressLenght,
width_a => MemoTableTInputEntryWidth,
width_b => MemoTableTInputEntryWidth,
width_byteena_a => 1
)
PORT MAP (
address_a => WAddress,
clock0 => Clock,
data_a => WAuxVector,
wren_a => WEnable,
address_b => RAddress,
q_b => RAuxVector
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_Input_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_Input_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "4096"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "1"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "1"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "64"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "64"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "64"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "64"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_Input_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_Input_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "64"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "64"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "6"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "6"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "64"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "64"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 64 0 INPUT NODEFVAL "data[MemoTableTInputEntryWidth-1..0]"
-- Retrieval info: USED_PORT: q 0 0 64 0 Input NODEFVAL "q[MemoTableTInputEntryWidth-1..0]"
-- Retrieval info: USED_PORT: rdaddress 0 0 6 0 INPUT NODEFVAL "rdaddress[MemoTableTWayAddressLenght-1..0]"
-- Retrieval info: USED_PORT: wraddress 0 0 6 0 INPUT NODEFVAL "wraddress[MemoTableTWayAddressLenght-1..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
-- Retrieval info: CONNECT: @address_a 0 0 6 0 wraddress 0 0 6 0
-- Retrieval info: CONNECT: @address_b 0 0 6 0 rdaddress 0 0 6 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 64 0 data 0 0 64 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 64 0 @q_b 0 0 64 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL MemoTableTInput.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL MemoTableTInput.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL MemoTableTInput.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL MemoTableTInput.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL MemoTableTInput_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL MemoTableTInput_syn.v TRUE
-- Retrieval info: LIB_FILE: altera_mf
| gpl-3.0 | 063a6502cf404bc763fdfa6855241364 | 0.697681 | 3.370238 | false | false | false | false |
hoglet67/CoPro6502 | src/LX9Co_CoProZ80fast.vhd | 1 | 11,335 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity LX9CoProZ80fast is
generic (
UseT80Core : boolean := false;
UseNextCore : boolean := true
);
port (
-- GOP Signals
fastclk : in std_logic;
test : inout std_logic_vector(8 downto 1);
sw : in std_logic_vector(3 downto 0);
-- Tube signals (use 16 out of 22 DIL pins)
h_phi2 : in std_logic; -- 1,2,12,21,23 are global clocks
h_addr : in std_logic_vector(2 downto 0);
h_data : inout std_logic_vector(7 downto 0);
h_rdnw : in std_logic;
h_cs_b : in std_logic;
h_rst_b : in std_logic;
h_irq_b : inout std_logic;
-- Ram Signals
ram_ub_b : out std_logic;
ram_lb_b : out std_logic;
ram_cs : out std_logic;
ram_oe : out std_logic;
ram_wr : out std_logic;
ram_addr : out std_logic_vector (18 downto 0);
ram_data : inout std_logic_vector (7 downto 0)
);
end LX9CoProZ80fast;
architecture BEHAVIORAL of LX9CoProZ80fast is
-------------------------------------------------
-- clock and reset signals
-------------------------------------------------
signal cpu_clk : std_logic;
signal cpu_clken : std_logic;
signal bootmode : std_logic;
signal RSTn : std_logic;
signal RSTn_sync : std_logic;
signal clken_counter : std_logic_vector (3 downto 0);
-------------------------------------------------
-- parasite signals
-------------------------------------------------
signal p_cs_b : std_logic;
signal tube_cs_b : std_logic;
signal p_data_out : std_logic_vector (7 downto 0);
-------------------------------------------------
-- ram/rom signals
-------------------------------------------------
signal ram_cs_b : std_logic;
signal ram_oe_int : std_logic;
signal ram_wr_int : std_logic;
signal rom_cs_b : std_logic;
signal rom_data_out : std_logic_vector (7 downto 0);
signal ram_data_out : std_logic_vector (7 downto 0);
-------------------------------------------------
-- cpu signals
-------------------------------------------------
signal cpu_rd_n : std_logic;
signal cpu_wr_n : std_logic;
signal cpu_iorq_n : std_logic;
signal cpu_mreq_n : std_logic;
signal cpu_m1_n : std_logic;
signal cpu_addr : std_logic_vector (15 downto 0);
signal cpu_din : std_logic_vector (7 downto 0);
signal cpu_dout : std_logic_vector (7 downto 0);
signal cpu_IRQ_n : std_logic;
signal cpu_NMI_n : std_logic;
signal cpu_IRQ_n_sync : std_logic;
signal cpu_NMI_n_sync : std_logic;
signal cpu_m1 : std_logic;
signal cpu_mreq : std_logic;
signal cpu_iorq : std_logic;
signal cpu_wr : std_logic;
signal digit1_cs_b : std_logic;
signal digit2_cs_b : std_logic;
signal digit3_cs_b : std_logic;
signal digit1 : std_logic_vector (7 downto 0);
signal digit2 : std_logic_vector (7 downto 0);
signal digit3 : std_logic_vector (7 downto 0);
signal sw_out : std_logic_vector (3 downto 0);
begin
---------------------------------------------------------------------
-- instantiated components
---------------------------------------------------------------------
inst_ICAP_config : entity work.ICAP_config port map (
fastclk => fastclk,
sw_in => sw,
sw_out => sw_out,
h_addr => h_addr,
h_cs_b => h_cs_b,
h_data => h_data,
h_phi2 => h_phi2,
h_rdnw => h_rdnw,
h_rst_b => h_rst_b
);
inst_dcm_32_56 : entity work.dcm_32_56 port map (
CLKIN_IN => fastclk,
CLK0_OUT => cpu_clk,
CLK0_OUT1 => open,
CLK2X_OUT => open
);
inst_tuberom : entity work.tuberom_z80_banner port map (
CLK => cpu_clk,
ADDR => cpu_addr(11 downto 0),
DATA => rom_data_out
);
GenT80Core: if UseT80Core generate
inst_Z80 : entity work.T80se port map (
RESET_n => RSTn_sync,
CLK_n => cpu_clk,
CLKEN => cpu_clken,
WAIT_n => '1',
INT_n => cpu_IRQ_n_sync,
NMI_n => cpu_NMI_n_sync,
BUSRQ_n => '1',
M1_n => cpu_m1_n,
MREQ_n => cpu_mreq_n,
IORQ_n => cpu_iorq_n,
RD_n => cpu_rd_n,
WR_n => cpu_wr_n,
RFSH_n => open,
HALT_n => open,
BUSAK_n => open,
A => cpu_addr,
DI => cpu_din,
DO => cpu_dout
);
end generate;
GenNextCore: if UseNextCore generate
Inst_Z80: entity work.NextZ80 PORT MAP(
RESET => not RSTn_sync,
CLK => cpu_clk,
WT => not cpu_clken,
INT => not cpu_IRQ_n_sync,
NMI => not cpu_NMI_n_sync,
M1 => cpu_m1,
MREQ => cpu_mreq,
IORQ => cpu_iorq,
WR => cpu_wr,
HALT => open,
ADDR => cpu_addr,
DI => cpu_din,
DO => cpu_dout
);
cpu_m1_n <= not cpu_m1;
cpu_mreq_n <= not cpu_mreq;
cpu_iorq_n <= not cpu_iorq;
cpu_rd_n <= cpu_wr;
cpu_wr_n <= not cpu_wr;
end generate;
inst_tube: entity work.tube port map (
h_addr => h_addr,
h_cs_b => h_cs_b,
h_data => h_data,
h_phi2 => h_phi2,
h_rdnw => h_rdnw,
h_rst_b => h_rst_b,
h_irq_b => h_irq_b,
p_addr => cpu_addr(2 downto 0),
p_cs_b => tube_cs_b,
p_data_in => cpu_dout,
p_data_out => p_data_out,
p_phi2 => cpu_clk,
p_rdnw => cpu_wr_n,
p_rst_b => RSTn,
p_nmi_b => cpu_NMI_n,
p_irq_b => cpu_IRQ_n
);
tube_cs_b <= not ((not p_cs_b) and cpu_clken);
Inst_RAM_64K: entity work.RAM_64K PORT MAP(
clk => cpu_clk,
we_uP => ram_wr_int,
ce => '1',
addr_uP => cpu_addr,
D_uP => cpu_dout,
Q_uP => ram_data_out
);
p_cs_b <= '0' when cpu_mreq_n = '1' and cpu_iorq_n = '0' and cpu_addr(7 downto 3) = "00000" else '1';
rom_cs_b <= '0' when cpu_mreq_n = '0' and cpu_rd_n = '0' and bootmode = '1' else '1';
digit1_cs_b <= '0' when rom_cs_b = '0' and cpu_addr(11 downto 0) = x"2A2" else '1';
digit2_cs_b <= '0' when rom_cs_b = '0' and cpu_addr(11 downto 0) = x"2A3" else '1';
digit3_cs_b <= '0' when rom_cs_b = '0' and cpu_addr(11 downto 0) = x"2A4" else '1';
-- Original: Acorn TUBE Z80 64k 1.21
-- Updated: Acorn TUBE Z80 112 Mhz
digit1 <= x"31" when sw_out(1 downto 0) = "11" else
x"06";
digit2 <= x"31" when sw_out(1 downto 0) = "11" else
x"35" when sw_out(1 downto 0) = "10" else
x"33" when sw_out(1 downto 0) = "01" else
x"31";
digit3 <= x"32" when sw_out(1 downto 0) = "11" else
x"36" when sw_out(1 downto 0) = "10" else
x"32" when sw_out(1 downto 0) = "01" else
x"36";
ram_cs_b <= '0' when cpu_mreq_n = '0' and rom_cs_b = '1' else '1';
ram_wr_int <= ((not ram_cs_b) and (not cpu_wr_n) and cpu_clken);
cpu_din <=
p_data_out when p_cs_b = '0' else
digit1 when digit1_cs_b = '0' else
digit2 when digit2_cs_b = '0' else
digit3 when digit3_cs_b = '0' else
rom_data_out when rom_cs_b = '0' else
ram_data_out when ram_cs_b = '0' else
x"fe";
--------------------------------------------------------
-- external Ram unused
--------------------------------------------------------
ram_ub_b <= '1';
ram_lb_b <= '1';
ram_cs <= '1';
ram_oe <= '1';
ram_wr <= '1';
ram_addr <= (others => '1');
ram_data <= (others => '1');
--------------------------------------------------------
-- test signals
--------------------------------------------------------
-- default to hi-impedence, to avoid conflicts with
-- a Raspberry Pi connected to the test connector
test <= (others => 'Z');
--------------------------------------------------------
-- boot mode generator
--------------------------------------------------------
boot_gen : process(cpu_clk, RSTn_sync)
begin
if RSTn_sync = '0' then
bootmode <= '1';
elsif rising_edge(cpu_clk) then
if (cpu_mreq_n = '0' and cpu_m1_n = '0') then
if (cpu_addr = x"0066") then
bootmode <= '1';
elsif cpu_addr(15) = '1' then
bootmode <= '0';
end if;
end if;
end if;
end process;
--------------------------------------------------------
-- synchronize interrupts etc into Z80 core
--------------------------------------------------------
sync_gen : process(cpu_clk, RSTn_sync)
begin
if RSTn_sync = '0' then
cpu_NMI_n_sync <= '1';
cpu_IRQ_n_sync <= '1';
elsif rising_edge(cpu_clk) then
if (cpu_clken = '1') then
cpu_NMI_n_sync <= cpu_NMI_n;
cpu_IRQ_n_sync <= cpu_IRQ_n;
end if;
end if;
end process;
--------------------------------------------------------
-- clock enable generator
-- 00 - 28MHz = 56 / 2
-- 01 - 14MHz = 56 / 4
-- 10 - 08MHz = 56 / 7
-- 11 - 04MHz = 56 / 14
--------------------------------------------------------
clk_gen : process(cpu_clk)
begin
if rising_edge(cpu_clk) then
case "00" & sw_out(1 downto 0) is
when x"3" =>
if (clken_counter = 1) then
clken_counter <= (others => '0');
else
clken_counter <= clken_counter + 1;
end if;
when x"2" =>
if (clken_counter = 3) then
clken_counter <= (others => '0');
else
clken_counter <= clken_counter + 1;
end if;
when x"1" =>
if (clken_counter = 6) then
clken_counter <= (others => '0');
else
clken_counter <= clken_counter + 1;
end if;
when others =>
if (clken_counter = 13) then
clken_counter <= (others => '0');
else
clken_counter <= clken_counter + 1;
end if;
end case;
cpu_clken <= not clken_counter(3) and not clken_counter(2) and not clken_counter(1) and not clken_counter(0);
RSTn_sync <= RSTn;
end if;
end process;
end BEHAVIORAL;
| gpl-3.0 | 67a36a9762c942b4a1dcc8c17b6539af | 0.421791 | 3.531153 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/sim/sdrtestmod.vhd | 1 | 5,696 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: sdrtestmod
-- File: sdrtestmod.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Test report module with SDRAM interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.sim.all;
entity sdrtestmod is
generic (
width: integer := 32; -- 32-bit or 64-bit supported
bank: integer range 0 to 3 := 0;
row: integer := 0;
halt: integer range 0 to 1 := 1;
swwidth: integer := 32 -- Internal reportdev size, can be 32/64
);
port (
clk: in std_ulogic;
csn: in std_ulogic;
rasn: in std_ulogic;
casn: in std_ulogic;
wen: in std_ulogic;
ba: in std_logic_vector(1 downto 0);
addr: in std_logic_vector(12 downto 0);
dq: inout std_logic_vector(width-1 downto 0);
dqm: in std_logic_vector(width/8-1 downto 0)
);
end;
architecture sim of sdrtestmod is
begin
dq <= (others => 'Z');
p: process(clk)
variable modereg: std_logic_vector(12 downto 0);
variable myrow: boolean := false;
variable wrburst: integer := 0;
variable wrcol: integer;
variable i,j,k: integer;
variable d: std_logic_vector(31 downto 0);
variable errcnt, vendorid, deviceid : integer;
procedure write_main(addr: integer; d: std_logic_vector) is
variable errno, subtest : integer;
begin
case i is
when 0 =>
vendorid := conv_integer(d(31 downto 24));
deviceid := conv_integer(d(23 downto 12));
print(iptable(vendorid).device_table(deviceid));
when 1 =>
errno := conv_integer(d(15 downto 0));
if (halt = 1) then
assert false
report "test failed, error (" & tost(errno) & ")"
severity failure;
else
assert false
report "test failed, error (" & tost(errno) & ")"
severity warning;
end if;
when 2 =>
subtest := conv_integer(d(7 downto 0));
call_subtest(vendorid, deviceid, subtest);
when 4 =>
print ("");
print ("**** GRLIB system test starting ****");
errcnt := 0;
when 5 =>
if errcnt = 0 then
print ("Test passed, halting with IU error mode");
elsif errcnt = 1 then
print ("1 error detected, halting with IU error mode");
else
print (tost(errcnt) & " errors detected, halting with IU error mode");
end if;
print ("");
when 6 =>
grlib.testlib.print("Checkpoint " & tost(conv_integer(d(15 downto 0))));
when 7 =>
vendorid := 0; deviceid := 0;
print ("Basic memory test");
when others =>
end case;
end write_main;
begin
if rising_edge(clk) then
if csn='0' then
if rasn='0' and casn='0' and wen='0' then
modereg := addr;
elsif rasn='0' and casn='1' and wen='1' then
if ba=conv_std_logic_vector(bank,2) and addr=conv_std_logic_vector(row,13) then
myrow := true;
else
myrow := false;
end if;
elsif rasn='1' and casn='0' and wen='0' then
if myrow then
if modereg(9)='0' and modereg(2 downto 0)="001" then
wrburst := 2;
elsif modereg(9)='0' and modereg(2 downto 0)="010" then
wrburst := 4;
elsif modereg(9)='0' and (modereg(2 downto 0)="011" or modereg(2)='1') then
wrburst := 8;
else
wrburst := 1;
end if;
wrcol := conv_integer(addr(7 downto 0));
end if;
elsif rasn='0' and casn='1' and wen='0' then
if ba=conv_std_logic_vector(bank,2) or addr(10)='1' then
myrow := false;
wrburst := 0;
end if;
end if;
end if;
if wrburst > 0 then
for x in 0 to (width/32)-1 loop
if width=32 and swwidth=64 and (wrcol mod 2 < 1) then next; end if;
if width=64 and swwidth=64 and x=0 then next; end if;
if dqm(width/8-1-x*4 downto width/8-4-x*4) = "0000" then
i := (wrcol*width)/swwidth + (x*32)/swwidth;
d := dq(width-1-x*32 downto width-32-x*32);
if d /= x"DEADBEEF" then
write_main(i,d);
end if;
end if;
end loop;
wrburst := wrburst-1;
wrcol := wrcol+1;
end if;
end if;
end process;
end;
| gpl-3.0 | 783332217f77c5e7429039e373760cc6 | 0.545471 | 3.961057 | false | true | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/ec/ddr_ec.vhd | 1 | 2,087 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr_ec
-- File: ddr_ec.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Lattice DDR regs
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.ODDRXB;
--pragma translate_on
entity ec_oddr_reg is
port
( Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end;
architecture rtl of ec_oddr_reg is
component ODDRXB
port(
DA : in STD_LOGIC;
DB : in STD_LOGIC;
CLK : in STD_LOGIC;
LSR : in STD_LOGIC;
Q : out STD_LOGIC
);
end component;
begin
U0 : ODDRXB port map( DA => D1, DB => D2, CLK => C1, LSR => R, Q => Q);
end;
| gpl-3.0 | a666f5015e0d2a924b2c50a09cc1f04a | 0.541447 | 4.100196 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/stratixiv/ddr_uniphy.vhd | 1 | 15,954 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: uniphy_ddr2_phy
-- File: ddr_uniphy.vhd
-- Contact: [email protected]
-- Description: DDR2 PHY for Altera Stratix 4
-- Wrapper for Uniphy entity
-- generated from /boards/terasic-de4/uniphy_*.vhd
-- Author: Andrea Gianarro, Cobham Gaisler
-- Pascal Trotta
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
entity uniphy_ddr2_phy is
generic (
MHz : integer := 100;
rstdelay : integer := 200;
dbits : integer := 16;
clk_mul : integer := 2;
clk_div : integer := 2;
eightbanks : integer range 0 to 1 := 0;
abits : integer := 14;
nclk : integer := 3;
ncs : integer := 2);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
-- for operating without PLL
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqsn
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
addr : in std_logic_vector (abits-1 downto 0); -- ddr address
ba : in std_logic_vector ( 2 downto 0); -- ddr bank address
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
odt : in std_logic_vector(ncs-1 downto 0);
read_pend : in std_logic_vector(7 downto 0);
regwdata : in std_logic_vector(63 downto 0);
regwrite : in std_logic_vector(1 downto 0);
regrdata : out std_logic_vector(63 downto 0);
dqin_valid : out std_ulogic;
oct_rdn : in std_logic := '0';
oct_rup : in std_logic := '0'
);
end;
architecture rtl of uniphy_ddr2_phy is
component uniphy is
port (
pll_ref_clk : in std_logic := '0'; -- pll_ref_clk.clk
global_reset_n : in std_logic := '0'; -- global_reset.reset_n
soft_reset_n : in std_logic := '0'; -- soft_reset.reset_n
afi_clk : out std_logic; -- afi_clk.clk
afi_half_clk : out std_logic; -- afi_half_clk.clk
afi_reset_n : out std_logic; -- afi_reset.reset_n
afi_reset_export_n : out std_logic; -- afi_reset_export.reset_n
mem_a : out std_logic_vector(13 downto 0); -- memory.mem_a
mem_ba : out std_logic_vector(2 downto 0); -- .mem_ba
mem_ck : out std_logic_vector(1 downto 0); -- .mem_ck
mem_ck_n : out std_logic_vector(1 downto 0); -- .mem_ck_n
mem_cke : out std_logic_vector(0 downto 0); -- .mem_cke
mem_cs_n : out std_logic_vector(0 downto 0); -- .mem_cs_n
mem_dm : out std_logic_vector(7 downto 0); -- .mem_dm
mem_ras_n : out std_logic_vector(0 downto 0); -- .mem_ras_n
mem_cas_n : out std_logic_vector(0 downto 0); -- .mem_cas_n
mem_we_n : out std_logic_vector(0 downto 0); -- .mem_we_n
mem_dq : inout std_logic_vector(63 downto 0) := (others => '0'); -- .mem_dq
mem_dqs : inout std_logic_vector(7 downto 0) := (others => '0'); -- .mem_dqs
mem_dqs_n : inout std_logic_vector(7 downto 0) := (others => '0'); -- .mem_dqs_n
mem_odt : out std_logic_vector(0 downto 0); -- .mem_odt
afi_addr : in std_logic_vector(13 downto 0) := (others => '0'); -- afi.afi_addr
afi_ba : in std_logic_vector(2 downto 0) := (others => '0'); -- .afi_ba
afi_cke : in std_logic_vector(0 downto 0) := (others => '0'); -- .afi_cke
afi_cs_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .afi_cs_n
afi_ras_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .afi_ras_n
afi_we_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .afi_we_n
afi_cas_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .afi_cas_n
afi_odt : in std_logic_vector(0 downto 0) := (others => '0'); -- .afi_odt
afi_dqs_burst : in std_logic_vector(7 downto 0) := (others => '0'); -- .afi_dqs_burst
afi_wdata_valid : in std_logic_vector(7 downto 0) := (others => '0'); -- .afi_wdata_valid
afi_wdata : in std_logic_vector(127 downto 0) := (others => '0'); -- .afi_wdata
afi_dm : in std_logic_vector(15 downto 0) := (others => '0'); -- .afi_dm
afi_rdata : out std_logic_vector(127 downto 0); -- .afi_rdata
afi_rdata_en : in std_logic_vector(0 downto 0) := (others => '0'); -- .afi_rdata_en
afi_rdata_en_full : in std_logic_vector(0 downto 0) := (others => '0'); -- .afi_rdata_en_full
afi_rdata_valid : out std_logic_vector(0 downto 0); -- .afi_rdata_valid
afi_mem_clk_disable : in std_logic_vector(1 downto 0) := (others => '0'); -- .afi_mem_clk_disable
afi_init_req : in std_logic := '0'; -- .afi_init_req
afi_cal_req : in std_logic := '0'; -- .afi_cal_req
afi_wlat : out std_logic_vector(5 downto 0); -- .afi_wlat
afi_rlat : out std_logic_vector(5 downto 0); -- .afi_rlat
afi_cal_success : out std_logic; -- .afi_cal_success
afi_cal_fail : out std_logic; -- .afi_cal_fail
oct_rdn : in std_logic := '0'; -- oct.rdn
oct_rup : in std_logic := '0' -- .rup
);
end component;
signal vcc, gnd : std_logic;
signal vccv: std_logic_vector(4 downto 0);
signal gndv: std_logic_vector(4 downto 0);
signal clk0,clk0d: std_ulogic;
signal lrst: std_ulogic;
signal locki: std_logic;
signal pllcgi: clkgen_in_type;
signal pllcgo: clkgen_out_type;
signal rstdelay_arst: std_logic;
signal rstdelay_count: std_logic_vector(16 downto 0);
signal rstdelay_done: std_logic;
signal dfi_address, dfi_address_in: std_logic_vector(abits-1 downto 0);
signal dfi_ras_n, dfi_ras_n_in: std_logic_vector(0 downto 0);
signal dfi_cas_n, dfi_cas_n_in: std_logic_vector(0 downto 0);
signal dfi_we_n, dfi_we_n_in: std_logic_vector(0 downto 0);
signal dfi_bank, dfi_bank_in: std_logic_vector(1+eightbanks downto 0);
signal dfi_cs_n, dfi_cs_n_in: std_logic_vector(ncs-1 downto 0);
signal oe: std_ulogic;
signal cken: std_ulogic;
signal dfi_rddata_en: std_logic_vector(0 downto 0);
signal dfi_rddata_valid: std_logic_vector(0 downto 0);
signal dfi_dram_clk_disable: std_logic_vector(1 downto 0);
signal dfi_wrdata_en, dfi_wrdata_en_in: std_logic_vector(0 downto 0);
signal dfi_rddata, dfi_wrdata, dfi_wrdata_in: std_logic_vector(2*dbits-1 downto 0);
signal dfi_wrdata_mask, dfi_wrdata_mask_in: std_logic_vector(dbits/4-1 downto 0);
signal afi_dqs_burst_l, afi_wdata_valid_l : std_logic_vector(7 downto 0);
signal afi_wlat_l, afi_rlat_l : std_logic_vector(5 downto 0);
signal cal_succ_i : std_logic;
signal ddr_rasb_l, ddr_casb_l, ddr_web_l : std_logic_vector(0 downto 0);
begin
vcc <= '1';
gnd <= '0';
gndv <= "00000";
vccv <= "11111";
oe <= not oen;
cken <= not cke(0);
dfi_dram_clk_disable <= (others => cken);
dfi_wrdata_en_in <= (others => oe);
dqin_valid <= dfi_rddata_valid(0);
afi_dqs_burst_l <= ( others => (dfi_wrdata_en(0) or dfi_wrdata_en_in(0)));
afi_wdata_valid_l <= ( others => dfi_wrdata_en(0) );
-----------------------------------------------------------------------------
-- Reset delay with async reset
-----------------------------------------------------------------------------
rstdelay_arst <= rst and locki and cal_succ_i;
lrst <= rstdelay_done;
lock <= lrst;
rstdelproc: process(clkoutret,rstdelay_arst)
begin
if rising_edge(clkoutret) then
if rstdelay_done='0' then
rstdelay_count <= std_logic_vector(unsigned(rstdelay_count)-1);
end if;
if rstdelay_count=std_logic_vector(to_unsigned(0,rstdelay_count'length)) then
rstdelay_done <= '1';
end if;
end if;
if rstdelay_arst='0' then
rstdelay_count <= std_logic_vector(to_unsigned(rstdelay*MHz*clk_mul/clk_div,rstdelay_count'length));
rstdelay_done <= '0';
end if;
end process;
regrdata(63 downto 6) <= ( others => '0' );
regrdata(5 downto 0) <= afi_wlat_l;
dfi_rddata_en <= (others => read_pend(1));
regs: process(clkoutret, rstdelay_arst)
begin
if rising_edge(clkoutret) then
dfi_wrdata <= dfi_wrdata_in;
dfi_wrdata_mask <= dfi_wrdata_mask_in;
dfi_wrdata_en <= dfi_wrdata_en_in;
dfi_address <= dfi_address_in;
dfi_bank <= dfi_bank_in;
dfi_cas_n <= dfi_cas_n_in;
dfi_cs_n <= dfi_cs_n_in;
dfi_ras_n <= dfi_ras_n_in;
dfi_we_n <= dfi_we_n_in;
end if;
end process;
-----------------------------------------------------------------------------
-- Altera Uniphy DDR2 PHY instantiation
-----------------------------------------------------------------------------
-- NOTE: The phy reads and sends the lower part of the data vectors first
-- (on the rising edge of dqs) and higher part second (on the falling edge of dqs).
-- We swap this in both directions to match the memory simulation models and
-- our other PHY:s.
dqin <= dfi_rddata(dbits-1 downto 0) & dfi_rddata(2*dbits-1 downto dbits);
dfi_wrdata_in <= dqout(dbits-1 downto 0) & dqout(2*dbits-1 downto dbits);
dfi_wrdata_mask_in <= dm(dbits/8-1 downto 0) & dm(dbits/4-1 downto dbits/8);
dfi_cs_n_in <= csn;
dfi_address_in(abits-1 downto 0) <= addr;
dfi_bank_in(1+eightbanks downto 0) <= ba(1+eightbanks downto 0);
dfi_ras_n_in <= (others => rasn);
dfi_cas_n_in <= (others => casn);
dfi_we_n_in <= (others => wen);
phy: uniphy
port map (
pll_ref_clk => clk,
global_reset_n => rst,
soft_reset_n => rst,
afi_clk => clkout,
afi_half_clk => open,
afi_reset_n => locki,
afi_reset_export_n => open,
mem_a => ddr_ad,
mem_ba => ddr_ba,
mem_ck => ddr_clk,
mem_ck_n => ddr_clkb,
mem_cke => ddr_cke,
mem_cs_n => ddr_csb,
mem_dm => ddr_dm,
mem_ras_n => ddr_rasb_l,
mem_cas_n => ddr_casb_l,
mem_we_n => ddr_web_l,
mem_dq => ddr_dq,
mem_dqs => ddr_dqs,
mem_dqs_n => ddr_dqsn,
mem_odt => ddr_odt,
afi_addr => dfi_address,
afi_ba => dfi_bank,
afi_cke => cke,
afi_cs_n => dfi_cs_n,
afi_ras_n => dfi_ras_n,
afi_we_n => dfi_we_n,
afi_cas_n => dfi_cas_n,
afi_odt => odt,
afi_dqs_burst => afi_dqs_burst_l,
afi_wdata_valid => afi_wdata_valid_l,
afi_wdata => dfi_wrdata,
afi_dm => dfi_wrdata_mask,
afi_rdata => dfi_rddata,
afi_rdata_en => dfi_rddata_en,
afi_rdata_en_full => dfi_rddata_en,
afi_rdata_valid => dfi_rddata_valid,
afi_mem_clk_disable => dfi_dram_clk_disable,
afi_init_req => '0',
afi_cal_req => '0',
afi_wlat => afi_wlat_l,
afi_rlat => afi_rlat_l,
afi_cal_success => cal_succ_i,
afi_cal_fail => open,
oct_rdn => oct_rdn,
oct_rup => oct_rup
);
ddr_web <= ddr_web_l(0);
ddr_rasb <= ddr_rasb_l(0);
ddr_casb <= ddr_casb_l(0);
end;
| gpl-3.0 | ed549eaf6a6ad308d940559ad28e54df | 0.478125 | 3.594053 | false | false | false | false |
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