repo_name
stringlengths 6
79
| path
stringlengths 6
236
| copies
int64 1
472
| size
int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
| ratio
float64 1.51
17.5
| autogenerated
bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
hoglet67/CoPro6502 | src/DCM/dcm_32_8.vhd | 1 | 2,061 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity dcm_32_8 is
port (CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic);
end dcm_32_8;
architecture BEHAVIORAL of dcm_32_8 is
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKFX_BUFG_INST : BUFG
port map (I => CLKFX_BUF, O => CLK0_OUT);
DCM_INST : DCM
generic map(CLK_FEEDBACK => "NONE",
CLKDV_DIVIDE => 4.0, -- 8.000 = 32.000 * 5/20
CLKFX_DIVIDE => 20,
CLKFX_MULTIPLY => 5,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => 31.25,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => true,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => false)
port map (CLKFB => GND_BIT,
CLKIN => CLKIN_IN,
DSSEN => GND_BIT,
PSCLK => GND_BIT,
PSEN => GND_BIT,
PSINCDEC => GND_BIT,
RST => GND_BIT,
CLKDV => open,
CLKFX => CLKFX_BUF,
CLKFX180 => open,
CLK0 => open,
CLK2X => open,
CLK2X180 => open,
CLK90 => open,
CLK180 => open,
CLK270 => open,
LOCKED => open,
PSDONE => open,
STATUS => open);
end BEHAVIORAL;
| gpl-3.0 | 59babaa818a695c6abdab0477d132cc0 | 0.403688 | 4.223361 | false | false | false | false |
18545/FPGA | src/debounce_joystick.vhd | 1 | 902 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Description: Convert the push button to a 1PPS that can be used to restart
-- camera initialisation
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity debounce_joystick is
Port ( clk : in STD_LOGIC;
i : in STD_LOGIC;
o : out STD_LOGIC);
end debounce_joystick;
architecture Behavioral of debounce_joystick is
signal c : unsigned(23 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if i = '1' then
if c = x"00FFFF" then
o <= '1';
else
o <= '0';
end if;
c <= c+1;
else
c <= (others => '0');
o <= '0';
end if;
end if;
end process;
end Behavioral;
| mit | ca9c1cb6b50d7192c3d6f3c6aa1ed5e7 | 0.486696 | 3.681633 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-terasic-sockit/ddr3sim.vhd | 1 | 11,132 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.stdio.all;
entity ddr3controller_0002 is
port (
pll_ref_clk : in std_logic := 'X'; -- clk
global_reset_n : in std_logic := 'X'; -- reset_n
soft_reset_n : in std_logic := 'X'; -- reset_n
afi_clk : out std_logic; -- clk
afi_half_clk : out std_logic; -- clk
afi_reset_n : out std_logic; -- reset_n
afi_reset_export_n : out std_logic; -- reset_n
mem_a : out std_logic_vector(14 downto 0); -- mem_a
mem_ba : out std_logic_vector(2 downto 0); -- mem_ba
mem_ck : out std_logic_vector(0 downto 0); -- mem_ck
mem_ck_n : out std_logic_vector(0 downto 0); -- mem_ck_n
mem_cke : out std_logic_vector(0 downto 0); -- mem_cke
mem_cs_n : out std_logic_vector(0 downto 0); -- mem_cs_n
mem_dm : out std_logic_vector(3 downto 0); -- mem_dm
mem_ras_n : out std_logic_vector(0 downto 0); -- mem_ras_n
mem_cas_n : out std_logic_vector(0 downto 0); -- mem_cas_n
mem_we_n : out std_logic_vector(0 downto 0); -- mem_we_n
mem_reset_n : out std_logic; -- mem_reset_n
mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq
mem_dqs : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs
mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_n
mem_odt : out std_logic_vector(0 downto 0); -- mem_odt
avl_ready : out std_logic; -- waitrequest_n
avl_burstbegin : in std_logic := 'X'; -- beginbursttransfer
avl_addr : in std_logic_vector(25 downto 0) := (others => 'X'); -- address
avl_rdata_valid : out std_logic; -- readdatavalid
avl_rdata : out std_logic_vector(127 downto 0); -- readdata
avl_wdata : in std_logic_vector(127 downto 0) := (others => 'X'); -- writedata
avl_be : in std_logic_vector(15 downto 0) := (others => 'X'); -- byteenable
avl_read_req : in std_logic := 'X'; -- read
avl_write_req : in std_logic := 'X'; -- write
avl_size : in std_logic_vector(3 downto 0) := (others => 'X'); -- burstcount
local_init_done : out std_logic; -- local_init_done
local_cal_success : out std_logic; -- local_cal_success
local_cal_fail : out std_logic; -- local_cal_fail
oct_rzqin : in std_logic := 'X'; -- rzqin
pll_mem_clk : out std_logic; -- pll_mem_clk
pll_write_clk : out std_logic; -- pll_write_clk
pll_locked : out std_logic; -- pll_locked
pll_write_clk_pre_phy_clk : out std_logic; -- pll_write_clk_pre_phy_clk
pll_addr_cmd_clk : out std_logic; -- pll_addr_cmd_clk
pll_avl_clk : out std_logic; -- pll_avl_clk
pll_config_clk : out std_logic; -- pll_config_clk
-- pll_dr_clk : out std_logic; -- pll_dr_clk
-- pll_dr_clk_pre_phy_clk : out std_logic; -- pll_dr_clk_pre_phy_clk
pll_mem_phy_clk : out std_logic; -- pll_mem_phy_clk
afi_phy_clk : out std_logic; -- afi_phy_clk
pll_avl_phy_clk : out std_logic -- pll_avl_phy_clk
);
end ddr3controller_0002;
architecture sim of ddr3controller_0002 is
signal lafi_clk, lafi_rst_n: std_ulogic;
signal lafi_half_clk: std_ulogic;
begin
afi_clk <= lafi_clk;
afi_half_clk <= lafi_half_clk;
afi_reset_n <= lafi_rst_n;
mem_a <= (others => '0');
mem_ba <= (others => '0');
mem_ck <= (others => '0');
mem_ck_n <= (others => '1');
mem_cke <= (others => '0');
mem_cs_n <= (others => '1');
mem_dm <= (others => '0');
mem_ras_n <= (others => '1');
mem_cas_n <= (others => '1');
mem_we_n <= (others => '1');
mem_dq <= (others => 'Z');
mem_dqs <= (others => 'Z');
mem_dqs_n <= (others => 'Z');
mem_odt <= (others => '0');
avl_ready <= '1';
local_init_done <= '1';
local_cal_success <= '1';
local_cal_fail <= '0';
-- 200 MHz clock
clkproc: process
begin
lafi_clk <= '0';
lafi_half_clk <= '0';
loop
wait for 3.3 ns;
lafi_clk <= not lafi_clk;
if lafi_clk='0' then
lafi_half_clk <= not lafi_half_clk;
end if;
end loop;
end process;
rstproc: process
begin
lafi_rst_n <= '0';
wait for 10 ns;
loop
if global_reset_n='0' then
lafi_rst_n <= '0';
wait until global_reset_n/='0';
wait until rising_edge(lafi_clk);
end if;
lafi_rst_n <= '1';
wait until global_reset_n='0';
end loop;
end process;
avlproc: process
subtype BYTE is std_logic_vector(7 downto 0);
type MEM is array(0 to ((2**20)-1)) of BYTE;
variable MEMA: MEM;
procedure load_srec is
file TCF : text open read_mode is "ram.srec";
variable L1: line;
variable CH: character;
variable ai: integer;
variable rectype: std_logic_vector(3 downto 0);
variable recaddr: std_logic_vector(31 downto 0);
variable reclen: std_logic_vector(7 downto 0);
variable recdata: std_logic_vector(0 to 16*8-1);
variable len: integer;
begin
L1:= new string'(""); --'
while not endfile(TCF) loop
readline(TCF,L1);
if (L1'length /= 0) then --'
while (not (L1'length=0)) and (L1(L1'left) = ' ') loop
std.textio.read(L1,CH);
end loop;
if L1'length > 0 then --'
read(L1, ch);
if (ch = 'S') or (ch = 's') then
hread(L1, rectype);
hread(L1, reclen);
len := conv_integer(reclen)-1;
recaddr := (others => '0');
case rectype is
when "0001" =>
hread(L1, recaddr(15 downto 0));
len := len-2;
when "0010" =>
hread(L1, recaddr(23 downto 0));
len := len-3;
when "0011" =>
hread(L1, recaddr);
len := len-4;
when others => next;
end case;
hread(L1, recdata(0 to 8*len-1));
recaddr(31 downto 20) := (others => '0');
ai := conv_integer(recaddr);
-- print("Setting " & tost(len) & "bytes at " & tost(recaddr));
for i in 0 to len-1 loop
MEMA(ai+i) := recdata((i*8) to (i*8+7));
end loop;
end if;
end if;
end if;
end loop;
end load_srec;
constant avldbits: integer := 128;
variable outqueue: std_logic_vector(0 to 4*avldbits-1) := (others => 'X');
variable outqueue_valid: std_logic_vector(0 to 3) := (others => '0');
variable ai,p: integer;
variable wbleft: integer := 0;
begin
load_srec;
loop
wait until rising_edge(lafi_clk);
avl_rdata_valid <= outqueue_valid(0);
avl_rdata <= outqueue(0 to avldbits-1);
outqueue(0 to 3*avldbits-1) := outqueue(avldbits to 4*avldbits-1);
outqueue(3*avldbits to 4*avldbits-1) := (others => 'X');
outqueue_valid := outqueue_valid(1 to 3) & '0';
if avl_burstbegin='1' then wbleft:=0; end if;
if lafi_rst_n='0' then
outqueue_valid := (others => '0');
elsif avl_read_req='1' then
ai := conv_integer(avl_addr(16 downto 0));
p := 0;
while outqueue_valid(p)='1' loop p:=p+1; end loop;
for x in 0 to conv_integer(avl_size)-1 loop
for y in 0 to avldbits/8-1 loop
outqueue((p+x)*avldbits+y*8 to (p+x)*avldbits+y*8+7) := MEMA((ai+x)*avldbits/8+y);
end loop;
outqueue_valid(p+x) := '1';
end loop;
elsif avl_write_req='1' then
if wbleft=0 then
wbleft := conv_integer(avl_size);
ai := conv_integer(avl_addr(16 downto 0));
end if;
for y in 0 to avldbits/8-1 loop
if avl_be(avldbits/8-1-y)='1' then
MEMA(ai*avldbits/8+y) := avl_wdata(avldbits-8*y-1 downto avldbits-8*y-8);
end if;
end loop;
wbleft := wbleft-1;
ai := ai+1;
end if;
end loop;
end process;
end;
| gpl-3.0 | 07b67106ec6cb1fd2e42bfd6bc64a8a7 | 0.450773 | 3.849239 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/leon3v3/dsu3_mb.vhd | 1 | 2,687 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: dsu
-- File: dsu.vhd
-- Author: Jiri Gaisler, Edvin Catovic - Aeroflex Gaisler AB
-- Description: Combined LEON3 debug support with AHB trace unit
-- connected on separate bus.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.leon3.all;
library techmap;
use techmap.gencomp.all;
entity dsu3_mb is
generic (
hindex : integer := 0;
haddr : integer := 16#900#;
hmask : integer := 16#f00#;
ncpu : integer := 1;
tbits : integer := 30; -- timer bits (instruction trace time tag)
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 0;
testen : integer := 0;
bwidth : integer := 32;
ahbpf : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
tahbsi : in ahb_slv_in_type;
dbgi : in l3_debug_out_vector(0 to NCPU-1);
dbgo : out l3_debug_in_vector(0 to NCPU-1);
dsui : in dsu_in_type;
dsuo : out dsu_out_type
);
end;
architecture rtl of dsu3_mb is
signal gnd, vcc : std_ulogic;
begin
gnd <= '0'; vcc <= '1';
x0 : dsu3x generic map (hindex, haddr, hmask, ncpu, tbits, tech, irq, kbytes, 0, testen, bwidth, ahbpf)
port map (rst, gnd, clk, ahbmi, ahbsi, ahbso, tahbsi, dbgi, dbgo, dsui, dsuo, vcc
);
end;
| gpl-3.0 | 8c17c40199b3a4aadddd0d4426b5ef0c | 0.589877 | 3.773876 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/srmmu/mmulru.vhd | 1 | 6,023 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mmulru
-- File: mmulru.vhd
-- Author: Konrad Eisele, Jiri Gaisler, Gaisler Research
-- Description: MMU LRU logic
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
entity mmulru is
generic (
entries : integer := 8
);
port (
rst : in std_logic;
clk : in std_logic;
lrui : in mmulru_in_type;
lruo : out mmulru_out_type
);
end mmulru;
architecture rtl of mmulru is
constant entries_log : integer := log2(entries);
component mmulrue
generic (
position : integer;
entries : integer := 8
);
port (
rst : in std_logic;
clk : in std_logic;
lruei : in mmulrue_in_type;
lrueo : out mmulrue_out_type
);
end component;
type lru_rtype is record
bar : std_logic_vector(1 downto 0);
clear : std_logic_vector(M_ENT_MAX-1 downto 0);
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant ASYNC_RESET : boolean := GRLIB_CONFIG_ARRAY(grlib_async_reset_enable) = 1;
signal c,r : lru_rtype;
signal lruei : mmulruei_a (entries-1 downto 0);
signal lrueo : mmulrueo_a (entries-1 downto 0);
begin
p0: process (rst, r, lrui, lrueo)
variable v : lru_rtype;
variable reinit : std_logic;
variable pos : std_logic_vector(entries_log-1 downto 0);
variable touch : std_logic;
begin
v := r;
-- #init
reinit := '0';
--# eather element in luri or element 0 to top
pos := lrui.pos(entries_log-1 downto 0);
touch := lrui.touch;
if (lrui.touchmin) = '1' then
pos := lrueo(0).pos(entries_log-1 downto 0);
touch := '1';
end if;
for i in entries-1 downto 0 loop
lruei(i).pos <= (others => '0'); -- this is really ugly ...
lruei(i).left <= (others => '0');
lruei(i).right <= (others => '0');
lruei(i).pos(entries_log-1 downto 0) <= pos;
lruei(i).touch <= touch;
lruei(i).clear <= r.clear((entries-1)-i); -- reverse order
lruei(i).flush <= lrui.flush;
end loop;
lruei(entries-1).fromleft <= '0';
lruei(entries-1).fromright <= lrueo(entries-2).movetop;
lruei(entries-1).right(entries_log-1 downto 0) <= lrueo(entries-2).pos(entries_log-1 downto 0);
for i in entries-2 downto 1 loop
lruei(i).left(entries_log-1 downto 0) <= lrueo(i+1).pos(entries_log-1 downto 0);
lruei(i).right(entries_log-1 downto 0) <= lrueo(i-1).pos(entries_log-1 downto 0);
lruei(i).fromleft <= lrueo(i+1).movetop;
lruei(i).fromright <= lrueo(i-1).movetop;
end loop;
lruei(0).fromleft <= lrueo(1).movetop;
lruei(0).fromright <= '0';
lruei(0).left(entries_log-1 downto 0) <= lrueo(1).pos(entries_log-1 downto 0);
if not (r.bar = lrui.mmctrl1.bar) then
reinit := '1';
end if;
if ((not ASYNC_RESET) and (not RESET_ALL) and (rst = '0')) or (reinit = '1') then
v.bar := lrui.mmctrl1.bar;
v.clear := (others => '0');
case lrui.mmctrl1.bar is
when "01" =>
v.clear(1 downto 0) := "11"; -- reverse order
when "10" =>
v.clear(2 downto 0) := "111"; -- reverse order
when "11" =>
v.clear(4 downto 0) := "11111"; -- reverse order
when others =>
v.clear(0) := '1';
end case;
end if;
--# drive signals
lruo.pos <= lrueo(0).pos;
c <= v;
end process p0;
syncrregs : if not ASYNC_RESET generate
p1: process (clk)
begin
if rising_edge(clk) then
r <= c;
if RESET_ALL and (rst = '0') then
r.bar <= lrui.mmctrl1.bar;
r.clear <= (others => '0');
case lrui.mmctrl1.bar is
when "01" =>
r.clear(1 downto 0) <= "11"; -- reverse order
when "10" =>
r.clear(2 downto 0) <= "111"; -- reverse order
when "11" =>
r.clear(4 downto 0) <= "11111"; -- reverse order
when others =>
r.clear(0) <= '1';
end case;
end if;
end if;
end process p1;
end generate;
asyncrregs : if ASYNC_RESET generate
p1: process (clk, rst)
begin
if rst = '0' then
r.bar <= mmctrl_type1_none.bar;
r.clear <= (others => '0');
r.clear(0) <= '1';
elsif rising_edge(clk) then
r <= c;
end if;
end process p1;
end generate;
--# lru entries
lrue0: for i in entries-1 downto 0 generate
l1 : mmulrue
generic map ( position => i,
entries => entries )
port map (rst, clk, lruei(i), lrueo(i));
end generate lrue0;
end rtl;
| gpl-3.0 | 8ff1e0f10a5db8104c4257d8cde7ec6f | 0.561182 | 3.511953 | false | false | false | false |
ARC-Lab-UF/UAA | src/uaa_tb_all.vhd | 1 | 2,906 | -- Copyright (c) 2015 University of Florida
--
-- This file is part of uaa.
--
-- uaa is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- uaa is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with uaa. If not, see <http://www.gnu.org/licenses/>.
-- David Wilson
-- Greg Stitt
-- University of Florida
-- Description:
-- This file instantiates the uaa's testbench for each of the
-- architectures and verifies their correctness in a simple case
library ieee;
use ieee.std_logic_1164.all;
use work.uaa_pkg.all;
entity uaa_tb_all is
end uaa_tb_all;
architecture DEFAULT of uaa_tb_all is
begin
UUT_FCBT : entity work.uaa_tb
generic map(
test_name => "FCBT",
arch => UAA_FCBT,
parallel_inputs => 4,
add_core_name => "virtex7_latency",
use_bram => true,
FCBT_max_inputs => 300,
FCBT_obuf_size => 14,
total_groups => 20
)
port map(
min_group_size => 300,
max_group_size => 300,
input_delay_prob => 0.0,
group_delay_prob => 0.0,
hold_output_prob => 0.0,
acceptable_error_percent => 0.000,
print_status => false
);
UUT_DSA : entity work.uaa_tb
generic map(
test_name => "DSA",
arch => UAA_DSA,
parallel_inputs => 4,
add_core_name => "virtex7_speed",
use_bram => true,
FCBT_max_inputs => 300,
FCBT_obuf_size => 14,
total_groups => 20
)
port map(
min_group_size => 300,
max_group_size => 300,
input_delay_prob => 0.0,
group_delay_prob => 0.0,
hold_output_prob => 0.0,
acceptable_error_percent => 0.000,
print_status => false
);
UUT_SGA : entity work.uaa_tb
generic map(
test_name => "SGA",
arch => UAA_SGA,
parallel_inputs => 4,
add_core_name => "virtex7_speed",
use_bram => true,
FCBT_max_inputs => 300,
FCBT_obuf_size => 14,
total_groups => 20
)
port map(
min_group_size => 300,
max_group_size => 300,
input_delay_prob => 0.0,
group_delay_prob => 0.0,
hold_output_prob => 0.0,
acceptable_error_percent => 0.000,
print_status => false
);
end DEFAULT;
| gpl-3.0 | e6319445e9518d797c72c7ce98a26d6b | 0.552306 | 3.501205 | false | false | false | false |
pwsoft/fpga_examples | rtl/general/gen_lfsr.vhd | 1 | 3,753 | -- -----------------------------------------------------------------------
--
-- Syntiac's generic VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2019 by Peter Wendrich ([email protected])
-- http://www.syntiac.com/vhdl_lib.html
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
--
-- gen_lfsr.vhd
--
-- -----------------------------------------------------------------------
--
-- LFSR - Linear Feedback Shift Register
--
-- -----------------------------------------------------------------------
-- bits - number of bits in shift register (valid range 3 to 168)
-- -----------------------------------------------------------------------
-- clk - clock input
-- reset - reset shift register to zero
-- stop - stop shifting if set
-- load - Load shift register from d input
-- d - input for load
-- q - LFSR output
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- -----------------------------------------------------------------------
entity gen_lfsr is
generic (
bits : integer := 8
);
port (
clk : in std_logic;
reset : in std_logic := '0';
stop : in std_logic := '0';
load : in std_logic := '0';
d : in unsigned(bits-1 downto 0) := (others => '0');
q : out unsigned(bits-1 downto 0)
);
end entity;
-- -----------------------------------------------------------------------
architecture rtl of gen_lfsr is
signal shift_reg : unsigned(bits-1 downto 0) := (others => '0');
function feedback(sr : in unsigned(bits-1 downto 0)) return std_logic is
variable result : std_logic;
begin
result := '0';
-- Magic tap points following Xilinx application note XAPP052
-- Take note the application note counts bits from 1. Here we count from 0, so all the indexes are 1 lower.
case bits is
when 3 | 4 | 6 | 7 | 15 | 22 | 60 | 63 | 127 =>
result := sr(bits-1) xnor sr(bits-2);
when 5 =>
result := sr(bits-1) xnor sr(2);
when 8 =>
result := sr(bits-1) xnor sr(5) xnor sr(4) xnor sr(3);
when 9 =>
result := sr(bits-1) xnor sr(4);
when 10 =>
result := sr(bits-1) xnor sr(6);
when 11 =>
result := sr(bits-1) xnor sr(8);
when 12 =>
result := sr(bits-1) xnor sr(5) xnor sr(3) xnor sr(0);
when 13 =>
result := sr(bits-1) xnor sr(3) xnor sr(2) xnor sr(0);
when 14 =>
result := sr(bits-1) xnor sr(4) xnor sr(2) xnor sr(0);
when 16 =>
result := sr(bits-1) xnor sr(14) xnor sr(12) xnor sr(3);
when 17 =>
result := sr(bits-1) xnor sr(13);
when 18 =>
result := sr(bits-1) xnor sr(10);
when others =>
assert(false);
end case;
return result;
end function;
begin
q <= shift_reg;
process(clk) is
begin
if rising_edge(clk) then
if stop = '0' then
shift_reg <= shift_reg(bits-2 downto 0) & feedback(shift_reg);
end if;
if load = '1' then
shift_reg <= d;
end if;
if reset = '1' then
shift_reg <= (others => '0');
end if;
end if;
end process;
end architecture;
| lgpl-2.1 | dfef4b3dbeb358a66a73b547b405ab4a | 0.52518 | 3.591388 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/jtag/libjtagcom.vhd | 1 | 2,889 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: libjtagcom
-- File: libjtagcom.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: JTAG Commulnications link signal and component declarations
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library gaisler;
use gaisler.misc.all;
package libjtagcom is
type tap_in_type is record
en : std_ulogic;
tdo : std_ulogic;
end record;
type tap_out_type is record
tck : std_ulogic;
tdi : std_ulogic;
inst : std_logic_vector(7 downto 0);
asel : std_ulogic;
dsel : std_ulogic;
reset : std_ulogic;
capt : std_ulogic;
shift : std_ulogic;
upd : std_ulogic;
end record;
component jtagcom
generic (
isel : integer range 0 to 1 := 0;
nsync : integer range 1 to 2 := 2;
ainst : integer range 0 to 255 := 2;
dinst : integer range 0 to 255 := 3;
reread : integer range 0 to 1 := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
tapo : in tap_out_type;
tapi : out tap_in_type;
dmao : in ahb_dma_out_type;
dmai : out ahb_dma_in_type;
tck : in std_ulogic;
trst : in std_ulogic
);
end component;
component jtagcom2 is
generic (
gatetech: integer := 0;
isel : integer range 0 to 1 := 0;
ainst : integer range 0 to 255 := 2;
dinst : integer range 0 to 255 := 3);
port (
rst : in std_ulogic;
clk : in std_ulogic;
tapo : in tap_out_type;
tapi : out tap_in_type;
dmao : in ahb_dma_out_type;
dmai : out ahb_dma_in_type;
tckp : in std_ulogic;
tckn : in std_ulogic;
trst : in std_ulogic
);
end component;
end;
| gpl-3.0 | 39a560b7371541e164a4841c9c32bbe6 | 0.581516 | 3.841755 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/leon3v3/dsu3.vhd | 1 | 2,603 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: dsu
-- File: dsu.vhd
-- Author: Jiri Gaisler, Edvin Catovic - Gaisler Research
-- Description: Combined LEON3 debug support and AHB trace unit
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.leon3.all;
library techmap;
use techmap.gencomp.all;
entity dsu3 is
generic (
hindex : integer := 0;
haddr : integer := 16#900#;
hmask : integer := 16#f00#;
ncpu : integer := 1;
tbits : integer := 30; -- timer bits (instruction trace time tag)
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 0;
testen : integer := 0;
bwidth : integer := 32;
ahbpf : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
dbgi : in l3_debug_out_vector(0 to NCPU-1);
dbgo : out l3_debug_in_vector(0 to NCPU-1);
dsui : in dsu_in_type;
dsuo : out dsu_out_type
);
end;
architecture rtl of dsu3 is
signal gnd, vcc : std_ulogic;
begin
gnd <= '0'; vcc <= '1';
x0 : dsu3x generic map (hindex, haddr, hmask, ncpu, tbits, tech, irq, kbytes, 0, testen, bwidth, ahbpf)
port map (rst, gnd, clk, ahbmi, ahbsi, ahbso, ahbsi, dbgi, dbgo, dsui, dsuo, vcc
);
end;
| gpl-3.0 | 9ec214e710ab9d8cc4a317fda61b026b | 0.589704 | 3.78343 | false | false | false | false |
makestuff/mem-ctrl | vhdl/tb_unit/mem_ctrl_tb.vhdl | 1 | 6,776 | --
-- Copyright (C) 2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.hex_util.all;
use work.mem_ctrl_pkg.all;
entity mem_ctrl_tb is
end entity;
architecture behavioural of mem_ctrl_tb is
-- Clocks
signal intClk : std_logic; -- main system clock
signal extClk : std_logic; -- display version of intClk, which transitions 4ns before it
signal reset : std_logic;
-- Client interface
signal mcAutoMode : std_logic;
signal mcCmd : MCCmdType;
signal mcAddr : std_logic_vector(22 downto 0);
signal mcDataRd : std_logic_vector(15 downto 0);
signal mcDataWr : std_logic_vector(15 downto 0);
signal mcRDV : std_logic;
signal mcReady : std_logic;
-- SDRAM signals
signal ramCmd : std_logic_vector(2 downto 0);
signal ramBank : std_logic_vector(1 downto 0);
signal ramAddr : std_logic_vector(11 downto 0);
signal ramDataIO : std_logic_vector(15 downto 0);
signal ramLDQM : std_logic;
signal ramUDQM : std_logic;
begin
-- Instantiate the memory controller for testing
uut: entity work.mem_ctrl
generic map(
INIT_COUNT => "0" & x"004", --\
REFRESH_DELAY => "0" & x"010", -- Much longer in real hardware!
REFRESH_LENGTH => "0" & x"002" --/
)
port map(
clk_in => intClk,
reset_in => reset,
-- Client interface
mcAutoMode_in => mcAutoMode,
mcCmd_in => mcCmd,
mcAddr_in => mcAddr,
mcData_out => mcDataRd,
mcData_in => mcDataWr,
mcRDV_out => mcRDV,
mcReady_out => mcReady,
-- SDRAM interface
ramCmd_out => ramCmd,
ramBank_out => ramBank,
ramAddr_out => ramAddr,
ramData_io => ramDataIO,
ramLDQM_out => ramLDQM,
ramUDQM_out => ramUDQM
);
-- Instantiate the SDRAM model for testing
sdram_model: entity work.sdram_model
port map(
ramClk_in => extClk,
ramCmd_in => ramCmd,
ramBank_in => ramBank,
ramAddr_in => ramAddr,
ramData_io => ramDataIO
);
-- Drive the internal clock.
process
begin
intClk <= '0';
loop
wait for 10.417 ns;
intClk <= not(intClk);
end loop;
end process;
-- Drive the external clock.
process
begin
extClk <= '0';
wait for 15.625 ns; -- 3/4
loop
wait for 10.417 ns;
extClk <= not(extClk);
end loop;
end process;
-- Deassert the synchronous reset a couple of cycles after startup.
--
process
begin
reset <= '1';
wait until rising_edge(intClk);
wait until rising_edge(intClk);
reset <= '0';
wait;
end process;
-- Drive the unit under test. Read stimulus from stimulus.sim and write results to results.sim
process
variable inLine : line;
variable outLine : line;
file inFile : text open read_mode is "stimulus.sim";
file outFile : text open write_mode is "results.sim";
function to_mcCmd(c : character) return MCCmdType is begin
case c is
when 'R' =>
return MC_RD;
when 'W' =>
return MC_WR;
when '*' =>
return MC_REF;
when others =>
return MC_NOP;
end case;
end function;
function from_mcCmd(cmd : MCCmdType) return string is begin
case cmd is
when MC_RD =>
return "RD ";
when MC_WR =>
return "WR ";
when MC_REF =>
return "REF";
when MC_NOP =>
return "NOP";
when others =>
return "ILL";
end case;
end function;
function from_ramCmd(cmd : std_logic_vector(2 downto 0)) return string is begin
case cmd is
when "000" =>
return "LMR";
when "001" =>
return "REF";
when "010" =>
return "PRE";
when "011" =>
return "ACT";
when "100" =>
return "WR ";
when "101" =>
return "RD ";
when "111" =>
return "NOP";
when others =>
return "ILL";
end case;
end function;
begin
mcAutoMode <= '1';
mcCmd <= MC_NOP;
mcAddr <= (others => 'X');
mcDataWr <= (others => 'X');
wait until falling_edge(reset);
wait until rising_edge(intClk);
while ( not endfile(inFile) ) loop
readline(inFile, inLine);
while ( inLine.all'length = 0 or inLine.all(1) = '#' or inLine.all(1) = ht or inLine.all(1) = ' ' ) loop
readline(inFile, inLine);
end loop;
mcAutoMode <= to_1(inLine.all(1));
mcCmd <= to_mcCmd(inLine.all(3));
mcAddr <= to_3(inLine.all(5)) & to_4(inLine.all(6)) & to_4(inLine.all(7)) & to_4(inLine.all(8)) & to_4(inLine.all(9)) & to_4(inLine.all(10));
mcDataWr <= to_4(inLine.all(12)) & to_4(inLine.all(13)) & to_4(inLine.all(14)) & to_4(inLine.all(15));
wait until falling_edge(intClk);
write(outLine, mcAutoMode);
write(outLine, ' ');
write(outLine, mcReady);
write(outLine, ' ');
write(outLine, from_mcCmd(mcCmd));
write(outLine, ' ');
write(outLine, mcAddr(22 downto 20));
write(outLine, ':');
write(outLine, from_4(mcAddr(19 downto 16)) & from_4(mcAddr(15 downto 12)) & from_4(mcAddr(11 downto 8)) & from_4(mcAddr(7 downto 4)) & from_4(mcAddr(3 downto 0)));
write(outLine, ' ');
write(outLine, from_4(mcDataWr(15 downto 12)) & from_4(mcDataWr(11 downto 8)) & from_4(mcDataWr(7 downto 4)) & from_4(mcDataWr(3 downto 0)));
write(outLine, ' ');
write(outLine, from_4(mcDataRd(15 downto 12)) & from_4(mcDataRd(11 downto 8)) & from_4(mcDataRd(7 downto 4)) & from_4(mcDataRd(3 downto 0)));
write(outLine, ' ');
write(outLine, mcRDV);
write(outLine, ' ');
write(outLine, '|');
write(outLine, ' ');
write(outLine, from_ramCmd(ramCmd));
write(outLine, ' ');
write(outLine, ramBank);
write(outLine, ' ');
write(outLine, ramAddr(11 downto 8));
write(outLine, ':');
write(outLine, from_4(ramAddr(7 downto 4)) & from_4(ramAddr(3 downto 0)));
write(outLine, ' ');
write(outLine, from_4(ramDataIO(15 downto 12)) & from_4(ramDataIO(11 downto 8)) & from_4(ramDataIO(7 downto 4)) & from_4(ramDataIO(3 downto 0)));
writeline(outFile, outLine);
wait until rising_edge(intClk);
end loop;
mcAutoMode <= '1';
mcCmd <= MC_NOP;
mcAddr <= (others => 'X');
mcDataWr <= (others => 'X');
wait;
end process;
end architecture;
| gpl-3.0 | c73ed4240401ed5188461a0146d43b41 | 0.633412 | 3.089831 | false | false | false | false |
GLADICOS/SPACEWIRESYSTEMC | rtl/RTL_SL/spwxmit.vhd | 2 | 8,273 | --
-- SpaceWire Transmitter
--
-- This entity translates outgoing characters and tokens into
-- data-strobe signalling.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.spwpkg.all;
entity spwxmit is
port (
-- System clock.
clk: in std_logic;
-- Synchronous reset (active-high).
rst: in std_logic;
-- Scaling factor minus 1, used to scale the system clock into the
-- transmission bit rate. The system clock is divided by
-- (unsigned(divcnt) + 1). Changing this signal will immediately
-- change the transmission rate.
divcnt: in std_logic_vector(7 downto 0);
-- Input signals from spwlink.
xmiti: in spw_xmit_in_type;
-- Output signals to spwlink.
xmito: out spw_xmit_out_type;
-- Data Out signal to SpaceWire bus.
spw_do: out std_logic;
-- Strobe Out signal to SpaceWire bus.
spw_so: out std_logic
);
end entity spwxmit;
architecture spwxmit_arch of spwxmit is
-- Registers
type regs_type is record
-- tx clock
txclken: std_ulogic; -- high if a bit must be transmitted
txclkcnt: unsigned(7 downto 0);
-- output shift register
bitshift: std_logic_vector(12 downto 0);
bitcnt: unsigned(3 downto 0);
-- output signals
out_data: std_ulogic;
out_strobe: std_ulogic;
-- parity flag
parity: std_ulogic;
-- pending time tick
pend_tick: std_ulogic;
pend_time: std_logic_vector(7 downto 0);
-- transmitter mode
allow_fct: std_ulogic; -- allowed to send FCTs
allow_char: std_ulogic; -- allowed to send data and time
sent_null: std_ulogic; -- sent at least one NULL token
sent_fct: std_ulogic; -- sent at least one FCT token
end record;
-- Initial state
constant regs_reset: regs_type := (
txclken => '0',
txclkcnt => "00000000",
bitshift => (others => '0'),
bitcnt => "0000",
out_data => '0',
out_strobe => '0',
parity => '0',
pend_tick => '0',
pend_time => (others => '0'),
allow_fct => '0',
allow_char => '0',
sent_null => '0',
sent_fct => '0' );
-- Registers
signal r: regs_type := regs_reset;
signal rin: regs_type;
begin
-- Combinatorial process
process (r, rst, divcnt, xmiti) is
variable v: regs_type;
begin
v := r;
-- Generate TX clock.
if r.txclkcnt = 0 then
v.txclkcnt := unsigned(divcnt);
v.txclken := '1';
else
v.txclkcnt := r.txclkcnt - 1;
v.txclken := '0';
end if;
if xmiti.txen = '0' then
-- Transmitter disabled; reset state.
v.bitcnt := "0000";
v.parity := '0';
v.pend_tick := '0';
v.allow_fct := '0';
v.allow_char := '0';
v.sent_null := '0';
v.sent_fct := '0';
-- Gentle reset of spacewire bus signals
if r.txclken = '1' then
v.out_data := r.out_data and r.out_strobe;
v.out_strobe := '0';
end if;
else
-- Transmitter enabled.
v.allow_fct := (not xmiti.stnull) and r.sent_null;
v.allow_char := (not xmiti.stnull) and r.sent_null and
(not xmiti.stfct) and r.sent_fct;
-- On tick of transmission clock, put next bit on the output.
if r.txclken = '1' then
if r.bitcnt = 0 then
-- Need to start a new character.
if (r.allow_char = '1') and (r.pend_tick = '1') then
-- Send Time-Code.
v.out_data := r.parity;
v.bitshift(12 downto 5) := r.pend_time;
v.bitshift(4 downto 0) := "01111";
v.bitcnt := to_unsigned(13, v.bitcnt'length);
v.parity := '0';
v.pend_tick := '0';
elsif (r.allow_fct = '1') and (xmiti.fct_in = '1') then
-- Send FCT.
v.out_data := r.parity;
v.bitshift(2 downto 0) := "001";
v.bitcnt := to_unsigned(3, v.bitcnt'length);
v.parity := '1';
v.sent_fct := '1';
elsif (r.allow_char = '1') and (xmiti.txwrite = '1') then
-- Send N-Char.
v.bitshift(0) := xmiti.txflag;
v.parity := xmiti.txflag;
if xmiti.txflag = '0' then
-- Data byte
v.out_data := not r.parity;
v.bitshift(8 downto 1) := xmiti.txdata;
v.bitcnt := to_unsigned(9, v.bitcnt'length);
else
-- EOP or EEP
v.out_data := r.parity;
v.bitshift(1) := xmiti.txdata(0);
v.bitshift(2) := not xmiti.txdata(0);
v.bitcnt := to_unsigned(3, v.bitcnt'length);
end if;
else
-- Send NULL.
v.out_data := r.parity;
v.bitshift(6 downto 0) := "0010111";
v.bitcnt := to_unsigned(7, v.bitcnt'length);
v.parity := '0';
v.sent_null := '1';
end if;
else
-- Shift next bit to the output.
v.out_data := r.bitshift(0);
v.parity := r.parity xor r.bitshift(0);
v.bitshift(r.bitshift'high-1 downto 0) := r.bitshift(r.bitshift'high downto 1);
v.bitcnt := r.bitcnt - 1;
end if;
-- Data-Strobe encoding.
v.out_strobe := not (r.out_strobe xor r.out_data xor v.out_data);
end if;
-- Store requests for time tick transmission.
if xmiti.tick_in = '1' then
v.pend_tick := '1';
v.pend_time := xmiti.ctrl_in & xmiti.time_in;
end if;
end if;
-- Synchronous reset
if rst = '1' then
v := regs_reset;
end if;
-- Drive outputs.
-- Note: the outputs are combinatorially dependent on certain inputs.
-- Set fctack high if (transmitter enabled) AND
-- (ready for token) AND (FCTs allowed) AND
-- ((characters not allowed) OR (no timecode pending)) AND
-- (FCT requested)
if (xmiti.txen = '1') and
(r.txclken = '1') and (r.bitcnt = 0) and (r.allow_fct = '1') and
((r.allow_char = '0') or (r.pend_tick = '0')) then
xmito.fctack <= xmiti.fct_in;
else
xmito.fctack <= '0';
end if;
-- Set txrdy high if (transmitter enabled) AND
-- (ready for token) AND (characters enabled) AND
-- (no timecode pending) AND (no FCT requested) AND
-- (character requested)
if (xmiti.txen = '1') and
(r.txclken = '1') and (r.bitcnt = 0) and (r.allow_char = '1') and
(r.pend_tick = '0') and (xmiti.fct_in = '0') then
xmito.txack <= xmiti.txwrite;
else
xmito.txack <= '0';
end if;
-- Update registers
rin <= v;
end process;
-- Synchronous process
process (clk) is
begin
if rising_edge(clk) then
-- Update registers
r <= rin;
-- Drive spacewire output signals
spw_do <= r.out_data;
spw_so <= r.out_strobe;
end if;
end process;
end architecture spwxmit_arch;
| gpl-3.0 | 4d0c051c1431868304771aa8b13a5e5f | 0.45582 | 3.922712 | false | false | false | false |
NeuroML/org.neuroml.export | src/main/resources/vhdl/ParamExp.vhd | 1 | 7,205 | --
-- Parameterisable N to M mux.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- For Modelsim
--use ieee.fixed_pkg.all;
--use ieee.fixed_float_types.ALL;
-- For ISE
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use IEEE.numeric_std.all;
entity ParamExp is
generic(
BIT_TOP : integer := 20;
BIT_BOTTOM : integer := -20);
port(
clk : In Std_logic;
init_model : in STD_LOGIC; --signal to all components to go into their init state
Start : In Std_logic;
X : In sfixed(BIT_TOP downto BIT_BOTTOM);
Done : Out Std_logic;
Output : Out sfixed(BIT_TOP downto BIT_BOTTOM)
);
end ParamExp;
architecture RTL of ParamExp is
type MEM is array (0 to 7) of sfixed(BIT_TOP downto BIT_BOTTOM);
signal ISPOSITIVE : STD_LOGIC := '0';
signal ISGREATERTHANONE : STD_LOGIC := '0';
signal X_integer : sfixed(BIT_TOP downto 0);
signal X_fraction : sfixed(0 downto BIT_BOTTOM);
signal Output_int : sfixed(BIT_TOP downto BIT_BOTTOM);
signal Done_int : Std_logic;
signal output_fraction : sfixed(BIT_TOP downto BIT_BOTTOM);
signal output_fraction_next : sfixed(BIT_TOP downto BIT_BOTTOM);
signal current_term : sfixed(BIT_TOP downto BIT_BOTTOM);
signal current_term_next : sfixed(BIT_TOP downto BIT_BOTTOM);
signal COUNT_FRACTION : unsigned(3 downto 0);
signal COUNT_FRACTION_next : unsigned(3 downto 0);
signal DONEFRACTION : STD_LOGIC := '0';
signal DONEFRACTION_next : STD_LOGIC := '0';
signal output_integer : sfixed(BIT_TOP downto BIT_BOTTOM);
signal output_integer_next : sfixed(BIT_TOP downto BIT_BOTTOM);
signal COUNT_INTEGER : unsigned(BIT_TOP+1 downto 0);
signal COUNT_INTEGER_next : unsigned(BIT_TOP+1 downto 0);
signal DONEINTEGER : STD_LOGIC := '0';
signal DONEINTEGER_next : STD_LOGIC := '0';
signal E : sfixed(BIT_TOP downto BIT_BOTTOM) := to_sfixed(2.71828182845904523536028747135266249775724709369995,BIT_TOP,BIT_BOTTOM);
signal EInv : sfixed(BIT_TOP downto BIT_BOTTOM) := resize(reciprocal(to_sfixed(2.71828182845904523536028747135266249775724709369995,BIT_TOP,BIT_BOTTOM)),BIT_TOP,BIT_BOTTOM);
signal EMul : sfixed(BIT_TOP downto BIT_BOTTOM);
signal n1: sfixed (BIT_TOP downto 0);
signal n2: sfixed (n1'high + 1 downto n1'low);
signal n3: ufixed (BIT_TOP + 1 downto 0);
begin
splitUpXProcess: process(X,X_integer,ispositive,E,EInv)
begin
X_integer <= resize(abs(X) - 0.5,BIT_TOP,0);
X_fraction <= resize(abs(X) - X_integer,0,BIT_BOTTOM);
if To_slv ( resize ( X ,BIT_TOP,BIT_BOTTOM))(BIT_TOP-BIT_BOTTOM) = '0' then
ISPOSITIVE <= '1';
else
ISPOSITIVE <= '0';
end if;
if (ISPOSITIVE = '1') then
EMul <= E;
else
EMul <= EInv;
end if;
end process splitUpXProcess;
fractionCombProcess: process(COUNT_FRACTION,Start,output_fraction,current_term,X_fraction,ISPOSITIVE,current_term_next,init_model)
variable MEM8Xsfixed : MEM := (to_sfixed (1,BIT_TOP, BIT_BOTTOM),to_sfixed (0.5,BIT_TOP, BIT_BOTTOM),to_sfixed (0.33333333,BIT_TOP, BIT_BOTTOM),to_sfixed (0.25,BIT_TOP, BIT_BOTTOM),
to_sfixed (0.2,BIT_TOP, BIT_BOTTOM),to_sfixed (0.16666666667,BIT_TOP, BIT_BOTTOM),to_sfixed (0.142857142857,BIT_TOP, BIT_BOTTOM),to_sfixed (0.125,BIT_TOP, BIT_BOTTOM));
begin
output_fraction_next <= output_fraction;
COUNT_FRACTION_next <= COUNT_FRACTION;
current_term_next <= current_term;
DONEFRACTION_next <= '0';
current_term_next <= resize(MEM8Xsfixed(to_integer(unsigned(COUNT_FRACTION(2 downto 0)))) *
resize(X_fraction * current_term,BIT_TOP, BIT_BOTTOM),BIT_TOP, BIT_BOTTOM);
if init_model = '1' then
DONEFRACTION_next <= '1';
COUNT_FRACTION_next <= "1001";
output_fraction_next <= to_sfixed (1,BIT_TOP, BIT_BOTTOM);
current_term_next <= to_sfixed (1,BIT_TOP, BIT_BOTTOM);
else
if Start = '1' then
DONEFRACTION_next <= '0';
COUNT_FRACTION_next <= "0000";
output_fraction_next <= to_sfixed (1,BIT_TOP, BIT_BOTTOM);
current_term_next <= to_sfixed (1,BIT_TOP, BIT_BOTTOM);
elsif COUNT_FRACTION = "1001" then
DONEFRACTION_next <= '1';
current_term_next <= current_term;
else
DONEFRACTION_next <= '0';
if (ISPOSITIVE = '1') then
output_fraction_next <= resize(output_fraction + current_term_next,BIT_TOP, BIT_BOTTOM);
else
if (COUNT_FRACTION(0) = '0') then
output_fraction_next <= resize(output_fraction - current_term_next,BIT_TOP, BIT_BOTTOM);
else
output_fraction_next <= resize(output_fraction + current_term_next,BIT_TOP, BIT_BOTTOM);
end if;
end if;
COUNT_FRACTION_next <= COUNT_FRACTION + 1;
end if;
end if;
end process fractionCombProcess;
fractionSynProcess: process(clk)
variable Sel : integer;
begin
if clk'event and clk = '1' then
output_fraction <= output_fraction_next;
COUNT_FRACTION <= COUNT_FRACTION_next;
current_term <= current_term_next;
DONEFRACTION <= DONEFRACTION_next;
--report "The value of output_fraction = " & real'image(to_real(output_fraction)) & " and current_term " &
-- real'image(to_real(current_term));
end if;
end process fractionSynProcess;
integerCombProcess: process(COUNT_INTEGER,output_integer,x_integer,Start,EMul,init_model)
begin
DONEINTEGER_next <= '0';
COUNT_INTEGER_next <= COUNT_INTEGER;
output_integer_next <= output_integer;
if init_model = '1' then
DONEINTEGER_next <= '0';
COUNT_INTEGER_next <= to_unsigned(0,COUNT_INTEGER_next'length);
output_integer_next <= to_sfixed (1,BIT_TOP, BIT_BOTTOM);
else
if Start = '1' then
DONEINTEGER_next <= '0';
COUNT_INTEGER_next <= unsigned(ufixed(abs(X_integer)));
output_integer_next <= to_sfixed (1,BIT_TOP, BIT_BOTTOM);
else
if COUNT_INTEGER = 0 then
DONEINTEGER_next <= '1';
COUNT_INTEGER_next <= COUNT_INTEGER;
output_integer_next <= output_integer;
else
DONEINTEGER_next <= '0';
output_integer_next <= resize(output_integer * EMul,BIT_TOP,BIT_BOTTOM);
COUNT_INTEGER_next <= COUNT_INTEGER - 1;
end if;
end if;
end if;
end process integerCombProcess;
integerSynProcess: process(clk,x_integer,count_integer,output_integer)
begin
COUNT_INTEGER <= COUNT_INTEGER;
output_integer <= output_integer;
if clk = '1' and clk'event then
COUNT_INTEGER <= COUNT_INTEGER_next;
output_integer <= output_integer_next;
DONEINTEGER <= DONEINTEGER_next;
end if;
end process integerSynProcess;
outputCombProcess: process(output_fraction,output_integer,DONEINTEGER,DONEFRACTION)
begin
Output_int <= resize(output_fraction * output_integer,BIT_TOP, BIT_BOTTOM);
if DONEFRACTION = '1' and DONEINTEGER = '1' then
Done_int <= '1';
else
Done_int <= '0';
end if;
end process outputCombProcess;
Done <= Done_int;
Output <= Output_int;
--process (DONEFRACTION)
--begin
-- if (DONEFRACTION'event or DONEINTEGER'event) and DONEFRACTION = '1' and DONEINTEGER = '1' then
-- report "The value of X_integer = " & real'image(to_real(X_integer)) & " and X_fraction " & real'image(to_real(X_fraction));
-- report "The value of exp( " & real'image(to_real(X)) & " ) = " &
-- real'image(to_real(output_integer)) & " * " & real'image(to_real(output_fraction));
-- end if;
--end process;
end RTL;
| lgpl-3.0 | 847b47432a633efff5dd1011b1117ad2 | 0.682582 | 2.997088 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/unisim/clkgen_unisim.vhd | 1 | 18,468 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: clkgen_xilinx.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Author: Richard Pender, Pender Electronic Design
-- Description: Clock generators for Virtex and Virtex-2 fpgas
------------------------------------------------------------------------------
------------------------------------------------------------------
-- Virtex5 clock generator ---------------------------------------
------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
library unisim;
use unisim.BUFG;
use unisim.DCM;
--use unisim.BUFGDLL;
use unisim.BUFGMUX;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkgen_virtex5 is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000; -- clock frequency in KHz
clk2xen : integer := 0;
clksel : integer := 0); -- enable clock select
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
clkn : out std_ulogic; -- inverted main clock
clk2x : out std_ulogic; -- double clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk1xu : out std_ulogic; -- unscaled clock
clk2xu : out std_ulogic -- unscaled 2X clock
);
end;
architecture struct of clkgen_virtex5 is
component BUFG port (O : out std_logic; I : in std_logic); end component;
component BUFGMUX port ( O : out std_ulogic; I0 : in std_ulogic;
I1 : in std_ulogic; S : in std_ulogic);
end component;
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
-- component BUFGDLL port (O : out std_logic; I : in std_logic); end component;
constant VERSION : integer := 1;
--constant CLKIN_PERIOD_ST : string := "20.0";
constant FREQ_MHZ : integer := freq/1000;
--attribute CLKIN_PERIOD : string;
--attribute CLKIN_PERIOD of dll0: label is CLKIN_PERIOD_ST;
signal gnd, clk_i, clk_j, clk_k, clk_l, clk_m, lsdclk : std_logic;
signal clk_x, clk_n, clk_o, clk_p, clk_i2, clk_sd, clk_r: std_logic;
signal dll0rst, dll0lock, dll1lock, dll2xlock : std_logic;
signal dll1rst, dll2xrst : std_logic_vector(0 to 3);
signal clk0B, clkint, pciclkint : std_logic;
begin
gnd <= '0';
clk <= clk_i when (CLK2XEN = 0) else clk_p;
clkn <= clk_m; clk2x <= clk_i2;
c0 : if (PCISYSCLK = 0) or (PCIEN = 0) generate
clkint <= clkin;
end generate;
c2 : if PCIEN /= 0 generate
pciclkint <= pciclkin;
p3 : if PCISYSCLK = 1 generate clkint <= pciclkint; end generate;
p0 : if PCIDLL = 1 generate
-- x1 : BUFGDLL port map (I => pciclkint, O => pciclk);
--pragma translate_off
assert false report "PCIDLL = 1 currently not supported for virtex5_clkgen"
severity failure;
--pragma translate_on
end generate;
p1 : if PCIDLL = 0 generate
x1 : BUFG port map (I => pciclkint, O => pciclk);
end generate;
end generate;
c3 : if PCIEN = 0 generate
pciclk <= '0';
end generate;
clk1xu <= clk_k;
clk2xu <= clk_x;
bufg0 : BUFG port map (I => clk0B, O => clk_i);
bufg1 : BUFG port map (I => clk_j, O => clk_k);
bufg2 : BUFG port map (I => clk_l, O => clk_m);
buf34gen : if (CLK2XEN /= 0) generate
cs0 : if (clksel = 0) generate
bufg3 : BUFG port map (I => clk_n, O => clk_i2);
end generate;
cs1 : if (clksel /= 0) generate
bufg3 : BUFGMUX port map (S => cgi.clksel(0), I0 => clk_o, I1 => clk_n, O => clk_i2);
end generate;
bufg4 : BUFG port map (I => clk_o, O => clk_p);
end generate;
dll0rst <= not cgi.pllrst;
-- HMODE_dll0 : if (((FREQ_MHZ*clk_mul)/clk_div >= 140) or (FREQ_MHZ >= 120)) generate
-- dll0 : DCM
-- generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div,
-- DFS_FREQUENCY_MODE => "HIGH", DLL_FREQUENCY_MODE => "HIGH")
-- port map ( CLKIN => clkint, CLKFB => clk_k, DSSEN => gnd, PSCLK => gnd,
-- PSEN => gnd, PSINCDEC => gnd, RST => dll0rst, CLK0 => clk_j,
-- CLKFX => clk0B, CLK2X => clk_x, CLKFX180 => clk_l, LOCKED => dll0lock);
-- end generate;
-- LMODE_dll0 : if not (((FREQ_MHZ*clk_mul)/clk_div >= 140) or (FREQ_MHZ >= 120)) generate
dll0 : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW")
port map ( CLKIN => clkint, CLKFB => clk_k, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst, CLK0 => clk_j,
CLKFX => clk0B, CLK2X => clk_x, CLKFX180 => clk_l, LOCKED => dll0lock);
-- end generate;
clk2xgen : if (CLK2XEN /= 0) generate
-- HMODE_dll2x : if ((FREQ_MHZ*clk_mul)/clk_div >= 120) generate
-- dll2x : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2,
-- DFS_FREQUENCY_MODE => "HIGH", DLL_FREQUENCY_MODE => "HIGH")
-- port map ( CLKIN => clk_i, CLKFB => clk_p, DSSEN => gnd, PSCLK => gnd,
-- PSEN => gnd, PSINCDEC => gnd, RST => dll2xrst(0), CLK0 => clk_o,
-- CLK2X => clk_n, LOCKED => dll2xlock);
-- end generate;
-- LMODE_dll2x : if not ((FREQ_MHZ*clk_mul)/clk_div >= 120) generate
dll2x : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW")
port map ( CLKIN => clk_i, CLKFB => clk_p, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2xrst(0), CLK0 => clk_o,
CLK2X => clk_n, LOCKED => dll2xlock);
-- end generate;
rstdel2x : process (clk_i, dll0lock)
begin
if dll0lock = '0' then dll2xrst <= (others => '1');
elsif rising_edge(clk_i) then
dll2xrst <= dll2xrst(1 to 3) & '0';
end if;
end process;
end generate;
clk_sd1 : if (CLK2XEN = 0) generate
clk_i2 <= clk_x;
dll2xlock <= dll0lock;
clk_sd <= clk_i;
end generate;
clk_sd2 : if (CLK2XEN = 1) generate clk_sd <= clk_p; end generate;
clk_sd3 : if (CLK2XEN = 2) generate clk_sd <= clk_i2; end generate;
sd0 : if (SDRAMEN /= 0) and (NOCLKFB=0) generate
cgo.clklock <= dll1lock;
-- HMODE_dll1 : if ((FREQ_MHZ*clk_mul)/clk_div >= (120-60*(CLK2XEN/2))) generate
-- dll1 : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2,
-- DFS_FREQUENCY_MODE => "HIGH", DLL_FREQUENCY_MODE => "HIGH",
-- DESKEW_ADJUST => "SOURCE_SYNCHRONOUS")
-- port map ( CLKIN => clk_sd, CLKFB => cgi.pllref, DSSEN => gnd, PSCLK => gnd,
-- PSEN => gnd, PSINCDEC => gnd, RST => dll1rst(0), CLK0 => lsdclk, --CLK2X => clk2x,
-- LOCKED => dll1lock);
-- end generate;
-- LMODE_dll1 : if not ((FREQ_MHZ*clk_mul)/clk_div >= (120-60*(CLK2XEN/2))) generate
dll1 : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW",
DESKEW_ADJUST => "SOURCE_SYNCHRONOUS")
port map ( CLKIN => clk_sd, CLKFB => cgi.pllref, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll1rst(0), CLK0 => lsdclk, --CLK2X => clk2x,
LOCKED => dll1lock);
-- end generate;
bufgx : BUFG port map (I => lsdclk, O => sdclk);
rstdel : process (clk_sd, dll2xlock)
begin
if dll2xlock = '0' then dll1rst <= (others => '1');
elsif rising_edge(clk_sd) then
dll1rst <= dll1rst(1 to 3) & '0';
end if;
end process;
end generate;
sd1 : if ((SDRAMEN = 0) or (NOCLKFB = 1)) and (CLK2XEN /= 2) generate
sdclk <= clk_i;
cgo.clklock <= dll0lock when (CLK2XEN = 0) else dll2xlock;
end generate;
sd1_2x : if ((SDRAMEN = 0) or (NOCLKFB = 1)) and (CLK2XEN = 2) generate
sdclk <= clk_i2;
cgo.clklock <= dll2xlock;
end generate;
cgo.pcilock <= '1';
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_virtex5" & ": virtex-5 sdram/pci clock generator, version " & tost(VERSION),
"clkgen_virtex5" & ": Frequency " & tost(freq) & " KHz, DCM divisor " & tost(clk_mul) & "/" & tost(clk_div));
-- pragma translate_on
end;
------------------------------------------------------------------
-- Virtex7 clock generator ---------------------------------------
------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
library unisim;
use UNISIM.vcomponents.all;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkgen_virtex7 is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
freq : integer := 200000 -- clock frequency in KHz
);
port (
clkin : in std_ulogic;
clk : out std_ulogic; -- main clock
clk90 : out std_ulogic; -- main clock 90deg
clkio : out std_ulogic; -- IO ref clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type
);
end;
architecture struct of clkgen_virtex7 is
component BUFG port (O : out std_logic; I : in std_logic); end component;
----- component PLLE2_ADV -----
component PLLE2_ADV
generic (
BANDWIDTH : string := "OPTIMIZED";
CLKFBOUT_MULT : integer := 5;
CLKFBOUT_PHASE : real := 0.0;
CLKIN1_PERIOD : real := 0.0;
CLKIN2_PERIOD : real := 0.0;
CLKOUT0_DIVIDE : integer := 1;
CLKOUT0_DUTY_CYCLE : real := 0.5;
CLKOUT0_PHASE : real := 0.0;
CLKOUT1_DIVIDE : integer := 1;
CLKOUT1_DUTY_CYCLE : real := 0.5;
CLKOUT1_PHASE : real := 0.0;
CLKOUT2_DIVIDE : integer := 1;
CLKOUT2_DUTY_CYCLE : real := 0.5;
CLKOUT2_PHASE : real := 0.0;
CLKOUT3_DIVIDE : integer := 1;
CLKOUT3_DUTY_CYCLE : real := 0.5;
CLKOUT3_PHASE : real := 0.0;
CLKOUT4_DIVIDE : integer := 1;
CLKOUT4_DUTY_CYCLE : real := 0.5;
CLKOUT4_PHASE : real := 0.0;
CLKOUT5_DIVIDE : integer := 1;
CLKOUT5_DUTY_CYCLE : real := 0.5;
CLKOUT5_PHASE : real := 0.0;
COMPENSATION : string := "ZHOLD";
DIVCLK_DIVIDE : integer := 1;
REF_JITTER1 : real := 0.0;
REF_JITTER2 : real := 0.0;
STARTUP_WAIT : string := "FALSE"
);
port (
CLKFBOUT : out std_ulogic := '0';
CLKOUT0 : out std_ulogic := '0';
CLKOUT1 : out std_ulogic := '0';
CLKOUT2 : out std_ulogic := '0';
CLKOUT3 : out std_ulogic := '0';
CLKOUT4 : out std_ulogic := '0';
CLKOUT5 : out std_ulogic := '0';
DO : out std_logic_vector (15 downto 0);
DRDY : out std_ulogic := '0';
LOCKED : out std_ulogic := '0';
CLKFBIN : in std_ulogic;
CLKIN1 : in std_ulogic;
CLKIN2 : in std_ulogic;
CLKINSEL : in std_ulogic;
DADDR : in std_logic_vector(6 downto 0);
DCLK : in std_ulogic;
DEN : in std_ulogic;
DI : in std_logic_vector(15 downto 0);
DWE : in std_ulogic;
PWRDWN : in std_ulogic;
RST : in std_ulogic
);
end component;
constant VERSION : integer := 1;
constant period : real := 1000000.0/real(freq);
constant clkio_div : integer := freq*clk_mul/200000;
signal CLKFBOUT : std_logic;
signal CLKFBIN : std_logic;
signal int_rst : std_logic;
signal clk_nobuf : std_logic;
signal clk90_nobuf : std_logic;
signal clkio_nobuf : std_logic;
begin
CLKFBIN <= CLKFBOUT;
int_rst <= not cgi.pllrst;
PLLE2_ADV_inst : PLLE2_ADV
generic map (
BANDWIDTH => "OPTIMIZED", -- OPTIMIZED, HIGH, LOW
CLKFBOUT_MULT => clk_mul, -- Multiply value for all CLKOUT, (2-64)
CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB, (-360.000-360.000).
-- CLKIN_PERIOD: Input clock period in nS to ps resolution (i.e. 33.333 is 30 MHz).
CLKIN1_PERIOD => period,
CLKIN2_PERIOD => 0.0,
-- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for CLKOUT (1-128)
CLKOUT0_DIVIDE => clk_div,
CLKOUT1_DIVIDE => clk_div,
CLKOUT2_DIVIDE => clkio_div,
CLKOUT3_DIVIDE => 1,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
-- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for CLKOUT outputs (0.001-0.999).
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT2_DUTY_CYCLE => 0.5,
CLKOUT3_DUTY_CYCLE => 0.5,
CLKOUT4_DUTY_CYCLE => 0.5,
CLKOUT5_DUTY_CYCLE => 0.5,
-- CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for CLKOUT outputs (-360.000-360.000).
CLKOUT0_PHASE => 0.0,
CLKOUT1_PHASE => 90.0,
CLKOUT2_PHASE => 0.0,
CLKOUT3_PHASE => 0.0,
CLKOUT4_PHASE => 0.0,
CLKOUT5_PHASE => 0.0,
COMPENSATION => "ZHOLD", -- ZHOLD, BUF_IN, EXTERNAL, INTERNAL
DIVCLK_DIVIDE => 1, -- Master division value (1-56)
-- REF_JITTER: Reference input jitter in UI (0.000-0.999).
REF_JITTER1 => 0.0,
REF_JITTER2 => 0.0,
STARTUP_WAIT => "TRUE" -- Delay DONE until PLL Locks, ("TRUE"/"FALSE")
)
port map (
-- Clock Outputs: 1-bit (each) output: User configurable clock outputs
CLKOUT0 => clk_nobuf,
CLKOUT1 => clk90_nobuf,
CLKOUT2 => clkio_nobuf,
CLKOUT3 => OPEN,
CLKOUT4 => OPEN,
CLKOUT5 => OPEN,
-- DRP Ports: 16-bit (each) output: Dynamic reconfigration ports
DO => OPEN,
DRDY => OPEN,
-- Feedback Clocks: 1-bit (each) output: Clock feedback ports
CLKFBOUT => CLKFBOUT,
-- Status Ports: 1-bit (each) output: PLL status ports
LOCKED => cgo.clklock,
-- Clock Inputs: 1-bit (each) input: Clock inputs
CLKIN1 => clkin,
CLKIN2 => '0',
-- Con trol Ports: 1-bit (each) input: PLL control ports
CLKINSEL => '1',
PWRDWN => '0',
RST => int_rst,
-- DRP Ports: 7-bit (each) input: Dynamic reconfigration ports
DADDR => "0000000",
DCLK => '0',
DEN => '0',
DI => "0000000000000000",
DWE => '0',
-- Feedback Clocks: 1-bit (each) input: Clock feedback ports
CLKFBIN => CLKFBIN
);
cgo.pcilock <= '0';
bufgclk0 : BUFG port map (I => clk_nobuf, O => clk);
bufgclk90 : BUFG port map (I => clk90_nobuf, O => clk90);
bufgclkio : BUFG port map (I => clkio_nobuf, O => clkio);
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_virtex7" & ": virtex-7 sdram/pci clock generator, version " & tost(VERSION),
"clkgen_virtex7" & ": Frequency " & tost(freq) & " KHz, DCM divisor " & tost(clk_mul) & "/" & tost(clk_div));
-- pragma translate_on
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BUFGMUX;
-- pragma translate_on
entity clkand_unisim is
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic
);
end entity;
architecture rtl of clkand_unisim is
component BUFGCE
port(
O : out STD_ULOGIC;
CE: in STD_ULOGIC;
I : in STD_ULOGIC
);
end component;
begin
buf : bufgce port map(I => i, CE => en, O => o);
end architecture;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BUFGMUX;
-- pragma translate_on
entity clkmux_unisim is
port(
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic
);
end entity;
architecture rtl of clkmux_unisim is
component bufgmux is
port(
i0, i1 : in std_ulogic;
s : in std_ulogic;
o : out std_ulogic);
end component;
signal sel0, sel1, cg0, cg1 : std_ulogic;
begin
buf : bufgmux port map(S => sel, I0 => i0, I1 => i1, O => o);
end architecture;
| gpl-3.0 | b9e2a845e8dc7f59c9dab41642007b2c | 0.564652 | 3.417469 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-terasic-de4/testbench.vhd | 1 | 21,785 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2013 Aeroflex Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
use gaisler.net.all;
use work.debug.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 10; -- system clock period
romdepth : integer := 25; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 20; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
constant ct : integer := clkperiod/2;
-- clocks
signal OSC_50_BANK2 : std_logic := '0';
signal OSC_50_BANK3 : std_logic := '0';
signal OSC_50_BANK4 : std_logic := '0';
signal OSC_50_BANK5 : std_logic := '0';
signal OSC_50_BANK6 : std_logic := '0';
signal OSC_50_BANK7 : std_logic := '0';
signal PLL_CLKIN_p : std_logic := '0';
signal SMA_CLKIN_p : std_logic := '0';
--signal SMA_GXBCLK_p : std_logic;
signal GCLKIN : std_logic := '0';
-- signal GCLKOUT_FPGA : std_logic := '0';
-- signal SMA_CLKOUT_p : std_logic := '0';
signal clk_125 : std_logic := '0';
-- cpu reset
signal CPU_RESET_n : std_ulogic := '0';
-- max i/o
-- signal MAX_CONF_D : std_logic_vector(3 downto 0);
-- signal MAX_I2C_SCLK : std_logic;
-- signal MAX_I2C_SDAT : std_logic;
-- LEDs
signal LED : std_logic_vector(7 downto 0);
-- buttons
signal BUTTON : std_logic_vector(3 downto 0);
-- switches
signal SW : std_logic_vector(3 downto 0);
-- slide switches
signal SLIDE_SW : std_logic_vector(3 downto 0);
-- temperature
-- signal TEMP_SMCLK : std_logic;
-- signal TEMP_SMDAT : std_logic;
-- signal TEMP_INT_n : std_logic;
-- current
signal CSENSE_ADC_FO : std_logic;
signal CSENSE_SCK : std_logic;
signal CSENSE_SDI : std_logic;
signal CSENSE_SDO : std_logic;
signal CSENSE_CS_n : std_logic_vector(1 downto 0);
-- fan
signal FAN_CTRL : std_logic;
-- eeprom
signal EEP_SCL : std_logic;
signal EEP_SDA : std_logic;
-- sdcard
-- signal SD_CLK : std_logic;
-- signal SD_CMD : std_logic;
-- signal SD_DAT : std_logic_vector(3 downto 0);
-- signal SD_WP_n : std_logic;
-- Ethernet interfaces
signal ETH_INT_n : std_logic_vector(3 downto 0);
signal ETH_MDC : std_logic_vector(3 downto 0);
signal ETH_MDIO : std_logic_vector(3 downto 0);
signal ETH_RST_n : std_ulogic;
signal ETH_RX_p : std_logic_vector(3 downto 0);
signal ETH_TX_p : std_logic_vector(3 downto 0);
-- PCIe interfaces
--signal PCIE_PREST_n : std_ulogic;
--signal PCIE_REFCLK_p : std_ulogic;
--signal PCIE_RX_p : std_logic_vector(7 downto 0);
--signal PCIE_SMBCLK : std_logic;
--signal PCIE_SMBDAT : std_logic;
--signal PCIE_TX_p : std_logic_vector(7 downto 0);
--signal PCIE_WAKE_n : std_logic;
-- Flash and SRAM, shared signals
signal FSM_A : std_logic_vector(25 downto 1);
signal FSM_D : std_logic_vector(15 downto 0);
-- Flash control
signal FLASH_ADV_n : std_ulogic;
signal FLASH_CE_n : std_ulogic;
signal FLASH_CLK : std_ulogic;
signal FLASH_OE_n : std_ulogic;
signal FLASH_RESET_n : std_ulogic;
signal FLASH_RYBY_n : std_ulogic;
signal FLASH_WE_n : std_ulogic;
-- SSRAM control
signal SSRAM_ADV : std_ulogic;
signal SSRAM_BWA_n : std_ulogic;
signal SSRAM_BWB_n : std_ulogic;
signal SSRAM_CE_n : std_ulogic;
signal SSRAM_CKE_n : std_ulogic;
signal SSRAM_CLK : std_ulogic;
signal SSRAM_OE_n : std_ulogic;
signal SSRAM_WE_n : std_ulogic;
-- USB OTG
--signal OTG_A : std_logic_vector(17 downto 1);
--signal OTG_CS_n : std_ulogic;
--signal OTG_D : std_logic_vector(31 downto 0);
--signal OTG_DC_DACK : std_ulogic;
--signal OTG_DC_DREQ : std_ulogic;
--signal OTG_DC_IRQ : std_ulogic;
--signal OTG_HC_DACK : std_ulogic;
--signal OTG_HC_DREQ : std_ulogic;
--signal OTG_HC_IRQ : std_ulogic;
--signal OTG_OE_n : std_ulogic;
--signal OTG_RESET_n : std_ulogic;
--signal OTG_WE_n : std_ulogic;
-- SATA
--signal SATA_REFCLK_p : std_logic;
--signal SATA_HOST_RX_p : std_logic_vector(1 downto 0);
--signal SATA_HOST_TX_p : std_logic_vector(1 downto 0);
--signal SATA_DEVICE_RX_p : std_logic_vector(1 downto 0);
--signal SATA_DEVICE_TX_p : std_logic_vector(1 downto 0);
-- DDR2 SODIMM
signal M1_DDR2_addr : std_logic_vector(15 downto 0);
signal M1_DDR2_ba : std_logic_vector(2 downto 0);
signal M1_DDR2_cas_n : std_logic;
signal M1_DDR2_cke : std_logic_vector(1 downto 0);
signal M1_DDR2_clk : std_logic_vector(1 downto 0);
signal M1_DDR2_clk_n : std_logic_vector(1 downto 0);
signal M1_DDR2_cs_n : std_logic_vector(1 downto 0);
signal M1_DDR2_dm : std_logic_vector(7 downto 0);
signal M1_DDR2_dq : std_logic_vector(63 downto 0);
signal M1_DDR2_dqs : std_logic_vector(7 downto 0);
signal M1_DDR2_dqsn : std_logic_vector(7 downto 0);
signal M1_DDR2_odt : std_logic_vector(1 downto 0);
signal M1_DDR2_ras_n : std_logic;
-- signal M1_DDR2_SA : std_logic_vector(1 downto 0);
-- signal M1_DDR2_SCL : std_logic;
-- signal M1_DDR2_SDA : std_logic;
signal M1_DDR2_we_n : std_logic;
signal M1_DDR2_oct_rdn : std_logic;
signal M1_DDR2_oct_rup : std_logic;
-- DDR2 SODIMM
--signal M2_DDR2_addr : std_logic_vector(15 downto 0);
--signal M2_DDR2_ba : std_logic_vector(2 downto 0);
--signal M2_DDR2_cas_n : std_logic;
--signal M2_DDR2_cke : std_logic_vector(1 downto 0);
--signal M2_DDR2_clk : std_logic_vector(1 downto 0);
--signal M2_DDR2_clk_n : std_logic_vector(1 downto 0);
--signal M2_DDR2_cs_n : std_logic_vector(1 downto 0);
--signal M2_DDR2_dm : std_logic_vector(7 downto 0);
--signal M2_DDR2_dq : std_logic_vector(63 downto 0);
--signal M2_DDR2_dqs : std_logic_vector(7 downto 0);
--signal M2_DDR2_dqsn : std_logic_vector(7 downto 0);
--signal M2_DDR2_odt : std_logic_vector(1 downto 0);
--signal M2_DDR2_ras_n : std_logic;
--signal M2_DDR2_SA : std_logic_vector(1 downto 0);
--signal M2_DDR2_SCL : std_logic;
--signal M2_DDR2_SDA : std_logic;
--signal M2_DDR2_we_n : std_logic;
-- GPIO
signal GPIO0_D : std_logic_vector(35 downto 0);
-- signal GPIO1_D : std_logic_vector(35 downto 0);
-- Ext I/O
signal EXT_IO : std_logic;
-- HSMC A
-- signal HSMA_CLKIN_n1 : std_logic;
-- signal HSMA_CLKIN_n2 : std_logic;
-- signal HSMA_CLKIN_p1 : std_logic;
-- signal HSMA_CLKIN_p2 : std_logic;
-- signal HSMA_CLKIN0 : std_logic;
signal HSMA_CLKOUT_n2 : std_logic;
signal HSMA_CLKOUT_p2 : std_logic;
-- signal HSMA_D : std_logic_vector(3 downto 0);
-- HSMA_GXB_RX_p : std_logic_vector(3 downto 0);
-- HSMA_GXB_TX_p : std_logic_vector(3 downto 0);
-- signal HSMA_OUT_n1 : std_logic;
-- signal HSMA_OUT_p1 : std_logic;
-- signal HSMA_OUT0 : std_logic;
-- HSMA_REFCLK_p : in std_logic;
-- signal HSMA_RX_n : std_logic_vector(16 downto 0);
-- signal HSMA_RX_p : std_logic_vector(16 downto 0);
-- signal HSMA_TX_n : std_logic_vector(16 downto 0);
-- signal HSMA_TX_p : std_logic_vector(16 downto 0);
-- HSMC_B
-- signal HSMB_CLKIN_n1 : std_logic;
-- signal HSMB_CLKIN_n2 : std_logic;
-- signal HSMB_CLKIN_p1 : std_logic;
-- signal HSMB_CLKIN_p2 : std_logic;
-- signal HSMB_CLKIN0 : std_logic;
-- signal HSMB_CLKOUT_n2 : std_logic;
-- signal HSMB_CLKOUT_p2 : std_logic;
-- signal HSMB_D : std_logic_vector(3 downto 0);
-- signal HSMB_GXB_RX_p : in std_logic_vector(3 downto 0);
-- signal HSMB_GXB_TX_p : out std_logic_vector(3 downto 0);
-- signal HSMB_OUT_n1 : std_logic;
-- signal HSMB_OUT_p1 : std_logic;
-- signal HSMB_OUT0 : std_logic;
-- signal HSMB_REFCLK_p : in std_logic;
-- signal HSMB_RX_n : std_logic_vector(16 downto 0);
-- signal HSMB_RX_p : std_logic_vector(16 downto 0);
-- signal HSMB_TX_n : std_logic_vector(16 downto 0);
-- signal HSMB_TX_p : std_logic_vector(16 downto 0);
-- HSMC i2c
-- signal HSMC_SCL : std_logic;
-- signal HSMC_SDA : std_logic;
-- Display
-- signal SEG0_D : std_logic_vector(6 downto 0);
-- signal SEG1_D : std_logic_vector(6 downto 0);
-- signal SEG0_DP : std_ulogic;
-- signal SEG1_DP : std_ulogic;
-- UART
signal UART_CTS : std_ulogic;
signal UART_RTS : std_ulogic;
signal UART_RXD : std_logic;
signal UART_TXD : std_logic;
signal dsuen, dsubren, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal rst_125 : std_logic;
constant lresp : boolean := false;
constant slips : integer := 11;
signal ETH_RX_p_0_d : std_logic;
signal ETH_RX_p_1_d : std_logic;
begin
-- clock and reset
-- 50 MHz clocks
OSC_50_BANK2 <= not OSC_50_BANK2 after 10 ns;
OSC_50_BANK3 <= not OSC_50_BANK3 after 10 ns;
OSC_50_BANK4 <= not OSC_50_BANK4 after 10 ns;
OSC_50_BANK5 <= not OSC_50_BANK5 after 10 ns;
OSC_50_BANK6 <= not OSC_50_BANK6 after 10 ns;
OSC_50_BANK7 <= not OSC_50_BANK7 after 10 ns;
-- 100 MHz
PLL_CLKIN_p <= not PLL_CLKIN_p after 5 ns;
SMA_CLKIN_p <= not SMA_CLKIN_p after 10 ns;
GCLKIN <= not GCLKIN after 10 ns;
clk_125 <= not clk_125 after 4 ns;
CPU_RESET_n <= '0', '1' after 200 ns;
-- various interfaces
-- MAX_CONF_D <= (others => 'H');
-- MAX_I2C_SDAT <= 'H';
BUTTON <= "HHHH";
SW <= (others => 'H');
SLIDE_SW <= (others => 'L');
-- TEMP_SMDAT <= 'H';
-- TEMP_INT_n <= 'H';
CSENSE_SCK <= 'H';
CSENSE_SDO <= 'H';
EEP_SDA <= 'H';
-- SD_CMD <= 'H';
-- SD_DAT <= (others => 'H');
-- SD_WP_n <= 'H';
GPIO0_D <= (others => 'H');
-- GPIO1_D <= (others => 'H');
EXT_IO <= 'H';
LED(0) <= 'H';
-- HSMC_SDA <= 'H';
UART_RTS <= '1';
UART_RXD <= 'H';
-- LEON3 SoC
d3 : entity work.leon3mp
generic map (
fabtech, memtech, padtech, clktech, disas, dbguart, pclow)
port map (
OSC_50_BANK2, OSC_50_BANK3, OSC_50_BANK4, OSC_50_BANK5, OSC_50_BANK6,
OSC_50_BANK7, PLL_CLKIN_p, SMA_CLKIN_p,
-- SMA_GXBCLK_p
GCLKIN,
-- GCLKOUT_FPGA, SMA_CLKOUT_p,
-- cpu reset
CPU_RESET_n,
-- max i/o
-- MAX_CONF_D, MAX_I2C_SCLK, MAX_I2C_SDAT,
-- LEDs
LED,
-- buttons
BUTTON,
-- switches
SW,
-- slide switches
SLIDE_SW,
-- temperature
-- TEMP_SMCLK, TEMP_SMDAT, TEMP_INT_n,
-- current
CSENSE_ADC_FO, CSENSE_SCK, CSENSE_SDI, CSENSE_SDO, CSENSE_CS_n,
-- fan
FAN_CTRL,
-- eeprom
EEP_SCL, EEP_SDA,
-- sdcard
-- SD_CLK, SD_CMD, SD_DAT, SD_WP_n,
-- Ethernet interfaces
ETH_INT_n, ETH_MDC, ETH_MDIO, ETH_RST_n, ETH_RX_p, ETH_TX_p,
-- PCIe interfaces
-- PCIE_PREST_n, PCIE_REFCLK_p, PCIE_RX_p, PCIE_SMBCLK,
-- PCIE_SMBDAT, PCIE_TX_p PCIE_WAKE_n
-- Flash and SRAM, shared signals
FSM_A, FSM_D,
-- Flash control
FLASH_ADV_n, FLASH_CE_n, FLASH_CLK, FLASH_OE_n,
FLASH_RESET_n, FLASH_RYBY_n, FLASH_WE_n,
-- SSRAM control
SSRAM_ADV, SSRAM_BWA_n, SSRAM_BWB_n, SSRAM_CE_n,
SSRAM_CKE_n, SSRAM_CLK, SSRAM_OE_n, SSRAM_WE_n,
-- USB OTG
-- OTG_A, OTG_CS_n, OTG_D, OTG_DC_DACK, OTG_DC_DRE, OTG_DC_IRQ,
-- OTG_HC_DACK, OTG_HC_DREQ, OTG_HC_IRQ, OTG_OE_n, OTG_RESET_n,
-- OTG_WE_n,
-- SATA
-- SATA_REFCLK_p, SATA_HOST_RX_p, SATA_HOST_TX_p, SATA_DEVICE_RX_p, SATA_DEVICE_TX_p,
-- DDR2 SODIMM
M1_DDR2_addr, M1_DDR2_ba, M1_DDR2_cas_n, M1_DDR2_cke, M1_DDR2_clk, M1_DDR2_clk_n,
M1_DDR2_cs_n, M1_DDR2_dm, M1_DDR2_dq, M1_DDR2_dqs, M1_DDR2_dqsn, M1_DDR2_odt,
M1_DDR2_ras_n,
-- M1_DDR2_SA, M1_DDR2_SCL, M1_DDR2_SDA,
M1_DDR2_we_n,
M1_DDR2_oct_rdn, M1_DDR2_oct_rup,
-- DDR2 SODIMM
-- M2_DDR2_addr, M2_DDR2_ba, M2_DDR2_cas_n, M2_DDR2_cke, M2_DDR2_clk, M2_DDR2_clk_n
-- M2_DDR2_cs_n, M2_DDR2_dm, M2_DDR2_dq, M2_DDR2_dqs, M2_DDR2_dqsn, M2_DDR2_odt,
-- M2_DDR2_ras_n, M2_DDR2_SA, M2_DDR2_SCL, M2_DDR2_SDA M2_DDR2_we_n
-- GPIO
GPIO0_D,
-- GPIO1_D,
-- Ext I/O
-- EXT_IO,
-- HSMC A
-- HSMA_CLKIN_n1, HSMA_CLKIN_n2, HSMA_CLKIN_p1, HSMA_CLKIN_p2, HSMA_CLKIN0,
HSMA_CLKOUT_n2, HSMA_CLKOUT_p2,
-- HSMA_D,
-- HSMA_GXB_RX_p, HSMA_GXB_TX_p,
-- HSMA_OUT_n1, HSMA_OUT_p1, HSMA_OUT0,
-- HSMA_REFCLK_p,
-- HSMA_RX_n, HSMA_RX_p, HSMA_TX_n, HSMA_TX_p,
-- HSMC_B
-- HSMB_CLKIN_n1, HSMB_CLKIN_n2, HSMB_CLKIN_p1, HSMB_CLKIN_p2, HSMB_CLKIN0,
-- HSMB_CLKOUT_n2, HSMB_CLKOUT_p2, HSMB_D,
-- HSMB_GXB_RX_p, HSMB_GXB_TX_p,
-- HSMB_OUT_n1, HSMB_OUT_p1, HSMB_OUT0,
-- HSMB_REFCLK_p,
-- HSMB_RX_n, HSMB_RX_p, HSMB_TX_n, HSMB_TX_p,
-- HSMC i2c
-- HSMC_SCL, HSMC_SDA,
-- Display
-- SEG0_D, SEG1_D, SEG0_DP, SEG1_DP,
-- UART
UART_CTS, UART_RTS, UART_RXD, UART_TXD
);
ethsim0 : if CFG_GRETH /= 0 generate
rst_125 <= not CPU_RESET_n;
-- delaying rx line
ETH_RX_p(0) <= transport ETH_RX_p_0_d after 0.8 ns * slips;
p0: ser_phy
generic map(
address => 0,
extended_regs => 1,
aneg => 1,
fd_10 => 1,
hd_10 => 1,
base100_t4 => 1,
base100_x_fd => 1,
base100_x_hd => 1,
base100_t2_fd => 1,
base100_t2_hd => 1,
base1000_x_fd => CFG_GRETH1G,
base1000_x_hd => CFG_GRETH1G,
base1000_t_fd => CFG_GRETH1G,
base1000_t_hd => CFG_GRETH1G,
fabtech => fabtech,
memtech => memtech
)
port map(
rstn => CPU_RESET_n,
clk_125 => clk_125,
rst_125 => rst_125,
eth_rx_p => ETH_RX_p_0_d,
eth_tx_p => ETH_TX_p(0),
mdio => ETH_MDIO(0),
mdc => ETH_MDC(0)
);
end generate;
ethsim1 : if CFG_GRETH2 /= 0 generate
-- delaying rx line
ETH_RX_p(1) <= transport ETH_RX_p_1_d after 0.8 ns * slips;
p1: ser_phy
generic map(
address => 1,
extended_regs => 1,
aneg => 1,
fd_10 => 1,
hd_10 => 1,
base100_t4 => 1,
base100_x_fd => 1,
base100_x_hd => 1,
base100_t2_fd => 1,
base100_t2_hd => 1,
base1000_x_fd => CFG_GRETH21G,
base1000_x_hd => CFG_GRETH21G,
base1000_t_fd => CFG_GRETH21G,
base1000_t_hd => CFG_GRETH21G,
fabtech => fabtech,
memtech => memtech
)
port map(
rstn => CPU_RESET_n,
clk_125 => clk_125,
rst_125 => rst_125,
eth_rx_p => ETH_RX_p_1_d,
eth_tx_p => ETH_TX_p(1),
mdio => ETH_MDIO(1),
mdc => ETH_MDC(1)
);
end generate;
prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile)
port map (FSM_A(romdepth downto 1), FSM_D, FLASH_CE_n, FLASH_CE_n, FLASH_CE_n,
FLASH_WE_n, FLASH_OE_n);
FLASH_RYBY_n <= 'H';
ddr2mem0 : ddr2ram
generic map(
width => 64,
abits => 14,
babits => 3,
colbits => 10,
rowbits => 11,
implbanks => 8,
fname => sdramfile,
speedbin => 1,
density => 3,
lddelay => (0 ns),
swap => 0,
ldguard => 1
)
port map (
a => M1_DDR2_addr(13 downto 0), -- ddr2_addr,
ba => M1_DDR2_ba, -- ddr2_ba,
ck => M1_DDR2_clk(0), -- ddr2_ck_p(0),
ckn => M1_DDR2_clk_n(0), -- ddr2_ck_n(0),
cke => M1_DDR2_cke(0), -- ddr2_cke(0),
csn => M1_DDR2_cs_n(0), -- ddr2_cs_n(0),
dm => M1_DDR2_dm, -- ddr2_dm,
rasn => M1_DDR2_ras_n, -- ddr2_ras_n,
casn => M1_DDR2_cas_n, -- ddr2_cas_n,
wen => M1_DDR2_we_n, -- ddr2_we_n,
dq => M1_DDR2_dq, -- ddr2_dq(15 downto 0),
dqs => M1_DDR2_dqs, -- ddr2_dqs_p,
dqsn => M1_DDR2_dqsn, -- ddr2_dqs_n,
odt => M1_DDR2_odt(0), -- ddr2_odt(0),
doload => LED(2)
);
test0 : grtestmod
generic map ( width => 16 )
port map ( CPU_RESET_n, OSC_50_BANK3, LED(0), FSM_A(20 downto 1), FSM_D,
'0', FLASH_OE_n, FLASH_WE_n);
iuerr : process
begin
wait for 2500 ns;
if to_x01(LED(0)) = '1' then wait on LED(0); end if;
assert (to_x01(LED(0)) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
FSM_D <= buskeep(FSM_D) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 320 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 2500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart--
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#2e#, txp);--
wait for 25000 ns;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#01#, txp);--
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0D#, txp);--
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#70#, 16#11#, 16#78#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#0D#, txp);--
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#00#, txp);--
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);--
wait;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#aa#, txp);
txa(dsutx, 16#00#, 16#55#, 16#00#, 16#55#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#a0#, txp);
txa(dsutx, 16#01#, 16#02#, 16#09#, 16#33#, txp);--
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#80#, 16#00#, 16#02#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);--
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);--
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);--
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);--
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);--
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);--
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);--
end;--
begin--
dsucfg(UART_TXD, UART_RXD);--
wait;
end process;
end ;
| gpl-3.0 | a99c1bfcc42dfd96ed5ad41c2000e43f | 0.563186 | 2.749243 | false | false | false | false |
hoglet67/CoPro6502 | src/PDP2011/fpuregs.vhd | 1 | 4,485 |
--
-- Copyright (c) 2008-2015 Sytse van Slooten
--
-- Permission is hereby granted to any person obtaining a copy of these VHDL source files and
-- other language source files and associated documentation files ("the materials") to use
-- these materials solely for personal, non-commercial purposes.
-- You are also granted permission to make changes to the materials, on the condition that this
-- copyright notice is retained unchanged.
--
-- The materials are distributed in the hope that they will be useful, but WITHOUT ANY WARRANTY;
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
--
-- $Revision: 1.15 $
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity fpuregs is
port(
raddr : in std_logic_vector(2 downto 0);
waddr : in std_logic_vector(2 downto 0);
d : in std_logic_vector(63 downto 0);
o : out std_logic_vector(63 downto 0);
fpmode : in std_logic;
we : in std_logic;
clk : in std_logic
);
end fpuregs;
architecture implementation of fpuregs is
subtype fp_unit is std_logic_vector(15 downto 0);
type fp_type is array(5 downto 0) of fp_unit;
signal fpreg1 : fp_type := fp_type'(
fp_unit'("0000000000000000"),
fp_unit'("0000000000000000"),
fp_unit'("0000000000000000"),
fp_unit'("0000000000000000"),
fp_unit'("0000000000000000"),
fp_unit'("0000000000000000")
);
signal fpreg2 : fp_type := fp_type'(
fp_unit'("0000000000000000"),
fp_unit'("0000000000000000"),
fp_unit'("0000000000000000"),
fp_unit'("0000000000000000"),
fp_unit'("0000000000000000"),
fp_unit'("0000000000000000")
);
signal fpreg3 : fp_type := fp_type'(
fp_unit'("0000000000000000"),
fp_unit'("0000000000000000"),
fp_unit'("0000000000000000"),
fp_unit'("0000000000000000"),
fp_unit'("0000000000000000"),
fp_unit'("0000000000000000")
);
signal fpreg4 : fp_type := fp_type'(
fp_unit'("0000000000000000"),
fp_unit'("0000000000000000"),
fp_unit'("0000000000000000"),
fp_unit'("0000000000000000"),
fp_unit'("0000000000000000"),
fp_unit'("0000000000000000")
);
signal r_loc : std_logic_vector(2 downto 0);
signal w_loc : std_logic_vector(2 downto 0);
signal ac0 : std_logic_vector(63 downto 0);
signal ac1 : std_logic_vector(63 downto 0);
signal ac2 : std_logic_vector(63 downto 0);
signal ac3 : std_logic_vector(63 downto 0);
signal ac4 : std_logic_vector(63 downto 0);
signal ac5 : std_logic_vector(63 downto 0);
begin
ac0 <= fpreg1(conv_integer("0")) & fpreg2(conv_integer("0")) & fpreg3(conv_integer("0")) & fpreg4(conv_integer("0"));
ac1 <= fpreg1(conv_integer("1")) & fpreg2(conv_integer("1")) & fpreg3(conv_integer("1")) & fpreg4(conv_integer("1"));
ac2 <= fpreg1(conv_integer("10")) & fpreg2(conv_integer("10")) & fpreg3(conv_integer("10")) & fpreg4(conv_integer("10"));
ac3 <= fpreg1(conv_integer("11")) & fpreg2(conv_integer("11")) & fpreg3(conv_integer("11")) & fpreg4(conv_integer("11"));
ac4 <= fpreg1(conv_integer("100")) & fpreg2(conv_integer("100")) & fpreg3(conv_integer("100")) & fpreg4(conv_integer("100"));
ac5 <= fpreg1(conv_integer("101")) & fpreg2(conv_integer("101")) & fpreg3(conv_integer("101")) & fpreg4(conv_integer("101"));
r_loc <= raddr;
w_loc <= waddr;
process(clk, we, w_loc, d, fpmode)
begin
if clk = '1' and clk'event then
if we = '1' and w_loc(2 downto 1) /= "11" then
if fpmode = '1' then
fpreg1(conv_integer(w_loc)) <= d(63 downto 48);
fpreg2(conv_integer(w_loc)) <= d(47 downto 32);
fpreg3(conv_integer(w_loc)) <= d(31 downto 16);
fpreg4(conv_integer(w_loc)) <= d(15 downto 0);
else
fpreg1(conv_integer(w_loc)) <= d(63 downto 48);
fpreg2(conv_integer(w_loc)) <= d(47 downto 32);
end if;
end if;
end if;
end process;
process(r_loc, fpreg1, fpreg2, fpreg3, fpreg4, fpmode)
begin
if r_loc(2 downto 1) /= "11" then
if fpmode = '1' then
o <= fpreg1(conv_integer(r_loc)) & fpreg2(conv_integer(r_loc)) & fpreg3(conv_integer(r_loc)) & fpreg4(conv_integer(r_loc));
else
o <= fpreg1(conv_integer(r_loc)) & fpreg2(conv_integer(r_loc)) & "00000000000000000000000000000000";
end if;
else
o <= "0000000000000000000000000000000000000000000000000000000000000000";
end if;
end process;
end implementation;
| gpl-3.0 | 35ae54c0fc2a8912526a7c2695fc914a | 0.643701 | 3.369647 | false | false | false | false |
pwsoft/fpga_examples | rtl/general/gen_uart.vhd | 1 | 5,367 | -- -----------------------------------------------------------------------
--
-- Syntiac's generic VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2011 by Peter Wendrich ([email protected])
-- http://www.syntiac.com
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
--
-- gen_uart.vhd
--
-- -----------------------------------------------------------------------
--
-- UART
--
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- -----------------------------------------------------------------------
entity gen_uart is
generic (
bits : integer := 8;
baud : integer;
ticksPerUsec : integer
);
port (
clk : in std_logic;
d : in unsigned(bits-1 downto 0) := (others => '0');
d_trigger : in std_logic := '0';
d_empty : out std_logic;
q : out unsigned(bits-1 downto 0);
q_trigger : out std_logic;
serial_rxd : in std_logic := '1';
serial_txd : out std_logic
);
end entity;
architecture rtl of gen_uart is
constant ticksPerBit : integer := (1000000*ticksPerUsec) / baud;
type state_t is (
STATE_IDLE,
STATE_START,
STATE_BITS,
STATE_LAST,
STATE_STOP);
signal receive_state : state_t := STATE_IDLE;
signal receive_buffer : unsigned(bits-1 downto 0) := (others => '0');
signal receive_shift : unsigned(bits-1 downto 0) := (others => '0');
signal receive_cnt : integer range 0 to bits-1 := 0;
signal receive_baud_cnt : integer range 0 to ticksPerBit := 0;
signal transmit_state : state_t := STATE_IDLE;
signal transmit_empty : std_logic := '1';
signal transmit_buffer : unsigned(bits-1 downto 0) := (others => '0');
signal transmit_shift : unsigned(bits-1 downto 0) := (others => '0');
signal transmit_cnt : integer range 0 to bits-1 := 0;
signal transmit_baud_cnt : integer range 0 to ticksPerBit := 0;
signal serial_rxd_reg : std_logic := '1';
signal serial_txd_reg : std_logic := '1';
begin
d_empty <= transmit_empty and (not d_trigger);
q <= receive_buffer;
serial_txd <= serial_txd_reg;
receive_process: process(clk)
begin
if rising_edge(clk) then
serial_rxd_reg <= serial_rxd;
q_trigger <= '0';
case receive_state is
when STATE_IDLE =>
receive_cnt <= 0;
-- start bit?
if serial_rxd_reg = '0' then
receive_state <= STATE_START;
receive_baud_cnt <= ticksPerBit;
end if;
when STATE_START =>
if receive_baud_cnt = 0 then
-- Sample half-way of the bit
receive_baud_cnt <= ticksPerBit/2;
receive_state <= STATE_BITS;
else
receive_baud_cnt <= receive_baud_cnt - 1;
end if;
when STATE_BITS =>
if receive_baud_cnt = 0 then
receive_baud_cnt <= ticksPerBit;
receive_shift(receive_cnt) <= serial_rxd_reg;
if receive_cnt = bits-1 then
receive_state <= STATE_LAST;
else
receive_cnt <= receive_cnt + 1;
end if;
else
receive_baud_cnt <= receive_baud_cnt - 1;
end if;
when STATE_LAST =>
q_trigger <= '1';
receive_baud_cnt <= ticksPerBit;
receive_buffer <= receive_shift;
receive_state <= STATE_STOP;
when STATE_STOP =>
if receive_baud_cnt = 0 then
receive_state <= STATE_IDLE;
else
receive_baud_cnt <= receive_baud_cnt - 1;
end if;
when others =>
null;
end case;
end if;
end process;
transmit_process: process(clk)
begin
if rising_edge(clk) then
case transmit_state is
when STATE_IDLE =>
serial_txd_reg <= '1';
transmit_cnt <= 0;
transmit_baud_cnt <= ticksPerBit;
if transmit_empty = '0' then
transmit_shift <= transmit_buffer;
transmit_empty <= '1';
transmit_state <= STATE_BITS;
serial_txd_reg <= '0';
end if;
when STATE_BITS =>
if transmit_baud_cnt = 0 then
transmit_baud_cnt <= ticksPerBit;
serial_txd_reg <= transmit_shift(transmit_cnt);
if transmit_cnt = bits-1 then
transmit_state <= STATE_LAST;
else
transmit_cnt <= transmit_cnt + 1;
end if;
else
transmit_baud_cnt <= transmit_baud_cnt - 1;
end if;
when STATE_LAST =>
if transmit_baud_cnt = 0 then
transmit_baud_cnt <= ticksPerBit;
transmit_state <= STATE_STOP;
else
transmit_baud_cnt <= transmit_baud_cnt - 1;
end if;
when STATE_STOP =>
serial_txd_reg <= '1';
if transmit_baud_cnt = 0 then
transmit_state <= STATE_IDLE;
else
transmit_baud_cnt <= transmit_baud_cnt - 1;
end if;
when others =>
null;
end case;
if d_trigger = '1' then
transmit_buffer <= d;
transmit_empty <= '0';
end if;
end if;
end process;
end architecture;
| lgpl-2.1 | d11c3b618a337811edc2d5a06901c2a2 | 0.587479 | 3.34601 | false | false | false | false |
firecake/IRIS | FPGA/VHDL/ipcore_dir/RAM/simulation/RAM_synth.vhd | 1 | 10,708 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: RAM_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY RAM_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
CLKB_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE RAM_synth_ARCH OF RAM_synth IS
COMPONENT RAM_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL CLKB: STD_LOGIC := '0';
SIGNAL RSTB: STD_LOGIC := '0';
SIGNAL WEB: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEB_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRB: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRB_R: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINB: STD_LOGIC_VECTOR( 31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINB_R: STD_LOGIC_VECTOR( 31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTB: STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL CHECK_DATA_TDP : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECKER_ENB_R : STD_LOGIC := '0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL clkb_in_i: STD_LOGIC;
SIGNAL RESETB_SYNC_R1 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R2 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R3 : STD_LOGIC := '1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
-- clkb_buf: bufg
-- PORT map(
-- i => CLKB_IN,
-- o => clkb_in_i
-- );
clkb_in_i <= CLKB_IN;
CLKB <= clkb_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
RSTB <= RESETB_SYNC_R3 AFTER 50 ns;
PROCESS(clkb_in_i)
BEGIN
IF(RISING_EDGE(clkb_in_i)) THEN
RESETB_SYNC_R1 <= RESET_IN;
RESETB_SYNC_R2 <= RESETB_SYNC_R1;
RESETB_SYNC_R3 <= RESETB_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST_A: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 32,
READ_WIDTH => 32 )
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => CHECKER_EN_R,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RSTA='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECK_DATA_TDP(0) AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_DATA_CHECKER_INST_B: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 32,
READ_WIDTH => 32 )
PORT MAP (
CLK => CLKB,
RST => RSTB,
EN => CHECKER_ENB_R,
DATA_IN => DOUTB,
STATUS => ISSUE_FLAG(1)
);
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(RSTB='1') THEN
CHECKER_ENB_R <= '0';
ELSE
CHECKER_ENB_R <= CHECK_DATA_TDP(1) AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLKA => CLKA,
CLKB => CLKB,
TB_RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
CHECK_DATA => CHECK_DATA_TDP
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
WEB_R <= (OTHERS=>'0') AFTER 50 ns;
DINB_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
WEB_R <= WEB AFTER 50 ns;
DINB_R <= DINB AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ADDRB_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
ADDRB_R <= ADDRB AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: RAM_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
DOUTA => DOUTA,
CLKA => CLKA,
--Port B
WEB => WEB_R,
ADDRB => ADDRB_R,
DINB => DINB_R,
DOUTB => DOUTB,
CLKB => CLKB
);
END ARCHITECTURE;
| gpl-3.0 | 730f941bfc8d5e5bb9a786593b2adb9a | 0.535861 | 3.621238 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/leon3v3/leon3s.vhd | 1 | 6,790 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: leon3s
-- File: leon3s.vhd
-- Author: Jan Andersson, Aeroflex Gaisler
-- Description: Top-level LEON3 component
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
entity leon3s is
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0;
pwd : integer range 0 to 2 := 2;
svt : integer range 0 to 1 := 1;
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0;
cached : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0;
rex : integer range 0 to 1 := 0;
altwin : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type
);
end;
architecture rtl of leon3s is
signal gnd, vcc : std_logic;
signal fpuo : grfpu_out_type;
begin
gnd <= '0'; vcc <= '1';
fpuo <= grfpu_out_none;
leon3x0 : leon3x
generic map (
hindex => hindex,
fabtech => fabtech,
memtech => memtech,
nwindows => nwindows,
dsu => dsu,
fpu => fpu,
v8 => v8,
cp => cp,
mac => mac,
pclow => pclow,
notag => notag,
nwp => nwp,
icen => icen,
irepl => irepl,
isets => isets,
ilinesize => ilinesize,
isetsize => isetsize,
isetlock => isetlock,
dcen => dcen,
drepl => drepl,
dsets => dsets,
dlinesize => dlinesize,
dsetsize => dsetsize,
dsetlock => dsetlock,
dsnoop => dsnoop,
ilram => ilram,
ilramsize => ilramsize,
ilramstart => ilramstart,
dlram => dlram,
dlramsize => dlramsize,
dlramstart => dlramstart,
mmuen => mmuen,
itlbnum => itlbnum,
dtlbnum => dtlbnum,
tlb_type => tlb_type,
tlb_rep => tlb_rep,
lddel => lddel,
disas => disas,
tbuf => tbuf,
pwd => pwd,
svt => svt,
rstaddr => rstaddr,
smp => smp,
iuft => 0,
fpft => 0,
cmft => 0,
iuinj => 0,
ceinj => 0,
cached => cached,
clk2x => 0,
netlist => 0,
scantest => scantest,
mmupgsz => mmupgsz,
bp => bp,
npasi => npasi,
pwrpsr => pwrpsr,
rex => rex,
altwin => altwin)
port map (
clk => gnd,
gclk2 => clk,
gfclk2 => clk,
clk2 => clk,
rstn => rstn,
ahbi => ahbi,
ahbo => ahbo,
ahbsi => ahbsi,
ahbso => ahbso,
irqi => irqi,
irqo => irqo,
dbgi => dbgi,
dbgo => dbgo,
fpui => open,
fpuo => fpuo,
clken => vcc
);
end;
| gpl-3.0 | 61e3f58cd180d2034b2258bb280ca870 | 0.461856 | 3.963806 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/uart/dcom.vhd | 1 | 5,672 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: dcom
-- File: dcom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: DSU Communications module
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.misc.all;
use gaisler.libdcom.all;
entity dcom is
port (
rst : in std_ulogic;
clk : in std_ulogic;
dmai : out ahb_dma_in_type;
dmao : in ahb_dma_out_type;
uarti : out dcom_uart_in_type;
uarto : in dcom_uart_out_type;
ahbi : in ahb_mst_in_type
);
end;
architecture struct of dcom is
type dcom_state_type is (idle, addr1, read1, read2, write1, write2);
type reg_type is record
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
len : std_logic_vector(5 downto 0);
write : std_ulogic;
clen : std_logic_vector(1 downto 0);
state : dcom_state_type;
hresp : std_logic_vector(1 downto 0);
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RES : reg_type := ((others => '0'), (others => '0'), (others => '0'), '0',
(others => '0'), idle, (others => '0'));
signal r, rin : reg_type;
begin
comb : process(dmao, rst, uarto, ahbi, r)
variable v : reg_type;
variable enable : std_ulogic;
variable newlen : std_logic_vector(5 downto 0);
variable vuarti : dcom_uart_in_type;
variable vdmai : ahb_dma_in_type;
variable newaddr : std_logic_vector(31 downto 2);
begin
v := r;
vuarti.read := '0'; vuarti.write := '0'; vuarti.data := r.data(31 downto 24);
vdmai.start := '0'; vdmai.burst := '0'; vdmai.size := "010"; vdmai.busy := '0';
vdmai.address := r.addr; vdmai.wdata := ahbdrivedata(r.data);
vdmai.write := r.write; vdmai.irq := '0';
-- save hresp
if dmao.ready = '1' then v.hresp := ahbi.hresp; end if;
-- address incrementer
newlen := r.len - 1;
newaddr := r.addr(31 downto 2) + 1;
case r.state is
when idle => -- idle state
v.clen := "00";
if uarto.dready = '1' then
if uarto.data(7) = '1' then v.state := addr1; end if;
v.write := uarto.data(6); v.len := uarto.data(5 downto 0);
vuarti.read := '1';
end if;
when addr1 => -- receive address
if uarto.dready = '1' then
v.addr := r.addr(23 downto 0) & uarto.data;
vuarti.read := '1'; v.clen := r.clen + 1;
end if;
if (r.clen(1) and not v.clen(1)) = '1' then
if r.write = '1' then v.state := write1; else v.state := read1; end if;
end if;
when read1 => -- read AHB
if dmao.active = '1' then
if dmao.ready = '1' then
v.data := ahbreadword(dmao.rdata); v.state := read2;
end if;
else vdmai.start := '1'; end if;
v.clen := "00";
when read2 => -- send read-data on uart
if uarto.thempty = '1' then
v.data := r.data(23 downto 0) & uarto.data;
vuarti.write := '1'; v.clen := r.clen + 1;
if (r.clen(1) and not v.clen(1)) = '1' then
v.addr(31 downto 2) := newaddr; v.len := newlen;
if (v.len(5) and not r.len(5)) = '1' then v.state := idle;
else v.state := read1; end if;
end if;
end if;
when write1 => -- receive write-data
if uarto.dready = '1' then
v.data := r.data(23 downto 0) & uarto.data;
vuarti.read := '1'; v.clen := r.clen + 1;
end if;
if (r.clen(1) and not v.clen(1)) = '1' then v.state := write2; end if;
when write2 => -- write AHB
if dmao.active = '1' then
if dmao.ready = '1' then
v.addr(31 downto 2) := newaddr; v.len := newlen;
if (v.len(5) and not r.len(5)) = '1' then v.state := idle;
else v.state := write1; end if;
end if;
else vdmai.start := '1'; end if;
v.clen := "00";
when others =>
v.state := idle; v.write := '0';
end case;
if (not RESET_ALL) and (uarto.lock and rst) = '0' then
v.state := RES.state; v.write := RES.write;
end if;
rin <= v; dmai <= vdmai; uarti <= vuarti;
end process;
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
if RESET_ALL and (uarto.lock and rst) = '0' then
r <= RES;
end if;
end if;
end process;
end;
| gpl-3.0 | 7f14ccdc1f29add6624948513750a591 | 0.552715 | 3.402519 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/eth/core/eth_edcl_ahb_mst.vhd | 1 | 4,714 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: eth_edcl_ahb_mst
-- File: eth_edcl_ahb_mst.vhd
-- Author: Marko Isomaki - Gaisler Research
-- Description: Ethernet EDCL MAC AHB master interface
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library eth;
use eth.grethpkg.all;
entity eth_edcl_ahb_mst is
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahbc_mst_in_type;
ahbmo : out ahbc_mst_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type
);
attribute sync_set_reset of rst : signal is "true";
end entity;
architecture rtl of eth_edcl_ahb_mst is
type reg_type is record
bg : std_ulogic; --bus granted
ba : std_ulogic; --bus active
bb : std_ulogic; --1kB burst boundary detected
retry : std_ulogic;
end record;
signal r, rin : reg_type;
begin
comb : process(rst, r, tmsti, ahbmi) is
variable v : reg_type;
variable htrans : std_logic_vector(1 downto 0);
variable hbusreq : std_ulogic;
variable hwrite : std_ulogic;
variable haddr : std_logic_vector(31 downto 0);
variable hwdata : std_logic_vector(31 downto 0);
variable tretry : std_ulogic;
variable tready : std_ulogic;
variable terror : std_ulogic;
variable tgrant : std_ulogic;
variable hsize : std_logic_vector(2 downto 0);
begin
v := r; htrans := HTRANS_IDLE; tready := '0'; tretry := '0';
terror := '0'; tgrant := '0';
hsize := HSIZE_WORD;
hwdata := tmsti.data;
hbusreq := tmsti.req;
if hbusreq = '1' then htrans := HTRANS_NONSEQ; end if;
haddr := tmsti.addr; hwrite := tmsti.write;
if (tmsti.req and r.ba and not r.retry) = '1' then
htrans := HTRANS_SEQ;
end if;
if (tmsti.req and r.bg and ahbmi.hready and not r.retry) = '1' then
tgrant := '1';
end if;
--1 kB burst boundary
if ahbmi.hready = '1' then
if haddr(9 downto 2) = "11111111" then
v.bb := '1';
else
v.bb := '0';
end if;
end if;
if (r.bb = '1') and (htrans /= HTRANS_IDLE) then
htrans := HTRANS_NONSEQ;
end if;
if r.ba = '1' then
if ahbmi.hready = '1' then
case ahbmi.hresp is
when HRESP_OKAY => tready := '1';
when HRESP_SPLIT | HRESP_RETRY => tretry := '1';
when HRESP_ERROR => terror := '1';
when others => null;
end case;
end if;
end if;
if (r.ba = '1') and
((ahbmi.hresp = HRESP_RETRY) or (ahbmi.hresp = HRESP_SPLIT))
then v.retry := not ahbmi.hready; else v.retry := '0'; end if;
if r.retry = '1' then htrans := HTRANS_IDLE; end if;
if ahbmi.hready = '1' then
v.bg := ahbmi.hgrant;
if (htrans = HTRANS_NONSEQ) or (htrans = HTRANS_SEQ) then
v.ba := r.bg;
else
v.ba := '0';
end if;
end if;
if rst = '0' then
v.bg := '0'; v.ba := '0'; v.bb := '0';
end if;
rin <= v;
tmsto.data <= ahbmi.hrdata;
tmsto.error <= terror;
tmsto.retry <= tretry;
tmsto.ready <= tready;
tmsto.grant <= tgrant;
ahbmo.htrans <= htrans;
ahbmo.hsize <= hsize;
ahbmo.hbusreq <= hbusreq;
ahbmo.haddr <= haddr;
ahbmo.hwrite <= hwrite;
ahbmo.hwdata <= hwdata;
end process;
regs : process(clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process;
ahbmo.hlock <= '0';
ahbmo.hburst <= HBURST_INCR;
ahbmo.hprot <= "0011";
end architecture;
| gpl-3.0 | bda8ae6c66076b2dfe27c3d3d7bda911 | 0.569156 | 3.628945 | false | false | false | false |
pwsoft/fpga_examples | rtl/ttl/ttl_74574.vhd | 1 | 4,314 | -- -----------------------------------------------------------------------
--
-- Syntiac VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2018 by Peter Wendrich ([email protected])
-- http://www.syntiac.com
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
-- Octal D-type flip-flop; positive edge-trigger; 3-state
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.ttl_pkg.all;
-- -----------------------------------------------------------------------
entity ttl_74574 is
generic (
latency : integer := 2
);
port (
emuclk : in std_logic;
p1 : in ttl_t; -- OEn
p2 : in ttl_t; -- D0
p3 : in ttl_t; -- D1
p4 : in ttl_t; -- D2
p5 : in ttl_t; -- D3
p6 : in ttl_t; -- D4
p7 : in ttl_t; -- D5
p8 : in ttl_t; -- D6
p9 : in ttl_t; -- D7
p11 : in ttl_t; -- CP
p12 : out ttl_t; -- Q7
p13 : out ttl_t; -- Q6
p14 : out ttl_t; -- Q5
p15 : out ttl_t; -- Q4
p16 : out ttl_t; -- Q3
p17 : out ttl_t; -- Q2
p18 : out ttl_t; -- Q1
p19 : out ttl_t -- Q0
);
end entity;
architecture rtl of ttl_74574 is
signal cp_ena : std_logic;
signal p12_loc : ttl_t;
signal p13_loc : ttl_t;
signal p14_loc : ttl_t;
signal p15_loc : ttl_t;
signal p16_loc : ttl_t;
signal p17_loc : ttl_t;
signal p18_loc : ttl_t;
signal p19_loc : ttl_t;
signal register_reg : unsigned(7 downto 0) := (others => '0');
begin
edge_inst : entity work.ttl_edge
port map (emuclk => emuclk, edge => '1', d => p1, ena => cp_ena);
p12_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p12_loc, q => p12);
p13_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p13_loc, q => p13);
p14_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p14_loc, q => p14);
p15_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p15_loc, q => p15);
p16_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p16_loc, q => p16);
p17_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p17_loc, q => p17);
p18_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p18_loc, q => p18);
p19_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p19_loc, q => p19);
p12_loc <= FLOAT when is_high(p1) else std2ttl(register_reg(7));
p13_loc <= FLOAT when is_high(p1) else std2ttl(register_reg(6));
p14_loc <= FLOAT when is_high(p1) else std2ttl(register_reg(5));
p15_loc <= FLOAT when is_high(p1) else std2ttl(register_reg(4));
p16_loc <= FLOAT when is_high(p1) else std2ttl(register_reg(3));
p17_loc <= FLOAT when is_high(p1) else std2ttl(register_reg(2));
p18_loc <= FLOAT when is_high(p1) else std2ttl(register_reg(1));
p19_loc <= FLOAT when is_high(p1) else std2ttl(register_reg(0));
process(emuclk)
begin
if rising_edge(emuclk) then
if cp_ena = '1' then
register_reg(0) <= ttl2std(p2);
register_reg(1) <= ttl2std(p3);
register_reg(2) <= ttl2std(p4);
register_reg(3) <= ttl2std(p5);
register_reg(4) <= ttl2std(p6);
register_reg(5) <= ttl2std(p7);
register_reg(6) <= ttl2std(p8);
register_reg(7) <= ttl2std(p9);
end if;
end if;
end process;
end architecture;
| lgpl-2.1 | 1e83f9e9c07ba172a0a25c7161f94474 | 0.58994 | 2.87984 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/pci/grpci2/grpci2.vhd | 1 | 268,632 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grpci2
-- File: grpci2.vhd
-- Author: Nils-Johan Wessman - Aeroflex Gaisler
-- Description: PCI master and target interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use grlib.dftlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.pci.all;
use work.pcilib2.all;
entity grpci2 is
generic (
memtech : integer := DEFMEMTECH;
tbmemtech : integer := DEFMEMTECH; -- For trace buffers
oepol : integer := 0;
hmindex : integer := 0;
hdmindex : integer := 0;
hsindex : integer := 0;
haddr : integer := 0;
hmask : integer := 0;
ioaddr : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
irq : integer := 0;
irqmode : integer range 0 to 3 := 0;
master : integer range 0 to 1 := 1;
target : integer range 0 to 1 := 1;
dma : integer range 0 to 1 := 1;
tracebuffer : integer range 0 to 16384 := 0;
confspace : integer range 0 to 1 := 1;
vendorid : integer := 16#0000#;
deviceid : integer := 16#0000#;
classcode : integer := 16#000000#;
revisionid : integer := 16#00#;
cap_pointer : integer := 16#40#;
ext_cap_pointer : integer := 16#00#;
iobase : integer := 16#FFF#;
extcfg : integer := 16#0000000#;
bar0 : integer range 0 to 31 := 28;
bar1 : integer range 0 to 31 := 0;
bar2 : integer range 0 to 31 := 0;
bar3 : integer range 0 to 31 := 0;
bar4 : integer range 0 to 31 := 0;
bar5 : integer range 0 to 31 := 0;
bar0_map : integer := 16#000000#;
bar1_map : integer := 16#000000#;
bar2_map : integer := 16#000000#;
bar3_map : integer := 16#000000#;
bar4_map : integer := 16#000000#;
bar5_map : integer := 16#000000#;
bartype : integer range 0 to 65535 := 16#0000#;
barminsize : integer range 5 to 31 := 12;
fifo_depth : integer range 3 to 7 := 3;
fifo_count : integer range 2 to 4 := 2;
conv_endian : integer range 0 to 1 := 1; -- 1: little (PCI) <~> big (AHB), 0: big (PCI) <=> big (AHB)
deviceirq : integer range 0 to 1 := 1;
deviceirqmask : integer range 0 to 15 := 16#0#;
hostirq : integer range 0 to 1 := 1;
hostirqmask : integer range 0 to 15 := 16#0#;
nsync : integer range 0 to 2 := 2; -- with nsync = 0, wrfst needed on syncram...
hostrst : integer range 0 to 2 := 0; -- 0: PCI reset is never driven, 1: PCI reset is driven from AHB reset if host, 2: PCI reset is always driven from AHB reset
bypass : integer range 0 to 1 := 1;
ft : integer range 0 to 1 := 0;
scantest : integer range 0 to 1 := 0;
debug : integer range 0 to 1 := 0;
tbapben : integer range 0 to 1 := 0;
tbpindex : integer := 0;
tbpaddr : integer := 0;
tbpmask : integer := 16#F00#;
netlist : integer range 0 to 1 := 0; -- Use PHY netlist
multifunc : integer range 0 to 1 := 0; -- Enables Multi-function support
multiint : integer range 0 to 1 := 0;
masters : integer := 16#FFFF#;
mf1_deviceid : integer := 16#0000#;
mf1_classcode : integer := 16#000000#;
mf1_revisionid : integer := 16#00#;
mf1_bar0 : integer range 0 to 31 := 0;
mf1_bar1 : integer range 0 to 31 := 0;
mf1_bar2 : integer range 0 to 31 := 0;
mf1_bar3 : integer range 0 to 31 := 0;
mf1_bar4 : integer range 0 to 31 := 0;
mf1_bar5 : integer range 0 to 31 := 0;
mf1_bartype : integer range 0 to 65535 := 16#0000#;
mf1_bar0_map : integer := 16#000000#;
mf1_bar1_map : integer := 16#000000#;
mf1_bar2_map : integer := 16#000000#;
mf1_bar3_map : integer := 16#000000#;
mf1_bar4_map : integer := 16#000000#;
mf1_bar5_map : integer := 16#000000#;
mf1_cap_pointer : integer := 16#40#;
mf1_ext_cap_pointer : integer := 16#00#;
mf1_extcfg : integer := 16#0000000#;
mf1_masters : integer := 16#0000#;
iotest : integer := 0
);
port(
rst : in std_logic;
clk : in std_logic;
pciclk : in std_logic;
dirq : in std_logic_vector(3 downto 0);
pcii : in pci_in_type;
pcio : out pci_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbdmi : in ahb_mst_in_type;
ahbdmo : out ahb_mst_out_type;
ptarst : out std_logic;
tbapbi : in apb_slv_in_type := apb_slv_in_none;
tbapbo : out apb_slv_out_type;
debugo : out std_logic_vector(debug*255 downto 0)
);
end;
architecture rtl of grpci2 is
-- PHY =>
signal phyi : grpci2_phy_in_type;
signal phyo : grpci2_phy_out_type;
signal sig_m_request, sig_m_mabort, sig_t_abort, sig_t_ready, sig_t_retry : std_logic;
signal sig_pr_conf_comm_serren, sig_pr_conf_comm_perren : std_logic;
signal sig_soft_rst : std_logic_vector(2 downto 0);
-- PHY <=
constant PT_DEPTH : integer := 5 + log2(tracebuffer/32);
constant HIOMASK : integer := 16#E00# - 16#200#*conv_integer(conv_std_logic(tracebuffer/=0));
constant MST_ACC_CNT : integer := fifo_count - 1;
constant RAM_LATENCY : integer := 1 + ram_raw_latency(memtech); -- Delay FIFO readout one extra write clock cycle for some technologies
type pci_bars_type is array (0 to 5) of std_logic_vector(31 downto 0);
constant pci_bars_none : pci_bars_type := (others => (others => '0'));
type pci_config_space_type is record
bar : pci_bars_type;
comm : pci_config_command_type;
stat : pci_config_status_type;
ltimer : std_logic_vector(7 downto 0);
iline : std_logic_vector(7 downto 0);
pta_map : pci_bars_type; -- PCI to AHB mapping for each PCI bar
bar_mask : pci_bars_type; -- PCI bar mask (bar size)
cfg_map : std_logic_vector(31 downto 0);-- Map extended PCI configuration space to AHB address
end record;
constant pci_config_space_none : pci_config_space_type := (pci_bars_none, pci_config_command_none, pci_config_status_none, (others => '0'), (others => '0'), pci_bars_none, pci_bars_none, (others => '0'));
type pci_config_space_multi_type is array (0 to multifunc) of pci_config_space_type;
type pci_fifo_out_type is record
data : std_logic_vector(31 downto 0);
err : std_logic_vector(3 downto 0);
end record;
constant pci_fifo_out_none : pci_fifo_out_type := ((others => '0'), (others => '0'));
type pci_fifo_in_type is record
en : std_logic; -- Read/write enable for fifo
addr : std_logic_vector((FIFO_DEPTH+log2(FIFO_COUNT))-1 downto 0); -- Fifo address
data : std_logic_vector(31 downto 0); -- Fifo input data
end record;
constant pci_fifo_in_none : pci_fifo_in_type := ('0', zero32((FIFO_DEPTH+log2(FIFO_COUNT))-1 downto 0), (others => '0'));
type pci_g_acc_trans_type is record
pending : std_logic; -- Access pending (valid)
addr : std_logic_vector(31 downto 0); -- Access start address
acctype : std_logic_vector(3 downto 0); -- Access type (conf_read/write, io_read/write, data_read/write)
accmode : std_logic_vector(2 downto 0); -- Access mode (use cancel, use length, burst)
size : std_logic_vector(2 downto 0); -- Access size
offset : std_logic_vector(1 downto 0); -- Access byte offset
index : integer range 0 to FIFO_COUNT-1;-- FIFO index for first data
length : std_logic_vector(15 downto 0); -- Access length
func : std_logic_vector(2 downto 0); -- The master belongs to this PCI function
--
cbe : std_logic_vector(3 downto 0); -- Byte enable (size and offset)
endianess : std_logic; -- PCI bus endianess
end record;
constant pci_g_acc_trans_none : pci_g_acc_trans_type := ('0', (others => '0'), (others => '0'), (others => '0'), (others => '0'), (others => '0'), 0, (others => '0'), (others => '0'), (others => '0'), '0');
type pci_g_acc_status_trans_type is record
done : std_logic; -- Access done
status : std_logic_vector(3 downto 0); -- Access status
count : std_logic_vector(15 downto 0);-- Access transfer count
end record;
constant pci_g_acc_status_trans_none : pci_g_acc_status_trans_type := ('0', (others => '0'), (others => '0'));
type pci_g_acc_status_trans_multi_type is array (0 to 1) of pci_g_acc_status_trans_type;
constant pci_g_acc_status_trans_multi_none : pci_g_acc_status_trans_multi_type := (others => pci_g_acc_status_trans_none);
type pci_g_fifo_trans_type is record
pending : std_logic_vector(2 downto 0); -- FIFO pending (valid)
start : std_logic_vector(FIFO_DEPTH-1 downto 0);-- FIFO start address (first valid data)
stop : std_logic_vector(FIFO_DEPTH-1 downto 0);-- FIFO stop address (last valid data)
firstf : std_logic; -- First FIFO
lastf : std_logic; -- Last FIFO
status : std_logic_vector(3 downto 0); -- Error status
--
last_cbe : std_logic_vector(3 downto 0); -- Byte enable of last data
end record;
constant pci_g_fifo_trans_none : pci_g_fifo_trans_type := ((others => '0'), zero32(FIFO_DEPTH-1 downto 0), zero32(FIFO_DEPTH-1 downto 0), '0', '0', (others => '0'), (others => '0'));
type pci_g_acc_trans_multi_type is array (0 to 1) of pci_g_acc_trans_type;
constant pci_g_acc_trans_multi_none : pci_g_acc_trans_multi_type := (others => pci_g_acc_trans_none);
type pci_g_acc_trans_vector_type is array (0 to 3) of pci_g_acc_trans_type;
constant pci_g_acc_trans_vector_none : pci_g_acc_trans_vector_type := (others => pci_g_acc_trans_none);
type pci_g_acc_trans_vector_multi_type is array (0 to 1) of pci_g_acc_trans_vector_type;
constant pci_g_acc_trans_vector_multi_none : pci_g_acc_trans_vector_multi_type := (others => pci_g_acc_trans_vector_none);
type pci_g_fifo_trans_vector_type is array (0 to FIFO_COUNT-1) of pci_g_fifo_trans_type;
constant pci_g_fifo_trans_vector_none: pci_g_fifo_trans_vector_type := (others => pci_g_fifo_trans_none);
type pci_g_fifo_trans_vector_multi_type is array (0 to 1) of pci_g_fifo_trans_vector_type;
constant pci_g_fifo_trans_vector_multi_none : pci_g_fifo_trans_vector_multi_type := (others => pci_g_fifo_trans_vector_none);
subtype pci_g_fifo_ack_trans_vector_type is std_logic_vector(FIFO_COUNT-1 downto 0);
constant pci_g_fifo_ack_trans_vector_none : pci_g_fifo_ack_trans_vector_type := (others => '0');
type pci_g_fifo_ack_trans_vector_multi_type is array (0 to 1) of pci_g_fifo_ack_trans_vector_type;
constant pci_g_fifo_ack_trans_vector_multi_none : pci_g_fifo_ack_trans_vector_multi_type := (others => pci_g_fifo_ack_trans_vector_none);
type pci_master_acc_type is record
pending : std_logic; -- Access valid
addr : std_logic_vector(31 downto 0); -- Access start address
cmd : std_logic_vector(3 downto 0); -- Access type (conf_read/write, io_read/write, data_read/write)
cbe : std_logic_vector(3 downto 0); -- Byte enable (size and offset)
endianess : std_logic; -- PCI bus endianess
mode : std_logic_vector(2 downto 0); -- Mode[use length, burst]
length : std_logic_vector(15 downto 0); -- Access length
active : std_logic_vector(1 downto 0); -- [1]: access has data to transfer, [0]: access active
done : std_logic_vector(2 downto 0); -- [2]: access terminated by error, [1]:(PCI master write: all pending fifos acked), [0]: access done
status : std_logic_vector(2 downto 0); -- Error status
first : std_logic; -- First data in access
func : integer range 0 to multifunc; -- PCI function accessed
--
fifo_index : integer range 0 to FIFO_COUNT-1;-- FIFO index for first data
fifo_addr : std_logic_vector(FIFO_DEPTH-1 downto 0); -- Fifo address
fifo_wen : std_logic; -- FIFO write enable
fifo_ren : std_logic; -- FIFO read enable
end record;
constant pci_master_acc_none : pci_master_acc_type := ('0', (others => '0'), (others => '0'), (others => '0'), '0', (others => '0'),
(others => '0'), (others => '0'), (others => '0'), (others => '0'), '0', 0, 0, zero32(FIFO_DEPTH-1 downto 0), '0', '0');
type pci_master_acc_multi_type is array (0 to 1) of pci_master_acc_type;
constant pci_master_acc_multi_none : pci_master_acc_multi_type := (pci_master_acc_none, pci_master_acc_none);
constant acc_sel_ahb : integer := 0;
constant acc_sel_dma : integer := 1;
type ahb_master_acc_type is record
pending : std_logic; -- Access valid
addr : std_logic_vector(31 downto 0); -- Access start address
cbe : std_logic_vector(3 downto 0); -- Access byte enable (size and offset)
endianess : std_logic; -- PCI bus endianess
acctype : std_logic_vector(3 downto 0); --
mode : std_logic_vector(2 downto 0); -- Mode[use length, burst]
length : std_logic_vector(15 downto 0); -- Access length
burst : std_logic; -- Same as accmode(0);
--
fifo_index : integer range 0 to FIFO_COUNT-1;-- FIFO index for first data
fifo_addr : std_logic_vector((FIFO_DEPTH+log2(FIFO_COUNT))-1 downto 0); -- Fifo address
fifo_wen : std_logic; -- FIFO write enable
fifo_ren : std_logic; -- FIFO read enable
fifo_wdata : std_logic_vector(31 downto 0);
end record;
constant ahb_master_acc_none : ahb_master_acc_type := ('0', (others => '0'), (others => '0'), '0', (others => '0'), (others => '0'),
(others => '0'), '0', 0, (others => '0'), '0', '0', (others => '0'));
type pci_fifo_type is record
index : integer range 0 to FIFO_COUNT-1;-- FIFO index
ctrl : pci_fifo_in_type; -- FIFO RAM control signal
end record;
constant pci_fifo_none : pci_fifo_type := (0, pci_fifo_in_none);
type pci_access_type is record
addr : std_logic_vector(31 downto 0); -- Access address
ready : std_logic; -- Data ready
pending : std_logic; -- Access saved and pending
read : std_logic; -- Target read / write access
burst : std_logic; -- Burst access
retry : std_logic; -- Access terminated with retry
acc_type: std_logic_vector(1 downto 0); -- Access type: 00: memory, 10: configuration space, 11: mapping registers, 01: ext conf space mapped to AHB
bar : std_logic_vector(5 downto 0); -- PCI bar accessed
func : integer range 0 to multifunc; -- PCI function accessed
match : std_logic; -- Access matching pending access
continue: std_logic; -- Burst may continue
newacc : std_logic; -- New access, discard old data
oldburst: std_logic; -- When "new access" store last burst
impcfgreg: std_logic; -- Indicates if the current Configuration Space register is implemented
end record;
constant pci_access_none : pci_access_type := ((others => '0'), '0', '0', '0', '0', '0', (others => '0'), (others => '0'), 0, '0', '0', '0', '0', '1');
type pci_access_vector_type is array (0 to 1) of pci_access_type;
constant pci_access_vector_none : pci_access_vector_type := (others => pci_access_none);
type pci_target_type is record
state : pci_target_state_type;
fstate : pci_target_fifo_state_type;
cfifo : pci_core_fifo_vector_type; -- Core FIFO
atp : pci_fifo_type; -- AMBA to PCI FIFO
pta : pci_fifo_type; -- PCI to AMBA FIFO
addr : std_logic_vector(31 downto 0);-- Used as FIFO address during write
cur_acc : pci_access_vector_type; -- Current PCI access
lcount : std_logic_vector(2 downto 0); -- Target latency counter 8 clocks (initial latency should 16 clocks)
preload : std_logic; -- Preload the internal FIFO
preload_count : std_logic_vector(1 downto 0); -- Counter used when preloading the internal FIFO
stop : std_logic;
stoped : std_logic;
hold : std_logic_vector(0 downto 0);
hold_fifo : std_logic;
hold_reset : std_logic;
hold_write : std_logic;
first : std_logic_vector(1 downto 0); -- Used to mark first fifo. bit[1]: first fifo in transfer, bit[0]: first word in fifo
conf_addr : std_logic_vector(3 downto 0);
first_word : std_logic; -- Indicate first word in access
diswithout : std_logic; -- Disconnect without data
addr_perr : std_logic; -- Address Parity Error detected
abort : std_logic; -- Target abort
retry : std_logic;
discard : std_logic;
accbuf : pci_g_acc_trans_vector_type; -- PCI target to AHB master access buffer
blen : std_logic_vector(15 downto 0);-- PCI target burst length boundary
blenmask : std_logic_vector(15 downto 0);-- PCI target burst length boundary mask
saverfifo : std_logic; -- Save prefetched FIFO until next PCI access in case of target termination (disconnect without data)
discardtimeren : std_logic; -- Enable/Disable discard timer
discardtimer : std_logic_vector(15 downto 0);-- Discard prefetched data after 2^15 PCI clock cycles
end record;
constant pci_target_none : pci_target_type := (
pt_idle, ptf_idle, pci_core_fifo_vector_none, pci_fifo_none, pci_fifo_none,
(others => '0'), pci_access_vector_none, (others => '0'), '0', (others => '0'), '0', '0',
(others => '0'), '0', '0', '0', (others => '0'), (others => '0'),
'0', '0', '0', '0', '0', '0', pci_g_acc_trans_vector_none, (others => '0'),
(others => '0'), '0', '0', (others => '0'));
type pci_master_type is record
state : pci_master_state_type;
fstate : pci_master_fifo_state_type;
cfifo : pci_core_fifo_vector_type; -- Core FIFO
abort : std_logic_vector(1 downto 0); -- Master/Target abort [0]: master or target abort; [1]: 1 = target abort, 0 = master abort
ltimer : std_logic_vector(7 downto 0); -- PCI master latency timer
framedel : std_logic; -- Delayed frame
devsel_tout : std_logic_vector(2 downto 0); -- Devsel time out conter;
devsel_asserted : std_logic; -- Devsel asserted;
addr : std_logic_vector(31 downto 0);-- PCI state address
cbe_data : std_logic_vector(3 downto 0);
cbe_cmd : std_logic_vector(3 downto 0);
hold : std_logic_vector(1 downto 0); -- Hold transfer due to no available fifo
hold_fifo : std_logic; -- Hold FIFO due to no available fifo
done_fifo : std_logic; -- No more FIFO Available
done_trans : std_logic; -- No more data in FIFO (transfer done)
term : std_logic_vector(1 downto 0); -- Terminate transfer
done : std_logic; -- Transfer done
first : std_logic_vector(1 downto 0); -- First word in current access
last : std_logic_vector(1 downto 0); -- Last word in transfer
preload : std_logic;
preload_count : std_logic_vector(1 downto 0);
afull : std_logic; -- FIFO almost full on read
afullcnt : std_logic_vector(1 downto 0); -- Counter for the three last word in FIFO on read
burst : std_logic; -- Read burst access => signle accecc or preload
perren : std_logic_vector(1 downto 0); -- bit[0]: Drive output enable for Parity error, bit[1] delayed bit[0]
detectperr : std_logic_vector(1 downto 0); -- bit[2] = 1: Detect Parity error on write
twist : std_logic; -- On for PCI configuration space access, otherwise = pr.pta_trans.ca_twist
first_word : std_logic; -- Indicate first word in access
waitonstop : std_logic;
acc : pci_master_acc_multi_type; -- DMA/AHB slave => PCI master accesses
acc_sel : integer range 0 to 1; -- Active access, 0 = AHB slave; 1 = DMA
acc_cnt : integer range 0 to MST_ACC_CNT; -- Access transfer count (FIFO), for switching DMA/AHB-slave
acc_switch : std_logic; -- Access switching DMA/AHB-slave
fifo_addr : std_logic_vector((FIFO_DEPTH+log2(FIFO_COUNT))-1 downto 0); -- Fifo address
fifo_wdata : std_logic_vector(31 downto 0);
fifo_switch : std_logic;
end record;
constant pci_master_none : pci_master_type := (
pm_idle, pmf_idle, pci_core_fifo_vector_none, (others => '0'), (others => '0'), '0',
(others => '0'), '0', (others => '0'), (others => '0'), (others => '0'), (others => '0'), '0',
'0', '0', (others => '0'), '0', (others => '0'), (others => '0'), '0', (others => '0'), '0',
(others => '0'), '0', (others => '0'), (others => '0'), '0', '0', '0', pci_master_acc_multi_none,
0, 0, '0', zero32((FIFO_DEPTH+log2(FIFO_COUNT))-1 downto 0), (others => '0'), '0');
type pci_trace_to_apb_trans_type is record
enable : std_logic;
armed : std_logic;
wrap : std_logic;
taddr : std_logic_vector(PT_DEPTH-1 downto 0);
start_ack : std_logic;
stop_ack : std_logic;
--
dbg_ad : std_logic_vector(31 downto 0);
dbg_sig : std_logic_vector(16 downto 0);
dbg_cur_ad : std_logic_vector(31 downto 0);
dbg_cur_acc : std_logic_vector(8 downto 0);
end record;
constant pci_trace_to_apb_trans_none : pci_trace_to_apb_trans_type := ('0', '0', '0', zero32(PT_DEPTH-1 downto 0), '0', '0',
(others => '0'), (others => '0'), (others => '0'), (others => '0'));
type apb_to_pci_trace_trans_type is record
start : std_logic;
stop : std_logic;
mode : std_logic_vector(3 downto 0);
count : std_logic_vector(PT_DEPTH-1 downto 0);
tcount : std_logic_vector(7 downto 0);
ad : std_logic_vector(31 downto 0);
admask : std_logic_vector(31 downto 0);
sig : std_logic_vector(16 downto 0);
sigmask : std_logic_vector(16 downto 0);
end record;
constant apb_to_pci_trace_trans_none : apb_to_pci_trace_trans_type := ('0', '0', (others => '0'), zero32(PT_DEPTH-1 downto 0),
(others => '0'), (others => '0'), (others => '0'), (others => '0'), (others => '0'));
type pci_trace_type is record
addr : std_logic_vector(PT_DEPTH-1 downto 0);
count : std_logic_vector(PT_DEPTH-1 downto 0);
tcount : std_logic_vector(7 downto 0);
end record;
constant pci_trace_none : pci_trace_type := (zero32(PT_DEPTH-1 downto 0), zero32(PT_DEPTH-1 downto 0), (others => '0'));
type pci_msd_acc_cancel_acc_multi_type is array (0 to 1) of std_logic_vector(2 downto 0);
type pci_to_ahb_trans_type is record
-- PCI target <=> AHB master
tm_acc : pci_g_acc_trans_type; -- AHB master access (read/write) [PCI target]
tm_acc_cancel : std_logic; -- Cancel access [PCI target]
tm_acc_done_ack : std_logic; -- Ack access done [PCI target]
tm_fifo : pci_g_fifo_trans_vector_type; -- PCI target => AHB master FIFO
tm_fifo_ack : pci_g_fifo_ack_trans_vector_type; -- AHB master => PCI target FIFO ack
-- PCI master <=> AHB slave / DMA
msd_acc_ack : std_logic_vector(0 to 1); -- PCI master access ack [AHB/DMA]
--msd_acc_cancel_ack : std_logic_vector(0 to 1); -- Cancel access ack [AHB/DMA]
msd_acc_cancel_ack : pci_msd_acc_cancel_acc_multi_type; -- Cancel access ack [AHB/DMA]
msd_acc_done : pci_g_acc_status_trans_multi_type; -- Access status [AHB/DMA]
msd_fifo : pci_g_fifo_trans_vector_multi_type; -- PCI master => AHB/DMA slave FIFO
msd_fifo_ack : pci_g_fifo_ack_trans_vector_multi_type; -- AHB/DMA slave => PCI master FIFO ack
-- PCI config space <=> AHB
ca_host : std_logic;
ca_pcimsten : std_logic_vector(0 to multifunc);
ca_twist : std_logic; -- 1: byte twisting litle (PCI) <~> big (AHB), 0: big (PCI) <=> big (AHB)
-- PCI system
pa_serr : std_logic;
pa_discardtout: std_logic;
rst_ack : std_logic_vector(2 downto 0);
end record;
type ahb_to_pci_trans_type is record
-- PCI target <=> AHB master
tm_acc_ack : std_logic; -- AHB master access ack [PCI target]
tm_acc_cancel_ack : std_logic_vector(2 downto 0); -- Cancel access ack [PCI target]
tm_acc_done : pci_g_acc_status_trans_type; -- Access status [PCI target]
tm_fifo : pci_g_fifo_trans_vector_type; -- AHB master => PCI target FIFO
tm_fifo_ack : pci_g_fifo_ack_trans_vector_type; -- PCI target => AHB master FIFO ack
-- PCI master <=> AHB slave / DMA
msd_acc : pci_g_acc_trans_multi_type; -- PCI master access (read/write) [AHB/DMA]
msd_acc_cancel : std_logic_vector(1 downto 0); -- Cancel access [AHB/DMA]
msd_acc_done_ack : std_logic_vector(1 downto 0); -- Ack access done [AHB/DMA]
msd_fifo : pci_g_fifo_trans_vector_multi_type; -- AHB/DMA slave => PCI master FIFO
msd_fifo_ack : pci_g_fifo_ack_trans_vector_multi_type; -- PCI master => AHB/DMA slave FIFO ack
-- PCI system
pa_serr_rst : std_logic;
pa_discardtout_rst: std_logic;
rst : std_logic_vector(2 downto 0);
mstswdis : std_logic;
end record;
type pci_sync_type is array (1 to 2) of ahb_to_pci_trans_type;
type ahb_sync_type is array (1 to 2) of pci_to_ahb_trans_type;
type pci_trace_sync_type is array (1 to 2) of apb_to_pci_trace_trans_type;
type apb_sync_type is array (1 to 2) of pci_trace_to_apb_trans_type;
type ahb_to_pci_map_type is array (0 to 15) of std_logic_vector(31 downto 0);
constant ahb_to_pci_map_none : ahb_to_pci_map_type := (others => (others => '0'));
-- Calculate AADDR_WIDTH for HMASK
function calc_aaddr_width(di : in integer) return integer is
variable bits : integer;
begin
if di = 16#800# then bits := 31;
elsif di = 16#c00# then bits := 30;
elsif di = 16#e00# then bits := 29;
elsif di = 16#f00# then bits := 28;
elsif di = 16#f80# then bits := 27;
elsif di = 16#fc0# then bits := 26;
elsif di = 16#fe0# then bits := 25;
elsif di = 16#ff0# then bits := 24;
elsif di = 16#ff8# then bits := 23;
elsif di = 16#ffc# then bits := 22;
elsif di = 16#ffe# then bits := 21;
elsif di = 16#fff# then bits := 20;
else bits := 4; end if;
return bits;
end function;
constant AADDR_WIDTH : integer := calc_aaddr_width(hmask);
type pci_reg_type is record
conf : pci_config_space_multi_type;-- Configuration Space
po : pci_reg_out_type; -- PCI output signals
m : pci_master_type; -- PCI Master
t : pci_target_type; -- PCI Target
pta_trans : pci_to_ahb_trans_type;-- Signals between PCI clock domain and AHB clock domain (need synchronisation)
sync : pci_sync_type;
pt : pci_trace_type;
ptta_trans: pci_trace_to_apb_trans_type;
pt_sync : pci_trace_sync_type;
pciinten : std_logic_vector(3 downto 0); -- Drives output enable for INTA..D
pci66 : std_logic_vector(1 downto 0);
debug : std_logic_vector(31 downto 0);
end record;
subtype AHB_FIFO_BITS is natural range FIFO_DEPTH + 1 downto 2;
type amba_master_state_type is (am_idle, am_read, am_write, am_error);
type amba_master_type is record
state : amba_master_state_type;
first : std_logic_vector(2 downto 0); -- First data in access (mark starting fifo)
done : std_logic_vector(2 downto 0);
stop : std_logic;
dmai0 : dma_ahb_in_type;
dma_hold : std_logic;
active : std_logic;
retry : std_logic;
retry_blen: std_logic_vector(15 downto 0);
retry_size: std_logic_vector(1 downto 0);
retry_offset: std_logic_vector(1 downto 0);
acc : ahb_master_acc_type; -- PCI target => AHB master accesses
hold : std_logic_vector(2 downto 0);
last : std_logic_vector(2 downto 0);
faddr : std_logic_vector(AHB_FIFO_BITS);
blen : std_logic_vector(15 downto 0);
end record;
constant amba_master_none : amba_master_type := (
am_idle, (others => '0'), (others => '0'), '0', dma_ahb_in_none, '0', '0', '0', (others => '0'), (others => '0'),
(others => '0'), ahb_master_acc_none, (others => '0'), (others => '0'), (others => '0'), (others => '0'));
type amba_slave_state_type is (as_idle, as_checkpcimst, as_read, as_write, as_pcitrace);
type amba_slave_type is record
state : amba_slave_state_type;
atp : pci_fifo_type;
pta : pci_fifo_type;
hready : std_logic;
hwrite : std_logic;
hsel : std_logic;
hmbsel : std_logic_vector(0 to 2);
hresp : std_logic_vector(1 downto 0);
htrans : std_logic_vector(1 downto 0);
hsize : std_logic_vector(2 downto 0);
hmaster : std_logic_vector(3 downto 0);
hburst : std_logic;
haddr : std_logic_vector(31 downto 0);
retry : std_logic;
first : std_logic; -- First access in transfer
firstf : std_logic; -- First fifo
pending : std_logic_vector(1 downto 0);
addr : std_logic_vector(31 downto 0);
offset : std_logic_vector(1 downto 0);
master : std_logic_vector(3 downto 0);
write : std_logic;
oneword : std_logic;
burst : std_logic;
config : std_logic;
io : std_logic;
size : std_logic_vector(2 downto 0);
start : std_logic;
hrdata : std_logic_vector(31 downto 0);
continue : std_logic;
discard : std_logic;
atp_map : ahb_to_pci_map_type;
io_map : std_logic_vector(31 downto 16);
cfg_bus : std_logic_vector(23 downto 16);
cfg_status: std_logic_vector(1 downto 0);
io_cfg_burst : std_logic_vector(1 downto 0); -- Alow burst on PCI IO / CONF
erren : std_logic; -- Enables AHB error response for Master/Target abort
parerren : std_logic; -- Enables AHB error response for PAR error
accbuf : pci_g_acc_trans_vector_type; -- AHB slave to PCI master access buffer
blen : std_logic_vector(7 downto 0); -- AHB slave prefetch burst length
blenmask : std_logic_vector(15 downto 0); -- AHB slave prefetch length AHB master mask
done_fifo : std_logic_vector(1 downto 0);
tb_ren : std_logic; -- PCI trace buffer read enable
fakehost : std_logic; -- Fake device in system slot (HOST)
stoppciacc: std_logic;
end record;
constant amba_slave_none : amba_slave_type := (
as_idle, pci_fifo_none, pci_fifo_none, '1', '0', '0', (others => '0'), (others => '0'),
(others => '0'), (others => '0'), (others => '0'), '0', (others => '0'), '0', '0', '0',
(others => '0'), (others => '0'), (others => '0'), (others => '0'), '0', '0', '0', '0', '0',
(others => '0'), '0', (others => '0'), '0', '0', ahb_to_pci_map_none, (others => '0'),
(others => '0'), (others => '0'), (others => '0'), '0', '0', pci_g_acc_trans_vector_none,
(others => '0'), (others => '0'), (others => '0'), '0', '0', '0');
type irq_reg_type is record
device_mask : std_logic_vector(3 downto 0);
device_force : std_logic;
host_mask : std_logic_vector(3 downto 0);
host_status : std_logic_vector(3 downto 0);
host_pirq_vl : std_logic_vector(3 downto 0);
host_pirq_l : std_logic;
access_en : std_logic; -- Enables IRQ for Master/Target abort and PAR error
access_status: std_logic_vector(2 downto 0);
access_pirq : std_logic;
access_pirq_l: std_logic;
system_en : std_logic; -- Enables IRQ for System error
system_status: std_logic_vector(1 downto 0);
system_pirq : std_logic;
system_pirq_l: std_logic;
dma_pirq_l : std_logic;
irqen : std_logic;
end record;
constant irq_reg_none : irq_reg_type := (
(others => '0'), '0', (others => '0'), (others => '0'), (others => '0'),
'0', '0', (others => '0'), '0', '0', '0', (others => '0'), '0', '0', '0', '0');
type dma_state_type is (dma_idle, dma_read_desc, dma_next_channel, dma_write_status, dma_read, dma_write, dma_error);
type dma_desc_type is record
en : std_logic;
irqen : std_logic;
write : std_logic;
tw : std_logic;
desctype: std_logic_vector(1 downto 0);
cio : std_logic_vector(1 downto 0);
len : std_logic_vector(15 downto 0);
ch : std_logic_vector(31 downto 0);
nextch : std_logic_vector(31 downto 0);
addr : std_logic_vector(31 downto 0);
nextdesc: std_logic_vector(31 downto 0);
cnt : std_logic_vector(15 downto 0);
emptych : std_logic;
chcnt : std_logic_vector(2 downto 0);
paddr : std_logic_vector(31 downto 0);
aaddr : std_logic_vector(31 downto 0);
acctype : std_logic_vector(3 downto 0);
chid : std_logic_vector(2 downto 0);
end record;
constant dma_desc_none : dma_desc_type := (
'0', '0', '0', '0', (others => '0'), (others => '0'), (others => '0'), (others => '0'),
(others => '0'), (others => '0'), (others => '0'), (others => '0'), '0',
(others => '0'), (others => '0'), (others => '0'), (others => '0'), (others => '0'));
type dma_reg_type is record
state : dma_state_type;
dmai1 : dma_ahb_in_type;
desc : dma_desc_type;
dtp : pci_fifo_type;
ptd : pci_fifo_type;
rcnt : std_logic_vector(1 downto 0);
en : std_logic;
err : std_logic_vector(2 downto 0);
errlen : std_logic_vector(15 downto 0);
numch : std_logic_vector(2 downto 0);
dma_hold : std_logic_vector(2 downto 0);
dma_last : std_logic_vector(2 downto 0);
newfifo : std_logic;
active : std_logic;
done : std_logic_vector(1 downto 0);
faddr : std_logic_vector(AHB_FIFO_BITS);
first : std_logic_vector(2 downto 0);
retry : std_logic;
retry_len : std_logic_vector(15 downto 0);
addr : std_logic_vector(31 downto 0);
irq : std_logic;
irqen : std_logic;
irqstatus : std_logic_vector(1 downto 0);
len : std_logic_vector(15 downto 0);
errstatus : std_logic_vector(4 downto 0); -- DMA error status
irqch : std_logic_vector(7 downto 0); -- DMA Channel irq status
running : std_logic; -- DMA is running
end record;
constant dma_reg_none : dma_reg_type := (
dma_idle, dma_ahb_in_none, dma_desc_none, pci_fifo_none, pci_fifo_none,
(others => '0'), '0', (others => '0'), (others => '0'), (others => '0'),
(others => '0'), (others => '0'), '0', '0', (others => '0'), zero32(AHB_FIFO_BITS),
(others => '0'), '0', (others => '0'), (others => '0'), '0', '0', (others => '0'),
(others => '0'), (others => '0'), (others => '0'), '0');
type amba_reg_type is record
m : amba_master_type;
atp_trans : ahb_to_pci_trans_type;
sync : ahb_sync_type;
s : amba_slave_type;
irq : irq_reg_type;
dma : dma_reg_type;
atpt_trans: apb_to_pci_trace_trans_type;
apb_sync : apb_sync_type;
apb_pt_stat : std_logic_vector(31 downto 0);
apb_pr_conf_0_pta_map : pci_bars_type; -- PCI to AHB mapping for each PCI bar (read only)
debug : std_logic_vector(31 downto 0);
debug_pr : std_logic_vector(31 downto 0);
debuga : std_logic_vector(31 downto 0);
end record;
constant REVISION : amba_version_type := 1;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_GRPCI2, 0, REVISION, irq),
1 => apb_iobar(paddr, pmask));
-- APB DEBUG
constant tbpconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_GRPCI2_TB, 0, REVISION, 0),
1 => apb_iobar(tbpaddr, tbpmask));
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_GRPCI2, 0, REVISION, 0),
4 => ahb_membar(haddr, '0', '0', hmask),
5 => ahb_iobar (ioaddr, HIOMASK),
others => zero32);
constant oeon : std_logic := conv_std_logic_vector(oepol,1)(0);
constant oeoff : std_logic := not conv_std_logic_vector(oepol,1)(0);
constant ones32 : std_logic_vector(31 downto 0) := (others => '1');
signal pr, prin : pci_reg_type;
signal pi, piin : pci_in_type; -- Registered PCI signals.
signal pcirstout : std_logic; -- PCI reset
signal pciasyncrst, pciasyncrst_comb : std_logic; -- PCI asynchronous reset
signal pcirst : std_logic_vector(2 downto 0); -- PCI reset
signal pciinten,pciinten_pad : std_logic_vector(3 downto 0);
signal pcisig : std_logic_vector(16 downto 0);
signal po, poin, po_keep : pci_reg_out_type; -- PCI output signals (to drive pads)
signal poin_keep : std_logic_vector(90 downto 0);
signal raden, rinaden, rinaden_tmp : std_logic_vector(31 downto 0);
signal pr_pta_trans_gated : pci_to_ahb_trans_type; -- PCI Target => AHB Master pending gated with pcirst
signal tm_fifoo_atp : pci_fifo_out_type; -- FIFO output data
signal ms_fifoo_atp : pci_fifo_out_type; -- FIFO output data
signal tm_fifoo_pta : pci_fifo_out_type;
signal ms_fifoo_pta : pci_fifo_out_type;
signal md_fifoo_dtp : pci_fifo_out_type; -- DMA FIFO output data
signal md_fifoo_ptd : pci_fifo_out_type;
signal pt_fifoo_ad : pci_fifo_out_type; -- PCI trace output data
signal pt_fifoo_sig : pci_fifo_out_type;
-- Scan test support
signal scanen : std_logic;
signal testin : std_logic_vector(TESTIN_WIDTH-1 downto 0);
signal scan_prin_t_atp_ctrl_en : std_logic;
signal scan_ar_m_acc_fifo_wen : std_logic;
signal scan_arin_m_acc_fifo_ren : std_logic;
signal scan_pr_t_pta_ctrl_en : std_logic;
signal scan_prin_m_acc_acc_sel_ahb_fifo_ren : std_logic;
signal scan_ar_s_atp_ctrl_en : std_logic;
signal scan_arin_s_pta_ctrl_en : std_logic;
signal scan_pr_m_acc_acc_sel_ahb_fifo_wen : std_logic;
signal scan_prin_m_acc_acc_sel_dma_fifo_ren : std_logic;
signal scan_ar_dma_dtp_ctrl_en : std_logic;
signal scan_arin_dma_ptd_ctrl_en : std_logic;
signal scan_pr_m_acc_acc_sel_dma_fifo_wen : std_logic;
signal scan_tb_ren : std_logic;
signal scan_pr_ptta_trans_enable : std_logic;
signal tb_addr : std_logic_vector(31 downto 0); -- Trace Buffer address
signal tb_ren : std_logic; -- Trace Buffer read enable
signal ar, arin : amba_reg_type;
signal dmao0, dmao1 : dma_ahb_out_type;
signal disabled_dmai : dma_ahb_in_type;
signal ahbmo_con : ahb_mst_out_type; -- Connect AHB-master to ahbmo
signal lpcim_rst, lpcit_rst, lpci_rst: std_ulogic;
signal lahbm_rst, lahbs_rst, lahb_rst: std_ulogic;
signal iotmdin: std_logic_vector(45 downto 0);
signal iotmdout: std_logic_vector(44 downto 0);
signal iotmact, iotmoe: std_ulogic;
attribute sync_set_reset of lpcim_rst : signal is "true";
attribute sync_set_reset of lpcit_rst : signal is "true";
attribute sync_set_reset of lpci_rst : signal is "true";
attribute sync_set_reset of pcirst : signal is "true";
--attribute sync_set_reset of rst : signal is "true";
attribute sync_set_reset of lahbm_rst : signal is "true";
attribute sync_set_reset of lahbs_rst : signal is "true";
attribute sync_set_reset of lahb_rst : signal is "true";
type bar_size_type is array (0 to 5) of integer range 0 to 31;
constant func0_bar_size : bar_size_type := (bar0, bar1, bar2, bar3, bar4, bar5);
constant func1_bar_size : bar_size_type := (mf1_bar0, mf1_bar1, mf1_bar2, mf1_bar3, mf1_bar4, mf1_bar5);
constant none_bar_size : bar_size_type := (0, 0, 0, 0, 0, 0);
type bar_size_vector_type is array (0 to 7) of bar_size_type;
constant bar_size : bar_size_vector_type := (func0_bar_size, func1_bar_size, none_bar_size, none_bar_size,
none_bar_size, none_bar_size, none_bar_size, none_bar_size);
constant func0_bar_type : std_logic_vector(15 downto 0) := conv_std_logic_vector(bartype,16);
constant func1_bar_type : std_logic_vector(15 downto 0) := conv_std_logic_vector(mf1_bartype,16);
constant func0_bar_prefetch : std_logic_vector(5 downto 0) := func0_bar_type(5 downto 0);
constant func1_bar_prefetch : std_logic_vector(5 downto 0) := func1_bar_type(5 downto 0);
type bar_prefetch_vector_type is array (0 to 7) of std_logic_vector(5 downto 0);
constant bar_prefetch : bar_prefetch_vector_type := (func0_bar_prefetch, func1_bar_prefetch, (others => '0'), (others => '0'),
(others => '0'), (others => '0'), (others => '0'), (others => '0'));
constant func0_bar_io : std_logic_vector(5 downto 0) := func0_bar_type(13 downto 8);
constant func1_bar_io : std_logic_vector(5 downto 0) := func1_bar_type(13 downto 8);
constant bar_io : bar_prefetch_vector_type := (func0_bar_io, func1_bar_io, (others => '0'), (others => '0'),
(others => '0'), (others => '0'), (others => '0'), (others => '0'));
type conf_int_vector_type is array (0 to 7) of integer;
constant deviceid_vector : conf_int_vector_type := (deviceid, mf1_deviceid, 0, 0, 0, 0, 0, 0);
constant classcode_vector : conf_int_vector_type := (classcode, mf1_classcode, 0, 0, 0, 0, 0, 0);
constant revisionid_vector : conf_int_vector_type := (revisionid, mf1_revisionid, 0, 0, 0, 0, 0, 0);
constant cap_pointer_vector : conf_int_vector_type := (cap_pointer, mf1_cap_pointer, 0, 0, 0, 0, 0, 0);
constant ext_cap_pointer_vector : conf_int_vector_type := (ext_cap_pointer, mf1_ext_cap_pointer, 0, 0, 0, 0, 0, 0);
constant extcfg_vector : conf_int_vector_type := (extcfg, mf1_extcfg, 0, 0, 0, 0, 0, 0);
type conf_vector16_vector_type is array (0 to 7) of std_logic_vector(15 downto 0);
constant masters_vector : conf_vector16_vector_type := (conv_std_logic_vector(masters, 16), conv_std_logic_vector(mf1_masters, 16),
x"0000", x"0000", x"0000", x"0000", x"0000", x"0000");
constant deviceirq_vector : conf_int_vector_type := (1*deviceirq, (1+1*multiint)*deviceirq, (1+2*multiint)*deviceirq, (1+3*multiint)*deviceirq,
1*deviceirq, (1+1*multiint)*deviceirq, (1+2*multiint)*deviceirq, (1+3*multiint)*deviceirq);
type default_bar_map_type is array (0 to 7) of pci_bars_type;
constant default_bar_map : default_bar_map_type := ((conv_std_logic_vector(bar0_map, 24)&x"00", conv_std_logic_vector(bar1_map, 24)&x"00",
conv_std_logic_vector(bar2_map, 24)&x"00", conv_std_logic_vector(bar3_map, 24)&x"00",
conv_std_logic_vector(bar4_map, 24)&x"00", conv_std_logic_vector(bar5_map, 24)&x"00"),
(conv_std_logic_vector(mf1_bar0_map, 24)&x"00", conv_std_logic_vector(mf1_bar1_map, 24)&x"00",
conv_std_logic_vector(mf1_bar2_map, 24)&x"00", conv_std_logic_vector(mf1_bar3_map, 24)&x"00",
conv_std_logic_vector(mf1_bar4_map, 24)&x"00", conv_std_logic_vector(mf1_bar5_map, 24)&x"00"),
pci_bars_none, pci_bars_none, pci_bars_none, pci_bars_none, pci_bars_none, pci_bars_none);
function blenmask_size(barminsize : in integer)
return integer is
variable res : integer;
begin
res := 16;
if barminsize < 16 then res := barminsize; end if;
return (res - 1);
end function;
function set_pta_addr(paddr : in std_logic_vector(31 downto 0);
pta_map : in pci_bars_type;
bar : in std_logic_vector(5 downto 0);
bar_mask: in pci_bars_type;
barminsize : in integer)
return std_logic_vector is
variable res : std_logic_vector(31 downto 0);
begin
res := paddr;
for i in 0 to 5 loop
if bar(i) = '1' then
res(31 downto barminsize) := (pta_map(i)(31 downto barminsize) and bar_mask(i)(31 downto barminsize)) or
(paddr(31 downto barminsize) and not bar_mask(i)(31 downto barminsize));
end if;
end loop;
return res;
end function;
function byte_twist(di : in std_logic_vector(31 downto 0); twist : in std_logic) return std_logic_vector is
variable do : std_logic_vector(31 downto 0);
begin
if twist = '1' then
for i in 0 to 3 loop
do(31-i*8 downto 24-i*8) := di(31-(3-i)*8 downto 24-(3-i)*8);
end loop;
else
do := di;
end if;
return do;
end function;
function set_size_from_cbe(cbe : in std_logic_vector(3 downto 0))
return std_logic_vector is
variable res : std_logic_vector(1 downto 0);
begin
case cbe is
when "0111" => res := "00";
when "1011" => res := "00";
when "1101" => res := "00";
when "1110" => res := "00";
when "0011" => res := "01";
when "1100" => res := "01";
when others => res := "10";
end case;
return res;
end function;
function set_addr_from_cbe(cbe : in std_logic_vector(3 downto 0);
twist: in std_logic)
return std_logic_vector is
variable res : std_logic_vector(1 downto 0);
begin
if twist = '1' then -- Little (PCI) to big (AHB) endian
case cbe is
when "0111" => res := "11";
when "1011" => res := "10";
when "1101" => res := "01";
when "1110" => res := "00";
when "0011" => res := "10";
when "1100" => res := "00";
when others => res := "00";
end case;
else -- Big (PCI) to big (AHB) endian
case cbe is
when "0111" => res := "00";
when "1011" => res := "01";
when "1101" => res := "10";
when "1110" => res := "11";
when "0011" => res := "00";
when "1100" => res := "10";
when others => res := "00";
end case;
end if;
return res;
end function;
function set_cbe_from_size_addr(size : in std_logic_vector(2 downto 0);
addr : in std_logic_vector(1 downto 0);
twist : in std_logic)
return std_logic_vector is
variable res : std_logic_vector(3 downto 0);
begin
if twist = '1' then
if size = "000" then -- byte
case addr is
when "11" => res := "0111";
when "10" => res := "1011";
when "01" => res := "1101";
when others => res := "1110";
end case;
elsif size = "001" then -- half word
case addr is
when "10" => res := "0011";
when others => res := "1100";
end case;
else
res := "0000";
end if;
else
if size = "000" then -- byte
case addr is
when "11" => res := "1110";
when "10" => res := "1101";
when "01" => res := "1011";
when others => res := "0111";
end case;
elsif size = "001" then -- half word
case addr is
when "10" => res := "1100";
when others => res := "0011";
end case;
else
res := "0000";
end if;
end if;
return res;
end function;
function set_atp_addr(haddr : in std_logic_vector(31 downto 0);
atp_map : in ahb_to_pci_map_type;
hmaster : in std_logic_vector(3 downto 0);
size : in integer)
return std_logic_vector is
variable res : std_logic_vector(31 downto 0);
variable i : integer;
begin
i := conv_integer(hmaster);
res := haddr;
if AADDR_WIDTH /= 4 then
res(31 downto size) := atp_map(i)(31 downto size);
end if;
return res;
end function;
function set_pci_conf_addr(addr : in std_logic_vector(31 downto 0);
cfg_bus : in std_logic_vector(23 downto 16))
return std_logic_vector is
variable res : std_logic_vector(31 downto 0);
variable i : integer range 0 to 21;
begin
res := (others => '0');
i := conv_integer(addr(15 downto 11));
if cfg_bus = zero32(23 downto 16) then -- Type 0 config
if i /= 0 then
res(10 + i) := '1';
end if;
res(10 downto 2) := addr(10 downto 2); -- Function number [10:8], Register address [7:2]
res(0) := '0'; -- Type
else -- Type 1 config
res(23 downto 16) := cfg_bus;
res(15 downto 2) := addr(15 downto 2); -- Function number [10:8], Register address [7:2]
res(0) := '1'; -- Type
end if;
return res;
end function;
function set_pci_io_addr(addr : in std_logic_vector(31 downto 0);
io_map : in std_logic_vector(31 downto 16))
return std_logic_vector is
variable res : std_logic_vector(31 downto 0);
begin
res := io_map & addr(15 downto 0);
return res;
end function;
function set_pci_io_byte_addr(addr : in std_logic_vector(1 downto 0);
size : in std_logic_vector(2 downto 0);
twist : in std_logic)
return std_logic_vector is
variable res : std_logic_vector(1 downto 0);
begin
if twist = '1' then
res := addr;
else
if size = "010" then
res := "00";
elsif size = "001" then
case addr is
when "00" => res := "10";
when others => res := "00";
end case;
else
case addr is
when "00" => res := "11";
when "01" => res := "10";
when "10" => res := "01";
when "11" => res := "00";
when others => res := "00";
end case;
end if;
end if;
return res;
end function;
begin
-- PHY =>
pciphy0 : grpci2_phy_wrapper
generic map(tech => memtech, oepol => oepol,
bypass => bypass, netlist => netlist,
scantest => scantest, iotest => iotest)
port map(
pciclk => pciclk,
pcii => pcii,
phyi => phyi,
pcio => pcio,
phyo => phyo,
iotmact => iotmact,
iotmoe => iotmoe,
iotdout => iotmdout,
iotdin => iotmdin
);
phyi.pciasyncrst <= pciasyncrst;
phyi.pcisoftrst <= sig_soft_rst;
phyi.pcirstout <= pcirstout;
phyi.pciinten <= pciinten_pad;
phyi.m_request <= sig_m_request;
phyi.m_mabort <= sig_m_mabort;
phyi.pr_m_fstate <= pr.m.fstate;
phyi.pr_m_cfifo <= pr.m.cfifo;
phyi.pv_m_cfifo <= prin.m.cfifo;
phyi.pr_m_addr <= pr.m.addr;
phyi.pr_m_cbe_data <= pr.m.cbe_data;
phyi.pr_m_cbe_cmd <= pr.m.cbe_cmd;
phyi.pr_m_first <= pr.m.first(1 downto 0);
phyi.pv_m_term <= prin.m.term(1 downto 0);
phyi.pr_m_ltimer <= pr.m.ltimer;
phyi.pr_m_burst <= pr.m.burst;
phyi.pr_m_abort <= pr.m.abort(0 downto 0);
phyi.pr_m_perren <= pr.m.perren(0 downto 0);
phyi.pr_m_done_fifo <= pr.m.done_fifo;
phyi.t_abort <= sig_t_abort;
phyi.t_ready <= sig_t_ready;
phyi.t_retry <= sig_t_retry;
phyi.pr_t_state <= pr.t.state;
phyi.pv_t_state <= prin.t.state;
phyi.pr_t_fstate <= pr.t.fstate;
phyi.pr_t_cfifo <= pr.t.cfifo;
phyi.pv_t_diswithout <= prin.t.diswithout;
phyi.pr_t_stoped <= pr.t.stoped;
phyi.pr_t_lcount <= pr.t.lcount;
phyi.pr_t_first_word <= pr.t.first_word;
phyi.pr_t_cur_acc_0_read <= pr.t.cur_acc(0).read;
phyi.pv_t_hold_write <= prin.t.hold_write;
phyi.pv_t_hold_reset <= prin.t.hold_reset;
phyi.pr_conf_comm_perren <= sig_pr_conf_comm_perren;
phyi.pr_conf_comm_serren <= sig_pr_conf_comm_serren; -- SERR# only asserted for address parity error
phyi.testen <= ahbsi.testen when scantest=1 else '0';
phyi.testoen <= ahbsi.testoen;
phyi.testrst <= ahbsi.testrst;
pcirst <= (others => phyo.pcirsto(0));
pi <= phyo.pio;
po <= phyo.poo;
-- PHY <=
disabled_dmai <= ('0', '0', (others => '0'), (others => '0'), (others => '0'), '0', '0');
scanen <= (ahbsi.testen and ahbsi.scanen) when (scantest = 1) else '0';
testin <= ahbsi.testen & "0" & ahbsi.testin(TESTIN_WIDTH-3 downto 0);
pciasyncrst <= ahbsi.testrst when (scantest = 1) and (ahbsi.testen = '1') else pcii.rst;
pciasyncrst_comb <= pcii.rst; -- Version used in comb logic, don't mux in testrst
hostrst2 : if hostrst = 2 generate
pcirstout <= rst and not ar.atp_trans.rst(2);
end generate;
hostrst1 : if hostrst = 1 generate
pcirstout <= rst and not ar.atp_trans.rst(2) when pcii.host = '0' else '1';
end generate;
hostrst0 : if hostrst = 0 generate
pcirstout <= '1';
end generate;
-- Propagate PCI reset to AMBA for peripheral devices
ptarst <= pcii.rst when pcii.host = '1' and hostrst /= 2 else '1';
-- PCI trace signal
pcisig <= pi.cbe &
pi.frame & pi.irdy & pi.trdy & pi.stop &
pi.devsel & pi.par & pi.perr & pi.serr &
pi.idsel & pr.po.req & pi.gnt & pi.lock &
pi.rst; -- & "000";
pcomb : process(pr, pi, pcirst(0), pcii, ar.atp_trans, tm_fifoo_atp, ms_fifoo_atp, md_fifoo_dtp, pcirstout, pciinten, pcisig, ar.atpt_trans,
phyo, pciasyncrst_comb, lpcim_rst, lpcit_rst, lpci_rst, iotmact)
variable pv : pci_reg_type;
variable atp_trans : ahb_to_pci_trans_type;
variable pci : pci_in_type;
variable t_hit : std_logic; -- Target bar address match
variable t_chit : std_logic; -- Target configuration space hit
variable t_bar : std_logic_vector(5 downto 0); -- PCI bar with hit
variable t_func : integer range 0 to multifunc;
variable t_ready : std_logic; -- Backend ready to send/receive data
variable t_abort : std_logic; -- Stop PCI access
variable t_retry : std_logic; -- Stop PCI access
variable t_index : integer range 0 to FIFO_COUNT-1;-- FIFO index
variable t_cad : std_logic_vector(31 downto 0); -- Data from PCI Configuration Space Header
variable conf_func : integer range 0 to 7;
variable all_func_serren : std_logic;
variable t_acc_type : std_logic_vector(1 downto 0);
variable t_acc_impcfgreg: std_logic;
variable t_acc_burst: std_logic;
variable t_acc_read : std_logic;
variable tm_acc_pending : std_logic;
variable tm_acc_cancel : std_logic;
variable tm_acc_done : std_logic;
variable tm_fifo_pending : std_logic_vector(FIFO_COUNT-1 downto 0);
variable tm_fifo_empty : std_logic_vector(FIFO_COUNT-1 downto 0);
variable tm_fifo : pci_g_fifo_trans_vector_type;
variable accbufindex : integer range 0 to 3;
-- PCI master
variable m_request : std_logic;
variable m_ready : std_logic;
variable m_mabort : std_logic; -- Master abort
variable m_tabort : std_logic; -- Target abort
variable m_index : integer range 0 to FIFO_COUNT-1;-- FIFO index
variable m_func : integer range 0 to multifunc;
variable acc : pci_master_acc_type;
variable accdone : std_logic; -- Renamed to be synthesized with XST
variable acc_cancel : std_logic;
variable acc_switch : std_logic;
variable fifo : pci_g_fifo_trans_vector_type;
variable fifo_pending : std_logic_vector(FIFO_COUNT-1 downto 0);
variable fifo_empty : std_logic_vector(FIFO_COUNT-1 downto 0);
variable fifo_nindex : integer range 0 to FIFO_COUNT-1;-- FIFO index
variable msd_acc : pci_g_acc_trans_multi_type;
variable ms_acc_pending : std_logic;
variable ms_acc_done : std_logic;
variable ms_acc_cancel : std_logic;
variable ms_fifo_pending : std_logic_vector(FIFO_COUNT-1 downto 0);
variable ms_fifo_empty : std_logic_vector(FIFO_COUNT-1 downto 0);
variable ms_fifo : pci_g_fifo_trans_vector_type;
variable md_acc_pending : std_logic;
variable md_acc_done : std_logic;
variable md_acc_cancel : std_logic;
variable md_fifo_pending : std_logic_vector(FIFO_COUNT-1 downto 0);
variable md_fifo_empty : std_logic_vector(FIFO_COUNT-1 downto 0);
variable md_fifo : pci_g_fifo_trans_vector_type;
-- PCI trace
variable pt_start : std_logic;
variable pt_stop : std_logic;
variable atpt_trans : apb_to_pci_trace_trans_type;
variable pt_setup : apb_to_pci_trace_trans_type;
constant z : std_logic_vector(48 downto 0) := (others => '0');
-- Soft reset
variable pci_target_rst : std_logic;
variable pci_master_rst : std_logic;
variable pci_hard_rst : std_logic;
begin
-- --------------------------------------------------------------------------------
-- Global defaults
-- --------------------------------------------------------------------------------
-- Defaults
pv := pr;
pv.pta_trans.ca_host := pcii.host;
pv.pci66(0) := pcii.pci66; pv.pci66(1) := pr.pci66(0);
-- FIFO and PCI<=>AHB sync
pv.sync(1) := ar.atp_trans; pv.sync(2) := pr.sync(1);
if nsync = 0 then atp_trans := ar.atp_trans;
else atp_trans := pr.sync(nsync); end if;
-- PCI soft reset
pv.pta_trans.rst_ack(0) := atp_trans.rst(0);
pv.pta_trans.rst_ack(1) := atp_trans.rst(1);
pci_target_rst := not pr.pta_trans.rst_ack(0) and (pr.pta_trans.rst_ack(0) xor atp_trans.rst(0));
pci_master_rst := not pr.pta_trans.rst_ack(1) and (pr.pta_trans.rst_ack(1) xor atp_trans.rst(1));
pci_hard_rst := atp_trans.rst(2);
pci := phyo.pciv;
if (pr.po.perr = '0' -- Parity Error detected
and (pr.m.perren /= "00")) then -- During master read
pv.conf(pr.m.acc(pr.m.acc_sel).func).stat.dpe := '1';
end if;
if (pr.po.perr = '0' -- Parity Error detected
and ((pr.t.state = pt_s_data or pr.t.state = pt_turn_ar) and pr.t.cur_acc(0).read = '0')) -- Write to target
or (pr.t.addr_perr = '1') then -- Parity Error in Address phase
pv.conf(pr.t.cur_acc(0).func).stat.dpe := '1';
end if;
-- Signaled System Error
for j in 0 to multifunc loop
if pr.conf(j).comm.perren = '1' and pr.conf(j).comm.serren = '1' and pr.po.serren = oeon then
pv.conf(j).stat.sse := '1';
end if;
end loop;
-- SERR to AHB
if atp_trans.pa_serr_rst = '1' then
pv.pta_trans.pa_serr := '1';
elsif pi.serr = '0' then
pv.pta_trans.pa_serr := '0';
end if;
-- --------------------------------------------------------------------------------
-- PCI master defaults
-- --------------------------------------------------------------------------------
-- Default
m_request := '0';
m_ready := '0';
m_ready := '1';
pv.m.fifo_switch := '0';
pv.m.acc(0).fifo_ren := '0'; -- read enable [AHB]
pv.m.acc(0).fifo_wen := '0'; -- write enable [AHB]
pv.m.acc(1).fifo_ren := '0'; -- read enable [DMA]
pv.m.acc(1).fifo_wen := '0'; -- write enable [DMA]
pv.m.fifo_wdata := byte_twist(pi.ad, pr.m.twist);
pv.m.framedel := pr.po.frame;
ms_acc_pending := atp_trans.msd_acc(0).pending xor pr.pta_trans.msd_acc_ack(0);
ms_acc_done := atp_trans.msd_acc_done_ack(0) xor pr.pta_trans.msd_acc_done(0).done;
ms_acc_cancel := atp_trans.msd_acc_cancel(0) xor pr.pta_trans.msd_acc_cancel_ack(0)(0);
-- Stop_ack also needs to be delayed when pending is delayed
pv.pta_trans.msd_acc_cancel_ack(0)(1) := pr.pta_trans.msd_acc_cancel_ack(0)(0);
pv.pta_trans.msd_acc_cancel_ack(0)(2) := pr.pta_trans.msd_acc_cancel_ack(0)(1);
for i in 0 to FIFO_COUNT-1 loop
ms_fifo_pending(i) := atp_trans.msd_fifo(0)(i).pending(RAM_LATENCY) xor pr.pta_trans.msd_fifo_ack(0)(i);
ms_fifo_empty(i) := not (pr.pta_trans.msd_fifo(0)(i).pending(0) xor atp_trans.msd_fifo_ack(0)(i));
-- To set pending when data is stored in fifo, with this stop_ack also needs to be delayed
pv.pta_trans.msd_fifo(0)(i).pending(1) := pr.pta_trans.msd_fifo(0)(i).pending(0);
pv.pta_trans.msd_fifo(0)(i).pending(2) := pr.pta_trans.msd_fifo(0)(i).pending(1);
end loop;
ms_fifo := ar.atp_trans.msd_fifo(0);
msd_acc(0) := ar.atp_trans.msd_acc(0);
md_acc_pending := atp_trans.msd_acc(1).pending xor pr.pta_trans.msd_acc_ack(1);
md_acc_done := atp_trans.msd_acc_done_ack(1) xor pr.pta_trans.msd_acc_done(1).done;
md_acc_cancel := atp_trans.msd_acc_cancel(1) xor pr.pta_trans.msd_acc_cancel_ack(1)(0);
-- Stop_ack also needs to be delayed when pending is delayed
pv.pta_trans.msd_acc_cancel_ack(1)(1) := pr.pta_trans.msd_acc_cancel_ack(1)(0);
pv.pta_trans.msd_acc_cancel_ack(1)(2) := pr.pta_trans.msd_acc_cancel_ack(1)(1);
for i in 0 to FIFO_COUNT-1 loop
md_fifo_pending(i) := atp_trans.msd_fifo(1)(i).pending(RAM_LATENCY) xor pr.pta_trans.msd_fifo_ack(1)(i);
md_fifo_empty(i) := not (pr.pta_trans.msd_fifo(1)(i).pending(0) xor atp_trans.msd_fifo_ack(1)(i));
-- To set pending when data is stored in fifo, with this stop_ack also needs to be delayed
pv.pta_trans.msd_fifo(1)(i).pending(1) := pr.pta_trans.msd_fifo(1)(i).pending(0);
pv.pta_trans.msd_fifo(1)(i).pending(2) := pr.pta_trans.msd_fifo(1)(i).pending(1);
end loop;
md_fifo := ar.atp_trans.msd_fifo(1);
msd_acc(1) := ar.atp_trans.msd_acc(1);
-- PCI master function
m_func := pr.m.acc(pr.m.acc_sel).func;
-- --------------------------------------------------------------------------------
-- PCI master core
-- --------------------------------------------------------------------------------
if master /= 0 or dma /= 0 then -- PCI master enabled
-- First
if pr.m.state = pm_idle or pr.m.state = pm_turn_ar or pr.m.state = pm_dr_bus then
pv.m.first(0) := '1';
else
pv.m.first(0) := '0';
end if;
pv.m.first(1) := pr.m.first(0);
-- Master Data Parity Error
if pr.m.state = pm_m_data then
if pr.m.fstate = pmf_read then
pv.m.perren(0) := '1';
elsif pr.m.fstate = pmf_fifo then
pv.m.detectperr(0) := '1';
end if;
else
pv.m.perren(0) := '0';
pv.m.detectperr(0) := '0';
end if;
pv.m.perren(1) := pr.m.perren(0);
pv.m.detectperr(1) := pr.m.detectperr(0);
if pr.conf(m_func).comm.perren = '1' and -- Parity error response bit[6] = 1
((pr.m.perren /= "00" and pr.po.perr = '0') -- Parity error is signaled by master on read
or (pr.m.detectperr(1) = '1' and pci.perr = '0')) then-- Parity error is signaled by target on write
pv.conf(m_func).stat.mdpe := '1';
pv.m.acc(pr.m.acc_sel).status(0) := '1';
end if;
-- PCI master latency timer
if (pr.m.framedel and not pr.po.frame) = '1' then
pv.m.ltimer := pr.conf(m_func).ltimer;
elsif pr.m.ltimer /= x"00" and pr.po.frame = '0' then
pv.m.ltimer := pr.m.ltimer - 1;
end if;
-- Devsel time out counter (and master abort signaling)
if pci.devsel = '0' then pv.m.devsel_asserted := '1'; end if;
if (pr.m.framedel and not pr.po.frame) = '1' then
pv.m.devsel_tout := "100";
pv.m.devsel_asserted := '0';
elsif pr.m.devsel_asserted = '1' then
pv.m.devsel_tout := "100";
elsif pr.m.devsel_tout /= "000" then
pv.m.devsel_tout := pr.m.devsel_tout - 1;
end if;
if (pr.m.devsel_tout = "000" and pr.m.devsel_asserted = '0') and pi.devsel = '1' and pr.m.state = pm_m_data then m_mabort := '1'; pv.conf(m_func).stat.rma := '1'; else m_mabort := '0'; end if; -- Master abort -- delayed mabort one cycle (to reduce pci.devsel timing path)
if pi.devsel = '1' and pi.stop = '0' and pr.m.state = pm_s_tar then m_tabort := '1'; pv.conf(m_func).stat.rta := '1'; else m_tabort := '0'; end if; -- Target abort
if (pr.m.state = pm_m_data and m_mabort = '1') or (pr.m.state = pm_s_tar and m_tabort = '1') then
pv.m.abort(0) := '1';
pv.m.abort(1) := m_tabort;
elsif pr.m.state = pm_s_tar or pr.m.state = pm_idle or pr.m.state = pm_dr_bus then
pv.m.abort := (others => '0');
end if;
if pr.m.abort(0) = '1' then pv.m.abort(0) := '0'; end if;
-- Access acknowledge and arbitration [AHB/DMA]
for i in 0 to 1*dma loop
if ((ms_acc_pending = '1' and i = acc_sel_ahb) or (md_acc_pending = '1' and i = acc_sel_dma)) and pr.m.acc(i).pending = '0' then
pv.pta_trans.msd_acc_ack(i) := atp_trans.msd_acc(i).pending;
pv.m.acc(i).pending := '1';
pv.m.acc(i).active := (others => '0');
pv.m.acc(i).done := (others => '0');
pv.m.acc(i).status := (others => '0');
pv.m.acc(i).first := '1';
pv.m.acc(i).addr := msd_acc(i).addr(31 downto 2) & "00";
pv.m.acc(i).func := conv_integer(msd_acc(i).func);
pv.m.acc(i).cmd := msd_acc(i).acctype;
pv.m.acc(i).mode := msd_acc(i).accmode;
pv.m.acc(i).fifo_index := msd_acc(i).index;
if msd_acc(i).acctype(0) = '1' then
pv.m.acc(i).length := (others => '0');
else
pv.m.acc(i).length := msd_acc(i).length;
end if;
if msd_acc(i).acctype = CONF_READ or msd_acc(i).acctype = CONF_WRITE then -- Config
if i = acc_sel_ahb then pv.m.acc(i).endianess := '1'; -- Endianess is not set for AHB slave
else pv.m.acc(i).endianess := msd_acc(i).endianess; end if; -- Endianess is set for DMA
pv.m.acc(i).addr := msd_acc(i).addr; -- PCI CONF address set in AHB slave
pv.m.acc(i).cbe := set_cbe_from_size_addr(msd_acc(i).size, msd_acc(i).offset(1 downto 0), '1'); -- Set CBE depending on AHB size and address
elsif msd_acc(i).acctype = IO_READ or msd_acc(i).acctype = IO_WRITE then -- IO
if i = acc_sel_ahb then pv.m.acc(i).endianess := pr.pta_trans.ca_twist; -- Endianess is not set for AHB slave
else pv.m.acc(i).endianess := msd_acc(i).endianess; end if; -- Endianess is set for DMA
pv.m.acc(i).addr(1 downto 0) := set_pci_io_byte_addr(msd_acc(i).offset(1 downto 0), msd_acc(i).size, pr.pta_trans.ca_twist); -- PCI IO used byte address
pv.m.acc(i).cbe := set_cbe_from_size_addr(msd_acc(i).size, msd_acc(i).offset(1 downto 0), pr.pta_trans.ca_twist); -- Set CBE depending on AHB size and address
else -- Mem
if i = acc_sel_ahb then pv.m.acc(i).endianess := pr.pta_trans.ca_twist; -- Endianess is not set for AHB slave
else pv.m.acc(i).endianess := msd_acc(i).endianess; end if; -- Endianess is set for DMA
pv.m.acc(i).cbe := set_cbe_from_size_addr(msd_acc(i).size, msd_acc(i).offset(1 downto 0), pr.pta_trans.ca_twist); -- Set CBE depending on AHB size and address
end if;
end if;
if pr.m.acc(i).pending = '1' and pr.m.acc(i).active(1) = '0' and pr.m.acc(i).done(0) = '1' and pr.m.acc(i).cmd(0) = '1' then -- Status pending
if pr.m.acc(i).done(2 downto 1) = "10" then
if (i = acc_sel_ahb and ms_fifo_pending(pr.m.acc(i).fifo_index) = '1') or (i = acc_sel_dma and md_fifo_pending(pr.m.acc(i).fifo_index) = '1') then
if pr.m.acc(i).fifo_index /= FIFO_COUNT-1 then pv.m.acc(i).fifo_index := pr.m.acc(i).fifo_index + 1;
else pv.m.acc(i).fifo_index := 0; end if;
pv.pta_trans.msd_fifo_ack(i)(pr.m.acc(i).fifo_index) := not pv.pta_trans.msd_fifo_ack(i)(pr.m.acc(i).fifo_index);
if (i = acc_sel_ahb and ms_fifo(pr.m.acc(i).fifo_index).lastf = '1') or (i = acc_sel_dma and md_fifo(pr.m.acc(i).fifo_index).lastf = '1') then
pv.m.acc(i).done(1) := '1';
end if;
end if;
elsif ((ms_acc_done = '0' and i = acc_sel_ahb) or (md_acc_done = '0' and i = acc_sel_dma)) then
pv.pta_trans.msd_acc_done(i).done := not pr.pta_trans.msd_acc_done(i).done;
pv.pta_trans.msd_acc_done(i).status(2 downto 0) := pr.m.acc(i).status;
if pr.m.acc(i).cmd = CONF_WRITE then pv.pta_trans.msd_acc_done(i).status(3) := '1'; -- Status(3) indicates CONF_WRITE
else pv.pta_trans.msd_acc_done(i).status(3) := '0'; end if;
pv.pta_trans.msd_acc_done(i).count := pr.m.acc(i).length;
pv.m.acc(i).pending := '0';
end if;
end if;
-- Access canceled
if pr.m.acc(i).pending = '1' and pr.m.acc(i).active = "10" and pr.m.acc(i).cmd(0) = '0' then
if ((ms_acc_cancel = '1' and i = acc_sel_ahb) or (md_acc_cancel = '1' and i = acc_sel_dma)) then
pv.m.acc(i).done(0) := '1';
pv.m.acc(i).active(1) := '0';
end if;
end if;
if pr.m.acc(i).pending = '1' and pr.m.acc(i).active(1) = '0' and pr.m.acc(i).done(0) = '1' and pr.m.acc(i).cmd(0) = '0' then -- Status pending
if pr.m.acc(i).done(1 downto 0) = "01" then
if ((ms_acc_cancel = '1' and i = acc_sel_ahb) or (md_acc_cancel = '1' and i = acc_sel_dma)) then
pv.m.acc(pr.m.acc_sel).done(1) := '1';
for j in 0 to FIFO_COUNT-1 loop
if (i = acc_sel_ahb and ms_fifo_empty(j) = '0') or (i = acc_sel_dma and md_fifo_empty(j) = '0') then
pv.pta_trans.msd_fifo(i)(j).pending(0) := not pr.pta_trans.msd_fifo(i)(j).pending(0);
else
pv.pta_trans.msd_fifo(i)(j).pending(0) := pr.pta_trans.msd_fifo(i)(j).pending(0);
end if;
end loop;
end if;
else
pv.pta_trans.msd_acc_cancel_ack(i)(0) := atp_trans.msd_acc_cancel(i);
pv.m.acc(i).pending := '0';
end if;
end if;
end loop;
-- control access switching
if atp_trans.mstswdis = '0' then
if (pr.m.acc_sel = acc_sel_dma and pr.m.acc(0).pending = '1' and pr.m.acc(0).done(0) = '0'
and ((pr.m.acc(0).cmd(0) and ms_fifo_pending(pr.m.acc(0).fifo_index))
or (not pr.m.acc(0).cmd(0) and ms_fifo_empty(pr.m.acc(0).fifo_index))) = '1')
or
(pr.m.acc_sel = acc_sel_ahb and pr.m.acc(1).pending = '1' and pr.m.acc(1).done(0) = '0'
and ((pr.m.acc(1).cmd(0) and md_fifo_pending(pr.m.acc(1).fifo_index))
or (not pr.m.acc(1).cmd(0) and md_fifo_empty(pr.m.acc(1).fifo_index))) = '1')
then
if pr.m.acc_cnt = MST_ACC_CNT then
pv.m.acc_switch := '1';
end if;
end if;
else
pv.m.acc_switch := '0';
end if;
acc_switch := pv.m.acc_switch;
if ((pr.m.acc(0).pending = '1' and pr.m.acc(0).done(0) = '0'
and ms_acc_cancel = '0' and pr.m.acc(1).active(0) = '0'
and ((pr.m.acc(0).cmd(0) and ms_fifo_pending(pr.m.acc(0).fifo_index))
or (not pr.m.acc(0).cmd(0) and ms_fifo_empty(pr.m.acc(0).fifo_index))) = '1')
and not (pr.m.acc_switch = '1' and pr.m.acc_sel = acc_sel_ahb))
or pr.m.acc(0).active(0) = '1' then
acc := pr.m.acc(0);
accdone := ms_acc_done;
acc_cancel := ms_acc_cancel;
pv.m.acc_sel := acc_sel_ahb;
fifo_pending := ms_fifo_pending;
fifo_empty := ms_fifo_empty;
fifo := ms_fifo;
if pr.m.acc_sel = acc_sel_dma then
pv.m.acc_cnt := 0;
pv.m.acc_switch := '0';
end if;
elsif (pr.m.acc(1).pending = '1' and pr.m.acc(1).done(0) = '0'
and md_acc_cancel = '0' and pr.m.acc(0).active(0) = '0'
and ((pr.m.acc(1).cmd(0) and md_fifo_pending(pr.m.acc(1).fifo_index))
or (not pr.m.acc(1).cmd(0) and md_fifo_empty(pr.m.acc(1).fifo_index))) = '1')
or pr.m.acc(1).active(0) = '1' then
acc := pr.m.acc(1);
accdone := md_acc_done;
acc_cancel := md_acc_cancel;
pv.m.acc_sel := acc_sel_dma;
fifo_pending := md_fifo_pending;
fifo_empty := md_fifo_empty;
fifo := md_fifo;
if pr.m.acc_sel = acc_sel_ahb then
pv.m.acc_cnt := 0;
pv.m.acc_switch := '0';
end if;
else
acc := pci_master_acc_none;
accdone := '0';
acc_cancel := '0';
pv.m.acc_sel := acc_sel_ahb;
fifo_pending := (others => '0');
fifo_empty := (others => '0');
fifo := ms_fifo;
pv.m.acc_cnt := 0;
pv.m.acc_switch := '0';
end if;
if acc.fifo_index /= FIFO_COUNT-1 then fifo_nindex := (acc.fifo_index + 1);
else fifo_nindex := 0; end if;
-- FIFO state machine
case pr.m.fstate is
when pmf_idle =>
pv.m.waitonstop := '0';
pv.m.done := '0';
pv.m.done_fifo := '0';
pv.m.done_trans := '0';
pv.m.term := (others => '0');
pv.m.preload := '0';
pv.m.preload_count := (others => '0');
pv.m.afull := '0';
pv.m.afullcnt := (others => '0');
if acc.pending = '1' then
pv.m.addr := acc.addr;
pv.m.twist := acc.endianess;
pv.m.cbe_cmd := acc.cmd;
pv.m.cbe_data := acc.cbe;
pv.m.burst := acc.mode(0);
pv.m.acc_cnt := 0;
if acc.cmd(0) = '1' then -- Write access
pv.m.fstate := pmf_fifo;
pv.m.fifo_addr := conv_std_logic_vector(acc.fifo_index, log2(FIFO_COUNT)) & fifo(acc.fifo_index).start; -- Set fifo start address
else -- Read access
pv.m.fstate := pmf_read;
end if;
pv.m.acc(pv.m.acc_sel).active := "11";
end if;
when pmf_fifo =>
pv.m.acc(pr.m.acc_sel).fifo_ren := fifo_pending(acc.fifo_index);
if pr.m.term = "00" and pr.m.last(0) = '0' and pr.m.done = '0' and (pr.m.cfifo(0).valid = '1' or pr.m.hold(0) = '1')
and m_mabort = '0' and pr.m.abort(0) = '0' then -- request bus if not: latency timer count out; last data phase; transfer done
m_request := '1';
end if;
if (fifo_pending(acc.fifo_index) = '1') and pr.m.done = '0' then -- preload data
pv.m.preload := '1';
pv.m.hold_fifo := '0';
end if;
if ((pi.trdy or pi.irdy) = '0' and (pr.m.state = pm_m_data or pr.m.state = pm_turn_ar or pr.m.state = pm_s_tar)) or pr.m.preload = '1' or (pr.m.abort(0)) = '1' then
if ((pi.trdy or pi.irdy) = '0' and (pr.m.state = pm_m_data or pr.m.state = pm_turn_ar or pr.m.state = pm_s_tar)) or (pr.m.abort(0)) = '1' then
pv.m.cfifo(0) := pr.m.cfifo(1); pv.m.cfifo(1) := pr.m.cfifo(2); -- Preload master core fifo
elsif pr.m.preload = '1' then
if pr.m.cfifo(0).valid = '0' then
pv.m.cfifo(0) := pr.m.cfifo(1); pv.m.cfifo(1) := pr.m.cfifo(2); -- Preload master core fifo
elsif pr.m.cfifo(0).valid = '1' and pr.m.cfifo(1).valid = '0' then
pv.m.cfifo(1) := pr.m.cfifo(2); -- Preload master core fifo
end if;
end if;
if pr.m.acc(0).active(0) = '1' then
pv.m.cfifo(2).data := byte_twist(ms_fifoo_atp.data, acc.endianess); -- shifting in data from backend fifo
elsif pr.m.acc(1).active(0) = '1' then
pv.m.cfifo(2).data := byte_twist(md_fifoo_dtp.data, acc.endianess); -- shifting in data from DMA fifo
end if;
if pr.m.done_fifo = '0' and fifo_pending(acc.fifo_index) = '1' then
if pr.m.fifo_addr(FIFO_DEPTH-1 downto 0) = fifo(acc.fifo_index).stop then -- Mark last word
if pr.m.acc_cnt /= MST_ACC_CNT then pv.m.acc_cnt := pr.m.acc_cnt + 1; end if; -- Switch DAM/AHB-slave after MST_ACC_CNT FIFOs
pv.m.fifo_switch := '1';
pv.m.acc(pr.m.acc_sel).fifo_index := fifo_nindex;
pv.pta_trans.msd_fifo_ack(pr.m.acc_sel)(acc.fifo_index) := fifo(acc.fifo_index).pending(RAM_LATENCY); -- Ack the fifo (done using this data)
pv.m.fifo_addr := conv_std_logic_vector(fifo_nindex, log2(FIFO_COUNT)) & zero32(FIFO_DEPTH-1 downto 0); -- New fifo address (should be ok with [index & zero] or & fifo(fifo_nindex).start)
if fifo_pending(fifo_nindex) = '0' or acc_switch = '1' then -- If no fifo pending => idle
pv.m.cfifo(2).last := '1';
pv.m.done_fifo := '1';
else
pv.m.cfifo(2).hold := '0';
pv.m.cfifo(2).last := '0';
end if;
if fifo(acc.fifo_index).lastf = '1' then -- Last fifo, transfer is done
pv.m.cfifo(2).last := '1';
pv.m.done_fifo := '1';
pv.m.done_trans := '1';
end if;
else
pv.m.cfifo(2).hold := '0';
pv.m.cfifo(2).last := '0';
if pr.m.done_fifo = '0' and fifo_pending(acc.fifo_index) = '1' then
pv.m.fifo_addr(FIFO_DEPTH-1 downto 0) := pr.m.fifo_addr(FIFO_DEPTH-1 downto 0) + 1; -- inc backend fifo address
end if;
end if;
else
pv.m.cfifo(2).hold := '0';
pv.m.cfifo(2).last := '0';
end if;
pv.m.cfifo(2).stlast := '0';
if fifo_pending(acc.fifo_index) = '1' and pr.m.done_fifo = '0' then -- Adding valid data to CFIFO
pv.m.cfifo(2).valid := '1';
else
pv.m.cfifo(2).valid := '0';
pv.m.cfifo(2).last := '0';
pv.m.cfifo(2).stlast := '0';
pv.m.cfifo(2).hold := '0';
end if;
end if;
if (pv.m.cfifo(0).valid = '1' and pv.m.cfifo(1).valid = '1' and pv.m.cfifo(2).valid = '1')
or (pv.m.cfifo(0).valid = '1' and pr.m.done_fifo = '1' and not (pv.m.cfifo(1).valid = '0' and pv.m.cfifo(2).valid = '1')) then
pv.m.preload := '0';
if pr.m.cfifo(0).hold = '1' and pv.m.cfifo(1).valid = '1' then pv.m.cfifo(0).hold := '0'; end if;
if pr.m.cfifo(1).hold = '1' and pv.m.cfifo(2).valid = '1' then pv.m.cfifo(1).hold := '0'; end if;
end if;
if pr.m.abort(0) = '1' then -- Empty core FIFO on master/target abort
for i in 0 to 2 loop
pv.m.cfifo(i).valid := '0';
end loop;
end if;
if ((pi.trdy or pi.irdy) = '0' and (pr.m.state = pm_m_data or pr.m.state = pm_turn_ar or pr.m.state = pm_s_tar)) or (pr.m.abort(0)) = '1' then
pv.m.addr := pr.m.addr + 4;
if acc.mode(1) = '1' and pr.m.abort(0) = '0' then -- Use acc.length
pv.m.acc(pr.m.acc_sel).length := pr.m.acc(pr.m.acc_sel).length + 1;
end if;
if pr.m.last(1) = '1' or pr.m.abort(0) = '1' then pv.m.done := '1'; end if; -- Last data phase is done => transfer done
-- Signal ERROR to AHB
if pr.m.abort(0) = '1' then
pv.m.acc(pr.m.acc_sel).done(2) := '1'; -- Error
pv.m.acc(pr.m.acc_sel).status(2 downto 1) := (not pr.m.abort(1) or m_mabort) & (pr.m.abort(1) or m_tabort); -- Error type: Master abort, Target abort, (PAR error)
end if;
end if;
if (pr.m.state = pm_s_tar or pr.m.state = pm_turn_ar) then
pv.m.term := (others => '0'); m_request := '0';
end if;
if pr.m.done = '1' then
pv.m.fstate := pmf_idle;
pv.m.acc(pr.m.acc_sel).active(0) := '0';
pv.m.acc(pr.m.acc_sel).addr := pr.m.addr;
if pr.m.done_trans = '1' or acc.done(2) = '1' then
pv.m.acc(pr.m.acc_sel).active(1) := '0';
pv.m.acc(pr.m.acc_sel).done(0) := '1';
if pr.m.done_trans = '1' then pv.m.acc(pr.m.acc_sel).done(1) := '1'; end if;
if accdone = '0' and pr.m.done_trans = '1' then
pv.pta_trans.msd_acc_done(pr.m.acc_sel).done := not pr.pta_trans.msd_acc_done(pr.m.acc_sel).done;
pv.pta_trans.msd_acc_done(pr.m.acc_sel).status(2 downto 0) := pv.m.acc(pr.m.acc_sel).status; -- use pv.. (par error detection)
if pr.m.acc(pr.m.acc_sel).cmd = CONF_WRITE then pv.pta_trans.msd_acc_done(pr.m.acc_sel).status(3) := '1'; -- Status(3) indicates CONF_WRITE
else pv.pta_trans.msd_acc_done(pr.m.acc_sel).status(3) := '0'; end if;
pv.pta_trans.msd_acc_done(pr.m.acc_sel).count := pr.m.acc(pr.m.acc_sel).length;
pv.m.acc(pr.m.acc_sel).pending := '0';
end if;
end if;
end if;
if pi.stop = '0' and pr.m.state /= pm_idle then m_request := '0'; end if; -- Second deasserted req cycle
when pmf_read =>
if pr.m.term(0) = '0' and m_mabort = '0' and pr.m.abort(0) = '0' and (pi.stop = '1' or pr.m.first(0) = '1') and pr.m.waitonstop = '0' then -- request bus if not: latency timer count out; no empty fifo to fill
m_request := '1'; -- request should be deasserted earlier
end if;
if pr.m.burst = '0' then -- Single access, only one data phase
if pr.po.frame = '0' then
pv.m.term(0) := '1';
elsif (pi.trdy and not pi.stop) = '1' then -- retry
pv.m.term := (others => '0');
end if;
end if;
if (pi.irdy or pi.trdy) = '0' and (pr.m.state = pm_m_data or pr.m.state = pm_s_tar or pr.m.state = pm_turn_ar)then
pv.m.addr := pr.m.addr + 4;
if acc.mode(1) = '1' then -- Use acc.length
pv.m.acc(pr.m.acc_sel).length := pr.m.acc(pr.m.acc_sel).length - 1;
end if;
if pr.m.addr(AHB_FIFO_BITS) = ones32(FIFO_DEPTH-1 downto 0) or pr.m.burst = '0' or (acc.mode(1) = '1' and acc.length = x"0000") then
if pr.m.acc_cnt /= MST_ACC_CNT then pv.m.acc_cnt := pr.m.acc_cnt + 1; end if; -- Switch DMA/AHB-slave after MST_ACC_CNT FIFOs
pv.m.fifo_switch := '1';
pv.m.acc(pr.m.acc_sel).fifo_index := fifo_nindex;
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).pending(0) := not pr.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).pending(0);
pv.m.acc(pr.m.acc_sel).first := '0';
if acc.first = '1' then
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).firstf := '1';
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).start := acc.addr(AHB_FIFO_BITS);
else
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).firstf := '0';
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).start := (others => '0');
end if;
if (acc.mode(1) = '1' and acc.length = x"0000") or pr.m.burst = '0' then
pv.m.acc(pr.m.acc_sel).done(0) := '1';
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).lastf := '1';
else
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).lastf := '0';
end if;
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).status := (others => '0');
end if;
pv.m.acc(pr.m.acc_sel).fifo_wen := '1';
pv.m.fifo_addr := conv_std_logic_vector(acc.fifo_index, log2(FIFO_COUNT)) & pr.m.addr(AHB_FIFO_BITS);
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).stop := pv.m.fifo_addr(FIFO_DEPTH-1 downto 0);
if ((fifo_empty(fifo_nindex) = '0' or acc_switch = '1') and pr.m.fifo_addr(FIFO_DEPTH-1 downto 0) = conv_std_logic_vector((conv_integer(ones32(FIFO_DEPTH-1 downto 0)) - 3), FIFO_DEPTH)) -- terminate access when 3 words left to store in FIFO or 3 word left i transfer
or (acc.mode(1) = '1' and acc.length = x"0002") then
pv.m.term(0) := '1';
pv.m.afull := '1'; -- almost full
pv.m.afullcnt := "00"; -- reset full counter
end if;
if pr.m.afull = '1' then -- when transfer is terminated, count data phases (1 - 3)
if pr.m.afullcnt = "01" then
pv.m.afullcnt := (others => '0');
pv.m.afull := '0';
else
pv.m.afullcnt := pr.m.afullcnt + 1;
end if;
end if;
end if;
if (pr.m.afull = '1' and pr.m.afullcnt = "01" and pr.m.first(0) = '1' and pr.m.state = pm_addr)
or (pr.m.afull = '1' and pr.m.afullcnt = "00" and pr.m.state = pm_m_data) -- terminate first or second data phase depending on space left in fifo
or (acc.mode(1) = '1' and ((acc.length = x"0000" and pr.m.state = pm_addr) or (acc.length = x"0001" and pr.m.state = pm_m_data)))then pv.m.term(0) := '1'; end if; -- DMA 1 or 2 word to complete transfer
if pr.m.term(0) = '1' and fifo_empty(acc.fifo_index) = '1' and (pr.m.state = pm_idle or pr.m.state = pm_dr_bus) then
pv.m.term := (others => '0'); -- Start new access when a fifo becomes empty
end if;
if pr.m.state = pm_s_tar and fifo_empty(acc.fifo_index) = '1' and pv.m.fifo_switch = '0' then pv.m.term(0) := '0'; end if; -- If disconnected, rerequest the bus if fifo is available (but not if fifo switch)
if (pr.m.state = pm_m_data or pr.m.state = pm_turn_ar or pr.m.state = pm_s_tar) and pi.irdy = '0' and (pi.trdy = '0' or (pi.stop = '0' and pi.devsel = '1')) then pv.m.first_word := '0'; end if;
if (acc.done(0) = '1' and (pv.m.first_word = '0' or acc.done(2) = '1'))
or ((pr.m.acc_switch = '1' or fifo_empty(acc.fifo_index) = '0') and pr.m.fifo_switch = '1') then -- Transfer read is done (or no empty fifo), cancelled or access arbitration
m_request := '0';
pv.m.term(0) := '1';
if ((pi.frame and pi.irdy) = '1' and (pr.m.state = pm_idle or pr.m.state = pm_dr_bus)) then
pv.m.fstate := pmf_idle;
pv.m.term := (others => '0');
pv.m.acc(pr.m.acc_sel).active(0) := '0';
pv.m.acc(pr.m.acc_sel).addr := pr.m.addr;
if acc.done(0) = '1' then
pv.m.acc(pr.m.acc_sel).active(1) := '0';
if acc.mode(2) = '0' or acc.mode(0) = '0' then
pv.m.acc(pr.m.acc_sel).pending := '0';
pv.m.acc(pr.m.acc_sel).done(1) := '1';
else
pv.m.acc(pr.m.acc_sel).done(1) := '0';
end if;
end if;
end if;
end if;
-- Access canceled
if acc_cancel = '1' then
pv.m.acc(pr.m.acc_sel).done(0) := '1';
end if;
-- Access aborted by PCI error
if pr.m.abort(0) = '1' and pr.m.acc(pr.m.acc_sel).done(2) = '0' then
pv.m.acc(pr.m.acc_sel).done(0) := '1';
pv.m.acc(pr.m.acc_sel).done(2) := '1'; -- error
pv.m.acc(pr.m.acc_sel).fifo_index := fifo_nindex;
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).pending(0) := not pr.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).pending(0);
pv.m.acc(pr.m.acc_sel).first := '0';
if acc.first = '1' then
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).firstf := '1';
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).start := acc.addr(AHB_FIFO_BITS);
else
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).firstf := '0';
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).start := (others => '0');
end if;
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).lastf := '1';
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).status := '0' & (not pr.m.abort(1) or m_mabort) & (pr.m.abort(1) or m_tabort) & '0'; -- Error type: Master abort, Target abort, (PAR error)
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).stop := pr.m.addr(AHB_FIFO_BITS);
end if;
-- Set PAR error status
if pr.m.fifo_switch = '1' then
pv.pta_trans.msd_fifo(pr.m.acc_sel)(conv_integer(pr.m.fifo_addr(pr.m.fifo_addr'left downto FIFO_DEPTH))).status(0) := pv.m.acc(pr.m.acc_sel).status(0);
pv.m.acc(pr.m.acc_sel).status(0) := '0';
end if;
when others =>
end case;
-- New (Master state machine is moed to PHY)
if pr.m.state = pm_addr then pv.m.first_word := '1'; end if;
end if; -- PCI master enabled
-- --------------------------------------------------------------------------------
-- PCI target defaults
-- --------------------------------------------------------------------------------
-- Defaults
t_hit := '0'; t_chit := '0';
pv.t.cur_acc(0).newacc := '0';
pv.t.hold_reset := '1';
t_cad := (others => '0');
pv.t.first_word := '0';
t_ready := '0'; t_retry := '0';
t_abort := pr.t.stop;
t_acc_read := '1';
t_acc_burst := '1';
t_acc_type := "00";
t_acc_impcfgreg := '1';
-- FIFO (Block RAM enable(read)/write)
pv.t.atp.ctrl.en := '0'; -- read enable
pv.t.pta.ctrl.en := '0'; -- write enable
pv.t.pta.ctrl.data := byte_twist(pi.ad, pr.pta_trans.ca_twist);
tm_acc_pending := pr.pta_trans.tm_acc.pending xor atp_trans.tm_acc_ack;
tm_acc_cancel := pr.pta_trans.tm_acc_cancel xor atp_trans.tm_acc_cancel_ack(RAM_LATENCY);
tm_acc_done := pr.pta_trans.tm_acc_done_ack xor atp_trans.tm_acc_done.done;
for i in 0 to FIFO_COUNT-1 loop
tm_fifo_pending(i) := atp_trans.tm_fifo(i).pending(RAM_LATENCY) xor pr.pta_trans.tm_fifo_ack(i);
tm_fifo_empty(i) := not (pr.pta_trans.tm_fifo(i).pending(0) xor atp_trans.tm_fifo_ack(i));
pv.pta_trans.tm_fifo(i).pending(1) := pr.pta_trans.tm_fifo(i).pending(0);
pv.pta_trans.tm_fifo(i).pending(2) := pr.pta_trans.tm_fifo(i).pending(1);
end loop;
tm_fifo := ar.atp_trans.tm_fifo;
accbufindex := 0;
-- Not used
if tm_acc_done = '1' then
pv.pta_trans.tm_acc_done_ack := atp_trans.tm_acc_done.done;
end if;
-- --------------------------------------------------------------------------------
-- PCI target core
-- --------------------------------------------------------------------------------
if target /= 0 then -- PCI target enabled
-- Target latency counter
if pv.t.state = pt_s_data and pr.po.trdy = '1' and pr.t.lcount /= "111" then
pv.t.lcount := pr.t.lcount + 1;
elsif pr.po.trdy = '0' then
pv.t.lcount := (others => '0');
end if;
-- select next fifo
if pr.t.cur_acc(0).read = '1' then
if pr.t.atp.index /= FIFO_COUNT-1 then t_index := (pr.t.atp.index + 1);
else t_index := 0; end if;
else
if pr.t.pta.index /= FIFO_COUNT-1 then t_index := (pr.t.pta.index + 1);
else t_index := 0; end if;
end if;
-- PCI BAR address matching
t_bar := (others => '0'); t_func := 0;
for j in 0 to multifunc loop
for i in 0 to 5 loop
if (pi.ad(31 downto barminsize) and pr.conf(j).bar_mask(i)(31 downto barminsize)) =
(pr.conf(j).bar(i)(31 downto barminsize) and pr.conf(j).bar_mask(i)(31 downto barminsize)) and
pr.conf(j).bar_mask(i)(31) = '1' then
if pr.conf(j).bar_mask(i)(0) = '0' and (pi.cbe = MEM_READ or pi.cbe = MEM_R_MULT or pi.cbe = MEM_R_LINE
or pi.cbe = MEM_WRITE or pi.cbe = MEM_W_INV) then
t_hit := pr.conf(j).comm.memen; -- Only hit if memory access is enabled
t_bar(i) := '1';
t_func := j;
elsif pr.conf(j).bar_mask(i)(0) = '1' and (pi.cbe = IO_READ or pi.cbe = IO_WRITE) then
t_hit := pr.conf(j).comm.ioen; -- Only hit if io access is enabled
t_bar(i) := '1';
t_func := j;
end if;
end if;
end loop;
end loop;
-- Configuration hit when IDSEL or self config (AD[31:11]=0 => no IDSEL) and in host slot
if ((pi.idsel = '1' or (pi.ad(31 downto 11) = zero32(31 downto 11) and pi.host = '0')) -- IDSEL asserted
and (pi.cbe = CONF_READ or pi.cbe = CONF_WRITE)) and pi.ad(1 downto 0) = "00" -- Command = config read or write, Type = 0
and pi.ad(10 downto 8) <= conv_std_logic_vector(multifunc, 3) then -- Respond to implemented function
t_chit := '1';
end if;
-- Read prefetch discard timer
if atp_trans.pa_discardtout_rst = '1' then
pv.pta_trans.pa_discardtout := '0';
end if;
if pr.t.cur_acc(0).pending = '1' and pr.t.discardtimeren = '1' then
if pr.t.discardtimer = x"0000" then
if pr.t.state = pt_idle then
pv.pta_trans.pa_discardtout := '1';
pv.t.cur_acc(0).pending := '0';
pv.t.cur_acc(0).newacc := '1';
pv.t.cur_acc(0).oldburst := pr.t.cur_acc(0).burst;
end if;
else
pv.t.discardtimer := pr.t.discardtimer - 1;
end if;
end if;
-- Access buffer
if tm_acc_pending = '0' and pr.t.accbuf(0).pending = '1' then
pv.pta_trans.tm_acc := pr.t.accbuf(0);
pv.pta_trans.tm_acc.pending := not pr.pta_trans.tm_acc.pending;
pv.t.accbuf(0) := pr.t.accbuf(1);
pv.t.accbuf(1) := pr.t.accbuf(2);
pv.t.accbuf(2) := pr.t.accbuf(3);
pv.t.accbuf(3).pending := '0';
end if;
pv.pciinten := (others => oeoff);
for i in 0 to 3 loop
if i <= multifunc then
pv.conf(i).stat.intsta := conv_std_logic(pciinten(i) /= oeoff);
if pr.conf(i).comm.intdis = '0' then
pv.pciinten(i) := pciinten(i);
end if;
else
pv.conf(0).stat.intsta := conv_std_logic(pciinten(i) /= oeoff);
if pr.conf(0).comm.intdis = '0' then
pv.pciinten(i) := pciinten(i);
end if;
end if;
end loop;
if multiint = 0 then
if oeoff = '1' then
pciinten_pad(0) <= andv(pr.pciinten);
else
pciinten_pad(0) <= orv(pr.pciinten);
end if;
pciinten_pad(3 downto 1) <= (others => oeoff);
else
pciinten_pad <= pr.pciinten;
end if;
-- PCI Configuration Space Header
conf_func := 0;
if conv_integer(pr.t.cur_acc(0).addr(10 downto 8)) <= multifunc then
conf_func := conv_integer(pr.t.cur_acc(0).addr(10 downto 8));
end if;
-- read
if pr.t.cur_acc(0).impcfgreg = '1' then
if pr.t.cur_acc(0).acc_type(0) = '0' then
case pr.t.conf_addr is
when "0000" => -- Device and Vendor ID
t_cad := conv_std_logic_vector(deviceid_vector(conf_func),16) & conv_std_logic_vector(vendorid,16);
when "0001" => -- Status and Command
t_cad := pr.conf(conf_func).stat.dpe & pr.conf(conf_func).stat.sse & pr.conf(conf_func).stat.rma & pr.conf(conf_func).stat.rta &
pr.conf(conf_func).stat.sta & "01" & pr.conf(conf_func).stat.mdpe & "00"& pr.pci66(1) &
"1"& pr.conf(conf_func).stat.intsta &"000" &
"00000" & pr.conf(conf_func).comm.intdis & "0" & pr.conf(conf_func).comm.serren & "0" & pr.conf(conf_func).comm.perren & "0" &
pr.conf(conf_func).comm.mwien & "0" & pr.conf(conf_func).comm.msten & pr.conf(conf_func).comm.memen & pr.conf(conf_func).comm.ioen;
when "0010" => -- Class Code and Revision ID
t_cad := conv_std_logic_vector(classcode_vector(conf_func),24) & conv_std_logic_vector(revisionid_vector(conf_func),8);
when "0011" => -- BIST, Header Type, Latency Timer and Cache Line Size
t_cad := "00000000" & conv_std_logic(multifunc /= 0) & "0000000" & pr.conf(conf_func).ltimer & "00000000";
when "0100" => -- BAR0
t_cad := pr.conf(conf_func).bar(0);
--t_cad(3) := bar_prefetch(0);
t_cad(3) := pr.conf(conf_func).bar_mask(0)(3);
t_cad(0) := pr.conf(conf_func).bar_mask(0)(0);
when "0101" => -- BAR1
t_cad := pr.conf(conf_func).bar(1);
--t_cad(3) := bar_prefetch(1);
t_cad(3) := pr.conf(conf_func).bar_mask(1)(3);
t_cad(0) := pr.conf(conf_func).bar_mask(1)(0);
when "0110" => -- BAR2
t_cad := pr.conf(conf_func).bar(2);
--t_cad(3) := bar_prefetch(2);
t_cad(3) := pr.conf(conf_func).bar_mask(2)(3);
t_cad(0) := pr.conf(conf_func).bar_mask(2)(0);
when "0111" => -- BAR3
t_cad := pr.conf(conf_func).bar(3);
--t_cad(3) := bar_prefetch(3);
t_cad(3) := pr.conf(conf_func).bar_mask(3)(3);
t_cad(0) := pr.conf(conf_func).bar_mask(3)(0);
when "1000" => -- BAR4
t_cad := pr.conf(conf_func).bar(4);
--t_cad(3) := bar_prefetch(4);
t_cad(3) := pr.conf(conf_func).bar_mask(4)(3);
t_cad(0) := pr.conf(conf_func).bar_mask(4)(0);
when "1001" => -- BAR5
t_cad := pr.conf(conf_func).bar(5);
--t_cad(3) := bar_prefetch(5);
t_cad(3) := pr.conf(conf_func).bar_mask(5)(3);
t_cad(0) := pr.conf(conf_func).bar_mask(5)(0);
when "1010" => -- Cardbus CIS Pointer
t_cad := (others => '0');
when "1011" => -- Subsystem ID and Subsystem Vendor ID
t_cad := (others => '0');
when "1100" => -- Expansion ROM Base Address
t_cad := (others => '0');
when "1101" => -- Reserved and Capabillities Pointer
t_cad := (others => '0');
t_cad(7 downto 0) := conv_std_logic_vector(cap_pointer_vector(conf_func), 8);
when "1110" => -- Reserved
t_cad := (others => '0');
when "1111" => -- Max_Lat, Min_Gnt, Interrupt Pin and Interrupt Line
t_cad := x"00" & x"00" & (x"0"&"0"&conv_std_logic_vector(deviceirq_vector(conf_func), 3)) & pr.conf(conf_func).iline;
when others =>
t_cad := (others => '0');
end case;
else -- Mapping register
case pr.t.conf_addr is
when "0000" =>
t_cad := x"0040" & conv_std_logic_vector(ext_cap_pointer_vector(conf_func), 8) & x"09";
when "0001" =>
t_cad := pr.conf(conf_func).pta_map(0);
when "0010" =>
t_cad := pr.conf(conf_func).pta_map(1);
when "0011" =>
t_cad := pr.conf(conf_func).pta_map(2);
when "0100" =>
t_cad := pr.conf(conf_func).pta_map(3);
when "0101" =>
t_cad := pr.conf(conf_func).pta_map(4);
when "0110" =>
t_cad := pr.conf(conf_func).pta_map(5);
when "0111" =>
t_cad := pr.conf(conf_func).cfg_map;
when "1000" =>
t_cad := conv_std_logic_vector(iobase, 12) & x"0000"&"00"&pr.t.discardtimeren&pr.pta_trans.ca_twist; -- AHB IO base address (used to find P&P information) and byte twisting
when "1001" =>
t_cad := pr.conf(conf_func).bar_mask(0);
when "1010" =>
t_cad := pr.conf(conf_func).bar_mask(1);
when "1011" =>
t_cad := pr.conf(conf_func).bar_mask(2);
when "1100" =>
t_cad := pr.conf(conf_func).bar_mask(3);
when "1101" =>
t_cad := pr.conf(conf_func).bar_mask(4);
when "1110" =>
t_cad := pr.conf(conf_func).bar_mask(5);
when "1111" =>
t_cad := pr.t.saverfifo & "000" & x"000" & pr.t.blenmask; -- Burst lenght boundary mask
when others =>
t_cad := (others => '0');
end case;
end if;
end if;
-- write
if (pi.irdy or pi.trdy) = '0' and pr.t.cur_acc(0).acc_type(1) = '1' and pr.t.cur_acc(0).impcfgreg = '1' and
pr.t.cur_acc(0).read = '0' and pr.t.fstate = ptf_cwrite then
-- Support for all CBE combinations
if pi.cbe(3) = '0' then t_cad(31 downto 24) := pi.ad(31 downto 24); end if;
if pi.cbe(2) = '0' then t_cad(23 downto 16) := pi.ad(23 downto 16); end if;
if pi.cbe(1) = '0' then t_cad(15 downto 8) := pi.ad(15 downto 8); end if;
if pi.cbe(0) = '0' then t_cad( 7 downto 0) := pi.ad( 7 downto 0); end if;
if pr.t.cur_acc(0).acc_type(0) = '0'then
case pr.t.conf_addr is
--when "0000" => -- Device and Vendor ID
when "0001" => -- Status and Command
-- Command register
pv.conf(conf_func).comm.ioen := t_cad(0);
pv.conf(conf_func).comm.memen := t_cad(1);
if MASTER = 1 then
pv.conf(conf_func).comm.msten := t_cad(2);
pv.pta_trans.ca_pcimsten(conf_func) := pv.conf(conf_func).comm.msten;
end if;
pv.conf(conf_func).comm.mwien := t_cad(4);
pv.conf(conf_func).comm.perren := t_cad(6);
pv.conf(conf_func).comm.serren := t_cad(8);
pv.conf(conf_func).comm.intdis := t_cad(10);
-- Status register, sticky bits
pv.conf(conf_func).stat.mdpe := pr.conf(conf_func).stat.mdpe and not t_cad(24);
pv.conf(conf_func).stat.sta := pr.conf(conf_func).stat.sta and not t_cad(27);
pv.conf(conf_func).stat.rta := pr.conf(conf_func).stat.rta and not t_cad(28);
pv.conf(conf_func).stat.rma := pr.conf(conf_func).stat.rma and not t_cad(29);
pv.conf(conf_func).stat.sse := pr.conf(conf_func).stat.sse and not t_cad(30);
pv.conf(conf_func).stat.dpe := pr.conf(conf_func).stat.dpe and not t_cad(31);
--when "0010" => -- Class Code and Revision ID
when "0011" => -- BIST, Header Type, Latency Timer and Cache Line Size
pv.conf(conf_func).ltimer := t_cad(15 downto 8);
when "0100" => -- BAR0
if bar_size(conf_func)(0) /= 0 then
t_cad := t_cad and pr.conf(conf_func).bar_mask(0);
pv.conf(conf_func).bar(0)(31 downto barminsize) := t_cad(31 downto barminsize);
end if;
when "0101" => -- BAR1
if bar_size(conf_func)(1) /= 0 then
t_cad := t_cad and pr.conf(conf_func).bar_mask(1);
pv.conf(conf_func).bar(1)(31 downto barminsize) := t_cad(31 downto barminsize);
end if;
when "0110" => -- BAR2
if bar_size(conf_func)(2) /= 0 then
t_cad := t_cad and pr.conf(conf_func).bar_mask(2);
pv.conf(conf_func).bar(2)(31 downto barminsize) := t_cad(31 downto barminsize);
end if;
when "0111" => -- BAR3
if bar_size(conf_func)(3) /= 0 then
t_cad := t_cad and pr.conf(conf_func).bar_mask(3);
pv.conf(conf_func).bar(3)(31 downto barminsize) := t_cad(31 downto barminsize);
end if;
when "1000" => -- BAR4
if bar_size(conf_func)(4) /= 0 then
t_cad := t_cad and pr.conf(conf_func).bar_mask(4);
pv.conf(conf_func).bar(4)(31 downto barminsize) := t_cad(31 downto barminsize);
end if;
when "1001" => -- BAR5
if bar_size(conf_func)(5) /= 0 then
t_cad := t_cad and pr.conf(conf_func).bar_mask(5);
pv.conf(conf_func).bar(5)(31 downto barminsize) := t_cad(31 downto barminsize);
end if;
--when "1010" => -- Cardbus CIS Pointer
--when "1011" => -- Subsystem ID and Subsystem Vendor ID
--when "1100" => -- Expansion ROM Base Address
--when "1101" => -- Reserved and Capabillities Pointer
--when "1110" => -- Reserved
when "1111" => -- Max_Lat, Min_Gnt, Interrupt Pin and Interrupt Line
pv.conf(conf_func).iline := t_cad(7 downto 0);
when others =>
end case;
else -- Mapping registers
case pr.t.conf_addr is
when "0001" =>
if bar_size(conf_func)(0) /= 0 then
t_cad := t_cad and pr.conf(conf_func).bar_mask(0);
pv.conf(conf_func).pta_map(0)(31 downto barminsize) := t_cad(31 downto barminsize);
end if;
when "0010" =>
if bar_size(conf_func)(1) /= 0 then
t_cad := t_cad and pr.conf(conf_func).bar_mask(1);
pv.conf(conf_func).pta_map(1)(31 downto barminsize) := t_cad(31 downto barminsize);
end if;
when "0011" =>
if bar_size(conf_func)(2) /= 0 then
t_cad := t_cad and pr.conf(conf_func).bar_mask(2);
pv.conf(conf_func).pta_map(2)(31 downto barminsize) := t_cad(31 downto barminsize);
end if;
when "0100" =>
if bar_size(conf_func)(3) /= 0 then
t_cad := t_cad and pr.conf(conf_func).bar_mask(3);
pv.conf(conf_func).pta_map(3)(31 downto barminsize) := t_cad(31 downto barminsize);
end if;
when "0101" =>
if bar_size(conf_func)(4) /= 0 then
t_cad := t_cad and pr.conf(conf_func).bar_mask(4);
pv.conf(conf_func).pta_map(4)(31 downto barminsize) := t_cad(31 downto barminsize);
end if;
when "0110" =>
if bar_size(conf_func)(5) /= 0 then
t_cad := t_cad and pr.conf(conf_func).bar_mask(5);
pv.conf(conf_func).pta_map(5)(31 downto barminsize) := t_cad(31 downto barminsize);
end if;
when "0111" =>
pv.conf(conf_func).cfg_map(31 downto 8) := t_cad(31 downto 8);
when "1000" =>
pv.t.discardtimeren := t_cad(1);
pv.pta_trans.ca_twist := t_cad(0);
when "1001" =>
if bar_size(conf_func)(0) /= 0 then
pv.conf(conf_func).bar_mask(0)(31 downto barminsize) := t_cad(31 downto barminsize);
pv.conf(conf_func).bar_mask(0)(3) := t_cad(3);
pv.conf(conf_func).bar_mask(0)(0) := t_cad(0);
end if;
when "1010" =>
if bar_size(conf_func)(1) /= 0 then
pv.conf(conf_func).bar_mask(1)(31 downto barminsize) := t_cad(31 downto barminsize);
pv.conf(conf_func).bar_mask(1)(3) := t_cad(3);
pv.conf(conf_func).bar_mask(1)(0) := t_cad(0);
end if;
when "1011" =>
if bar_size(conf_func)(2) /= 0 then
pv.conf(conf_func).bar_mask(2)(31 downto barminsize) := t_cad(31 downto barminsize);
pv.conf(conf_func).bar_mask(2)(3) := t_cad(3);
pv.conf(conf_func).bar_mask(2)(0) := t_cad(0);
end if;
when "1100" =>
if bar_size(conf_func)(3) /= 0 then
pv.conf(conf_func).bar_mask(3)(31 downto barminsize) := t_cad(31 downto barminsize);
pv.conf(conf_func).bar_mask(3)(3) := t_cad(3);
pv.conf(conf_func).bar_mask(3)(0) := t_cad(0);
end if;
when "1101" =>
if bar_size(conf_func)(4) /= 0 then
pv.conf(conf_func).bar_mask(4)(31 downto barminsize) := t_cad(31 downto barminsize);
pv.conf(conf_func).bar_mask(4)(3) := t_cad(3);
pv.conf(conf_func).bar_mask(4)(0) := t_cad(0);
end if;
when "1110" =>
if bar_size(conf_func)(5) /= 0 then
pv.conf(conf_func).bar_mask(5)(31 downto barminsize) := t_cad(31 downto barminsize);
pv.conf(conf_func).bar_mask(5)(3) := t_cad(3);
pv.conf(conf_func).bar_mask(5)(0) := t_cad(0);
end if;
when "1111" =>
pv.t.blenmask(blenmask_size(barminsize) downto FIFO_DEPTH) := t_cad(blenmask_size(barminsize) downto FIFO_DEPTH);
pv.t.saverfifo := t_cad(31);
when others =>
end case;
end if;
end if;
-- FIFO State machine
case pr.t.fstate is
when ptf_idle =>
pv.t.first := (others => '1');
pv.t.preload := '0';
pv.t.preload_count := (others => '0');
pv.t.diswithout := '0';
if pr.t.cur_acc(0).pending = '1' then
if pr.t.cur_acc(0).read = '1' then -- Memory and Config read
pv.t.fstate := ptf_fifo;
pv.t.atp.ctrl.addr := conv_std_logic_vector(pr.t.atp.index, log2(FIFO_COUNT)) & pr.t.cur_acc(0).addr(FIFO_DEPTH+1 downto 2);
else
if pr.t.cur_acc(0).acc_type(1) = '1' then -- Config write
pv.t.fstate := ptf_cwrite;
pv.t.conf_addr := pr.t.cur_acc(0).addr(5 downto 2);
t_ready := '1';
elsif tm_fifo_empty(pr.t.pta.index) = '1' then -- Memory write
-- Burst length (only burst up to this boundary)
pv.t.blen := ((not pr.t.cur_acc(0).addr(17 downto 2)) and pr.t.blenmask);
pv.t.fstate := ptf_write;
t_ready := '1';
pv.t.pta.ctrl.addr := conv_std_logic_vector(pr.t.pta.index, log2(FIFO_COUNT)) & pr.t.cur_acc(0).addr(FIFO_DEPTH+1 downto 2);
if pr.t.cur_acc(0).acc_type(0) = '0' then -- memory access
pv.t.addr := set_pta_addr(pr.t.cur_acc(0).addr, pr.conf(pr.t.cur_acc(0).func).pta_map, pr.t.cur_acc(0).bar, pr.conf(pr.t.cur_acc(0).func).bar_mask, barminsize);
else
pv.t.addr := pr.conf(conf_func).cfg_map(31 downto 8) & pr.t.cur_acc(0).addr(7 downto 0);
end if;
else
t_retry := '1';
pv.t.fstate := ptf_idle;
pv.t.cur_acc(0).pending := '0';
end if;
end if;
if pr.t.cur_acc(0).acc_type(1) = '0' and -- Access to AHB
( (pr.t.cur_acc(0).read = '1') -- Read
or (pr.t.cur_acc(0).read = '0' and tm_fifo_empty(pr.t.pta.index) = '1')) then -- Write
if tm_acc_pending = '0' and pr.t.accbuf(0).pending = '0' then
pv.pta_trans.tm_acc.pending := not pr.pta_trans.tm_acc.pending;
if pr.t.cur_acc(0).acc_type(0) = '0' then -- memory access
pv.pta_trans.tm_acc.addr := set_pta_addr(pr.t.cur_acc(0).addr, pr.conf(pr.t.cur_acc(0).func).pta_map, pr.t.cur_acc(0).bar, pr.conf(pr.t.cur_acc(0).func).bar_mask, barminsize);
else
pv.pta_trans.tm_acc.addr := pr.conf(conf_func).cfg_map(31 downto 8) & pr.t.cur_acc(0).addr(7 downto 0);
end if;
pv.pta_trans.tm_acc.acctype := "000" & not pr.t.cur_acc(0).read; -- acctype(0) = write
pv.pta_trans.tm_acc.accmode := "00" & pr.t.cur_acc(0).burst;
pv.pta_trans.tm_acc.size := (others => '0'); -- not used
pv.pta_trans.tm_acc.offset := (others => '0'); -- not used
if pr.t.cur_acc(0).read = '1' then pv.pta_trans.tm_acc.index := pr.t.atp.index;
else pv.pta_trans.tm_acc.index := pr.t.pta.index; end if;
pv.pta_trans.tm_acc.length := ((not pr.t.cur_acc(0).addr(17 downto 2)) and pr.t.blenmask);
pv.pta_trans.tm_acc.cbe := pi.cbe;
pv.pta_trans.tm_acc.endianess := pr.pta_trans.ca_twist;
else
accbufindex := 0;
for i in 3 downto 0 loop
if pv.t.accbuf(i).pending = '0' then accbufindex := i; end if;
end loop;
pv.t.accbuf(accbufindex).pending := '1';
if pr.t.cur_acc(0).acc_type(0) = '0' then -- memory access
pv.t.accbuf(accbufindex).addr := set_pta_addr(pr.t.cur_acc(0).addr, pr.conf(pr.t.cur_acc(0).func).pta_map, pr.t.cur_acc(0).bar, pr.conf(pr.t.cur_acc(0).func).bar_mask, barminsize);
else
pv.t.accbuf(accbufindex).addr := pr.conf(conf_func).cfg_map(31 downto 8) & pr.t.cur_acc(0).addr(7 downto 0);
end if;
pv.t.accbuf(accbufindex).acctype := "000" & not pr.t.cur_acc(0).read; -- acctype(0) = write
pv.t.accbuf(accbufindex).accmode := "00" & pr.t.cur_acc(0).burst;
pv.t.accbuf(accbufindex).size := (others => '0'); -- not used
pv.t.accbuf(accbufindex).offset := (others => '0'); -- not used
if pr.t.cur_acc(0).read = '1' then pv.t.accbuf(accbufindex).index := pr.t.atp.index;
else pv.t.accbuf(accbufindex).index := pr.t.pta.index; end if;
pv.t.accbuf(accbufindex).length := ((not pr.t.cur_acc(0).addr(17 downto 2)) and pr.t.blenmask);
pv.t.accbuf(accbufindex).cbe := pi.cbe;
pv.t.accbuf(accbufindex).endianess := pr.pta_trans.ca_twist;
end if;
end if;
end if;
when ptf_fifo =>
pv.t.atp.ctrl.en := tm_fifo_pending(pr.t.atp.index);
if (pr.t.hold(0) = '0' or pr.t.first_word = '1') and pr.t.cfifo(0).valid = '1' then
t_ready := '1';
end if;
if pr.t.cur_acc(0).newacc = '1' or
(tm_acc_cancel = '1' and pr.t.cur_acc(0).acc_type(1) = '0') or
pr.t.cur_acc(0).read = '0' then
t_ready := '0';
end if;
if (tm_acc_cancel = '0' and tm_fifo_pending(pr.t.atp.index) = '1') or pr.t.preload = '1' or pr.t.cur_acc(0).acc_type(1) = '1' then -- FIFO pending or Config access
pv.t.preload := '1';
if pr.t.preload = '0' then pv.t.hold_fifo := '0'; end if;
end if;
if ((pi.trdy or pi.irdy) = '0' and pr.t.state = pt_s_data) or pr.t.preload = '1' then
if (pi.trdy or pi.irdy) = '0' and pr.t.state = pt_s_data then
pv.t.cfifo(0) := pr.t.cfifo(1); pv.t.cfifo(1) := pr.t.cfifo(2); -- Preload target core fifo
pv.t.cur_acc(0).addr := pr.t.cur_acc(0).addr + 4;
elsif pr.t.preload = '1' then
if pr.t.cfifo(0).valid = '0' then
pv.t.cfifo(0) := pr.t.cfifo(1); pv.t.cfifo(1) := pr.t.cfifo(2); -- Preload target core fifo
elsif pr.t.cfifo(0).valid = '1' and pr.t.cfifo(1).valid = '0' then
pv.t.cfifo(1) := pr.t.cfifo(2); -- Preload target core fifo
end if;
end if;
if pr.t.cur_acc(0).acc_type(1) = '0' then -- Memory access
pv.t.cfifo(2).data := byte_twist(tm_fifoo_atp.data, pr.pta_trans.ca_twist); -- shifting in data from backend fifo
else
pv.t.cfifo(2).data := t_cad; -- Configuration access
end if;
if pr.t.cur_acc(0).acc_type(1) = '0' then -- Memory access
if tm_fifo_pending(pr.t.atp.index) = '1' then
if pr.t.atp.ctrl.addr(FIFO_DEPTH-1 downto 0) = tm_fifo(pr.t.atp.index).stop and pr.t.hold_fifo = '0' then -- Mark last word
pv.t.atp.index := t_index;
pv.t.atp.ctrl.addr := conv_std_logic_vector(pv.t.atp.index, log2(FIFO_COUNT)) & zero32(FIFO_DEPTH-1 downto 0); -- Reset backend fifo address
pv.pta_trans.tm_fifo_ack(pr.t.atp.index) := tm_fifo(pr.t.atp.index).pending(RAM_LATENCY); -- Ack the fifo (done using this data)
if tm_fifo_pending(t_index) = '1' then
pv.t.cfifo(2).hold := '0';
else
pv.t.cfifo(2).hold := '1';
pv.t.hold_fifo := '1';
-- Disconnect on last fifo
if tm_fifo(pr.t.atp.index).lastf = '1' then pv.t.cfifo(2).stlast := '1'; end if;
-- Disable fifo read
pv.t.atp.ctrl.en := '0';
end if;
else
pv.t.cfifo(2).hold := '0';
if pr.t.hold_fifo = '0' then
pv.t.atp.ctrl.addr := conv_std_logic_vector(pv.t.atp.index, log2(FIFO_COUNT)) & pr.t.atp.ctrl.addr(FIFO_DEPTH-1 downto 0) + 1; -- inc backend fifo address
end if;
end if;
if pr.t.atp.ctrl.addr(FIFO_DEPTH-1 downto 0) = tm_fifo(pr.t.atp.index).stop and tm_fifo(pr.t.atp.index).status /= "0000" then
pv.t.cfifo(2).err := '1';
else
pv.t.cfifo(2).err := '0';
end if;
end if;
else -- Configuration access
if pr.t.conf_addr = "1110" then
pv.t.cfifo(2).stlast := '1';
else
pv.t.cfifo(2).stlast := '0';
end if;
if pr.t.conf_addr = "1111" then
pv.t.cfifo(2).hold := '1';
if pr.t.preload_count = "00" then pv.t.cfifo(2).stlast := '1'; end if;
else
pv.t.cfifo(2).hold := '0';
pv.t.conf_addr := pr.t.conf_addr + 1; -- inc backend fifo address
end if;
pv.t.cfifo(2).err := '0';
end if;
if (tm_fifo_pending(pr.t.atp.index) = '1' or pr.t.cur_acc(0).acc_type(1) = '1') and pr.t.hold_fifo = '0' then
pv.t.cfifo(2).valid := '1';
else
pv.t.cfifo(2).valid := '0';
end if;
end if;
if (pv.t.cfifo(0).valid = '1' and pv.t.cfifo(1).valid = '1' and pv.t.cfifo(2).valid = '1')
or (pv.t.cfifo(0).valid = '1' and pr.t.cfifo(0).valid = '0')
or (pv.t.cfifo(0).valid = '1' and pr.t.cfifo(0).hold = '1' and pv.t.cfifo(1).valid = '1') then
pv.t.preload := '0';
if pr.t.preload = '1' or (pr.t.hold_fifo = '1' and pv.t.hold_fifo = '0') then
pv.t.hold_reset := '0';
if pr.t.cfifo(0).hold = '1' and pv.t.cfifo(1).valid = '1' then pv.t.cfifo(0).hold := '0'; end if;
if pr.t.cfifo(1).hold = '1' and pv.t.cfifo(2).valid = '1' then pv.t.cfifo(1).hold := '0'; end if;
if pr.t.cfifo(2).hold = '1' and tm_fifo_pending(pr.t.atp.index) = '1' then pv.t.cfifo(2).hold := '0'; end if;
end if;
end if;
if (pr.t.state = pt_turn_ar and pr.t.cur_acc(0).pending = '0' and pr.t.cur_acc(0).continue = '0')
or (pr.t.cur_acc(0).newacc = '1')
or ((pr.t.abort = '1' or pr.t.diswithout = '1') and (pr.t.state = pt_backoff or pr.t.state = pt_turn_ar))
then
if pr.t.cur_acc(0).burst = '1' and pr.t.abort = '0' then
if pr.t.cur_acc(0).acc_type(1) = '0' or pr.t.cur_acc(0).read = '0' or pr.t.cur_acc(0).pending = '0' then
pv.t.fstate := ptf_idle;
end if;
else
pv.t.fstate := ptf_idle;
if pr.t.abort = '1' then pv.t.cur_acc(0).pending := '0'; end if;
if pr.t.cur_acc(0).burst = '1' then pv.pta_trans.tm_acc_cancel := not pr.pta_trans.tm_acc_cancel; end if;
end if;
pv.t.hold_reset := '0';
for i in 0 to 2 loop
pv.t.cfifo(i).valid := '0';
pv.t.cfifo(i).hold := '0';
pv.t.cfifo(i).stlast := '0';
pv.t.cfifo(i).last := '0';
pv.t.cfifo(i).err := '0';
end loop;
if (pr.t.cur_acc(0).pending = '0' and pr.t.cur_acc(0).acc_type(1) = '0' and pr.t.cur_acc(0).burst = '1') or
(pr.t.cur_acc(0).newacc = '1' and pr.t.cur_acc(0).oldburst = '1') then
pv.pta_trans.tm_acc_cancel := not pr.pta_trans.tm_acc_cancel;
end if;
end if;
when ptf_cwrite =>
if pr.t.hold(0) = '0' then -- can maybe be optimized
t_ready := '1';
end if;
if pr.t.state = pt_turn_ar then
pv.t.fstate := ptf_idle;
pv.t.hold_reset := '0';
end if;
if (pi.trdy or pi.irdy) = '0' then
if pr.t.conf_addr /= "1111" then -- Config access
pv.t.conf_addr := pr.t.conf_addr + 1; -- inc backend fifo address
end if;
end if;
when ptf_write =>
if pr.t.hold(0) = '0' then -- can maybe be optimized
t_ready := '1';
elsif tm_fifo_empty(pr.t.pta.index) = '1' and pr.t.hold_write = '0' then
t_ready := '1';
pv.t.hold_reset := '0';
end if;
if (pr.t.addr(AHB_FIFO_BITS) = ones32(FIFO_DEPTH-1 downto 0) and pr.t.first(0) = '1' and
(tm_fifo_empty(t_index) = '0' or pr.t.blen = x"0000")) or
((pi.trdy or pi.irdy) = '0' and pr.t.blen = x"0001") or
pr.t.cur_acc(0).burst = '0' then
pv.t.diswithout := '1';
end if;
if pr.t.state = pt_turn_ar then
pv.t.fstate := ptf_idle;
pv.t.hold_reset := '0';
end if;
if (pi.trdy or pi.irdy) = '0' then
pv.t.pta.ctrl.en := '1';
pv.t.pta.ctrl.addr := conv_std_logic_vector(pr.t.pta.index, log2(FIFO_COUNT)) & pr.t.addr(AHB_FIFO_BITS);
if pi.cbe /= ones32(3 downto 0) or pr.t.first(0) = '1' then
pv.t.first(0) := '0';
pv.pta_trans.tm_fifo(pr.t.pta.index).stop := pr.t.addr(AHB_FIFO_BITS);
pv.pta_trans.tm_fifo(pr.t.pta.index).last_cbe := pi.cbe;
end if;
if pr.t.first(0) = '1' then -- First data in this fifo
pv.pta_trans.tm_fifo(pr.t.pta.index).start := pr.t.addr(AHB_FIFO_BITS);
end if;
pv.t.addr := pr.t.addr + 4; -- inc backend fifo address
if pr.t.blen /= zero32(15 downto 0) then
pv.t.blen := pr.t.blen - 1;
end if;
if pr.t.addr(AHB_FIFO_BITS) /= ones32(FIFO_DEPTH-1 downto 0) and pi.frame = '0' and pr.t.diswithout = '0' and pi.stop = '1' then
if pr.t.addr(AHB_FIFO_BITS) = conv_std_logic_vector((conv_integer(ones32(FIFO_DEPTH-1 downto 0)) - 1), FIFO_DEPTH) then
if tm_fifo_empty(t_index) = '0' then
pv.t.hold_write := '1';
t_ready := '0';
pv.t.diswithout := '1';
end if;
end if;
else
pv.t.first(0) := '1';
pv.t.first(1) := '0';
pv.t.hold_write := '0';
pv.t.pta.index := t_index;
pv.pta_trans.tm_fifo(pr.t.pta.index).pending(0) := not pr.pta_trans.tm_fifo(pr.t.pta.index).pending(0);
pv.pta_trans.tm_fifo(pr.t.pta.index).status := (others => '0');
if pr.t.first(1) = '1' then pv.pta_trans.tm_fifo(pr.t.pta.index).firstf := '1';
else pv.pta_trans.tm_fifo(pr.t.pta.index).firstf := '0'; end if;
if pi.frame = '1' or pr.t.diswithout = '1' then pv.pta_trans.tm_fifo(pr.t.pta.index).lastf := '1'; -- Mark last fifo
else pv.pta_trans.tm_fifo(pr.t.pta.index).lastf := '0'; end if;
end if;
end if;
when others =>
end case;
-- PCI State machine
case pr.t.state is
when pt_idle => -- The bus is in idle state
pv.t.hold_write := '0';
pv.t.lcount := (others => '0'); -- reset latency counter
pv.t.stoped := '0';
pv.t.retry := '0';
if pi.frame = '0' then
if t_hit = '1' or t_chit = '1' then
pv.t.state := pt_s_data;
pv.t.first_word := '1';
case pi.cbe is
when CONF_READ =>
t_acc_read := '1';
t_acc_burst := '1';
t_acc_type := "10";
pv.t.conf_addr := pi.ad(5 downto 2);
if pi.ad(7 downto 4) >= "0100" then
if ext_cap_pointer_vector(conf_func) /= 16#00# then
t_acc_type := "01";
else
t_acc_impcfgreg := '0';
end if;
if pi.ad(7 downto 4) >= conv_std_logic_vector(cap_pointer, 8)(7 downto 4)
and pi.ad(7 downto 4) < conv_std_logic_vector(cap_pointer + 16#40#, 8)(7 downto 4) then
t_acc_type := "11";
t_acc_impcfgreg := '1';
end if;
end if;
when CONF_WRITE =>
t_acc_read := '0';
t_acc_burst := '1';
t_acc_type := "10";
pv.t.conf_addr := pi.ad(5 downto 2);
if pi.ad(7 downto 4) >= "0100" then
if ext_cap_pointer_vector(conf_func) /= 16#00# then
t_acc_type := "01";
else
t_acc_impcfgreg := '0';
end if;
if pi.ad(7 downto 4) >= conv_std_logic_vector(cap_pointer, 8)(7 downto 4)
and pi.ad(7 downto 4) < conv_std_logic_vector(cap_pointer + 16#40#, 8)(7 downto 4) then
t_acc_type := "11";
t_acc_impcfgreg := '1';
end if;
end if;
when MEM_READ =>
t_acc_read := '1';
t_acc_burst := '0';
t_acc_type := "00";
when MEM_WRITE | MEM_W_INV =>
t_acc_read := '0';
-- Burst ordering: Linear Incrementing
if pi.ad(1 downto 0) = "00" then t_acc_burst := '1';
else t_acc_burst := '0'; end if;
t_acc_type := "00";
when IO_READ =>
t_acc_read := '1';
t_acc_burst := '0';
t_acc_type := "00";
when IO_WRITE =>
t_acc_read := '0';
t_acc_burst := '0';
t_acc_type := "00";
when MEM_R_MULT | MEM_R_LINE =>
t_acc_read := '1';
-- Burst ordering: Linear Incrementing
if pi.ad(1 downto 0) = "00" then t_acc_burst := '1';
else t_acc_burst := '0'; end if;
t_acc_type := "00";
when others =>
t_acc_read := '1';
t_acc_burst := '1';
t_acc_type := "00";
end case;
if (pr.t.cur_acc(0).pending = '1' or pr.t.cur_acc(0).continue = '1') and pr.t.cur_acc(0).addr = pi.ad
and t_acc_read = '1' and pr.t.cur_acc(0).acc_type(1) = '0' then
pv.t.cur_acc(0).match := '1';
pv.t.cur_acc(0).pending := '1';
pv.t.discardtimer := (others => '1');
elsif pr.t.cur_acc(0).pending = '0' then -- Save new access
pv.t.cur_acc(0).addr := pi.ad;
pv.t.cur_acc(0).pending := '1';
pv.t.cur_acc(0).retry := '0';
pv.t.cur_acc(0).read := t_acc_read;
pv.t.cur_acc(0).burst := t_acc_burst;
pv.t.cur_acc(0).acc_type := t_acc_type;
pv.t.cur_acc(0).impcfgreg := t_acc_impcfgreg;
pv.t.cur_acc(0).bar := t_bar;
pv.t.cur_acc(0).func := t_func;
pv.t.cur_acc(0).match := '0';
pv.t.discardtimer := (others => '1');
if pr.t.cur_acc(0).continue = '1' then
pv.t.cur_acc(0).newacc := '1';
pv.t.cur_acc(0).oldburst := pr.t.cur_acc(0).burst;
end if;
else
pv.t.cur_acc(0).match := '0';
end if;
pv.t.cur_acc(0).continue := '0';
else
pv.t.state := pt_b_busy;
end if;
end if;
when pt_b_busy => -- Wait for the current transaction to complete and bus return
-- to idle sate
if (pi.frame and pi.irdy) = '1' then
pv.t.state := pt_idle;
end if;
when pt_s_data => -- Target is transfering data
if (pi.frame and not pi.irdy and ( not pi.trdy or not pi.stop)) = '1' then
pv.t.state := pt_turn_ar;
pv.t.retry := '0';
if pr.t.cur_acc(0).pending = '0' and pr.t.cur_acc(0).acc_type(1) = '0' and
pr.t.cur_acc(0).read = '1' and pi.trdy = '1' and pi.stop = '0' and pr.t.stop = '0' and
pr.t.cur_acc(0).burst = '1' and pr.t.discardtimer /= x"0000" then
if pr.t.saverfifo = '1' then -- FIFO is saved until next access (disconnect without data).
-- If the next access is not the read continuing, the prefetched data is discarded.
pv.t.cur_acc(0).continue := '1';
end if;
end if;
elsif (not pi.frame and not pi.stop) = '1' then
pv.t.state := pt_backoff;
pv.t.retry := '0';
if pr.t.cur_acc(0).pending = '0' and pr.t.cur_acc(0).acc_type(1) = '0' and
pr.t.cur_acc(0).read = '1' and pr.t.stop = '0' and pr.t.stop = '0' and
pr.t.cur_acc(0).burst = '1' and pr.t.discardtimer /= x"0000" then
if pr.t.saverfifo = '1' then -- FIFO is saved until next access (disconnect without data).
-- If the next access is not the read continuing, the prefetched data is discarded.
pv.t.cur_acc(0).continue := '1';
end if;
end if;
end if;
if (not pi.irdy and not pi.trdy) = '1' then pv.t.cur_acc(0).pending := '0'; end if; -- Data transfered, reset pending
-- can maybe be optimized
if ((pr.t.cfifo(0).valid = '0' or pr.t.cur_acc(0).match = '0') and
pr.t.cur_acc(0).pending = '1' and pr.t.cur_acc(0).acc_type(1) = '0' and pr.t.cur_acc(0).read = '1') or
pr.t.retry = '1' then t_retry := '1'; pv.t.retry := '1'; end if;
-- CFIFO valid again after FIFO switch (First word in continued access), to reassert trdy
if pr.t.fstate = ptf_fifo and pr.t.preload = '1' and pr.t.first_word = '0' and
pr.t.cfifo(0).valid = '0' and pr.t.cfifo(1).valid = '1' then
pv.t.first_word := '1';
end if;
-- When FIFO is saved until next access (disconnect without data)
-- the first_word signal needs to be set one extra cycle to be valid the cycle before
-- FIFO state-machine moves to FIFO write state
if pr.t.fstate = ptf_fifo and pr.t.first_word = '1' and
pr.t.cur_acc(0).pending = '1' and pr.t.cur_acc(0).newacc = '1' and
pr.t.cur_acc(0).read = '0' then
if pr.t.saverfifo = '1' then
pv.t.first_word := '1';
end if;
end if;
when pt_backoff => -- STOP# is asserted, waiting on deasserted FRAME#
if pi.frame = '1' then
pv.t.state := pt_turn_ar;
end if;
when pt_turn_ar => -- Deassert active signals before tri-state
-- from idle
pv.t.hold_write := '0';
pv.t.lcount := (others => '0'); -- reset latency counter
pv.t.stoped := '0';
pv.t.retry := '0';
if pi.frame = '1' then
pv.t.state := pt_idle;
elsif pi.frame = '0' then
if t_hit = '1' or t_chit = '1' then
pv.t.state := pt_s_data;
pv.t.first_word := '1';
case pi.cbe is
when CONF_READ =>
t_acc_read := '1';
t_acc_burst := '1';
t_acc_type := "10";
pv.t.conf_addr := pi.ad(5 downto 2);
if pi.ad(7 downto 4) >= "0100" then
if ext_cap_pointer_vector(conf_func) /= 16#00# then
t_acc_type := "01";
else
t_acc_impcfgreg := '0';
end if;
if pi.ad(7 downto 4) >= conv_std_logic_vector(cap_pointer, 8)(7 downto 4)
and pi.ad(7 downto 4) < conv_std_logic_vector(cap_pointer + 16#40#, 8)(7 downto 4) then
t_acc_type := "11";
t_acc_impcfgreg := '1';
end if;
end if;
when CONF_WRITE =>
t_acc_read := '0';
t_acc_burst := '1';
t_acc_type := "10";
pv.t.conf_addr := pi.ad(5 downto 2);
if pi.ad(7 downto 4) >= "0100" then
if ext_cap_pointer_vector(conf_func) /= 16#00# then
t_acc_type := "01";
else
t_acc_impcfgreg := '0';
end if;
if pi.ad(7 downto 4) >= conv_std_logic_vector(cap_pointer, 8)(7 downto 4)
and pi.ad(7 downto 4) < conv_std_logic_vector(cap_pointer + 16#40#, 8)(7 downto 4) then
t_acc_type := "11";
t_acc_impcfgreg := '1';
end if;
end if;
when MEM_READ =>
t_acc_read := '1';
t_acc_burst := '0';
t_acc_type := "00";
when MEM_WRITE | MEM_W_INV =>
t_acc_read := '0';
-- Burst ordering: Linear Incrementing
if pi.ad(1 downto 0) = "00" then t_acc_burst := '1';
else t_acc_burst := '0'; end if;
t_acc_type := "00";
when IO_READ =>
t_acc_read := '1';
t_acc_burst := '0';
t_acc_type := "00";
when IO_WRITE =>
t_acc_read := '0';
t_acc_burst := '0';
t_acc_type := "00";
when MEM_R_MULT | MEM_R_LINE =>
t_acc_read := '1';
-- Burst ordering: Linear Incrementing
if pi.ad(1 downto 0) = "00" then t_acc_burst := '1';
else t_acc_burst := '0'; end if;
t_acc_type := "00";
when others =>
t_acc_read := '1';
t_acc_burst := '1';
t_acc_type := "00";
end case;
if (pr.t.cur_acc(0).pending = '1' or pr.t.cur_acc(0).continue = '1') and pr.t.cur_acc(0).addr = pi.ad and t_acc_read = '1' and pr.t.cur_acc(0).acc_type(1) = '0' then
pv.t.cur_acc(0).match := '1';
pv.t.cur_acc(0).pending := '1';
pv.t.discardtimer := (others => '1');
elsif pr.t.cur_acc(0).pending = '0' then -- Save new access
pv.t.cur_acc(0).addr := pi.ad;
pv.t.cur_acc(0).pending := '1';
pv.t.cur_acc(0).retry := '0';
pv.t.cur_acc(0).read := t_acc_read;
pv.t.cur_acc(0).burst := t_acc_burst;
pv.t.cur_acc(0).acc_type := t_acc_type;
pv.t.cur_acc(0).impcfgreg := t_acc_impcfgreg;
pv.t.cur_acc(0).bar := t_bar;
pv.t.cur_acc(0).func := t_func;
pv.t.cur_acc(0).match := '0';
pv.t.discardtimer := (others => '1');
if pr.t.cur_acc(0).continue = '1' then
pv.t.cur_acc(0).newacc := '1';
pv.t.cur_acc(0).oldburst := pr.t.cur_acc(0).burst;
end if;
else
pv.t.cur_acc(0).match := '0';
end if;
pv.t.cur_acc(0).continue := '0';
else
pv.t.state := pt_b_busy;
end if;
end if;
when others =>
end case;
if pr.t.fstate = ptf_idle then pv.t.hold_reset := '0'; end if;
if pr.po.stop = '0' then pv.t.stoped := '1'; end if;
end if; -- PCI target enabled
-- --------------------------------------------------------------------------------
-- PCI trace
-- --------------------------------------------------------------------------------
-- sync
pv.pt_sync(1) := ar.atpt_trans; pv.pt_sync(2) := pr.pt_sync(1);
if nsync = 0 then atpt_trans := ar.atpt_trans;
else atpt_trans := pr.pt_sync(nsync); end if;
pt_setup := ar.atpt_trans;
pv.ptta_trans.start_ack := atpt_trans.start;
pv.ptta_trans.stop_ack := atpt_trans.stop;
pt_start := not pr.ptta_trans.start_ack and (pr.ptta_trans.start_ack xor atpt_trans.start);
pt_stop := not pr.ptta_trans.stop_ack and (pr.ptta_trans.stop_ack xor atpt_trans.stop);
if tracebuffer /= 0 then -- PCI trace buffer enabled
if pr.ptta_trans.enable = '1' then -- PCI tracing
pv.pt.addr := pr.pt.addr + 1;
if pr.ptta_trans.armed = '1' then -- Check for match
if ((((pi.ad & pcisig) xor (pt_setup.ad & pt_setup.sig)) and (pt_setup.admask & pt_setup.sigmask)) = z) then
if pr.pt.tcount = x"00" then
pv.ptta_trans.armed := '0'; -- Start saving trace
pv.ptta_trans.taddr := pr.pt.addr;
else pv.pt.tcount := pr.pt.tcount - 1; end if;
end if;
if pr.pt.addr = pr.ptta_trans.taddr then pv.ptta_trans.wrap := '1'; end if;
else
if pr.pt.count = zero32(PT_DEPTH-1 downto 0) then pv.ptta_trans.enable := '0'; -- Trace done
else pv.pt.count := pr.pt.count - 1; end if;
end if;
end if;
if pt_stop = '1' then -- Start PCI tracing
pv.ptta_trans.enable := '0';
if pr.ptta_trans.enable = '1' then
pv.ptta_trans.taddr := pr.pt.addr;
end if;
end if;
if pt_start = '1' then -- Start PCI tracing
pv.ptta_trans.enable := '1';
pv.ptta_trans.armed := '1';
pv.ptta_trans.wrap := '0';
pv.pt.count := pt_setup.count;
pv.pt.tcount := pt_setup.tcount;
end if;
--
pv.ptta_trans.dbg_ad := pi.ad;
pv.ptta_trans.dbg_sig := pcisig;
pv.ptta_trans.dbg_cur_ad := pr.t.cur_acc(0).addr;
pv.ptta_trans.dbg_cur_acc := pr.t.cur_acc(0).oldburst &
pr.t.cur_acc(0).acc_type &
pr.t.cur_acc(0).read &
pr.t.cur_acc(0).continue &
pr.t.cur_acc(0).burst &
pr.t.cur_acc(0).newacc &
pr.t.cur_acc(0).match &
pr.t.cur_acc(0).pending;
end if; -- PCI trace buffer enabled
-- --------------------------------------------------------------------------------
-- PCI debug
-- --------------------------------------------------------------------------------
--[31:30] ms_fifo_pending
--[29:28] ms_fifo_empty
--[37:36] tm_fifo_pending
--[25:24] tm_fifo_empty
--[ :23] ms_acc_pending;
--[ :22] ms_acc_cancel;
--[ :21] ms_acc_done;
--[ :20] md_acc_pending;
--[ :19] md_acc_cancel;
--[ :18] md_acc_done;
--[ :17] tm_acc_pending;
--[ :16] tm_acc_cancel;
--[ :15] tm_acc_done;
--[14:12] t.state
--[11: 8] t.fstate
--[ 7: 4] m.state
--[ 3: 0] m.fstate
pv.debug(31 downto 30) := ms_fifo_pending(1 downto 0);
pv.debug(29 downto 28) := ms_fifo_empty(1 downto 0);
pv.debug(27 downto 26) := tm_fifo_pending(1 downto 0);
pv.debug(25 downto 24) := tm_fifo_empty(1 downto 0);
pv.debug( 23) := ms_acc_pending;
pv.debug( 22) := ms_acc_cancel;
pv.debug( 21) := ms_acc_done;
pv.debug( 20) := md_acc_pending;
pv.debug( 19) := md_acc_cancel;
pv.debug( 18) := md_acc_done;
pv.debug( 17) := tm_acc_pending;
pv.debug( 16) := tm_acc_cancel;
pv.debug( 15) := tm_acc_done;
case pr.t.state is
when pt_idle => pv.debug(14 downto 12) := "000";
when pt_b_busy => pv.debug(14 downto 12) := "001";
when pt_s_data => pv.debug(14 downto 12) := "010";
when pt_backoff => pv.debug(14 downto 12) := "011";
when pt_turn_ar => pv.debug(14 downto 12) := "100";
when others => pv.debug(14 downto 12) := "111";
end case;
case pr.t.fstate is
when ptf_idle => pv.debug(11 downto 8) := "0000";
when ptf_fifo => pv.debug(11 downto 8) := "0001";
when ptf_cwrite => pv.debug(11 downto 8) := "0010";
when ptf_write => pv.debug(11 downto 8) := "0011";
when others => pv.debug(11 downto 8) := "1111";
end case;
case pr.m.state is
when pm_idle => pv.debug(7 downto 4) := "0000";
when pm_addr => pv.debug(7 downto 4) := "0001";
when pm_m_data => pv.debug(7 downto 4) := "0010";
when pm_turn_ar => pv.debug(7 downto 4) := "0011";
when pm_s_tar => pv.debug(7 downto 4) := "0100";
when pm_dr_bus => pv.debug(7 downto 4) := "0101";
when others => pv.debug(7 downto 4) := "1111";
end case;
case pr.m.fstate is
when pmf_idle => pv.debug(3 downto 0) := "0000";
when pmf_fifo => pv.debug(3 downto 0) := "0001";
when pmf_read => pv.debug(3 downto 0) := "0010";
when others => pv.debug(3 downto 0) := "1111";
end case;
debugo <= (others => '0');
-- --------------------------------------------------------------------------------
-- PCI reset
-- --------------------------------------------------------------------------------
-- PCI master
lpcim_rst <= pcirst(0) and not pci_master_rst and not pci_hard_rst;
if lpcim_rst = '0' then
-- state
pv.m.fstate := pmf_idle;
for i in 0 to 2 loop
pv.m.cfifo(i).last := '0';
pv.m.cfifo(i).stlast := '0';
pv.m.cfifo(i).hold := '0';
pv.m.cfifo(i).valid := '0';
pv.m.cfifo(i).err := '0';
end loop;
-- core
pv.m.devsel_asserted := '1';
pv.m.abort := (others => '0');
pv.m.hold := (others => '0');
pv.m.hold_fifo := '0';
pv.m.term := (others => '0');
pv.m.acc_cnt := 0;
pv.m.acc_switch := '0';
for i in 0 to 1 loop
pv.m.acc(i).pending := '0';
pv.m.acc(i).active := (others => '0');
pv.m.acc(i).fifo_index := 0;
end loop;
pv.m.fifo_addr := (others => '0');
pv.m.addr := (others => '0'); -- X-prop fix
-- trans
for i in 0 to 1 loop
pv.pta_trans.msd_acc_ack(i) := '0';
pv.pta_trans.msd_acc_cancel_ack(i) := (others => '0');
pv.pta_trans.msd_acc_done(i).done := '0';
for j in 0 to FIFO_COUNT-1 loop
pv.pta_trans.msd_fifo(i)(j).pending := (others => '0');
end loop;
pv.pta_trans.msd_fifo_ack(i) := (others => '0');
end loop;
end if;
-- PCI target
lpcit_rst <= pcirst(0) and not pci_target_rst and not pci_hard_rst;
if lpcit_rst = '0' then
-- state
pv.t.fstate := ptf_idle;
for i in 0 to 2 loop
pv.t.cfifo(i).last := '0';
pv.t.cfifo(i).stlast := '0';
pv.t.cfifo(i).hold := '0';
pv.t.cfifo(i).valid := '0';
pv.t.cfifo(i).err := '0';
end loop;
pv.t.cfifo(0).data := (others => '0'); -- X-prop fix
pv.t.cfifo(1).data := (others => '0'); -- X-prop fix
pv.t.atp.ctrl.addr := (others => '0'); -- X-prop fix
pv.t.cur_acc(0).addr(31) := '0'; -- X-prop fix
-- core
pv.t.discardtimeren := '1';
pv.t.hold := (others => '0');
pv.t.hold_fifo := '0';
pv.t.stop := '0';
pv.t.addr_perr := '0';
pv.t.cur_acc(0).pending := '0';
pv.t.cur_acc(0).continue := '0';
pv.t.cur_acc(0).read := '0';
pv.t.cur_acc(0).impcfgreg := '1';
pv.t.atp.index := 0;
pv.t.pta.index := 0;
pv.t.blenmask := (others => '0');
pv.t.blenmask(blenmask_size(barminsize) downto 0) := (others => '1');
pv.t.saverfifo := '0';
for i in 0 to 3 loop
pv.t.accbuf(i).pending := '0';
end loop;
-- trans
for i in 0 to FIFO_COUNT-1 loop
pv.pta_trans.tm_fifo(i).pending := (others => '0');
end loop;
pv.pta_trans.tm_fifo_ack := (others => '0');
pv.pta_trans.tm_acc.pending := '0';
pv.pta_trans.tm_acc_cancel := '0';
pv.pta_trans.tm_acc_done_ack := '0';
end if;
-- PCI reset
lpci_rst <= pcirst(0) and not pci_hard_rst;
if lpci_rst = '0' then
-- Master state
pv.m.state := pm_idle;
-- Target state
pv.t.state := pt_idle;
-- PCI signals
pv.po.frame := '1'; pv.po.irdy := '1'; pv.po.req := '1';
pv.po.trdy := '1'; pv.po.stop := '1';
pv.po.perr := '1'; pv.po.devsel := '1';
-- PCI system
pv.pta_trans.pa_serr := '1';
pv.pta_trans.pa_discardtout := '0';
-- Configuration space
for j in 0 to multifunc loop
pv.conf(j).comm.ioen := '0';
pv.conf(j).comm.memen := '0';
pv.conf(j).comm.msten := '0';
pv.conf(j).comm.mwien := '0';
pv.conf(j).comm.perren := '0';
pv.conf(j).comm.serren := '0';
pv.conf(j).comm.intdis := '0';
pv.conf(j).stat.intsta := '0';
pv.conf(j).stat.mdpe := '0';
pv.conf(j).stat.sta := '0';
pv.conf(j).stat.rta := '0';
pv.conf(j).stat.rma := '0';
pv.conf(j).stat.sse := '0';
pv.conf(j).stat.dpe := '0';
--pv.conf.clsize := (others => '0');
pv.conf(j).ltimer := (others => '0');
pv.conf(j).iline := (others => '0');
for i in 0 to 5 loop
pv.conf(j).bar(i) := (others => '0');
pv.conf(j).pta_map(i) := default_bar_map(j)(i);
pv.conf(j).bar_mask(i) := (others => '0');
pv.conf(j).bar_mask(i)(31 downto bar_size(j)(i)) := ones32(31 downto bar_size(j)(i));
pv.conf(j).bar_mask(i)(3) := bar_prefetch(j)(i);
pv.conf(j).bar_mask(i)(0) := bar_io(j)(i);
if bar_size(j)(i) <= 1 then pv.conf(j).bar_mask(i) := (others => '0'); end if;
end loop;
pv.conf(j).cfg_map := conv_std_logic_vector(extcfg_vector(j),28) & "0000";
end loop;
pv.pta_trans.ca_pcimsten := (others => '0');
pv.pta_trans.ca_twist := conv_std_logic_vector(conv_endian, 1)(0);
-- PCI trace
pv.ptta_trans.enable := '0';
pv.ptta_trans.armed := '0';
pv.ptta_trans.start_ack := '0';
pv.ptta_trans.stop_ack := '0';
pv.pt.addr := (others => '0');
end if;
if pcirst(0) = '0' then
pv.pta_trans.rst_ack := (others => '0');
end if;
-- Disabled parts
if target = 0 then -- PCI targer disabled
pv.t := pci_target_none;
pv.pta_trans.tm_acc := pci_g_acc_trans_none;
pv.pta_trans.tm_acc_cancel := '0';
pv.pta_trans.tm_acc_done_ack := '0';
pv.pta_trans.tm_fifo := pci_g_fifo_trans_vector_none;
pv.pta_trans.tm_fifo_ack := pci_g_fifo_ack_trans_vector_none;
pv.po.trdy := '1'; pv.po.trdyen := oeoff; pv.po.stop := '1'; pv.po.stopen := oeoff;
pv.po.devsel := '1'; pv.po.devsel := oeoff;
for j in 0 to multifunc loop
pv.conf(j).comm.memen := '0';
pv.conf(j).stat.sta := '0';
for i in 0 to 5 loop
pv.conf(j).bar(i) := (others => '0');
end loop;
if master /= 0 and confspace = 0 then -- No Configuration Space but PCI master => master enabled
pv.conf(j).comm.msten := '1'; pv.pta_trans.ca_pcimsten := (others => '1');
end if;
end loop;
end if;
if master = 0 and dma = 0 then -- PCI master disabled
pv.m := pci_master_none;
pv.pta_trans.msd_acc_ack(0) := '0';
pv.pta_trans.msd_acc_cancel_ack(0) := (others => '0');
pv.pta_trans.msd_acc_done(0) := pci_g_acc_status_trans_none;
pv.pta_trans.msd_fifo(0) := pci_g_fifo_trans_vector_none;
pv.pta_trans.msd_fifo_ack(0) := pci_g_fifo_ack_trans_vector_none;
pv.po.irdy := '1'; pv.po.irdyen := oeoff; pv.po.frame := '1'; pv.po.frameen := oeoff;
pv.po.req := '1'; pv.po.reqen := oeoff;
pv.po.cbe := (others => '0'); pv.po.cbeen := (others => oeoff);
for j in 0 to multifunc loop
pv.conf(j).comm.msten := '0'; pv.pta_trans.ca_pcimsten := (others => '0');
pv.conf(j).comm.mwien := '0';
pv.conf(j).stat.mdpe := '0';
pv.conf(j).stat.rta := '0';
pv.conf(j).stat.rma := '0';
end loop;
end if;
if dma = 0 then -- DMA disabled
pv.m.acc(1) := pci_master_acc_none;
pv.pta_trans.msd_acc_ack(1) := '0';
pv.pta_trans.msd_acc_cancel_ack(1) := (others => '0');
pv.pta_trans.msd_acc_done(1) := pci_g_acc_status_trans_none;
pv.pta_trans.msd_fifo(1) := pci_g_fifo_trans_vector_none;
pv.pta_trans.msd_fifo_ack(1) := pci_g_fifo_ack_trans_vector_none;
end if;
if tracebuffer = 0 then -- PCI trace buffer disabled
pv.pt := pci_trace_none;
pv.ptta_trans := pci_trace_to_apb_trans_none;
end if;
if dma = 0 and master = 0 and target = 0 then
pv.po.par := '1'; pv.po.paren := oeoff; pv.po.perr := '1'; pv.po.perren := oeoff;
pv.po.serren := oeoff; pv.po.inten := oeoff; pv.po.vinten := (others => oeoff);
pv.po.ad := (others => '0'); pv.po.aden := (others => oeoff);
for j in 0 to multifunc loop
pv.conf(j).stat.sse := '0';
pv.conf(j).stat.dpe := '0';
pv.conf(j).comm.perren := '0';
pv.conf(j).comm.serren := '0';
end loop;
end if;
-- --------------
prin <= pv;
-- PHY =>
sig_m_request <= m_request;
sig_m_mabort <= m_mabort;
sig_t_abort <= t_abort;
sig_t_ready <= t_ready;
sig_t_retry <= t_retry;
sig_soft_rst <= pci_hard_rst & pci_master_rst & pci_target_rst;
all_func_serren := '0';
for j in 0 to multifunc loop
all_func_serren := all_func_serren or pr.conf(j).comm.serren;
end loop;
sig_pr_conf_comm_serren <= all_func_serren;
if pr.m.perren /= "00" then
sig_pr_conf_comm_perren <= pr.conf(pr.m.acc(pr.m.acc_sel).func).comm.perren;
else
sig_pr_conf_comm_perren <= pr.conf(pr.t.cur_acc(0).func).comm.perren;
end if;
-- PHY <=
-- Gate PCI target => AHB master pending with pcirst
pr_pta_trans_gated <= pr.pta_trans;
pr_pta_trans_gated.tm_acc.pending <= pr.pta_trans.tm_acc.pending and pciasyncrst_comb;
end process;
acomb : process(ar, rst, pr_pta_trans_gated, dmao0, dmao1, tm_fifoo_pta, ms_fifoo_pta, md_fifoo_ptd, ahbsi, apbi, dirq, pcii.int, pt_fifoo_ad, pt_fifoo_sig, pr.ptta_trans, pcisig, lahbm_rst, lahbs_rst, lahb_rst, iotmact)
variable av : amba_reg_type;
variable pta_trans: pci_to_ahb_trans_type;
variable first : std_logic;
variable tm_nindex : integer range 0 to FIFO_COUNT-1;-- FIFO index
variable tm_acc : pci_g_acc_trans_type;
variable tm_acc_pending : std_logic;
variable tm_acc_done : std_logic;
variable tm_acc_cancel : std_logic;
variable tm_fifo_pending : std_logic_vector(FIFO_COUNT-1 downto 0);
variable tm_fifo_empty : std_logic_vector(FIFO_COUNT-1 downto 0);
variable tm_fifo : pci_g_fifo_trans_vector_type;
-- AHB slave
variable slv_access : std_logic;
variable tb_access : std_logic;
variable ms_index : integer range 0 to FIFO_COUNT-1;-- FIFO index
variable blen : std_logic_vector(15 downto 0);
variable ms_acc_pending : std_logic;
variable ms_acc_cancel : std_logic;
variable ms_acc_done : std_logic;
variable ms_acc_done_status : pci_g_acc_status_trans_type;
variable ms_fifo_pending : std_logic_vector(FIFO_COUNT-1 downto 0);
variable ms_fifo_empty : std_logic_vector(FIFO_COUNT-1 downto 0);
variable ms_fifo : pci_g_fifo_trans_vector_type;
variable accbufindex : integer range 0 to 3;
variable ms_func : std_logic_vector(2 downto 0);
variable ms_vifunc : integer range 0 to multifunc;
-- APB slave
variable apbaddr : std_logic_vector(6 downto 2);
variable prdata : std_logic_vector(31 downto 0);
variable pirq : std_logic_vector(NAHBIRQ-1 downto 0);
variable c_blenmask_update : std_logic;
variable ptta_trans : pci_trace_to_apb_trans_type;
variable pt_status : pci_trace_to_apb_trans_type;
-- DMA
variable md_index : integer range 0 to FIFO_COUNT-1;-- FIFO index
variable md_acc_pending : std_logic;
variable md_acc_cancel : std_logic;
variable md_acc_done : std_logic;
variable md_acc_done_status : pci_g_acc_status_trans_type;
variable md_fifo_pending : std_logic_vector(FIFO_COUNT-1 downto 0);
variable md_fifo_empty : std_logic_vector(FIFO_COUNT-1 downto 0);
variable md_fifo : pci_g_fifo_trans_vector_type;
-- Soft reset
variable pci_master_rst : std_logic;
variable pci_target_rst : std_logic;
variable pci_hard_rst : std_logic;
-- APB DEBUG
variable tbapbaddr : std_logic_vector(6 downto 2);
variable tbprdata : std_logic_vector(31 downto 0);
variable tbpirq : std_logic_vector(NAHBIRQ-1 downto 0);
begin
-- --------------------------------------------------------------------------------
-- AHB global defaults
-- --------------------------------------------------------------------------------
-- defaults
av := ar;
av.irq.access_pirq := '0';
av.irq.system_pirq := '0';
-- FIFO and AHB<=>PCI sync
av.sync(1) := pr_pta_trans_gated; av.sync(2) := ar.sync(1);
if nsync = 0 then pta_trans := pr_pta_trans_gated;
else pta_trans := ar.sync(nsync); end if;
-- PCI trace <=> APB sync
av.apb_sync(1) := pr.ptta_trans; av.apb_sync(2) := ar.apb_sync(1);
if nsync = 0 then ptta_trans := pr.ptta_trans;
else ptta_trans := ar.apb_sync(nsync); end if;
pt_status := pr.ptta_trans;
if tracebuffer = 0 then -- PCI trace buffer disabled
av.atpt_trans.start := '0'; av.atpt_trans.stop := '0'; av.atpt_trans.mode := (others => '0');
av.atpt_trans.count := (others => '0'); av.atpt_trans.tcount := (others => '0');
av.atpt_trans.ad := (others => '0'); av.atpt_trans.admask := (others => '0');
av.atpt_trans.sig := (others => '0'); av.atpt_trans.sigmask := (others => '0');
else
if ptta_trans.start_ack = '1' then av.atpt_trans.start := '0'; end if;
if ptta_trans.stop_ack = '1' then av.atpt_trans.stop := '0'; end if;
end if;
-- Soft reset
if pta_trans.rst_ack(0) = '1' then av.atp_trans.rst(0) := '0'; end if; -- PCI-target/AHB-master reset
if pta_trans.rst_ack(1) = '1' then av.atp_trans.rst(1) := '0'; end if; -- PCI-master/AHB-slave reset
pci_target_rst := pta_trans.rst_ack(0) or ar.atp_trans.rst(0);
pci_master_rst := pta_trans.rst_ack(1) or ar.atp_trans.rst(1);
pci_hard_rst := ar.atp_trans.rst(2);
-- --------------------------------------------------------------------------------
-- AHB master defaults
-- --------------------------------------------------------------------------------
-- FIFO enable(read)/write
av.m.acc.fifo_ren := '0';
av.m.acc.fifo_wen := '0';
av.m.acc.fifo_wdata := dmao0.data;
av.m.dmai0.noreq := '0';
tm_acc_pending := pta_trans.tm_acc.pending xor ar.atp_trans.tm_acc_ack;
tm_acc_done := pta_trans.tm_acc_done_ack xor ar.atp_trans.tm_acc_done.done;
tm_acc_cancel := pta_trans.tm_acc_cancel xor ar.atp_trans.tm_acc_cancel_ack(0);
-- Stop_ack also needs to be delayed when pending is delayed
av.atp_trans.tm_acc_cancel_ack(1) := ar.atp_trans.tm_acc_cancel_ack(0);
av.atp_trans.tm_acc_cancel_ack(2) := ar.atp_trans.tm_acc_cancel_ack(1);
for i in 0 to FIFO_COUNT-1 loop
tm_fifo_pending(i) := pta_trans.tm_fifo(i).pending(RAM_LATENCY) xor ar.atp_trans.tm_fifo_ack(i);
tm_fifo_empty(i) := not (ar.atp_trans.tm_fifo(i).pending(0) xor pta_trans.tm_fifo_ack(i));
-- To set pending when data is stored in fifo, with this stop_ack also needs to be delayed
av.atp_trans.tm_fifo(i).pending(1) := ar.atp_trans.tm_fifo(i).pending(0);
av.atp_trans.tm_fifo(i).pending(2) := ar.atp_trans.tm_fifo(i).pending(1);
end loop;
tm_fifo := pr_pta_trans_gated.tm_fifo;
tm_acc := pr_pta_trans_gated.tm_acc;
-- --------------------------------------------------------------------------------
-- AHB master core
-- --------------------------------------------------------------------------------
if target /= 0 then -- PCI target enabled
-- Select next fifo
if ar.m.acc.fifo_index /= FIFO_COUNT-1 then tm_nindex := ar.m.acc.fifo_index + 1;
else tm_nindex := 0; end if;
-- latch PCI target access
if tm_acc_pending = '1' and ar.m.acc.pending = '0' then
av.atp_trans.tm_acc_ack := pta_trans.tm_acc.pending;
av.m.acc.pending := '1';
av.m.acc.addr := tm_acc.addr;
av.m.acc.mode := tm_acc.accmode;
av.m.acc.burst := tm_acc.accmode(0);
av.m.acc.cbe := tm_acc.cbe;
av.m.acc.endianess := tm_acc.endianess;
av.m.acc.length := tm_acc.length;
av.m.acc.fifo_index := tm_acc.index;
av.m.acc.acctype := tm_acc.acctype;
end if;
-- AHB master state machine
case ar.m.state is
when am_idle =>
av.m.done := (others => '0');
av.m.stop := '0';
av.m.dmai0.req := '0';
av.m.dmai0.burst := '1';
av.m.dma_hold := '0';
av.m.active := '0';
av.m.retry := '0';
if ar.m.acc.pending = '1' then
av.m.dmai0.addr := ar.m.acc.addr;
av.m.dmai0.size := set_size_from_cbe(ar.m.acc.cbe);
av.m.dmai0.addr(1 downto 0) := set_addr_from_cbe(ar.m.acc.cbe, ar.m.acc.endianess);
-- Burst length (only burst up to this boundary)
av.m.blen := ar.m.acc.length;
if ar.m.acc.acctype(0) = '1' then -- Write
av.m.state := am_write;
av.m.first := "010";
av.m.hold := (others => '1');
elsif ar.m.acc.acctype(0) = '0' then -- Read
av.m.state := am_read;
av.m.first := "001";
av.m.hold := (others => '0');
av.m.dmai0.write := '0';
av.m.dmai0.req := '1';
av.m.acc.fifo_addr := conv_std_logic_vector(ar.m.acc.fifo_index, log2(FIFO_COUNT)) & ar.m.acc.addr(AHB_FIFO_BITS); -- Set fifo start address
av.m.faddr := av.m.acc.addr(AHB_FIFO_BITS);
if ar.m.acc.burst = '0' then
av.m.dmai0.size := set_size_from_cbe(ar.m.acc.cbe);
av.m.dmai0.addr(1 downto 0) := set_addr_from_cbe(ar.m.acc.cbe, ar.m.acc.endianess);
av.m.dmai0.burst := '0'; -- sinlge access
else
av.m.dmai0.size := "10";
av.m.dmai0.addr(1 downto 0) := "00";
end if;
end if;
end if;
if tm_acc_cancel = '1' then
av.atp_trans.tm_acc_cancel_ack(0) := pta_trans.tm_acc_cancel;
end if;
when am_read =>
if tm_fifo_empty(ar.m.acc.fifo_index) = '1' and ar.m.hold(0) = '1' and ar.m.done(0) = '0' and ar.m.active = '0' then
av.m.dmai0.req := '1';
av.m.hold := (others => '0');
end if;
if tm_acc_cancel = '1' then
av.m.done(2) := '1';
end if;
if dmao0.grant = '1' then
av.m.active := '1';
av.m.dmai0.addr := ar.m.dmai0.addr + 4;
if ar.m.blen /= zero32(15 downto 0) then
av.m.blen := ar.m.blen - 1;
end if;
if ar.m.dmai0.addr(AHB_FIFO_BITS) = ones32(AHB_FIFO_BITS) or ar.m.done(2) = '1' or ar.m.acc.burst = '0' then
if tm_fifo_empty(tm_nindex) = '0' then
av.m.dmai0.req := '0';
av.m.hold(0) := '1';
end if;
if ar.m.done(2) = '1' or ar.m.acc.burst = '0' or ar.m.blen = zero32(15 downto 0) then
av.m.dmai0.req := '0';
av.m.done(1) := '1';
end if;
end if;
-- Retry save & restore
av.m.retry := '0';
-- Save len for retry
av.m.retry_blen := ar.m.blen;
-- Restore len for retry
if ar.m.retry = '1' then
av.m.blen := ar.m.retry_blen;
end if;
elsif dmao0.retry = '1' then
av.m.dmai0.req := '1';
av.m.dmai0.addr := ar.m.dmai0.addr - 4;
--av.m.blen := ar.m.blen + 1;
av.m.done(1) := '0';
-- Retry save & restore
av.m.retry := '1';
-- Save len for retry
av.m.retry_blen := ar.m.blen;
-- Restore len for retry
av.m.blen := ar.m.retry_blen;
end if;
if dmao0.ready = '1' then
if dmao0.grant = '0' then av.m.active := '0'; end if;
if ar.m.faddr(AHB_FIFO_BITS) /= ones32(AHB_FIFO_BITS) and ar.m.done(1) = '0' then
av.m.faddr(AHB_FIFO_BITS) := ar.m.faddr(AHB_FIFO_BITS) + 1;
else -- Last word in fifo
av.m.faddr(AHB_FIFO_BITS) := (others => '0');
av.m.acc.fifo_index := tm_nindex; -- Go to next fifo
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).pending(0) := not ar.atp_trans.tm_fifo(ar.m.acc.fifo_index).pending(0);
if ar.m.first(0) = '1' then -- Mark first fifo in transfer
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).firstf := '1';
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).start := ar.m.acc.addr(AHB_FIFO_BITS);
av.m.first(0) := '0';
else
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).start := (others => '0');
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).firstf := '0';
end if;
if ar.m.done(1) = '1' then -- Mark last fifo in transfer
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).lastf := '1';
av.m.done(0) := '1';
else
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).lastf := '0';
end if;
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).stop := ar.m.faddr(AHB_FIFO_BITS);
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).status := (others => '0'); -- Not used
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).last_cbe := (others => '0'); -- Not used
end if;
av.m.acc.fifo_wen := '1';
av.m.acc.fifo_addr := conv_std_logic_vector(ar.m.acc.fifo_index, log2(FIFO_COUNT)) & ar.m.faddr(AHB_FIFO_BITS);
elsif dmao0.error = '1' then
av.m.active := '0';
av.m.dmai0.req := '0';
av.m.done(0) := '1';
av.m.acc.fifo_index := tm_nindex; -- Go to next fifo
if ar.m.first(0) = '1' then -- Mark first fifo in transfer
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).firstf := '1';
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).start := ar.m.acc.addr(AHB_FIFO_BITS);
av.m.first(0) := '0';
else
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).firstf := '0';
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).start := (others => '0');
end if;
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).lastf := '1';
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).stop := ar.m.faddr(AHB_FIFO_BITS);
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).pending(0) := not ar.atp_trans.tm_fifo(ar.m.acc.fifo_index).pending(0);
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).status(0) := '1'; -- AHB error
av.m.acc.fifo_wen := '1';
av.m.acc.fifo_addr := conv_std_logic_vector(ar.m.acc.fifo_index, log2(FIFO_COUNT)) & ar.m.faddr(AHB_FIFO_BITS);
end if;
-- to deassert req on last address phase
if av.m.dmai0.addr(AHB_FIFO_BITS) = ones32(AHB_FIFO_BITS) then av.m.dmai0.noreq := '1'; end if;
if ar.m.done(2) = '1' and ar.m.active = '0' and dmao0.grant = '0' then
av.m.dmai0.req := '0';
av.m.done := (others => '1');
end if;
if ar.m.done(0) = '1' then
av.m.dmai0.req := '0';
if ar.m.done(2) = '1' or ar.m.acc.burst = '0' then
if ar.m.done(2) = '1' then
for i in 0 to FIFO_COUNT-1 loop
if tm_fifo_empty(i) = '0' then
av.atp_trans.tm_fifo(i).pending(0) := not ar.atp_trans.tm_fifo(i).pending(0);
else
av.atp_trans.tm_fifo(i).pending(0) := ar.atp_trans.tm_fifo(i).pending(0);
end if;
end loop;
end if;
av.m.state := am_idle;
av.m.acc.pending := '0';
end if;
end if;
when am_write =>
av.m.acc.fifo_ren := tm_fifo_pending(ar.m.acc.fifo_index);
av.m.dmai0.write := '1';
av.m.first(0) := '0';
if tm_fifo_pending(ar.m.acc.fifo_index) = '1' and ar.m.hold(0) = '1' and ar.m.active = '0' and ar.m.done(0) = '0' and ar.m.first(2) = '0' then
av.m.first(0) := '1';
av.m.first(2) := '1';
av.m.hold := "000";
av.m.last := "000";
av.m.acc.fifo_addr := conv_std_logic_vector(ar.m.acc.fifo_index, log2(FIFO_COUNT)) & tm_fifo(ar.m.acc.fifo_index).start; -- Set fifo start address
av.m.faddr := tm_fifo(ar.m.acc.fifo_index).start; -- Set fifo start address
if ar.m.first(1) = '1' then
av.m.first(1) := '0';
end if;
-- Last access is non-word or first/last is no-data
if tm_fifo(ar.m.acc.fifo_index).start = tm_fifo(ar.m.acc.fifo_index).stop then
if ar.m.acc.cbe = ones32(3 downto 0) then
av.m.done(0) := '1';
av.m.first(0) := '0';
av.m.dmai0.req := '0';
av.m.acc.fifo_index := tm_nindex; -- Go to next fifo
av.atp_trans.tm_fifo_ack(ar.m.acc.fifo_index) := pta_trans.tm_fifo(ar.m.acc.fifo_index).pending(RAM_LATENCY);
elsif tm_fifo(ar.m.acc.fifo_index).last_cbe /= ar.m.acc.cbe then
av.m.dmai0.size := set_size_from_cbe(tm_fifo(ar.m.acc.fifo_index).last_cbe);
av.m.dmai0.addr(1 downto 0) := set_addr_from_cbe(tm_fifo(ar.m.acc.fifo_index).last_cbe, ar.m.acc.endianess);
av.m.dmai0.burst := '0';
end if;
elsif ar.m.acc.cbe = ones32(3 downto 0) then
av.m.dmai0.addr := ar.m.dmai0.addr + 4;
av.m.acc.fifo_addr := conv_std_logic_vector(ar.m.acc.fifo_index, log2(FIFO_COUNT)) & (tm_fifo(ar.m.acc.fifo_index).start + 1); -- Set fifo start address
av.m.faddr := (tm_fifo(ar.m.acc.fifo_index).start + 1); -- Set fifo start address
end if;
end if;
if ar.m.first(0) = '1' then -- Latch first word in fifo
av.m.dmai0.req := '1';
if ar.m.acc.fifo_addr(FIFO_DEPTH-1 downto 0) /= tm_fifo(ar.m.acc.fifo_index).stop then
av.m.acc.fifo_addr(FIFO_DEPTH-1 downto 0) := ar.m.acc.fifo_addr(FIFO_DEPTH-1 downto 0) + 1;
else
av.m.hold(0) := '1';
if tm_fifo(ar.m.acc.fifo_index).lastf = '1' then
av.m.last(0) := '1';
if tm_fifo(ar.m.acc.fifo_index).status /= "0000" then
av.m.done(0) := '1';
av.m.dmai0.req := '0';
av.m.acc.fifo_index := tm_nindex; -- Go to next fifo
av.atp_trans.tm_fifo_ack(ar.m.acc.fifo_index) := pta_trans.tm_fifo(ar.m.acc.fifo_index).pending(RAM_LATENCY);
end if;
end if;
end if;
av.m.dmai0.data := tm_fifoo_pta.data;
end if;
if dmao0.grant = '1' then
av.m.active := '1';
av.m.dmai0.addr := ar.m.dmai0.addr + 4;
av.m.faddr := ar.m.faddr + 1;
av.m.retry := '0';
if (ar.m.active = '1' and ar.m.faddr = tm_fifo(ar.m.acc.fifo_index).stop) or ar.m.hold(1 downto 0) /= "00" or ar.m.done(0) = '1' then
if (ar.m.active = '1' and (tm_fifo_pending(tm_nindex) = '0' or tm_fifo(ar.m.acc.fifo_index).lastf = '1')) or ar.m.hold(1 downto 0) /= "00" or ar.m.done(0) = '1' then
av.m.dmai0.req := '0';
av.m.hold(0) := '1';
if tm_fifo(ar.m.acc.fifo_index).lastf = '1' then av.m.last(0) := '1'; end if;
end if;
if tm_fifo_pending(tm_nindex) = '1' then
if tm_fifo(tm_nindex).start = tm_fifo(tm_nindex).stop and tm_fifo(tm_nindex).last_cbe = ones32(3 downto 0) then
av.m.dmai0.req := '0';
av.m.hold(0) := '1';
end if;
end if;
end if;
-- Last access is non-word
if av.m.faddr(AHB_FIFO_BITS) = tm_fifo(ar.m.acc.fifo_index).stop and tm_fifo(ar.m.acc.fifo_index).last_cbe /= ar.m.acc.cbe then
av.m.dmai0.size := set_size_from_cbe(tm_fifo(ar.m.acc.fifo_index).last_cbe);
av.m.dmai0.addr(1 downto 0) := set_addr_from_cbe(tm_fifo(ar.m.acc.fifo_index).last_cbe, ar.m.acc.endianess);
av.m.dmai0.burst := '0';
elsif (tm_fifo(ar.m.acc.fifo_index).lastf = '0' and tm_fifo_pending(tm_nindex) = '1' and
av.m.faddr(AHB_FIFO_BITS) = zero32(AHB_FIFO_BITS) and tm_fifo(tm_nindex).stop = zero32(AHB_FIFO_BITS) and
tm_fifo(tm_nindex).last_cbe /= ar.m.acc.cbe) then
av.m.dmai0.size := set_size_from_cbe(tm_fifo(tm_nindex).last_cbe);
av.m.dmai0.addr(1 downto 0) := set_addr_from_cbe(tm_fifo(tm_nindex).last_cbe, ar.m.acc.endianess);
av.m.dmai0.burst := '0';
end if;
-- Save size and offset for retry
av.m.retry_size := ar.m.dmai0.size;
av.m.retry_offset := ar.m.dmai0.addr(1 downto 0);
-- Restore size and offset for retry
if ar.m.retry = '1' then
av.m.dmai0.size := ar.m.retry_size;
av.m.dmai0.addr(1 downto 0) := ar.m.retry_offset;
end if;
elsif dmao0.retry = '1' then
av.m.dmai0.req := '1';
av.m.dmai0.addr := ar.m.dmai0.addr - 4;
av.m.faddr := ar.m.faddr - 1;
av.m.retry := '1';
-- Save size and offset for retry
av.m.retry_size := ar.m.dmai0.size;
av.m.retry_offset := ar.m.dmai0.addr(1 downto 0);
-- Restore size and offset for retry
av.m.dmai0.size := ar.m.retry_size;
av.m.dmai0.addr(1 downto 0) := ar.m.retry_offset;
end if;
if dmao0.ready = '1' then
av.m.first(2) := '0';
if dmao0.grant = '0' and ar.m.dmai0.req = '0' then av.m.active := '0'; end if;
if ar.m.hold(1 downto 0) = "00" then
av.m.dmai0.data := tm_fifoo_pta.data;
av.m.acc.fifo_addr(FIFO_DEPTH-1 downto 0) := ar.m.acc.fifo_addr(FIFO_DEPTH-1 downto 0) + 1;
end if;
if tm_fifo_pending(ar.m.acc.fifo_index) = '1' and ar.m.acc.fifo_addr(FIFO_DEPTH-1 downto 0) = tm_fifo(ar.m.acc.fifo_index).stop and
ar.m.hold(1 downto 0) /= "11" and ar.m.done(0) = '0' then
av.m.acc.fifo_index := tm_nindex; -- Go to next fifo
av.atp_trans.tm_fifo_ack(ar.m.acc.fifo_index) := pta_trans.tm_fifo(ar.m.acc.fifo_index).pending(RAM_LATENCY);
av.m.acc.fifo_addr := conv_std_logic_vector(av.m.acc.fifo_index, log2(FIFO_COUNT)) & tm_fifo(tm_nindex).start; -- Set fifo start address
if tm_fifo_pending(tm_nindex) = '0' or ar.m.hold(0) = '1' then
av.m.hold(1) := '1';
end if;
if tm_fifo(ar.m.acc.fifo_index).lastf = '1' or ar.m.last(1 downto 0) /= "00" then -- Transfer done
av.m.done(0) := '1';
end if;
end if;
elsif dmao0.error = '1' then
av.m.active := '0';
av.m.dmai0.req := '0';
if ar.m.done(0) = '0' then
if tm_fifo_pending(ar.m.acc.fifo_index) = '1' and tm_fifo(ar.m.acc.fifo_index).lastf = '1' then
av.m.acc.fifo_index := tm_nindex; -- Go to next fifo
av.atp_trans.tm_fifo_ack(ar.m.acc.fifo_index) := pta_trans.tm_fifo(ar.m.acc.fifo_index).pending(RAM_LATENCY);
av.m.done(0) := '1';
else
av.m.state := am_error;
end if;
end if;
end if;
if ar.m.done(0) = '1' and ar.m.active = '0' then
av.m.state := am_idle;
av.m.acc.pending := '0';
end if;
if av.m.dmai0.addr(AHB_FIFO_BITS) = tm_fifo(ar.m.acc.fifo_index).stop or ar.m.done(0) = '1' then av.m.dmai0.noreq := '1'; end if; -- to deassert req on last address phase
when am_error =>
if tm_fifo_pending(ar.m.acc.fifo_index) = '1' and ar.m.done(0) = '0' then
if tm_fifo(ar.m.acc.fifo_index).lastf = '1' then
av.m.done(0) := '1';
end if;
av.m.acc.fifo_index := tm_nindex; -- Go to next fifo
av.atp_trans.tm_fifo_ack(ar.m.acc.fifo_index) := pta_trans.tm_fifo(ar.m.acc.fifo_index).pending(RAM_LATENCY);
end if;
if ar.m.done(0) = '1' then
av.m.state := am_idle;
av.m.acc.pending := '0';
end if;
when others =>
end case;
end if; -- PCI target enabled
-- --------------------------------------------------------------------------------
-- AHB slave defaults
-- --------------------------------------------------------------------------------
-- Default
av.s.hready := '1'; slv_access := '0'; tb_access := '0'; av.s.hresp := HRESP_OKAY;
av.s.retry := '0';
av.s.atp.ctrl.en := '0';
av.s.atp.ctrl.data := ahbreadword(ahbsi.hwdata);
av.s.pta.ctrl.en := '0';
av.s.stoppciacc := '0';
ms_acc_pending := ar.atp_trans.msd_acc(0).pending xor pta_trans.msd_acc_ack(0);
ms_acc_cancel := ar.atp_trans.msd_acc_cancel(0) xor pta_trans.msd_acc_cancel_ack(0)(RAM_LATENCY);
ms_acc_done := ar.atp_trans.msd_acc_done_ack(0) xor pta_trans.msd_acc_done(0).done;
for i in 0 to FIFO_COUNT-1 loop
ms_fifo_pending(i) := pta_trans.msd_fifo(0)(i).pending(RAM_LATENCY) xor ar.atp_trans.msd_fifo_ack(0)(i);
ms_fifo_empty(i) := not (ar.atp_trans.msd_fifo(0)(i).pending(0) xor pta_trans.msd_fifo_ack(0)(i));
av.atp_trans.msd_fifo(0)(i).pending(1) := ar.atp_trans.msd_fifo(0)(i).pending(0);
av.atp_trans.msd_fifo(0)(i).pending(2) := ar.atp_trans.msd_fifo(0)(i).pending(1);
end loop;
ms_fifo := pr_pta_trans_gated.msd_fifo(0);
ms_acc_done_status := pr_pta_trans_gated.msd_acc_done(0);
accbufindex := 0;
-- PCI function number
ms_func := ar.s.atp_map(conv_integer(ar.s.hmaster))(2 downto 0);
ms_vifunc := conv_integer(ar.s.atp_map(conv_integer(av.s.hmaster))(2 downto 0));
if multifunc = 0 then ms_func := (others => '0'); ms_vifunc := 0; end if;
-- --------------------------------------------------------------------------------
-- AHB slave core
-- --------------------------------------------------------------------------------
if master /= 0 then -- PCI master enabled
if ms_acc_done = '1' then -- Handle PCI error on AHB to PCI write
av.atp_trans.msd_acc_done_ack(0) := pta_trans.msd_acc_done(0).done;
if ms_acc_done_status.status(3) = '1' then -- PCI configuration access done
av.s.cfg_status(1) := '1';
if ms_acc_done_status.status(2 downto 0) /= "000" then av.s.cfg_status(0) := '1'; end if;
else
if ar.irq.access_en = '1' and ms_acc_done_status.status(2 downto 0) /= "000" then av.irq.access_pirq := '1'; end if;
av.irq.access_status := ar.irq.access_status or ms_acc_done_status.status(2 downto 0);
end if;
end if;
-- Select next fifo
if ar.s.state = as_write then
if ar.s.atp.index /= FIFO_COUNT-1 then ms_index := ar.s.atp.index + 1;
else ms_index := 0; end if;
else
if ar.s.pta.index /= FIFO_COUNT-1 then ms_index := ar.s.pta.index + 1;
else ms_index := 0; end if;
end if;
-- Access buffer
if ms_acc_pending = '0' and ar.s.accbuf(0).pending = '1' then
av.atp_trans.msd_acc(0) := ar.s.accbuf(0);
av.atp_trans.msd_acc(0).pending := not ar.atp_trans.msd_acc(0).pending;
av.s.accbuf(0) := ar.s.accbuf(1);
av.s.accbuf(1) := ar.s.accbuf(2);
av.s.accbuf(2) := ar.s.accbuf(3);
av.s.accbuf(3).pending := '0';
end if;
-- Set prefetch burst length
blen := x"00" & ar.s.blen;
-- AHB access latchning
if (ahbsi.hready and ahbsi.hsel(hsindex) and ahbsi.htrans(1)) = '1' then
slv_access := '1';
av.s.haddr := ahbsi.haddr; av.s.hwrite := ahbsi.hwrite;
av.s.hsel := ahbsi.hsel(hsindex); av.s.hmbsel := ahbsi.hmbsel(0 to 2);
av.s.htrans := ahbsi.htrans; av.s.hsize := ahbsi.hsize;
av.s.hburst := ahbsi.hburst(0);
av.s.hmaster := ahbsi.hmaster;
end if;
-- PCI trace buffer access
if tracebuffer /= 0 then
if (ahbsi.hsel(hsindex) and ahbsi.hmbsel(1) and ahbsi.haddr(17) and ahbsi.htrans(1)) = '1' then
tb_access := '1';
end if;
end if;
-- Second retry/error cycle
if ar.s.retry = '1' then
if ar.s.hresp = HRESP_ERROR then
av.s.hresp := HRESP_ERROR;
else
av.s.hresp := HRESP_RETRY;
if ar.s.pending = "00" and ar.s.hwrite = '0' and ar.s.start = '0' and ar.s.stoppciacc = '0' then
av.s.pending := "01";
av.s.addr := ar.s.haddr;
av.s.write := ar.s.hwrite;
av.s.master := ar.s.hmaster;
av.s.burst := ar.s.hburst;
av.s.size := ar.s.hsize;
av.s.config := (not ar.s.hmbsel(0) and ar.s.haddr(16));
av.s.io := (not ar.s.hmbsel(0) and not ar.s.haddr(16));
av.s.pta.ctrl.addr := conv_std_logic_vector(ar.s.pta.index, log2(FIFO_COUNT)) & ar.s.haddr(AHB_FIFO_BITS);
-- Change to sigle access on PCI IO and PCI CONF
if ar.s.io_cfg_burst(0) = '0' and av.s.config = '1' then av.s.burst := '0'; end if;
if ar.s.io_cfg_burst(1) = '0' and av.s.io = '1' then av.s.burst := '0'; end if;
-- Use blen if less than 1k limit and AHB-master is unmasked, else use 1k limit
if (not av.s.addr(9 downto 2)) < ar.s.blen(7 downto 0) or ar.s.blenmask(conv_integer(av.s.master)) = '0' then blen(7 downto 0) := (not av.s.addr(9 downto 2)); end if;
if ar.s.continue = '0' then
if ar.s.hmbsel(0) = '0' then -- config access and io access
if ar.s.haddr(16) = '1' then
av.s.addr := set_pci_conf_addr(ar.s.haddr, ar.s.cfg_bus);
else av.s.addr := set_pci_io_addr(ar.s.haddr, ar.s.io_map); end if;
else
av.s.addr := set_atp_addr(ar.s.haddr, ar.s.atp_map, ar.s.hmaster, AADDR_WIDTH);
end if;
if ms_acc_pending = '0' and ar.s.accbuf(0).pending = '0' then
av.atp_trans.msd_acc(0).pending := not ar.atp_trans.msd_acc(0).pending;
av.atp_trans.msd_acc(0).addr := av.s.addr;
av.atp_trans.msd_acc(0).func := ms_func; -- set PCI function
if av.s.config = '1' then av.atp_trans.msd_acc(0).acctype := CONF_READ;
elsif av.s.io = '1' then av.atp_trans.msd_acc(0).acctype := IO_READ;
else
if av.s.burst = '1' then av.atp_trans.msd_acc(0).acctype := MEM_R_MULT;
else av.atp_trans.msd_acc(0).acctype := MEM_READ; end if;
end if;
av.atp_trans.msd_acc(0).accmode := av.s.burst & '1' & av.s.burst;
av.atp_trans.msd_acc(0).size := av.s.size;
av.atp_trans.msd_acc(0).offset := ar.s.haddr(1 downto 0);
av.atp_trans.msd_acc(0).index := ar.s.pta.index;
av.atp_trans.msd_acc(0).length := blen;
av.atp_trans.msd_acc(0).cbe := (others => '0'); -- not used
av.atp_trans.msd_acc(0).endianess := '0'; -- not used
else
accbufindex := 0;
for i in 3 downto 0 loop
if av.s.accbuf(i).pending = '0' then accbufindex := i; end if;
end loop;
av.s.accbuf(accbufindex).pending := '1';
av.s.accbuf(accbufindex).addr := av.s.addr;
av.s.accbuf(accbufindex).func := ms_func; -- set PCI function
if av.s.config = '1' then av.s.accbuf(accbufindex).acctype := CONF_READ;
elsif av.s.io = '1' then av.s.accbuf(accbufindex).acctype := IO_READ;
else
if av.s.burst = '1' then av.s.accbuf(accbufindex).acctype := MEM_R_MULT;
else av.s.accbuf(accbufindex).acctype := MEM_READ; end if;
end if;
av.s.accbuf(accbufindex).accmode := av.s.burst & '1' & av.s.burst;
av.s.accbuf(accbufindex).size := av.s.size;
av.s.accbuf(accbufindex).offset := ar.s.haddr(1 downto 0);
av.s.accbuf(accbufindex).index := ar.s.pta.index;
av.s.accbuf(accbufindex).length := blen;
av.s.accbuf(accbufindex).cbe := (others => '0'); -- not used
av.s.accbuf(accbufindex).endianess := '0'; -- not used
end if;
end if;
end if;
end if;
end if;
if ms_fifo_pending(ar.s.pta.index) = '1' and ar.s.pending = "01" and ar.s.discard = '0' then
av.s.done_fifo := (others => '0');
av.s.pending := "10";
av.s.pta.ctrl.addr := conv_std_logic_vector(ar.s.pta.index, log2(FIFO_COUNT)) & ar.s.pta.ctrl.addr(FIFO_DEPTH-1 downto 0);
elsif ar.s.pending = "10" then
av.s.pending := "11";
av.s.pta.ctrl.addr := conv_std_logic_vector(ar.s.pta.index, log2(FIFO_COUNT)) & (ar.s.pta.ctrl.addr(FIFO_DEPTH-1 downto 0) + 1);
av.s.hrdata := ms_fifoo_pta.data;
if ms_fifo(ar.s.pta.index).start = ms_fifo(ar.s.pta.index).stop then
av.s.oneword := '1';
av.s.pta.ctrl.addr := conv_std_logic_vector(ar.s.pta.index, log2(FIFO_COUNT)) & ar.s.pta.ctrl.addr(FIFO_DEPTH-1 downto 0);
if ms_fifo_pending(ms_index) = '0' then av.s.done_fifo(0) := '1'; end if;
if ms_fifo(ar.s.pta.index).lastf = '1' then av.s.done_fifo(1) := '1'; end if;
else av.s.oneword := '0'; end if;
end if;
-- FIFO read enable
av.s.pta.ctrl.en := ms_fifo_pending(ar.s.pta.index);
-- Discard unused fifo data
if ar.s.discard = '1' then
if ms_acc_cancel = '0' then
-- moved to PCI master
av.s.discard := '0';
end if;
end if;
-- AHB slave state machine
case ar.s.state is
when as_idle =>
av.s.continue := '0';
av.s.first := '1';
av.s.firstf := '1';
av.s.tb_ren := '0';
if slv_access = '1' then
if tb_access = '1' then -- PCI trace
av.s.hready := '0';
av.s.state := as_pcitrace;
av.s.tb_ren := '1';
else
if av.s.hwrite = '1' and ms_fifo_empty(ar.s.atp.index) = '1' and
pta_trans.ca_pcimsten(ms_vifunc) = '1' and (pci_hard_rst or pci_master_rst) = '0' then -- Write
av.s.state := as_write;
elsif ar.s.pending(1) = '1' and ar.s.master = ahbsi.hmaster and
(pci_hard_rst or pci_master_rst) = '0' then -- Read
if (ms_fifo(ar.s.pta.index).status(2 downto 1) /= "00" and
ms_fifo(ar.s.pta.index).start = ms_fifo(ar.s.pta.index).stop) or -- Master/Target abort
(ms_fifo(ar.s.pta.index).status(0) = '1') then -- PAR error
if ar.s.config = '1' then -- Master/target abort during PCI config access
av.s.state := as_read;
av.s.cfg_status := "11";
else
if ar.s.erren = '1' and ms_fifo(ar.s.pta.index).status(2 downto 1) /= "00" and
ms_fifo(ar.s.pta.index).start = ms_fifo(ar.s.pta.index).stop then
av.s.hready := '0';
av.s.hresp := HRESP_ERROR;
av.s.retry := '1';
end if;
if ar.s.parerren = '1' and ms_fifo(ar.s.pta.index).status(0) = '1' then
av.s.hready := '0';
av.s.hresp := HRESP_ERROR;
av.s.retry := '1';
end if;
if ar.s.burst = '1' then
av.atp_trans.msd_acc_cancel(0) := not ar.atp_trans.msd_acc_cancel(0);
av.s.discard := '1';
else
av.s.pta.index := ms_index; -- Go to next fifo
av.atp_trans.msd_fifo_ack(0)(ar.s.pta.index) := pta_trans.msd_fifo(0)(ar.s.pta.index).pending(RAM_LATENCY);
end if;
av.s.pending := (others => '0');
if ar.irq.access_en = '1' then av.irq.access_pirq := '1'; end if; -- If enabled, generate irq on error
av.irq.access_status := ar.irq.access_status or ms_fifo(ar.s.pta.index).status(2 downto 0); -- Update irq status
end if;
else
if ar.s.config = '1' then av.s.cfg_status(1) := '1'; end if;
av.s.state := as_read;
end if;
elsif ms_fifo_empty(ar.s.atp.index) = '1' and pta_trans.ca_pcimsten(ms_vifunc) = '0' and
(pci_hard_rst or pci_master_rst) = '0' then
av.s.state := as_checkpcimst;
av.s.hready := '0';
elsif (pci_hard_rst or pci_master_rst) = '1' then -- Error during reset
av.s.hresp := HRESP_ERROR;
av.s.hready := '0';
av.s.retry := '1';
else -- Retry
av.s.hresp := HRESP_RETRY;
av.s.hready := '0';
av.s.retry := '1';
end if;
end if;
end if;
when as_checkpcimst =>
if ar.s.hmbsel(0) = '0' and ar.s.haddr(16) = '1' and
((ar.s.haddr(15 downto 11) = zero32(15 downto 11) and pta_trans.ca_host = '0') or ar.s.fakehost = '1') then
if ar.s.hwrite = '1' then
av.s.state := as_write;
else
av.s.hresp := HRESP_RETRY;
av.s.hready := '0';
av.s.retry := '1';
av.s.state := as_idle;
end if;
else
av.s.hresp := HRESP_ERROR;
av.s.hready := '0';
av.s.retry := '1';
av.s.state := as_idle;
end if;
when as_read =>
av.s.pending := (others => '0');
if ar.s.hready = '1' then
if ar.s.htrans(1) = '1' then
if ms_fifo_pending(ar.s.pta.index) = '1' then
if ar.s.pta.ctrl.addr(FIFO_DEPTH-1 downto 0) = ms_fifo(ar.s.pta.index).stop or ar.s.burst = '0' or ar.s.oneword = '1' then
av.s.pta.index := ms_index; -- Go to next fifo
av.atp_trans.msd_fifo_ack(0)(ar.s.pta.index) := pta_trans.msd_fifo(0)(ar.s.pta.index).pending(RAM_LATENCY);
if ms_fifo_pending(ms_index) = '0' then av.s.done_fifo(0) := '1'; end if;
if ms_fifo(ar.s.pta.index).lastf = '1' then av.s.done_fifo(1) := '1'; end if;
end if;
end if;
av.s.hrdata := ms_fifoo_pta.data;
av.s.pta.ctrl.addr := conv_std_logic_vector(av.s.pta.index, log2(FIFO_COUNT)) & (ar.s.pta.ctrl.addr(FIFO_DEPTH-1 downto 0) + 1);
end if;
if ahbsi.htrans(1) = '1' and ahbsi.hsel(hsindex) = '1' then
if ahbsi.htrans(0) = '0' then
if ahbsi.hwrite = '1' and ms_fifo_empty(ar.s.atp.index) = '1' then -- new write access
av.s.state := as_write;
if ar.s.burst = '1' then
av.s.discard := '1';
av.atp_trans.msd_acc_cancel(0) := not ar.atp_trans.msd_acc_cancel(0);
end if;
else -- retry
av.s.hready := '0';
av.s.hresp := HRESP_RETRY;
av.s.retry := '1';
av.s.state := as_idle;
if ar.s.burst = '1' then
av.s.discard := '1';
av.atp_trans.msd_acc_cancel(0) := not ar.atp_trans.msd_acc_cancel(0);
end if;
end if;
end if;
if ms_fifo_pending(ar.s.pta.index) = '1' and
((ms_fifo(ar.s.pta.index).status(2 downto 1) /= "00" and -- Master/Target abort
ar.s.pta.ctrl.addr(FIFO_DEPTH-1 downto 0) = ms_fifo(ar.s.pta.index).stop) or
(ms_fifo(ar.s.pta.index).status(0) = '1')) then -- PAR error
if ar.s.config = '1' then -- No AHB error for PCI Config Space
av.s.cfg_status := "11";
av.s.hready := '0';
av.s.hresp := HRESP_RETRY;
av.s.retry := '1';
else
if ar.s.erren = '1' and ms_fifo(ar.s.pta.index).status(2 downto 1) /= "00" and
ar.s.pta.ctrl.addr(FIFO_DEPTH-1 downto 0) = ms_fifo(ar.s.pta.index).stop then
av.s.hready := '0';
av.s.hresp := HRESP_ERROR;
av.s.retry := '1';
end if;
if ar.s.parerren = '1' and ms_fifo(ar.s.pta.index).status(0) = '1' then
av.s.hready := '0';
av.s.hresp := HRESP_ERROR;
av.s.retry := '1';
end if;
av.irq.access_status := ar.irq.access_status or ms_fifo(ar.s.pta.index).status(2 downto 0); -- Update irq status
if ar.irq.access_en = '1' then av.irq.access_pirq := '1'; end if; -- If enabled, generate irq on error
end if;
av.s.state := as_idle;
if ar.s.burst = '1' then
av.s.discard := '1';
av.atp_trans.msd_acc_cancel(0) := not ar.atp_trans.msd_acc_cancel(0);
end if;
elsif (ahbsi.hwrite = '0' and ar.s.done_fifo(0) = '1') or ar.s.burst = '0' or ar.s.oneword = '1' then -- no pending fifo => retry
av.s.hready := '0';
av.s.hresp := HRESP_RETRY;
av.s.retry := '1';
av.s.stoppciacc := not pta_trans.ca_pcimsten(ms_vifunc);
if ar.s.burst = '1' and ahbsi.htrans(0) = '1' then
if ar.s.done_fifo(1) = '1' then
av.s.discard := '1';
av.atp_trans.msd_acc_cancel(0) := not ar.atp_trans.msd_acc_cancel(0);
else
av.s.continue := '1'; -- Only for continuing bursts
end if;
end if;
av.s.state := as_idle;
end if;
elsif ahbsi.hsel(hsindex) = '0' or ahbsi.htrans(0) = '0' then -- idle
av.s.state := as_idle;
if ar.s.burst = '1' then
av.s.discard := '1';
av.atp_trans.msd_acc_cancel(0) := not ar.atp_trans.msd_acc_cancel(0);
end if;
end if;
end if;
when as_write =>
av.s.first := '0';
if ar.s.first = '1' then -- Store fifo start address
if ar.s.hmbsel(0) = '0' then -- mem/io/config access
if ar.s.haddr(16) = '1' then
av.s.addr := set_pci_conf_addr(ar.s.haddr, ar.s.cfg_bus);
av.s.offset := ar.s.haddr(1 downto 0);
else av.s.addr := set_pci_io_addr(ar.s.haddr, ar.s.io_map); end if;
else
av.s.addr := set_atp_addr(ar.s.haddr, ar.s.atp_map, ar.s.hmaster, AADDR_WIDTH);
end if;
av.s.size := ar.s.hsize;
av.s.config := (not ar.s.hmbsel(0) and ar.s.haddr(16));
av.s.io := (not ar.s.hmbsel(0) and not ar.s.haddr(16));
if ms_acc_pending = '0' and ar.s.accbuf(0).pending = '0' then
av.atp_trans.msd_acc(0).pending := not ar.atp_trans.msd_acc(0).pending;
av.atp_trans.msd_acc(0).addr := av.s.addr;
av.atp_trans.msd_acc(0).func := ms_func; -- set PCI function
if av.s.config = '1' then av.atp_trans.msd_acc(0).acctype := CONF_WRITE;
elsif av.s.io = '1' then av.atp_trans.msd_acc(0).acctype := IO_WRITE;
else av.atp_trans.msd_acc(0).acctype := MEM_WRITE; end if;
av.atp_trans.msd_acc(0).accmode := "00" & ar.s.hburst;
av.atp_trans.msd_acc(0).size := av.s.size;
av.atp_trans.msd_acc(0).offset := ar.s.haddr(1 downto 0);
av.atp_trans.msd_acc(0).index := ar.s.atp.index;
av.atp_trans.msd_acc(0).length := (others => '0'); -- not used
av.atp_trans.msd_acc(0).cbe := (others => '0'); -- not used
av.atp_trans.msd_acc(0).endianess := '0'; -- not used
else
accbufindex := 0;
for i in 3 downto 0 loop
if av.s.accbuf(i).pending = '0' then accbufindex := i; end if;
end loop;
av.s.accbuf(accbufindex).pending := '1';
av.s.accbuf(accbufindex).addr := av.s.addr;
av.s.accbuf(accbufindex).func := ms_func; -- set PCI function
if av.s.config = '1' then av.s.accbuf(accbufindex).acctype := CONF_WRITE;
elsif av.s.io = '1' then av.s.accbuf(accbufindex).acctype := IO_WRITE;
else av.s.accbuf(accbufindex).acctype := MEM_WRITE; end if;
av.s.accbuf(accbufindex).accmode := "00" & ar.s.hburst;
av.s.accbuf(accbufindex).size := av.s.size;
av.s.accbuf(accbufindex).offset := ar.s.haddr(1 downto 0);
av.s.accbuf(accbufindex).index := ar.s.atp.index;
av.s.accbuf(accbufindex).length := (others => '0'); -- not used
av.s.accbuf(accbufindex).cbe := (others => '0'); -- not used
av.s.accbuf(accbufindex).endianess := '0'; -- not used
end if;
end if;
if ar.s.hready = '1' then
if ar.s.htrans(1) = '1' then
if ar.s.haddr(AHB_FIFO_BITS) = ones32(AHB_FIFO_BITS) or ahbsi.htrans(0) = '0' then
av.s.firstf := '0';
av.s.atp.index := ms_index; -- Go to next fifo
av.atp_trans.msd_fifo(0)(ar.s.atp.index).pending(0) := not ar.atp_trans.msd_fifo(0)(ar.s.atp.index).pending(0);
if ar.s.firstf = '1' then
av.atp_trans.msd_fifo(0)(ar.s.atp.index).start := av.s.addr(AHB_FIFO_BITS);
av.atp_trans.msd_fifo(0)(ar.s.atp.index).firstf := '1';
else
av.atp_trans.msd_fifo(0)(ar.s.atp.index).start := (others => '0');
av.atp_trans.msd_fifo(0)(ar.s.atp.index).firstf := '0';
end if;
av.atp_trans.msd_fifo(0)(ar.s.atp.index).stop := ar.s.haddr(AHB_FIFO_BITS);
av.atp_trans.msd_fifo(0)(ar.s.atp.index).lastf := not ahbsi.htrans(0) or not ms_fifo_empty(ms_index);
av.atp_trans.msd_fifo(0)(ar.s.atp.index).status := (others => '0'); -- Not used
av.atp_trans.msd_fifo(0)(ar.s.atp.index).last_cbe := (others => '0'); -- Not used
end if;
av.s.atp.ctrl.en := '1';
av.s.atp.ctrl.addr := conv_std_logic_vector(ar.s.atp.index, log2(FIFO_COUNT)) & ar.s.haddr(AHB_FIFO_BITS);
end if;
if ahbsi.htrans(1) = '1' and ahbsi.hsel(hsindex) = '1' then
if ahbsi.htrans(0) = '0' then
if ahbsi.hwrite = '1' and ms_fifo_empty(ms_index) = '1' then -- new write access
av.s.first := '1';
av.s.firstf := '1';
else -- retry
av.s.hready := '0';
av.s.hresp := HRESP_RETRY;
av.s.retry := '1';
av.s.state := as_idle;
end if;
end if;
if ahbsi.hwrite = '1' and ar.s.haddr(AHB_FIFO_BITS) = ones32(AHB_FIFO_BITS) and ms_fifo_empty(ms_index) = '0' then -- no empty fifo => retry
av.s.hready := '0';
av.s.hresp := HRESP_RETRY;
av.s.retry := '1';
av.s.state := as_idle;
end if;
elsif ahbsi.hsel(hsindex) = '0' or ahbsi.htrans(0) = '0' then -- idle
av.s.state := as_idle;
end if;
end if;
when as_pcitrace =>
if ar.s.hready = '1' then
if tb_access = '1' then
av.s.hready := '0';
av.s.tb_ren := '1';
else
av.s.state := as_idle;
if ahbsi.htrans(1) = '1' and ahbsi.hsel(hsindex) = '1' then
av.s.hready := '0';
av.s.retry := '1';
av.s.hresp := HRESP_RETRY;
end if;
end if;
else
av.s.tb_ren := '0';
if ar.s.tb_ren = '0' then
av.s.hready := '1';
if ar.s.haddr(16) = '0' then
av.s.hrdata := pt_fifoo_ad.data;
else
av.s.hrdata := zero32(31 downto 20) & pt_fifoo_sig.data(16 downto 0) & "000";
end if;
else
av.s.hready := '0';
end if;
end if;
when others =>
end case;
end if; -- PCI master enabled
-- --------------------------------------------------------------------------------
-- DMA defaults
-- --------------------------------------------------------------------------------
av.dma.irq := '0';
-- FIFO enable(read)/write
av.dma.ptd.ctrl.en := '0';
av.dma.dtp.ctrl.en := '0';
av.dma.dtp.ctrl.data := dmao1.data;
av.dma.dmai1.noreq := '0';
av.dma.desc.addr(3 downto 0) := (others => '0');
md_acc_pending := ar.atp_trans.msd_acc(1).pending xor pta_trans.msd_acc_ack(1);
md_acc_cancel := ar.atp_trans.msd_acc_cancel(1) xor pta_trans.msd_acc_cancel_ack(1)(RAM_LATENCY);
md_acc_done := ar.atp_trans.msd_acc_done_ack(1) xor pta_trans.msd_acc_done(1).done;
for i in 0 to FIFO_COUNT-1 loop
md_fifo_pending(i) := pta_trans.msd_fifo(1)(i).pending(RAM_LATENCY) xor ar.atp_trans.msd_fifo_ack(1)(i);
md_fifo_empty(i) := not (ar.atp_trans.msd_fifo(1)(i).pending(0) xor pta_trans.msd_fifo_ack(1)(i));
av.atp_trans.msd_fifo(1)(i).pending(1) := ar.atp_trans.msd_fifo(1)(i).pending(0);
av.atp_trans.msd_fifo(1)(i).pending(2) := ar.atp_trans.msd_fifo(1)(i).pending(1);
end loop;
md_fifo := pr_pta_trans_gated.msd_fifo(1);
md_acc_done_status := pr_pta_trans_gated.msd_acc_done(1);
-- --------------------------------------------------------------------------------
-- DMA core
-- --------------------------------------------------------------------------------
if dma /= 0 then -- DMA enabled
-- Select next fifo
if ar.dma.state = dma_read then
if ar.dma.dtp.index /= FIFO_COUNT-1 then md_index := ar.dma.dtp.index + 1;
else md_index := 0; end if;
else
if ar.dma.ptd.index /= FIFO_COUNT-1 then md_index := ar.dma.ptd.index + 1;
else md_index := 0; end if;
end if;
case ar.dma.state is
when dma_idle =>
av.dma.err := (others => '0');
av.dma.running := '0';
av.dma.dmai1.req := '0';
av.dma.dmai1.write := '0';
av.dma.dmai1.burst := '1';
av.dma.dmai1.addr := ar.dma.desc.addr;
av.dma.desc.chcnt := ar.dma.numch;
if ar.dma.errstatus /= "00000" then
av.dma.en := '0';
elsif ar.dma.en = '1' then
av.dma.state := dma_read_desc;
av.dma.rcnt := (others => '0');
av.dma.dmai1.req := '1';
av.dma.dmai1.size := "10";
av.dma.running := '1';
end if;
when dma_read_desc =>
av.dma.active := '0';
av.dma.dma_hold := (others => '0');
av.dma.done := (others => '0');
av.dma.first(0) := '1';
av.dma.retry := '0';
if ar.dma.rcnt = "11" and ar.dma.desc.desctype /= "01"
and (ar.dma.desc.emptych = '0' or ar.dma.desc.chcnt = "000") then av.dma.dmai1.req := '0';
else av.dma.dmai1.req := '1'; end if;
av.dma.dmai1.burst := '1';
if dmao1.grant = '1' then
av.dma.dmai1.addr := ar.dma.dmai1.addr + 4;
if ar.dma.dmai1.addr(3 downto 2) = "11" then
if ar.dma.desc.desctype = "01" then
av.dma.dmai1.addr := dmao1.data;
elsif ar.dma.desc.emptych = '1' then
av.dma.desc.addr := ar.dma.desc.nextch;
av.dma.dmai1.addr := ar.dma.desc.nextch;
if ar.dma.desc.chcnt = "000" then
av.dma.dmai1.req := '0';
end if;
else
av.dma.dmai1.req := '0';
end if;
end if;
elsif dmao1.retry = '1' then
av.dma.dmai1.addr := ar.dma.dmai1.addr - 4;
end if;
if av.dma.dmai1.addr(3 downto 2) = "11" then av.dma.dmai1.noreq := '1'; end if;
if dmao1.ready = '1' then
av.dma.err := (others => '0');
av.dma.rcnt := ar.dma.rcnt + 1;
case ar.dma.rcnt is
when "00" => -- Ctrl
av.dma.desc.en := dmao1.data(31);
av.dma.desc.irqen := dmao1.data(30);
av.dma.desc.write := dmao1.data(29);
av.dma.desc.tw := dmao1.data(28);
av.dma.desc.cio := dmao1.data(27 downto 26);
av.dma.desc.acctype := dmao1.data(25 downto 22);
av.dma.desc.desctype := dmao1.data(21 downto 20);
-- dmao1.data(19) = err
av.dma.desc.len := dmao1.data(15 downto 0);
when "01" => -- PCI address / Next DMA CH
if ar.dma.desc.desctype = "01" then
av.dma.desc.ch := ar.dma.desc.addr;
av.dma.desc.nextch := dmao1.data;
av.dma.desc.cnt := ar.dma.desc.len;
av.dma.desc.chid := ar.dma.desc.acctype(2 downto 0);
av.dma.desc.emptych := '1';
else
if ar.dma.desc.en = '1' then
av.dma.desc.emptych := '0';
end if;
av.dma.desc.paddr := dmao1.data;
end if;
when "10" => -- AHB address / Next desc
if ar.dma.desc.desctype = "01" then
av.dma.desc.addr := dmao1.data;
else
av.dma.desc.aaddr := dmao1.data;
end if;
when "11" => -- Next desc / ----
if ar.dma.desc.en = '1' then
if ar.dma.desc.desctype = "00" then
av.dma.desc.chcnt := ar.dma.numch;
av.dma.desc.nextdesc := dmao1.data;
if ar.dma.desc.write = '1' then -- AHB read => PCI write
av.dma.state := dma_read;
av.dma.dmai1.req := '1';
av.dma.dmai1.write := '0';
av.dma.dmai1.addr := ar.dma.desc.aaddr;
if ar.dma.desc.len /= x"0000" then av.dma.dmai1.burst := '1';
else av.dma.dmai1.burst := '0'; end if;
av.dma.dmai1.size := "10"; -- 32-bit access -- add support for unaligned accesses
av.dma.dtp.ctrl.addr := conv_std_logic_vector(ar.dma.dtp.index, log2(FIFO_COUNT)) & ar.dma.desc.aaddr(AHB_FIFO_BITS); -- Set fifo start address
av.dma.faddr := ar.dma.desc.aaddr(AHB_FIFO_BITS);
av.dma.len := (others => '0');
av.dma.errlen := (others => '0');
else -- PCI read => AHB write
av.dma.state := dma_write;
av.dma.first := "010";
av.dma.dma_hold := "111";
av.dma.addr := ar.dma.desc.aaddr;
av.dma.len := (others => '0');
av.dma.errlen := (others => '0');
end if;
-- Setup access [Read and Write]
av.atp_trans.msd_acc(1).pending := not ar.atp_trans.msd_acc(1).pending;
av.atp_trans.msd_acc(1).addr := ar.dma.desc.paddr;
av.atp_trans.msd_acc(1).func := "000"; -- DMA uses PCI function 0
if ar.dma.desc.write = '1' then -- AHB read => PCI write
av.atp_trans.msd_acc(1).index := ar.dma.dtp.index;
if ar.dma.desc.cio = "01" then -- PCI IO access
av.atp_trans.msd_acc(1).acctype := IO_WRITE;
elsif ar.dma.desc.cio = "01" then -- PCI Configuration access
av.atp_trans.msd_acc(1).acctype := CONF_WRITE;
else -- PCI Memory access
av.atp_trans.msd_acc(1).acctype := MEM_WRITE;
end if;
else
av.atp_trans.msd_acc(1).index := ar.dma.ptd.index;
if ar.dma.desc.cio = "01" then -- PCI IO access
av.atp_trans.msd_acc(1).acctype := IO_READ;
elsif ar.dma.desc.cio = "01" then -- PCI Configuration access
av.atp_trans.msd_acc(1).acctype := CONF_READ;
else -- PCI Memory access
if ar.dma.desc.len /= x"0000" then
av.atp_trans.msd_acc(1).acctype := MEM_R_MULT;
else
av.atp_trans.msd_acc(1).acctype := MEM_READ;
end if;
end if;
end if;
if ar.dma.desc.len /= x"0000" then
av.atp_trans.msd_acc(1).accmode := "011";
else
av.atp_trans.msd_acc(1).accmode := "010";
end if;
av.atp_trans.msd_acc(1).size := "010"; -- add size support
av.atp_trans.msd_acc(1).offset := ar.dma.desc.paddr(1 downto 0);
av.atp_trans.msd_acc(1).length := ar.dma.desc.len;
av.atp_trans.msd_acc(1).cbe := (others => '0'); -- not used
av.atp_trans.msd_acc(1).endianess := av.dma.desc.tw;
end if;
else
if ar.dma.desc.emptych = '0' then
av.dma.state := dma_next_channel;
av.dma.dmai1.req := '1';
av.dma.dmai1.write := '1';
av.dma.dmai1.burst := '0';
av.dma.dmai1.addr := ar.dma.desc.ch + 8;
av.dma.dmai1.data := ar.dma.desc.nextdesc;
else
if ar.dma.desc.chcnt = "000" then
av.dma.en := '0';
av.dma.state := dma_idle;
else
av.dma.desc.chcnt := ar.dma.desc.chcnt - 1;
end if;
end if;
end if;
when others =>
end case;
elsif dmao1.error = '1' then
av.dma.en := '0';
av.dma.state := dma_idle;
av.dma.dmai1.req := '0';
av.dma.irq := '1'; av.dma.irqstatus(0) := '1';
av.dma.errstatus(0) := '1';
end if;
when dma_next_channel =>
if dmao1.grant = '1' then
av.dma.dmai1.req := '0';
elsif dmao1.retry = '1' then
av.dma.dmai1.req := '1';
end if;
if dmao1.ready = '1' then
av.dma.state := dma_read_desc;
av.dma.dmai1.req := '1';
av.dma.dmai1.write := '0';
av.dma.dmai1.burst := '1';
av.dma.desc.addr := ar.dma.desc.nextch;
av.dma.dmai1.addr := ar.dma.desc.nextch;
elsif dmao1.error = '1' then
av.dma.en := '0';
av.dma.state := dma_idle;
av.dma.dmai1.req := '0';
av.dma.irq := '1'; av.dma.irqstatus(0) := '1';
end if;
when dma_write_status =>
if dmao1.grant = '1' then
if ar.dma.desc.cnt = x"0001" then -- Next Channel
av.dma.dmai1.addr := ar.dma.desc.ch + 8;
else
av.dma.dmai1.req := '0';
end if;
elsif dmao1.retry = '1' then
av.dma.dmai1.req := '1';
av.dma.dmai1.addr := ar.dma.desc.addr;
end if;
if dmao1.ready = '1' then
if ar.dma.err /= "000" then
av.dma.en := '0';
av.dma.state := dma_idle;
av.dma.irq := '1'; av.dma.irqstatus(0) := '1';
else
if ar.dma.desc.irqen = '1' then
av.dma.irq := '1';
av.dma.irqstatus(1) := '1';
av.dma.irqch(conv_integer(ar.dma.desc.chid)) := '1';
end if;
if ar.dma.en = '0' then -- DMA disabled
av.dma.state := dma_idle;
av.dma.desc.addr := ar.dma.desc.nextdesc;
else
if ar.dma.desc.cnt = x"0001" then -- Next Channel
av.dma.state := dma_next_channel;
av.dma.dmai1.req := '1';
av.dma.dmai1.write := '1';
av.dma.dmai1.burst := '0';
av.dma.dmai1.data := ar.dma.desc.nextdesc;
else -- Next Desc
if ar.dma.desc.cnt /= x"0000" then
av.dma.desc.cnt := av.dma.desc.cnt - 1;
end if;
av.dma.state := dma_read_desc;
av.dma.dmai1.req := '1';
av.dma.dmai1.write := '0';
av.dma.dmai1.burst := '1';
av.dma.desc.addr := ar.dma.desc.nextdesc;
av.dma.dmai1.addr := ar.dma.desc.nextdesc;
end if;
end if;
end if;
elsif dmao1.error = '1' then
av.dma.en := '0';
av.dma.state := dma_idle;
av.dma.dmai1.req := '0';
av.dma.irq := '1'; av.dma.irqstatus(0) := '1';
av.dma.errstatus(0) := '1';
end if;
when dma_read => -- AHB read => PCI write
if md_fifo_empty(ar.dma.dtp.index) = '1' and ar.dma.dma_hold(0) = '1' and ar.dma.done(0) = '0' and ar.dma.active = '0' then
av.dma.dmai1.req := '1';
av.dma.dma_hold(1 downto 0) := "00";
end if;
if dmao1.grant = '1' then
av.dma.active := '1';
av.dma.dmai1.addr := ar.dma.dmai1.addr + 4;
if ar.dma.len /= ar.dma.desc.len then
av.dma.len := ar.dma.len + 1;
end if;
if ar.dma.dmai1.addr(AHB_FIFO_BITS) = ones32(AHB_FIFO_BITS) or ar.dma.len = ar.dma.desc.len then
if md_fifo_empty(md_index) = '0' then
av.dma.dmai1.req := '0';
av.dma.dma_hold(0) := '1';
end if;
if ar.dma.len = ar.dma.desc.len then
av.dma.dmai1.req := '0';
av.dma.done(1) := '1';
end if;
end if;
-- Retry save & restore
av.dma.retry := '0';
-- Save len for retry
av.dma.retry_len := ar.dma.len;
-- Restore len for retry
if ar.dma.retry = '1' then
av.dma.len := ar.dma.retry_len;
end if;
elsif dmao1.retry = '1' then
av.dma.dmai1.req := '1';
av.dma.dmai1.addr := ar.dma.dmai1.addr - 4;
--av.dma.len := ar.dma.len - 1;
av.dma.done(1) := '0';
-- Retry save & restore
av.dma.retry := '1';
-- Save len for retry
av.dma.retry_len := ar.dma.len;
-- Restore len for retry
av.dma.len := ar.dma.retry_len;
end if;
if dmao1.ready = '1' then
if ar.dma.errlen /= ar.dma.desc.len then
av.dma.errlen := ar.dma.errlen + 1;
end if;
if dmao1.grant = '0' then av.dma.active := '0'; end if;
if ar.dma.faddr(AHB_FIFO_BITS) /= ones32(AHB_FIFO_BITS) and ar.dma.done(1) = '0' then -- Store data in fifo
av.dma.faddr(AHB_FIFO_BITS) := ar.dma.faddr(AHB_FIFO_BITS) + 1;
else -- Last word in fifo
av.dma.faddr(AHB_FIFO_BITS) := (others => '0');
av.dma.dtp.index := md_index; -- Go to next fifo
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).pending(0) := not ar.atp_trans.msd_fifo(1)(ar.dma.dtp.index).pending(0);
if ar.dma.first(0) = '1' then -- Mark first fifo in transfer
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).firstf := '1';
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).start := ar.dma.desc.aaddr(AHB_FIFO_BITS);
av.dma.first(0) := '0';
else
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).start := (others => '0');
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).firstf := '0';
end if;
if ar.dma.done(1) = '1' then -- Mark last fifo in transfer
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).lastf := '1';
av.dma.done(0) := '1';
else
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).lastf := '0';
end if;
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).stop := ar.dma.faddr(AHB_FIFO_BITS);
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).status := (others => '0'); -- Not used
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).last_cbe := (others => '0'); -- Not used
end if;
av.dma.dtp.ctrl.en := '1';
av.dma.dtp.ctrl.addr := conv_std_logic_vector(ar.dma.dtp.index, log2(FIFO_COUNT)) & ar.dma.faddr(AHB_FIFO_BITS);
elsif dmao1.error = '1' then
av.dma.active := '0';
av.dma.dmai1.req := '0';
av.dma.done(0) := '1';
av.dma.err(0) := '1';
av.dma.dtp.index := md_index; -- Go to next fifo
if ar.dma.first(0) = '1' then -- Mark first fifo in transfer
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).firstf := '1';
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).start := ar.dma.desc.aaddr(AHB_FIFO_BITS);
av.dma.first(0) := '0';
else
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).firstf := '0';
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).start := (others => '0');
end if;
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).lastf := '1';
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).stop := ar.dma.faddr(AHB_FIFO_BITS);
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).pending(0) := not ar.atp_trans.msd_fifo(1)(ar.dma.dtp.index).pending(0);
av.dma.dtp.ctrl.en := '1';
av.dma.dtp.ctrl.addr := conv_std_logic_vector(ar.dma.dtp.index, log2(FIFO_COUNT)) & ar.dma.faddr(AHB_FIFO_BITS);
end if;
if av.dma.dmai1.addr(AHB_FIFO_BITS) = ones32(AHB_FIFO_BITS) or av.dma.len = ar.dma.desc.len then av.dma.dmai1.noreq := '1'; end if; -- to deassert req on last address phase
if ar.dma.done(0) = '1' then
av.dma.dmai1.req := '0';
if md_acc_done = '1' then
av.atp_trans.msd_acc_done_ack(1) := not ar.atp_trans.msd_acc_done_ack(1);
av.dma.state := dma_write_status;
av.dma.dmai1.req := '1';
av.dma.dmai1.write := '1';
av.dma.dmai1.burst := '0';
av.dma.dmai1.addr := ar.dma.desc.addr;
av.dma.dmai1.data := (others => '0');
av.dma.dmai1.data(30) := ar.dma.desc.irqen;
av.dma.dmai1.data(29) := ar.dma.desc.write;
av.dma.dmai1.data(28) := ar.dma.desc.tw;
av.dma.dmai1.data(21 downto 20) := ar.dma.desc.desctype;
if ar.dma.err(0) = '1' then
av.dma.dmai1.data(19) := '1';
av.dma.dmai1.data(15 downto 0) := ar.dma.errlen;
av.dma.errstatus(1) := '1';
elsif md_acc_done_status.status /= "0000" then
av.dma.err(2) := '1';
av.dma.dmai1.data(19) := '1';
av.dma.dmai1.data(15 downto 0) := md_acc_done_status.count;
av.dma.errstatus(4 downto 2) := md_acc_done_status.status(2 downto 0);
else
av.dma.dmai1.data(19) := '0';
av.dma.dmai1.data(15 downto 0) := ar.dma.errlen;
end if;
end if;
end if;
when dma_write => -- PCI read => AHB write
av.dma.ptd.ctrl.en := md_fifo_pending(ar.dma.ptd.index);
av.dma.dmai1.write := '1';
av.dma.first(0) := '0';
if md_fifo_pending(ar.dma.ptd.index) = '1' and ar.dma.dma_hold(0) = '1' and ar.dma.active = '0' and ar.dma.done(0) = '0' and ar.dma.first(2) = '0' then
av.dma.first(0) := '1';
av.dma.first(2) := '1';
av.dma.dma_hold := "000";
av.dma.dma_last := "000";
av.dma.newfifo := '0';
av.dma.ptd.ctrl.addr := conv_std_logic_vector(ar.dma.ptd.index, log2(FIFO_COUNT)) & md_fifo(ar.dma.ptd.index).start; -- Set fifo start address
av.dma.faddr := md_fifo(ar.dma.ptd.index).start; -- Set fifo start address
if ar.dma.first(1) = '1' then
av.dma.first(1) := '0';
av.dma.dmai1.addr := ar.dma.addr;
av.dma.dmai1.size := "10";
av.dma.dmai1.addr(1 downto 0) := "00";
end if;
end if;
if ar.dma.first(0) = '1' then -- Latch first word in fifo
av.dma.dmai1.req := '1';
if ar.dma.ptd.ctrl.addr(FIFO_DEPTH-1 downto 0) /= md_fifo(ar.dma.ptd.index).stop then
av.dma.ptd.ctrl.addr(FIFO_DEPTH-1 downto 0) := ar.dma.ptd.ctrl.addr(FIFO_DEPTH-1 downto 0) + 1;
else
av.dma.dma_hold(0) := '1';
if md_fifo(ar.dma.ptd.index).lastf = '1' then
av.dma.dma_last(0) := '1';
if md_fifo(ar.dma.ptd.index).status /= "0000" then
av.dma.done(0) := '1';
av.dma.dmai1.req := '0';
av.dma.err(2) := '1'; -- PCI error
av.dma.errlen := ar.dma.errlen;
av.dma.ptd.index := md_index; -- Go to next fifo
av.atp_trans.msd_fifo_ack(1)(ar.dma.ptd.index) := pta_trans.msd_fifo(1)(ar.dma.ptd.index).pending(RAM_LATENCY);
av.dma.errstatus(4 downto 2) := md_fifo(ar.dma.ptd.index).status(2 downto 0);
end if;
end if;
end if;
av.dma.dmai1.data := md_fifoo_ptd.data;
end if;
if dmao1.grant = '1' then
av.dma.active := '1';
av.dma.newfifo := '0';
av.dma.dmai1.addr := ar.dma.dmai1.addr + 4;
av.dma.faddr := ar.dma.faddr + 1;
if (ar.dma.active = '1' and ar.dma.faddr = md_fifo(ar.dma.ptd.index).stop) or ar.dma.dma_hold(1 downto 0) /= "00" or ar.dma.done(0) = '1' then
if (ar.dma.active = '1' and md_fifo_pending(md_index) = '0') or ar.dma.dma_hold(1 downto 0) /= "00" or ar.dma.done(0) = '1' then
av.dma.dmai1.req := '0';
av.dma.dma_hold(0) := '1';
end if;
end if;
elsif dmao1.retry = '1' then
av.dma.dmai1.req := '1';
av.dma.dmai1.addr := ar.dma.dmai1.addr - 4;
av.dma.faddr := ar.dma.faddr - 1;
end if;
if dmao1.ready = '1' then
av.dma.first(2) := '0';
if ar.dma.errlen /= ar.dma.desc.len then
av.dma.errlen := ar.dma.errlen + 1;
end if;
if dmao1.grant = '0' and ar.dma.dmai1.req = '0' then av.dma.active := '0'; end if;
if ar.dma.dma_hold(1 downto 0) = "00" then
av.dma.dmai1.data := md_fifoo_ptd.data;
av.dma.ptd.ctrl.addr(FIFO_DEPTH-1 downto 0) := ar.dma.ptd.ctrl.addr(FIFO_DEPTH-1 downto 0) + 1;
end if;
if md_fifo_pending(ar.dma.ptd.index) = '1' and ar.dma.ptd.ctrl.addr(FIFO_DEPTH-1 downto 0) = md_fifo(ar.dma.ptd.index).stop and
ar.dma.dma_hold(1 downto 0) /= "11" and ar.dma.done(0) = '0' then
av.dma.ptd.index := md_index; -- Go to next fifo
av.atp_trans.msd_fifo_ack(1)(ar.dma.ptd.index) := pta_trans.msd_fifo(1)(ar.dma.ptd.index).pending(RAM_LATENCY);
av.dma.ptd.ctrl.addr := conv_std_logic_vector(av.dma.ptd.index, log2(FIFO_COUNT)) & md_fifo(md_index).start; -- Set fifo start address
if md_fifo_pending(md_index) = '0' or ar.dma.dma_hold(0) = '1' then
av.dma.dma_hold(1) := '1';
end if;
if md_fifo(ar.dma.ptd.index).lastf = '1' or ar.dma.dma_last(1 downto 0) /= "00" then -- Transfer done
av.dma.done(0) := '1';
if md_fifo(ar.dma.ptd.index).status /= "0000" then
av.dma.err(2) := '1'; -- PCI error
av.dma.errlen := ar.dma.errlen;
av.dma.errstatus(4 downto 2) := md_fifo(ar.dma.ptd.index).status(2 downto 0);
end if;
end if;
end if;
elsif dmao1.error = '1' then
av.dma.err(0) := '1';
av.dma.errstatus(1) := '1';
av.dma.active := '0';
av.dma.dmai1.req := '0';
if ar.dma.done(0) = '0' then
if md_fifo_pending(ar.dma.ptd.index) = '1' and md_fifo(ar.dma.ptd.index).lastf = '1' then
av.dma.ptd.index := md_index; -- Go to next fifo
av.atp_trans.msd_fifo_ack(1)(ar.dma.ptd.index) := pta_trans.msd_fifo(1)(ar.dma.ptd.index).pending(RAM_LATENCY);
av.dma.done(0) := '1';
else
av.dma.state := dma_error;
end if;
end if;
end if;
if ar.dma.done(0) = '1' and ar.dma.active = '0' then
av.dma.state := dma_write_status;
av.dma.dmai1.req := '1';
av.dma.dmai1.write := '1';
av.dma.dmai1.burst := '0';
av.dma.dmai1.addr := ar.dma.desc.addr;
av.dma.dmai1.data := (others => '0');
av.dma.dmai1.data(30) := ar.dma.desc.irqen;
av.dma.dmai1.data(29) := ar.dma.desc.write;
av.dma.dmai1.data(28) := ar.dma.desc.tw;
av.dma.dmai1.data(21 downto 20) := ar.dma.desc.desctype;
if ar.dma.err(0) = '1' or ar.dma.err(2) = '1' then
av.dma.dmai1.data(19) := '1';
av.dma.dmai1.data(15 downto 0) := ar.dma.errlen;
else
av.dma.dmai1.data(19) := '0';
av.dma.dmai1.data(15 downto 0) := ar.dma.errlen;
end if;
end if;
if av.dma.dmai1.addr(AHB_FIFO_BITS) = md_fifo(ar.dma.ptd.index).stop or ar.dma.done(0) = '1' then av.dma.dmai1.noreq := '1'; end if; -- to deassert req on last address phase
when dma_error => -- Wait for last fifo
if md_fifo_pending(ar.dma.ptd.index) = '1' and ar.dma.done(0) = '0' then
if md_fifo(ar.dma.ptd.index).lastf = '1' then
av.dma.done(0) := '1';
end if;
av.dma.ptd.index := md_index; -- Go to next fifo
av.atp_trans.msd_fifo_ack(1)(ar.dma.ptd.index) := pta_trans.msd_fifo(1)(ar.dma.ptd.index).pending(RAM_LATENCY);
end if;
if ar.dma.done(0) = '1' then
av.dma.state := dma_write_status;
av.dma.dmai1.req := '1';
av.dma.dmai1.write := '1';
av.dma.dmai1.burst := '0';
av.dma.dmai1.addr := ar.dma.desc.addr;
av.dma.dmai1.data := (others => '0');
av.dma.dmai1.data(30) := ar.dma.desc.irqen;
av.dma.dmai1.data(29) := ar.dma.desc.write;
av.dma.dmai1.data(28) := ar.dma.desc.tw;
av.dma.dmai1.data(21 downto 20) := ar.dma.desc.desctype;
if ar.dma.err(0) = '1' or ar.dma.err(2) = '1' then
av.dma.dmai1.data(19) := '1';
av.dma.dmai1.data(15 downto 0) := ar.dma.errlen;
else
av.dma.dmai1.data(19) := '0';
av.dma.dmai1.data(15 downto 0) := ar.dma.errlen;
end if;
end if;
when others =>
end case;
end if; -- DMA enabled
-- --------------------------------------------------------------------------------
-- IRQ
-- --------------------------------------------------------------------------------
pirq := (others => '0');
-- PCI device driving PCI INTA
if deviceirq = 1 then
pciinten(0) <= oeoff xor (ar.irq.device_mask(0) and (ar.irq.device_force or dirq(0)));
pciinten(1) <= oeoff xor (ar.irq.device_mask(1) and (ar.irq.device_force or dirq(1)));
pciinten(2) <= oeoff xor (ar.irq.device_mask(2) and (ar.irq.device_force or dirq(2)));
pciinten(3) <= oeoff xor (ar.irq.device_mask(3) and (ar.irq.device_force or dirq(3)));
else
av.irq.device_mask := (others => '0');
av.irq.device_force := '0';
pciinten <= (others => oeoff);
end if;
-- PCI host sampling PCI INTA..D
if hostirq = 1 then
av.irq.host_pirq_vl := (pcii.int(3) or not ar.irq.host_mask(3))
& (pcii.int(2) or not ar.irq.host_mask(2))
& (pcii.int(1) or not ar.irq.host_mask(1))
& (pcii.int(0) or not ar.irq.host_mask(0));
av.irq.host_pirq_l := not ( av.irq.host_pirq_vl(0) and av.irq.host_pirq_vl(1)
and av.irq.host_pirq_vl(2) and av.irq.host_pirq_vl(3));
av.irq.host_status := pcii.int(3)
& pcii.int(2)
& pcii.int(1)
& pcii.int(0);
else
av.irq.host_mask := (others => '0');
av.irq.host_status := (others => '0');
av.irq.host_pirq_vl:= (others => '0');
av.irq.host_pirq_l := '0';
end if;
-- System error irq (SERR)
if pta_trans.pa_serr = '1' and ar.atp_trans.pa_serr_rst = '1' then
av.irq.system_status(0) := '0';
av.atp_trans.pa_serr_rst := '0';
elsif pta_trans.pa_serr = '0' then
av.irq.system_status(0) := '1';
if ar.irq.system_en = '1' and ar.irq.system_status(0) = '0' then
av.irq.system_pirq := '1';
end if;
end if;
-- System error irq (Discard time out)
if pta_trans.pa_discardtout = '0' and ar.atp_trans.pa_discardtout_rst = '1' then
av.irq.system_status(1) := '0';
av.atp_trans.pa_discardtout_rst := '0';
elsif pta_trans.pa_discardtout = '1' then
av.irq.system_status(1) := '1';
if ar.irq.system_en = '1' and ar.irq.system_status(1) = '0' then
av.irq.system_pirq := '1';
end if;
end if;
-- Level IRQ
av.irq.system_pirq_l := ar.irq.system_en and orv(ar.irq.system_status);
av.irq.access_pirq_l := ar.irq.access_en and orv(ar.irq.access_status);
av.irq.dma_pirq_l := ar.dma.irqen and orv(ar.dma.irqstatus);
if irqmode = 0 then -- PCI INTA..D, Error irq and DMA irq on the same interrupt
pirq(irq) := ar.irq.host_pirq_l or ar.irq.access_pirq_l or ar.irq.dma_pirq_l or ar.irq.system_pirq_l; -- All level irq
elsif irqmode = 1 then -- PCI INTA..D and Error irq on the same interrupt. DMA irq no next interrupt
pirq(irq) := ar.irq.host_pirq_l or ar.irq.access_pirq_l or ar.irq.system_pirq_l;
pirq(irq+1) := (ar.dma.irqen and ar.dma.irq);
elsif irqmode = 2 then -- PCI INTA..D on separate interrupt, Error irq and DMA irq on first interrupt
pirq(irq) := not ar.irq.host_pirq_vl(0) or ar.irq.access_pirq_l or ar.irq.dma_pirq_l or ar.irq.system_pirq_l;
pirq(irq+1) := not ar.irq.host_pirq_vl(1);
pirq(irq+2) := not ar.irq.host_pirq_vl(2);
pirq(irq+3) := not ar.irq.host_pirq_vl(3);
else --if irqmode = 3 then -- PCI INTA..D on separate interrupt, Error irq on first interrupt, DMA irq on interrupt after PCI INTD
pirq(irq) := not ar.irq.host_pirq_vl(0) or ar.irq.access_pirq_l or ar.irq.system_pirq_l;
pirq(irq+1) := not ar.irq.host_pirq_vl(1);
pirq(irq+2) := not ar.irq.host_pirq_vl(2);
pirq(irq+3) := not ar.irq.host_pirq_vl(3);
pirq(irq+4) := (ar.dma.irqen and ar.dma.irq);
end if;
-- --------------------------------------------------------------------------------
-- APB Slave
-- --------------------------------------------------------------------------------
av.apb_pt_stat := zero32(15 downto PT_DEPTH) & pt_status.taddr
& pt_status.armed & ptta_trans.enable & pt_status.wrap & "0"
& conv_std_logic_vector(PT_DEPTH, 8)
& "00" & ar.atpt_trans.stop & ar.atpt_trans.start;
av.debug_pr := pr.debug;
av.apb_pr_conf_0_pta_map := pr.conf(0).pta_map;
prdata := (others => '0');
apbaddr := apbi.paddr(6 downto 2);
if iotest/=0 and iotmact='0' then av.debuga(5 downto 0) := "000000"; end if;
if (apbi.psel(pindex) and apbi.penable) = '1' then
if apbi.paddr(7) = '0' then -- PCI core and DMA
case apbaddr is
when "00000" => -- 0x00 Control
prdata(31 downto 29) := ar.atp_trans.rst(2 downto 0);
prdata( 28) := '0';
prdata( 27) := ar.irq.system_en;
prdata( 26) := ar.s.parerren;
prdata( 25) := ar.s.erren;
prdata( 24) := ar.irq.access_en;
prdata(23 downto 16) := ar.s.cfg_bus;
prdata(15 downto 12) := (others => '0'); -- RESERVED
prdata( 11) := ar.atp_trans.mstswdis;
prdata(10 downto 9) := ar.s.io_cfg_burst;
prdata( 8) := ar.irq.device_force;
prdata( 7 downto 4) := ar.irq.device_mask;
prdata( 3 downto 0) := ar.irq.host_mask;
if apbi.pwrite = '1' then
av.atp_trans.rst(2) := apbi.pwdata(31);
av.atp_trans.rst(1 downto 0) := ar.atp_trans.rst(1 downto 0) or apbi.pwdata(30 downto 29);
av.irq.system_en := apbi.pwdata( 27);
av.s.parerren := apbi.pwdata( 26);
av.s.erren := apbi.pwdata( 25);
av.irq.access_en := apbi.pwdata( 24);
av.s.cfg_bus := apbi.pwdata(23 downto 16);
-- := apbi.pwdata(15 downto 12);
av.atp_trans.mstswdis:= apbi.pwdata( 11);
av.s.io_cfg_burst := apbi.pwdata(10 downto 9);
av.irq.device_force := apbi.pwdata( 8);
av.irq.device_mask := apbi.pwdata( 7 downto 4);
av.irq.host_mask := apbi.pwdata( 3 downto 0);
end if;
when "00001" => -- 0x04 Status
prdata(31) := (pta_trans.ca_host and not ar.s.fakehost);
prdata(30) := conv_std_logic(master/=0);
prdata(29) := conv_std_logic(target/=0);
prdata(28) := conv_std_logic(dma/=0);
prdata(27) := conv_std_logic(deviceirq/=0);
prdata(26) := conv_std_logic(hostirq/=0);
prdata(25 downto 24) := conv_std_logic_vector(irqmode, 2);
prdata(23) := conv_std_logic(tracebuffer/=0);
prdata(22 downto 22) := (others => '0'); -- RESERVED
prdata( 21) := ar.s.fakehost;
prdata(20 downto 19) := ar.s.cfg_status;
prdata(18 downto 17) := ar.irq.system_status;
prdata(16 downto 12) := ar.dma.irqstatus & ar.irq.access_status;
prdata(11 downto 8) := ar.irq.host_status;
prdata( 7 downto 5) := (others => '0');-- conv_std_logic_vector(dma_fifo_depth, 2);
prdata( 4 downto 2) := conv_std_logic_vector(fifo_depth, 3);
prdata( 1 downto 0) := conv_std_logic_vector(fifo_count, 2);
if apbi.pwrite = '1' then
av.s.fakehost := ar.s.fakehost xor apbi.pwdata(21);
av.s.cfg_status(0) := ar.s.cfg_status(0) and not (apbi.pwdata(20) or apbi.pwdata(19)); -- Clear cfg_status
av.s.cfg_status(1) := ar.s.cfg_status(1) and not (apbi.pwdata(20) or apbi.pwdata(19)); -- Clear cfg_status
av.atp_trans.pa_discardtout_rst := ar.atp_trans.pa_discardtout_rst or apbi.pwdata(18);
av.atp_trans.pa_serr_rst := ar.atp_trans.pa_serr_rst or apbi.pwdata(17);
av.dma.irqstatus := ar.dma.irqstatus and not apbi.pwdata(16 downto 15);
av.irq.access_status := ar.irq.access_status and not apbi.pwdata(14 downto 12);
end if;
when "00010" => -- 0x08 AHB slave burst lenght and AHB-master mask
if apbi.pwrite = '1' then
av.s.blen := apbi.pwdata(7 downto 0);
av.s.blenmask := apbi.pwdata(31 downto 16);
end if;
prdata(31 downto 0) := ar.s.blenmask & zero32(15 downto 8) & ar.s.blen;
when "00011" => -- 0x0c AHB to PCI IO map
if apbi.pwrite = '1' then
av.s.io_map := apbi.pwdata(31 downto 16);
end if;
prdata(31 downto 0) := ar.s.io_map & zero32(15 downto 0);
when "00100" => -- 0x10 DMA Control
if apbi.pwrite = '1' then
av.dma.irqch := ar.dma.irqch and not apbi.pwdata(19 downto 12);
av.dma.errstatus := ar.dma.errstatus and not apbi.pwdata(11 downto 7);
if apbi.pwdata(31) = '1' then -- Safety guard for update of control fields
av.dma.numch := apbi.pwdata(6 downto 4);
av.dma.irqen := apbi.pwdata(1);
end if;
av.dma.en := (ar.dma.en and not apbi.pwdata(2)) or apbi.pwdata(0); -- bit[2] = disable/stop bit[0] = enable/start
end if;
prdata(31) := '1';
prdata(30 downto 0) := (others => '0');
prdata(19 downto 12) := ar.dma.irqch;
prdata(11 downto 7) := ar.dma.errstatus;
prdata(6 downto 4) := ar.dma.numch;
prdata(3) := ar.dma.running;
prdata(2) := '0';
prdata(1) := ar.dma.irqen;
prdata(0) := ar.dma.en;
when "00101" => -- 0x14 DMA Data desc
if apbi.pwrite = '1' then
av.dma.desc.addr(31 downto 4) := apbi.pwdata(31 downto 4);
end if;
prdata(31 downto 0) := ar.dma.desc.addr;
when "00110" => -- 0x18 DMA Channel desc
prdata(31 downto 0) := ar.dma.desc.ch;
when "00111" => -- 0x1c Reserved
prdata(31 downto 0) := ar.debuga;
if apbi.pwrite = '1' then
av.debuga := apbi.pwdata;
end if;
when "01000" => -- 0x20 PCI BAR0 to AHB map (read only)
prdata(31 downto 0) := ar.apb_pr_conf_0_pta_map(0);
when "01001" => -- 0x24 PCI BAR1 to AHB map (read only)
prdata(31 downto 0) := ar.apb_pr_conf_0_pta_map(1);
when "01010" => -- 0x28 PCI BAR2 to AHB map (read only)
prdata(31 downto 0) := ar.apb_pr_conf_0_pta_map(2);
when "01011" => -- 0x2c PCI BAR3 to AHB map (read only)
prdata(31 downto 0) := ar.apb_pr_conf_0_pta_map(3);
when "01100" => -- 0x30 PCI BAR4 to AHB map (read only)
prdata(31 downto 0) := ar.apb_pr_conf_0_pta_map(4);
when "01101" => -- 0x34 PCI BAR5 to AHB map (read only)
prdata(31 downto 0) := ar.apb_pr_conf_0_pta_map(5);
when "01110" => -- 0x38 Reserved
--prdata(31 downto 0) := (others => '0');
prdata := ar.debug;
when "01111" => -- 0x3c Reserved
--prdata(31 downto 0) := (others => '0');
prdata := ar.debug_pr;
when "10000" => -- 0x40 AHB master00 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(0)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(0)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(0);
when "10001" => -- 0x44 AHB master01 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(1)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(1)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(1);
when "10010" => -- 0x48 AHB master02 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(2)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(2)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(2);
when "10011" => -- 0x4c AHB master03 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(3)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(3)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(3);
when "10100" => -- 0x50 AHB master04 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(4)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(4)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(4);
when "10101" => -- 0x54 AHB master05 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(5)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(5)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(5);
when "10110" => -- 0x58 AHB master06 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(6)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(6)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(6);
when "10111" => -- 0x5c AHB master07 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(7)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(7)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(7);
when "11000" => -- 0x60 AHB master08 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(8)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(8)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(8);
when "11001" => -- 0x64 AHB master09 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(9)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(9)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(9);
when "11010" => -- 0x68 AHB master10 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(10)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(10)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(10);
when "11011" => -- 0x6c AHB master11 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(11)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(11)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(11);
when "11100" => -- 0x70 AHB master12 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(12)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(12)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(12);
when "11101" => -- 0x74 AHB master13 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(13)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(13)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(13);
when "11110" => -- 0x78 AHB master14 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(14)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(14)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(14);
when "11111" => -- 0x7c AHB master15 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(15)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(15)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(15);
when others =>
prdata(31 downto 0) := (others => '0');
end case;
elsif tracebuffer /= 0 then -- PCI trace buffer enabled
case apbaddr is
when "00000" => -- 0x80 PCI trace control & status
if apbi.pwrite = '1' then
av.atpt_trans.start := ar.atpt_trans.start or apbi.pwdata(0);
av.atpt_trans.stop := ar.atpt_trans.stop or apbi.pwdata(1);
end if;
prdata(31 downto 0) := ar.apb_pt_stat;
when "00001" => -- 0x84 PCI trace count & mode
if apbi.pwrite = '1' then
av.atpt_trans.mode := apbi.pwdata(27 downto 24);
av.atpt_trans.tcount := apbi.pwdata(23 downto 16);
av.atpt_trans.count := apbi.pwdata(PT_DEPTH-1 downto 0);
end if;
prdata(31 downto 0) := x"0" & ar.atpt_trans.mode & ar.atpt_trans.tcount & zero32(15 downto PT_DEPTH) & ar.atpt_trans.count;
when "00010" => -- 0x88 PCI trace AD pattern
if apbi.pwrite = '1' then
av.atpt_trans.ad := apbi.pwdata;
end if;
prdata(31 downto 0) := ar.atpt_trans.ad;
when "00011" => -- 0x8c PCI trace AD mask
if apbi.pwrite = '1' then
av.atpt_trans.admask := apbi.pwdata;
end if;
prdata(31 downto 0) := ar.atpt_trans.admask;
when "00100" => -- 0x90 PCI trace Signal pattern
if apbi.pwrite = '1' then
av.atpt_trans.sig := apbi.pwdata(19 downto 3);
end if;
prdata(31 downto 0) := x"000" & ar.atpt_trans.sig & "000";
when "00101" => -- 0x94 PCI trace Signal mask
if apbi.pwrite = '1' then
av.atpt_trans.sigmask := apbi.pwdata(19 downto 3);
end if;
prdata(31 downto 0) := x"000" & ar.atpt_trans.sigmask & "000";
when "00110" => -- 0x98 PCI AD
prdata(31 downto 0) := ptta_trans.dbg_ad;
when "00111" => -- 0x9c PCI Ctrl signal
prdata(19 downto 0) := ptta_trans.dbg_sig & "000";
prdata(31 downto 16) := (others => '0');
when "01000" => -- 0xA0 tmp target cur addr
prdata(31 downto 0) := ptta_trans.dbg_cur_ad;
when "01001" => -- 0xA4 tmp target cur state
prdata(31 downto 8) := (others => '0');
prdata(8 downto 0) := ptta_trans.dbg_cur_acc;
when others =>
prdata(31 downto 0) := (others => '0');
end case;
end if;
end if;
apbo.pirq <= pirq;
apbo.prdata <= prdata;
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
-- --------------------------------------------------------------------------------
-- APB DEBUG Slave
-- --------------------------------------------------------------------------------
tb_ren <= ar.s.tb_ren;
tb_addr <= ar.s.haddr;
tbpirq := (others => '0');
tbprdata := (others => '0');
tbapbaddr := tbapbi.paddr(6 downto 2);
if tbapben = 1 then
if (tbapbi.psel(tbpindex) and tbapbi.paddr(17)) = '1' then
tb_ren <= '1'; tb_addr <= tbapbi.paddr;
end if;
if (tbapbi.psel(tbpindex) and tbapbi.penable) = '1' then
if tbapbi.paddr(17) = '1' then
if tbapbi.paddr(16) = '0' then
tbprdata := pt_fifoo_ad.data;
else
tbprdata := zero32(31 downto 20) & pt_fifoo_sig.data(16 downto 0) & "000";
end if;
else
if tbapbi.paddr(7) = '0' then -- PCI core and DMA
case tbapbaddr is
when "01110" => -- 0x38 Reserved
--prdata(31 downto 0) := (others => '0');
tbprdata := ar.debug;
when "01111" => -- 0x3c Reserved
--prdata(31 downto 0) := (others => '0');
tbprdata := ar.debug_pr;
when others =>
tbprdata(31 downto 0) := (others => '0');
end case;
elsif tracebuffer /= 0 then -- PCI trace buffer enabled
case tbapbaddr is
when "00000" => -- 0x80 PCI trace control & status
if tbapbi.pwrite = '1' then
av.atpt_trans.start := ar.atpt_trans.start or tbapbi.pwdata(0);
av.atpt_trans.stop := ar.atpt_trans.stop or tbapbi.pwdata(1);
end if;
tbprdata(31 downto 0) := ar.apb_pt_stat;
when "00001" => -- 0x84 PCI trace count & mode
if tbapbi.pwrite = '1' then
av.atpt_trans.mode := tbapbi.pwdata(27 downto 24);
av.atpt_trans.tcount := tbapbi.pwdata(23 downto 16);
av.atpt_trans.count := tbapbi.pwdata(PT_DEPTH-1 downto 0);
end if;
tbprdata(31 downto 0) := x"0" & ar.atpt_trans.mode & ar.atpt_trans.tcount & zero32(15 downto PT_DEPTH) & ar.atpt_trans.count;
when "00010" => -- 0x88 PCI trace AD pattern
if tbapbi.pwrite = '1' then
av.atpt_trans.ad := tbapbi.pwdata;
end if;
tbprdata(31 downto 0) := ar.atpt_trans.ad;
when "00011" => -- 0x8c PCI trace AD mask
if tbapbi.pwrite = '1' then
av.atpt_trans.admask := tbapbi.pwdata;
end if;
tbprdata(31 downto 0) := ar.atpt_trans.admask;
when "00100" => -- 0x90 PCI trace Signal pattern
if tbapbi.pwrite = '1' then
av.atpt_trans.sig := tbapbi.pwdata(19 downto 3);
end if;
tbprdata(31 downto 0) := x"000" & ar.atpt_trans.sig & "000";
when "00101" => -- 0x94 PCI trace Signal mask
if tbapbi.pwrite = '1' then
av.atpt_trans.sigmask := tbapbi.pwdata(19 downto 3);
end if;
tbprdata(31 downto 0) := x"000" & ar.atpt_trans.sigmask & "000";
when "00110" => -- 0x98 PCI AD
tbprdata(31 downto 0) := ptta_trans.dbg_ad;
when "00111" => -- 0x9c PCI Ctrl signal
tbprdata(19 downto 0) := ptta_trans.dbg_sig & "000";
tbprdata(31 downto 16) := (others => '0');
when "01000" => -- 0xA0 tmp target cur addr
tbprdata(31 downto 0) := ptta_trans.dbg_cur_ad;
when "01001" => -- 0xA4 tmp target cur state
tbprdata(31 downto 8) := (others => '0');
tbprdata(8 downto 0) := ptta_trans.dbg_cur_acc;
when others =>
tbprdata(31 downto 0) := (others => '0');
end case;
end if;
end if;
end if;
tbapbo.pirq <= tbpirq;
tbapbo.prdata <= tbprdata;
tbapbo.pconfig <= tbpconfig;
tbapbo.pindex <= tbpindex;
else
tbapbo <= apb_none;
end if;
-- --------------------------------------------------------------------------------
-- AHB global signal assignments
-- --------------------------------------------------------------------------------
ahbso.hready <= ar.s.hready;
ahbso.hresp <= ar.s.hresp;
ahbso.hrdata <= ahbdrivedata(ar.s.hrdata);
ahbso.hindex <= hsindex;
ahbso.hconfig <= hconfig;
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
if master = 0 then
ahbso <= ahbs_none;
end if;
-- --------------------------------------------------------------------------------
-- AHB debug
-- --------------------------------------------------------------------------------
--[31:30] s_pending
--[29:28] s_empty
--[27:26] tm_pending
--[25:24] tm_empty
--[ :23] ms_acc_pending
--[ :22] ms_acc_cancel
--[ :21] ms_acc_done
--[ :20] tm_acc_pending
--[ :19] tm_acc_cancel
--[ :18] tm_acc_done
--[ :17] md_acc_pending
--[ :16] md_acc_cancel
--[ :15] md_acc_done
--[ :14] ..
--[13:12] dma_done
--[11:10] s_pending
--[ 9: 7] m_done
--[ 6: 4] dma.state
--[ 3: 2] m.state
--[ 1: 0] s.state
av.debug(31 downto 30) := ms_fifo_pending(1 downto 0);
av.debug(29 downto 28) := ms_fifo_empty(1 downto 0);
av.debug(27 downto 26) := tm_fifo_pending(1 downto 0);
av.debug(25 downto 24) := tm_fifo_empty(1 downto 0);
av.debug( 23) := ms_acc_pending;
av.debug( 22) := ms_acc_cancel;
av.debug( 21) := ms_acc_done;
av.debug( 20) := tm_acc_pending;
av.debug( 19) := tm_acc_cancel;
av.debug( 18) := tm_acc_done;
av.debug( 17) := md_acc_pending;
av.debug( 16) := md_acc_cancel;
av.debug( 15) := md_acc_done;
av.debug( 14) := '0';
av.debug(13 downto 12) := ar.dma.done;
av.debug(11 downto 10) := ar.s.pending;
av.debug( 9 downto 7) := ar.m.done;
case ar.dma.state is
when dma_idle => av.debug(6 downto 4) := "000";
when dma_read_desc => av.debug(6 downto 4) := "001";
when dma_next_channel => av.debug(6 downto 4) := "010";
when dma_write_status => av.debug(6 downto 4) := "011";
when dma_read => av.debug(6 downto 4) := "100";
when dma_write => av.debug(6 downto 4) := "101";
when dma_error => av.debug(6 downto 4) := "110";
end case;
case ar.m.state is
when am_idle => av.debug(3 downto 2) := "00";
when am_read => av.debug(3 downto 2) := "01";
when am_write => av.debug(3 downto 2) := "10";
when am_error => av.debug(3 downto 2) := "11";
when others => av.debug(3 downto 2) := "00";
end case;
case ar.s.state is
when as_idle => av.debug(1 downto 0) := "00";
when as_checkpcimst => av.debug(1 downto 0) := "01";
when as_read => av.debug(1 downto 0) := "10";
when as_write => av.debug(1 downto 0) := "11";
when others => av.debug(1 downto 0) := "00";
end case;
-- --------------------------------------------------------------------------------
-- AHB reset
-- --------------------------------------------------------------------------------
-- AHB master
lahbm_rst <= rst and not pci_target_rst and not pci_hard_rst;
if lahbm_rst = '0' then
av.m.state := am_idle;
av.m.acc.fifo_index := 0;
av.m.acc.pending := '0';
av.m.retry := '0';
av.m.dmai0.addr := (others => '0');
av.atp_trans.mstswdis := '0';
av.atp_trans.tm_acc_ack := '0';
av.atp_trans.tm_acc_cancel_ack := (others => '0');
av.atp_trans.tm_acc_done.done := '0';
for i in 0 to FIFO_COUNT-1 loop
av.atp_trans.tm_fifo(i).pending := (others => '0');
end loop;
av.atp_trans.tm_fifo_ack := (others => '0');
end if;
-- AHB slave
lahbs_rst <= rst and not pci_master_rst and not pci_hard_rst;
if lahbs_rst = '0' then
av.s.state := as_idle;
av.s.atp.index := 0;
av.s.pta.index := 0;
av.s.pending := (others => '0');
av.s.discard := '0';
av.s.start := '0';
av.s.cfg_bus := (others => '0');
av.s.cfg_status := (others => '0');
av.s.parerren := '0';
av.s.erren := '0';
av.s.blen := (others => '1');
av.s.blenmask := (others => '0');
av.s.io_cfg_burst := (others => '0');
av.s.fakehost := '0';
for i in 0 to 3 loop
av.s.accbuf(i).pending := '0';
end loop;
for j in 0 to FIFO_COUNT-1 loop
av.atp_trans.msd_fifo(0)(j).pending := (others => '0');
end loop;
av.atp_trans.msd_fifo_ack(0) := (others => '0');
av.atp_trans.msd_acc(0).pending := '0';
av.atp_trans.msd_acc_cancel(0) := '0';
av.atp_trans.msd_acc_done_ack(0) := '0';
for i in 0 to 15 loop
if multifunc = 0 then
av.s.atp_map(i)(2 downto 0) := "000";
else
for j in 0 to multifunc loop
if masters_vector(j)(i) = '1' then
av.s.atp_map(i)(2 downto 0) := conv_std_logic_vector(j, 3);
end if;
end loop;
end if;
end loop;
end if;
-- DMA
if lahbs_rst = '0' then
av.dma.state := dma_idle;
av.dma.en := '0';
av.dma.irq := '0';
av.dma.irqen := '0';
av.dma.irqstatus := (others => '0');
av.dma.errstatus := (others => '0');
av.dma.irqch := (others => '0');
av.dma.desc.chid := (others => '0');
av.dma.dtp.index := 0;
av.dma.ptd.index := 0;
for j in 0 to FIFO_COUNT-1 loop
av.atp_trans.msd_fifo(1)(j).pending := (others => '0');
end loop;
av.atp_trans.msd_fifo_ack(1) := (others => '0');
av.atp_trans.msd_acc(1).pending := '0';
av.atp_trans.msd_acc_cancel(1) := '0';
av.atp_trans.msd_acc_done_ack(1) := '0';
end if;
-- AHB reset
lahb_rst <= rst and not pci_hard_rst;
if lahb_rst = '0' then
if deviceirq = 1 then
av.irq.device_mask := conv_std_logic_vector(deviceirqmask, 4);
av.irq.device_force := '0';
end if;
if hostirq = 1 then
av.irq.host_mask := conv_std_logic_vector(hostirqmask, 4);
av.irq.host_status := (others => '0');
av.irq.host_pirq_vl := (others => '0');
end if;
av.irq.irqen := '0';
av.irq.access_en := '0';
av.irq.access_status := (others => '0');
av.irq.system_en := '0';
av.irq.system_status := (others => '0');
av.atp_trans.pa_serr_rst := '0';
av.atp_trans.pa_discardtout_rst := '0';
-- APB (PCI trace)
av.atpt_trans.start := '0';
av.atpt_trans.stop := '1';
-- Soft reset
av.atp_trans.rst(1 downto 0) := (others => '0');
end if;
if rst = '0' then
-- Hard reset
av.atp_trans.rst(2) := '0';
if iotest /= 0 then
av.debuga(5 downto 0) := "000000";
end if;
end if;
-- Disabled parts
if target = 0 then -- PCI targer disabled
av.m := amba_master_none;
av.atp_trans.tm_acc_ack := '0';
av.atp_trans.tm_acc_cancel_ack := (others => '0');
av.atp_trans.tm_acc_done := pci_g_acc_status_trans_none;
av.atp_trans.tm_fifo := pci_g_fifo_trans_vector_none;
av.atp_trans.tm_fifo_ack := pci_g_fifo_ack_trans_vector_none;
end if;
if master = 0 then -- PCI master disabled
av.s := amba_slave_none;
av.atp_trans.msd_acc(0) := pci_g_acc_trans_none;
av.atp_trans.msd_acc_cancel(0) := '0';
av.atp_trans.msd_acc_done_ack(0) := '0';
av.atp_trans.msd_fifo(0) := pci_g_fifo_trans_vector_none;
av.atp_trans.msd_fifo_ack(0) := pci_g_fifo_ack_trans_vector_none;
end if;
if dma = 0 then -- DMA disabled
av.dma := dma_reg_none;
av.atp_trans.msd_acc(1) := pci_g_acc_trans_none;
av.atp_trans.msd_acc_cancel(1) := '0';
av.atp_trans.msd_acc_done_ack(1) := '0';
av.atp_trans.msd_fifo(1) := pci_g_fifo_trans_vector_none;
av.atp_trans.msd_fifo_ack(1) := pci_g_fifo_ack_trans_vector_none;
end if;
if tracebuffer = 0 then -- PCI trace buffer disabled
av.atpt_trans := apb_to_pci_trace_trans_none;
end if;
-- --------------
arin <= av;
end process;
preg : process(pciclk, phyo)
begin
if rising_edge(pciclk) then
pr <= prin;
end if;
-- PHY =>
pr.po <= phyo.pr_po;
pr.m.state <= phyo.pr_m_state;
pr.m.last <= phyo.pr_m_last;
pr.m.hold <= phyo.pr_m_hold;
pr.m.term <= phyo.pr_m_term;
pr.t.hold <= phyo.pr_t_hold;
pr.t.stop <= phyo.pr_t_stop;
pr.t.abort <= phyo.pr_t_abort;
pr.t.diswithout <= phyo.pr_t_diswithout;
pr.t.addr_perr <= phyo.pr_t_addr_perr;
-- PHY <=
end process;
areg : process(clk)
begin
if rising_edge(clk) then ar <= arin; end if;
end process;
-- AHB master
target_ahbm0 : if target /= 0 generate
ahbm0 : grpci2_ahb_mst generic map (hindex => hmindex, devid => GAISLER_GRPCI2, version => REVISION)
port map (rst, clk, ahbmi, ahbmo_con, ar.m.dmai0, dmao0, disabled_dmai, open);
ahbmo <= ahbmo_con;
end generate;
no_target_ahbm0 : if target = 0 generate
ahbmo <= ahbm_none;
end generate;
dma_ahbm0 : if dma /= 0 generate
ahbm1 : grpci2_ahb_mst generic map (hindex => hdmindex, devid => GAISLER_GRPCI2_DMA, version => REVISION)
port map (rst, clk, ahbdmi, ahbdmo, ar.dma.dmai1, dmao1, disabled_dmai, open);
end generate;
no_dma_ahbm0 : if dma = 0 generate
ahbdmo <= ahbm_none;
end generate;
target_fifo0 : if target /= 0 generate
scan_prin_t_atp_ctrl_en <= (prin.t.atp.ctrl.en and not scanen);
scan_ar_m_acc_fifo_wen <= (ar.m.acc.fifo_wen and not scanen);
scan_arin_m_acc_fifo_ren <= (arin.m.acc.fifo_ren and not scanen);
scan_pr_t_pta_ctrl_en <= (pr.t.pta.ctrl.en and not scanen);
ft0 : if ft /= 0 generate
-- AHB master to PCI target FIFO
atp_fifo0 : syncram_2pft generic map (tech => memtech, abits => FIFO_DEPTH+log2(FIFO_COUNT),
dbits => 32, sepclk => 1, wrfst => 0, ft => ft,
testen => scantest, custombits => memtest_vlen)
port map (pciclk, scan_prin_t_atp_ctrl_en, prin.t.atp.ctrl.addr, tm_fifoo_atp.data,
clk, scan_ar_m_acc_fifo_wen, ar.m.acc.fifo_addr, ar.m.acc.fifo_wdata,
tm_fifoo_atp.err, testin
);
-- PCI target to AHB master FIFO
pta_fifo0 : syncram_2pft generic map (tech => memtech, abits => FIFO_DEPTH+log2(FIFO_COUNT),
dbits => 32, sepclk => 1, wrfst => 0, ft => ft,
testen => scantest, custombits => memtest_vlen)
port map (clk, scan_arin_m_acc_fifo_ren, arin.m.acc.fifo_addr, tm_fifoo_pta.data,
pciclk, scan_pr_t_pta_ctrl_en, pr.t.pta.ctrl.addr, pr.t.pta.ctrl.data,
tm_fifoo_pta.err, testin
);
-- AHB master to PCI target FIFO
end generate;
noft0 : if ft = 0 generate
atp_fifo0 : syncram_2p generic map (tech => memtech, abits => FIFO_DEPTH+log2(FIFO_COUNT),
dbits => 32, sepclk => 1, wrfst => 0, testen => scantest,
custombits => memtest_vlen)
port map (pciclk, scan_prin_t_atp_ctrl_en, prin.t.atp.ctrl.addr, tm_fifoo_atp.data,
clk, scan_ar_m_acc_fifo_wen, ar.m.acc.fifo_addr, ar.m.acc.fifo_wdata,
testin
);
-- PCI target to AHB master FIFO
pta_fifo0 : syncram_2p generic map (tech => memtech, abits => FIFO_DEPTH+log2(FIFO_COUNT),
dbits => 32, sepclk => 1, wrfst => 0, testen => scantest,
custombits => memtest_vlen)
port map (clk, scan_arin_m_acc_fifo_ren, arin.m.acc.fifo_addr, tm_fifoo_pta.data,
pciclk, scan_pr_t_pta_ctrl_en, pr.t.pta.ctrl.addr, pr.t.pta.ctrl.data,
testin
);
end generate;
end generate;
master_fifo0 : if master /= 0 generate
scan_prin_m_acc_acc_sel_ahb_fifo_ren <= (prin.m.acc(acc_sel_ahb).fifo_ren and not scanen);
scan_ar_s_atp_ctrl_en <= (ar.s.atp.ctrl.en and not scanen);
scan_arin_s_pta_ctrl_en <= (arin.s.pta.ctrl.en and not scanen);
scan_pr_m_acc_acc_sel_ahb_fifo_wen <= (pr.m.acc(acc_sel_ahb).fifo_wen and not scanen);
ft0 : if ft /= 0 generate
-- AHB slave to PCI master FIFO
atp_fifo1 : syncram_2pft generic map (tech => memtech, abits => FIFO_DEPTH+log2(FIFO_COUNT),
dbits => 32, sepclk => 1, wrfst => 0, ft => ft,
testen => scantest, custombits => memtest_vlen)
port map (pciclk, scan_prin_m_acc_acc_sel_ahb_fifo_ren, prin.m.fifo_addr, ms_fifoo_atp.data,
clk, scan_ar_s_atp_ctrl_en, ar.s.atp.ctrl.addr, ar.s.atp.ctrl.data,
ms_fifoo_atp.err
);
-- PCI master to AHB slave FIFO
pta_fifo1 : syncram_2pft generic map (tech => memtech, abits => FIFO_DEPTH+log2(FIFO_COUNT),
dbits => 32, sepclk => 1, wrfst => 0, ft => ft,
testen => scantest, custombits => memtest_vlen)
port map (clk, scan_arin_s_pta_ctrl_en, arin.s.pta.ctrl.addr, ms_fifoo_pta.data,
pciclk, scan_pr_m_acc_acc_sel_ahb_fifo_wen, pr.m.fifo_addr, pr.m.fifo_wdata,
ms_fifoo_pta.err
);
end generate;
noft0 : if ft = 0 generate
-- AHB slave to PCI master FIFO
atp_fifo1 : syncram_2p generic map (tech => memtech, abits => FIFO_DEPTH+log2(FIFO_COUNT),
dbits => 32, sepclk => 1, wrfst => 0,
testen => scantest, custombits => memtest_vlen)
port map (pciclk, scan_prin_m_acc_acc_sel_ahb_fifo_ren, prin.m.fifo_addr, ms_fifoo_atp.data,
clk, scan_ar_s_atp_ctrl_en, ar.s.atp.ctrl.addr, ar.s.atp.ctrl.data,
testin
);
-- PCI master to AHB slave FIFO
pta_fifo1 : syncram_2p generic map (tech => memtech, abits => FIFO_DEPTH+log2(FIFO_COUNT),
dbits => 32, sepclk => 1, wrfst => 0,
testen => scantest, custombits => memtest_vlen)
port map (clk, scan_arin_s_pta_ctrl_en, arin.s.pta.ctrl.addr, ms_fifoo_pta.data,
pciclk, scan_pr_m_acc_acc_sel_ahb_fifo_wen, pr.m.fifo_addr, pr.m.fifo_wdata,
testin
);
end generate;
end generate;
dma_fifo0 : if dma /= 0 generate
scan_prin_m_acc_acc_sel_dma_fifo_ren <= (prin.m.acc(acc_sel_dma).fifo_ren and not scanen);
scan_ar_dma_dtp_ctrl_en <= (ar.dma.dtp.ctrl.en and not scanen);
scan_arin_dma_ptd_ctrl_en <= (arin.dma.ptd.ctrl.en and not scanen);
scan_pr_m_acc_acc_sel_dma_fifo_wen <= (pr.m.acc(acc_sel_dma).fifo_wen and not scanen);
ft0 : if ft /= 0 generate
-- DMA to PCI master FIFO
dtp_fifo2 : syncram_2pft generic map (tech => memtech, abits => FIFO_DEPTH+log2(FIFO_COUNT),
dbits => 32, sepclk => 1, wrfst => 0, ft => ft,
testen => scantest, custombits => memtest_vlen)
port map (pciclk, scan_prin_m_acc_acc_sel_dma_fifo_ren, prin.m.fifo_addr, md_fifoo_dtp.data,
clk, scan_ar_dma_dtp_ctrl_en, ar.dma.dtp.ctrl.addr, ar.dma.dtp.ctrl.data,
md_fifoo_dtp.err, testin
);
-- PCI master to DMA
ptd_fifo2 : syncram_2pft generic map (tech => memtech, abits => FIFO_DEPTH+log2(FIFO_COUNT),
dbits => 32, sepclk => 1, wrfst => 0, ft => ft,
testen => scantest, custombits => memtest_vlen)
port map (clk, scan_arin_dma_ptd_ctrl_en, arin.dma.ptd.ctrl.addr, md_fifoo_ptd.data,
pciclk, scan_pr_m_acc_acc_sel_dma_fifo_wen, pr.m.fifo_addr, pr.m.fifo_wdata,
md_fifoo_dtp.err, testin
);
end generate;
noft0 : if ft = 0 generate
-- DMA to PCI master FIFO
dtp_fifo2 : syncram_2p generic map (tech => memtech, abits => FIFO_DEPTH+log2(FIFO_COUNT),
dbits => 32, sepclk => 1, wrfst => 0,
testen => scantest, custombits => memtest_vlen)
port map (pciclk, scan_prin_m_acc_acc_sel_dma_fifo_ren, prin.m.fifo_addr, md_fifoo_dtp.data,
clk, scan_ar_dma_dtp_ctrl_en, ar.dma.dtp.ctrl.addr, ar.dma.dtp.ctrl.data,
testin
);
-- PCI master to DMA
ptd_fifo2 : syncram_2p generic map (tech => memtech, abits => FIFO_DEPTH+log2(FIFO_COUNT),
dbits => 32, sepclk => 1, wrfst => 0,
testen => scantest, custombits => memtest_vlen)
port map (clk, scan_arin_dma_ptd_ctrl_en, arin.dma.ptd.ctrl.addr, md_fifoo_ptd.data,
pciclk, scan_pr_m_acc_acc_sel_dma_fifo_wen, pr.m.fifo_addr, pr.m.fifo_wdata,
testin
);
end generate;
end generate;
-- PCI trace
trace_fifo0 : if tracebuffer /= 0 generate
scan_tb_ren <= (tb_ren and not scanen);
scan_pr_ptta_trans_enable <= (pr.ptta_trans.enable and not scanen);
pt_fifo0 : syncram_2p generic map (tech => tbmemtech, abits => PT_DEPTH, dbits => 32, sepclk => 1, wrfst => 0,
testen => scantest, custombits => memtest_vlen)
port map (clk, scan_tb_ren, tb_addr(PT_DEPTH+1 downto 2), pt_fifoo_ad.data,
pciclk, scan_pr_ptta_trans_enable, pr.pt.addr, pi.ad,
testin
);
pt_fifoo_ad.err <= (others => '0');
pt_fifo1 : syncram_2p generic map (tech => tbmemtech, abits => PT_DEPTH, dbits => 17, sepclk => 1, wrfst => 0,
testen => scantest, custombits => memtest_vlen)
port map (clk, scan_tb_ren, tb_addr(PT_DEPTH+1 downto 2), pt_fifoo_sig.data(16 downto 0),
pciclk, scan_pr_ptta_trans_enable, pr.pt.addr, pcisig,
testin
);
pt_fifoo_sig.err <= (others => '0');
end generate;
-- IO test module
iotgen : if iotest /= 0 generate
iotm : synciotest
generic map (ninputs => 2, noutputs => 1, nbidir => 44)
port map (
clk => pciclk,
rstn => pcii.rst,
datain => iotmdin,
dataout => iotmdout,
tmode => ar.debuga(5 downto 0),
tmodeact => iotmact,
tmodeoe => iotmoe
);
end generate;
iotngen : if iotest = 0 generate
iotmdout <= (others => '0');
iotmact <= '0';
iotmoe <= '0';
end generate;
--pragma translate_off
bootmsg : report_version
generic map ("grpci2" & tost(hmindex) &
": 32-bit PCI/AHB bridge rev, " & tost(REVISION) &
", " & tost(2**FIFO_DEPTH) & "-word FIFOs" & ", PCI trace: " & tost(((2**PT_DEPTH)*conv_integer(conv_std_logic(tracebuffer/=0)))));
--pragma translate_on
end;
| gpl-3.0 | 79d77726e694572230d751af4689c80b | 0.517556 | 3.13142 | false | false | false | false |
kdgwill/VHDL_Framer_Example | VHDL_Framer_Example/Example2/tb_Framer_generator.vhd | 1 | 4,435 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_bit.ALL;
entity tb_framer_generator is
port (clk :out std_logic;
resetb :out std_logic;
ser_in :out std_logic);
end tb_framer_generator;
architecture testbench_gen of tb_framer_generator is
signal clock:std_logic:= '0'; ---clock signal
signal reset_n:std_logic:='0'; ---reset signal
signal bit_count:integer:=0; ---counter
signal byte_count:integer:=0; ---incoming byte count
signal din:std_logic; ---data input
signal framereg:std_logic_vector(15 downto 0); ---frame register
signal dout_payload:std_logic_vector(7 downto 0); ---data out to payload
signal dout_d1_d3:std_logic_vector(7 downto 0); ---data out to D1-D3 port
signal dout_d4_d12:std_logic_vector(7 downto 0); ---Data out to D4-D12 ports
signal F6_byte:std_logic_vector(7 downto 0):=X"F6"; ---input F6 byte
signal TE_byte:std_logic_vector(7 downto 0):=X"28"; ---input 28 byte
signal C0_byte:std_logic_vector(7 downto 0):=X"C0"; ---input C0 byte
signal d1_byte: std_logic_vector(7 downto 0):=X"02"; ---input D1 byte
signal d2_byte: std_logic_vector(7 downto 0):=X"17"; ---input D2 byte
signal d3_byte: std_logic_vector(7 downto 0):=X"81"; ---input D3 byte
signal d4_byte: std_logic_vector(7 downto 0):=X"53"; ---input Ascii S in D4 byte
signal d5_byte: std_logic_vector(7 downto 0):=X"74"; ---input t in D5 byte
signal d6_byte: std_logic_vector(7 downto 0):=X"65"; ---input e in D6 byte
signal d7_byte: std_logic_vector(7 downto 0):=X"61"; ---input a in D7 byte
signal d8_byte: std_logic_vector(7 downto 0):=X"76"; ---input v in D8 byte
signal d9_byte: std_logic_vector(7 downto 0):=X"69"; ---input i in D9 byte
signal d10_byte: std_logic_vector(7 downto 0):=X"61"; ---input a in D10 byte
signal d11_byte: std_logic_vector(7 downto 0):=X"6E"; ---input n in D11 byte
signal d12_byte: std_logic_vector(7 downto 0):=X"53"; ---input S in D12 byte
signal payload_byte:std_logic_vector(7 downto 0):=X"55"; ---payload ?55? byte
signal bit_no: integer:=7;
BEGIN
clocking: block
BEGIN
clock <= not clock after 5 ns;
END block;
Reset: PROCESS
BEGIN
reset_n <= '0';
wait for 35 ns;
reset_n <= '1';
wait until false;
END Process;
-- output ports driven by signals
clk <= clock;
resetb <= reset_n;
ser_in <= din;
--bit counter
process (clock, reset_n)
begin
if (reset_n = '0') then
bit_count <= 0;
elsif (clock'event and clock = '1') then
if (bit_count = 7) then
bit_count <= 0;
else
bit_count <= bit_count + 1;
end if;
end if;
end process;
---byte counter
process (clock, reset_n)
begin
if (reset_n = '0') then
byte_count <= 0;
elsif (clock'event and clock = '1') then
if (byte_count = 809) then
byte_count <= 0;
elsif (bit_count = 7) then
byte_count<=byte_count+1;
end if;
end if;
end process;
process(bit_count, reset_n)
begin
case byte_count is
when 0=>
din<=F6_byte(7 - bit_count);
when 1=>
din<=TE_byte(7 - bit_count);
when 2=>
din<=C0_byte(7 - bit_count);
when 3 to 89|93 to 179|183 to 269|273 to 359|363 to 449|453 to 539|543 to 629|633 to 719|723 to 809=>
din<=payload_byte(7 - bit_count);
when 180=>
din<=D1_byte(7 - bit_count);
when 181=>
din<=D2_byte(7 - bit_count);
when 182=>
din<=D3_byte(7 - bit_count);
when 450=>
din<=D4_byte(7 - bit_count);
when 451=>
din<=D5_byte(7 - bit_count);
when 452=>
din<=D6_byte(7 - bit_count);
when 540=>
din<=D7_byte(7 - bit_count);
when 541=>
din<=D8_byte(7 - bit_count);
when 542=>
din<=D9_byte(7 - bit_count);
when 630=>
din<=D10_byte(7 - bit_count);
when 631=>
din<=D11_byte(7 - bit_count);
when 632=>
din<=D12_byte(7 - bit_count);
-- when 180 to 182|270 to 272|360 to 362|450 to 452|540 to 542|630 to 632|720 to 722 =>
-- din<=d4_d12_byte(7 - bit_count);
when others=>din<='0';
end case;
end process;
end testbench_gen;
| gpl-3.0 | 9868d0b46b8be87dc79f4a599cd72a1c | 0.574746 | 3.086291 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-terasic-de0-nano/leon3mp.vhd | 1 | 20,992 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2012 Aeroflex Gaisler
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.jtag.all;
use gaisler.i2c.all;
use gaisler.spi.all;
-- pragma translate_off
use gaisler.sim.all;
-- pragma translate_on
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS;
dbguart : integer := CFG_DUART;
pclow : integer := CFG_PCLOW
);
port (
clock_50 : in std_logic;
led : inout std_logic_vector(7 downto 0);
key : in std_logic_vector(1 downto 0);
sw : in std_logic_vector(3 downto 0);
dram_ba : out std_logic_vector(1 downto 0);
dram_dqm : out std_logic_vector(1 downto 0);
dram_ras_n : out std_ulogic;
dram_cas_n : out std_ulogic;
dram_cke : out std_ulogic;
dram_clk : out std_ulogic;
dram_we_n : out std_ulogic;
dram_cs_n : out std_ulogic;
dram_dq : inout std_logic_vector(15 downto 0);
dram_addr : out std_logic_vector(12 downto 0);
epcs_data0 : in std_ulogic;
epcs_dclk : out std_ulogic;
epcs_ncso : out std_ulogic;
epcs_asdo : out std_ulogic;
i2c_sclk : inout std_logic;
i2c_sdat : inout std_logic;
g_sensor_cs_n : out std_ulogic;
g_sensor_int : in std_ulogic;
adc_cs_n : out std_ulogic;
adc_saddr : out std_ulogic;
adc_sclk : out std_ulogic;
adc_sdat : in std_ulogic;
gpio_2 : inout std_logic_vector(12 downto 0);
gpio_2_in : in std_logic_vector(2 downto 0);
gpio_1_in : in std_logic_vector(1 downto 0);
gpio_1 : inout std_logic_vector(33 downto 0);
gpio_0_in : in std_logic_vector(1 downto 0);
gpio_0 : inout std_logic_vector(33 downto 0)
);
end;
architecture rtl of leon3mp is
signal vcc, gnd : std_logic_vector(4 downto 0);
signal clkm, rstn, rstraw, sdclkl, lclk, rst, clklck : std_ulogic;
signal sdi : sdctrl_in_type;
signal sdo : sdctrl_out_type;
signal spmi : spimctrl_in_type;
signal spmo : spimctrl_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal fpi : grfpu_in_vector_type;
signal fpo : grfpu_out_vector_type;
signal stati : ahbstat_in_type;
signal gpti : gptimer_in_type;
signal i2ci : i2c_in_type;
signal i2co : i2c_out_type;
signal spii : spi_in_type;
signal spio : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal gpio0i, gpio1i, gpio2i : gpio_in_type;
signal gpio0o, gpio1o, gpio2o : gpio_out_type;
signal dsubren : std_ulogic;
signal tck, tms, tdi, tdo : std_logic;
constant BOARD_FREQ : integer := 50000; -- Board frequency in KHz, used in clkgen
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV;
constant IOAEN : integer := 1;
constant OEPOL : integer := padoen_polarity(padtech);
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
clk_pad : clkpad generic map (tech => padtech) port map (clock_50, lclk);
clkgen0 : entity work.clkgen_de0
generic map (clk_mul => CFG_CLKMUL, clk_div => CFG_CLKDIV,
clk_freq => BOARD_FREQ, sdramen => CFG_SDCTRL)
port map (inclk0 => lclk, c0 => clkm, c0_2x => open, e0 => sdclkl,
locked => clklck);
sdclk_pad : outpad generic map (tech => padtech, slew => 1)
port map (dram_clk, sdclkl);
resetn_pad : inpad generic map (tech => padtech) port map (key(0), rst);
rst0 : rstgen -- reset generator (reset is active LOW)
port map (rst, clkm, clklck, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => IOAEN,
nahbm => CFG_NCPU+CFG_AHB_JTAG,
nahbs => 6)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
----- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
cpu : for i in 0 to CFG_NCPU-1 generate
nosh : if CFG_GRFPUSH = 0 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
0, 0, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
end generate;
sh : if CFG_GRFPUSH = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3sh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
0, 0, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), fpi(i), fpo(i));
end generate;
grfpush0 : grfpushwx generic map ((CFG_FPU-1), CFG_NCPU, fabtech)
port map (clkm, rstn, fpi, fpo);
end generate;
errorn_pad : outpad generic map (tech => padtech) port map (led(6), dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0,
kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsuen_pad : inpad generic map (tech => padtech) port map (sw(0), dsui.enable);
dsubre_pad : inpad generic map (tech => padtech) port map (key(1), dsubren);
dsui.break <= not dsubren;
dsuact_pad : outpad generic map (tech => padtech) port map (led(7), dsuo.active);
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
sdctrl0 : if CFG_SDCTRL = 1 generate -- 16-bit SDRAM controller
sdc : entity work.sdctrl16
generic map (hindex => 3, haddr => 16#400#, hmask => 16#FE0#,
ioaddr => 1, fast => 0, pwron => 0, invclk => 0,
sdbits => 16, pageburst => 2)
port map (rstn, clkm, ahbsi, ahbso(3), sdi, sdo);
sa_pad : outpadv generic map (width => 13, tech => padtech)
port map (dram_addr, sdo.address(14 downto 2));
ba0_pad : outpadv generic map (tech => padtech, width => 2)
port map (dram_ba, sdo.address(16 downto 15));
sd_pad : iopadvv generic map (width => 16, tech => padtech, oepol => OEPOL)
port map (dram_dq(15 downto 0), sdo.data(15 downto 0), sdo.vbdrive(15 downto 0), sdi.data(15 downto 0));
sdcke_pad : outpad generic map (tech => padtech)
port map (dram_cke, sdo.sdcke(0));
sdwen_pad : outpad generic map (tech => padtech)
port map (dram_we_n, sdo.sdwen);
sdcsn_pad : outpad generic map (tech => padtech)
port map (dram_cs_n, sdo.sdcsn(0));
sdras_pad : outpad generic map (tech => padtech)
port map (dram_ras_n, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (dram_cas_n, sdo.casn);
sddqm_pad : outpadv generic map (tech => padtech, width => 2)
port map (dram_dqm, sdo.dqm(1 downto 0));
end generate;
spimctrl0: if CFG_SPIMCTRL /= 0 generate -- SPI Memory Controller
spimc : spimctrl
generic map (hindex => 0, hirq => 10, faddr => 16#000#, fmask => 16#f00#,
ioaddr => 16#002#, iomask => 16#fff#,
spliten => CFG_SPLIT, oepol => OEPOL,sdcard => CFG_SPIMCTRL_SDCARD,
readcmd => CFG_SPIMCTRL_READCMD, dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => CFG_SPIMCTRL_DUALOUTPUT, scaler => CFG_SPIMCTRL_SCALER,
altscaler => CFG_SPIMCTRL_ASCALER, pwrupcnt => CFG_SPIMCTRL_PWRUPCNT,
offset => CFG_SPIMCTRL_OFFSET)
port map (rstn, clkm, ahbsi, ahbso(0), spmi, spmo);
end generate;
nospimctrl0 : if CFG_SPIMCTRL = 0 generate spmo <= spimctrl_out_none; end generate;
miso_pad : inpad generic map (tech => padtech)
port map (epcs_data0, spmi.miso);
mosi_pad : outpad generic map (tech => padtech)
port map (epcs_asdo, spmo.mosi);
sck_pad : outpad generic map (tech => padtech)
port map (epcs_dclk, spmo.sck);
slvsel0_pad : outpad generic map (tech => padtech)
port map (epcs_ncso, spmo.csn);
----------------------------------------------------------------------
--- AHB ROM ---------------------------------------------------------
----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 and CFG_SPIMCTRL = 0 generate
brom : entity work.ahbrom
generic map (hindex => 0, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map (rstn, clkm, ahbsi, ahbso(0));
end generate;
noprom : if CFG_AHBROMEN = 0 and CFG_SPIMCTRL = 0 generate
ahbso(0) <= ahbs_none;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various peripherals ------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
apbo(0) <= apb_none; -- Typically occupied by memory controller
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0';
u1i.ctsn <= '0';
u1i.rxd <= '1';
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW,
ntimers => CFG_GPT_NTIM, nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti <= gpti_dhalt_drive(dsuo.tstop);
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master
i2c0 : i2cmst
generic map (pindex => 4, paddr => 4, pmask => 16#FFF#,
pirq => 3, filter => 3, dynfilt => 1)
port map (rstn, clkm, apbi, apbo(4), i2ci, i2co);
end generate;
noi2cm: if CFG_I2C_ENABLE = 0 generate
i2co.scloen <= '1'; i2co.sdaoen <= '1';
i2co.scl <= '0'; i2co.sda <= '0';
end generate;
i2c_scl_pad : iopad generic map (tech => padtech)
port map (i2c_sclk, i2co.scl, i2co.scloen, i2ci.scl);
i2c_sda_pad : iopad generic map (tech => padtech)
port map (i2c_sdat, i2co.sda, i2co.sdaoen, i2ci.sda);
spic: if CFG_SPICTRL_ENABLE = 1 generate -- SPI controller
spi1 : spictrl
generic map (pindex => 5, paddr => 5, pmask => 16#fff#, pirq => 5,
fdepth => CFG_SPICTRL_FIFO, slvselen => CFG_SPICTRL_SLVREG,
slvselsz => CFG_SPICTRL_SLVS, odmode => 0, netlist => 0,
syncram => CFG_SPICTRL_SYNCRAM, ft => CFG_SPICTRL_FT)
port map (rstn, clkm, apbi, apbo(5), spii, spio, slvsel);
spii.spisel <= '1'; -- Master only
spii.astart <= '0';
miso_pad : inpad generic map (tech => padtech)
port map (adc_sdat, spii.miso);
mosi_pad : outpad generic map (tech => padtech)
port map (adc_saddr, spio.mosi);
sck_pad : outpad generic map (tech => padtech)
port map (adc_sclk, spio.sck);
slvsel_pad : outpad generic map (tech => padtech)
port map (adc_cs_n, slvsel(0));
end generate spic;
nospi: if CFG_SPICTRL_ENABLE = 0 generate
miso_pad : inpad generic map (tech => padtech)
port map (adc_sdat, spii.miso);
mosi_pad : outpad generic map (tech => padtech)
port map (adc_saddr, vcc(0));
sck_pad : outpad generic map (tech => padtech)
port map (adc_sclk, gnd(0));
slvsel_pad : outpad generic map (tech => padtech)
port map (adc_cs_n, vcc(0));
end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GRGPIO0 port
grgpio0: grgpio
generic map( pindex => 9, paddr => 9, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH)
port map( rstn, clkm, apbi, apbo(9), gpio0i, gpio0o);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio_0(i), gpio0o.dout(i), gpio0o.oen(i), gpio0i.din(i));
end generate;
end generate;
nogpio0: if CFG_GRGPIO_ENABLE = 0 generate apbo(9) <= apb_none; end generate;
gpio1 : if CFG_GRGPIO2_ENABLE /= 0 generate -- GRGPIO1 port
grgpio1: grgpio
generic map( pindex => 10, paddr => 10, imask => CFG_GRGPIO2_IMASK, nbits => CFG_GRGPIO2_WIDTH)
port map( rstn, clkm, apbi, apbo(10), gpio1i, gpio1o);
pio_pads : for i in 0 to CFG_GRGPIO2_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio_1(i), gpio1o.dout(i), gpio1o.oen(i), gpio1i.din(i));
end generate;
end generate;
nogpio1: if CFG_GRGPIO2_ENABLE = 0 generate apbo(10) <= apb_none; end generate;
grgpio2: grgpio -- GRGPIO2 port
generic map( pindex => 11, paddr => 11, imask => 2**30, nbits => 31)
port map( rstn, clkm, apbi, apbo(11), gpio2i, gpio2o);
gpio_2_pads : iopadvv generic map (tech => padtech, width => 13)
port map (gpio_2(12 downto 0), gpio2o.dout(12 downto 0), gpio2o.oen(12 downto 0),
gpio2i.din(12 downto 0));
gpio_2_inpads : inpadv generic map (tech => padtech, width => 3)
port map (gpio_2_in, gpio2i.din(15 downto 13));
gpio_0_pads : iopadvv generic map (tech => padtech, width => 2)
port map (gpio_0(33 downto 32), gpio2o.dout(17 downto 16), gpio2o.oen(17 downto 16),
gpio2i.din(17 downto 16));
gpio_0_inpads : inpadv generic map (tech => padtech, width => 2)
port map (gpio_0_in, gpio2i.din(19 downto 18));
gpio_1_pads : iopadvv generic map (tech => padtech, width => 2)
port map (gpio_1(33 downto 32), gpio2o.dout(21 downto 20), gpio2o.oen(21 downto 20),
gpio2i.din(21 downto 20));
gpio_1_inpads : inpadv generic map (tech => padtech, width => 2)
port map (gpio_1_in, gpio2i.din(23 downto 22));
led_pads : iopadvv generic map (tech => padtech, width => 6)
port map (led(5 downto 0), gpio2o.dout(29 downto 24), gpio2o.oen(29 downto 24),
gpio2i.din(29 downto 24));
g_sensor_int_pad : inpad generic map (tech => padtech)
port map (g_sensor_int, gpio2i.din(30));
-- g_sensor_cs_n_pad : outpad generic map (tech => padtech)
-- port map (g_sensor_cs_n, gpio2o.dout(31));
g_sensor_cs_n <= '1';
-- gpio2i.din(31) <= gpio2o.dout(31);
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
stati <= ahbstat_in_none;
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 1, nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
nop2 : if CFG_AHBSTAT = 0 generate apbo(15) <= apb_none; end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
port map (rstn, clkm, ahbsi, ahbso(4));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(4) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0 : ahbrep generic map (hindex => 5, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(5));
-- pragma translate_on
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Altera DE0-EP4CE22 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-3.0 | ec6d416f9547c221fe8089032e228929 | 0.560166 | 3.596984 | false | false | false | false |
pedabraham/MDSM | crs/bitsToNumbers.vhd | 1 | 948 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity bitsToNumbers is
port(
cadenaOriginalDeBits: IN STD_LOGIC_VECTOR(8 downto 0);
numero : OUT STD_LOGIC_VECTOR(3 downto 0)
);
end bitsToNumbers;
architecture Behavioral of bitsToNumbers is
begin
process(cadenaOriginalDeBits)
begin
case cadenaOriginalDeBits is
when "100000000" => numero <= "0001";
when "010000000" => numero <= "0010";
when "001000000" => numero <= "0011";
when "000100000" => numero <= "0100";
when "000010000" => numero <= "0101";
when "000001000" => numero <= "0110";
when "000000100" => numero <= "0111";
when "000000010" => numero <= "1000";
when "000000001" => numero <= "1001";
when others => numero <= "0000";
end case;
end process;
end architecture;
| mit | 4e7b1006b7c7952040c841fa0cdcdfb7 | 0.537975 | 4.121739 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/sim/ddrram.vhd | 1 | 20,427 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddrram
-- File: ddrram.vhd
-- Author: Magnus Hjorth, Aeroflex Gaisler
-- Description: Generic simulation model of DDR SDRAM (JESD79E)
------------------------------------------------------------------------------
--pragma translate_off
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdio.hread;
use grlib.stdlib.all;
entity ddrram is
generic (
width: integer := 32;
abits: integer range 12 to 14 := 12;
colbits: integer range 8 to 13 := 8;
rowbits: integer range 1 to 14 := 12;
implbanks: integer range 1 to 4 := 1;
fname: string;
lddelay: time := (0 ns);
speedbin: integer range 0 to 5 := 0; -- 0:DDR200,1:266,2:333,3:400C,4:400B,5:400A
density: integer range 0 to 3 := 0; -- 0:128Mbit 1:256Mbit 2:512Mbit 3:1Gbit / chip
igndqs: integer range 0 to 1 := 0
);
port (
ck: in std_ulogic;
cke: in std_ulogic;
csn: in std_ulogic;
rasn: in std_ulogic;
casn: in std_ulogic;
wen: in std_ulogic;
dm: in std_logic_vector(width/8-1 downto 0);
ba: in std_logic_vector(1 downto 0);
a: in std_logic_vector(abits-1 downto 0);
dq: inout std_logic_vector(width-1 downto 0);
dqs: inout std_logic_vector(width/8-1 downto 0)
);
end;
architecture sim of ddrram is
type moderegs is record
-- Mode register (0)
opmode: std_logic_vector(6 downto 0);
caslat: std_logic_vector(2 downto 0);
bt: std_ulogic;
blen: std_logic_vector(2 downto 0);
-- Extended mode register (1)
opmode1: std_logic_vector(10 downto 0);
res1: std_ulogic;
ds: std_ulogic;
dlldis: std_ulogic;
end record;
-- Mode registers as signal, useful for debugging
signal mr: moderegs;
-- Handshaking between command and DQ/DQS processes
signal read_en, write_en: boolean := false;
signal hcmode: boolean := false; -- Shift DQS/read data one cycle for CL=1.5/2.5
signal hcread_en: boolean := false; -- One cycle earlier for half-cycle mode read preamble gen
signal read_data, write_data: std_logic_vector(2*width-1 downto 0);
signal write_mask: std_logic_vector(width/4-1 downto 0);
signal initdone: boolean := false;
-- Small delta-t to adjust calculations for jitter tol.
constant deltat: time := 50 ps;
-- Timing parameters
constant tWR: time := 15 ns;
constant tMRD_ck: integer := 2;
type timetab is array (0 to 5) of time;
constant tRAS : timetab := (50 ns, 45 ns, 42 ns, 40 ns, 40 ns, 40 ns);
constant tRP : timetab := (20 ns, 20 ns, 18 ns, 18 ns, 15 ns, 15 ns);
constant tRCD: timetab := (20 ns, 20 ns, 18 ns, 18 ns, 15 ns, 15 ns);
constant tRRD: timetab := (15 ns, 15 ns, 12 ns, 10 ns, 10 ns, 10 ns);
constant tRFC_lt1G: timetab := (80 ns, 75 ns, 72 ns, 70 ns, 70 ns, 70 ns); --Assuming<1Gb
constant tRFC_mt1G: time := 120 ns;
function tRFC return time is
begin
if density < 3 then return tRFC_lt1G(speedbin);
else return tRFC_mt1G; end if;
end tRFC;
begin
-----------------------------------------------------------------------------
-- Init sequence checker
-----------------------------------------------------------------------------
initp: process
variable cyctr : integer := 0;
procedure checkcmd(crasn,ccasn,cwen: std_ulogic;
cba: std_logic_vector(1 downto 0);
a10,a8,a0: std_ulogic) is
begin
wait until rising_edge(ck);
cyctr := cyctr+1;
while cke='1' and (csn='1' or (rasn='1' and casn='1' and wen='1')) loop
wait until rising_edge(ck);
cyctr := cyctr+1;
end loop;
assert cke='1' and csn='0' and rasn=crasn and casn=ccasn and wen=cwen and
(cba="--" or cba=ba) and (a10='-' or a10=a(10)) and (a8='-' or a8=a(8)) and
(a0='-' or a0=a(0))
report "Wrong command during init sequence" severity warning;
end checkcmd;
begin
initdone <= false;
-- Allow cke to be X or U for a while during sim start
if is_x(cke) then
wait until not is_x(cke);
end if;
assert cke='0' report "CKE not deasserted on power-up" severity warning;
wait until cke/='0' for 200 us;
assert cke='0' report "CKE raised with less than 200 us init delay" severity warning;
wait until cke/='0' and rising_edge(ck);
assert cke='1' and (csn='1' or (rasn='1' and casn='1' and wen='1'));
-- Precharge all
checkcmd('0','1','0',"--",'1','-','-');
-- EMRS enable DLL
checkcmd('0','0','0',"01",'-','-','0');
-- MRS reset DLL
checkcmd('0','0','0',"00",'-','1','-');
cyctr := 0;
-- 200 cycle NOP
-- Precharge all
checkcmd('0','1','0',"--",'1','-','-');
assert cyctr >= 200
report "Command issued too quickly after DLL reset" severity warning;
-- 2 x auto refresh
checkcmd('0','0','1',"--",'-','-','-');
checkcmd('0','0','1',"--",'-','-','-');
-- MRS !reset DLL
checkcmd('0','0','0',"00",'-','0','-');
initdone <= true;
wait;
end process;
-----------------------------------------------------------------------------
-- Command state machine
-----------------------------------------------------------------------------
cmdp: process(ck)
subtype coldata is std_logic_vector(width-1 downto 0);
type coldata_arr is array(0 to implbanks*(2**(colbits+rowbits))-1) of coldata;
variable memdata: coldata_arr;
procedure load_srec is
file TCF : text open read_mode is fname;
variable L1: line;
variable CH : character;
variable rectype : std_logic_vector(3 downto 0);
variable recaddr : std_logic_vector(31 downto 0);
variable reclen : std_logic_vector(7 downto 0);
variable recdata : std_logic_vector(0 to 16*8-1);
variable col, coloffs, len: integer;
begin
L1:= new string'("");
while not endfile(TCF) loop
readline(TCF,L1);
if (L1'length /= 0) then
while (not (L1'length=0)) and (L1(L1'left) = ' ') loop
std.textio.read(L1,CH);
end loop;
if L1'length > 0 then
read(L1, ch);
if (ch = 'S') or (ch = 's') then
hread(L1, rectype);
hread(L1, reclen);
len := to_integer(unsigned(reclen))-1;
recaddr := (others => '0');
case rectype is
when "0001" => hread(L1, recaddr(15 downto 0)); len := len - 2;
when "0010" => hread(L1, recaddr(23 downto 0)); len := len - 3;
when "0011" => hread(L1, recaddr); len := len - 4;
when others => next;
end case;
hread(L1, recdata(0 to len*8-1));
col := to_integer(unsigned(recaddr(log2(width/8)+rowbits+colbits+1 downto log2(width/8))));
coloffs := 8*to_integer(unsigned(recaddr(log2(width/8)-1 downto 0)));
while len > width/8 loop
assert coloffs=0;
memdata(col) := recdata(0 to width-1);
col := col+1;
len := len-width/8;
recdata(0 to recdata'length-width-1) := recdata(width to recdata'length-1);
end loop;
memdata(col)(width-1-coloffs downto width-coloffs-len*8) := recdata(0 to len*8-1);
end if;
end if;
end if;
end loop;
end load_srec;
variable vmr: moderegs := ((others => '0'), "UUU", 'U', "UUU", (others => '0'), '0', '0', '0');
type bankstate is record
openrow: integer;
opentime: time;
closetime: time;
writetime: time;
autopch: integer;
end record;
type bankstate_arr is array(natural range <>) of bankstate;
variable banks: bankstate_arr(3 downto 0) := (others => (-1, 0 ns, 0 ns, 0 ns, -1));
type int_arr is array(natural range <>) of integer;
type dataacc is record
r,w: boolean;
col: int_arr(0 to 1);
bank: integer;
end record;
type dataacc_arr is array(natural range <>) of dataacc;
variable accpipe: dataacc_arr(0 to 9);
variable cmd: std_logic_vector(2 downto 0);
variable bank: integer;
variable colv: unsigned(a'high-1 downto 0);
variable alow: unsigned(2 downto 0);
variable col: integer;
variable prev_re, re: time;
variable blen: integer;
variable lastref: time := 0 ns;
variable i: integer;
variable b: boolean;
variable mrscount: integer := 0;
variable loaded: boolean := false;
procedure checktime(got, exp: time; gt: boolean; req: string) is
begin
assert (got + deltat > exp and gt) or (got-deltat < exp and not gt)
report (req & " violation, got: " & tost(got/(1 ps)) & " ps, exp: " & tost(exp/(1 ps)) & "ps")
severity warning;
end checktime;
begin
if rising_edge(ck) then
-- Update pipe regs
prev_re := re;
re := now;
accpipe(1 to accpipe'high) := accpipe(0 to accpipe'high-1);
accpipe(0).r:=false; accpipe(0).w:=false;
-- Main command handler
cmd := rasn & casn & wen;
if mrscount > 0 then
mrscount := mrscount-1;
assert cke='1' and (csn='1' or cmd="111") report "tMRS violation!" severity warning;
end if;
if cke='1' and csn='0' and cmd/="111" then
checktime(now-lastref, tRFC, true, "tRFC");
end if;
if cke='1' and csn='0' then
case cmd is
when "111" => -- NOP
when "011" => -- RAS
assert initdone report "Opening row before init sequence done!" severity warning;
bank := to_integer(unsigned(ba));
assert banks(bank).openrow < 0
report "Row already open" severity warning;
checktime(now-banks(bank).closetime, tRP(speedbin), true, "tRP");
for x in 0 to 3 loop
checktime(now-banks(x).opentime, tRRD(speedbin), true, "tRRD");
end loop;
banks(bank).openrow := to_integer(unsigned(a(rowbits-1 downto 0)));
banks(bank).opentime := now;
when "101" | "100" => -- Read/Write
bank := to_integer(unsigned(ba));
assert banks(bank).openrow >= 0
report "Row not open" severity error;
checktime(now-banks(bank).opentime, tRCD(speedbin), true, "tRCD");
for x in 0 to 3 loop
-- Xilinx V4 MIG controller issues multiple overlapping load commands
-- during calibration, therefore this assertion is bypassed before
-- load-delay has passed.
assert (not accpipe(x).r and not accpipe(x).w) or (now < lddelay);
end loop;
if cmd(0)='1' then accpipe(3).r:=true; else accpipe(3).w:=true; end if;
colv := unsigned(std_logic_vector'(a(a'high downto 11) & a(9 downto 0)));
case vmr.blen is
when "001" => blen := 2;
when "010" => blen := 4;
when "011" => blen := 8;
when others => assert false report "Invalid burst length setting in MR!" severity error;
end case;
alow := unsigned(a(2 downto 0));
for x in 0 to blen-1 loop
accpipe(3-x/2).bank := bank;
if cmd(0)='1' then accpipe(3-x/2).r:=true; else accpipe(3-x/2).w:=true; end if;
if vmr.bt='0' then -- Sequential
colv(log2(blen)-1 downto 0) := alow(log2(blen)-1 downto 0) + x;
else -- Interleaved
colv(log2(blen)-1 downto 0) := alow(log2(blen)-1 downto 0) xor to_unsigned(x,log2(blen));
end if;
col := to_integer(unsigned(ba))*(2**(colbits+rowbits)) +
banks(bank).openrow * (2**colbits) + to_integer(colv(colbits-1 downto 0));
accpipe(3-x/2).col(x mod 2) := col;
end loop;
-- Auto precharge
if a(10)='1' then
if cmd(0)='1' then
banks(bank).autopch := blen/2;
else
banks(bank).autopch := 1+blen/2 + (tWR-deltat+(re-prev_re))/(re-prev_re);
end if;
end if;
when "110" => -- Burst terminate
assert not accpipe(3).w
report "Burst terminate on write burst!" severity warning;
assert banks(accpipe(3).bank).autopch<0
report "Burst terminate on read with auto-precharge!" severity warning;
assert accpipe(3).r
report "Burst terminate with no effect!" severity warning;
for x in 3 downto 0 loop
accpipe(x).r := false;
accpipe(x).w := false;
end loop;
when "010" => -- Precharge
for x in 3 downto 0 loop
accpipe(x).r := false;
accpipe(x).w := false;
end loop;
for x in 0 to 3 loop
if a(10)='1' or ba=std_logic_vector(to_unsigned(x,2)) then
assert banks(x).autopch<0
report "Precharging bank that is auto-precharged" severity note;
assert a(10)='1' or banks(x).openrow>=0
report "Precharging single bank that is in idle state" severity note;
banks(x).autopch := 0; -- Handled below
end if;
end loop;
when "001" => -- Auto refresh
for x in 0 to 3 loop
assert banks(x).openrow < 0
report "Bank in wrong state for auto refresh!" severity warning;
checktime(now-banks(x).closetime, tRP(speedbin), true, "tRP");
end loop;
lastref := now;
when "000" => -- MRS
for x in 0 to 3 loop
checktime(now-banks(x).closetime, tRP(speedbin), true, "tRP");
end loop;
case ba is
when "00" =>
vmr.opmode(a'high-7 downto 0) := a(a'high downto 7);
vmr.caslat := a(6 downto 4);
vmr.bt := a(3);
vmr.blen := a(2 downto 0);
when "01" =>
vmr.opmode1(a'high-3 downto 0) := a(a'high downto 3);
vmr.res1 := a(2);
vmr.ds := a(1);
vmr.dlldis := a(0);
when others =>
assert false report ("MRS to invalid bank addr: " & std_logic'image(ba(1)) & std_logic'image(ba(0))) severity warning;
end case;
mrscount := tMRD_ck-1;
when others =>
assert false report ("Invalid command: " & std_logic'image(rasn) & std_logic'image(casn) & std_logic'image(wen)) severity warning;
end case;
end if;
-- Manual or auto precharge
for x in 0 to 3 loop
if banks(x).autopch=0 then
checktime(now-banks(x).writetime, tWR, true, "tWR");
checktime(now-banks(x).opentime, tRAS(speedbin), true, "tRAS");
banks(x).openrow := -1;
banks(x).closetime := now;
end if;
if banks(x).autopch >= 0 then
banks(x).autopch := banks(x).autopch - 1;
end if;
end loop;
-- Read/write management
if not loaded and lddelay < now then
load_srec;
loaded := true;
end if;
case vmr.caslat is
when "010" => i := 2; b:=false; -- CL2
when "011" => i := 3; b:=false; -- CL3
when "101" => i := 2; b:=true; -- CL1.5
when "110" => i := 3; b:=true; -- CL2.5
when others => i := 1;
end case;
hcmode <= b;
if b then hcread_en <= accpipe(1+i).r; else hcread_en <= false; end if;
if accpipe(2+i).r then
assert i>1 report "Incorrect CL setting!" severity warning;
read_en <= true;
-- print("Reading from col " & tost(accpipe(2+i).col(0)) & " and " & tost(accpipe(2+i).col(1)));
-- col0 <= accpipe(2+i).col(0); col1 <= accpipe(2+i).col(1);
read_data <= memdata(accpipe(2+i).col(0)) & memdata(accpipe(2+i).col(1));
else
read_en <= false;
end if;
write_en <= accpipe(3).w or accpipe(4).w;
if accpipe(5).w and write_mask/=(write_mask'range => '1') then
assert not is_x(write_mask) report "Write error";
for x in 0 to 1 loop
for b in width/8-1 downto 0 loop
if write_mask((1-x)*width/8+b)='0' then
memdata(accpipe(5).col(x))(8*b+7 downto 8*b) :=
write_data( (1-x)*width+b*8+7 downto (1-x)*width+b*8);
end if;
end loop;
end loop;
banks(accpipe(5).bank).writetime := now;
end if;
end if;
mr <= vmr;
end process;
-----------------------------------------------------------------------------
-- DQS/DQ handling and data sampling process
-----------------------------------------------------------------------------
dqproc: process
variable rdata: std_logic_vector(2*width-1 downto 0);
variable hdata: std_logic_vector(width-1 downto 0);
variable hmask: std_logic_vector(width/8-1 downto 0);
variable prevdqs: std_logic_vector(width/8-1 downto 0);
begin
dq <= (others => 'Z');
dqs <= (others => 'Z');
wait until (hcmode and hcread_en) or read_en or write_en;
assert not ((read_en or hcread_en) and write_en);
if (read_en or hcread_en) then
if hcmode then
wait until falling_edge(ck);
end if;
dqs <= (others => '0');
wait until falling_edge(ck);
while read_en loop
rdata := read_data;
if not hcmode then
wait until rising_edge(ck);
end if;
dqs <= (others => '1');
dq <= rdata(2*width-1 downto width);
if hcmode then
wait until rising_edge(ck);
else
wait until falling_edge(ck);
end if;
dqs <= (others => '0');
dq <= rdata(width-1 downto 0);
if hcmode then
wait until falling_edge(ck);
end if;
end loop;
if not hcmode then
wait until rising_edge(ck);
end if;
else
wait until falling_edge(ck);
assert to_X01(dqs)=(dqs'range => '0') or igndqs/=0;
while write_en loop
prevdqs := to_X01(dqs);
if igndqs /= 0 then
wait on ck,write_en;
else
wait until to_X01(dqs) /= prevdqs or not write_en or rising_edge(ck);
end if;
if rising_edge(ck) then
-- Just to make sure missing DQS is not undetected
write_data <= (others => 'X');
write_mask <= (others => 'X');
end if;
for x in dqs'range loop
if (igndqs=0 and prevdqs(x)='0' and to_X01(dqs(x))='1') or (igndqs/=0 and rising_edge(ck)) then
hdata(8*x+7 downto 8*x) := dq(8*x+7 downto 8*x);
hmask(x) := dm(x);
elsif (igndqs=0 and prevdqs(x)='1' and to_X01(dqs(x))='0') or (igndqs/=0 and falling_edge(ck)) then
write_data(width+8*x+7 downto width+8*x) <= hdata(8*x+7 downto 8*x);
write_data(8*x+7 downto 8*x) <= dq(8*x+7 downto 8*x);
write_mask(width/8+x) <= hmask(x);
write_mask(x) <= dm(x);
end if;
end loop;
end loop;
end if;
end process;
end;
-- pragma translate_on
| gpl-3.0 | 5f25096db8b3dcfb1dac52830f8c8b99 | 0.532677 | 3.741894 | false | false | false | false |
hoglet67/CoPro6502 | src/DCM/dcm_32_96.vhd | 1 | 2,185 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity dcm_32_96 is
port (CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic);
end dcm_32_96;
architecture BEHAVIORAL of dcm_32_96 is
signal CLKFX_BUF : std_logic;
signal CLK2X_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKFX_BUFG_INST : BUFG
port map (I => CLKFX_BUF, O => CLK0_OUT);
CLK2X_BUFG_INST : BUFG
port map (I => CLK2X_BUF, O => CLK2X_OUT);
DCM_INST : DCM
generic map(CLK_FEEDBACK => "NONE",
CLKDV_DIVIDE => 4.0, -- 96.00 = 32.000 * 12/4
CLKFX_MULTIPLY => 12,
CLKFX_DIVIDE => 4,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => 31.25,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => true,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => false)
port map (CLKFB => GND_BIT,
CLKIN => CLKIN_IN,
DSSEN => GND_BIT,
PSCLK => GND_BIT,
PSEN => GND_BIT,
PSINCDEC => GND_BIT,
RST => GND_BIT,
CLKDV => open,
CLKFX => CLKFX_BUF,
CLKFX180 => open,
CLK0 => open,
CLK2X => CLK2X_BUF,
CLK2X180 => open,
CLK90 => open,
CLK180 => open,
CLK270 => open,
LOCKED => open,
PSDONE => open,
STATUS => open);
end BEHAVIORAL;
| gpl-3.0 | 4307a7d7e7456bdbd999ef41dfe2f363 | 0.413272 | 4.084112 | false | false | false | false |
18545/FPGA | FPGA.srcs/sources_1/ip/blk_mem_gen_0/synth/blk_mem_gen_0.vhd | 1 | 14,434 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY blk_mem_gen_0 IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END blk_mem_gen_0;
ARCHITECTURE blk_mem_gen_0_arch OF blk_mem_gen_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF blk_mem_gen_0_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(18 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF blk_mem_gen_0_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF blk_mem_gen_0_arch : ARCHITECTURE IS "blk_mem_gen_0,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF blk_mem_gen_0_arch: ARCHITECTURE IS "blk_mem_gen_0,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=blk_mem_gen_0.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=NO_CHANGE,C_WRITE_WIDTH_A=4,C_READ_WIDTH_A=4,C_WRITE_DEPTH_A=307200,C_READ_DEPTH_A=307200,C_ADDRA_WIDTH=19,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=4,C_READ_WIDTH_B=4,C_WRITE_DEPTH_B=307200,C_READ_DEPTH_B=307200,C_ADDRB_WIDTH=19,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=1,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=36,C_COUNT_18K_BRAM=3,C_EST_POWER_SUMMARY=Estimated Power for IP _ 16.198881 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 1,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "blk_mem_gen_0.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "NO_CHANGE",
C_WRITE_WIDTH_A => 4,
C_READ_WIDTH_A => 4,
C_WRITE_DEPTH_A => 307200,
C_READ_DEPTH_A => 307200,
C_ADDRA_WIDTH => 19,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 4,
C_READ_WIDTH_B => 4,
C_WRITE_DEPTH_B => 307200,
C_READ_DEPTH_B => 307200,
C_ADDRB_WIDTH => 19,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 1,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "36",
C_COUNT_18K_BRAM => "3",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 16.198881 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => addrb,
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END blk_mem_gen_0_arch;
| mit | c65617538fa3588e3e81e8bbac04b909 | 0.627892 | 3.010847 | false | false | false | false |
ARC-Lab-UF/UAA | src/flt_pkg.vhd | 1 | 2,407 | -- Copyright (c) 2015 University of Florida
--
-- This file is part of uaa.
--
-- uaa is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- uaa is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with uaa. If not, see <http://www.gnu.org/licenses/>.
-- Greg Stitt
-- University of Florida
-- flt_pkg.vhd
-- This package contains functions that specify various characteristics about
-- floating-point entities.
-- This example has been configured based on latencies of Stratix 3 cores used
-- in the *_flt entities.
library ieee;
use ieee.std_logic_1164.all;
package flt_pkg is
function add_flt_latency(core_name : string) return natural;
function mult_flt_latency(core_name : string) return natural;
end flt_pkg;
package body flt_pkg is
function add_flt_latency(core_name : string) return natural is
begin
if (core_name = "stratix3_latency") then
return 7;
elsif (core_name = "stratix3_area" or core_name = "stratix3_speed") then
return 14;
elsif (core_name = "stratix5_latency") then
return 7;
elsif (core_name = "stratix5_area" or core_name = "stratix5_speed") then
return 14;
elsif (core_name = "virtex7_latency") then
return 8;
elsif (core_name = "virtex7_speed") then
return 11;
end if;
assert(false) report "Error: No add_flt latency specified for architecture " & '"' & core_name & '"' & " in flt_pkg.vhd" severity error;
return 0;
end function;
function mult_flt_latency(core_name : string) return natural is
begin
if (core_name = "area") then
return 5;
elsif (core_name = "speed") then
return 11;
end if;
assert(false) report "Error: No latency specified for mult_flt architecture " & '"' & core_name & '"' & " in flt_pkg.vhd" severity error;
return 0;
end function;
end package body;
| gpl-3.0 | 8fd70ffbb76eb0bd37420ec139a53b93 | 0.653511 | 3.869775 | false | false | false | false |
freecores/cryptopan_core | rtl/aes_encrypt_unit.vhd | 1 | 11,312 | --
-- This file is part of the Crypto-PAn core (www.opencores.org).
--
-- Copyright (c) 2007 The University of Waikato, Hamilton, New Zealand.
-- Authors: Anthony Blake ([email protected])
--
-- All rights reserved.
--
-- This code has been developed by the University of Waikato WAND
-- research group. For further information please see http://www.wand.net.nz/
--
-- This source file is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This source is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with libtrace; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.cryptopan.all;
entity aes_encrypt_unit is
port (
key_in : in std_logic_vector(127 downto 0);
key_wren : in std_logic;
ready : out std_logic;
data_in : in std_logic_vector(127 downto 0);
data_wren : in std_logic;
data_dv : out std_logic;
data_out : out std_logic_vector(127 downto 0);
clk : in std_logic;
reset : in std_logic
);
end aes_encrypt_unit;
architecture rtl of aes_encrypt_unit is
component round_unit
generic (
do_mixcolumns : boolean);
port (
bytes_in : in s_vector;
bytes_out : out s_vector;
in_en : in std_logic;
out_en : out std_logic;
load_en : in std_logic;
load_data : in std_logic_vector(31 downto 0);
load_clk : in std_logic;
clk : in std_logic;
reset : in std_logic);
end component;
component dual_bram_256x8
port (
addra : IN std_logic_VECTOR(7 downto 0);
addrb : IN std_logic_VECTOR(7 downto 0);
clka : IN std_logic;
clkb : IN std_logic;
douta : OUT std_logic_VECTOR(7 downto 0);
doutb : OUT std_logic_VECTOR(7 downto 0));
end component;
component sbox
port (
clk : in std_logic;
reset : in std_logic;
addra : in std_logic_vector(7 downto 0);
douta : out std_logic_vector(7 downto 0));
end component;
signal cipher_key : s_vector;
signal input : s_vector;
type states is (INIT, KEY_EXP_INIT, KEY_EXP, LOADED);
signal state : states;
signal key_exp_counter : std_logic_vector(1 downto 0);
--signal round_onehot_counter : std_logic_vector(9 downto 0);
signal round_shift_counter : std_logic_vector(9 downto 0);
signal rcon : std_logic_vector(7 downto 0);
signal subword : std_logic_vector(31 downto 0);
signal subword_xor_rcon : std_logic_vector(31 downto 0);
signal cur_w : std_logic_vector(31 downto 0);
signal cur_w_rot : std_logic_vector(31 downto 0);
signal w0 : std_logic_vector(31 downto 0);
signal w1 : std_logic_vector(31 downto 0);
signal w2 : std_logic_vector(31 downto 0);
signal load_bit : std_logic;
type s_vector_array is array (0 to 10) of s_vector;
signal round_bytes : s_vector_array;
signal round_en : std_logic_vector(0 to 10);
signal round_load_en : std_logic_vector(0 to 9);
signal sbox_clk : std_logic;
signal slow_clk : std_logic;
signal clk_counter : std_logic_vector(1 downto 0);
signal key_wren_int : std_logic;
signal key_wren_counter : std_logic_vector(2 downto 0);
begin -- rtl
SLOWCLK_LOGIC: process (clk, reset)
begin
if reset = '1' then
clk_counter <= (others => '0');
elsif clk'event and clk = '1' then
clk_counter <= clk_counter + 1;
end if;
end process SLOWCLK_LOGIC;
slow_clk <= clk_counter(1);
sbox_clk <= not slow_clk;
cur_w_rot <= cur_w(23 downto 0) & cur_w(31 downto 24);
subword_xor_rcon <= (rcon xor subword(31 downto 24)) & subword(23 downto 0);
GEN_BRAM: if use_bram=true generate
GEN_SBOX_BRAM: for i in 0 to 1 generate
SBOX_i: dual_bram_256x8
port map (
addra => cur_w_rot((8*i)+7 downto (8*i)),
addrb => cur_w_rot((8*i)+23 downto (8*i)+16),
clka => sbox_clk,
clkb => sbox_clk,
douta => subword((8*i)+7 downto (8*i)),
doutb => subword((8*i)+23 downto (8*i)+16)
);
end generate GEN_SBOX_BRAM;
end generate GEN_BRAM;
GEN_NO_BRAM: if use_bram=false generate
GEN_SBOX_NO_BRAM: for i in 0 to 3 generate
SBOX_i: sbox
port map (
clk => sbox_clk,
reset => reset,
addra => cur_w_rot((8*i)+7 downto (8*i)),
douta => subword((8*i)+7 downto (8*i)) );
end generate GEN_SBOX_NO_BRAM;
end generate GEN_NO_BRAM;
round_en(0) <= data_wren;
data_dv <= round_en(10);
data_out(127 downto 120) <= round_bytes(10)(0);
data_out(119 downto 112) <= round_bytes(10)(4);
data_out(111 downto 104) <= round_bytes(10)(8);
data_out(103 downto 96) <= round_bytes(10)(12);
data_out(95 downto 88) <= round_bytes(10)(1);
data_out(87 downto 80) <= round_bytes(10)(5);
data_out(79 downto 72) <= round_bytes(10)(9);
data_out(71 downto 64) <= round_bytes(10)(13);
data_out(63 downto 56) <= round_bytes(10)(2);
data_out(55 downto 48) <= round_bytes(10)(6);
data_out(47 downto 40) <= round_bytes(10)(10);
data_out(39 downto 32) <= round_bytes(10)(14);
data_out(31 downto 24) <= round_bytes(10)(3);
data_out(23 downto 16) <= round_bytes(10)(7);
data_out(15 downto 8) <= round_bytes(10)(11);
data_out(7 downto 0) <= round_bytes(10)(15);
input(0) <= data_in(127 downto 120);
input(4) <= data_in(119 downto 112);
input(8) <= data_in(111 downto 104);
input(12) <= data_in(103 downto 96);
input(1) <= data_in(95 downto 88);
input(5) <= data_in(87 downto 80);
input(9) <= data_in(79 downto 72);
input(13) <= data_in(71 downto 64);
input(2) <= data_in(63 downto 56);
input(6) <= data_in(55 downto 48);
input(10) <= data_in(47 downto 40);
input(14) <= data_in(39 downto 32);
input(3) <= data_in(31 downto 24);
input(7) <= data_in(23 downto 16);
input(11) <= data_in(15 downto 8);
input(15) <= data_in(7 downto 0);
FIRST_ROUND_INPUT : for i in 0 to 15 generate
round_bytes(0)(i) <= cipher_key(i) xor input(i);
end generate FIRST_ROUND_INPUT;
KEYWREN_LOGIC: process (clk, reset)
begin
if reset = '1' then
key_wren_counter <= (others => '0');
elsif clk'event and clk = '1' then
if key_wren='1' then
key_wren_counter <= "100";
elsif key_wren_counter(2)='1' then
key_wren_counter <= key_wren_counter + 1;
end if;
end if;
end process KEYWREN_LOGIC;
key_wren_int <= key_wren_counter(2);
CLKLOGIC : process (slow_clk, reset)
begin
if reset = '1' then
for i in 0 to 15 loop
cipher_key(i) <= (others => '0');
end loop;
state <= INIT;
ready <= '0';
elsif slow_clk'event and slow_clk = '1' then
if key_wren_int = '1' then
cipher_key(0) <= key_in(127 downto 120);
cipher_key(4) <= key_in(119 downto 112);
cipher_key(8) <= key_in(111 downto 104);
cipher_key(12) <= key_in(103 downto 96);
cipher_key(1) <= key_in(95 downto 88);
cipher_key(5) <= key_in(87 downto 80);
cipher_key(9) <= key_in(79 downto 72);
cipher_key(13) <= key_in(71 downto 64);
cipher_key(2) <= key_in(63 downto 56);
cipher_key(6) <= key_in(55 downto 48);
cipher_key(10) <= key_in(47 downto 40);
cipher_key(14) <= key_in(39 downto 32);
cipher_key(3) <= key_in(31 downto 24);
cipher_key(7) <= key_in(23 downto 16);
cipher_key(11) <= key_in(15 downto 8);
cipher_key(15) <= key_in(7 downto 0);
state <= KEY_EXP_INIT;
end if;
if state = KEY_EXP_INIT then
state <= KEY_EXP;
end if;
if state = KEY_EXP then
if round_shift_counter(9) = '1' and key_exp_counter = "11" then
state <= LOADED;
end if;
end if;
if state = LOADED then
ready <= '1';
else
ready <= '0';
end if;
end if;
end process CLKLOGIC;
with round_shift_counter select
rcon <=
X"02" when "0000000010",
X"04" when "0000000100",
X"08" when "0000001000",
X"10" when "0000010000",
X"20" when "0000100000",
X"40" when "0001000000",
X"80" when "0010000000",
X"1b" when "0100000000",
X"36" when "1000000000",
X"01" when others;
with state select
load_bit <=
'1' when KEY_EXP,
'0' when others;
ROUNTER_CNT_LOGIC : process (slow_clk, reset)
begin
if reset = '1' then
key_exp_counter <= (others => '0');
--round_onehot_counter <= "0000000001";
round_shift_counter <= "0000000001";
w0 <= (others => '0');
w1 <= (others => '0');
w2 <= (others => '0');
cur_w <= (others => '0');
elsif slow_clk'event and slow_clk = '1' then
if key_wren_int = '1' then
w0 <= key_in(127 downto 96);
w1 <= key_in(95 downto 64);
w2 <= key_in(63 downto 32);
cur_w <= key_in(31 downto 0);
elsif state = KEY_EXP then
w0 <= w1;
w1 <= w2;
w2 <= cur_w;
if key_exp_counter = "00" then
cur_w <= subword_xor_rcon xor w0;
else
cur_w <= cur_w xor w0;
end if;
key_exp_counter <= key_exp_counter + 1;
if key_exp_counter = "11" then
round_shift_counter <= round_shift_counter(8 downto 0) & round_shift_counter(9);
end if;
end if;
end if;
end process ROUNTER_CNT_LOGIC;
ROUND_GEN : for i in 0 to 8 generate
ROUND_I : round_unit
generic map (
do_mixcolumns => true )
port map (
bytes_in => round_bytes(i),
bytes_out => round_bytes(i+1),
in_en => round_en(i),
out_en => round_en(i+1),
load_en => round_load_en(i),
load_data => cur_w,
load_clk => slow_clk,
clk => clk,
reset => reset);
end generate ROUND_GEN;
ROUND9 : round_unit
generic map (
do_mixcolumns => false)
port map (
bytes_in => round_bytes(9),
bytes_out => round_bytes(10),
in_en => round_en(9),
out_en => round_en(10),
load_en => round_load_en(9),
load_data => cur_w,
load_clk => slow_clk,
clk => clk,
reset => reset);
LOAD_EN_DELAY : process (slow_clk, reset)
begin
if reset = '1' then
round_load_en <= (others => '0');
elsif slow_clk'event and slow_clk = '1' then
for i in 0 to 9 loop
round_load_en(i) <= round_shift_counter(i) and load_bit;
end loop;
end if;
end process LOAD_EN_DELAY;
end rtl;
| gpl-2.0 | 2b917817b1df312972364d45032e2b2a | 0.572401 | 3.196383 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-digilent-atlys/ahbrom.vhd | 1 | 13,745 |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2010 Aeroflex Gaisler
----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 10;
constant bytes : integer := 976;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"821020C0";
when 16#00001# => romdata <= X"81884000";
when 16#00002# => romdata <= X"01000000";
when 16#00003# => romdata <= X"01000000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"01000000";
when 16#00006# => romdata <= X"01000000";
when 16#00007# => romdata <= X"81980000";
when 16#00008# => romdata <= X"01000000";
when 16#00009# => romdata <= X"01000000";
when 16#0000A# => romdata <= X"C0A00040";
when 16#0000B# => romdata <= X"01000000";
when 16#0000C# => romdata <= X"01000000";
when 16#0000D# => romdata <= X"11200000";
when 16#0000E# => romdata <= X"90122100";
when 16#0000F# => romdata <= X"821020A2";
when 16#00010# => romdata <= X"C222200C";
when 16#00011# => romdata <= X"82102003";
when 16#00012# => romdata <= X"C2222008";
when 16#00013# => romdata <= X"11000000";
when 16#00014# => romdata <= X"90122344";
when 16#00015# => romdata <= X"40000091";
when 16#00016# => romdata <= X"01000000";
when 16#00017# => romdata <= X"113FFC00";
when 16#00018# => romdata <= X"90122200";
when 16#00019# => romdata <= X"82102018";
when 16#0001A# => romdata <= X"C2222004";
when 16#0001B# => romdata <= X"9010202E";
when 16#0001C# => romdata <= X"40000080";
when 16#0001D# => romdata <= X"01000000";
when 16#0001E# => romdata <= X"113FFC00";
when 16#0001F# => romdata <= X"90122200";
when 16#00020# => romdata <= X"C2022008";
when 16#00021# => romdata <= X"80886004";
when 16#00022# => romdata <= X"02BFFFFC";
when 16#00023# => romdata <= X"01000000";
when 16#00024# => romdata <= X"9010202E";
when 16#00025# => romdata <= X"40000077";
when 16#00026# => romdata <= X"01000000";
when 16#00027# => romdata <= X"113FFC00";
when 16#00028# => romdata <= X"90122100";
when 16#00029# => romdata <= X"13208821";
when 16#0002A# => romdata <= X"92126091";
when 16#0002B# => romdata <= X"D2220000";
when 16#0002C# => romdata <= X"1300B140";
when 16#0002D# => romdata <= X"D2222008";
when 16#0002E# => romdata <= X"92102100";
when 16#0002F# => romdata <= X"D222200C";
when 16#00030# => romdata <= X"130011C0";
when 16#00031# => romdata <= X"92126004";
when 16#00032# => romdata <= X"D2222010";
when 16#00033# => romdata <= X"13208821";
when 16#00034# => romdata <= X"92126091";
when 16#00035# => romdata <= X"03000040";
when 16#00036# => romdata <= X"92124001";
when 16#00037# => romdata <= X"D2220000";
when 16#00038# => romdata <= X"9010202E";
when 16#00039# => romdata <= X"40000063";
when 16#0003A# => romdata <= X"01000000";
when 16#0003B# => romdata <= X"40000051";
when 16#0003C# => romdata <= X"01000000";
when 16#0003D# => romdata <= X"40000081";
when 16#0003E# => romdata <= X"01000000";
when 16#0003F# => romdata <= X"9010202E";
when 16#00040# => romdata <= X"4000005C";
when 16#00041# => romdata <= X"01000000";
when 16#00042# => romdata <= X"40000070";
when 16#00043# => romdata <= X"01000000";
when 16#00044# => romdata <= X"9010202E";
when 16#00045# => romdata <= X"40000057";
when 16#00046# => romdata <= X"01000000";
when 16#00047# => romdata <= X"A2100000";
when 16#00048# => romdata <= X"A4100000";
when 16#00049# => romdata <= X"A6103FFF";
when 16#0004A# => romdata <= X"40000074";
when 16#0004B# => romdata <= X"01000000";
when 16#0004C# => romdata <= X"80A460A0";
when 16#0004D# => romdata <= X"22800002";
when 16#0004E# => romdata <= X"90100000";
when 16#0004F# => romdata <= X"80A22000";
when 16#00050# => romdata <= X"1280000B";
when 16#00051# => romdata <= X"A404A001";
when 16#00052# => romdata <= X"80A4A010";
when 16#00053# => romdata <= X"24800008";
when 16#00054# => romdata <= X"A4100000";
when 16#00055# => romdata <= X"80A4FFFF";
when 16#00056# => romdata <= X"32800005";
when 16#00057# => romdata <= X"A4100000";
when 16#00058# => romdata <= X"A534A001";
when 16#00059# => romdata <= X"A6244012";
when 16#0005A# => romdata <= X"A4100000";
when 16#0005B# => romdata <= X"4000003D";
when 16#0005C# => romdata <= X"01000000";
when 16#0005D# => romdata <= X"80A460A0";
when 16#0005E# => romdata <= X"A2046001";
when 16#0005F# => romdata <= X"12BFFFEB";
when 16#00060# => romdata <= X"01000000";
when 16#00061# => romdata <= X"80A4FFFF";
when 16#00062# => romdata <= X"02800022";
when 16#00063# => romdata <= X"01000000";
when 16#00064# => romdata <= X"11000000";
when 16#00065# => romdata <= X"9012234F";
when 16#00066# => romdata <= X"40000040";
when 16#00067# => romdata <= X"01000000";
when 16#00068# => romdata <= X"9134E004";
when 16#00069# => romdata <= X"40000033";
when 16#0006A# => romdata <= X"90022030";
when 16#0006B# => romdata <= X"900CE00F";
when 16#0006C# => romdata <= X"80A2200A";
when 16#0006D# => romdata <= X"90022030";
when 16#0006E# => romdata <= X"36800002";
when 16#0006F# => romdata <= X"90022027";
when 16#00070# => romdata <= X"4000002C";
when 16#00071# => romdata <= X"01000000";
when 16#00072# => romdata <= X"4000001A";
when 16#00073# => romdata <= X"01000000";
when 16#00074# => romdata <= X"4000004A";
when 16#00075# => romdata <= X"01000000";
when 16#00076# => romdata <= X"80A4E000";
when 16#00077# => romdata <= X"02800006";
when 16#00078# => romdata <= X"01000000";
when 16#00079# => romdata <= X"4000001F";
when 16#0007A# => romdata <= X"01000000";
when 16#0007B# => romdata <= X"10BFFFF9";
when 16#0007C# => romdata <= X"A624E001";
when 16#0007D# => romdata <= X"11000000";
when 16#0007E# => romdata <= X"90122360";
when 16#0007F# => romdata <= X"40000027";
when 16#00080# => romdata <= X"01000000";
when 16#00081# => romdata <= X"03380000";
when 16#00082# => romdata <= X"81C04000";
when 16#00083# => romdata <= X"01000000";
when 16#00084# => romdata <= X"11000000";
when 16#00085# => romdata <= X"90122368";
when 16#00086# => romdata <= X"40000020";
when 16#00087# => romdata <= X"01000000";
when 16#00088# => romdata <= X"40000004";
when 16#00089# => romdata <= X"01000000";
when 16#0008A# => romdata <= X"10BFFFF7";
when 16#0008B# => romdata <= X"01000000";
when 16#0008C# => romdata <= X"03200000";
when 16#0008D# => romdata <= X"113FFC00";
when 16#0008E# => romdata <= X"90122100";
when 16#0008F# => romdata <= X"1300B140";
when 16#00090# => romdata <= X"92124001";
when 16#00091# => romdata <= X"D2222008";
when 16#00092# => romdata <= X"82102014";
when 16#00093# => romdata <= X"82A06001";
when 16#00094# => romdata <= X"12BFFFFF";
when 16#00095# => romdata <= X"01000000";
when 16#00096# => romdata <= X"81C3E008";
when 16#00097# => romdata <= X"01000000";
when 16#00098# => romdata <= X"0300003F";
when 16#00099# => romdata <= X"821063FF";
when 16#0009A# => romdata <= X"10BFFFF3";
when 16#0009B# => romdata <= X"01000000";
when 16#0009C# => romdata <= X"03200000";
when 16#0009D# => romdata <= X"82106100";
when 16#0009E# => romdata <= X"C2006004";
when 16#0009F# => romdata <= X"80886004";
when 16#000A0# => romdata <= X"02BFFFFC";
when 16#000A1# => romdata <= X"03200000";
when 16#000A2# => romdata <= X"82106100";
when 16#000A3# => romdata <= X"D0204000";
when 16#000A4# => romdata <= X"81C3E008";
when 16#000A5# => romdata <= X"01000000";
when 16#000A6# => romdata <= X"9A10000F";
when 16#000A7# => romdata <= X"92100008";
when 16#000A8# => romdata <= X"D00A4000";
when 16#000A9# => romdata <= X"80A20000";
when 16#000AA# => romdata <= X"02800006";
when 16#000AB# => romdata <= X"92026001";
when 16#000AC# => romdata <= X"7FFFFFF0";
when 16#000AD# => romdata <= X"01000000";
when 16#000AE# => romdata <= X"10BFFFFA";
when 16#000AF# => romdata <= X"01000000";
when 16#000B0# => romdata <= X"81C36008";
when 16#000B1# => romdata <= X"01000000";
when 16#000B2# => romdata <= X"11100000";
when 16#000B3# => romdata <= X"13000000";
when 16#000B4# => romdata <= X"92126374";
when 16#000B5# => romdata <= X"94102010";
when 16#000B6# => romdata <= X"C2024000";
when 16#000B7# => romdata <= X"92026004";
when 16#000B8# => romdata <= X"C2220000";
when 16#000B9# => romdata <= X"94A2A001";
when 16#000BA# => romdata <= X"12BFFFFC";
when 16#000BB# => romdata <= X"90022004";
when 16#000BC# => romdata <= X"81C3E008";
when 16#000BD# => romdata <= X"01000000";
when 16#000BE# => romdata <= X"11100000";
when 16#000BF# => romdata <= X"13000000";
when 16#000C0# => romdata <= X"92126374";
when 16#000C1# => romdata <= X"D41A0000";
when 16#000C2# => romdata <= X"90022008";
when 16#000C3# => romdata <= X"C2024000";
when 16#000C4# => romdata <= X"80A0400A";
when 16#000C5# => romdata <= X"1280000A";
when 16#000C6# => romdata <= X"C2026004";
when 16#000C7# => romdata <= X"80A0400B";
when 16#000C8# => romdata <= X"12800007";
when 16#000C9# => romdata <= X"92026008";
when 16#000CA# => romdata <= X"808A2040";
when 16#000CB# => romdata <= X"02BFFFF6";
when 16#000CC# => romdata <= X"01000000";
when 16#000CD# => romdata <= X"81C3E008";
when 16#000CE# => romdata <= X"90102001";
when 16#000CF# => romdata <= X"81C3E008";
when 16#000D0# => romdata <= X"90102000";
when 16#000D1# => romdata <= X"0D0A4148";
when 16#000D2# => romdata <= X"42524F4D";
when 16#000D3# => romdata <= X"3A200020";
when 16#000D4# => romdata <= X"64647232";
when 16#000D5# => romdata <= X"5F64656C";
when 16#000D6# => romdata <= X"6179203D";
when 16#000D7# => romdata <= X"20307800";
when 16#000D8# => romdata <= X"2C204F4B";
when 16#000D9# => romdata <= X"2E0D0A00";
when 16#000DA# => romdata <= X"4641494C";
when 16#000DB# => romdata <= X"45440D0A";
when 16#000DC# => romdata <= X"00000000";
when 16#000DD# => romdata <= X"12345678";
when 16#000DE# => romdata <= X"F0C3A596";
when 16#000DF# => romdata <= X"6789ABCD";
when 16#000E0# => romdata <= X"A6F1590E";
when 16#000E1# => romdata <= X"EDCBA987";
when 16#000E2# => romdata <= X"0F3C5A69";
when 16#000E3# => romdata <= X"98765432";
when 16#000E4# => romdata <= X"590EA6F1";
when 16#000E5# => romdata <= X"FFFF0000";
when 16#000E6# => romdata <= X"0000FFFF";
when 16#000E7# => romdata <= X"5AC3FFFF";
when 16#000E8# => romdata <= X"0000A53C";
when 16#000E9# => romdata <= X"01510882";
when 16#000EA# => romdata <= X"F4D908FD";
when 16#000EB# => romdata <= X"9B6F7A46";
when 16#000EC# => romdata <= X"C721271D";
when 16#000ED# => romdata <= X"00000000";
when 16#000EE# => romdata <= X"00000000";
when 16#000EF# => romdata <= X"00000000";
when 16#000F0# => romdata <= X"00000000";
when 16#000F1# => romdata <= X"00000000";
when 16#000F2# => romdata <= X"00000000";
when 16#000F3# => romdata <= X"00000000";
when 16#000F4# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
| gpl-3.0 | 2da3ba736b8bb3b864a2c42bfdce1d24 | 0.582976 | 3.088764 | false | false | false | false |
hoglet67/CoPro6502 | src/CoProSPI.vhd | 1 | 8,626 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.tube_comp_pack.all;
entity CoProSPI is
port (
-- Host
h_clk : in std_logic;
h_cs_b : in std_logic;
h_rdnw : in std_logic;
h_addr : in std_logic_vector(2 downto 0);
h_data_in : in std_logic_vector(7 downto 0);
h_data_out : out std_logic_vector(7 downto 0);
h_rst_b : in std_logic;
h_irq_b : out std_logic;
-- Parasite Clock (32 MHz)
p_clk : in std_logic;
-- SPI Slave
p_spi_ssel : in std_logic;
p_spi_sck : in std_logic;
p_spi_mosi : in std_logic;
p_spi_miso : out std_logic;
-- Interrupts/Control
p_irq_b : out std_logic;
p_nmi_b : out std_logic;
p_rst_b : out std_logic;
-- Test signals for debugging
test : out std_logic_vector(7 downto 0)
);
end;
architecture BEHAVIORAL of CoProSPI is
-- SPI state is simply a counter for the 16 clock cycles in
-- the SPI transaction
signal spi_state : integer range 0 to 15;
-- Indicates the current transaction is valid
signal valid : std_logic;
-- SPI data out shift register (MISO is bit 7 of this)
signal spi_shifter : std_logic_vector (7 downto 0);
-- Event passing from the SPI to Tube clock domain
signal tube_go : std_logic;
signal tube_go1 : std_logic;
signal tube_go2 : std_logic;
-- Signals driving the tube chip
signal p_rst_b_int : std_logic;
signal p_cs_b : std_logic;
signal p_rdnw : std_logic;
signal p_addr : std_logic_vector (2 downto 0);
signal p_data_in : std_logic_vector (7 downto 0);
signal p_data_out : std_logic_vector (7 downto 0);
-- Latched data out of the tube chip
signal p_data_out_r : std_logic_vector (7 downto 0);
-- Tube state is pretty simple as well
type TUBE_STATE_TYPE is (
IDLE,
READ,
WRITE
);
signal tube_state : TUBE_STATE_TYPE := IDLE;
begin
---------------------------------------------------------------------
-- instantiated components
---------------------------------------------------------------------
inst_tube: tube port map (
-- host
h_addr => h_addr,
h_cs_b => h_cs_b,
h_data_in => h_data_in,
h_data_out => h_data_out,
h_phi2 => not h_clk,
h_rdnw => h_rdnw,
h_rst_b => h_rst_b,
h_irq_b => h_irq_b,
-- parasite
p_addr => p_addr,
p_cs_b => p_cs_b,
p_data_in => p_data_in,
p_data_out => p_data_out,
p_rdnw => p_rdnw,
p_phi2 => p_clk,
p_rst_b => p_rst_b_int,
p_nmi_b => p_nmi_b,
p_irq_b => p_irq_b
);
p_rst_b <= p_rst_b_int;
---------------------------------------------------------------------
-- State Machine Running from the SPI clock
---------------------------------------------------------------------
process(p_spi_sck, p_spi_ssel)
begin
if p_spi_ssel = '1' then
-- this can only be an asynchronous reset
spi_state <= 0;
else
-- This works in Mode 0 only...
-- MOSI should be sampled on the rising edge
if rising_edge(p_spi_sck) then
-- capture the important bits from the transaction
case spi_state is
when 0 =>
-- Ignore commands where B7=0
valid <= p_spi_mosi;
when 1 =>
p_rdnw <= p_spi_mosi;
when 2 =>
p_addr(2) <= p_spi_mosi;
when 3 =>
p_addr(1) <= p_spi_mosi;
when 4 =>
p_addr(0) <= p_spi_mosi;
-- This is the earliest we can ask for a read request
if valid = '1' and p_rdnw = '1' then
-- An edge signifies the read request
tube_go <= not tube_go;
end if;
when 8 =>
p_data_in(7) <= p_spi_mosi;
when 9 =>
p_data_in(6) <= p_spi_mosi;
when 10 =>
p_data_in(5) <= p_spi_mosi;
when 11 =>
p_data_in(4) <= p_spi_mosi;
when 12 =>
p_data_in(3) <= p_spi_mosi;
when 13 =>
p_data_in(2) <= p_spi_mosi;
when 14 =>
p_data_in(1) <= p_spi_mosi;
when 15 =>
p_data_in(0) <= p_spi_mosi;
-- This is the earliest we can ask for a write request
if valid = '1' and p_rdnw = '0' then
-- An edge signifies the read request
tube_go <= not tube_go;
end if;
when others =>
null;
end case;
end if;
-- This works in Mode 0 only...
-- MISO should change on the falling edge
-- For very high speeds (e.g. 32MHz) change this to rising_edge
if falling_edge(p_spi_sck) then
case spi_state is
when 7 =>
-- is it a valid read cycle?
if valid = '1' and p_rdnw = '1' then
-- load the shift register just in time...
spi_shifter <= p_data_out_r;
else
spi_shifter <= (others => '0');
end if;
when 8 to 14 =>
-- shift the shift register one place to the left
spi_shifter <= spi_shifter(6 downto 0) & '0';
when others =>
spi_shifter <= (others => '0');
end case;
-- for convenience, internal state also changes on this edge
spi_state <= spi_state + 1;
end if;
end if;
end process;
-- MISO is simply the MS bit of the shift regster
p_spi_miso <= spi_shifter(7);
---------------------------------------------------------------------
-- State Machine Running from the tube clock
---------------------------------------------------------------------
process(p_clk)
begin
if rising_edge(p_clk) then
-- Synchronize the tube go signal
tube_go1 <= tube_go;
tube_go2 <= tube_go1;
if p_rst_b_int = '0' then
tube_state <= IDLE;
p_cs_b <= '1';
else
case tube_state is
when IDLE =>
-- Wait for an edge on tube_go
if tube_go1 /= tube_go2 then
-- assert CS for on the next clock edge
p_cs_b <= '0';
if p_rdnw = '0' then
tube_state <= WRITE;
else
tube_state <= READ;
end if;
else
p_cs_b <= '1';
end if;
-- Process write command
when WRITE =>
-- deassert CS on the next clock edge
p_cs_b <= '1';
-- back to idle
tube_state <= IDLE;
-- Process read command
when READ =>
-- deassert CS on the next clock edge
p_cs_b <= '1';
-- latch the data read out of the tube chip
p_data_out_r <= p_data_out;
-- back to idle
tube_state <= IDLE;
-- Should never get here
when others =>
tube_state <= IDLE;
end case;
end if;
end if;
end process;
test <= std_logic_vector(to_unsigned(spi_state, 4)) & p_cs_b & p_addr;
end BEHAVIORAL;
| gpl-3.0 | 0fe36243ac4240e5c0a07d7d5e5d210d | 0.399954 | 4.222222 | false | false | false | false |
yishinli/emc2 | src/hal/drivers/mesa-hostmot2/firmware/src/uartr8.vhd | 1 | 8,332 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
-- http://www.mesanet.com
--
-- This program is is licensed under a disjunctive dual license giving you
-- the choice of one of the two following sets of free software/open source
-- licensing terms:
--
-- * GNU General Public License (GPL), version 2.0 or later
-- * 3-clause BSD License
--
--
-- The GNU GPL License:
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- The 3-clause BSD License:
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- * Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- * Neither the name of Mesa Electronics nor the names of its
-- contributors may be used to endorse or promote products
-- derived from this software without specific prior written
-- permission.
--
--
-- Disclaimer:
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Simple UART
entity uartr8 is
port (
clk : in std_logic;
ibus : in std_logic_vector(7 downto 0);
obus : out std_logic_vector(7 downto 0);
popfifo : in std_logic;
loadbitratel : in std_logic;
loadbitrateh : in std_logic;
readbitratel : in std_logic;
readbitrateh : in std_logic;
clrfifo : in std_logic;
readfifocount : in std_logic;
loadmode : in std_logic;
readmode : in std_logic;
fifohasdata : out std_logic;
rxmask : in std_logic;
rxdata : in std_logic
);
end uartr8;
architecture Behavioral of uartr8 is
-- FIFO related signals
signal pushdata: std_logic_vector(7 downto 0);
signal popadd: std_logic_vector(3 downto 0) := x"f";
signal popdata: std_logic_vector(7 downto 0);
signal datacounter: std_logic_vector(4 downto 0);
signal push: std_logic;
signal pop: std_logic;
signal clear: std_logic;
signal lfifoempty: std_logic;
signal lfifohasdata: std_logic;
-- uart interface related signals
constant DDSWidth : integer := 16;
signal BitrateDDSReg : std_logic_vector(DDSWidth-1 downto 0);
signal BitrateDDSAccum : std_logic_vector(DDSWidth-1 downto 0);
alias DDSMSB : std_logic is BitrateDDSAccum(15);
signal OldDDSMSB: std_logic;
signal SampleTime: std_logic;
signal BitCount : std_logic_vector(3 downto 0);
signal SReg: std_logic_vector(9 downto 0);
alias SregData: std_logic_vector(7 downto 0)is SReg(8 downto 1);
alias StartBit: std_logic is Sreg(0);
alias StopBit: std_logic is Sreg(9);
signal RXPipe : std_logic_vector(1 downto 0);
signal Go: std_logic;
signal DAV: std_logic;
signal ModeReg: std_logic_vector(3 downto 0);
alias FalseStart: std_logic is ModeReg(0);
alias OverRun: std_logic is ModeReg(1);
alias RXMaskEn: std_logic is ModeReg(3);
component SRL16E
--
generic (INIT : bit_vector);
--
port (D : in std_logic;
CE : in std_logic;
CLK : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component;
begin
fifosrl: for i in 0 to 7 generate
asr16e: SRL16E generic map (x"0000") port map(
D => pushdata(i),
CE => push,
CLK => clk,
A0 => popadd(0),
A1 => popadd(1),
A2 => popadd(2),
A3 => popadd(3),
Q => popdata(i)
);
end generate;
afifo: process (clk,popdata,datacounter)
begin
if rising_edge(clk) then
if push = '1' and pop = '0' and datacounter /= 16 then -- a push
-- always increment the data counter if not full
datacounter <= datacounter +1;
popadd <= popadd +1; -- popadd must follow data down shiftreg
end if;
if (pop = '1') and (push = '0') then -- a pop
datacounter <= datacounter - 1;
popadd <= popadd -1;
end if;
if clear = '1' then -- a clear fifo
popadd <= (others => '1');
datacounter <= (others => '0');
end if;
end if; -- clk rise
if datacounter = 0 then
lfifoempty <= '1';
else
lfifoempty <= '0';
end if;
fifohasdata <= not lfifoempty;
end process afifo;
asimpleuartrx: process (clk)
begin
if rising_edge(clk) then
RXPipe <= RXPipe(0) & rxdata; -- Two stage rx data pipeline to compensate for
-- two clock delay from start bit detection to acquire loop startup
if Go = '1' then
BitRateDDSAccum <= BitRateDDSAccum + BitRateDDSReg;
if SampleTime = '1' then
if BitCount = 0 then
Go <= '0';
DAV <= '1';
if RXPipe(1) = '0' then
OverRun <= '1';
end if;
end if;
if BitCount = "1001" then -- false start bit check
if RXPipe(1) = '1' then
Go <= '0';
FalseStart <= '1';
end if;
end if;
SReg <= RXPipe(1) & SReg(9 downto 1); -- right shift = LSb first
BitCount <= BitCount -1;
end if;
else
BitRateDDSAccum <= (others => '0');
BitCount <= "1001";
end if;
if Go = '0' and rxdata = '0' and (rxmask and RXMaskEn) = '0' then -- start bit detection
Go <= '1';
end if;
if DAV = '1' then -- DAV is just one clock wide
DAV <= '0';
end if;
OldDDSMSB <= DDSMSB; -- for Phase accumulator MSB edge detection
if loadbitratel = '1' then
BitRateDDSReg(7 downto 0) <= ibus;
end if;
if loadbitrateh = '1' then
BitRateDDSReg(15 downto 8) <= ibus;
end if;
if loadmode= '1' then
ModeReg <= ibus(3 downto 0);
end if;
end if; -- clk
SampleTime <= (not OldDDSMSB) and DDSMSB; -- sample on rising edge of DDS MSB
pushdata <= SRegData;
push <= DAV;
pop <= popfifo;
clear <= clrfifo;
obus <= (others => 'Z');
if readfifocount = '1' then
obus(4 downto 0) <= datacounter;
obus(7 downto 5) <= (others => '0');
end if;
if readbitratel = '1' then
obus <= BitRateDDSReg(7 downto 0);
end if;
if readbitrateh = '1' then
obus <= BitRateDDSReg(15 downto 8);
end if;
if popfifo = '1' then
obus <= popdata;
end if;
if readmode = '1' then
obus(3 downto 0) <= ModeReg;
obus(6) <= rxmask;
obus(7) <= not lfifoempty;
end if;
fifohasdata <= not lfifoempty;
end process asimpleuartrx;
end Behavioral;
| lgpl-2.1 | 0526c8b73e15993a951323c397b0fa18 | 0.629261 | 3.320845 | false | false | false | false |
hoglet67/CoPro6502 | src/T80/T8080se.vhd | 3 | 6,367 | -- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- 8080 compatible microprocessor core, synchronous top level with clock enable
-- Different timing than the original 8080
-- Inputs needs to be synchronous and outputs may glitch
--
-- Version : 0242
--
-- Copyright (c) 2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
-- STACK status output not supported
--
-- File history :
--
-- 0237 : First version
--
-- 0238 : Updated for T80 interface change
--
-- 0240 : Updated for T80 interface change
--
-- 0242 : Updated for T80 interface change
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T8080se is
generic(
Mode : integer := 2; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
T2Write : integer := 0 -- 0 => WR_n active in T3, /=0 => WR_n active in T2
);
port(
RESET_n : in std_logic;
CLK : in std_logic;
CLKEN : in std_logic;
READY : in std_logic;
HOLD : in std_logic;
INT : in std_logic;
INTE : out std_logic;
DBIN : out std_logic;
SYNC : out std_logic;
VAIT : out std_logic;
HLDA : out std_logic;
WR_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0)
);
end T8080se;
architecture rtl of T8080se is
signal IntCycle_n : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal IORQ : std_logic;
signal INT_n : std_logic;
signal HALT_n : std_logic;
signal BUSRQ_n : std_logic;
signal BUSAK_n : std_logic;
signal DO_i : std_logic_vector(7 downto 0);
signal DI_Reg : std_logic_vector(7 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0);
signal One : std_logic;
begin
INT_n <= not INT;
BUSRQ_n <= HOLD;
HLDA <= not BUSAK_n;
SYNC <= '1' when TState = "001" else '0';
VAIT <= '1' when TState = "010" else '0';
One <= '1';
DO(0) <= not IntCycle_n when TState = "001" else DO_i(0); -- INTA
DO(1) <= Write when TState = "001" else DO_i(1); -- WO_n
DO(2) <= DO_i(2); -- STACK not supported !!!!!!!!!!
DO(3) <= not HALT_n when TState = "001" else DO_i(3); -- HLTA
DO(4) <= IORQ and Write when TState = "001" else DO_i(4); -- OUT
DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0'; -- M1
DO(6) <= IORQ and not Write when TState = "001" else DO_i(6); -- INP
DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7); -- MEMR
u0 : T80
generic map(
Mode => Mode,
IOWait => 0)
port map(
CEN => CLKEN,
M1_n => open,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => open,
HALT_n => HALT_n,
WAIT_n => READY,
INT_n => INT_n,
NMI_n => One,
RESET_n => RESET_n,
BUSRQ_n => One,
BUSAK_n => BUSAK_n,
CLK_n => CLK,
A => A,
DInst => DI,
DI => DI_Reg,
DO => DO_i,
MC => MCycle,
TS => TState,
IntCycle_n => IntCycle_n,
IntE => INTE);
process (RESET_n, CLK)
begin
if RESET_n = '0' then
DBIN <= '0';
WR_n <= '1';
DI_Reg <= "00000000";
elsif CLK'event and CLK = '1' then
if CLKEN = '1' then
DBIN <= '0';
WR_n <= '1';
if MCycle = "001" then
if TState = "001" or (TState = "010" and READY = '0') then
DBIN <= IntCycle_n;
end if;
else
if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then
DBIN <= '1';
end if;
if T2Write = 0 then
if TState = "010" and Write = '1' then
WR_n <= '0';
end if;
else
if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then
WR_n <= '0';
end if;
end if;
end if;
if TState = "010" and READY = '1' then
DI_Reg <= DI;
end if;
end if;
end if;
end process;
end;
| gpl-3.0 | 2e08b562155df26070cd9f28931c05e2 | 0.578137 | 3.280268 | false | false | false | false |
hoglet67/CoPro6502 | src/PDP2011/cpuregs.vhd | 1 | 4,084 |
--
-- Copyright (c) 2008-2015 Sytse van Slooten
--
-- Permission is hereby granted to any person obtaining a copy of these VHDL source files and
-- other language source files and associated documentation files ("the materials") to use
-- these materials solely for personal, non-commercial purposes.
-- You are also granted permission to make changes to the materials, on the condition that this
-- copyright notice is retained unchanged.
--
-- The materials are distributed in the hope that they will be useful, but WITHOUT ANY WARRANTY;
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
--
-- $Revision: 1.17 $
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity cpuregs is
port(
raddr : in std_logic_vector(5 downto 0);
waddr : in std_logic_vector(5 downto 0);
d : in std_logic_vector(15 downto 0);
o : out std_logic_vector(15 downto 0);
we : in std_logic;
clk : in std_logic
);
end cpuregs;
architecture implementation of cpuregs is
subtype mem_unit is std_logic_vector(15 downto 0);
type mem_type is array(15 downto 0) of mem_unit;
signal regs : mem_type := mem_type'(
mem_unit'("0000000000000000"),
mem_unit'("0000000000000000"),
mem_unit'("0000000000000000"),
mem_unit'("0000000000000000"),
mem_unit'("0000000000000000"),
mem_unit'("0000000000000000"),
mem_unit'("0000000000000000"),
mem_unit'("0000000000000000"),
mem_unit'("0000000000000000"),
mem_unit'("0000000000000000"),
mem_unit'("0000000000000000"),
mem_unit'("0000000000000000"),
mem_unit'("0000000000000000"),
mem_unit'("0000000000000000"),
mem_unit'("0000000000000000"),
mem_unit'("0000000000000000")
);
signal r_loc : std_logic_vector(3 downto 0);
signal w_loc : std_logic_vector(3 downto 0);
signal r0k : std_logic_vector(15 downto 0);
signal r1k : std_logic_vector(15 downto 0);
signal r2k : std_logic_vector(15 downto 0);
signal r3k : std_logic_vector(15 downto 0);
signal r4k : std_logic_vector(15 downto 0);
signal r5k : std_logic_vector(15 downto 0);
signal r6k : std_logic_vector(15 downto 0);
signal r6s : std_logic_vector(15 downto 0);
signal r6u : std_logic_vector(15 downto 0);
begin
r0k <= regs(conv_integer(0));
r1k <= regs(conv_integer(1));
r2k <= regs(conv_integer(2));
r3k <= regs(conv_integer(3));
r4k <= regs(conv_integer(4));
r5k <= regs(conv_integer(5));
r6k <= regs(conv_integer(6));
r6s <= regs(conv_integer(14));
r6u <= regs(conv_integer(15));
r_loc <=
raddr(3 downto 0) when raddr(2 downto 1) /= "11" else -- kernel 0-5 loc 0-5, u 0-5 loc 8-13
"0110" when raddr(2 downto 0) = "110" and raddr(5 downto 4) = "00" else -- kernel sp loc 6
"1110" when raddr(2 downto 0) = "110" and raddr(5 downto 4) = "01" else -- super sp loc 14
"1111" when raddr(2 downto 0) = "110" and raddr(5 downto 4) = "11" else -- user sp loc 15
"0111"; -- invalid
w_loc <=
waddr(3 downto 0) when waddr(2 downto 1) /= "11" else -- kernel 0-5 loc 0-5, u 0-5 loc 8-13
"0110" when waddr(2 downto 0) = "110" and waddr(5 downto 4) = "00" else -- kernel sp loc 6
"1110" when waddr(2 downto 0) = "110" and waddr(5 downto 4) = "01" else -- super sp loc 14
"1111" when waddr(2 downto 0) = "110" and waddr(5 downto 4) = "11" else -- user sp loc 15
"0111"; -- invalid
process(clk, we, w_loc, d)
begin
if clk = '1' and clk'event then
if we = '1' and w_loc /= "0111" then
regs(conv_integer(w_loc)) <= d;
end if;
end if;
end process;
process(r_loc, regs, raddr)
begin
if r_loc /= "0111" then
o <= regs(conv_integer(r_loc));
else
o <= (others => '0');
end if;
end process;
end implementation;
| gpl-3.0 | edeb63bae30740fc251163931814de21 | 0.608227 | 3.499572 | false | false | false | false |
makestuff/mem-ctrl | vhdl/mem_ctrl_rtl.vhdl | 1 | 8,550 | --
-- Copyright (C) 2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture rtl of mem_ctrl is
type StateType is (
-- Initialisation states
S_INIT_WAIT,
S_INIT_PRE,
S_INIT_REF1,
S_INIT_REF1_WAIT,
S_INIT_REF2,
S_INIT_REF2_WAIT,
S_INIT_LMR,
S_INIT_LMR_WAIT,
-- Execute a write
S_WRITE1,
S_WRITE2,
S_WRITE3,
-- Execute a read
S_READ1,
S_READ2,
S_READ3,
-- Do a refresh operation
S_REFRESH,
-- Execute an interruptable refresh
S_IDLE
);
constant RAM_NOP : std_logic_vector(2 downto 0) := "111";
constant RAM_ACT : std_logic_vector(2 downto 0) := "011";
constant RAM_READ : std_logic_vector(2 downto 0) := "101";
constant RAM_WRITE : std_logic_vector(2 downto 0) := "100";
constant RAM_PRE : std_logic_vector(2 downto 0) := "010";
constant RAM_REF : std_logic_vector(2 downto 0) := "001";
constant RAM_LMR : std_logic_vector(2 downto 0) := "000";
-- Reserved
-- / Write Burst Mode (0=Burst, 1=Single)
-- / / Reserved
-- / / / Latency Mode (CL=2)
-- / / / / Burst Type (0=Sequential, 1=Interleaved)
-- / / / / / Burst Length (1,2,4,8,X,X,X,Full)
-- / / / / / /
-- / / / / / /
constant LMR_VALUE : std_logic_vector(11 downto 0) := "00" & "1" & "00" & "010" & "0" & "000";
signal state : StateType := S_INIT_WAIT;
signal state_next : StateType;
signal count : unsigned(12 downto 0) := INIT_COUNT;
signal count_next : unsigned(12 downto 0);
signal rowAddr : std_logic_vector(8 downto 0) := (others => '0');
signal rowAddr_next : std_logic_vector(8 downto 0);
signal bankAddr : std_logic_vector(1 downto 0) := (others => '0');
signal bankAddr_next : std_logic_vector(1 downto 0);
signal wrData : std_logic_vector(15 downto 0) := (others => '0');
signal wrData_next : std_logic_vector(15 downto 0);
begin
-- Infer registers
process(clk_in)
begin
if ( rising_edge(clk_in) ) then
if ( reset_in = '1' ) then
state <= S_INIT_WAIT;
count <= INIT_COUNT;
rowAddr <= (others => '0');
bankAddr <= (others => '0');
wrData <= (others => '0');
else
state <= state_next;
count <= count_next;
rowAddr <= rowAddr_next;
bankAddr <= bankAddr_next;
wrData <= wrData_next;
end if;
end if;
end process;
-- Next state logic
process(
state, count, mcAutoMode_in, mcCmd_in, mcAddr_in, mcData_in, rowAddr, bankAddr, wrData,
ramData_io)
begin
-- Internal signal defaults
state_next <= state;
rowAddr_next <= rowAddr;
bankAddr_next <= bankAddr;
wrData_next <= wrData;
if ( count = 0 ) then
count_next <= count;
else
count_next <= count - 1;
end if;
-- Client interface defaults
mcReady_out <= '0';
mcRDV_out <= '0';
mcData_out <= (others => 'X');
-- SDRAM interface defaults
ramCmd_out <= RAM_NOP;
ramBank_out <= (others => 'X');
ramAddr_out <= (others => 'X');
ramData_io <= (others => 'Z');
case state is
----------------------------------------------------------------------------------------
-- The init sequence: 4800 NOPs, PRE all, 2xREF, & LMR
----------------------------------------------------------------------------------------
-- Issue NOPs until the count hits the threshold
when S_INIT_WAIT =>
if ( count = 0 ) then
state_next <= S_INIT_PRE;
end if;
-- Issue a PRECHARGE command to all banks
when S_INIT_PRE =>
state_next <= S_INIT_REF1;
ramCmd_out <= RAM_PRE;
ramAddr_out(10) <= '1'; -- A10=1: Precharge all banks
-- Issue a refresh command. Must wait 63ns (four clocks, conservatively)
when S_INIT_REF1 =>
state_next <= S_INIT_REF1_WAIT;
ramCmd_out <= RAM_REF;
count_next <= REFRESH_LENGTH;
when S_INIT_REF1_WAIT => -- Three NOPs
if ( count = 0 ) then
state_next <= S_INIT_REF2;
end if;
-- Issue a refresh command. Must wait 63ns (four clocks, conservatively)
when S_INIT_REF2 =>
state_next <= S_INIT_REF2_WAIT;
ramCmd_out <= RAM_REF;
count_next <= REFRESH_LENGTH;
when S_INIT_REF2_WAIT => -- Three NOPs
if ( count = 0 ) then
state_next <= S_INIT_LMR;
end if;
-- Issue a Load Mode Register command. Must wait tMRD (two clocks).
when S_INIT_LMR =>
state_next <= S_INIT_LMR_WAIT;
ramCmd_out <= RAM_LMR;
ramAddr_out <= LMR_VALUE;
when S_INIT_LMR_WAIT =>
count_next <= REFRESH_DELAY;
state_next <= S_IDLE;
-------------------------------------------------------------------------------------------
-- Do a write
-------------------------------------------------------------------------------------------
when S_WRITE1 =>
state_next <= S_WRITE2;
ramCmd_out <= RAM_WRITE;
ramData_io <= wrData;
ramBank_out <= bankAddr;
ramAddr_out <= "000" & rowAddr;
when S_WRITE2 =>
state_next <= S_WRITE3;
when S_WRITE3 =>
ramCmd_out <= RAM_PRE;
ramAddr_out(10) <= '1'; -- A10=1: Precharge all banks
state_next <= S_IDLE;
-------------------------------------------------------------------------------------------
-- Do a read
-------------------------------------------------------------------------------------------
when S_READ1 =>
state_next <= S_READ2;
ramCmd_out <= RAM_READ;
ramBank_out <= bankAddr;
ramAddr_out <= "000" & rowAddr; -- no auto precharge
when S_READ2 =>
state_next <= S_READ3;
when S_READ3 =>
ramCmd_out <= RAM_PRE;
ramAddr_out(10) <= '1'; -- A10=1: Precharge all banks
mcData_out <= ramData_io;
mcRDV_out <= '1';
state_next <= S_IDLE;
-------------------------------------------------------------------------------------------
-- Refresh
-------------------------------------------------------------------------------------------
when S_REFRESH =>
if ( count = 0 ) then
state_next <= S_IDLE;
count_next <= REFRESH_DELAY;
end if;
-------------------------------------------------------------------------------------------
-- S_IDLE, etc
-------------------------------------------------------------------------------------------
when others =>
if ( count = 0 and mcAutoMode_in = '1' ) then
state_next <= S_REFRESH;
ramCmd_out <= RAM_REF;
count_next <= REFRESH_LENGTH;
else
mcReady_out <= '1';
case mcCmd_in is
when MC_REF =>
state_next <= S_REFRESH;
ramCmd_out <= RAM_REF;
count_next <= REFRESH_LENGTH;
when MC_RD =>
state_next <= S_READ1;
ramCmd_out <= RAM_ACT;
ramAddr_out <= mcAddr_in(21 downto 10);
ramBank_out <= mcAddr_in(9 downto 8);
rowAddr_next <= mcAddr_in(22) & mcAddr_in(7 downto 0);
bankAddr_next <= mcAddr_in(9 downto 8);
when MC_WR =>
state_next <= S_WRITE1;
ramCmd_out <= RAM_ACT;
ramAddr_out <= mcAddr_in(21 downto 10);
ramBank_out <= mcAddr_in(9 downto 8);
rowAddr_next <= mcAddr_in(22) & mcAddr_in(7 downto 0);
bankAddr_next <= mcAddr_in(9 downto 8);
wrData_next <= mcData_in;
when others =>
null;
end case;
end if;
end case;
end process;
-- Don't mask anything
ramLDQM_out <= '0';
ramUDQM_out <= '0';
end architecture;
| gpl-3.0 | 818838b515a3e974b730b790eb88fe25 | 0.491579 | 3.521417 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/misc/rstgen.vhd | 1 | 4,495 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: rstgen
-- File: rstgen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Reset generation with glitch filter
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity rstgen is
generic (
acthigh : integer := 0;
syncrst : integer := 0;
scanen : integer := 0;
syncin : integer := 0);
port (
rstin : in std_ulogic;
clk : in std_ulogic;
clklock : in std_ulogic;
rstout : out std_ulogic;
rstoutraw : out std_ulogic;
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0'
);
end;
architecture rtl of rstgen is
signal r : std_logic_vector(4 downto 0);
signal rst, rstoutl, clklockl, arst : std_ulogic;
signal rstsyncin : std_ulogic;
signal inrst_syncreg : std_ulogic;
signal genrst : std_ulogic;
signal genrst_syncreg : std_logic_vector(1 downto 0);
attribute equivalent_register_removal: string;
attribute keep:string;
attribute equivalent_register_removal of r : signal is "no";
attribute equivalent_register_removal of rstsyncin : signal is "no";
attribute equivalent_register_removal of inrst_syncreg : signal is "no";
attribute equivalent_register_removal of genrst : signal is "no";
attribute equivalent_register_removal of genrst_syncreg : signal is "no";
attribute equivalent_register_removal of rst, rstoutl, clklockl, arst : signal is "no";
attribute keep of r : signal is "true";
attribute keep of rstsyncin : signal is "true";
attribute keep of inrst_syncreg : signal is "true";
attribute keep of genrst : signal is "true";
attribute keep of genrst_syncreg : signal is "true";
attribute keep of rst, rstoutl, clklockl, arst : signal is "true";
begin
nosyncinrst : if syncin = 0 generate
rst <= not rstin when acthigh = 1 else rstin;
clklockl <= clklock;
end generate;
syncinrst : if syncin = 1 generate
rstsyncin <= not rstin when acthigh = 1 else rstin;
syncreg0 : syncreg port map (clk, rstsyncin, inrst_syncreg);
genrst <= testrst when (scanen = 1) and (testen = '1') else inrst_syncreg;
gensyncrest : process (clk, genrst) begin
if rising_edge(clk) then
genrst_syncreg(0) <= '1';
genrst_syncreg(1) <= genrst_syncreg(0);
end if;
if ( genrst = '0') then genrst_syncreg <= (others => '0'); end if;
end process;
rst <= genrst_syncreg(1);
syncreg1 : syncreg port map (clk, clklock, clklockl);
end generate;
rstoutraw <= not rstin when acthigh = 1 else rstin;
arst <= testrst when (scanen = 1) and (testen = '1') else rst;
async : if (syncrst = 0 and syncin = 0) generate
reg1 : process (clk, arst) begin
if rising_edge(clk) then
r <= r(3 downto 0) & clklockl;
rstoutl <= r(4) and r(3) and r(2);
end if;
if (arst = '0') then r <= "00000"; rstoutl <= '0'; end if;
end process;
rstout <= (rstoutl and rst) when scanen = 1 else rstoutl;
end generate;
sync : if (syncrst = 1 or syncin = 1) generate
reg1 : process (clk) begin
if rising_edge(clk) then
r <= (r(3 downto 0) & clklockl) and (rst & rst & rst & rst & rst);
rstoutl <= r(4) and r(3) and r(2);
end if;
end process;
rstout <= rstoutl and rst;
end generate;
end;
| gpl-3.0 | e32d599196857f5e5a119c1ac4a74566 | 0.622914 | 3.861684 | false | false | false | false |
pwsoft/fpga_examples | rtl/ttl/ttl_7400.vhd | 1 | 2,375 | -- -----------------------------------------------------------------------
--
-- Syntiac VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2018 by Peter Wendrich ([email protected])
-- http://www.syntiac.com
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
-- Quad 2-input NAND gate
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.ttl_pkg.all;
-- -----------------------------------------------------------------------
entity ttl_7400 is
generic (
latency : integer := 1
);
port (
emuclk : in std_logic;
p1 : in ttl_t;
p2 : in ttl_t;
p3 : out ttl_t;
p4 : in ttl_t;
p5 : in ttl_t;
p6 : out ttl_t;
p8 : out ttl_t;
p9 : in ttl_t;
p10 : in ttl_t;
p11 : out ttl_t;
p12 : in ttl_t;
p13 : in ttl_t
);
end entity;
architecture rtl of ttl_7400 is
signal p3_loc : ttl_t;
signal p6_loc : ttl_t;
signal p8_loc : ttl_t;
signal p11_loc : ttl_t;
begin
p3_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p3_loc, q => p3);
p6_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p6_loc, q => p6);
p8_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p8_loc, q => p8);
p11_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p11_loc, q => p11);
p3_loc <= p1 nand p2;
p6_loc <= p4 nand p5;
p8_loc <= p9 nand p10;
p11_loc <= p12 nand p13;
end architecture;
| lgpl-2.1 | bcb04529922b4bf77ac49856a9da6f6b | 0.562947 | 3.289474 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-altera-c5ekit/memifsim.vhd | 1 | 12,414 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.stdio.all;
entity ddr3ctrl1 is
port (
pll_ref_clk : in std_logic;
global_reset_n : in std_logic;
soft_reset_n : in std_logic;
afi_clk : out std_logic;
afi_half_clk : out std_logic;
afi_reset_n : out std_logic;
afi_reset_export_n : out std_logic;
mem_a : out std_logic_vector(13 downto 0);
mem_ba : out std_logic_vector(2 downto 0);
mem_ck : out std_logic_vector(0 downto 0);
mem_ck_n : out std_logic_vector(0 downto 0);
mem_cke : out std_logic_vector(0 downto 0);
mem_cs_n : out std_logic_vector(0 downto 0);
mem_dm : out std_logic_vector(3 downto 0);
mem_ras_n : out std_logic_vector(0 downto 0);
mem_cas_n : out std_logic_vector(0 downto 0);
mem_we_n : out std_logic_vector(0 downto 0);
mem_reset_n : out std_logic;
mem_dq : inout std_logic_vector(31 downto 0);
mem_dqs : inout std_logic_vector(3 downto 0);
mem_dqs_n : inout std_logic_vector(3 downto 0);
mem_odt : out std_logic_vector(0 downto 0);
avl_ready : out std_logic;
avl_burstbegin : in std_logic;
avl_addr : in std_logic_vector(24 downto 0);
avl_rdata_valid : out std_logic;
avl_rdata : out std_logic_vector(127 downto 0);
avl_wdata : in std_logic_vector(127 downto 0);
avl_be : in std_logic_vector(15 downto 0);
avl_read_req : in std_logic;
avl_write_req : in std_logic;
avl_size : in std_logic_vector(2 downto 0);
local_init_done : out std_logic;
local_cal_success : out std_logic;
local_cal_fail : out std_logic;
oct_rzqin : in std_logic;
pll_mem_clk : out std_logic;
pll_write_clk : out std_logic;
pll_write_clk_pre_phy_clk : out std_logic;
pll_addr_cmd_clk : out std_logic;
pll_locked : out std_logic;
pll_avl_clk : out std_logic;
pll_config_clk : out std_logic;
pll_mem_phy_clk : out std_logic;
afi_phy_clk : out std_logic;
pll_avl_phy_clk : out std_logic
);
end;
architecture sim of ddr3ctrl1 is
signal lafi_clk, lafi_rst_n: std_ulogic;
signal lafi_half_clk: std_ulogic;
begin
afi_clk <= lafi_clk;
afi_half_clk <= lafi_half_clk;
afi_reset_n <= lafi_rst_n;
mem_a <= (others => '0');
mem_ba <= (others => '0');
mem_ck <= (others => '0');
mem_ck_n <= (others => '1');
mem_cke <= (others => '0');
mem_cs_n <= (others => '1');
mem_dm <= (others => '0');
mem_ras_n <= (others => '1');
mem_cas_n <= (others => '1');
mem_we_n <= (others => '1');
mem_reset_n <= '0';
mem_dq <= (others => 'Z');
mem_dqs <= (others => 'Z');
mem_dqs_n <= (others => 'Z');
mem_odt <= (others => '0');
avl_ready <= '1';
local_init_done <= '1';
local_cal_success <= '1';
local_cal_fail <= '0';
pll_mem_clk <= '0';
pll_write_clk <= '0';
pll_write_clk_pre_phy_clk <= '0';
pll_addr_cmd_clk <= '0';
pll_locked <= '1';
pll_avl_clk <= '0';
pll_config_clk <= '0';
pll_mem_phy_clk <= '0';
afi_phy_clk <= '0';
pll_avl_phy_clk <= '0';
clkproc: process
begin
lafi_clk <= '0';
lafi_half_clk <= '0';
loop
wait for 3.3 ns;
lafi_clk <= not lafi_clk;
if lafi_clk='0' then
lafi_half_clk <= not lafi_half_clk;
end if;
end loop;
end process;
rstproc: process
begin
lafi_rst_n <= '0';
wait for 10 ns;
loop
if global_reset_n='0' then
lafi_rst_n <= '0';
wait until global_reset_n/='0';
wait until rising_edge(lafi_clk);
end if;
lafi_rst_n <= '1';
wait until global_reset_n='0';
end loop;
end process;
avlproc: process
subtype BYTE is std_logic_vector(7 downto 0);
type MEM is array(0 to ((2**20)-1)) of BYTE;
variable MEMA: MEM;
procedure load_srec is
file TCF : text open read_mode is "ram.srec";
variable L1: line;
variable CH: character;
variable ai: integer;
variable rectype: std_logic_vector(3 downto 0);
variable recaddr: std_logic_vector(31 downto 0);
variable reclen: std_logic_vector(7 downto 0);
variable recdata: std_logic_vector(0 to 16*8-1);
variable len: integer;
begin
L1:= new string'(""); --'
while not endfile(TCF) loop
readline(TCF,L1);
if (L1'length /= 0) then --'
while (not (L1'length=0)) and (L1(L1'left) = ' ') loop
std.textio.read(L1,CH);
end loop;
if L1'length > 0 then --'
read(L1, ch);
if (ch = 'S') or (ch = 's') then
hread(L1, rectype);
hread(L1, reclen);
len := conv_integer(reclen)-1;
recaddr := (others => '0');
case rectype is
when "0001" =>
hread(L1, recaddr(15 downto 0));
len := len-2;
when "0010" =>
hread(L1, recaddr(23 downto 0));
len := len-3;
when "0011" =>
hread(L1, recaddr);
len := len-4;
when others => next;
end case;
hread(L1, recdata(0 to 8*len-1));
recaddr(31 downto 20) := (others => '0');
ai := conv_integer(recaddr);
-- print("Setting " & tost(len) & "bytes at " & tost(recaddr));
for i in 0 to len-1 loop
MEMA(ai+i) := recdata((i*8) to (i*8+7));
end loop;
end if;
end if;
end if;
end loop;
end load_srec;
constant avldbits: integer := 128;
variable outqueue: std_logic_vector(0 to 4*avldbits-1) := (others => 'X');
variable outqueue_valid: std_logic_vector(0 to 3) := (others => '0');
variable ai,p: integer;
variable wbleft: integer := 0;
begin
load_srec;
loop
wait until rising_edge(lafi_clk);
avl_rdata_valid <= outqueue_valid(0);
avl_rdata <= outqueue(0 to avldbits-1);
outqueue(0 to 3*avldbits-1) := outqueue(avldbits to 4*avldbits-1);
outqueue(3*avldbits to 4*avldbits-1) := (others => 'X');
outqueue_valid := outqueue_valid(1 to 3) & '0';
if avl_burstbegin='1' then wbleft:=0; end if;
if lafi_rst_n='0' then
outqueue_valid := (others => '0');
elsif avl_read_req='1' then
ai := conv_integer(avl_addr(16 downto 0));
p := 0;
while outqueue_valid(p)='1' loop p:=p+1; end loop;
for x in 0 to conv_integer(avl_size)-1 loop
for y in 0 to avldbits/8-1 loop
outqueue((p+x)*avldbits+y*8 to (p+x)*avldbits+y*8+7) := MEMA((ai+x)*avldbits/8+y);
end loop;
outqueue_valid(p+x) := '1';
end loop;
elsif avl_write_req='1' then
if wbleft=0 then
wbleft := conv_integer(avl_size);
ai := conv_integer(avl_addr(16 downto 0));
end if;
for y in 0 to avldbits/8-1 loop
if avl_be(avldbits/8-1-y)='1' then
MEMA(ai*avldbits/8+y) := avl_wdata(avldbits-8*y-1 downto avldbits-8*y-8);
end if;
end loop;
wbleft := wbleft-1;
ai := ai+1;
end if;
end loop;
end process;
end;
library ieee;
use ieee.std_logic_1164.all;
entity lpddr2ctrl1 is
port (
pll_ref_clk : in std_logic;
global_reset_n : in std_logic;
soft_reset_n : in std_logic;
afi_clk : out std_logic;
afi_half_clk : out std_logic;
afi_reset_n : out std_logic;
afi_reset_export_n : out std_logic;
mem_ca : out std_logic_vector(9 downto 0);
mem_ck : out std_logic_vector(0 downto 0);
mem_ck_n : out std_logic_vector(0 downto 0);
mem_cke : out std_logic_vector(0 downto 0);
mem_cs_n : out std_logic_vector(0 downto 0);
mem_dm : out std_logic_vector(1 downto 0);
mem_dq : inout std_logic_vector(15 downto 0);
mem_dqs : inout std_logic_vector(1 downto 0);
mem_dqs_n : inout std_logic_vector(1 downto 0);
avl_ready : out std_logic;
avl_burstbegin : in std_logic;
avl_addr : in std_logic_vector(24 downto 0);
avl_rdata_valid : out std_logic;
avl_rdata : out std_logic_vector(63 downto 0);
avl_wdata : in std_logic_vector(63 downto 0);
avl_be : in std_logic_vector(7 downto 0);
avl_read_req : in std_logic;
avl_write_req : in std_logic;
avl_size : in std_logic_vector(2 downto 0);
local_init_done : out std_logic;
local_cal_success : out std_logic;
local_cal_fail : out std_logic;
oct_rzqin : in std_logic;
pll_mem_clk : out std_logic;
pll_write_clk : out std_logic;
pll_write_clk_pre_phy_clk : out std_logic;
pll_addr_cmd_clk : out std_logic;
pll_locked : out std_logic;
pll_avl_clk : out std_logic;
pll_config_clk : out std_logic;
pll_mem_phy_clk : out std_logic;
afi_phy_clk : out std_logic;
pll_avl_phy_clk : out std_logic
);
end;
architecture sim of lpddr2ctrl1 is
signal lafi_clk: std_ulogic;
begin
afi_clk <= lafi_clk;
afi_reset_n <= '0';
afi_reset_export_n <= '0';
mem_ca <= (others => '0');
mem_ck <= (others => '0');
mem_ck_n <= (others => '1');
mem_cke <= (others => '0');
mem_cs_n <= (others => '1');
mem_dm <= (others => '0');
mem_dq <= (others => 'Z');
mem_dqs <= (others => 'Z');
mem_dqs_n <= (others => 'Z');
avl_ready <= '1';
avl_rdata_valid <= '1';
avl_rdata <= (others => '0');
local_init_done <= '1';
local_cal_success <= '1';
local_cal_fail <= '0';
pll_mem_clk <= '0';
pll_write_clk <= '0';
pll_write_clk_pre_phy_clk <= '0';
pll_addr_cmd_clk <= '0';
pll_locked <= '1';
pll_avl_clk <= '0';
pll_config_clk <= '0';
pll_mem_phy_clk <= '0';
afi_phy_clk <= '0';
pll_avl_phy_clk <= '0';
clkproc: process
variable vclk,vhclk: std_logic := '0';
begin
lafi_clk <= vclk;
afi_half_clk <= vhclk;
wait for 4 ns;
vclk := not vclk;
if vclk='0' then vhclk:=not vhclk; end if;
end process;
rstproc: process
begin
afi_reset_n <= '0';
for x in 1 to 10 loop
wait until rising_edge(lafi_clk);
end loop;
afi_reset_n <= '1';
wait;
end process;
end;
| gpl-3.0 | 5733a5053e73f0ca1c9d67d6a4346ffa | 0.509183 | 3.331723 | false | false | false | false |
pwsoft/fpga_examples | rtl/chameleon/chameleon2_io_a.vhd | 1 | 15,779 | -- -----------------------------------------------------------------------
--
-- Turbo Chameleon
--
-- Multi purpose FPGA expansion for the Commodore 64 computer
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2019 by Peter Wendrich ([email protected])
-- http://www.syntiac.com
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- -----------------------------------------------------------------------
architecture rtl of chameleon2_io is
-- Clocks
signal no_clock_loc : std_logic;
signal phi : std_logic;
signal end_of_phi_0 : std_logic;
signal end_of_phi_1 : std_logic;
-- I/O entity internal C64 bus
signal c64_cs_loc : std_logic;
signal c64_cs_roms_loc : std_logic;
signal c64_cs_vicii_loc : std_logic;
signal c64_cs_clockport_loc : std_logic;
signal c64_we_loc : std_logic;
signal c64_a_loc : unsigned(15 downto 0);
signal c64_d_loc : unsigned(7 downto 0);
signal c64_q_loc : unsigned(7 downto 0);
-- C64 joystick/keyboard
signal c64_joystick1 : unsigned(6 downto 0);
signal c64_joystick2 : unsigned(6 downto 0);
signal c64_joystick3 : unsigned(6 downto 0);
signal c64_joystick4 : unsigned(6 downto 0);
signal c64_keys : unsigned(63 downto 0);
-- CDTV remote
signal ir_up : std_logic := '0';
signal ir_down : std_logic := '0';
signal ir_left : std_logic := '0';
signal ir_right : std_logic := '0';
signal ir_f1 : std_logic := '0';
signal ir_f2 : std_logic := '0';
signal ir_f3 : std_logic := '0';
signal ir_f4 : std_logic := '0';
signal ir_f5 : std_logic := '0';
signal ir_f6 : std_logic := '0';
signal ir_f7 : std_logic := '0';
signal ir_f8 : std_logic := '0';
signal ir_space : std_logic := '0';
signal ir_enter : std_logic := '0';
signal ir_left_button : std_logic := '0';
signal ir_middle_button : std_logic := '0';
signal ir_right_button : std_logic := '0';
signal ir_arrowleft : std_logic := '0';
signal ir_y : std_logic := '0';
signal ir_n : std_logic := '0';
signal ir_runstop : std_logic := '0';
signal ir_keys : unsigned(63 downto 0);
signal ir_joystick1 : unsigned(6 downto 0) := (others => '1');
signal ir_joystick2 : unsigned(6 downto 0) := (others => '1');
-- Docking-station
signal docking_station_loc : std_logic;
signal docking_version_loc : std_logic;
signal docking_joystick1 : unsigned(6 downto 0);
signal docking_joystick2 : unsigned(6 downto 0);
signal docking_joystick3 : unsigned(6 downto 0);
signal docking_joystick4 : unsigned(6 downto 0);
signal docking_keys : unsigned(63 downto 0);
signal docking_amiga_reset_n : std_logic;
signal docking_amiga_scancode : unsigned(7 downto 0);
begin
no_clock <= no_clock_loc;
docking_station <= docking_station_loc;
docking_version <= docking_version_loc;
phi_out <= phi;
phi_end_0 <= end_of_phi_0;
phi_end_1 <= end_of_phi_1;
--
c64_q <= c64_q_loc;
--
joystick1 <= docking_joystick1 and ir_joystick1 and c64_joystick1;
joystick2 <= docking_joystick2 and ir_joystick2 and c64_joystick2;
joystick3 <= docking_joystick3 and c64_joystick3;
joystick4 <= docking_joystick4 and c64_joystick4;
keys <= docking_keys and c64_keys and ir_keys;
midi_rxd <= ba_in or (not docking_station_loc) or (not docking_version_loc);
-- -----------------------------------------------------------------------
-- PHI2 clock sync
-- -----------------------------------------------------------------------
phiInstance : entity work.chameleon_phi_clock
generic map (
phase_shift => 8
)
port map (
clk => clk,
phi2_n => phi2_n,
mode => phi_mode,
no_clock => no_clock_loc,
docking_station => docking_station_loc,
phiLocal => phi,
phiCnt => phi_cnt,
phiPreHalf => end_of_phi_0,
phiPreEnd => end_of_phi_1,
phiPost1 => phi_post_1,
phiPost2 => phi_post_2,
phiPost3 => phi_post_3,
phiPost4 => phi_post_4
);
-- -----------------------------------------------------------------------
-- Docking-station
-- To enable set enable_docking_station to true.
-- -----------------------------------------------------------------------
genDockingStation : if enable_docking_station generate
myDockingStation : entity work.chameleon_docking_station
port map (
clk => clk,
docking_station => docking_station_loc,
docking_version => docking_version_loc,
dotclock_n => dotclock_n,
io_ef_n => ioef,
rom_lh_n => romlh,
irq_q => docking_irq,
joystick1 => docking_joystick1,
joystick2 => docking_joystick2,
joystick3 => docking_joystick3,
joystick4 => docking_joystick4,
keys => docking_keys,
restore_key_n => restore_key_n,
amiga_power_led => amiga_power_led,
amiga_drive_led => amiga_drive_led,
amiga_reset_n => amiga_reset_n,
amiga_trigger => amiga_trigger,
amiga_scancode => amiga_scancode
);
end generate;
noDockingStation : if not enable_docking_station generate
docking_version <= '0';
docking_joystick1 <= (others => '1');
docking_joystick2 <= (others => '1');
docking_joystick3 <= (others => '1');
docking_joystick4 <= (others => '1');
docking_keys <= (others => '1');
end generate;
-- -----------------------------------------------------------------------
-- CDTV remote support
-- To enable set enable_cdtv_remote to true.
-- -----------------------------------------------------------------------
genCdtvRemote : if enable_cdtv_remote generate
myCdtvRemote : entity work.chameleon_cdtv_remote
port map (
clk => clk,
ena_1mhz => ena_1mhz,
ir => ir_data,
key_1 => ir_f1,
key_2 => ir_f2,
key_3 => ir_f3,
key_4 => ir_f4,
key_5 => ir_f5,
key_6 => ir_f6,
key_7 => ir_f7,
key_8 => ir_f8,
key_9 => ir_runstop,
key_0 => ir_space,
key_escape => ir_arrowleft,
key_enter => ir_enter,
key_genlock => ir_left_button,
key_cdtv => ir_middle_button,
key_power => ir_right_button,
key_rew => ir_left,
key_play => ir_up,
key_ff => ir_right,
key_stop => ir_down,
key_vol_up => ir_y,
key_vol_dn => ir_n,
joystick_a => ir_joystick1(5 downto 0),
joystick_b => ir_joystick2(5 downto 0)
);
-- IR remote doesn't have thrid fire button
ir_joystick1(6) <= '1';
ir_joystick2(6) <= '1';
ir_keys <= (not ir_runstop) & "11" & (not ir_n) & "111" & (not (ir_up or ir_down)) &
"1111111" & (not (ir_f5 or ir_f6)) &
"1111111" & (not (ir_f3 or ir_f4)) &
(not ir_space) & (not (ir_left or ir_up or ir_f2 or ir_f4 or ir_f6 or ir_f8)) & "11111" & (not (ir_f1 or ir_f2)) &
"1111111" & (not (ir_f7 or ir_f8)) &
"1111111" & (not (ir_left or ir_right)) &
(not ir_arrowleft) & "111" & (not ir_y) & "11" & (not ir_enter) &
"11111111";
end generate;
noCdtvRemote : if not enable_cdtv_remote generate
ir_keys <= (others => '1');
ir_joystick1 <= (others => '1');
ir_joystick2 <= (others => '1');
end generate;
-- -----------------------------------------------------------------------
-- C64 keyboard and joystick support
-- To enable set enable_c64_joykeyb to true.
-- -----------------------------------------------------------------------
c64_joykeyb_gen : if enable_c64_joykeyb generate
c64_joykeyb_blk : block
signal c64_kb_cs_reg : std_logic := '0';
signal c64_kb_req : std_logic := '0';
signal c64_kb_ack : std_logic := '0';
signal c64_kb_we : std_logic := '0';
signal c64_kb_a : unsigned(15 downto 0);
signal c64_kb_d : unsigned(7 downto 0);
signal c64_kb_q : unsigned(7 downto 0);
begin
c64_joykeyb_inst : entity work.chameleon_c64_joykeyb
generic map (
enable_4player => enable_c64_4player
)
port map (
clk => clk,
ena_1mhz => ena_1mhz,
no_clock => no_clock_loc,
reset => reset,
ba => ba_in,
req => c64_kb_req,
ack => c64_kb_ack,
we => c64_kb_we,
a => c64_kb_a,
d => c64_kb_d,
q => c64_kb_q,
joystick1 => c64_joystick1,
joystick2 => c64_joystick2,
joystick3 => c64_joystick3,
joystick4 => c64_joystick4,
keys => c64_keys
);
process(clk)
begin
if rising_edge(clk) then
if end_of_phi_1 = '1' then
c64_kb_cs_reg <= '0';
if c64_kb_req /= c64_kb_ack then
if c64_kb_cs_reg = '1' then
-- C64 bus transaction finished
c64_kb_ack <= c64_kb_req;
else
-- Start new C64 bus transaction
c64_kb_cs_reg <= '1';
end if;
end if;
end if;
end if;
end process;
c64_cs_loc <= c64_kb_cs_reg;
c64_cs_roms_loc <= '0';
c64_cs_vicii_loc <= '0';
c64_cs_clockport_loc <= '0';
c64_we_loc <= c64_kb_we;
c64_a_loc <= c64_kb_a;
c64_d_loc <= c64_kb_q;
c64_kb_d <= c64_q_loc;
end block;
end generate;
no_c64_joykeyb_gen : if not enable_c64_joykeyb generate
c64_joystick1 <= (others => '1');
c64_joystick2 <= (others => '1');
c64_joystick3 <= (others => '1');
c64_joystick4 <= (others => '1');
c64_keys <= (others => '1');
c64_cs_loc <= c64_cs;
c64_cs_roms_loc <= c64_cs_roms;
c64_cs_vicii_loc <= c64_cs_vicii;
c64_cs_clockport_loc <= c64_cs_clockport;
c64_we_loc <= c64_we;
c64_a_loc <= c64_a;
c64_d_loc <= c64_d;
end generate;
-- -----------------------------------------------------------------------
-- Cartridge port and C64 bus control
-- -----------------------------------------------------------------------
c64_bus_blk : block
constant dir_fr_c64 : std_logic := '0';
constant dir_to_c64 : std_logic := '1';
type state_t is (
BUS_RESET,
BUS_WAIT_PHI0,
BUS0_00, BUS0_01, BUS0_02, BUS0_03,
BUS0_04, BUS0_05, BUS0_06, BUS0_07, BUS0_08,
BUS0_09, BUS0_0A, --BUS0_0B, BUS0_0C, BUS0_0D, BUS0_0E, BUS0_0F,
BUS_WAIT_PHI1,
BUS1_00, BUS1_01, BUS1_02, BUS1_03, BUS1_04, BUS1_05);
signal state_reg : state_t := BUS_RESET;
--signal exrom_out_reg : std_logic := '0';
signal clock_ior_reg : std_logic := '1';
signal clock_iow_reg : std_logic := '1';
signal game_out_reg : std_logic := '1';
signal rw_out_reg : std_logic := '0';
signal sa_dir_reg : std_logic := '1';
signal sa_oe_reg : std_logic := '1';
signal sa15_out_reg : std_logic := '0';
signal low_a_oe_reg : std_logic := '0';
signal low_a_reg : unsigned(15 downto 0) := (others => '0');
signal sd_dir_reg : std_logic := '1';
signal sd_oe_reg : std_logic := '1';
signal low_d_inp_reg : unsigned(7 downto 0) := (others => '0');
signal low_d_oe_reg : std_logic := '0';
signal low_d_out_reg : unsigned(7 downto 0) := (others => '0');
signal c64_q_reg : unsigned(c64_q'range) := (others => '1');
begin
process(clk)
begin
if rising_edge(clk) then
low_d_inp_reg <= low_d;
case state_reg is
when BUS_RESET =>
clock_ior_reg <= '1';
clock_iow_reg <= '1';
game_out_reg <= '1';
rw_out_reg <= '0';
sa_oe_reg <= '1';
sa15_out_reg <= '0';
sd_oe_reg <= '1';
low_a_oe_reg <= '0';
low_d_oe_reg <= '0';
if reset = '0' then
state_reg <= BUS_WAIT_PHI0;
end if;
when BUS_WAIT_PHI0 =>
c64_q_reg <= low_d_inp_reg;
if phi = '0' then
state_reg <= BUS0_00;
else
if c64_cs_vicii_loc = '1' then
low_d_out_reg <= c64_d_loc;
end if;
end if;
when BUS0_00 =>
state_reg <= BUS0_01;
when BUS0_01 =>
game_out_reg <= '1';
low_a_reg(15) <= '0';
clock_ior_reg <= '1';
clock_iow_reg <= '1';
state_reg <= BUS0_02;
when BUS0_02 =>
state_reg <= BUS0_03;
when BUS0_03 =>
low_a_oe_reg <= '0';
rw_out_reg <= '0';
sa_oe_reg <= '1';
state_reg <= BUS0_04;
when BUS0_04 =>
sa15_out_reg <= '1';
state_reg <= BUS0_05;
when BUS0_05 =>
state_reg <= BUS0_06;
when BUS0_06 =>
state_reg <= BUS0_07;
when BUS0_07 =>
state_reg <= BUS0_08;
when BUS0_08 =>
state_reg <= BUS0_09;
when BUS0_09 =>
sd_dir_reg <= dir_to_c64;
state_reg <= BUS0_0A;
when BUS0_0A =>
low_d_oe_reg <= '1';
sd_oe_reg <= '0';
state_reg <= BUS_WAIT_PHI1;
-- state_reg <=
-- when BUS0_04 => state_reg <= BUS0_05;
-- when BUS0_05 => state_reg <= BUS0_06;
-- when BUS0_06 => state_reg <= BUS0_07;
-- when BUS0_07 => state_reg <= BUS0_08;
-- when BUS0_08 => state_reg <= BUS0_09;
-- when BUS0_09 => state_reg <= BUS0_0A;
-- when BUS0_0A => state_reg <= BUS0_0B;
-- when BUS0_0B => state_reg <= BUS0_0C;
-- when BUS0_0C => state_reg <= BUS0_0D;
-- when BUS0_0D => state_reg <= BUS0_0E;
-- when BUS0_0E => state_reg <= BUS0_0F;
-- when BUS0_0F =>
-- state_reg <= BUS_WAIT_PHI1;
when BUS_WAIT_PHI1 =>
low_d_out_reg <= c64_vicii_data;
if phi = '1' then
state_reg <= BUS1_00;
end if;
when BUS1_00 =>
state_reg <= BUS1_01;
when BUS1_01 =>
state_reg <= BUS1_02;
when BUS1_02 =>
sa_dir_reg <= dir_to_c64;
rw_out_reg <= c64_we_loc and c64_cs_loc;
if (c64_cs_loc = '1') and (c64_cs_vicii_loc = '0') then
sa15_out_reg <= '0';
low_a_oe_reg <= '1';
end if;
if ((c64_cs_loc and c64_we_loc) = '0') and (c64_cs_vicii_loc = '0') then
low_d_oe_reg <= '0';
sd_oe_reg <= '1';
end if;
-- For reading ROMs the GAME line need to be high (game_out_reg low as driver inverts).
game_out_reg <= '1';
if c64_cs_roms_loc = '1' then
game_out_reg <= '0';
end if;
low_a_reg <= "0" & c64_a_loc(14 downto 0);
low_d_out_reg <= c64_d_loc;
state_reg <= BUS1_03;
when BUS1_03 =>
if (c64_cs_loc = '1') and (c64_cs_vicii_loc = '0') then
sa_oe_reg <= '0';
end if;
if c64_cs_vicii_loc = '1' then
sa15_out_reg <= '1';
end if;
low_a_reg <= "0" & c64_a_loc(14 downto 0);
low_d_out_reg <= c64_d_loc;
state_reg <= BUS1_04;
when BUS1_04 =>
sd_dir_reg <= dir_fr_c64;
if ((c64_cs_loc and c64_we_loc) or c64_cs_vicii_loc) = '1' then
sd_dir_reg <= dir_to_c64;
low_d_oe_reg <= '1';
end if;
low_a_reg <= "0" & c64_a_loc(14 downto 0);
low_d_out_reg <= c64_d_loc;
state_reg <= BUS1_05;
when BUS1_05 =>
sd_oe_reg <= '0';
if c64_cs_clockport_loc = '1' then
clock_ior_reg <= c64_we_loc;
clock_iow_reg <= not c64_we_loc;
end if;
low_a_reg <= c64_a_loc(15 downto 0);
low_d_out_reg <= c64_d_loc;
state_reg <= BUS_WAIT_PHI0;
end case;
if (no_clock_loc = '1') and (docking_station_loc = '1') and (docking_version_loc = '1') then
-- GAME line is MIDI out on docking-station V2
game_out_reg <= not midi_txd;
end if;
end if;
end process;
clock_ior <= clock_ior_reg;
clock_iow <= clock_iow_reg;
dma_out <= '1';
exrom_out <= '0';
game_out <= game_out_reg;
rw_out <= rw_out_reg;
sa_dir <= sa_dir_reg;
sa_oe <= sa_oe_reg;
sa15_out <= sa15_out_reg;
low_a <= low_a_reg when low_a_oe_reg = '1' else (others => 'Z');
sd_dir <= sd_dir_reg;
sd_oe <= sd_oe_reg;
low_d <= low_d_out_reg when low_d_oe_reg = '1' else (others => 'Z');
c64_q_loc <= c64_q_reg;
end block;
end architecture;
| lgpl-2.1 | b8354fcc7039985855878fa1e69a104e | 0.550605 | 2.621096 | false | false | false | false |
pwsoft/fpga_examples | rtl/chameleon/chameleon_1khz.vhd | 1 | 2,301 | -- -----------------------------------------------------------------------
--
-- Turbo Chameleon
--
-- Multi purpose FPGA expansion for the Commodore 64 computer
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2011 by Peter Wendrich ([email protected])
-- http://www.syntiac.com/chameleon.html
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
--
-- 1 Khz clock source
--
-- -----------------------------------------------------------------------
-- clk - system clock input
-- ena_1mhz - 1 Mhz input, signal must be one cycle high each micro-second.
-- ena_1khz - 1 Khz output. Signal is one cycle '1' each 1 millisecond.
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
-- -----------------------------------------------------------------------
entity chameleon_1khz is
port (
clk : in std_logic;
ena_1mhz : in std_logic;
ena_1khz : out std_logic
);
end entity;
-- -----------------------------------------------------------------------
architecture rtl of chameleon_1khz is
constant reset_count : integer := 1025 - 1000;
signal cnt : unsigned(10 downto 0) := (others => '0');
signal ena_out : std_logic := '0';
begin
ena_1khz <= ena_out;
process(clk)
begin
if rising_edge(clk) then
ena_out <= '0';
if ena_1mhz = '1' then
ena_out <= cnt(cnt'high);
if cnt(cnt'high) = '1' then
cnt <= to_unsigned(reset_count, cnt'length);
else
cnt <= cnt + 1;
end if;
end if;
end if;
end process;
end architecture;
| lgpl-2.1 | c31bc7b855418b53373e300ebfc6e525 | 0.531073 | 4.043937 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/gr1553b/gr1553b_pads.vhd | 1 | 5,026 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: gr1553b_pads
-- File: gr1553b_pads.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Pad instantiations for GR1553B
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.gr1553b_pkg.all;
library techmap;
use techmap.gencomp.all;
entity gr1553b_pads is
generic (
padtech: integer;
outen_pol: integer range 0 to 1;
level: integer := ttl;
slew: integer := 0;
voltage: integer := x33v;
strength: integer := 12;
filter: integer := 0
);
port (
txout: in gr1553b_txout_type;
rxin: out gr1553b_rxin_type;
busainen : out std_logic;
busainp : in std_logic;
busainn : in std_logic;
busaoutenin : out std_logic;
busaoutp : out std_logic;
busaoutn : out std_logic;
busbinen : out std_logic;
busbinp : in std_logic;
busbinn : in std_logic;
busboutenin : out std_logic;
busboutp : out std_logic;
busboutn : out std_logic
);
end;
architecture rtl of gr1553b_pads is
begin
outin_gen: if outen_pol /= 0 generate
busa_outin_pad : outpad
generic map (tech => padtech, level => level, slew => slew,
voltage => voltage, strength => strength)
port map (busaoutenin, txout.busA_txin);
busb_outin_pad : outpad
generic map (tech => padtech, level => level, slew => slew,
voltage => voltage, strength => strength)
port map (busboutenin, txout.busB_txin);
end generate;
outen_gen: if outen_pol = 0 generate
busa_outen_pad : outpad
generic map (tech => padtech, level => level, slew => slew,
voltage => voltage, strength => strength)
port map (busaoutenin, txout.busA_txen);
busb_outen_pad : outpad
generic map (tech => padtech, level => level, slew => slew,
voltage => voltage, strength => strength)
port map (busboutenin, txout.busB_txen);
end generate;
busa_inen_pad : outpad
generic map (tech => padtech, level => level, slew => slew,
voltage => voltage, strength => strength)
port map (busainen, txout.busA_rxen);
busa_inp_pad : inpad
generic map (tech => padtech, level => level, filter => filter,
voltage => voltage, strength => strength)
port map (busainp, rxin.busA_rxP);
busa_inn_pad : inpad
generic map (tech => padtech, level => level, filter => filter,
voltage => voltage, strength => strength)
port map (busainn, rxin.busA_rxN);
busa_outp_pad : outpad
generic map (tech => padtech, level => level, slew => slew,
voltage => voltage, strength => strength)
port map (busaoutp, txout.busA_txP);
busa_outn_pad : outpad
generic map (tech => padtech, level => level, slew => slew,
voltage => voltage, strength => strength)
port map (busaoutn, txout.busA_txN);
busb_inen_pad : outpad
generic map (tech => padtech, level => level, slew => slew,
voltage => voltage, strength => strength)
port map (busbinen, txout.busB_rxen);
busb_inp_pad : inpad
generic map (tech => padtech, level => level, filter => filter,
voltage => voltage, strength => strength)
port map (busbinp, rxin.busB_rxP);
busb_inn_pad : inpad
generic map (tech => padtech, level => level, filter => filter,
voltage => voltage, strength => strength)
port map (busbinn, rxin.busB_rxN);
busb_outp_pad : outpad
generic map (tech => padtech, level => level, slew => slew,
voltage => voltage, strength => strength)
port map (busboutp, txout.busB_txP);
busb_outn_pad : outpad
generic map (tech => padtech, level => level, slew => slew,
voltage => voltage, strength => strength)
port map (busboutn, txout.busB_txN);
end;
| gpl-3.0 | 8c11595861c06d4f380e0940644fe65b | 0.600676 | 3.979414 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/grdmac/grdmac_pkg.vhd | 1 | 10,389 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: grdmac_pkg
-- File: grdmac_pkg.vhd
-- Author: Andrea Gianarro - Aeroflex Gaisler AB
-- Description: Package for GRDMAC and its components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- pragma translate_off
use std.textio.all;
-- pragma translate_on
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.stdlib.all;
use grlib.amba.all;
package grdmac_pkg is
type grdmac_ahb_dma_in_type is record
address : std_logic_vector(31 downto 0);
wdata : std_logic_vector(AHBDW-1 downto 0);
start : std_ulogic;
burst : std_ulogic;
first_beat : std_ulogic;
write : std_ulogic;
busy : std_ulogic;
idle : std_ulogic;
irq : std_ulogic;
size : std_logic_vector(2 downto 0);
end record;
type grdmac_ahb_dma_out_type is record
start : std_ulogic;
active : std_ulogic;
ready : std_ulogic;
retry : std_ulogic;
mexc : std_ulogic;
haddr : std_logic_vector(9 downto 0);
rdata : std_logic_vector(AHBDW-1 downto 0);
end record;
constant grdmac_ahb_dma_in_none : grdmac_ahb_dma_in_type := ( zx, zahbdw, '0', '0', '0', '0', '0', '0', '0', "000");
constant grdmac_ahb_dma_none : grdmac_ahb_dma_out_type := ('0', '0', '0', '0', '0', (others => '0'), zahbdw);
component grdmac is
generic (
hmindex : integer := 0; -- AHB master index
hirq : integer := 0;
pindex : integer := 0; -- APB configuration slave index
paddr : integer := 1;
pmask : integer := 16#FF0#;
en_ahbm1 : integer range 0 to 1 := 0;
hmindex1 : integer := 1; -- AHB master 1 index
ndmach : integer range 1 to 16 := 1; -- number of DMA channels --TODO: implement ndmach = 0
bufsize : integer range 4*AHBDW/8 to 64*1024:= 256; -- number of bytes in buffer (must be a multiple of WORD_SIZE and 4)
burstbound : integer range 4 to 1024 := 512;
en_timer : integer := 0;
memtech : integer := 0;
testen : integer := 0;
ft : integer range 0 to 2 := 0;
wbmask : integer := 0;
busw : integer := 64
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbmi1 : in ahb_mst_in_type;
ahbmo1 : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
irq_trig : in std_logic_vector(63 downto 0)
);
end component;
component grdmac_1p is
generic (
hmindex : integer := 0; -- AHB master index
hirq : integer := 0;
pindex : integer := 0; -- APB configuration slave index
paddr : integer := 1;
pmask : integer := 16#FFF#;
ndmach : integer range 1 to 16 := 1; -- number of DMA channels --TODO: implement ndmach = 0
bufsize : integer range 4*AHBDW/8 to 64*1024:= 256; -- number of bytes in buffer (must be a multiple of 4*WORD_SIZE)
burstbound : integer range 4 to 1024 := 512;
memtech : integer := 0;
testen : integer := 0;
ft : integer range 0 to 2 := 0;
wbmask : integer := 0;
busw : integer := 64
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
irq_trig : in std_logic_vector(63 downto 0)
);
end component;
component grdmac_ahbmst
generic (
hindex : integer := 0;
hirq : integer := 0;
venid : integer := 1;
devid : integer := 0;
version : integer := 0;
chprot : integer := 3;
incaddr : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
dmai : in grdmac_ahb_dma_in_type;
dmao : out grdmac_ahb_dma_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type
);
end component;
component grdmac_alignram is
generic (
memtech : integer := 0;
abits : integer := 6; -- number of BYTES in buffer
dbits : integer := 8;
testen : integer := 0;
ft : integer range 0 to 2 := 0
);
port (
clk : in std_ulogic;
rst : in std_logic;
enable : in std_logic;
write : in std_logic;
address : in std_logic_vector((abits-1) downto 0);
size : in std_logic_vector(2 downto 0); -- AHB HSIZE format
dataout : out std_logic_vector((dbits-1) downto 0);
datain : in std_logic_vector((dbits-1) downto 0);
data_offset : in std_logic_vector((log2(dbits/8))-1 downto 0)); -- offset in bytes
end component;
function sll_byte_lanes(arg: std_logic_vector; count: natural)
return std_logic_vector;
function srl_byte_lanes(arg: std_logic_vector; count: natural)
return std_logic_vector;
function rol_byte_lanes(arg: std_logic_vector; count: natural)
return std_logic_vector;
function ror_byte_lanes(arg: std_logic_vector; count: natural)
return std_logic_vector;
function mask_byte_lanes(arg: std_logic_vector; mask: std_logic_vector)
return std_logic_vector;
end package;
package body grdmac_pkg is
function sll_byte_lanes(arg: std_logic_vector; count: natural)
return std_logic_vector is
type striped_type is array (0 to 7) of std_logic_vector((arg'length/8)-1 downto 0);
variable arr : striped_type;
variable o : std_logic_vector(arg'high downto arg'low);
begin
-- stripe
for j in 0 to 7 loop
for i in 0 to (arg'length/8)-1 loop
arr(j)(i) := arg(arg'low+i*8+j);
end loop;
end loop;
-- shift
for j in 0 to 7 loop
arr(j) := std_logic_vector(shift_left(unsigned(arr(j)), count));
end loop;
-- unstripe
for j in 0 to 7 loop
for i in 0 to (arg'length/8)-1 loop
o(arg'low+i*8+j) := arr(j)(i);
end loop;
end loop;
return o;
end;
function srl_byte_lanes(arg: std_logic_vector; count: natural)
return std_logic_vector is
type striped_type is array (0 to 7) of std_logic_vector((arg'length/8)-1 downto 0);
variable arr : striped_type;
variable o : std_logic_vector(arg'high downto arg'low);
begin
-- stripe
for j in 0 to 7 loop
for i in 0 to (arg'length/8)-1 loop
arr(j)(i) := arg(arg'low+i*8+j);
end loop;
end loop;
-- shift
for j in 0 to 7 loop
arr(j) := std_logic_vector(shift_right(unsigned(arr(j)), count));
end loop;
-- unstripe
for j in 0 to 7 loop
for i in 0 to (arg'length/8)-1 loop
o(arg'low+i*8+j) := arr(j)(i);
end loop;
end loop;
return o;
end;
function rol_byte_lanes(arg: std_logic_vector; count: natural)
return std_logic_vector is
type striped_type is array (0 to 7) of std_logic_vector((arg'length/8)-1 downto 0);
variable arr : striped_type;
variable o : std_logic_vector(arg'high downto arg'low);
begin
-- stripe
for j in 0 to 7 loop
for i in 0 to (arg'length/8)-1 loop
arr(j)(i) := arg(arg'low+i*8+j);
end loop;
end loop;
-- rotate
for j in 0 to 7 loop
arr(j) := std_logic_vector(rotate_left(unsigned(arr(j)), count));
end loop;
-- unstripe
for j in 0 to 7 loop
for i in 0 to (arg'length/8)-1 loop
o(arg'low+i*8+j) := arr(j)(i);
end loop;
end loop;
return o;
end;
function ror_byte_lanes(arg: std_logic_vector; count: natural)
return std_logic_vector is
type striped_type is array (0 to 7) of std_logic_vector((arg'length/8)-1 downto 0);
variable arr : striped_type;
variable o : std_logic_vector(arg'high downto arg'low);
begin
-- stripe
for j in 0 to 7 loop
for i in 0 to (arg'length/8)-1 loop
arr(j)(i) := arg(arg'low+i*8+j);
end loop;
end loop;
-- rotate
for j in 0 to 7 loop
arr(j) := std_logic_vector(rotate_right(unsigned(arr(j)), count));
end loop;
-- unstripe
for j in 0 to 7 loop
for i in 0 to (arg'length/8)-1 loop
o(arg'low+i*8+j) := arr(j)(i);
end loop;
end loop;
return o;
end;
function mask_byte_lanes(arg: std_logic_vector; mask: std_logic_vector)
return std_logic_vector is
--variable m : std_logic_vector((arg'length/8)-1 downto 0);
variable lanemask : std_logic_vector(7 downto 0);
variable o : std_logic_vector(arg'high downto arg'low);
begin
for i in 0 to (arg'length/8)-1 loop
lanemask := (others => mask(mask'low+i));
--print(tost_bits(lanemask));
o(arg'low+i*8+7 downto arg'low+i*8) := (arg(arg'low+i*8+7 downto arg'low+i*8) and lanemask);
end loop;
return o;
end;
end package body;
| gpl-3.0 | 654ec28f308c801ff78080971c3b7f33 | 0.563096 | 3.448058 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/grdmac/grdmac.vhd | 1 | 47,573 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grdmac
-- File: grdmac.vhd
-- Author: Andrea Gianarro - Cobham Gaisler AB
-- Description: AMBA DMA controller with dual master interface
-- Supports scatter gather on unaligned data through internal
-- re-alignment buffer and conditional descriptors
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.grdmac_pkg.all;
use grlib.devices.all;
-- pragma translate_off
use std.textio.all;
-- pragma translate_on
entity grdmac is
generic (
hmindex : integer := 0; -- AHB master index
hirq : integer := 0;
pindex : integer := 0; -- APB configuration slave index
paddr : integer := 1;
pmask : integer := 16#FF0#;
en_ahbm1 : integer range 0 to 1 := 0;
hmindex1 : integer := 1; -- AHB master 1 index
ndmach : integer range 1 to 16 := 1; -- number of DMA channels --TODO: implement ndmach = 0
bufsize : integer range 4*AHBDW/8 to 64*1024:= 256; -- number of bytes in buffer (must be a multiple of 4*WORD_SIZE)
burstbound : integer range 4 to 1024 := 512;
en_timer : integer := 0;
memtech : integer := 0;
testen : integer := 0;
ft : integer range 0 to 2 := 0;
wbmask : integer := 0;
busw : integer := 64
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbmi1 : in ahb_mst_in_type;
ahbmo1 : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
irq_trig : in std_logic_vector(63 downto 0)
);
end;
architecture rtl of grdmac is
type conf_type is record
en : std_logic;
rst : std_logic;
irq_en : std_logic;
irq_err_en : std_logic;
cvp : std_logic_vector(31 downto 0);
direct_mode : std_logic;
ch_err : integer range 0 to ndmach-1;
cvp_err : std_logic;
desc_err : std_logic;
ahb_err : std_logic;
cond_err : std_logic;
to_err : std_logic;
err : std_logic;
trans_size_limit : std_logic_vector(1 downto 0);
timer_en : std_logic;
timer_rst : std_logic_vector(31 downto 0);
end record;
type desc_type is record
en : std_logic;
irq_en : std_logic;
nextdescp : std_logic_vector(31 downto 0);
addr : std_logic_vector(31 downto 0);
size : std_logic_vector(15 downto 0);
ahbm_num : std_logic;
status : std_logic;
complete : std_logic;
ahb_err : std_logic;
write_back : std_logic;
fixed_addr : std_logic;
cond_en : std_logic;
cond_irq_trig : std_logic;
cond_addr_irqn : std_logic_vector(31 downto 0);
cond_mask : std_logic_vector(31 downto 0);
cond_op : std_logic;
cond_tot_size : std_logic_vector(15 downto 0);
cond_rem_size : std_logic_vector(15 downto 0);
cond_ahbm_num : std_logic;
cond_outcome : std_logic;
end record;
type channel_type is record
en : std_logic;
irq_en : std_logic;
status : std_logic;
complete : std_logic;
irq_flag : std_logic;
end record;
type channel_vector is array (0 to ndmach-1) of channel_type;
constant abits : integer := log2ext(bufsize);
constant burstbit : integer := log2ext(burstbound);
constant apbmax : integer := 19;
constant wtbl : std_logic_vector(15 downto 0) := conv_std_logic_vector(wbmask, 16);
constant VERSION : amba_version_type := 2;
constant pconfig: apb_config_type :=
( 0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_GRDMAC, 0, VERSION, hirq),
1 => apb_iobar(paddr, pmask));
type dma_state_type is (idle,
control,
fetch_cvp_pointers,
descriptor_transfer,
AHB_transfer,
conditional_poll,
conditional_trigger,
stall);
type reg_type is record
dma_state : dma_state_type;
active_chan : integer range 0 to ndmach-1;
conf : conf_type;
chan_conf : channel_vector;
fifo_write_p : std_logic_vector(abits downto 0); --pointer to single bytes
fifo_read_p : std_logic_vector(abits downto 0); --pointer to single bytes
m2bdescp : std_logic_vector(31 downto 0);
m2bdesc : desc_type;
b2mdescp : std_logic_vector(31 downto 0);
b2mdesc : desc_type;
irq : std_logic;
trans_size : std_logic_vector(2 downto 0);
operation_direction : std_logic; -- 0 M2B, 1 B2M
desc_direction : std_logic; -- 0 read 1 write
desc_type : std_logic; -- 0 data desc, 1 cond desc
cond_counter : std_logic_vector(11 downto 0);
cond_counter_rst : std_logic_vector(11 downto 0);
cond_timer_start : std_logic;
init_descriptors : std_logic;
hready : std_logic;
htrans : std_logic_vector(1 downto 0);
active : std_logic;
apb_acc : std_logic;
timer : std_logic_vector(31 downto 0);
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant DESC_RES : desc_type :=
( en => '0',
irq_en => '0',
nextdescp => (others => '0'),
addr => (others => '0'),
size => (others => '0'),
ahbm_num => '0',
status => '0',
complete => '0',
ahb_err => '0',
write_back => '0',
fixed_addr => '0',
cond_en => '0',
cond_irq_trig => '0',
cond_addr_irqn => (others => '0'),
cond_mask => (others => '0'),
cond_op => '0',
cond_tot_size => (others => '0'),
cond_rem_size => (others => '0'),
cond_ahbm_num => '0',
cond_outcome => '0');
constant CHAN_RES : channel_type :=
( en => '0',
irq_en => '0',
status => '0',
complete => '0',
irq_flag => '0');
constant CONF_RES : conf_type :=
( en => '0',
rst => '0',
irq_en => '0',
irq_err_en => '0',
cvp => (others => '0'),
direct_mode => '0',
ch_err => 0,
cvp_err => '0',
desc_err => '0',
ahb_err => '0',
cond_err => '0',
to_err => '0',
err => '0',
trans_size_limit => (others => '0'),
timer_en => '0',
timer_rst => (others => '0'));
constant RES : reg_type :=
( dma_state => idle,
active_chan => 0,
conf => CONF_RES,
chan_conf => (others => CHAN_RES),
fifo_write_p => (others => '0'),
fifo_read_p => (others => '0'),
m2bdescp => (others => '0'),
m2bdesc => DESC_RES,
b2mdescp => (others => '0'),
b2mdesc => DESC_RES,
irq => '0',
trans_size => (others => '0'),
operation_direction => '0',
desc_direction => '0',
desc_type => '0',
cond_counter => (others => '0'),
cond_counter_rst => (others => '0'),
cond_timer_start => '0',
init_descriptors => '0',
hready => '0',
htrans => (others => '0'),
active => '0',
apb_acc => '0',
timer => (others => '0'));
signal dmai : grdmac_ahb_dma_in_type;
signal dmai1 : grdmac_ahb_dma_in_type;
signal dmao : grdmac_ahb_dma_out_type;
signal dmao1 : grdmac_ahb_dma_out_type;
signal l_ahbmo : ahb_mst_out_type;
signal fifoout : std_logic_vector(AHBDW-1 downto 0);
signal r, rin : reg_type;
signal buf_en : std_logic;
signal buf_wr : std_logic;
signal buf_offset : std_logic_vector(log2(AHBDW/8)-1 downto 0);
signal buf_address : std_logic_vector(abits-1 downto 0);
signal buf_size : std_logic_vector(2 downto 0);
signal buf_wdata : std_logic_vector(AHBDW-1 downto 0);
signal buf_rdata : std_logic_vector(AHBDW-1 downto 0);
signal rdescp : std_logic_vector(31 downto 0);
signal rdesc : desc_type;
signal rfifo_p : std_logic_vector(abits downto 0);
begin
comb : process(dmao, dmao1, r, rst, apbi, l_ahbmo, buf_wdata, irq_trig)
variable v : reg_type;
variable vdmai : grdmac_ahb_dma_in_type;
variable vdmao : grdmac_ahb_dma_out_type;
variable inc : std_logic_vector(log2(AHBDW/8) downto 0);
variable pointer : std_logic_vector(abits downto 0);
variable tot_size : std_logic_vector(15 downto 0);
variable enable : std_logic;
variable write : std_logic;
variable vprdata : std_logic_vector(31 downto 0);
variable irq : std_logic_vector(NAHBIRQ-1 downto 0);
variable vdescp : std_logic_vector(31 downto 0);
variable vdesc : desc_type;
variable vfifo_p : std_logic_vector(abits downto 0);
variable desc_wdata : std_logic_vector(31 downto 0);
variable dec_wbmask : std_logic;
variable temp_ahbm_num : std_logic;
variable read_data : std_logic_vector(31 downto 0);
variable hready : std_logic;
variable hresp : std_logic_vector(1 downto 0);
variable active : std_logic;
variable cond_rem_size : std_logic_vector(15 downto 0);
variable timeout_error : std_logic;
begin
v := r;
v.irq := '0';
v.apb_acc := '0';
inc := (others => '0');
tot_size := (others => '0');
enable := '0';
write := '0';
pointer := (others => '0');
desc_wdata := (others => '0');
dec_wbmask := '0';
timeout_error := '0';
-- B2M
rdesc <= r.b2mdesc;
rdescp <= r.b2mdescp;
rfifo_p <= r.fifo_read_p;
if r.operation_direction = '0' then --M2B
rdesc <= r.m2bdesc;
rdescp <= r.m2bdescp;
rfifo_p <= r.fifo_write_p;
end if;
vdesc := rdesc;
vdescp := rdescp;
vfifo_p := rfifo_p;
vdmai.address := (others => '0');
vdmai.size := (others => '0');
vdmai.start := '0';
vdmai.burst := '0';
vdmai.idle := '0';
vdmai.first_beat := '0';
vdmai.write := '0';
vdmai.busy := '0';
vdmai.irq := '0';
if en_ahbm1 /= 0 and (
(r.dma_state = AHB_transfer and rdesc.ahbm_num = '1') or
(r.dma_state = conditional_poll and rdesc.cond_ahbm_num = '1') ) then
-- AHB 1 master selected
vdmao := dmao1;
else
-- default master is AHB 0
vdmao := dmao;
end if;
if conv_integer(r.timer) /= 0 then
v.timer := r.timer - 1;
end if;
temp_ahbm_num := '0';
read_data := (others => '0');
irq := (others => '0');
irq(hirq) := r.irq and r.conf.irq_en;
vprdata := (others => '0');
-- APB slave
-- write (check we are not accessing the internal address debug space: paddr(11) = 0)
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite and not apbi.paddr(11)) = '1' then
case apbi.paddr(7 downto 2) is
when "000000" => -- 0x00 CONTROL REG
v.conf.en := apbi.pwdata(0);
v.conf.rst := apbi.pwdata(1);
v.conf.irq_en := apbi.pwdata(2);
v.conf.irq_err_en := apbi.pwdata(3);
v.conf.direct_mode := apbi.pwdata(4);
v.conf.timer_en := apbi.pwdata(5);
v.conf.trans_size_limit := apbi.pwdata(13 downto 12);
for i in 0 to ndmach-1 loop
v.chan_conf(i).en := apbi.pwdata(i+16);
end loop ;
when "000010" => -- 0x08 INTERRUPT MASK
for i in 0 to ndmach-1 loop
v.chan_conf(i).irq_en := apbi.pwdata(i);
end loop ;
when "000011" => -- 0x0C ERROR REGISTER: CLEAR ON 1
v.conf.err := r.conf.err and (not apbi.pwdata(0));
v.conf.cvp_err := r.conf.cvp_err and (not apbi.pwdata(1));
v.conf.desc_err := r.conf.desc_err and (not apbi.pwdata(2));
v.conf.ahb_err := r.conf.ahb_err and (not apbi.pwdata(3));
v.conf.cond_err := r.conf.cond_err and (not apbi.pwdata(4));
v.conf.to_err := r.conf.to_err and (not apbi.pwdata(5));
when "000100" => -- 0x10 CHANNEL VECTOR POINTER
v.conf.cvp(31 downto 7) := apbi.pwdata(31 downto 7);
v.conf.cvp(6 downto 0) := (others => '0');
when "000101" => -- 0x14 TIMER RST VALUE REGISTER
v.conf.timer_rst(31 downto 0) := apbi.pwdata(31 downto 0);
when "000111" => -- 0x1C INTERRUPT FLAG REGISTER: CLEAR ON 1
for i in 0 to ndmach-1 loop
v.chan_conf(i).irq_flag := r.chan_conf(i).irq_flag and (not apbi.pwdata(i));
end loop ;
-- DIRECT MODE DESCRIPTORS
when "001001" => -- 0x24 M2B DESCRIPTOR : START_ADDRESS
v.m2bdesc.addr := apbi.pwdata(31 downto 0);
when "001010" => -- 0x28 M2B DESCRIPTOR : DESC_CONTROL
v.m2bdesc.en := '1';
v.m2bdesc.irq_en := apbi.pwdata(2);
if en_ahbm1 /= 0 then
v.m2bdesc.ahbm_num := apbi.pwdata(3);
else
v.m2bdesc.ahbm_num := '0';
end if;
v.m2bdesc.fixed_addr := apbi.pwdata(4);
v.m2bdesc.size := apbi.pwdata(31 downto 16);
when "001101" => -- 0x34 B2M DESCRIPTOR : START_ADDRESS
v.b2mdesc.addr := apbi.pwdata(31 downto 0);
when "001110" => -- 0x38 B2M DESCRIPTOR : DESC_CONTROL
v.b2mdesc.en := '1';
v.b2mdesc.irq_en := apbi.pwdata(2);
if en_ahbm1 /= 0 then
v.b2mdesc.ahbm_num := apbi.pwdata(3);
else
v.b2mdesc.ahbm_num := '0';
end if;
v.b2mdesc.fixed_addr := apbi.pwdata(4);
v.b2mdesc.size := apbi.pwdata(31 downto 16);
when others => null;
end case;
end if;
--read
if (apbi.psel(pindex) and not apbi.pwrite and not apbi.paddr(11)) = '1' then
case apbi.paddr(7 downto 2) is
when "000000" => -- 0x00 CONTROL REG
vprdata(0) := r.conf.en;
vprdata(1) := r.conf.rst;
vprdata(2) := r.conf.irq_en;
vprdata(3) := r.conf.irq_err_en;
vprdata(4) := r.conf.direct_mode;
vprdata(5) := r.conf.timer_en;
vprdata(13 downto 12) := r.conf.trans_size_limit;
for i in 0 to ndmach-1 loop
vprdata(i+16) := r.chan_conf(i).en;
end loop ;
when "000001" => -- 0x04 STATUS REG
for i in 0 to ndmach-1 loop
vprdata(i) := r.chan_conf(i).complete;
vprdata(i+16) := r.chan_conf(i).status;
end loop ;
when "000010" => -- 0x08 INTERRUPT MASK
for i in 0 to ndmach-1 loop
vprdata(i) := r.chan_conf(i).irq_en;
end loop;
when "000011" => -- 0x0C ERROR REGISTER
vprdata(0) := r.conf.err;
vprdata(1) := r.conf.cvp_err;
vprdata(2) := r.conf.desc_err;
vprdata(3) := r.conf.ahb_err;
vprdata(4) := r.conf.cond_err;
vprdata(5) := r.conf.to_err;
vprdata(19 downto 16) := conv_std_logic_vector(r.conf.ch_err, 4);
when "000100" => -- 0x10 CHANNEL VECTOR POINTER
vprdata(31 downto 7) := r.conf.cvp(31 downto 7);
when "000101" => -- 0x14 TIMER RST VALUE REGISTER
vprdata(31 downto 0) := r.conf.timer_rst(31 downto 0);
when "000110" => -- 0x18 CAPABILITY REGISTER
vprdata(3 downto 0) := conv_std_logic_vector(VERSION, 4);
vprdata(7 downto 4) := conv_std_logic_vector(ndmach-1, 4);
if en_ahbm1 = 0 then
vprdata(8) := '0';
else
vprdata(8) := '1';
end if;
vprdata(10 downto 9) := conv_std_logic_vector(ft, 2);
if en_timer = 0 then
vprdata(11) := '0';
else
vprdata(11) := '1';
end if;
vprdata(31 downto 16) := conv_std_logic_vector(abits, 16);
when "000111" => -- 0x1C INTERRUPT FLAG REGISTER
for i in 0 to ndmach-1 loop
vprdata(i) := r.chan_conf(i).irq_flag;
end loop ;
when "001000" => -- 0x20 M2B DESCRIPTOR : NEXT_POINTER
vprdata := r.m2bdesc.nextdescp(31 downto 4) & "0000";
when "001001" => -- 0x24 M2B DESCRIPTOR : START_ADDRESS
vprdata := r.m2bdesc.addr;
when "001010" => -- 0x28 M2B DESCRIPTOR : DESC_CONTROL
vprdata(0) := r.m2bdesc.en;
vprdata(2) := r.m2bdesc.irq_en;
vprdata(3) := r.m2bdesc.ahbm_num;
vprdata(4) := r.m2bdesc.fixed_addr;
vprdata(31 downto 16) := r.m2bdesc.size;
when "001011" => -- 0x2C M2B DESCRIPTOR : DESC_STATUS
vprdata(0) := r.m2bdesc.complete;
vprdata(1) := r.m2bdesc.status;
vprdata(2) := r.m2bdesc.ahb_err;
when "001100" => -- 0x30 B2M DESCRIPTOR : NEXT_POINTER
vprdata := r.b2mdesc.nextdescp(31 downto 4) & "0000";
when "001101" => -- 0x34 B2M DESCRIPTOR : START_ADDRESS
vprdata := r.b2mdesc.addr;
when "001110" => -- 0x38 B2M DESCRIPTOR : DESC_CONTROL
vprdata(0) := r.b2mdesc.en;
vprdata(2) := r.b2mdesc.irq_en;
vprdata(3) := r.b2mdesc.ahbm_num;
vprdata(4) := r.b2mdesc.fixed_addr;
vprdata(31 downto 16) := r.b2mdesc.size;
when "001111" => -- 0x3C B2M DESCRIPTOR : DESC_STATUS
vprdata(0) := r.b2mdesc.complete;
vprdata(1) := r.b2mdesc.status;
vprdata(2) := r.b2mdesc.ahb_err;
when "010000" => -- 0x40 INTERNAL DEBUG BYPASS POINTERS
if abits < 16 then
vprdata(31 downto 16) := zero32(15 downto abits) & r.fifo_read_p(abits-1 downto 0);
vprdata(15 downto 0) := zero32(15 downto abits) & r.fifo_write_p(abits-1 downto 0);
else
vprdata(31 downto 16) := r.fifo_read_p(15 downto 0);
vprdata(15 downto 0) := r.fifo_write_p(15 downto 0);
end if;
when others =>
end case;
elsif (apbi.psel(pindex) and not apbi.pwrite and apbi.paddr(11)) = '1' then -- debug read from internal buffer
if r.dma_state = idle and r.conf.en = '0' then
-- only access max 2 KiB of the internal buffer due to APB memory mapping constraints
if abits > 10 then
pointer(10 downto 0) := apbi.paddr(10 downto 0);
else
pointer(abits downto 0) := apbi.paddr(abits downto 0);
end if;
vdmai.size := "010";
v.apb_acc := '1';
enable := '1';
end if;
end if;
-- DMA state machine
case r.dma_state is
when idle =>
if r.conf.en = '1' and r.conf.err = '0' then
if r.conf.direct_mode = '0' then -- normal operation mode
if r.chan_conf(r.active_chan).en = '1' and r.chan_conf(r.active_chan).complete = '0' then
v.dma_state := fetch_cvp_pointers;
v.chan_conf(r.active_chan).status := '1'; -- running
else
if r.active_chan < ndmach - 1 then
v.active_chan := r.active_chan + 1;
end if;
end if;
else -- direct mode, single descriptor chains!
if r.chan_conf(0).en = '1' and r.chan_conf(0).complete = '0' then
v.m2bdesc.nextdescp := (others => '0');
v.b2mdesc.nextdescp := (others => '0');
v.dma_state := control;
v.chan_conf(r.active_chan).status := '1'; -- running
end if;
end if;
end if;
when control => -- main sequencer
if bufsize - conv_integer(r.fifo_write_p) /= 0 and conv_integer(r.m2bdesc.size) > 0 and r.m2bdesc.en = '1' then
if r.m2bdesc.cond_en = '1' and r.m2bdesc.cond_outcome = '0' then -- executing a conditional descriptor
if r.m2bdesc.cond_irq_trig = '0' then
if r.cond_counter = r.cond_counter_rst then
v.dma_state := conditional_poll;
else
v.cond_counter := r.cond_counter + 1;
end if;
else
v.dma_state := conditional_trigger;
end if;
if r.cond_timer_start = '0' and r.conf.timer_en = '1' then
v.timer := r.conf.timer_rst;
v.cond_timer_start := '1';
end if;
else
v.m2bdesc.cond_outcome := '0';
v.dma_state := AHB_transfer;
end if;
v.operation_direction := '0'; --M2B
v.m2bdesc.status := '1';
elsif bufsize - conv_integer(r.fifo_write_p) /= 0 and r.m2bdesc.nextdescp /= zero32 then
v.dma_state := descriptor_transfer;
v.m2bdescp := r.m2bdesc.nextdescp;
v.desc_direction := '0'; --read
v.operation_direction := '0'; --M2B
else
if conv_integer(r.b2mdesc.size) > 0 and r.b2mdesc.en = '1' then
if r.b2mdesc.cond_en = '1' and r.b2mdesc.cond_outcome = '0' then -- executing a conditional descriptor
if r.b2mdesc.cond_irq_trig = '0' then
if r.cond_counter = r.cond_counter_rst then
v.dma_state := conditional_poll;
else
v.cond_counter := r.cond_counter + 1;
end if;
else
v.dma_state := conditional_trigger;
end if;
if r.cond_timer_start = '0' and r.conf.timer_en = '1' then
v.timer := r.conf.timer_rst;
v.cond_timer_start := '1';
end if;
else
v.b2mdesc.cond_outcome := '0';
v.dma_state := AHB_transfer;
end if;
v.operation_direction := '1'; --B2M
v.b2mdesc.status := '1';
elsif r.b2mdesc.nextdescp /= zero32 then
v.dma_state := descriptor_transfer;
v.b2mdescp := r.b2mdesc.nextdescp;
v.desc_direction := '0'; --read
v.operation_direction := '1'; --B2M
else -- end channel
if r.active_chan < ndmach - 1 then -- TODO see if it can be removed
v.active_chan := r.active_chan + 1;
end if;
v.chan_conf(r.active_chan).complete := '1';
v.chan_conf(r.active_chan).status := '0'; -- not running anymore
-- go to next channel
v.dma_state := idle;
end if;
end if;
when fetch_cvp_pointers =>
if vdmao.active = '1' then
vdmai.address := r.conf.cvp(31 downto 7) & (r.conf.cvp(6 downto 0) + "100");
else
vdmai.address := r.conf.cvp(31 downto 7) & conv_std_logic_vector(r.active_chan, 4) & "000";
end if;
if r.conf.cvp(2) = '1' and vdmao.active = '1' then -- idle last ctrl cycle
vdmai.idle := '1';
end if;
vdmai.start := '1';
vdmai.burst := '1';
vdmai.size := "010";
-- no 1kB boundary here
if vdmao.active = '1' and vdmao.ready = '1' then
if vdmao.mexc = '0' then
v.conf.cvp := vdmai.address;
read_data := ahbreadword(vdmao.rdata, r.conf.cvp(4 downto 2));
case r.conf.cvp(2) is
when '0' => -- M2B DESC pointer
v.m2bdescp := read_data;
when '1' => -- B2M DESC pointer
v.b2mdescp := read_data;
when others =>
end case ;
if vdmai.idle = '1' then
v.dma_state := descriptor_transfer;
v.operation_direction := '0'; --M2B
v.init_descriptors := '1';
v.desc_direction := '0'; -- read
end if;
else
vdmai.idle := '1';
v.irq := r.conf.irq_err_en;
v.chan_conf(r.active_chan).irq_flag := v.irq and r.conf.irq_en;
v.chan_conf(r.active_chan).status := '0';
v.conf.ch_err := r.active_chan;
v.conf.err := '1';
v.conf.cvp_err := '1';
v.dma_state := idle;
end if;
end if;
when conditional_poll => -- poll register and check for termination condition
vdmai.address := rdesc.cond_addr_irqn;
if vdmao.active = '1' then -- idle last ctrl cycle
vdmai.idle := '1';
end if;
vdmai.start := '1';
vdmai.burst := '0';
vdmai.size := "010";
-- time-out error when timer is started and timer is 0
timeout_error := r.cond_timer_start and not orv(r.timer);
-- no 1kB boundary here
if vdmao.active = '1' and vdmao.ready = '1' then
if vdmao.mexc = '0' and timeout_error = '0' then
read_data := ahbreadword(vdmao.rdata, rdesc.cond_addr_irqn(4 downto 2));
vdesc.cond_outcome := orv(read_data and rdesc.cond_mask);
if vdesc.cond_outcome = vdesc.cond_op then
v.cond_timer_start := '0';
end if;
if vdmai.idle = '1' then
v.dma_state := control;
vdesc.cond_rem_size := rdesc.cond_tot_size;
v.cond_counter := (others => '0');
end if;
else
vdmai.idle := '1';
v.irq := r.conf.irq_err_en;
v.chan_conf(r.active_chan).irq_flag := v.irq and r.conf.irq_en;
v.chan_conf(r.active_chan).status := '0';
v.conf.ch_err := r.active_chan;
v.conf.err := '1';
v.conf.cond_err := '1';
v.conf.to_err := timeout_error;
v.dma_state := idle;
end if;
end if;
if r.operation_direction = '0' then
v.m2bdesc := vdesc;
v.m2bdescp := vdescp;
else
v.b2mdesc := vdesc;
v.b2mdescp := vdescp;
end if;
when conditional_trigger => -- wait for signal trigger
-- time-out error when timer is started and timer is 0
timeout_error := r.cond_timer_start and not orv(r.timer);
if timeout_error = '1' then
v.irq := r.conf.irq_err_en;
v.chan_conf(r.active_chan).irq_flag := v.irq and r.conf.irq_en;
v.chan_conf(r.active_chan).status := '0';
v.conf.ch_err := r.active_chan;
v.conf.err := '1';
v.conf.cond_err := '1';
v.conf.to_err := timeout_error;
v.dma_state := idle;
elsif irq_trig(conv_integer(rdesc.cond_addr_irqn(5 downto 0))) = '1' then
vdesc.cond_outcome := '1';
vdesc.cond_rem_size := rdesc.cond_tot_size;
v.cond_timer_start := '0';
v.dma_state := control;
end if;
if r.operation_direction = '0' then
v.m2bdesc := vdesc;
v.m2bdescp := vdescp;
else
v.b2mdesc := vdesc;
v.b2mdescp := vdescp;
end if;
when descriptor_transfer => -- fetch M2B descriptor, 32-B aligned, 4- or 8-word read
if vdmao.active = '1' then
if r.desc_direction = '0' then
vdmai.address := rdescp(31 downto 4) & (rdescp(3 downto 0) + "0100");
else
vdmai.address := rdescp(31 downto 4) & "0000";
end if;
else
if r.desc_direction = '0' then
vdmai.address := rdescp;
else
vdmai.address := rdescp(31 downto 4) & "1100";
end if;
end if;
-- idle last ctrl cycle
if (r.desc_direction = '0' and
( (r.desc_type = '0' and rdescp(3 downto 2) = "10") or -- read up to 0x08
(r.desc_type = '1' and rdescp(3 downto 2) = "11"))) or -- read up to 0x0C if conditional desc
(r.desc_direction = '1' and vdmao.active = '1') then
vdmai.idle := '1';
end if;
vdmai.write := r.desc_direction;
vdmai.start := '1';
vdmai.burst := '1';
vdmai.size := "010";
if vdmao.active = '1' and vdmao.ready = '1' then
if vdmao.mexc = '0' then
vdescp := vdmai.address;
read_data := ahbreadword(vdmao.rdata, rdescp(4 downto 2));
if r.desc_direction = '1' then -- writing back descriptor
-- status
desc_wdata(0) := rdesc.complete;
desc_wdata(1) := rdesc.status;
desc_wdata(2) := rdesc.ahb_err;
else
case rdescp(3 downto 2) is
when "00" => -- next desc
vdesc.nextdescp := read_data(31 downto 4) & "0000";
v.desc_type := read_data(0);
when "01" => -- read addr
if r.desc_type = '0' then
vdesc.addr := read_data;
else
vdesc.cond_addr_irqn := read_data;
end if;
when "10" => -- control
if en_ahbm1 /= 0 then
temp_ahbm_num := read_data(3);
end if;
if r.desc_type = '0' then
vdesc.en := read_data(0);
vdesc.write_back := read_data(1);
vdesc.irq_en := read_data(2);
vdesc.ahbm_num := temp_ahbm_num;
vdesc.fixed_addr := read_data(4);
vdesc.size := read_data(31 downto 16);
else
vdesc.cond_en := read_data(0);
vdesc.cond_irq_trig := read_data(1);
vdesc.cond_op := read_data(2);
vdesc.cond_ahbm_num := temp_ahbm_num;
v.cond_counter_rst := read_data(15 downto 4);
v.cond_timer_start := '0';
vdesc.cond_tot_size := read_data(31 downto 16);
end if;
when "11" => -- cond.mask
vdesc.cond_mask := read_data;
when others =>
end case ;
end if;
if vdmai.idle = '1' then
if r.desc_type = '1' then -- fetch data descriptor after fetching the condition descriptor
v.desc_type := '0';
vdescp := rdesc.nextdescp;
elsif r.init_descriptors = '1' then -- initing the first two descriptors (M2B and B2M)
v.operation_direction := '1'; --B2M
v.init_descriptors := '0';
elsif r.conf.err = '1' then
if rdesc.write_back = '1' then --on error and desc wb, generate irq!
v.irq := r.conf.irq_err_en;
v.chan_conf(r.active_chan).irq_flag := v.irq and r.conf.irq_en;
end if;
v.dma_state := idle;
else
if rdesc.write_back = '1' and r.desc_direction = '1' and rdesc.complete = '1' then -- irq generation on completion after write back
v.irq := rdesc.irq_en and r.chan_conf(r.active_chan).irq_en;
v.chan_conf(r.active_chan).irq_flag := v.irq and r.conf.irq_en;
end if;
v.dma_state := control;
end if;
end if;
else
vdmai.idle := '1';
v.irq := r.conf.irq_err_en;
v.chan_conf(r.active_chan).irq_flag := v.irq and r.conf.irq_en;
v.chan_conf(r.active_chan).status := '0';
v.conf.ch_err := r.active_chan;
v.conf.err := '1';
v.conf.desc_err := '1';
v.dma_state := idle;
end if;
end if;
if r.operation_direction = '0' then
v.m2bdesc := vdesc;
v.m2bdescp := vdescp;
else
v.b2mdesc := vdesc;
v.b2mdescp := vdescp;
end if;
when AHB_transfer =>
if vdmao.active = '1' then
inc(conv_integer(r.trans_size(2 downto 0))) := '1';
if rdesc.fixed_addr = '0' then
vdmai.address := rdesc.addr + inc;
else
vdmai.address := rdesc.addr;
end if;
else
vdmai.address := rdesc.addr;
end if;
vdmai.start := '1';
tot_size := rdesc.size - inc;
pointer := rfifo_p + inc;
cond_rem_size := rdesc.cond_rem_size - inc;
dec_wbmask := wtbl(conv_integer(vdmai.address(31 downto 28)));
-- unaligned access check, up to 128b word alignment
if AHBDW >= 128 and busw >= 128 and dec_wbmask = '1'
and ( r.conf.trans_size_limit = "00" or r.conf.trans_size_limit >= "11" )
and vdmai.address(3 downto 0) = "0000" and conv_integer(tot_size) >= 16
and bufsize - conv_integer(pointer) >= 16
and (rdesc.cond_en = '0' or conv_integer(cond_rem_size) >= 16) then --qword aligned
vdmai.burst := '1' and not rdesc.fixed_addr;
vdmai.size := "100";
elsif AHBDW >= 64 and busw >= 64 and dec_wbmask = '1'
and ( r.conf.trans_size_limit = "00" or r.conf.trans_size_limit >= "10" )
and vdmai.address(2 downto 0) = "000" and conv_integer(tot_size) >= 8
and bufsize - conv_integer(pointer) >= 8
and (rdesc.cond_en = '0' or conv_integer(cond_rem_size) >= 8) then --dword aligned
vdmai.burst := '1' and not rdesc.fixed_addr;
vdmai.size := "011";
elsif vdmai.address(1 downto 0) = "00" and conv_integer(tot_size) >= 4
and bufsize - conv_integer(pointer) >= 4
and (rdesc.cond_en = '0' or conv_integer(cond_rem_size) >= 4) then --word aligned
vdmai.burst := '1' and not rdesc.fixed_addr;
vdmai.size := "010";
elsif vdmai.address(0) = '0' and conv_integer(tot_size) >= 2
and bufsize - conv_integer(pointer) >= 2
and (rdesc.cond_en = '0' or conv_integer(cond_rem_size) >= 2) then --half word aligned
vdmai.burst := '0';
vdmai.size := "001";
else --if size = 1 or address(0) = '1' then --byte aligned
vdmai.burst := '0';
vdmai.size := "000";
end if;
if (rdesc.addr(1 downto 0) /= "00" and vdmai.address(1 downto 0) = "00") or -- starting 32bit aligned transfer
(r.trans_size /= vdmai.size) then -- starting new burst with different size
vdmai.first_beat := '1'; -- burst initial transfer
end if;
if (rdesc.addr(burstbit) xor vdmai.address(burstbit)) = '1' then -- burst limitation
vdmai.idle := '1';
end if;
if bufsize - conv_integer(pointer) = 0 or conv_integer(tot_size) = 0 then -- buffer empty/full or descriptor done
vdmai.idle := '1';
end if;
if rdesc.cond_en = '1' and conv_integer(cond_rem_size) = 0 then
vdmai.idle := '1';
end if;
if vdmao.active = '1' then
if vdmao.ready = '1' then
if vdmao.mexc = '0' then
enable := '1';
vdesc.addr := vdmai.address;
vdesc.size := tot_size;
vfifo_p := pointer;
v.trans_size := vdmai.size;
vdesc.cond_rem_size := cond_rem_size;
if r.operation_direction = '0' then
write := '1';
else
write := '0';
if bufsize - conv_integer(pointer) = 0 then -- B2M emptied buffer
v.fifo_write_p := (others => '0');
--v.fifo_read_p := (others => '0');
vfifo_p := (others => '0');
end if;
end if;
if bufsize - conv_integer(pointer) = 0 -- buffer full/empty
or conv_integer(tot_size) = 0 -- descriptor completed
or (rdesc.cond_en = '1' and conv_integer(cond_rem_size) = 0) then -- condition size read/written
v.dma_state := control;
if conv_integer(tot_size) = 0 then
vdesc.status := '0';
vdesc.complete := '1';
vdesc.cond_en := '0';
if rdesc.write_back = '1' then
v.dma_state := descriptor_transfer;
v.desc_direction := '1'; --write
else
v.irq := rdesc.irq_en and r.chan_conf(r.active_chan).irq_en;
v.chan_conf(r.active_chan).irq_flag := v.irq and r.conf.irq_en;
end if;
end if;
end if;
else
vdmai.idle := '1';
v.conf.ch_err := r.active_chan;
v.conf.err := '1';
v.conf.ahb_err := '1';
vdesc.ahb_err := '1';
v.chan_conf(r.active_chan).status := '0';
if rdesc.write_back = '1' then
v.dma_state := descriptor_transfer;
v.desc_direction := '1'; --write
else -- simplified mode is included in this case
v.irq := r.conf.irq_err_en;
v.chan_conf(r.active_chan).irq_flag := v.irq and r.conf.irq_en;
v.dma_state := idle;
end if;
end if;
end if;
else -- dmao.active = '0'
v.trans_size := vdmai.size;
enable := '1'; --reading first data
end if;
if r.operation_direction = '0' then
v.m2bdesc := vdesc;
v.m2bdescp := vdescp;
v.fifo_write_p := vfifo_p;
vdmai.write := '0';
else
v.b2mdesc := vdesc;
v.b2mdescp := vdescp;
v.fifo_read_p := vfifo_p;
vdmai.write := '1';
end if;
when others =>
end case ;
if en_timer = 0 then
v.timer := (others => '0');
v.conf.timer_en := '0';
v.conf.timer_rst := (others => '0');
v.cond_timer_start := '0';
end if;
-- IRQ routing and filtering
ahbmo <= l_ahbmo;
ahbmo.hirq <= irq; --overriding internal master IRQ, which is unused
if (not RESET_ALL) and (rst = '0' or r.conf.rst = '1') then
v.fifo_write_p := (others => '0');
v.fifo_read_p := (others => '0');
v.operation_direction := '0';
v.dma_state := idle;
v.active_chan := 0;
v.init_descriptors := '0';
v.cond_counter := (others => '0');
v.timer := (others => '0');
v.desc_type := '0';
v.conf.rst := '0';
v.conf.en := '0';
v.conf.err := '0';
v.conf.cvp_err := '0';
v.conf.desc_err := '0';
v.conf.ahb_err := '0';
v.conf.cond_err := '0';
v.conf.to_err := '0';
v.conf.timer_en := '0';
v.conf.timer_rst := (others => '0');
v.desc_direction := '0';
v.m2bdesc.complete := '0';
v.m2bdesc.status := '0';
v.m2bdesc.ahb_err := '0';
v.m2bdesc.cond_en := '0';
v.m2bdesc.cond_outcome := '0';
v.m2bdesc.cond_rem_size := (others => '0');
v.b2mdesc.complete := '0';
v.b2mdesc.status := '0';
v.b2mdesc.ahb_err := '0';
v.b2mdesc.cond_en := '0';
v.b2mdesc.cond_outcome := '0';
v.b2mdesc.cond_rem_size := (others => '0');
for i in 0 to ndmach-1 loop
v.chan_conf(i).status := '0';
v.chan_conf(i).complete := '0';
end loop;
end if;
rin <= v;
-- drive AHB 0 Master input
dmai.address <= vdmai.address;
dmai.size <= vdmai.size;
dmai.start <= vdmai.start;
dmai.burst <= vdmai.burst;
dmai.first_beat <= vdmai.first_beat;
dmai.idle <= vdmai.idle;
dmai.write <= vdmai.write;
dmai.busy <= vdmai.busy;
dmai.irq <= vdmai.irq;
dmai.wdata <= buf_wdata;
if r.dma_state = descriptor_transfer then
dmai.wdata <= ahbdrivedata(desc_wdata);
end if;
dmai1 <= grdmac_ahb_dma_in_none;
if en_ahbm1 /= 0 and (
(r.dma_state = AHB_transfer and rdesc.ahbm_num = '1') or
(r.dma_state = conditional_poll and rdesc.cond_ahbm_num = '1') ) then
-- AHB 1 master selected
dmai1.address <= vdmai.address;
dmai1.size <= vdmai.size;
dmai1.start <= vdmai.start;
dmai1.burst <= vdmai.burst;
dmai1.first_beat <= vdmai.first_beat;
dmai1.idle <= vdmai.idle;
dmai1.write <= vdmai.write;
dmai1.busy <= vdmai.busy;
dmai1.irq <= vdmai.irq;
dmai1.wdata <= buf_wdata;
dmai <= grdmac_ahb_dma_in_none;
end if;
-- drive buffer inputs
buf_offset <= vdmai.address(log2(AHBDW/8)-1 downto 0);
buf_address <= pointer(abits-1 downto 0);
buf_size <= vdmai.size;
if r.operation_direction = '0' then
buf_offset <= r.m2bdesc.addr(log2(AHBDW/8)-1 downto 0);
buf_address <= r.fifo_write_p(abits-1 downto 0);
buf_size <= r.trans_size;
end if;
buf_en <= enable;
buf_wr <= write;
buf_rdata <= vdmao.rdata;
if r.apb_acc = '1' then
vprdata := buf_wdata(31 downto 0);
end if;
-- drive APB outputs
apbo <= ( prdata => vprdata,
pirq => (others => '0'),
pconfig => pconfig,
pindex => pindex);
end process;
reg : process(clk)
begin
if rising_edge(clk) then
r <= rin;
if RESET_ALL and rst = '0' then
r <= RES;
end if;
end if;
end process;
-- AHB internal master
dma_mst0: grdmac_ahbmst
generic map (
hindex => hmindex,
venid => VENDOR_GAISLER,
devid => GAISLER_GRDMAC,
version => VERSION,
hirq => hirq,
chprot => 3,
incaddr => 0)
port map (rst, clk, dmai, dmao, ahbmi, l_ahbmo);
-- AHB second internal master
dma_mst1_en: if en_ahbm1 /= 0 generate
dma_mst1: grdmac_ahbmst
generic map (
hindex => hmindex1,
venid => VENDOR_GAISLER,
devid => GAISLER_GRDMAC,
version => VERSION,
hirq => hirq,
chprot => 3,
incaddr => 0)
port map (rst, clk, dmai1, dmao1, ahbmi1, ahbmo1);
end generate;
dma_mst1_dis: if en_ahbm1 = 0 generate
dmao1 <= grdmac_ahb_dma_none;
ahbmo1 <= ahbm_none;
end generate;
-- buffer with support for unaligned read/write
ram: grdmac_alignram
generic map (
memtech => memtech,
abits => abits,
dbits => AHBDW,
testen => testen,
ft => ft)
port map (
clk => clk,
rst => rst,
enable => buf_en,
write => buf_wr,
address => buf_address,
size => buf_size,
dataout => buf_wdata,
datain => buf_rdata,
data_offset => buf_offset);
end architecture ; -- rtl
| gpl-3.0 | 770165b8e6da52044b75c6f0a950ec88 | 0.472411 | 3.607842 | false | false | false | false |
hoglet67/CoPro6502 | src/SYS09/cpu09l.vhd | 1 | 182,039 | --===========================================================================--
-- --
-- Synthesizable 6809 instruction compatible VHDL CPU core --
-- --
--===========================================================================--
--
-- File name : cpu09l.vhd
--
-- Entity name : cpu09
--
-- Purpose : 6809 instruction compatible CPU core written in VHDL
-- with Last Instruction Cycle, bus available, bus status,
-- and instruction fetch signals.
-- Not cycle compatible with the original 6809 CPU
--
-- Dependencies : ieee.std_logic_1164
-- ieee.std_logic_unsigned
--
-- Author : John E. Kent
--
-- Email : [email protected]
--
-- Web : http://opencores.org/project,system09
--
-- Description : VMA (valid memory address) is hight whenever a valid memory
-- access is made by an instruction fetch, interrupt vector fetch
-- or a data read or write otherwise it is low indicating an idle
-- bus cycle.
-- IFETCH (instruction fetch output) is high whenever an
-- instruction byte is read i.e. the program counter is applied
-- to the address bus.
-- LIC (last instruction cycle output) is normally low
-- but goes high on the last cycle of an instruction.
-- BA (bus available output) is normally low but goes high while
-- waiting in a Sync instruction state or the CPU is halted
-- i.e. a DMA grant.
-- BS (bus status output) is normally low but goes high during an
-- interrupt or reset vector fetch or the processor is halted
-- i.e. a DMA grant.
--
-- Copyright (C) 2003 - 2010 John Kent
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--===========================================================================--
-- --
-- Revision History --
-- --
--===========================================================================--
--
-- Version 0.1 - 26 June 2003 - John Kent
-- Added extra level in state stack
-- fixed some calls to the extended addressing state
--
-- Version 0.2 - 5 Sept 2003 - John Kent
-- Fixed 16 bit indexed offset (was doing read rather than fetch)
-- Added/Fixed STY and STS instructions.
-- ORCC_STATE ANDed CC state rather than ORed it - Now fixed
-- CMPX Loaded ACCA and ACCB - Now fixed
--
-- Version 1.0 - 6 Sep 2003 - John Kent
-- Initial release to Open Cores
-- reversed clock edge
--
-- Version 1.1 - 29 November 2003 John kent
-- ACCA and ACCB indexed offsets are 2's complement.
-- ALU Right Mux now sign extends ACCA & ACCB offsets
-- Absolute Indirect addressing performed a read on the
-- second byte of the address rather than a fetch
-- so it formed an incorrect address. Now fixed.
--
-- Version 1.2 - 29 November 2003 John Kent
-- LEAX and LEAY affect the Z bit only
-- LEAS and LEAU do not affect any condition codes
-- added an extra ALU control for LEA.
--
-- Version 1.3 - 12 December 2003 John Kent
-- CWAI did not work, was missed a PUSH_ST on calling
-- the ANDCC_STATE. Thanks go to Ghassan Kraidy for
-- finding this fault.
--
-- Version 1.4 - 12 December 2003 John Kent
-- Missing cc_ctrl assignment in otherwise case of
-- lea_state resulted in cc_ctrl being latched in
-- that state.
-- The otherwise statement should never be reached,
-- and has been fixed simply to resolve synthesis warnings.
--
-- Version 1.5 - 17 january 2004 John kent
-- The clear instruction used "alu_ld8" to control the ALU
-- rather than "alu_clr". This mean the Carry was not being
-- cleared correctly.
--
-- Version 1.6 - 24 January 2004 John Kent
-- Fixed problems in PSHU instruction
--
-- Version 1.7 - 25 January 2004 John Kent
-- removed redundant "alu_inx" and "alu_dex'
-- Removed "test_alu" and "test_cc"
-- STD instruction did not set condition codes
-- JMP direct was not decoded properly
-- CLR direct performed an unwanted read cycle
-- Bogus "latch_md" in Page2 indexed addressing
--
-- Version 1.8 - 27 January 2004 John Kent
-- CWAI in decode1_state should increment the PC.
-- ABX is supposed to be an unsigned addition.
-- Added extra ALU function
-- ASR8 slightly changed in the ALU.
--
-- Version 1.9 - 20 August 2005
-- LSR8 is now handled in ASR8 and ROR8 case in the ALU,
-- rather than LSR16. There was a problem with single
-- operand instructions using the MD register which is
-- sign extended on the first 8 bit fetch.
--
-- Version 1.10 - 13 September 2005
-- TFR & EXG instructions did not work for the Condition Code Register
-- An extra case has been added to the ALU for the alu_tfr control
-- to assign the left ALU input (alu_left) to the condition code
-- outputs (cc_out).
--
-- Version 1.11 - 16 September 2005
-- JSR ,X should not predecrement S before calculating the jump address.
-- The reason is that JSR [0,S] needs S to point to the top of the stack
-- to fetch a valid vector address. The solution is to have the addressing
-- mode microcode called before decrementing S and then decrementing S in
-- JSR_STATE. JSR_STATE in turn calls PUSH_RETURN_LO_STATE rather than
-- PUSH_RETURN_HI_STATE so that both the High & Low halves of the PC are
-- pushed on the stack. This adds one extra bus cycle, but resolves the
-- addressing conflict. I've also removed the pre-decement S in
-- JSR EXTENDED as it also calls JSR_STATE.
--
-- Version 1.12 - 6th June 2006
-- 6809 Programming reference manual says V is not affected by ASR, LSR and ROR
-- This is different to the 6800. CLR should reset the V bit.
--
-- Version 1.13 - 7th July 2006
-- Disable NMI on reset until S Stack pointer has been loaded.
-- Added nmi_enable signal in sp_reg process and nmi_handler process.
--
-- Version 1.14 - 11th July 2006
-- 1. Added new state to RTI called rti_entire_state.
-- This state tests the CC register after it has been loaded
-- from the stack. Previously the current CC was tested which
-- was incorrect. The Entire Flag should be set before the
-- interrupt stacks the CC.
-- 2. On bogus Interrupts, int_cc_state went to rti_state,
-- which was an enumerated state, but not defined anywhere.
-- rti_state has been changed to rti_cc_state so that bogus interrupt
-- will perform an RTI after entering that state.
-- 3. Sync should generate an interrupt if the interrupt masks
-- are cleared. If the interrupt masks are set, then an interrupt
-- will cause the the PC to advance to the next instruction.
-- Note that I don't wait for an interrupt to be asserted for
-- three clock cycles.
-- 4. Added new ALU control state "alu_mul". "alu_mul" is used in
-- the Multiply instruction replacing "alu_add16". This is similar
-- to "alu_add16" except it sets the Carry bit to B7 of the result
-- in ACCB, sets the Zero bit if the 16 bit result is zero, but
-- does not affect The Half carry (H), Negative (N) or Overflow (V)
-- flags. The logic was re-arranged so that it adds md or zero so
-- that the Carry condition code is set on zero multiplicands.
-- 5. DAA (Decimal Adjust Accumulator) should set the Negative (N)
-- and Zero Flags. It will also affect the Overflow (V) flag although
-- the operation is undefined. It's anyones guess what DAA does to V.
--
-- Version 1.15 - 25th Feb 2007 - John Kent
-- line 9672 changed "if Halt <= '1' then" to "if Halt = '1' then"
-- Changed sensitivity lists.
--
-- Version 1.16 - 5th February 2008 - John Kent
-- FIRQ interrupts should take priority over IRQ Interrupts.
-- This presumably means they should be tested for before IRQ
-- when they happen concurrently.
--
-- Version 1.17 - 18th February 2008 - John Kent
-- NMI in CWAI should mask IRQ and FIRQ interrupts
--
-- Version 1.18 - 21st February 2008 - John Kent
-- Removed default register settings in each case statement
-- and placed them at the beginning of the state sequencer.
-- Modified the SYNC instruction so that the interrupt vector(iv)
-- is not set unless an unmasked FIRQ or IRQ is received.
--
-- Version 1.19 - 25th February 2008 - John Kent
-- Enumerated separate states for FIRQ/FAST and NMIIRQ/ENTIRE
-- Enumerated separate states for MASKI and MASKIF states
-- Removed code on BSR/JSR in fetch cycle
--
-- Version 1.20 - 8th October 2011 - John Kent
-- added fetch output which should go high during the fetch cycle
--
-- Version 1.21 - 8th October 2011 - John Kent
-- added Last Instruction Cycle signal
-- replaced fetch with ifetch (instruction fetch) signal
-- added ba & bs (bus available & bus status) signals
--
-- Version 1.22 - 2011-10-29 John Kent
-- The halt state isn't correct.
-- The halt state is entered into from the fetch_state
-- It returned to the fetch state which may re-run an execute cycle
-- on the accumulator and it won't necessarily be the last instruction cycle
-- I've changed the halt state to return to the decode1_state
--
-- Version 1.23 - 2011-10-30 John Kent
-- sample halt in the change_state process if lic is high (last instruction cycle)
--
-- Version 1.24 - 2011-11-01 John Kent
-- Handle interrupts in change_state process
-- Sample interrupt inputs on last instruction cycle
-- Remove iv_ctrl and implement iv (interrupt vector) in change_state process.
-- Generate fic (first instruction cycle) from lic (last instruction cycle)
-- and use it to complete the dual operand execute cycle before servicing
-- halt or interrupts requests.
-- rename lic to lic_out on the entity declaration so that lic can be tested internally.
-- add int_firq1_state and int_nmirq1_state to allow for the dual operand execute cycle
-- integrated nmi_ctrl into change_state process
-- Reduces the microcode state stack to one entry (saved_state)
-- imm16_state jumps directly to the fetch_state
-- pull_return_lo states jumps directly to the fetch_state
-- duplicate andcc_state as cwai_state
-- rename exg1_state as exg2 state and duplicate tfr_state as exg1_state
--
-- Version 1.25 - 2011-11-27 John Kent
-- Changed the microcode for saving registers on an interrupt into a microcode subroutine.
-- Removed SWI servicing from the change state process and made SWI, SWI2 & SWI3
-- call the interrupt microcode subroutine.
-- Added additional states for nmi, and irq for interrupt servicing.
-- Added additional states for nmi/irq, firq, and swi interrupts to mask I & F flags.
--
-- Version 1.26 - 2013-03-18 John Kent
-- pre-initialized cond_true variable to true in state sequencer
-- re-arranged change_state process slightly
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cpu09 is
port (
clk : in std_logic; -- E clock input (rising edge)
rst : in std_logic; -- reset input (active high)
vma : out std_logic; -- valid memory address (active high)
lic_out : out std_logic; -- last instruction cycle (active high)
ifetch : out std_logic; -- instruction fetch cycle (active high)
opfetch : out std_logic; -- opcode fetch (active high)
ba : out std_logic; -- bus available (high on sync wait or DMA grant)
bs : out std_logic; -- bus status (high on interrupt or reset vector fetch or DMA grant)
addr : out std_logic_vector(15 downto 0); -- address bus output
rw : out std_logic; -- read not write output
data_out : out std_logic_vector(7 downto 0); -- data bus output
data_in : in std_logic_vector(7 downto 0); -- data bus input
irq : in std_logic; -- interrupt request input (active high)
firq : in std_logic; -- fast interrupt request input (active high)
nmi : in std_logic; -- non maskable interrupt request input (active high)
halt : in std_logic; -- halt input (active high) grants DMA
hold : in std_logic -- hold input (active high) extend bus cycle
);
end cpu09;
architecture rtl of cpu09 is
constant EBIT : integer := 7;
constant FBIT : integer := 6;
constant HBIT : integer := 5;
constant IBIT : integer := 4;
constant NBIT : integer := 3;
constant ZBIT : integer := 2;
constant VBIT : integer := 1;
constant CBIT : integer := 0;
--
-- Interrupt vector modifiers
--
constant RST_VEC : std_logic_vector(2 downto 0) := "111";
constant NMI_VEC : std_logic_vector(2 downto 0) := "110";
constant SWI_VEC : std_logic_vector(2 downto 0) := "101";
constant IRQ_VEC : std_logic_vector(2 downto 0) := "100";
constant FIRQ_VEC : std_logic_vector(2 downto 0) := "011";
constant SWI2_VEC : std_logic_vector(2 downto 0) := "010";
constant SWI3_VEC : std_logic_vector(2 downto 0) := "001";
constant RESV_VEC : std_logic_vector(2 downto 0) := "000";
type state_type is (-- Start off in Reset
reset_state,
-- Fetch Interrupt Vectors (including reset)
vect_lo_state, vect_hi_state, vect_idle_state,
-- Fetch Instruction Cycle
fetch_state,
-- Decode Instruction Cycles
decode1_state, decode2_state, decode3_state,
-- Calculate Effective Address
imm16_state,
indexed_state, index8_state, index16_state, index16_2_state,
pcrel8_state, pcrel16_state, pcrel16_2_state,
indexaddr_state, indexaddr2_state,
postincr1_state, postincr2_state,
indirect_state, indirect2_state, indirect3_state,
extended_state,
-- single ops
single_op_read_state,
single_op_exec_state,
single_op_write_state,
-- Dual op states
dual_op_read8_state, dual_op_read16_state, dual_op_read16_2_state,
dual_op_write8_state, dual_op_write16_state,
--
sync_state, halt_state, cwai_state,
--
andcc_state, orcc_state,
tfr_state,
exg_state, exg1_state, exg2_state,
lea_state,
-- Multiplication
mul_state, mulea_state, muld_state,
mul0_state, mul1_state, mul2_state, mul3_state,
mul4_state, mul5_state, mul6_state, mul7_state,
-- Branches
lbranch_state, sbranch_state,
-- Jumps, Subroutine Calls and Returns
jsr_state, jmp_state,
push_return_hi_state, push_return_lo_state,
pull_return_hi_state, pull_return_lo_state,
-- Interrupt cycles
int_nmi_state, int_nmi1_state,
int_irq_state, int_irq1_state,
int_firq_state, int_firq1_state,
int_entire_state, int_fast_state,
int_pcl_state, int_pch_state,
int_upl_state, int_uph_state,
int_iyl_state, int_iyh_state,
int_ixl_state, int_ixh_state,
int_dp_state,
int_accb_state, int_acca_state,
int_cc_state,
int_cwai_state,
int_nmimask_state, int_firqmask_state, int_swimask_state, int_irqmask_state,
-- Return From Interrupt
rti_cc_state, rti_entire_state,
rti_acca_state, rti_accb_state,
rti_dp_state,
rti_ixl_state, rti_ixh_state,
rti_iyl_state, rti_iyh_state,
rti_upl_state, rti_uph_state,
rti_pcl_state, rti_pch_state,
-- Push Registers using SP
pshs_state,
pshs_pcl_state, pshs_pch_state,
pshs_upl_state, pshs_uph_state,
pshs_iyl_state, pshs_iyh_state,
pshs_ixl_state, pshs_ixh_state,
pshs_dp_state,
pshs_acca_state, pshs_accb_state,
pshs_cc_state,
-- Pull Registers using SP
puls_state,
puls_cc_state,
puls_acca_state, puls_accb_state,
puls_dp_state,
puls_ixl_state, puls_ixh_state,
puls_iyl_state, puls_iyh_state,
puls_upl_state, puls_uph_state,
puls_pcl_state, puls_pch_state,
-- Push Registers using UP
pshu_state,
pshu_pcl_state, pshu_pch_state,
pshu_spl_state, pshu_sph_state,
pshu_iyl_state, pshu_iyh_state,
pshu_ixl_state, pshu_ixh_state,
pshu_dp_state,
pshu_acca_state, pshu_accb_state,
pshu_cc_state,
-- Pull Registers using UP
pulu_state,
pulu_cc_state,
pulu_acca_state, pulu_accb_state,
pulu_dp_state,
pulu_ixl_state, pulu_ixh_state,
pulu_iyl_state, pulu_iyh_state,
pulu_spl_state, pulu_sph_state,
pulu_pcl_state, pulu_pch_state );
type st_type is (reset_st, push_st, idle_st );
type iv_type is (latch_iv, swi3_iv, swi2_iv, firq_iv, irq_iv, swi_iv, nmi_iv, reset_iv);
type addr_type is (idle_ad, fetch_ad, read_ad, write_ad, pushu_ad, pullu_ad, pushs_ad, pulls_ad, int_hi_ad, int_lo_ad );
type dout_type is (cc_dout, acca_dout, accb_dout, dp_dout,
ix_lo_dout, ix_hi_dout, iy_lo_dout, iy_hi_dout,
up_lo_dout, up_hi_dout, sp_lo_dout, sp_hi_dout,
pc_lo_dout, pc_hi_dout, md_lo_dout, md_hi_dout );
type op_type is (reset_op, fetch_op, latch_op );
type pre_type is (reset_pre, fetch_pre, latch_pre );
type cc_type is (reset_cc, load_cc, pull_cc, latch_cc );
type acca_type is (reset_acca, load_acca, load_hi_acca, pull_acca, latch_acca );
type accb_type is (reset_accb, load_accb, pull_accb, latch_accb );
type dp_type is (reset_dp, load_dp, pull_dp, latch_dp );
type ix_type is (reset_ix, load_ix, pull_lo_ix, pull_hi_ix, latch_ix );
type iy_type is (reset_iy, load_iy, pull_lo_iy, pull_hi_iy, latch_iy );
type sp_type is (reset_sp, latch_sp, load_sp, pull_hi_sp, pull_lo_sp );
type up_type is (reset_up, latch_up, load_up, pull_hi_up, pull_lo_up );
type pc_type is (reset_pc, latch_pc, load_pc, pull_lo_pc, pull_hi_pc, incr_pc );
type md_type is (reset_md, latch_md, load_md, fetch_first_md, fetch_next_md, shiftl_md );
type ea_type is (reset_ea, latch_ea, load_ea, fetch_first_ea, fetch_next_ea );
type left_type is (cc_left, acca_left, accb_left, dp_left,
ix_left, iy_left, up_left, sp_left,
accd_left, md_left, pc_left, ea_left );
type right_type is (ea_right, zero_right, one_right, two_right,
acca_right, accb_right, accd_right,
md_right, md_sign5_right, md_sign8_right );
type alu_type is (alu_add8, alu_sub8, alu_add16, alu_sub16, alu_adc, alu_sbc,
alu_and, alu_ora, alu_eor,
alu_tst, alu_inc, alu_dec, alu_clr, alu_neg, alu_com,
alu_lsr16, alu_lsl16,
alu_ror8, alu_rol8, alu_mul,
alu_asr8, alu_asl8, alu_lsr8,
alu_andcc, alu_orcc, alu_sex, alu_tfr, alu_abx,
alu_seif, alu_sei, alu_see, alu_cle,
alu_ld8, alu_st8, alu_ld16, alu_st16, alu_lea, alu_nop, alu_daa );
signal op_code: std_logic_vector(7 downto 0);
signal pre_code: std_logic_vector(7 downto 0);
signal acca: std_logic_vector(7 downto 0);
signal accb: std_logic_vector(7 downto 0);
signal cc: std_logic_vector(7 downto 0);
signal cc_out: std_logic_vector(7 downto 0);
signal dp: std_logic_vector(7 downto 0);
signal xreg: std_logic_vector(15 downto 0);
signal yreg: std_logic_vector(15 downto 0);
signal sp: std_logic_vector(15 downto 0);
signal up: std_logic_vector(15 downto 0);
signal ea: std_logic_vector(15 downto 0);
signal pc: std_logic_vector(15 downto 0);
signal md: std_logic_vector(15 downto 0);
signal left: std_logic_vector(15 downto 0);
signal right: std_logic_vector(15 downto 0);
signal out_alu: std_logic_vector(15 downto 0);
signal iv: std_logic_vector(2 downto 0);
signal nmi_req: std_logic;
signal nmi_ack: std_logic;
signal nmi_enable: std_logic;
signal fic: std_logic; -- first instruction cycle
signal lic: std_logic; -- last instruction cycle
signal state: state_type;
signal next_state: state_type;
signal return_state: state_type;
signal saved_state: state_type;
signal st_ctrl: st_type;
signal iv_ctrl: iv_type;
signal pc_ctrl: pc_type;
signal ea_ctrl: ea_type;
signal op_ctrl: op_type;
signal pre_ctrl: pre_type;
signal md_ctrl: md_type;
signal acca_ctrl: acca_type;
signal accb_ctrl: accb_type;
signal ix_ctrl: ix_type;
signal iy_ctrl: iy_type;
signal cc_ctrl: cc_type;
signal dp_ctrl: dp_type;
signal sp_ctrl: sp_type;
signal up_ctrl: up_type;
signal left_ctrl: left_type;
signal right_ctrl: right_type;
signal alu_ctrl: alu_type;
signal addr_ctrl: addr_type;
signal dout_ctrl: dout_type;
begin
----------------------------------
--
-- State machine stack
--
----------------------------------
--state_stack_proc: process( clk, hold, state_stack, st_ctrl,
-- return_state, fetch_state )
state_stack_proc: process( clk, st_ctrl, return_state )
begin
if clk'event and clk = '1' then
if hold = '0' then
case st_ctrl is
when reset_st =>
saved_state <= fetch_state;
when push_st =>
saved_state <= return_state;
when others =>
null;
end case;
end if;
end if;
end process;
----------------------------------
--
-- Interrupt Vector control
--
----------------------------------
--
int_vec_proc: process( clk, iv_ctrl )
begin
if clk'event and clk = '1' then
if hold = '0' then
case iv_ctrl is
when reset_iv =>
iv <= RST_VEC;
when nmi_iv =>
iv <= NMI_VEC;
when swi_iv =>
iv <= SWI_VEC;
when irq_iv =>
iv <= IRQ_VEC;
when firq_iv =>
iv <= FIRQ_VEC;
when swi2_iv =>
iv <= SWI2_VEC;
when swi3_iv =>
iv <= SWI3_VEC;
when others =>
null;
end case;
end if; -- hold
end if; -- clk
end process;
----------------------------------
--
-- Program Counter Control
--
----------------------------------
--pc_reg: process( clk, pc_ctrl, hold, pc, out_alu, data_in )
pc_reg: process( clk )
begin
if clk'event and clk = '1' then
if hold = '0' then
case pc_ctrl is
when reset_pc =>
pc <= (others=>'0');
when load_pc =>
pc <= out_alu(15 downto 0);
when pull_lo_pc =>
pc(7 downto 0) <= data_in;
when pull_hi_pc =>
pc(15 downto 8) <= data_in;
when incr_pc =>
pc <= pc + 1;
when others =>
null;
end case;
end if;
end if;
end process;
----------------------------------
--
-- Effective Address Control
--
----------------------------------
--ea_reg: process( clk, ea_ctrl, hold, ea, out_alu, data_in, dp )
ea_reg: process( clk )
begin
if clk'event and clk = '1' then
if hold= '0' then
case ea_ctrl is
when reset_ea =>
ea <= (others=>'0');
when fetch_first_ea =>
ea(7 downto 0) <= data_in;
ea(15 downto 8) <= dp;
when fetch_next_ea =>
ea(15 downto 8) <= ea(7 downto 0);
ea(7 downto 0) <= data_in;
when load_ea =>
ea <= out_alu(15 downto 0);
when others =>
null;
end case;
end if;
end if;
end process;
--------------------------------
--
-- Accumulator A
--
--------------------------------
--acca_reg : process( clk, acca_ctrl, hold, out_alu, acca, data_in )
acca_reg : process( clk )
begin
if clk'event and clk = '1' then
if hold = '0' then
case acca_ctrl is
when reset_acca =>
acca <= (others=>'0');
when load_acca =>
acca <= out_alu(7 downto 0);
when load_hi_acca =>
acca <= out_alu(15 downto 8);
when pull_acca =>
acca <= data_in;
when others =>
null;
end case;
end if;
end if;
end process;
--------------------------------
--
-- Accumulator B
--
--------------------------------
--accb_reg : process( clk, accb_ctrl, hold, out_alu, accb, data_in )
accb_reg : process( clk )
begin
if clk'event and clk = '1' then
if hold = '0' then
case accb_ctrl is
when reset_accb =>
accb <= (others=>'0');
when load_accb =>
accb <= out_alu(7 downto 0);
when pull_accb =>
accb <= data_in;
when others =>
null;
end case;
end if;
end if;
end process;
--------------------------------
--
-- X Index register
--
--------------------------------
--ix_reg : process( clk, ix_ctrl, hold, out_alu, xreg, data_in )
ix_reg : process( clk )
begin
if clk'event and clk = '1' then
if hold = '0' then
case ix_ctrl is
when reset_ix =>
xreg <= (others=>'0');
when load_ix =>
xreg <= out_alu(15 downto 0);
when pull_hi_ix =>
xreg(15 downto 8) <= data_in;
when pull_lo_ix =>
xreg(7 downto 0) <= data_in;
when others =>
null;
end case;
end if;
end if;
end process;
--------------------------------
--
-- Y Index register
--
--------------------------------
--iy_reg : process( clk, iy_ctrl, hold, out_alu, yreg, data_in )
iy_reg : process( clk )
begin
if clk'event and clk = '1' then
if hold = '0' then
case iy_ctrl is
when reset_iy =>
yreg <= (others=>'0');
when load_iy =>
yreg <= out_alu(15 downto 0);
when pull_hi_iy =>
yreg(15 downto 8) <= data_in;
when pull_lo_iy =>
yreg(7 downto 0) <= data_in;
when others =>
null;
end case;
end if;
end if;
end process;
--------------------------------
--
-- S stack pointer
--
--------------------------------
--sp_reg : process( clk, sp_ctrl, hold, sp, out_alu, data_in, nmi_enable )
sp_reg : process( clk )
begin
if clk'event and clk = '1' then
if hold = '0' then
case sp_ctrl is
when reset_sp =>
sp <= (others=>'0');
nmi_enable <= '0';
when load_sp =>
sp <= out_alu(15 downto 0);
nmi_enable <= '1';
when pull_hi_sp =>
sp(15 downto 8) <= data_in;
when pull_lo_sp =>
sp(7 downto 0) <= data_in;
nmi_enable <= '1';
when others =>
null;
end case;
end if;
end if;
end process;
--------------------------------
--
-- U stack pointer
--
--------------------------------
--up_reg : process( clk, up_ctrl, hold, up, out_alu, data_in )
up_reg : process( clk )
begin
if clk'event and clk = '1' then
if hold = '0' then
case up_ctrl is
when reset_up =>
up <= (others=>'0');
when load_up =>
up <= out_alu(15 downto 0);
when pull_hi_up =>
up(15 downto 8) <= data_in;
when pull_lo_up =>
up(7 downto 0) <= data_in;
when others =>
null;
end case;
end if;
end if;
end process;
--------------------------------
--
-- Memory Data
--
--------------------------------
--md_reg : process( clk, md_ctrl, hold, out_alu, data_in, md )
md_reg : process( clk )
begin
if clk'event and clk = '1' then
if hold = '0' then
case md_ctrl is
when reset_md =>
md <= (others=>'0');
when load_md =>
md <= out_alu(15 downto 0);
when fetch_first_md => -- sign extend md for branches
md(15 downto 8) <= data_in(7) & data_in(7) & data_in(7) & data_in(7) &
data_in(7) & data_in(7) & data_in(7) & data_in(7) ;
md(7 downto 0) <= data_in;
when fetch_next_md =>
md(15 downto 8) <= md(7 downto 0);
md(7 downto 0) <= data_in;
when shiftl_md =>
md(15 downto 1) <= md(14 downto 0);
md(0) <= '0';
when others =>
null;
end case;
end if;
end if;
end process;
----------------------------------
--
-- Condition Codes
--
----------------------------------
--cc_reg: process( clk, cc_ctrl, hold, cc_out, cc, data_in )
cc_reg: process( clk )
begin
if clk'event and clk = '1' then
if hold = '0' then
case cc_ctrl is
when reset_cc =>
cc <= "11010000"; -- set EBIT, FBIT & IBIT
when load_cc =>
cc <= cc_out;
when pull_cc =>
cc <= data_in;
when others =>
null;
end case;
end if;
end if;
end process;
----------------------------------
--
-- Direct Page register
--
----------------------------------
--dp_reg: process( clk, dp_ctrl, hold, out_alu, dp, data_in )
dp_reg: process( clk )
begin
if clk'event and clk = '1' then
if hold = '0' then
case dp_ctrl is
when reset_dp =>
dp <= (others=>'0');
when load_dp =>
dp <= out_alu(7 downto 0);
when pull_dp =>
dp <= data_in;
when others =>
null;
end case;
end if;
end if;
end process;
----------------------------------
--
-- op code register
--
----------------------------------
--op_reg: process( clk, op_ctrl, hold, op_code, data_in )
op_reg: process( clk )
begin
if clk'event and clk = '1' then
if hold = '0' then
case op_ctrl is
when reset_op =>
op_code <= "00010010";
when fetch_op =>
op_code <= data_in;
when others =>
null;
end case;
end if;
end if;
end process;
----------------------------------
--
-- pre byte op code register
--
----------------------------------
--pre_reg: process( clk, pre_ctrl, hold, pre_code, data_in )
pre_reg: process( clk )
begin
if clk'event and clk = '1' then
if hold = '0' then
case pre_ctrl is
when reset_pre =>
pre_code <= (others=>'0');
when fetch_pre =>
pre_code <= data_in;
when others =>
null;
end case;
end if;
end if;
end process;
--------------------------------
--
-- state machine
--
--------------------------------
--change_state: process( clk, rst, state, hold, next_state )
change_state: process( clk )
begin
if clk'event and clk = '1' then
if rst = '1' then
fic <= '0';
nmi_ack <= '0';
state <= reset_state;
elsif hold = '0' then
fic <= lic;
--
-- nmi request is not cleared until nmi input goes low
--
if (nmi_req = '0') and (nmi_ack='1') then
nmi_ack <= '0';
end if;
if (nmi_req = '1') and (nmi_ack = '0') and (state = int_nmimask_state) then
nmi_ack <= '1';
end if;
if lic = '1' then
if halt = '1' then
state <= halt_state;
-- service non maskable interrupts
elsif (nmi_req = '1') and (nmi_ack = '0') then
state <= int_nmi_state;
--
-- FIRQ & IRQ are level sensitive
--
elsif (firq = '1') then
if (cc(FBIT) = '0') then
state <= int_firq_state;
else
state <= fetch_state;
end if;
elsif (irq = '1') then
if (cc(IBIT) = '0') then
state <= int_irq_state;
else
state <= fetch_state;
end if;
else
state <= next_state;
end if; -- halt, nmi, firq, irq
else
state <= next_state;
end if; -- lic
end if; -- reset/hold
end if; -- clk
end process;
------------------------------------
--
-- Detect Edge of NMI interrupt
--
------------------------------------
--nmi_handler : process( clk, rst, nmi, nmi_ack, nmi_req, nmi_enable )
nmi_handler : process( rst, clk )
begin
if rst='1' then
nmi_req <= '0';
elsif clk'event and clk='0' then
if (nmi='1') and (nmi_ack='0') and (nmi_enable='1') then
nmi_req <= '1';
else
if (nmi='0') and (nmi_ack='1') then
nmi_req <= '0';
end if;
end if;
end if;
end process;
----------------------------------
--
-- Address output multiplexer
--
----------------------------------
addr_mux: process( addr_ctrl, pc, ea, up, sp, iv )
begin
ifetch <= '0';
vma <= '1';
case addr_ctrl is
when fetch_ad =>
addr <= pc;
rw <= '1';
ifetch <= '1';
when read_ad =>
addr <= ea;
rw <= '1';
when write_ad =>
addr <= ea;
rw <= '0';
when pushs_ad =>
addr <= sp;
rw <= '0';
when pulls_ad =>
addr <= sp;
rw <= '1';
when pushu_ad =>
addr <= up;
rw <= '0';
when pullu_ad =>
addr <= up;
rw <= '1';
when int_hi_ad =>
addr <= "111111111111" & iv & "0";
rw <= '1';
when int_lo_ad =>
addr <= "111111111111" & iv & "1";
rw <= '1';
when others =>
addr <= "1111111111111111";
rw <= '1';
vma <= '0';
end case;
end process;
--------------------------------
--
-- Data Bus output
--
--------------------------------
dout_mux : process( dout_ctrl, md, acca, accb, dp, xreg, yreg, sp, up, pc, cc )
begin
case dout_ctrl is
when cc_dout => -- condition code register
data_out <= cc;
when acca_dout => -- accumulator a
data_out <= acca;
when accb_dout => -- accumulator b
data_out <= accb;
when dp_dout => -- direct page register
data_out <= dp;
when ix_lo_dout => -- X index reg
data_out <= xreg(7 downto 0);
when ix_hi_dout => -- X index reg
data_out <= xreg(15 downto 8);
when iy_lo_dout => -- Y index reg
data_out <= yreg(7 downto 0);
when iy_hi_dout => -- Y index reg
data_out <= yreg(15 downto 8);
when up_lo_dout => -- U stack pointer
data_out <= up(7 downto 0);
when up_hi_dout => -- U stack pointer
data_out <= up(15 downto 8);
when sp_lo_dout => -- S stack pointer
data_out <= sp(7 downto 0);
when sp_hi_dout => -- S stack pointer
data_out <= sp(15 downto 8);
when md_lo_dout => -- alu output
data_out <= md(7 downto 0);
when md_hi_dout => -- alu output
data_out <= md(15 downto 8);
when pc_lo_dout => -- low order pc
data_out <= pc(7 downto 0);
when pc_hi_dout => -- high order pc
data_out <= pc(15 downto 8);
end case;
end process;
----------------------------------
--
-- Left Mux
--
----------------------------------
left_mux: process( left_ctrl, acca, accb, cc, dp, xreg, yreg, up, sp, pc, ea, md )
begin
case left_ctrl is
when cc_left =>
left(15 downto 8) <= "00000000";
left(7 downto 0) <= cc;
when acca_left =>
left(15 downto 8) <= "00000000";
left(7 downto 0) <= acca;
when accb_left =>
left(15 downto 8) <= "00000000";
left(7 downto 0) <= accb;
when dp_left =>
left(15 downto 8) <= "00000000";
left(7 downto 0) <= dp;
when accd_left =>
left(15 downto 8) <= acca;
left(7 downto 0) <= accb;
when md_left =>
left <= md;
when ix_left =>
left <= xreg;
when iy_left =>
left <= yreg;
when sp_left =>
left <= sp;
when up_left =>
left <= up;
when pc_left =>
left <= pc;
when others =>
-- when ea_left =>
left <= ea;
end case;
end process;
----------------------------------
--
-- Right Mux
--
----------------------------------
right_mux: process( right_ctrl, md, acca, accb, ea )
begin
case right_ctrl is
when ea_right =>
right <= ea;
when zero_right =>
right <= "0000000000000000";
when one_right =>
right <= "0000000000000001";
when two_right =>
right <= "0000000000000010";
when acca_right =>
if acca(7) = '0' then
right <= "00000000" & acca(7 downto 0);
else
right <= "11111111" & acca(7 downto 0);
end if;
when accb_right =>
if accb(7) = '0' then
right <= "00000000" & accb(7 downto 0);
else
right <= "11111111" & accb(7 downto 0);
end if;
when accd_right =>
right <= acca & accb;
when md_sign5_right =>
if md(4) = '0' then
right <= "00000000000" & md(4 downto 0);
else
right <= "11111111111" & md(4 downto 0);
end if;
when md_sign8_right =>
if md(7) = '0' then
right <= "00000000" & md(7 downto 0);
else
right <= "11111111" & md(7 downto 0);
end if;
when others =>
-- when md_right =>
right <= md;
end case;
end process;
----------------------------------
--
-- Arithmetic Logic Unit
--
----------------------------------
alu: process( alu_ctrl, cc, left, right, out_alu, cc_out )
variable valid_lo, valid_hi : boolean;
variable carry_in : std_logic;
variable daa_reg : std_logic_vector(7 downto 0);
begin
case alu_ctrl is
when alu_adc | alu_sbc |
alu_rol8 | alu_ror8 =>
carry_in := cc(CBIT);
when alu_asr8 =>
carry_in := left(7);
when others =>
carry_in := '0';
end case;
valid_lo := left(3 downto 0) <= 9;
valid_hi := left(7 downto 4) <= 9;
--
-- CBIT HBIT VHI VLO DAA
-- 0 0 0 0 66 (!VHI : hi_nybble>8)
-- 0 0 0 1 60
-- 0 0 1 1 00
-- 0 0 1 0 06 ( VHI : hi_nybble<=8)
--
-- 0 1 1 0 06
-- 0 1 1 1 06
-- 0 1 0 1 66
-- 0 1 0 0 66
--
-- 1 1 0 0 66
-- 1 1 0 1 66
-- 1 1 1 1 66
-- 1 1 1 0 66
--
-- 1 0 1 0 66
-- 1 0 1 1 60
-- 1 0 0 1 60
-- 1 0 0 0 66
--
-- 66 = (!VHI & !VLO) + (CBIT & HBIT) + (HBIT & !VHI) + (CBIT & !VLO)
-- = (CBIT & (HBIT + !VLO)) + (!VHI & (HBIT + !VLO))
-- = (!VLO & (CBIT + !VHI)) + (HBIT & (CBIT + !VHI))
-- 60 = (CBIT & !HBIT & VLO) + (!HBIT & !VHI & VLO)
-- = (!HBIT & VLO & (CBIT + !VHI))
-- 06 = (!CBIT & VHI & (!VLO + VHI)
-- 00 = (!CBIT & !HBIT & VHI & VLO)
--
if (cc(CBIT) = '0') then
-- CBIT=0
if( cc(HBIT) = '0' ) then
-- HBIT=0
if valid_lo then
-- lo <= 9 (no overflow in low nybble)
if valid_hi then
-- hi <= 9 (no overflow in either low or high nybble)
daa_reg := "00000000";
else
-- hi > 9 (overflow in high nybble only)
daa_reg := "01100000";
end if;
else
-- lo > 9 (overflow in low nybble)
--
-- since there is already an overflow in the low nybble
-- you need to make room in the high nybble for the low nybble carry
-- so compare the high nybble with 8 rather than 9
-- if the high nybble is 9 there will be an overflow on the high nybble
-- after the decimal adjust which means it will roll over to an invalid BCD digit
--
if( left(7 downto 4) <= 8 ) then
-- hi <= 8 (overflow in low nybble only)
daa_reg := "00000110";
else
-- hi > 8 (overflow in low and high nybble)
daa_reg := "01100110";
end if;
end if;
else
-- HBIT=1 (overflow in low nybble)
if valid_hi then
-- hi <= 9 (overflow in low nybble only)
daa_reg := "00000110";
else
-- hi > 9 (overflow in low and high nybble)
daa_reg := "01100110";
end if;
end if;
else
-- CBIT=1 (carry => overflow in high nybble)
if ( cc(HBIT) = '0' )then
-- HBIT=0 (half carry clear => may or may not be an overflow in the low nybble)
if valid_lo then
-- lo <=9 (overflow in high nybble only)
daa_reg := "01100000";
else
-- lo >9 (overflow in low and high nybble)
daa_reg := "01100110";
end if;
else
-- HBIT=1 (overflow in low and high nybble)
daa_reg := "01100110";
end if;
end if;
case alu_ctrl is
when alu_add8 | alu_inc |
alu_add16 | alu_adc | alu_mul =>
out_alu <= left + right + ("000000000000000" & carry_in);
when alu_sub8 | alu_dec |
alu_sub16 | alu_sbc =>
out_alu <= left - right - ("000000000000000" & carry_in);
when alu_abx =>
out_alu <= left + ("00000000" & right(7 downto 0)) ;
when alu_and =>
out_alu <= left and right; -- and/bit
when alu_ora =>
out_alu <= left or right; -- or
when alu_eor =>
out_alu <= left xor right; -- eor/xor
when alu_lsl16 | alu_asl8 | alu_rol8 =>
out_alu <= left(14 downto 0) & carry_in; -- rol8/asl8/lsl16
when alu_lsr16 =>
out_alu <= carry_in & left(15 downto 1); -- lsr16
when alu_lsr8 | alu_asr8 | alu_ror8 =>
out_alu <= "00000000" & carry_in & left(7 downto 1); -- ror8/asr8/lsr8
when alu_neg =>
out_alu <= right - left; -- neg (right=0)
when alu_com =>
out_alu <= not left;
when alu_clr | alu_ld8 | alu_ld16 | alu_lea =>
out_alu <= right; -- clr, ld
when alu_st8 | alu_st16 | alu_andcc | alu_orcc | alu_tfr =>
out_alu <= left;
when alu_daa =>
out_alu <= left + ("00000000" & daa_reg);
when alu_sex =>
if left(7) = '0' then
out_alu <= "00000000" & left(7 downto 0);
else
out_alu <= "11111111" & left(7 downto 0);
end if;
when others =>
out_alu <= left; -- nop
end case;
--
-- carry bit
--
case alu_ctrl is
when alu_add8 | alu_adc =>
cc_out(CBIT) <= (left(7) and right(7)) or
(left(7) and not out_alu(7)) or
(right(7) and not out_alu(7));
when alu_sub8 | alu_sbc =>
cc_out(CBIT) <= ((not left(7)) and right(7)) or
((not left(7)) and out_alu(7)) or
(right(7) and out_alu(7));
when alu_add16 =>
cc_out(CBIT) <= (left(15) and right(15)) or
(left(15) and not out_alu(15)) or
(right(15) and not out_alu(15));
when alu_sub16 =>
cc_out(CBIT) <= ((not left(15)) and right(15)) or
((not left(15)) and out_alu(15)) or
(right(15) and out_alu(15));
when alu_ror8 | alu_lsr16 | alu_lsr8 | alu_asr8 =>
cc_out(CBIT) <= left(0);
when alu_rol8 | alu_asl8 =>
cc_out(CBIT) <= left(7);
when alu_lsl16 =>
cc_out(CBIT) <= left(15);
when alu_com =>
cc_out(CBIT) <= '1';
when alu_neg | alu_clr =>
cc_out(CBIT) <= out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or
out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0);
when alu_mul =>
cc_out(CBIT) <= out_alu(7);
when alu_daa =>
if ( daa_reg(7 downto 4) = "0110" ) then
cc_out(CBIT) <= '1';
else
cc_out(CBIT) <= '0';
end if;
when alu_andcc =>
cc_out(CBIT) <= left(CBIT) and cc(CBIT);
when alu_orcc =>
cc_out(CBIT) <= left(CBIT) or cc(CBIT);
when alu_tfr =>
cc_out(CBIT) <= left(CBIT);
when others =>
cc_out(CBIT) <= cc(CBIT);
end case;
--
-- Zero flag
--
case alu_ctrl is
when alu_add8 | alu_sub8 |
alu_adc | alu_sbc |
alu_and | alu_ora | alu_eor |
alu_inc | alu_dec |
alu_neg | alu_com | alu_clr |
alu_rol8 | alu_ror8 | alu_asr8 | alu_asl8 | alu_lsr8 |
alu_ld8 | alu_st8 | alu_sex | alu_daa =>
cc_out(ZBIT) <= not( out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or
out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0) );
when alu_add16 | alu_sub16 | alu_mul |
alu_lsl16 | alu_lsr16 |
alu_ld16 | alu_st16 | alu_lea =>
cc_out(ZBIT) <= not( out_alu(15) or out_alu(14) or out_alu(13) or out_alu(12) or
out_alu(11) or out_alu(10) or out_alu(9) or out_alu(8) or
out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or
out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0) );
when alu_andcc =>
cc_out(ZBIT) <= left(ZBIT) and cc(ZBIT);
when alu_orcc =>
cc_out(ZBIT) <= left(ZBIT) or cc(ZBIT);
when alu_tfr =>
cc_out(ZBIT) <= left(ZBIT);
when others =>
cc_out(ZBIT) <= cc(ZBIT);
end case;
--
-- negative flag
--
case alu_ctrl is
when alu_add8 | alu_sub8 |
alu_adc | alu_sbc |
alu_and | alu_ora | alu_eor |
alu_rol8 | alu_ror8 | alu_asr8 | alu_asl8 | alu_lsr8 |
alu_inc | alu_dec | alu_neg | alu_com | alu_clr |
alu_ld8 | alu_st8 | alu_sex | alu_daa =>
cc_out(NBIT) <= out_alu(7);
when alu_add16 | alu_sub16 |
alu_lsl16 | alu_lsr16 |
alu_ld16 | alu_st16 =>
cc_out(NBIT) <= out_alu(15);
when alu_andcc =>
cc_out(NBIT) <= left(NBIT) and cc(NBIT);
when alu_orcc =>
cc_out(NBIT) <= left(NBIT) or cc(NBIT);
when alu_tfr =>
cc_out(NBIT) <= left(NBIT);
when others =>
cc_out(NBIT) <= cc(NBIT);
end case;
--
-- Interrupt mask flag
--
case alu_ctrl is
when alu_andcc =>
cc_out(IBIT) <= left(IBIT) and cc(IBIT);
when alu_orcc =>
cc_out(IBIT) <= left(IBIT) or cc(IBIT);
when alu_tfr =>
cc_out(IBIT) <= left(IBIT);
when alu_seif | alu_sei =>
cc_out(IBIT) <= '1';
when others =>
cc_out(IBIT) <= cc(IBIT); -- interrupt mask
end case;
--
-- Half Carry flag
--
case alu_ctrl is
when alu_add8 | alu_adc =>
cc_out(HBIT) <= (left(3) and right(3)) or
(right(3) and not out_alu(3)) or
(left(3) and not out_alu(3));
when alu_andcc =>
cc_out(HBIT) <= left(HBIT) and cc(HBIT);
when alu_orcc =>
cc_out(HBIT) <= left(HBIT) or cc(HBIT);
when alu_tfr =>
cc_out(HBIT) <= left(HBIT);
when others =>
cc_out(HBIT) <= cc(HBIT);
end case;
--
-- Overflow flag
--
case alu_ctrl is
when alu_add8 | alu_adc =>
cc_out(VBIT) <= (left(7) and right(7) and (not out_alu(7))) or
((not left(7)) and (not right(7)) and out_alu(7));
when alu_sub8 | alu_sbc =>
cc_out(VBIT) <= (left(7) and (not right(7)) and (not out_alu(7))) or
((not left(7)) and right(7) and out_alu(7));
when alu_add16 =>
cc_out(VBIT) <= (left(15) and right(15) and (not out_alu(15))) or
((not left(15)) and (not right(15)) and out_alu(15));
when alu_sub16 =>
cc_out(VBIT) <= (left(15) and (not right(15)) and (not out_alu(15))) or
((not left(15)) and right(15) and out_alu(15));
when alu_inc =>
cc_out(VBIT) <= ((not left(7)) and left(6) and left(5) and left(4) and
left(3) and left(2) and left(1) and left(0));
when alu_dec | alu_neg =>
cc_out(VBIT) <= (left(7) and (not left(6)) and (not left(5)) and (not left(4)) and
(not left(3)) and (not left(2)) and (not left(1)) and (not left(0)));
-- 6809 Programming reference manual says
-- V not affected by ASR, LSR and ROR
-- This is different to the 6800
-- John Kent 6th June 2006
-- when alu_asr8 =>
-- cc_out(VBIT) <= left(0) xor left(7);
-- when alu_lsr8 | alu_lsr16 =>
-- cc_out(VBIT) <= left(0);
-- when alu_ror8 =>
-- cc_out(VBIT) <= left(0) xor cc(CBIT);
when alu_lsl16 =>
cc_out(VBIT) <= left(15) xor left(14);
when alu_rol8 | alu_asl8 =>
cc_out(VBIT) <= left(7) xor left(6);
--
-- 11th July 2006 - John Kent
-- What DAA does with V is anyones guess
-- It is undefined in the 6809 programming manual
--
when alu_daa =>
cc_out(VBIT) <= left(7) xor out_alu(7) xor cc(CBIT);
-- CLR resets V Bit
-- John Kent 6th June 2006
when alu_and | alu_ora | alu_eor | alu_com | alu_clr |
alu_st8 | alu_st16 | alu_ld8 | alu_ld16 | alu_sex =>
cc_out(VBIT) <= '0';
when alu_andcc =>
cc_out(VBIT) <= left(VBIT) and cc(VBIT);
when alu_orcc =>
cc_out(VBIT) <= left(VBIT) or cc(VBIT);
when alu_tfr =>
cc_out(VBIT) <= left(VBIT);
when others =>
cc_out(VBIT) <= cc(VBIT);
end case;
case alu_ctrl is
when alu_andcc =>
cc_out(FBIT) <= left(FBIT) and cc(FBIT);
when alu_orcc =>
cc_out(FBIT) <= left(FBIT) or cc(FBIT);
when alu_tfr =>
cc_out(FBIT) <= left(FBIT);
when alu_seif =>
cc_out(FBIT) <= '1';
when others =>
cc_out(FBIT) <= cc(FBIT);
end case;
case alu_ctrl is
when alu_andcc =>
cc_out(EBIT) <= left(EBIT) and cc(EBIT);
when alu_orcc =>
cc_out(EBIT) <= left(EBIT) or cc(EBIT);
when alu_tfr =>
cc_out(EBIT) <= left(EBIT);
when alu_see =>
cc_out(EBIT) <= '1';
when alu_cle =>
cc_out(EBIT) <= '0';
when others =>
cc_out(EBIT) <= cc(EBIT);
end case;
end process;
------------------------------------
--
-- state sequencer
--
------------------------------------
process( state, saved_state,
op_code, pre_code,
cc, ea, md, iv, fic, halt,
nmi_req, firq, irq, lic )
variable cond_true : boolean; -- variable used to evaluate coditional branches
begin
cond_true := (1=1);
ba <= '0';
bs <= '0';
lic <= '0';
opfetch <= '0';
iv_ctrl <= latch_iv;
-- Registers preserved
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
ea_ctrl <= latch_ea;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
-- ALU Idle
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
-- Bus idle
addr_ctrl <= idle_ad;
dout_ctrl <= cc_dout;
-- Next State Fetch
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= fetch_state;
case state is
when reset_state => -- released from reset
-- reset the registers
iv_ctrl <= reset_iv;
op_ctrl <= reset_op;
pre_ctrl <= reset_pre;
cc_ctrl <= reset_cc;
acca_ctrl <= reset_acca;
accb_ctrl <= reset_accb;
dp_ctrl <= reset_dp;
ix_ctrl <= reset_ix;
iy_ctrl <= reset_iy;
up_ctrl <= reset_up;
sp_ctrl <= reset_sp;
pc_ctrl <= reset_pc;
ea_ctrl <= reset_ea;
md_ctrl <= reset_md;
st_ctrl <= reset_st;
next_state <= vect_hi_state;
--
-- Jump via interrupt vector
-- iv holds interrupt type
-- fetch PC hi from vector location
--
when vect_hi_state =>
-- fetch pc low interrupt vector
pc_ctrl <= pull_hi_pc;
addr_ctrl <= int_hi_ad;
bs <= '1';
next_state <= vect_lo_state;
--
-- jump via interrupt vector
-- iv holds vector type
-- fetch PC lo from vector location
--
when vect_lo_state =>
-- fetch the vector low byte
pc_ctrl <= pull_lo_pc;
addr_ctrl <= int_lo_ad;
bs <= '1';
next_state <= fetch_state;
when vect_idle_state =>
--
-- Last Instruction Cycle for SWI, SWI2 & SWI3
--
if op_code = "00111111" then
lic <= '1';
end if;
next_state <= fetch_state;
--
-- Here to fetch an instruction
-- PC points to opcode
--
when fetch_state =>
-- fetch the op code
opfetch <= '1';
op_ctrl <= fetch_op;
pre_ctrl <= fetch_pre;
ea_ctrl <= reset_ea;
-- Fetch op code
addr_ctrl <= fetch_ad;
-- Advance the PC to fetch next instruction byte
pc_ctrl <= incr_pc;
next_state <= decode1_state;
--
-- Here to decode instruction
-- and fetch next byte of intruction
-- whether it be necessary or not
--
when decode1_state =>
-- fetch first byte of address or immediate data
ea_ctrl <= fetch_first_ea;
md_ctrl <= fetch_first_md;
addr_ctrl <= fetch_ad;
case op_code(7 downto 4) is
--
-- direct single op (2 bytes)
-- 6809 => 6 cycles
-- cpu09 => 5 cycles
-- 1 op=(pc) / pc=pc+1
-- 2 ea_hi=dp / ea_lo=(pc) / pc=pc+1
-- 3 md_lo=(ea) / pc=pc
-- 4 alu_left=md / md=alu_out / pc=pc
-- 5 (ea)=md_lo / pc=pc
--
-- Exception is JMP
-- 6809 => 3 cycles
-- cpu09 => 3 cycles
-- 1 op=(pc) / pc=pc+1
-- 2 ea_hi=dp / ea_lo=(pc) / pc=pc+1
-- 3 pc=ea
--
when "0000" =>
-- advance the PC
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "1110" => -- jmp
next_state <= jmp_state;
when "1111" => -- clr
next_state <= single_op_exec_state;
when others =>
next_state <= single_op_read_state;
end case;
-- acca / accb inherent instructions
when "0001" =>
case op_code(3 downto 0) is
--
-- Page2 pre byte
-- pre=(pc) / pc=pc+1
-- op=(pc) / pc=pc+1
--
when "0000" => -- page2
opfetch <= '1';
op_ctrl <= fetch_op;
-- advance pc
pc_ctrl <= incr_pc;
next_state <= decode2_state;
--
-- Page3 pre byte
-- pre=(pc) / pc=pc+1
-- op=(pc) / pc=pc+1
--
when "0001" => -- page3
opfetch <= '1';
op_ctrl <= fetch_op;
-- advance pc
pc_ctrl <= incr_pc;
next_state <= decode3_state;
--
-- nop - No operation ( 1 byte )
-- 6809 => 2 cycles
-- cpu09 => 2 cycles
-- 1 op=(pc) / pc=pc+1
-- 2 decode
--
when "0010" => -- nop
lic <= '1';
next_state <= fetch_state;
--
-- sync - halt execution until an interrupt is received
-- interrupt may be NMI, IRQ or FIRQ
-- program execution continues if the
-- interrupt is asserted for 3 clock cycles
-- note that registers are not pushed onto the stack
-- CPU09 => Interrupts need only be asserted for one clock cycle
--
when "0011" => -- sync
next_state <= sync_state;
--
-- lbra -- long branch (3 bytes)
-- 6809 => 5 cycles
-- cpu09 => 4 cycles
-- 1 op=(pc) / pc=pc+1
-- 2 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1
-- 3 md_hi=md_lo / md_lo=(pc) / pc=pc+1
-- 4 pc=pc+md
--
when "0110" =>
-- increment the pc
pc_ctrl <= incr_pc;
next_state <= lbranch_state;
--
-- lbsr - long branch to subroutine (3 bytes)
-- 6809 => 9 cycles
-- cpu09 => 6 cycles
-- 1 op=(pc) /pc=pc+1
-- 2 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1 / sp=sp-1
-- 3 md_hi=md_lo / md_lo=(pc) / pc=pc+1
-- 4 (sp)= pc_lo / sp=sp-1 / pc=pc
-- 5 (sp)=pc_hi / pc=pc
-- 6 pc=pc+md
--
when "0111" =>
-- pre decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- increment the pc
pc_ctrl <= incr_pc;
next_state <= lbranch_state;
--
-- Decimal Adjust Accumulator
--
when "1001" => -- daa
left_ctrl <= acca_left;
right_ctrl <= accb_right;
alu_ctrl <= alu_daa;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
lic <= '1';
next_state <= fetch_state;
--
-- OR Condition Codes
--
when "1010" => -- orcc
-- increment the pc
pc_ctrl <= incr_pc;
next_state <= orcc_state;
--
-- AND Condition Codes
--
when "1100" => -- andcc
-- increment the pc
pc_ctrl <= incr_pc;
next_state <= andcc_state;
--
-- Sign Extend
--
when "1101" => -- sex
left_ctrl <= accb_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_sex;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
lic <= '1';
next_state <= fetch_state;
--
-- Exchange Registers
--
when "1110" => -- exg
-- increment the pc
pc_ctrl <= incr_pc;
next_state <= exg_state;
--
-- Transfer Registers
--
when "1111" => -- tfr
-- increment the pc
pc_ctrl <= incr_pc;
next_state <= tfr_state;
when others =>
-- increment the pc
pc_ctrl <= incr_pc;
lic <= '1';
next_state <= fetch_state;
end case;
--
-- Short branch conditional
-- 6809 => always 3 cycles
-- cpu09 => always = 3 cycles
-- 1 op=(pc) / pc=pc+1
-- 2 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1 / test cc
-- 3 if cc tru pc=pc+md else pc=pc
--
when "0010" => -- branch conditional
-- increment the pc
pc_ctrl <= incr_pc;
next_state <= sbranch_state;
--
-- Single byte stack operators
-- Do not advance PC
--
when "0011" =>
--
-- lea - load effective address (2+ bytes)
-- 6809 => 4 cycles + addressing mode
-- cpu09 => 4 cycles + addressing mode
-- 1 op=(pc) / pc=pc+1
-- 2 md_lo=(pc) / pc=pc+1
-- 3 calculate ea
-- 4 ix/iy/sp/up = ea
--
case op_code(3 downto 0) is
when "0000" | -- leax
"0001" | -- leay
"0010" | -- leas
"0011" => -- leau
-- advance PC
pc_ctrl <= incr_pc;
st_ctrl <= push_st;
return_state <= lea_state;
next_state <= indexed_state;
--
-- pshs - push registers onto sp stack
-- 6809 => 5 cycles + registers
-- cpu09 => 3 cycles + registers
-- 1 op=(pc) / pc=pc+1
-- 2 ea_lo=(pc) / pc=pc+1
-- 3 if ea(7 downto 0) != "00000000" then sp=sp-1
-- 4 if ea(7) = 1 (sp)=pcl, sp=sp-1
-- 5 if ea(7) = 1 (sp)=pch
-- if ea(6 downto 0) != "0000000" then sp=sp-1
-- 6 if ea(6) = 1 (sp)=upl, sp=sp-1
-- 7 if ea(6) = 1 (sp)=uph
-- if ea(5 downto 0) != "000000" then sp=sp-1
-- 8 if ea(5) = 1 (sp)=iyl, sp=sp-1
-- 9 if ea(5) = 1 (sp)=iyh
-- if ea(4 downto 0) != "00000" then sp=sp-1
-- 10 if ea(4) = 1 (sp)=ixl, sp=sp-1
-- 11 if ea(4) = 1 (sp)=ixh
-- if ea(3 downto 0) != "0000" then sp=sp-1
-- 12 if ea(3) = 1 (sp)=dp
-- if ea(2 downto 0) != "000" then sp=sp-1
-- 13 if ea(2) = 1 (sp)=accb
-- if ea(1 downto 0) != "00" then sp=sp-1
-- 14 if ea(1) = 1 (sp)=acca
-- if ea(0 downto 0) != "0" then sp=sp-1
-- 15 if ea(0) = 1 (sp)=cc
--
when "0100" => -- pshs
-- advance PC
pc_ctrl <= incr_pc;
next_state <= pshs_state;
--
-- puls - pull registers of sp stack
-- 6809 => 5 cycles + registers
-- cpu09 => 3 cycles + registers
--
when "0101" => -- puls
-- advance PC
pc_ctrl <= incr_pc;
next_state <= puls_state;
--
-- pshu - push registers onto up stack
-- 6809 => 5 cycles + registers
-- cpu09 => 3 cycles + registers
--
when "0110" => -- pshu
-- advance PC
pc_ctrl <= incr_pc;
next_state <= pshu_state;
--
-- pulu - pull registers of up stack
-- 6809 => 5 cycles + registers
-- cpu09 => 3 cycles + registers
--
when "0111" => -- pulu
-- advance PC
pc_ctrl <= incr_pc;
next_state <= pulu_state;
--
-- rts - return from subroutine
-- 6809 => 5 cycles
-- cpu09 => 4 cycles
-- 1 op=(pc) / pc=pc+1
-- 2 decode op
-- 3 pc_hi = (sp) / sp=sp+1
-- 4 pc_lo = (sp) / sp=sp+1
--
when "1001" =>
next_state <= pull_return_hi_state;
--
-- ADD accb to index register
-- *** Note: this is an unsigned addition.
-- does not affect any condition codes
-- 6809 => 3 cycles
-- cpu09 => 2 cycles
-- 1 op=(pc) / pc=pc+1
-- 2 alu_left=ix / alu_right=accb / ix=alu_out / pc=pc
--
when "1010" => -- abx
lic <= '1';
left_ctrl <= ix_left;
right_ctrl <= accb_right;
alu_ctrl <= alu_abx;
ix_ctrl <= load_ix;
next_state <= fetch_state;
--
-- Return From Interrupt
--
when "1011" => -- rti
next_state <= rti_cc_state;
--
-- CWAI
--
when "1100" => -- cwai #$<cc_mask>
-- pre decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- increment pc
pc_ctrl <= incr_pc;
next_state <= cwai_state;
--
-- MUL Multiply
--
when "1101" => -- mul
next_state <= mul_state;
--
-- SWI Software Interrupt
--
when "1111" => -- swi
-- predecrement SP
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
iv_ctrl <= swi_iv;
st_ctrl <= push_st;
return_state <= int_swimask_state;
next_state <= int_entire_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
--
-- Accumulator A Single operand
-- source = acca, dest = acca
-- Do not advance PC
-- Typically 2 cycles 1 bytes
-- 1 opcode fetch
-- 2 post byte fetch / instruction decode
-- Note that there is no post byte
-- so do not advance PC in decode cycle
-- Re-run opcode fetch cycle after decode
--
when "0100" => -- acca single op
left_ctrl <= acca_left;
case op_code(3 downto 0) is
when "0000" => -- neg
right_ctrl <= zero_right;
alu_ctrl <= alu_neg;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "0011" => -- com
right_ctrl <= zero_right;
alu_ctrl <= alu_com;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "0100" => -- lsr
right_ctrl <= zero_right;
alu_ctrl <= alu_lsr8;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "0110" => -- ror
right_ctrl <= zero_right;
alu_ctrl <= alu_ror8;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "0111" => -- asr
right_ctrl <= zero_right;
alu_ctrl <= alu_asr8;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "1000" => -- asl
right_ctrl <= zero_right;
alu_ctrl <= alu_asl8;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "1001" => -- rol
right_ctrl <= zero_right;
alu_ctrl <= alu_rol8;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "1010" => -- dec
right_ctrl <= one_right;
alu_ctrl <= alu_dec;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "1011" => -- undefined
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
acca_ctrl <= latch_acca;
cc_ctrl <= latch_cc;
when "1100" => -- inc
right_ctrl <= one_right;
alu_ctrl <= alu_inc;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "1101" => -- tst
right_ctrl <= zero_right;
alu_ctrl <= alu_st8;
acca_ctrl <= latch_acca;
cc_ctrl <= load_cc;
when "1110" => -- jmp (not defined)
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
acca_ctrl <= latch_acca;
cc_ctrl <= latch_cc;
when "1111" => -- clr
right_ctrl <= zero_right;
alu_ctrl <= alu_clr;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when others =>
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
acca_ctrl <= latch_acca;
cc_ctrl <= latch_cc;
end case;
lic <= '1';
next_state <= fetch_state;
--
-- Single Operand accb
-- source = accb, dest = accb
-- Typically 2 cycles 1 bytes
-- 1 opcode fetch
-- 2 post byte fetch / instruction decode
-- Note that there is no post byte
-- so do not advance PC in decode cycle
-- Re-run opcode fetch cycle after decode
--
when "0101" =>
left_ctrl <= accb_left;
case op_code(3 downto 0) is
when "0000" => -- neg
right_ctrl <= zero_right;
alu_ctrl <= alu_neg;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "0011" => -- com
right_ctrl <= zero_right;
alu_ctrl <= alu_com;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "0100" => -- lsr
right_ctrl <= zero_right;
alu_ctrl <= alu_lsr8;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "0110" => -- ror
right_ctrl <= zero_right;
alu_ctrl <= alu_ror8;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "0111" => -- asr
right_ctrl <= zero_right;
alu_ctrl <= alu_asr8;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "1000" => -- asl
right_ctrl <= zero_right;
alu_ctrl <= alu_asl8;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "1001" => -- rol
right_ctrl <= zero_right;
alu_ctrl <= alu_rol8;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "1010" => -- dec
right_ctrl <= one_right;
alu_ctrl <= alu_dec;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "1011" => -- undefined
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
when "1100" => -- inc
right_ctrl <= one_right;
alu_ctrl <= alu_inc;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "1101" => -- tst
right_ctrl <= zero_right;
alu_ctrl <= alu_st8;
accb_ctrl <= latch_accb;
cc_ctrl <= load_cc;
when "1110" => -- jmp (undefined)
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
when "1111" => -- clr
right_ctrl <= zero_right;
alu_ctrl <= alu_clr;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when others =>
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
end case;
lic <= '1';
next_state <= fetch_state;
--
-- Single operand indexed
-- Two byte instruction so advance PC
-- EA should hold index offset
--
when "0110" => -- indexed single op
-- increment the pc
pc_ctrl <= incr_pc;
st_ctrl <= push_st;
case op_code(3 downto 0) is
when "1110" => -- jmp
return_state <= jmp_state;
when "1111" => -- clr
return_state <= single_op_exec_state;
when others =>
return_state <= single_op_read_state;
end case;
next_state <= indexed_state;
--
-- Single operand extended addressing
-- three byte instruction so advance the PC
-- Low order EA holds high order address
--
when "0111" => -- extended single op
-- increment PC
pc_ctrl <= incr_pc;
st_ctrl <= push_st;
case op_code(3 downto 0) is
when "1110" => -- jmp
return_state <= jmp_state;
when "1111" => -- clr
return_state <= single_op_exec_state;
when others =>
return_state <= single_op_read_state;
end case;
next_state <= extended_state;
when "1000" => -- acca immediate
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- subd #
"1100" | -- cmpx #
"1110" => -- ldx #
next_state <= imm16_state;
--
-- bsr offset - Branch to subroutine (2 bytes)
-- 6809 => 7 cycles
-- cpu09 => 5 cycles
-- 1 op=(pc) / pc=pc+1
-- 2 md_hi=sign(pc) / md_lo=(pc) / sp=sp-1 / pc=pc+1
-- 3 (sp)=pc_lo / sp=sp-1
-- 4 (sp)=pc_hi
-- 5 pc=pc+md
--
when "1101" => -- bsr
-- pre decrement SP
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
--
st_ctrl <= push_st;
return_state <= sbranch_state;
next_state <= push_return_lo_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
when "1001" => -- acca direct
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- subd
"1100" | -- cmpx
"1110" => -- ldx
next_state <= dual_op_read16_state;
when "0111" => -- sta direct
next_state <= dual_op_write8_state;
--
-- jsr direct - Jump to subroutine in direct page (2 bytes)
-- 6809 => 7 cycles
-- cpu09 => 5 cycles
-- 1 op=(pc) / pc=pc+1
-- 2 ea_hi=0 / ea_lo=(pc) / sp=sp-1 / pc=pc+1
-- 3 (sp)=pc_lo / sp=sp-1
-- 4 (sp)=pc_hi
-- 5 pc=ea
--
when "1101" => -- jsr direct
-- pre decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
--
st_ctrl <= push_st;
return_state <= jmp_state;
next_state <= push_return_lo_state;
when "1111" => -- stx direct
-- idle ALU
left_ctrl <= ix_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
sp_ctrl <= latch_sp;
next_state <= dual_op_write16_state;
when others =>
next_state <= dual_op_read8_state;
end case;
when "1010" => -- acca indexed
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- subd
"1100" | -- cmpx
"1110" => -- ldx
st_ctrl <= push_st;
return_state <= dual_op_read16_state;
next_state <= indexed_state;
when "0111" => -- staa ,x
st_ctrl <= push_st;
return_state <= dual_op_write8_state;
next_state <= indexed_state;
when "1101" => -- jsr ,x
-- DO NOT pre decrement SP
st_ctrl <= push_st;
return_state <= jsr_state;
next_state <= indexed_state;
when "1111" => -- stx ,x
st_ctrl <= push_st;
return_state <= dual_op_write16_state;
next_state <= indexed_state;
when others =>
st_ctrl <= push_st;
return_state <= dual_op_read8_state;
next_state <= indexed_state;
end case;
when "1011" => -- acca extended
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- subd
"1100" | -- cmpx
"1110" => -- ldx
st_ctrl <= push_st;
return_state <= dual_op_read16_state;
next_state <= extended_state;
when "0111" => -- staa >
st_ctrl <= push_st;
return_state <= dual_op_write8_state;
next_state <= extended_state;
when "1101" => -- jsr >extended
-- DO NOT pre decrement sp
st_ctrl <= push_st;
return_state <= jsr_state;
next_state <= extended_state;
when "1111" => -- stx >
st_ctrl <= push_st;
return_state <= dual_op_write16_state;
next_state <= extended_state;
when others =>
st_ctrl <= push_st;
return_state <= dual_op_read8_state;
next_state <= extended_state;
end case;
when "1100" => -- accb immediate
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- addd #
"1100" | -- ldd #
"1110" => -- ldu #
next_state <= imm16_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
when "1101" => -- accb direct
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- addd
"1100" | -- ldd
"1110" => -- ldu
next_state <= dual_op_read16_state;
when "0111" => -- stab direct
next_state <= dual_op_write8_state;
when "1101" => -- std direct
next_state <= dual_op_write16_state;
when "1111" => -- stu direct
next_state <= dual_op_write16_state;
when others =>
next_state <= dual_op_read8_state;
end case;
when "1110" => -- accb indexed
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- addd
"1100" | -- ldd
"1110" => -- ldu
st_ctrl <= push_st;
return_state <= dual_op_read16_state;
next_state <= indexed_state;
when "0111" => -- stab indexed
st_ctrl <= push_st;
return_state <= dual_op_write8_state;
next_state <= indexed_state;
when "1101" => -- std indexed
st_ctrl <= push_st;
return_state <= dual_op_write16_state;
next_state <= indexed_state;
when "1111" => -- stu indexed
st_ctrl <= push_st;
return_state <= dual_op_write16_state;
next_state <= indexed_state;
when others =>
st_ctrl <= push_st;
return_state <= dual_op_read8_state;
next_state <= indexed_state;
end case;
when "1111" => -- accb extended
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- addd
"1100" | -- ldd
"1110" => -- ldu
st_ctrl <= push_st;
return_state <= dual_op_read16_state;
next_state <= extended_state;
when "0111" => -- stab extended
st_ctrl <= push_st;
return_state <= dual_op_write8_state;
next_state <= extended_state;
when "1101" => -- std extended
st_ctrl <= push_st;
return_state <= dual_op_write16_state;
next_state <= extended_state;
when "1111" => -- stu extended
st_ctrl <= push_st;
return_state <= dual_op_write16_state;
next_state <= extended_state;
when others =>
st_ctrl <= push_st;
return_state <= dual_op_read8_state;
next_state <= extended_state;
end case;
--
-- not sure why I need this
--
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
--
-- Here to decode prefix 2 instruction
-- and fetch next byte of intruction
-- whether it be necessary or not
--
when decode2_state =>
-- fetch first byte of address or immediate data
ea_ctrl <= fetch_first_ea;
md_ctrl <= fetch_first_md;
addr_ctrl <= fetch_ad;
case op_code(7 downto 4) is
--
-- lbcc -- long branch conditional
-- 6809 => branch 6 cycles, no branch 5 cycles
-- cpu09 => always 5 cycles
-- 1 pre=(pc) / pc=pc+1
-- 2 op=(pc) / pc=pc+1
-- 3 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1
-- 4 md_hi=md_lo / md_lo=(pc) / pc=pc+1
-- 5 if cond pc=pc+md else pc=pc
--
when "0010" =>
-- increment the pc
pc_ctrl <= incr_pc;
next_state <= lbranch_state;
--
-- Single byte stack operators
-- Do not advance PC
--
when "0011" =>
case op_code(3 downto 0) is
when "1111" => -- swi 2
-- predecrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
iv_ctrl <= swi2_iv;
st_ctrl <= push_st;
return_state <= vect_hi_state;
next_state <= int_entire_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
when "1000" => -- acca immediate
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- cmpd #
"1100" | -- cmpy #
"1110" => -- ldy #
next_state <= imm16_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
when "1001" => -- acca direct
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- cmpd <
"1100" | -- cmpy <
"1110" => -- ldy <
next_state <= dual_op_read16_state;
when "1111" => -- sty <
next_state <= dual_op_write16_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
when "1010" => -- acca indexed
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- cmpd ,ind
"1100" | -- cmpy ,ind
"1110" => -- ldy ,ind
st_ctrl <= push_st;
return_state <= dual_op_read16_state;
next_state <= indexed_state;
when "1111" => -- sty ,ind
st_ctrl <= push_st;
return_state <= dual_op_write16_state;
next_state <= indexed_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
when "1011" => -- acca extended
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- cmpd <
"1100" | -- cmpy <
"1110" => -- ldy <
st_ctrl <= push_st;
return_state <= dual_op_read16_state;
next_state <= extended_state;
when "1111" => -- sty >
st_ctrl <= push_st;
return_state <= dual_op_write16_state;
next_state <= extended_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
when "1100" => -- accb immediate
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- undef #
"1100" | -- undef #
"1110" => -- lds #
next_state <= imm16_state;
when others =>
next_state <= fetch_state;
end case;
when "1101" => -- accb direct
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- undef <
"1100" | -- undef <
"1110" => -- lds <
next_state <= dual_op_read16_state;
when "1111" => -- sts <
next_state <= dual_op_write16_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
when "1110" => -- accb indexed
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- undef ,ind
"1100" | -- undef ,ind
"1110" => -- lds ,ind
st_ctrl <= push_st;
return_state <= dual_op_read16_state;
next_state <= indexed_state;
when "1111" => -- sts ,ind
st_ctrl <= push_st;
return_state <= dual_op_write16_state;
next_state <= indexed_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
when "1111" => -- accb extended
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- undef >
"1100" | -- undef >
"1110" => -- lds >
st_ctrl <= push_st;
return_state <= dual_op_read16_state;
next_state <= extended_state;
when "1111" => -- sts >
st_ctrl <= push_st;
return_state <= dual_op_write16_state;
next_state <= extended_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
--
-- Here to decode instruction
-- and fetch next byte of intruction
-- whether it be necessary or not
--
when decode3_state =>
ea_ctrl <= fetch_first_ea;
md_ctrl <= fetch_first_md;
addr_ctrl <= fetch_ad;
dout_ctrl <= md_lo_dout;
case op_code(7 downto 4) is
--
-- Single byte stack operators
-- Do not advance PC
--
when "0011" =>
case op_code(3 downto 0) is
when "1111" => -- swi3
-- predecrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
iv_ctrl <= swi3_iv;
st_ctrl <= push_st;
return_state <= vect_hi_state;
next_state <= int_entire_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
when "1000" => -- acca immediate
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- cmpu #
"1100" | -- cmps #
"1110" => -- undef #
next_state <= imm16_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
when "1001" => -- acca direct
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- cmpu <
"1100" | -- cmps <
"1110" => -- undef <
next_state <= dual_op_read16_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
when "1010" => -- acca indexed
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- cmpu ,X
"1100" | -- cmps ,X
"1110" => -- undef ,X
st_ctrl <= push_st;
return_state <= dual_op_read16_state;
next_state <= indexed_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
when "1011" => -- acca extended
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- cmpu >
"1100" | -- cmps >
"1110" => -- undef >
st_ctrl <= push_st;
return_state <= dual_op_read16_state;
next_state <= extended_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
--
-- here if ea holds low byte
-- Direct
-- Extended
-- Indexed
-- read memory location
--
when single_op_read_state =>
-- read memory into md
md_ctrl <= fetch_first_md;
addr_ctrl <= read_ad;
dout_ctrl <= md_lo_dout;
next_state <= single_op_exec_state;
when single_op_exec_state =>
case op_code(3 downto 0) is
when "0000" => -- neg
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_neg;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= single_op_write_state;
when "0011" => -- com
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_com;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= single_op_write_state;
when "0100" => -- lsr
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_lsr8;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= single_op_write_state;
when "0110" => -- ror
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_ror8;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= single_op_write_state;
when "0111" => -- asr
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_asr8;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= single_op_write_state;
when "1000" => -- asl
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_asl8;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= single_op_write_state;
when "1001" => -- rol
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_rol8;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= single_op_write_state;
when "1010" => -- dec
left_ctrl <= md_left;
right_ctrl <= one_right;
alu_ctrl <= alu_dec;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= single_op_write_state;
when "1011" => -- undefined
lic <= '1';
next_state <= fetch_state;
when "1100" => -- inc
left_ctrl <= md_left;
right_ctrl <= one_right;
alu_ctrl <= alu_inc;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= single_op_write_state;
when "1101" => -- tst
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st8;
cc_ctrl <= load_cc;
lic <= '1';
next_state <= fetch_state;
when "1110" => -- jmp
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_ld16;
pc_ctrl <= load_pc;
lic <= '1';
next_state <= fetch_state;
when "1111" => -- clr
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_clr;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= single_op_write_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
--
-- single operand 8 bit write
-- Write low 8 bits of ALU output
-- EA holds address
-- MD holds data
--
when single_op_write_state =>
-- write ALU low byte output
addr_ctrl <= write_ad;
dout_ctrl <= md_lo_dout;
lic <= '1';
next_state <= fetch_state;
--
-- here if ea holds address of low byte
-- read memory location
--
when dual_op_read8_state =>
-- read first data byte from ea
md_ctrl <= fetch_first_md;
addr_ctrl <= read_ad;
lic <= '1';
next_state <= fetch_state;
--
-- Here to read a 16 bit value into MD
-- pointed to by the EA register
-- The first byte is read
-- and the EA is incremented
--
when dual_op_read16_state =>
-- increment the effective address
left_ctrl <= ea_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
-- read the high byte of the 16 bit data
md_ctrl <= fetch_first_md;
addr_ctrl <= read_ad;
next_state <= dual_op_read16_2_state;
--
-- here to read the second byte
-- pointed to by EA into MD
--
when dual_op_read16_2_state =>
-- read the low byte of the 16 bit data
md_ctrl <= fetch_next_md;
addr_ctrl <= read_ad;
lic <= '1';
next_state <= fetch_state;
--
-- 16 bit Write state
-- EA hold address of memory to write to
-- Advance the effective address in ALU
-- decode op_code to determine which
-- register to write
--
when dual_op_write16_state =>
-- increment the effective address
left_ctrl <= ea_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
-- write the ALU hi byte at ea
addr_ctrl <= write_ad;
if op_code(6) = '0' then
case op_code(3 downto 0) is
when "1111" => -- stx / sty
case pre_code is
when "00010000" => -- page 2 -- sty
dout_ctrl <= iy_hi_dout;
when others => -- page 1 -- stx
dout_ctrl <= ix_hi_dout;
end case;
when others =>
dout_ctrl <= md_hi_dout;
end case;
else
case op_code(3 downto 0) is
when "1101" => -- std
dout_ctrl <= acca_dout; -- acca is high byte of ACCD
when "1111" => -- stu / sts
case pre_code is
when "00010000" => -- page 2 -- sts
dout_ctrl <= sp_hi_dout;
when others => -- page 1 -- stu
dout_ctrl <= up_hi_dout;
end case;
when others =>
dout_ctrl <= md_hi_dout;
end case;
end if;
next_state <= dual_op_write8_state;
--
-- Dual operand 8 bit write
-- Write 8 bit accumulator
-- or low byte of 16 bit register
-- EA holds address
-- decode opcode to determine
-- which register to apply to the bus
-- Also set the condition codes here
--
when dual_op_write8_state =>
if op_code(6) = '0' then
case op_code(3 downto 0) is
when "0111" => -- sta
dout_ctrl <= acca_dout;
when "1111" => -- stx / sty
case pre_code is
when "00010000" => -- page 2 -- sty
dout_ctrl <= iy_lo_dout;
when others => -- page 1 -- stx
dout_ctrl <= ix_lo_dout;
end case;
when others =>
dout_ctrl <= md_lo_dout;
end case;
else
case op_code(3 downto 0) is
when "0111" => -- stb
dout_ctrl <= accb_dout;
when "1101" => -- std
dout_ctrl <= accb_dout; -- accb is low byte of accd
when "1111" => -- stu / sts
case pre_code is
when "00010000" => -- page 2 -- sts
dout_ctrl <= sp_lo_dout;
when others => -- page 1 -- stu
dout_ctrl <= up_lo_dout;
end case;
when others =>
dout_ctrl <= md_lo_dout;
end case;
end if;
-- write ALU low byte output
addr_ctrl <= write_ad;
lic <= '1';
next_state <= fetch_state;
--
-- 16 bit immediate addressing mode
--
when imm16_state =>
-- increment pc
pc_ctrl <= incr_pc;
-- fetch next immediate byte
md_ctrl <= fetch_next_md;
addr_ctrl <= fetch_ad;
lic <= '1';
next_state <= fetch_state;
--
-- md & ea holds 8 bit index offset
-- calculate the effective memory address
-- using the alu
--
when indexed_state =>
--
-- decode indexing mode
--
if md(7) = '0' then
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
right_ctrl <= md_sign5_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
next_state <= saved_state;
else
case md(3 downto 0) is
when "0000" => -- ,R+
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
left_ctrl <= sp_left;
end case;
--
right_ctrl <= zero_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
next_state <= postincr1_state;
when "0001" => -- ,R++
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
right_ctrl <= zero_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
next_state <= postincr2_state;
when "0010" => -- ,-R
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
ix_ctrl <= load_ix;
when "01" =>
left_ctrl <= iy_left;
iy_ctrl <= load_iy;
when "10" =>
left_ctrl <= up_left;
up_ctrl <= load_up;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
sp_ctrl <= load_sp;
end case;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
ea_ctrl <= load_ea;
next_state <= saved_state;
when "0011" => -- ,--R
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
ix_ctrl <= load_ix;
when "01" =>
left_ctrl <= iy_left;
iy_ctrl <= load_iy;
when "10" =>
left_ctrl <= up_left;
up_ctrl <= load_up;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
sp_ctrl <= load_sp;
end case;
right_ctrl <= two_right;
alu_ctrl <= alu_sub16;
ea_ctrl <= load_ea;
if md(4) = '0' then
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
when "0100" => -- ,R (zero offset)
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
right_ctrl <= zero_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
if md(4) = '0' then
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
when "0101" => -- ACCB,R
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
right_ctrl <= accb_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
if md(4) = '0' then
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
when "0110" => -- ACCA,R
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
right_ctrl <= acca_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
if md(4) = '0' then
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
when "0111" => -- undefined
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
right_ctrl <= zero_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
if md(4) = '0' then
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
when "1000" => -- offset8,R
md_ctrl <= fetch_first_md; -- pick up 8 bit offset
addr_ctrl <= fetch_ad;
pc_ctrl <= incr_pc;
next_state <= index8_state;
when "1001" => -- offset16,R
md_ctrl <= fetch_first_md; -- pick up first byte of 16 bit offset
addr_ctrl <= fetch_ad;
pc_ctrl <= incr_pc;
next_state <= index16_state;
when "1010" => -- undefined
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
right_ctrl <= zero_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
--
if md(4) = '0' then
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
when "1011" => -- ACCD,R
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
right_ctrl <= accd_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
if md(4) = '0' then
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
when "1100" => -- offset8,PC
-- fetch 8 bit offset
md_ctrl <= fetch_first_md;
addr_ctrl <= fetch_ad;
pc_ctrl <= incr_pc;
next_state <= pcrel8_state;
when "1101" => -- offset16,PC
-- fetch offset
md_ctrl <= fetch_first_md;
addr_ctrl <= fetch_ad;
pc_ctrl <= incr_pc;
next_state <= pcrel16_state;
when "1110" => -- undefined
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
right_ctrl <= zero_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
if md(4) = '0' then
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
when others =>
-- when "1111" => -- [,address]
-- advance PC to pick up address
md_ctrl <= fetch_first_md;
addr_ctrl <= fetch_ad;
pc_ctrl <= incr_pc;
next_state <= indexaddr_state;
end case;
end if;
-- load index register with ea plus one
when postincr1_state =>
left_ctrl <= ea_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
case md(6 downto 5) is
when "00" =>
ix_ctrl <= load_ix;
when "01" =>
iy_ctrl <= load_iy;
when "10" =>
up_ctrl <= load_up;
when others =>
-- when "11" =>
sp_ctrl <= load_sp;
end case;
-- return to previous state
if md(4) = '0' then
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
-- load index register with ea plus two
when postincr2_state =>
-- increment register by two (address)
left_ctrl <= ea_left;
right_ctrl <= two_right;
alu_ctrl <= alu_add16;
case md(6 downto 5) is
when "00" =>
ix_ctrl <= load_ix;
when "01" =>
iy_ctrl <= load_iy;
when "10" =>
up_ctrl <= load_up;
when others =>
-- when "11" =>
sp_ctrl <= load_sp;
end case;
-- return to previous state
if md(4) = '0' then
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
--
-- ea = index register + md (8 bit signed offset)
-- ea holds post byte
--
when index8_state =>
case ea(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
-- ea = index reg + md
right_ctrl <= md_sign8_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
-- return to previous state
if ea(4) = '0' then
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
-- fetch low byte of 16 bit indexed offset
when index16_state =>
-- advance pc
pc_ctrl <= incr_pc;
-- fetch low byte
md_ctrl <= fetch_next_md;
addr_ctrl <= fetch_ad;
next_state <= index16_2_state;
-- ea = index register + md (16 bit offset)
-- ea holds post byte
when index16_2_state =>
case ea(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
-- ea = index reg + md
right_ctrl <= md_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
-- return to previous state
if ea(4) = '0' then
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
--
-- pc relative with 8 bit signed offest
-- md holds signed offset
--
when pcrel8_state =>
-- ea = pc + signed md
left_ctrl <= pc_left;
right_ctrl <= md_sign8_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
-- return to previous state
if ea(4) = '0' then
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
-- pc relative addressing with 16 bit offset
-- pick up the low byte of the offset in md
-- advance the pc
when pcrel16_state =>
-- advance pc
pc_ctrl <= incr_pc;
-- fetch low byte
md_ctrl <= fetch_next_md;
addr_ctrl <= fetch_ad;
next_state <= pcrel16_2_state;
-- pc relative with16 bit signed offest
-- md holds signed offset
when pcrel16_2_state =>
-- ea = pc + md
left_ctrl <= pc_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
-- return to previous state
if ea(4) = '0' then
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
-- indexed to address
-- pick up the low byte of the address
-- advance the pc
when indexaddr_state =>
-- advance pc
pc_ctrl <= incr_pc;
-- fetch low byte
md_ctrl <= fetch_next_md;
addr_ctrl <= fetch_ad;
next_state <= indexaddr2_state;
-- indexed to absolute address
-- md holds address
-- ea hold indexing mode byte
when indexaddr2_state =>
-- ea = md
left_ctrl <= pc_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
ea_ctrl <= load_ea;
-- return to previous state
if ea(4) = '0' then
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
--
-- load md with high byte of indirect address
-- pointed to by ea
-- increment ea
--
when indirect_state =>
-- increment ea
left_ctrl <= ea_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
-- fetch high byte
md_ctrl <= fetch_first_md;
addr_ctrl <= read_ad;
next_state <= indirect2_state;
--
-- load md with low byte of indirect address
-- pointed to by ea
-- ea has previously been incremented
--
when indirect2_state =>
-- fetch high byte
md_ctrl <= fetch_next_md;
addr_ctrl <= read_ad;
dout_ctrl <= md_lo_dout;
next_state <= indirect3_state;
--
-- complete idirect addressing
-- by loading ea with md
--
when indirect3_state =>
-- load ea with md
left_ctrl <= ea_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
ea_ctrl <= load_ea;
-- return to previous state
next_state <= saved_state;
--
-- ea holds the low byte of the absolute address
-- Move ea low byte into ea high byte
-- load new ea low byte to for absolute 16 bit address
-- advance the program counter
--
when extended_state => -- fetch ea low byte
-- increment pc
pc_ctrl <= incr_pc;
-- fetch next effective address bytes
ea_ctrl <= fetch_next_ea;
addr_ctrl <= fetch_ad;
-- return to previous state
next_state <= saved_state;
when lea_state => -- here on load effective address
-- load index register with effective address
left_ctrl <= pc_left;
right_ctrl <= ea_right;
alu_ctrl <= alu_lea;
case op_code(3 downto 0) is
when "0000" => -- leax
cc_ctrl <= load_cc;
ix_ctrl <= load_ix;
when "0001" => -- leay
cc_ctrl <= load_cc;
iy_ctrl <= load_iy;
when "0010" => -- leas
sp_ctrl <= load_sp;
when "0011" => -- leau
up_ctrl <= load_up;
when others =>
null;
end case;
lic <= '1';
next_state <= fetch_state;
--
-- jump to subroutine
-- sp=sp-1
-- call push_return_lo_state to save pc
-- return to jmp_state
--
when jsr_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- call push_return_state
st_ctrl <= push_st;
return_state <= jmp_state;
next_state <= push_return_lo_state;
--
-- Load pc with ea
-- (JMP)
--
when jmp_state =>
-- load PC with effective address
left_ctrl <= pc_left;
right_ctrl <= ea_right;
alu_ctrl <= alu_ld16;
pc_ctrl <= load_pc;
lic <= '1';
next_state <= fetch_state;
--
-- long branch or branch to subroutine
-- pick up next md byte
-- md_hi = md_lo
-- md_lo = (pc)
-- pc=pc+1
-- if a lbsr push return address
-- continue to sbranch_state
-- to evaluate conditional branches
--
when lbranch_state =>
pc_ctrl <= incr_pc;
-- fetch the next byte into md_lo
md_ctrl <= fetch_next_md;
addr_ctrl <= fetch_ad;
-- if lbsr - push return address
-- then continue on to short branch
if op_code = "00010111" then
st_ctrl <= push_st;
return_state <= sbranch_state;
next_state <= push_return_lo_state;
else
next_state <= sbranch_state;
end if;
--
-- here to execute conditional branch
-- short conditional branch md = signed 8 bit offset
-- long branch md = 16 bit offset
--
when sbranch_state =>
left_ctrl <= pc_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add16;
-- Test condition for branch
if op_code(7 downto 4) = "0010" then -- conditional branch
case op_code(3 downto 0) is
when "0000" => -- bra
cond_true := (1 = 1);
when "0001" => -- brn
cond_true := (1 = 0);
when "0010" => -- bhi
cond_true := ((cc(CBIT) or cc(ZBIT)) = '0');
when "0011" => -- bls
cond_true := ((cc(CBIT) or cc(ZBIT)) = '1');
when "0100" => -- bcc/bhs
cond_true := (cc(CBIT) = '0');
when "0101" => -- bcs/blo
cond_true := (cc(CBIT) = '1');
when "0110" => -- bne
cond_true := (cc(ZBIT) = '0');
when "0111" => -- beq
cond_true := (cc(ZBIT) = '1');
when "1000" => -- bvc
cond_true := (cc(VBIT) = '0');
when "1001" => -- bvs
cond_true := (cc(VBIT) = '1');
when "1010" => -- bpl
cond_true := (cc(NBIT) = '0');
when "1011" => -- bmi
cond_true := (cc(NBIT) = '1');
when "1100" => -- bge
cond_true := ((cc(NBIT) xor cc(VBIT)) = '0');
when "1101" => -- blt
cond_true := ((cc(NBIT) xor cc(VBIT)) = '1');
when "1110" => -- bgt
cond_true := ((cc(ZBIT) or (cc(NBIT) xor cc(VBIT))) = '0');
when "1111" => -- ble
cond_true := ((cc(ZBIT) or (cc(NBIT) xor cc(VBIT))) = '1');
when others =>
null;
end case;
end if;
if cond_true then
pc_ctrl <= load_pc;
end if;
lic <= '1';
next_state <= fetch_state;
--
-- push return address onto the S stack
--
-- (sp) = pc_lo
-- sp = sp - 1
--
when push_return_lo_state =>
-- decrement the sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write PC low
addr_ctrl <= pushs_ad;
dout_ctrl <= pc_lo_dout;
next_state <= push_return_hi_state;
--
-- push program counter hi byte onto the stack
-- (sp) = pc_hi
-- sp = sp
-- return to originating state
--
when push_return_hi_state =>
-- write pc hi bytes
addr_ctrl <= pushs_ad;
dout_ctrl <= pc_hi_dout;
next_state <= saved_state;
--
-- RTS pull return address from stack
--
when pull_return_hi_state =>
-- increment the sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read pc hi
pc_ctrl <= pull_hi_pc;
addr_ctrl <= pulls_ad;
next_state <= pull_return_lo_state;
when pull_return_lo_state =>
-- increment the SP
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read pc low
pc_ctrl <= pull_lo_pc;
addr_ctrl <= pulls_ad;
dout_ctrl <= pc_lo_dout;
--
lic <= '1';
next_state <= fetch_state;
when andcc_state =>
-- AND CC with md
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_andcc;
cc_ctrl <= load_cc;
--
lic <= '1';
next_state <= fetch_state;
when orcc_state =>
-- OR CC with md
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_orcc;
cc_ctrl <= load_cc;
--
lic <= '1';
next_state <= fetch_state;
when tfr_state =>
-- select source register
case md(7 downto 4) is
when "0000" =>
left_ctrl <= accd_left;
when "0001" =>
left_ctrl <= ix_left;
when "0010" =>
left_ctrl <= iy_left;
when "0011" =>
left_ctrl <= up_left;
when "0100" =>
left_ctrl <= sp_left;
when "0101" =>
left_ctrl <= pc_left;
when "1000" =>
left_ctrl <= acca_left;
when "1001" =>
left_ctrl <= accb_left;
when "1010" =>
left_ctrl <= cc_left;
when "1011" =>
left_ctrl <= dp_left;
when others =>
left_ctrl <= md_left;
end case;
right_ctrl <= zero_right;
alu_ctrl <= alu_tfr;
-- select destination register
case md(3 downto 0) is
when "0000" => -- accd
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
when "0001" => -- ix
ix_ctrl <= load_ix;
when "0010" => -- iy
iy_ctrl <= load_iy;
when "0011" => -- up
up_ctrl <= load_up;
when "0100" => -- sp
sp_ctrl <= load_sp;
when "0101" => -- pc
pc_ctrl <= load_pc;
when "1000" => -- acca
acca_ctrl <= load_acca;
when "1001" => -- accb
accb_ctrl <= load_accb;
when "1010" => -- cc
cc_ctrl <= load_cc;
when "1011" => --dp
dp_ctrl <= load_dp;
when others =>
null;
end case;
--
lic <= '1';
next_state <= fetch_state;
when exg_state =>
-- save destination register
case md(3 downto 0) is
when "0000" =>
left_ctrl <= accd_left;
when "0001" =>
left_ctrl <= ix_left;
when "0010" =>
left_ctrl <= iy_left;
when "0011" =>
left_ctrl <= up_left;
when "0100" =>
left_ctrl <= sp_left;
when "0101" =>
left_ctrl <= pc_left;
when "1000" =>
left_ctrl <= acca_left;
when "1001" =>
left_ctrl <= accb_left;
when "1010" =>
left_ctrl <= cc_left;
when "1011" =>
left_ctrl <= dp_left;
when others =>
left_ctrl <= md_left;
end case;
right_ctrl <= zero_right;
alu_ctrl <= alu_tfr;
ea_ctrl <= load_ea;
-- call tranfer microcode
next_state <= exg1_state;
when exg1_state =>
-- select source register
case md(7 downto 4) is
when "0000" =>
left_ctrl <= accd_left;
when "0001" =>
left_ctrl <= ix_left;
when "0010" =>
left_ctrl <= iy_left;
when "0011" =>
left_ctrl <= up_left;
when "0100" =>
left_ctrl <= sp_left;
when "0101" =>
left_ctrl <= pc_left;
when "1000" =>
left_ctrl <= acca_left;
when "1001" =>
left_ctrl <= accb_left;
when "1010" =>
left_ctrl <= cc_left;
when "1011" =>
left_ctrl <= dp_left;
when others =>
left_ctrl <= md_left;
end case;
right_ctrl <= zero_right;
alu_ctrl <= alu_tfr;
-- select destination register
case md(3 downto 0) is
when "0000" => -- accd
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
when "0001" => -- ix
ix_ctrl <= load_ix;
when "0010" => -- iy
iy_ctrl <= load_iy;
when "0011" => -- up
up_ctrl <= load_up;
when "0100" => -- sp
sp_ctrl <= load_sp;
when "0101" => -- pc
pc_ctrl <= load_pc;
when "1000" => -- acca
acca_ctrl <= load_acca;
when "1001" => -- accb
accb_ctrl <= load_accb;
when "1010" => -- cc
cc_ctrl <= load_cc;
when "1011" => --dp
dp_ctrl <= load_dp;
when others =>
null;
end case;
next_state <= exg2_state;
when exg2_state =>
-- restore destination
left_ctrl <= ea_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_tfr;
-- save as source register
case md(7 downto 4) is
when "0000" => -- accd
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
when "0001" => -- ix
ix_ctrl <= load_ix;
when "0010" => -- iy
iy_ctrl <= load_iy;
when "0011" => -- up
up_ctrl <= load_up;
when "0100" => -- sp
sp_ctrl <= load_sp;
when "0101" => -- pc
pc_ctrl <= load_pc;
when "1000" => -- acca
acca_ctrl <= load_acca;
when "1001" => -- accb
accb_ctrl <= load_accb;
when "1010" => -- cc
cc_ctrl <= load_cc;
when "1011" => --dp
dp_ctrl <= load_dp;
when others =>
null;
end case;
lic <= '1';
next_state <= fetch_state;
when mul_state =>
-- move acca to md
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
md_ctrl <= load_md;
next_state <= mulea_state;
when mulea_state =>
-- move accb to ea
left_ctrl <= accb_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
ea_ctrl <= load_ea;
next_state <= muld_state;
when muld_state =>
-- clear accd
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_ld8;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
next_state <= mul0_state;
when mul0_state =>
-- if bit 0 of ea set, add accd to md
left_ctrl <= accd_left;
if ea(0) = '1' then
right_ctrl <= md_right;
else
right_ctrl <= zero_right;
end if;
alu_ctrl <= alu_mul;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
md_ctrl <= shiftl_md;
next_state <= mul1_state;
when mul1_state =>
-- if bit 1 of ea set, add accd to md
left_ctrl <= accd_left;
if ea(1) = '1' then
right_ctrl <= md_right;
else
right_ctrl <= zero_right;
end if;
alu_ctrl <= alu_mul;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
md_ctrl <= shiftl_md;
next_state <= mul2_state;
when mul2_state =>
-- if bit 2 of ea set, add accd to md
left_ctrl <= accd_left;
if ea(2) = '1' then
right_ctrl <= md_right;
else
right_ctrl <= zero_right;
end if;
alu_ctrl <= alu_mul;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
md_ctrl <= shiftl_md;
next_state <= mul3_state;
when mul3_state =>
-- if bit 3 of ea set, add accd to md
left_ctrl <= accd_left;
if ea(3) = '1' then
right_ctrl <= md_right;
else
right_ctrl <= zero_right;
end if;
alu_ctrl <= alu_mul;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
md_ctrl <= shiftl_md;
next_state <= mul4_state;
when mul4_state =>
-- if bit 4 of ea set, add accd to md
left_ctrl <= accd_left;
if ea(4) = '1' then
right_ctrl <= md_right;
else
right_ctrl <= zero_right;
end if;
alu_ctrl <= alu_mul;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
md_ctrl <= shiftl_md;
next_state <= mul5_state;
when mul5_state =>
-- if bit 5 of ea set, add accd to md
left_ctrl <= accd_left;
if ea(5) = '1' then
right_ctrl <= md_right;
else
right_ctrl <= zero_right;
end if;
alu_ctrl <= alu_mul;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
md_ctrl <= shiftl_md;
next_state <= mul6_state;
when mul6_state =>
-- if bit 6 of ea set, add accd to md
left_ctrl <= accd_left;
if ea(6) = '1' then
right_ctrl <= md_right;
else
right_ctrl <= zero_right;
end if;
alu_ctrl <= alu_mul;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
md_ctrl <= shiftl_md;
next_state <= mul7_state;
when mul7_state =>
-- if bit 7 of ea set, add accd to md
left_ctrl <= accd_left;
if ea(7) = '1' then
right_ctrl <= md_right;
else
right_ctrl <= zero_right;
end if;
alu_ctrl <= alu_mul;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
md_ctrl <= shiftl_md;
lic <= '1';
next_state <= fetch_state;
--
-- Enter here on pushs
-- ea holds post byte
--
when pshs_state =>
-- decrement sp if any registers to be pushed
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
-- idle address
addr_ctrl <= idle_ad;
dout_ctrl <= cc_dout;
if ea(7 downto 0) = "00000000" then
sp_ctrl <= latch_sp;
else
sp_ctrl <= load_sp;
end if;
if ea(7) = '1' then
next_state <= pshs_pcl_state;
elsif ea(6) = '1' then
next_state <= pshs_upl_state;
elsif ea(5) = '1' then
next_state <= pshs_iyl_state;
elsif ea(4) = '1' then
next_state <= pshs_ixl_state;
elsif ea(3) = '1' then
next_state <= pshs_dp_state;
elsif ea(2) = '1' then
next_state <= pshs_accb_state;
elsif ea(1) = '1' then
next_state <= pshs_acca_state;
elsif ea(0) = '1' then
next_state <= pshs_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pshs_pcl_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write pc low
addr_ctrl <= pushs_ad;
dout_ctrl <= pc_lo_dout;
next_state <= pshs_pch_state;
when pshs_pch_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(6 downto 0) = "0000000" then
sp_ctrl <= latch_sp;
else
sp_ctrl <= load_sp;
end if;
-- write pc hi
addr_ctrl <= pushs_ad;
dout_ctrl <= pc_hi_dout;
if ea(6) = '1' then
next_state <= pshs_upl_state;
elsif ea(5) = '1' then
next_state <= pshs_iyl_state;
elsif ea(4) = '1' then
next_state <= pshs_ixl_state;
elsif ea(3) = '1' then
next_state <= pshs_dp_state;
elsif ea(2) = '1' then
next_state <= pshs_accb_state;
elsif ea(1) = '1' then
next_state <= pshs_acca_state;
elsif ea(0) = '1' then
next_state <= pshs_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pshs_upl_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write pc low
addr_ctrl <= pushs_ad;
dout_ctrl <= up_lo_dout;
next_state <= pshs_uph_state;
when pshs_uph_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(5 downto 0) = "000000" then
sp_ctrl <= latch_sp;
else
sp_ctrl <= load_sp;
end if;
-- write pc hi
addr_ctrl <= pushs_ad;
dout_ctrl <= up_hi_dout;
if ea(5) = '1' then
next_state <= pshs_iyl_state;
elsif ea(4) = '1' then
next_state <= pshs_ixl_state;
elsif ea(3) = '1' then
next_state <= pshs_dp_state;
elsif ea(2) = '1' then
next_state <= pshs_accb_state;
elsif ea(1) = '1' then
next_state <= pshs_acca_state;
elsif ea(0) = '1' then
next_state <= pshs_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pshs_iyl_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write iy low
addr_ctrl <= pushs_ad;
dout_ctrl <= iy_lo_dout;
next_state <= pshs_iyh_state;
when pshs_iyh_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(4 downto 0) = "00000" then
sp_ctrl <= latch_sp;
else
sp_ctrl <= load_sp;
end if;
-- write iy hi
addr_ctrl <= pushs_ad;
dout_ctrl <= iy_hi_dout;
if ea(4) = '1' then
next_state <= pshs_ixl_state;
elsif ea(3) = '1' then
next_state <= pshs_dp_state;
elsif ea(2) = '1' then
next_state <= pshs_accb_state;
elsif ea(1) = '1' then
next_state <= pshs_acca_state;
elsif ea(0) = '1' then
next_state <= pshs_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pshs_ixl_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write ix low
addr_ctrl <= pushs_ad;
dout_ctrl <= ix_lo_dout;
next_state <= pshs_ixh_state;
when pshs_ixh_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(3 downto 0) = "0000" then
sp_ctrl <= latch_sp;
else
sp_ctrl <= load_sp;
end if;
-- write ix hi
addr_ctrl <= pushs_ad;
dout_ctrl <= ix_hi_dout;
if ea(3) = '1' then
next_state <= pshs_dp_state;
elsif ea(2) = '1' then
next_state <= pshs_accb_state;
elsif ea(1) = '1' then
next_state <= pshs_acca_state;
elsif ea(0) = '1' then
next_state <= pshs_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pshs_dp_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(2 downto 0) = "000" then
sp_ctrl <= latch_sp;
else
sp_ctrl <= load_sp;
end if;
-- write dp
addr_ctrl <= pushs_ad;
dout_ctrl <= dp_dout;
if ea(2) = '1' then
next_state <= pshs_accb_state;
elsif ea(1) = '1' then
next_state <= pshs_acca_state;
elsif ea(0) = '1' then
next_state <= pshs_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pshs_accb_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(1 downto 0) = "00" then
sp_ctrl <= latch_sp;
else
sp_ctrl <= load_sp;
end if;
-- write accb
addr_ctrl <= pushs_ad;
dout_ctrl <= accb_dout;
if ea(1) = '1' then
next_state <= pshs_acca_state;
elsif ea(0) = '1' then
next_state <= pshs_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pshs_acca_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(0) = '1' then
sp_ctrl <= load_sp;
else
sp_ctrl <= latch_sp;
end if;
-- write acca
addr_ctrl <= pushs_ad;
dout_ctrl <= acca_dout;
if ea(0) = '1' then
next_state <= pshs_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pshs_cc_state =>
-- idle sp
-- write cc
addr_ctrl <= pushs_ad;
dout_ctrl <= cc_dout;
lic <= '1';
next_state <= fetch_state;
--
-- enter here on PULS
-- ea hold register mask
--
when puls_state =>
if ea(0) = '1' then
next_state <= puls_cc_state;
elsif ea(1) = '1' then
next_state <= puls_acca_state;
elsif ea(2) = '1' then
next_state <= puls_accb_state;
elsif ea(3) = '1' then
next_state <= puls_dp_state;
elsif ea(4) = '1' then
next_state <= puls_ixh_state;
elsif ea(5) = '1' then
next_state <= puls_iyh_state;
elsif ea(6) = '1' then
next_state <= puls_uph_state;
elsif ea(7) = '1' then
next_state <= puls_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when puls_cc_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read cc
cc_ctrl <= pull_cc;
addr_ctrl <= pulls_ad;
if ea(1) = '1' then
next_state <= puls_acca_state;
elsif ea(2) = '1' then
next_state <= puls_accb_state;
elsif ea(3) = '1' then
next_state <= puls_dp_state;
elsif ea(4) = '1' then
next_state <= puls_ixh_state;
elsif ea(5) = '1' then
next_state <= puls_iyh_state;
elsif ea(6) = '1' then
next_state <= puls_uph_state;
elsif ea(7) = '1' then
next_state <= puls_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when puls_acca_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read acca
acca_ctrl <= pull_acca;
addr_ctrl <= pulls_ad;
if ea(2) = '1' then
next_state <= puls_accb_state;
elsif ea(3) = '1' then
next_state <= puls_dp_state;
elsif ea(4) = '1' then
next_state <= puls_ixh_state;
elsif ea(5) = '1' then
next_state <= puls_iyh_state;
elsif ea(6) = '1' then
next_state <= puls_uph_state;
elsif ea(7) = '1' then
next_state <= puls_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when puls_accb_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read accb
accb_ctrl <= pull_accb;
addr_ctrl <= pulls_ad;
if ea(3) = '1' then
next_state <= puls_dp_state;
elsif ea(4) = '1' then
next_state <= puls_ixh_state;
elsif ea(5) = '1' then
next_state <= puls_iyh_state;
elsif ea(6) = '1' then
next_state <= puls_uph_state;
elsif ea(7) = '1' then
next_state <= puls_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when puls_dp_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read dp
dp_ctrl <= pull_dp;
addr_ctrl <= pulls_ad;
if ea(4) = '1' then
next_state <= puls_ixh_state;
elsif ea(5) = '1' then
next_state <= puls_iyh_state;
elsif ea(6) = '1' then
next_state <= puls_uph_state;
elsif ea(7) = '1' then
next_state <= puls_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when puls_ixh_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- pull ix hi
ix_ctrl <= pull_hi_ix;
addr_ctrl <= pulls_ad;
next_state <= puls_ixl_state;
when puls_ixl_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read ix low
ix_ctrl <= pull_lo_ix;
addr_ctrl <= pulls_ad;
if ea(5) = '1' then
next_state <= puls_iyh_state;
elsif ea(6) = '1' then
next_state <= puls_uph_state;
elsif ea(7) = '1' then
next_state <= puls_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when puls_iyh_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- pull iy hi
iy_ctrl <= pull_hi_iy;
addr_ctrl <= pulls_ad;
next_state <= puls_iyl_state;
when puls_iyl_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read iy low
iy_ctrl <= pull_lo_iy;
addr_ctrl <= pulls_ad;
if ea(6) = '1' then
next_state <= puls_uph_state;
elsif ea(7) = '1' then
next_state <= puls_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when puls_uph_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- pull up hi
up_ctrl <= pull_hi_up;
addr_ctrl <= pulls_ad;
next_state <= puls_upl_state;
when puls_upl_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read up low
up_ctrl <= pull_lo_up;
addr_ctrl <= pulls_ad;
if ea(7) = '1' then
next_state <= puls_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when puls_pch_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- pull pc hi
pc_ctrl <= pull_hi_pc;
addr_ctrl <= pulls_ad;
next_state <= puls_pcl_state;
when puls_pcl_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read pc low
pc_ctrl <= pull_lo_pc;
addr_ctrl <= pulls_ad;
lic <= '1';
next_state <= fetch_state;
--
-- Enter here on pshu
-- ea holds post byte
--
when pshu_state =>
-- decrement up if any registers to be pushed
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(7 downto 0) = "00000000" then
up_ctrl <= latch_up;
else
up_ctrl <= load_up;
end if;
-- write idle bus
if ea(7) = '1' then
next_state <= pshu_pcl_state;
elsif ea(6) = '1' then
next_state <= pshu_spl_state;
elsif ea(5) = '1' then
next_state <= pshu_iyl_state;
elsif ea(4) = '1' then
next_state <= pshu_ixl_state;
elsif ea(3) = '1' then
next_state <= pshu_dp_state;
elsif ea(2) = '1' then
next_state <= pshu_accb_state;
elsif ea(1) = '1' then
next_state <= pshu_acca_state;
elsif ea(0) = '1' then
next_state <= pshu_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
--
-- push PC onto U stack
--
when pshu_pcl_state =>
-- decrement up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
up_ctrl <= load_up;
-- write pc low
addr_ctrl <= pushu_ad;
dout_ctrl <= pc_lo_dout;
next_state <= pshu_pch_state;
when pshu_pch_state =>
-- decrement up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(6 downto 0) = "0000000" then
up_ctrl <= latch_up;
else
up_ctrl <= load_up;
end if;
-- write pc hi
addr_ctrl <= pushu_ad;
dout_ctrl <= pc_hi_dout;
if ea(6) = '1' then
next_state <= pshu_spl_state;
elsif ea(5) = '1' then
next_state <= pshu_iyl_state;
elsif ea(4) = '1' then
next_state <= pshu_ixl_state;
elsif ea(3) = '1' then
next_state <= pshu_dp_state;
elsif ea(2) = '1' then
next_state <= pshu_accb_state;
elsif ea(1) = '1' then
next_state <= pshu_acca_state;
elsif ea(0) = '1' then
next_state <= pshu_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pshu_spl_state =>
-- decrement up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
up_ctrl <= load_up;
-- write sp low
addr_ctrl <= pushu_ad;
dout_ctrl <= sp_lo_dout;
next_state <= pshu_sph_state;
when pshu_sph_state =>
-- decrement up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(5 downto 0) = "000000" then
up_ctrl <= latch_up;
else
up_ctrl <= load_up;
end if;
-- write sp hi
addr_ctrl <= pushu_ad;
dout_ctrl <= sp_hi_dout;
if ea(5) = '1' then
next_state <= pshu_iyl_state;
elsif ea(4) = '1' then
next_state <= pshu_ixl_state;
elsif ea(3) = '1' then
next_state <= pshu_dp_state;
elsif ea(2) = '1' then
next_state <= pshu_accb_state;
elsif ea(1) = '1' then
next_state <= pshu_acca_state;
elsif ea(0) = '1' then
next_state <= pshu_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pshu_iyl_state =>
-- decrement up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
up_ctrl <= load_up;
-- write iy low
addr_ctrl <= pushu_ad;
dout_ctrl <= iy_lo_dout;
next_state <= pshu_iyh_state;
when pshu_iyh_state =>
-- decrement up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(4 downto 0) = "00000" then
up_ctrl <= latch_up;
else
up_ctrl <= load_up;
end if;
-- write iy hi
addr_ctrl <= pushu_ad;
dout_ctrl <= iy_hi_dout;
if ea(4) = '1' then
next_state <= pshu_ixl_state;
elsif ea(3) = '1' then
next_state <= pshu_dp_state;
elsif ea(2) = '1' then
next_state <= pshu_accb_state;
elsif ea(1) = '1' then
next_state <= pshu_acca_state;
elsif ea(0) = '1' then
next_state <= pshu_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pshu_ixl_state =>
-- decrement up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
up_ctrl <= load_up;
-- write ix low
addr_ctrl <= pushu_ad;
dout_ctrl <= ix_lo_dout;
next_state <= pshu_ixh_state;
when pshu_ixh_state =>
-- decrement up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(3 downto 0) = "0000" then
up_ctrl <= latch_up;
else
up_ctrl <= load_up;
end if;
-- write ix hi
addr_ctrl <= pushu_ad;
dout_ctrl <= ix_hi_dout;
if ea(3) = '1' then
next_state <= pshu_dp_state;
elsif ea(2) = '1' then
next_state <= pshu_accb_state;
elsif ea(1) = '1' then
next_state <= pshu_acca_state;
elsif ea(0) = '1' then
next_state <= pshu_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pshu_dp_state =>
-- decrement up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(2 downto 0) = "000" then
up_ctrl <= latch_up;
else
up_ctrl <= load_up;
end if;
-- write dp
addr_ctrl <= pushu_ad;
dout_ctrl <= dp_dout;
if ea(2) = '1' then
next_state <= pshu_accb_state;
elsif ea(1) = '1' then
next_state <= pshu_acca_state;
elsif ea(0) = '1' then
next_state <= pshu_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pshu_accb_state =>
-- decrement up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(1 downto 0) = "00" then
up_ctrl <= latch_up;
else
up_ctrl <= load_up;
end if;
-- write accb
addr_ctrl <= pushu_ad;
dout_ctrl <= accb_dout;
if ea(1) = '1' then
next_state <= pshu_acca_state;
elsif ea(0) = '1' then
next_state <= pshu_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pshu_acca_state =>
-- decrement up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(0) = '0' then
up_ctrl <= latch_up;
else
up_ctrl <= load_up;
end if;
-- write acca
addr_ctrl <= pushu_ad;
dout_ctrl <= acca_dout;
if ea(0) = '1' then
next_state <= pshu_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pshu_cc_state =>
-- idle up
-- write cc
addr_ctrl <= pushu_ad;
dout_ctrl <= cc_dout;
lic <= '1';
next_state <= fetch_state;
--
-- enter here on PULU
-- ea hold register mask
--
when pulu_state =>
-- idle UP
-- idle bus
if ea(0) = '1' then
next_state <= pulu_cc_state;
elsif ea(1) = '1' then
next_state <= pulu_acca_state;
elsif ea(2) = '1' then
next_state <= pulu_accb_state;
elsif ea(3) = '1' then
next_state <= pulu_dp_state;
elsif ea(4) = '1' then
next_state <= pulu_ixh_state;
elsif ea(5) = '1' then
next_state <= pulu_iyh_state;
elsif ea(6) = '1' then
next_state <= pulu_sph_state;
elsif ea(7) = '1' then
next_state <= pulu_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pulu_cc_state =>
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read cc
cc_ctrl <= pull_cc;
addr_ctrl <= pullu_ad;
if ea(1) = '1' then
next_state <= pulu_acca_state;
elsif ea(2) = '1' then
next_state <= pulu_accb_state;
elsif ea(3) = '1' then
next_state <= pulu_dp_state;
elsif ea(4) = '1' then
next_state <= pulu_ixh_state;
elsif ea(5) = '1' then
next_state <= pulu_iyh_state;
elsif ea(6) = '1' then
next_state <= pulu_sph_state;
elsif ea(7) = '1' then
next_state <= pulu_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pulu_acca_state =>
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read acca
acca_ctrl <= pull_acca;
addr_ctrl <= pullu_ad;
if ea(2) = '1' then
next_state <= pulu_accb_state;
elsif ea(3) = '1' then
next_state <= pulu_dp_state;
elsif ea(4) = '1' then
next_state <= pulu_ixh_state;
elsif ea(5) = '1' then
next_state <= pulu_iyh_state;
elsif ea(6) = '1' then
next_state <= pulu_sph_state;
elsif ea(7) = '1' then
next_state <= pulu_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pulu_accb_state =>
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read accb
accb_ctrl <= pull_accb;
addr_ctrl <= pullu_ad;
if ea(3) = '1' then
next_state <= pulu_dp_state;
elsif ea(4) = '1' then
next_state <= pulu_ixh_state;
elsif ea(5) = '1' then
next_state <= pulu_iyh_state;
elsif ea(6) = '1' then
next_state <= pulu_sph_state;
elsif ea(7) = '1' then
next_state <= pulu_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pulu_dp_state =>
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read dp
dp_ctrl <= pull_dp;
addr_ctrl <= pullu_ad;
if ea(4) = '1' then
next_state <= pulu_ixh_state;
elsif ea(5) = '1' then
next_state <= pulu_iyh_state;
elsif ea(6) = '1' then
next_state <= pulu_sph_state;
elsif ea(7) = '1' then
next_state <= pulu_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pulu_ixh_state =>
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read ix hi
ix_ctrl <= pull_hi_ix;
addr_ctrl <= pullu_ad;
next_state <= pulu_ixl_state;
when pulu_ixl_state =>
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read ix low
ix_ctrl <= pull_lo_ix;
addr_ctrl <= pullu_ad;
if ea(5) = '1' then
next_state <= pulu_iyh_state;
elsif ea(6) = '1' then
next_state <= pulu_sph_state;
elsif ea(7) = '1' then
next_state <= pulu_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pulu_iyh_state =>
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read iy hi
iy_ctrl <= pull_hi_iy;
addr_ctrl <= pullu_ad;
next_state <= pulu_iyl_state;
when pulu_iyl_state =>
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read iy low
iy_ctrl <= pull_lo_iy;
addr_ctrl <= pullu_ad;
if ea(6) = '1' then
next_state <= pulu_sph_state;
elsif ea(7) = '1' then
next_state <= pulu_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pulu_sph_state =>
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read sp hi
sp_ctrl <= pull_hi_sp;
addr_ctrl <= pullu_ad;
next_state <= pulu_spl_state;
when pulu_spl_state =>
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read sp low
sp_ctrl <= pull_lo_sp;
addr_ctrl <= pullu_ad;
if ea(7) = '1' then
next_state <= pulu_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pulu_pch_state =>
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- pull pc hi
pc_ctrl <= pull_hi_pc;
addr_ctrl <= pullu_ad;
next_state <= pulu_pcl_state;
when pulu_pcl_state =>
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read pc low
pc_ctrl <= pull_lo_pc;
addr_ctrl <= pullu_ad;
lic <= '1';
next_state <= fetch_state;
--
-- pop the Condition codes
--
when rti_cc_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read cc
cc_ctrl <= pull_cc;
addr_ctrl <= pulls_ad;
next_state <= rti_entire_state;
--
-- Added RTI cycle 11th July 2006 John Kent.
-- test the "Entire" Flag
-- that has just been popped off the stack
--
when rti_entire_state =>
--
-- The Entire flag must be recovered from the stack
-- before testing.
--
if cc(EBIT) = '1' then
next_state <= rti_acca_state;
else
next_state <= rti_pch_state;
end if;
when rti_acca_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read acca
acca_ctrl <= pull_acca;
addr_ctrl <= pulls_ad;
next_state <= rti_accb_state;
when rti_accb_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read accb
accb_ctrl <= pull_accb;
addr_ctrl <= pulls_ad;
next_state <= rti_dp_state;
when rti_dp_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read dp
dp_ctrl <= pull_dp;
addr_ctrl <= pulls_ad;
next_state <= rti_ixh_state;
when rti_ixh_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read ix hi
ix_ctrl <= pull_hi_ix;
addr_ctrl <= pulls_ad;
next_state <= rti_ixl_state;
when rti_ixl_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read ix low
ix_ctrl <= pull_lo_ix;
addr_ctrl <= pulls_ad;
next_state <= rti_iyh_state;
when rti_iyh_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read iy hi
iy_ctrl <= pull_hi_iy;
addr_ctrl <= pulls_ad;
next_state <= rti_iyl_state;
when rti_iyl_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read iy low
iy_ctrl <= pull_lo_iy;
addr_ctrl <= pulls_ad;
next_state <= rti_uph_state;
when rti_uph_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read up hi
up_ctrl <= pull_hi_up;
addr_ctrl <= pulls_ad;
next_state <= rti_upl_state;
when rti_upl_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read up low
up_ctrl <= pull_lo_up;
addr_ctrl <= pulls_ad;
next_state <= rti_pch_state;
when rti_pch_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- pull pc hi
pc_ctrl <= pull_hi_pc;
addr_ctrl <= pulls_ad;
next_state <= rti_pcl_state;
when rti_pcl_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- pull pc low
pc_ctrl <= pull_lo_pc;
addr_ctrl <= pulls_ad;
lic <= '1';
next_state <= fetch_state;
--
-- here on NMI interrupt
-- Complete execute cycle of the last instruction.
-- If it was a dual operand instruction
--
when int_nmi_state =>
next_state <= int_nmi1_state;
-- Idle bus cycle
when int_nmi1_state =>
-- pre decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
iv_ctrl <= nmi_iv;
st_ctrl <= push_st;
return_state <= int_nmimask_state;
next_state <= int_entire_state;
--
-- here on IRQ interrupt
-- Complete execute cycle of the last instruction.
-- If it was a dual operand instruction
--
when int_irq_state =>
next_state <= int_irq1_state;
-- pre decrement the sp
-- Idle bus cycle
when int_irq1_state =>
-- pre decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
iv_ctrl <= irq_iv;
st_ctrl <= push_st;
return_state <= int_irqmask_state;
next_state <= int_entire_state;
--
-- here on FIRQ interrupt
-- Complete execution cycle of the last instruction
-- if it was a dual operand instruction
--
when int_firq_state =>
next_state <= int_firq1_state;
-- Idle bus cycle
when int_firq1_state =>
-- pre decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
iv_ctrl <= firq_iv;
st_ctrl <= push_st;
return_state <= int_firqmask_state;
next_state <= int_fast_state;
--
-- CWAI entry point
-- stack pointer already pre-decremented
-- mask condition codes
--
when cwai_state =>
-- AND CC with md
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_andcc;
cc_ctrl <= load_cc;
st_ctrl <= push_st;
return_state <= int_cwai_state;
next_state <= int_entire_state;
--
-- wait here for an interrupt
--
when int_cwai_state =>
if (nmi_req = '1') then
iv_ctrl <= nmi_iv;
next_state <= int_nmimask_state;
--
-- FIRQ & IRQ are level sensitive
--
elsif (firq = '1') and (cc(FBIT) = '0') then
iv_ctrl <= firq_iv;
next_state <= int_firqmask_state;
elsif (irq = '1') and (cc(IBIT) = '0') then
iv_ctrl <= irq_iv;
next_state <= int_irqmask_state;
else
next_state <= int_cwai_state;
end if;
--
-- State to mask I Flag and F Flag (NMI)
--
when int_nmimask_state =>
alu_ctrl <= alu_seif;
cc_ctrl <= load_cc;
next_state <= vect_hi_state;
--
-- State to mask I Flag and F Flag (FIRQ)
--
when int_firqmask_state =>
alu_ctrl <= alu_seif;
cc_ctrl <= load_cc;
next_state <= vect_hi_state;
--
-- State to mask I Flag and F Flag (SWI)
--
when int_swimask_state =>
alu_ctrl <= alu_seif;
cc_ctrl <= load_cc;
next_state <= vect_hi_state;
--
-- State to mask I Flag only (IRQ)
--
when int_irqmask_state =>
alu_ctrl <= alu_sei;
cc_ctrl <= load_cc;
next_state <= vect_hi_state;
--
-- set Entire Flag on SWI, SWI2, SWI3 and CWAI, IRQ and NMI
-- before stacking all registers
--
when int_entire_state =>
-- set entire flag
alu_ctrl <= alu_see;
cc_ctrl <= load_cc;
next_state <= int_pcl_state;
--
-- clear Entire Flag on FIRQ
-- before stacking all registers
--
when int_fast_state =>
-- clear entire flag
alu_ctrl <= alu_cle;
cc_ctrl <= load_cc;
next_state <= int_pcl_state;
when int_pcl_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write pc low
addr_ctrl <= pushs_ad;
dout_ctrl <= pc_lo_dout;
next_state <= int_pch_state;
when int_pch_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write pc hi
addr_ctrl <= pushs_ad;
dout_ctrl <= pc_hi_dout;
if cc(EBIT) = '1' then
next_state <= int_upl_state;
else
next_state <= int_cc_state;
end if;
when int_upl_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write up low
addr_ctrl <= pushs_ad;
dout_ctrl <= up_lo_dout;
next_state <= int_uph_state;
when int_uph_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write ix hi
addr_ctrl <= pushs_ad;
dout_ctrl <= up_hi_dout;
next_state <= int_iyl_state;
when int_iyl_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write ix low
addr_ctrl <= pushs_ad;
dout_ctrl <= iy_lo_dout;
next_state <= int_iyh_state;
when int_iyh_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write ix hi
addr_ctrl <= pushs_ad;
dout_ctrl <= iy_hi_dout;
next_state <= int_ixl_state;
when int_ixl_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write ix low
addr_ctrl <= pushs_ad;
dout_ctrl <= ix_lo_dout;
next_state <= int_ixh_state;
when int_ixh_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write ix hi
addr_ctrl <= pushs_ad;
dout_ctrl <= ix_hi_dout;
next_state <= int_dp_state;
when int_dp_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write accb
addr_ctrl <= pushs_ad;
dout_ctrl <= dp_dout;
next_state <= int_accb_state;
when int_accb_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write accb
addr_ctrl <= pushs_ad;
dout_ctrl <= accb_dout;
next_state <= int_acca_state;
when int_acca_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write acca
addr_ctrl <= pushs_ad;
dout_ctrl <= acca_dout;
next_state <= int_cc_state;
when int_cc_state =>
-- write cc
addr_ctrl <= pushs_ad;
dout_ctrl <= cc_dout;
next_state <= saved_state;
--
-- According to the 6809 programming manual:
-- If an interrupt is received and is masked
-- or lasts for less than three cycles, the PC
-- will advance to the next instruction.
-- If an interrupt is unmasked and lasts
-- for more than three cycles, an interrupt
-- will be generated.
-- Note that I don't wait 3 clock cycles.
-- John Kent 11th July 2006
--
when sync_state =>
lic <= '1';
ba <= '1';
next_state <= sync_state;
when halt_state =>
--
-- 2011-10-30 John Kent
-- ba & bs should be high
ba <= '1';
bs <= '1';
if halt = '1' then
next_state <= halt_state;
else
next_state <= fetch_state;
end if;
end case;
--
-- Ver 1.23 2011-10-30 John Kent
-- First instruction cycle might be
-- fetch_state
-- halt_state
-- int_nmirq_state
-- int_firq_state
--
if fic = '1' then
--
case op_code(7 downto 6) is
when "10" => -- acca
case op_code(3 downto 0) is
when "0000" => -- suba
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
when "0001" => -- cmpa
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
when "0010" => -- sbca
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sbc;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
when "0011" =>
case pre_code is
when "00010000" => -- page 2 -- cmpd
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= load_cc;
when "00010001" => -- page 3 -- cmpu
left_ctrl <= up_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= load_cc;
when others => -- page 1 -- subd
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
end case;
when "0100" => -- anda
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_and;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
when "0101" => -- bita
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_and;
cc_ctrl <= load_cc;
when "0110" => -- ldaa
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld8;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
when "0111" => -- staa
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st8;
cc_ctrl <= load_cc;
when "1000" => -- eora
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_eor;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
when "1001" => -- adca
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_adc;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
when "1010" => -- oraa
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ora;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
when "1011" => -- adda
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add8;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
when "1100" =>
case pre_code is
when "00010000" => -- page 2 -- cmpy
left_ctrl <= iy_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= load_cc;
when "00010001" => -- page 3 -- cmps
left_ctrl <= sp_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= load_cc;
when others => -- page 1 -- cmpx
left_ctrl <= ix_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= load_cc;
end case;
when "1101" => -- bsr / jsr
null;
when "1110" => -- ldx
case pre_code is
when "00010000" => -- page 2 -- ldy
left_ctrl <= iy_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
cc_ctrl <= load_cc;
iy_ctrl <= load_iy;
when others => -- page 1 -- ldx
left_ctrl <= ix_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
cc_ctrl <= load_cc;
ix_ctrl <= load_ix;
end case;
when "1111" => -- stx
case pre_code is
when "00010000" => -- page 2 -- sty
left_ctrl <= iy_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st16;
cc_ctrl <= load_cc;
when others => -- page 1 -- stx
left_ctrl <= ix_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st16;
cc_ctrl <= load_cc;
end case;
when others =>
null;
end case;
when "11" => -- accb dual op
case op_code(3 downto 0) is
when "0000" => -- subb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
accb_ctrl <= load_accb;
when "0001" => -- cmpb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
when "0010" => -- sbcb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sbc;
cc_ctrl <= load_cc;
accb_ctrl <= load_accb;
when "0011" => -- addd
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add16;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
when "0100" => -- andb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_and;
cc_ctrl <= load_cc;
accb_ctrl <= load_accb;
when "0101" => -- bitb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_and;
cc_ctrl <= load_cc;
when "0110" => -- ldab
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld8;
cc_ctrl <= load_cc;
accb_ctrl <= load_accb;
when "0111" => -- stab
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st8;
cc_ctrl <= load_cc;
when "1000" => -- eorb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_eor;
cc_ctrl <= load_cc;
accb_ctrl <= load_accb;
when "1001" => -- adcb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_adc;
cc_ctrl <= load_cc;
accb_ctrl <= load_accb;
when "1010" => -- orab
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ora;
cc_ctrl <= load_cc;
accb_ctrl <= load_accb;
when "1011" => -- addb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add8;
cc_ctrl <= load_cc;
accb_ctrl <= load_accb;
when "1100" => -- ldd
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
when "1101" => -- std
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st16;
cc_ctrl <= load_cc;
when "1110" => -- ldu
case pre_code is
when "00010000" => -- page 2 -- lds
left_ctrl <= sp_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
cc_ctrl <= load_cc;
sp_ctrl <= load_sp;
when others => -- page 1 -- ldu
left_ctrl <= up_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
cc_ctrl <= load_cc;
up_ctrl <= load_up;
end case;
when "1111" =>
case pre_code is
when "00010000" => -- page 2 -- sts
left_ctrl <= sp_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st16;
cc_ctrl <= load_cc;
when others => -- page 1 -- stu
left_ctrl <= up_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st16;
cc_ctrl <= load_cc;
end case;
when others =>
null;
end case;
when others =>
null;
end case;
end if; -- first instruction cycle (fic)
lic_out <= lic;
end process;
end rtl;
| gpl-3.0 | e53f6a5df6100154c278516887e15139 | 0.456292 | 3.635981 | false | false | false | false |
ggaray/nicsim-vhd | memsub.vhd | 1 | 4,905 | -- NICSim-vhd: A VHDL-based modelling and simulation of NIC's buffers
-- Copyright (C) 2013 Godofredo R. Garay <godofredo.garay (-at-) gmail.com>
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
use std.textio.all;
library ieee;
use ieee.math_real.all; -- for uniform
use ieee.std_logic_1164.all;
entity memsub is
port (
irdy : in bit;
trdy : out bit := '1';
frame : inout std_logic := 'Z';
AD : in bit;
target_latency_cycles_counter_out : out integer := 0; -- Always equals to 1 cycle
pciclk : in bit
);
end memsub;
architecture V1 of memsub is
--------------- Variables Declarations ---------------
signal trdy_value : bit := '1';
shared variable random_cycles_count : integer := 0;
shared variable target_latency_cycles_count : integer := 0;
-- Variables needed for Memsub FSM
type memsub_state is (waiting_memory_write_transaction_start, target_ready);
shared variable state : memsub_state := waiting_memory_write_transaction_start; --Initial state = idle
shared variable next_state : memsub_state := waiting_memory_write_transaction_start;
begin
trdy <= trdy_value;
memsub_fsm: process
begin
wait until pciclk'event and pciclk = '1';
case state is
when waiting_memory_write_transaction_start =>
if frame = '1'
or (frame = '0'
and AD = '1')
then trdy_value <= '1';
next_state := waiting_memory_write_transaction_start;
elsif frame = '0'
and AD = '0'
then trdy_value <= '0';
assert false
report "memsub_fsm: target_ready"
severity note;
next_state := target_ready;
end if;
when target_ready =>
if frame = '0'
then trdy_value <= '0';
next_state := target_ready;
elsif frame = '1'
then trdy_value <= '1';
assert false
report "memsub_fsm: waiting_memory_write_transaction_start"
severity note;
next_state := waiting_memory_write_transaction_start;
end if;
end case;
state := next_state;
end process memsub_fsm;
target_latency_cycles_counter_fsm: process
-- Variables needed for target_latency_cycles_counter_fsm
type target_latency_cycles_counter_fsm_state is
(idle, incrementing_target_latency_cycles_count, waiting_transaction_end);
variable state : target_latency_cycles_counter_fsm_state := idle;
variable next_state : target_latency_cycles_counter_fsm_state := idle;
begin
wait until pciclk'event and pciclk = '1';
case state is
when idle =>
target_latency_cycles_count := 0;
if frame = '1'
then next_state := idle;
elsif frame = '0'
and AD = '0'
then target_latency_cycles_count := target_latency_cycles_count + 1;
assert false
report "target_latency_cycles_counter_fsm: incrementing_target_latency_cycles_count"
severity note;
next_state := incrementing_target_latency_cycles_count;
end if;
when incrementing_target_latency_cycles_count =>
if frame = '0'
and AD = '0'
and trdy_value = '1'
then target_latency_cycles_count := target_latency_cycles_count + 1;
next_state := incrementing_target_latency_cycles_count;
elsif frame = '0'
and AD = '0'
and trdy_value = '0'
then target_latency_cycles_count := 0;
assert false
report "target_latency_cycles_counter_fsm: waiting_transaction_end"
severity note;
next_state := waiting_transaction_end;
end if;
when waiting_transaction_end =>
if frame = '0'
and AD = '0'
then next_state := waiting_transaction_end;
elsif frame = '1'
and AD = '1'
then next_state := idle;
end if;
end case;
state := next_state;
end process target_latency_cycles_counter_fsm;
acquisition_latency_cycles_counter_out_driver: process
begin
wait until pciclk'event and pciclk = '0';
target_latency_cycles_counter_out <= target_latency_cycles_count;
end process acquisition_latency_cycles_counter_out_driver;
-- output_signals_driver: process
-- begin
-- wait until pciclk'event and pciclk = '1';
-- trdy <= trdy_value;
-- end process output_signals_driver;
end V1;
| gpl-3.0 | 3dca8c4a8e241cc8215b32a2b938ed27 | 0.643017 | 3.248344 | false | false | false | false |
kdgwill/VHDL_Framer_Example | VHDL_Framer_Example/Example2/Divider.vhd | 1 | 4,686 | -- megafunction wizard: %LPM_DIVIDE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_DIVIDE
-- ============================================================
-- File Name: Divider.vhd
-- Megafunction Name(s):
-- LPM_DIVIDE
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 173 11/01/2011 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY Divider IS
PORT
(
denom : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
numer : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
quotient : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
remain : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END Divider;
ARCHITECTURE SYN OF divider IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT lpm_divide
GENERIC (
lpm_drepresentation : STRING;
lpm_hint : STRING;
lpm_nrepresentation : STRING;
lpm_type : STRING;
lpm_widthd : NATURAL;
lpm_widthn : NATURAL
);
PORT (
denom : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
numer : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
quotient : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
remain : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
quotient <= sub_wire0(31 DOWNTO 0);
remain <= sub_wire1(31 DOWNTO 0);
LPM_DIVIDE_component : LPM_DIVIDE
GENERIC MAP (
lpm_drepresentation => "UNSIGNED",
lpm_hint => "LPM_REMAINDERPOSITIVE=TRUE",
lpm_nrepresentation => "UNSIGNED",
lpm_type => "LPM_DIVIDE",
lpm_widthd => 32,
lpm_widthn => 32
)
PORT MAP (
denom => denom,
numer => numer,
quotient => sub_wire0,
remain => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
-- Retrieval info: PRIVATE: PRIVATE_LPM_REMAINDERPOSITIVE STRING "TRUE"
-- Retrieval info: PRIVATE: PRIVATE_MAXIMIZE_SPEED NUMERIC "-1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USING_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: VERSION_NUMBER NUMERIC "2"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_DREPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_HINT STRING "LPM_REMAINDERPOSITIVE=TRUE"
-- Retrieval info: CONSTANT: LPM_NREPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_DIVIDE"
-- Retrieval info: CONSTANT: LPM_WIDTHD NUMERIC "32"
-- Retrieval info: CONSTANT: LPM_WIDTHN NUMERIC "32"
-- Retrieval info: USED_PORT: denom 0 0 32 0 INPUT NODEFVAL "denom[31..0]"
-- Retrieval info: USED_PORT: numer 0 0 32 0 INPUT NODEFVAL "numer[31..0]"
-- Retrieval info: USED_PORT: quotient 0 0 32 0 OUTPUT NODEFVAL "quotient[31..0]"
-- Retrieval info: USED_PORT: remain 0 0 32 0 OUTPUT NODEFVAL "remain[31..0]"
-- Retrieval info: CONNECT: @denom 0 0 32 0 denom 0 0 32 0
-- Retrieval info: CONNECT: @numer 0 0 32 0 numer 0 0 32 0
-- Retrieval info: CONNECT: quotient 0 0 32 0 @quotient 0 0 32 0
-- Retrieval info: CONNECT: remain 0 0 32 0 @remain 0 0 32 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL Divider.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Divider.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Divider.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Divider.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Divider_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
| gpl-3.0 | c3fed812b8f16e7512bf008afcdf4364 | 0.639778 | 3.666667 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/maps/syncram.vhd | 1 | 12,208 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: syncram
-- File: syncram.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: syncronous 1-port ram with tech selection
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config.all;
use grlib.config_types.all;
use grlib.stdlib.all;
use work.gencomp.all;
use work.allmem.all;
entity syncram is
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
testen : integer := 0; custombits: integer := 1);
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic;
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0) := testin_none
);
end;
architecture rtl of syncram is
constant nctrl : integer := abits + (TESTIN_WIDTH-2) + 2;
signal rena, wena : std_logic;
signal dataoutx, databp, testdata : std_logic_vector((dbits -1) downto 0);
constant SCANTESTBP : boolean := (testen = 1) and syncram_add_scan_bypass(tech)=1;
signal xenable, xwrite: std_ulogic;
signal gnd : std_ulogic;
signal custominx,customoutx: std_logic_vector(syncram_customif_maxwidth downto 0);
signal customclkx: std_ulogic;
begin
gnd <= '0';
xenable <= enable and not testin(TESTIN_WIDTH-2) when testen/=0 else enable;
xwrite <= write and not testin(TESTIN_WIDTH-2) when testen/=0 else write;
-- RAM bypass for scan
scanbp : if SCANTESTBP generate
comb : process (address, datain, enable, write, testin)
variable tmp : std_logic_vector((dbits -1) downto 0);
variable ctrlsigs : std_logic_vector((nctrl -1) downto 0);
begin
ctrlsigs := testin(TESTIN_WIDTH-3 downto 0) & write & enable & address;
tmp := datain;
for i in 0 to nctrl-1 loop
tmp(i mod dbits) := tmp(i mod dbits) xor ctrlsigs(i);
end loop;
testdata <= tmp;
end process;
reg : process (clk)
begin
if rising_edge(clk) then
databp <= testdata;
end if;
end process;
dmuxout : for i in 0 to dbits-1 generate
x0: grmux2 generic map (tech)
port map (dataoutx(i), databp(i), testin(TESTIN_WIDTH-1), dataout(i));
end generate;
end generate;
custominx <= (others => '0');
customclkx <= '0';
nocust: if syncram_has_customif(tech)=0 generate
customoutx <= (others => '0');
end generate;
noscanbp : if not SCANTESTBP generate dataout <= dataoutx; end generate;
inf : if tech = inferred generate
x0 : generic_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, write);
end generate;
xcv : if (tech = virtex) generate
x0 : virtex_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
xc2v : if (is_unisim(tech) = 1) and (tech /= virtex) generate
x0 : unisim_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
vir : if tech = memvirage generate
x0 : virage_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
atrh : if tech = atc18rha generate
x0 : atc18rha_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite,
testin(TESTIN_WIDTH-1 downto TESTIN_WIDTH-4));
end generate;
axc : if (tech = axcel) or (tech = axdsp) generate
x0 : axcel_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
proa : if tech = proasic generate
x0 : proasic_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
igl2 : if tech = igloo2 generate
x0 : igloo2_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
rt4 : if tech = rtg4 generate
x0 : rtg4_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite,
open, gnd);
end generate;
umc18 : if tech = umc generate
x0 : umc_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
rhu : if tech = rhumc generate
x0 : rhumc_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
saed : if tech = saed32 generate
x0 : saed32_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
rhs : if tech = rhs65 generate
x0 : rhs65_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, enable, write,
testin(TESTIN_WIDTH-8),testin(TESTIN_WIDTH-3),
custominx(0),customoutx(0),
testin(TESTIN_WIDTH-4),testin(TESTIN_WIDTH-5),testin(TESTIN_WIDTH-6),
customclkx,testin(TESTIN_WIDTH-7),'0',
customoutx(1), customoutx(7 downto 2));
customoutx(customoutx'high downto 8) <= (others => '0');
end generate;
dar : if tech = dare generate
x0 : dare_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
proa3 : if tech = apa3 generate
x0 : proasic3_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
proa3e : if tech = apa3e generate
x0 : proasic3e_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
proa3l : if tech = apa3l generate
x0 : proasic3l_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
fus : if tech = actfus generate
x0 : fusion_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
ihp : if tech = ihp25 generate
x0 : ihp25_syncram generic map(abits, dbits)
port map(clk, address, datain, dataoutx, xenable, xwrite);
end generate;
ihprh : if tech = ihp25rh generate
x0 : ihp25rh_syncram generic map(abits, dbits)
port map(clk, address, datain, dataoutx, xenable, xwrite);
end generate;
alt : if (tech = altera) or (tech = stratix1) or (tech = stratix2) or
(tech = stratix3) or (tech = stratix4) or (tech = cyclone3) generate
x0 : altera_syncram generic map(abits, dbits)
port map(clk, address, datain, dataoutx, xenable, xwrite);
end generate;
rht : if tech = rhlib18t generate
x0 : rh_lib18t_syncram generic map(abits, dbits)
port map(clk, address, datain, dataoutx, xenable, xwrite, testin(TESTIN_WIDTH-3 downto TESTIN_WIDTH-4));
end generate;
lat : if tech = lattice generate
x0 : ec_syncram generic map(abits, dbits)
port map(clk, address, datain, dataoutx, xenable, xwrite);
end generate;
ut025 : if tech = ut25 generate
x0 : ut025crh_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
ut09 : if tech = ut90 generate
x0 : ut90nhbd_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite, testin(TESTIN_WIDTH-3));
end generate;
ut13 : if tech = ut130 generate
x0 : ut130hbd_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
pere : if tech = peregrine generate
x0 : peregrine_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
arti : if tech = memartisan generate
x0 : artisan_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
cust1 : if tech = custom1 generate
x0 : custom1_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
ecl : if tech = eclipse generate
rena <= xenable and not write;
wena <= xenable and write;
x0 : eclipse_syncram_2p generic map(abits, dbits)
port map(clk, rena, address, dataoutx, clk, address,
datain, wena);
end generate;
virage90 : if tech = memvirage90 generate
x0 : virage90_syncram generic map(abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
nex : if tech = easic90 generate
x0 : nextreme_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
smic : if tech = smic013 generate
x0 : smic13_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
tm65gplu : if tech = tm65gplus generate
x0 : tm65gplus_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
cmos9sfx : if tech = cmos9sf generate
x0 : cmos9sf_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
n2x : if tech = easic45 generate
x0 : n2x_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
rh13t : if tech = rhlib13t generate
x0 : rh_lib13t_syncram generic map(abits, dbits)
port map(clk, address, datain, dataoutx, xenable, xwrite, testin(TESTIN_WIDTH-3 downto TESTIN_WIDTH-4));
end generate;
-- pragma translate_off
noram : if has_sram(tech) = 0 generate
x : process
begin
assert false report "syncram: technology " & tech_table(tech) &
" not supported"
severity failure;
wait;
end process;
end generate;
dmsg : if GRLIB_CONFIG_ARRAY(grlib_debug_level) >= 2 generate
x : process
begin
assert false report "syncram: " & tost(2**abits) & "x" & tost(dbits) &
" (" & tech_table(tech) & ")"
severity note;
wait;
end process;
end generate;
chk : if GRLIB_CONFIG_ARRAY(grlib_syncram_selftest_enable) /= 0 generate
chkblk: block
signal refdo: std_logic_vector(dbits-1 downto 0);
signal pren: std_ulogic;
signal paddr: std_logic_vector(abits-1 downto 0);
begin
refram : generic_syncram generic map (abits, dbits)
port map (clk, address, datain, refdo, write);
p: process(clk)
begin
if rising_edge(clk) then
assert pren/='1' or refdo=dataoutx or is_x(refdo) or is_x(paddr)
report "Read mismatch addr=" & tost(paddr) & " impl=" & tost(dataoutx) & " ref=" & tost(refdo)
severity error;
pren <= enable and not write;
paddr <= address;
end if;
end process;
end block;
end generate;
-- pragma translate_on
end;
| gpl-3.0 | ca9a0b1de8ce3d9fd05e32ac2f7f09dc | 0.643431 | 3.81858 | false | true | false | false |
hoglet67/CoPro6502 | src/ROM/tuberom_6809.vhd | 2 | 86,728 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tuberom_6809 is
port (
CLK : in std_logic;
ADDR : in std_logic_vector(10 downto 0);
DATA : out std_logic_vector(7 downto 0)
);
end;
architecture RTL of tuberom_6809 is
signal rom_addr : std_logic_vector(11 downto 0);
begin
p_addr : process(ADDR)
begin
rom_addr <= (others => '0');
rom_addr(10 downto 0) <= ADDR;
end process;
p_rom : process
begin
wait until rising_edge(CLK);
DATA <= (others => '0');
case rom_addr is
when x"000" => DATA <= x"F8";
when x"001" => DATA <= x"2C";
when x"002" => DATA <= x"F8";
when x"003" => DATA <= x"6E";
when x"004" => DATA <= x"FF";
when x"005" => DATA <= x"E0";
when x"006" => DATA <= x"F8";
when x"007" => DATA <= x"E9";
when x"008" => DATA <= x"F8";
when x"009" => DATA <= x"FD";
when x"00A" => DATA <= x"FF";
when x"00B" => DATA <= x"EE";
when x"00C" => DATA <= x"F8";
when x"00D" => DATA <= x"F2";
when x"00E" => DATA <= x"FF";
when x"00F" => DATA <= x"E7";
when x"010" => DATA <= x"F8";
when x"011" => DATA <= x"EF";
when x"012" => DATA <= x"F8";
when x"013" => DATA <= x"E8";
when x"014" => DATA <= x"20";
when x"015" => DATA <= x"58";
when x"016" => DATA <= x"0D";
when x"017" => DATA <= x"36";
when x"018" => DATA <= x"38";
when x"019" => DATA <= x"30";
when x"01A" => DATA <= x"39";
when x"01B" => DATA <= x"20";
when x"01C" => DATA <= x"54";
when x"01D" => DATA <= x"55";
when x"01E" => DATA <= x"42";
when x"01F" => DATA <= x"45";
when x"020" => DATA <= x"20";
when x"021" => DATA <= x"36";
when x"022" => DATA <= x"34";
when x"023" => DATA <= x"4B";
when x"024" => DATA <= x"20";
when x"025" => DATA <= x"31";
when x"026" => DATA <= x"2E";
when x"027" => DATA <= x"30";
when x"028" => DATA <= x"35";
when x"029" => DATA <= x"20";
when x"02A" => DATA <= x"0D";
when x"02B" => DATA <= x"00";
when x"02C" => DATA <= x"1A";
when x"02D" => DATA <= x"50";
when x"02E" => DATA <= x"10";
when x"02F" => DATA <= x"CE";
when x"030" => DATA <= x"F8";
when x"031" => DATA <= x"00";
when x"032" => DATA <= x"1F";
when x"033" => DATA <= x"41";
when x"034" => DATA <= x"EC";
when x"035" => DATA <= x"84";
when x"036" => DATA <= x"ED";
when x"037" => DATA <= x"81";
when x"038" => DATA <= x"8C";
when x"039" => DATA <= x"FE";
when x"03A" => DATA <= x"C0";
when x"03B" => DATA <= x"26";
when x"03C" => DATA <= x"03";
when x"03D" => DATA <= x"8E";
when x"03E" => DATA <= x"FE";
when x"03F" => DATA <= x"F0";
when x"040" => DATA <= x"8C";
when x"041" => DATA <= x"FF";
when x"042" => DATA <= x"8C";
when x"043" => DATA <= x"26";
when x"044" => DATA <= x"03";
when x"045" => DATA <= x"8E";
when x"046" => DATA <= x"FF";
when x"047" => DATA <= x"94";
when x"048" => DATA <= x"8C";
when x"049" => DATA <= x"00";
when x"04A" => DATA <= x"00";
when x"04B" => DATA <= x"26";
when x"04C" => DATA <= x"E7";
when x"04D" => DATA <= x"B6";
when x"04E" => DATA <= x"FE";
when x"04F" => DATA <= x"E0";
when x"050" => DATA <= x"1A";
when x"051" => DATA <= x"50";
when x"052" => DATA <= x"10";
when x"053" => DATA <= x"CE";
when x"054" => DATA <= x"FF";
when x"055" => DATA <= x"80";
when x"056" => DATA <= x"8D";
when x"057" => DATA <= x"66";
when x"058" => DATA <= x"BE";
when x"059" => DATA <= x"FF";
when x"05A" => DATA <= x"90";
when x"05B" => DATA <= x"BF";
when x"05C" => DATA <= x"FF";
when x"05D" => DATA <= x"8C";
when x"05E" => DATA <= x"1C";
when x"05F" => DATA <= x"00";
when x"060" => DATA <= x"BD";
when x"061" => DATA <= x"F9";
when x"062" => DATA <= x"36";
when x"063" => DATA <= x"BD";
when x"064" => DATA <= x"FF";
when x"065" => DATA <= x"E7";
when x"066" => DATA <= x"4F";
when x"067" => DATA <= x"BD";
when x"068" => DATA <= x"FF";
when x"069" => DATA <= x"EE";
when x"06A" => DATA <= x"4F";
when x"06B" => DATA <= x"BD";
when x"06C" => DATA <= x"FA";
when x"06D" => DATA <= x"40";
when x"06E" => DATA <= x"10";
when x"06F" => DATA <= x"CE";
when x"070" => DATA <= x"FF";
when x"071" => DATA <= x"80";
when x"072" => DATA <= x"8D";
when x"073" => DATA <= x"4A";
when x"074" => DATA <= x"10";
when x"075" => DATA <= x"FE";
when x"076" => DATA <= x"FF";
when x"077" => DATA <= x"8A";
when x"078" => DATA <= x"8E";
when x"079" => DATA <= x"FF";
when x"07A" => DATA <= x"B9";
when x"07B" => DATA <= x"BF";
when x"07C" => DATA <= x"FF";
when x"07D" => DATA <= x"90";
when x"07E" => DATA <= x"1C";
when x"07F" => DATA <= x"00";
when x"080" => DATA <= x"8E";
when x"081" => DATA <= x"F8";
when x"082" => DATA <= x"93";
when x"083" => DATA <= x"BD";
when x"084" => DATA <= x"F9";
when x"085" => DATA <= x"39";
when x"086" => DATA <= x"BD";
when x"087" => DATA <= x"FF";
when x"088" => DATA <= x"F1";
when x"089" => DATA <= x"25";
when x"08A" => DATA <= x"14";
when x"08B" => DATA <= x"8E";
when x"08C" => DATA <= x"FF";
when x"08D" => DATA <= x"00";
when x"08E" => DATA <= x"BD";
when x"08F" => DATA <= x"FF";
when x"090" => DATA <= x"F7";
when x"091" => DATA <= x"20";
when x"092" => DATA <= x"ED";
when x"093" => DATA <= x"36";
when x"094" => DATA <= x"38";
when x"095" => DATA <= x"30";
when x"096" => DATA <= x"39";
when x"097" => DATA <= x"3E";
when x"098" => DATA <= x"2A";
when x"099" => DATA <= x"00";
when x"09A" => DATA <= x"FF";
when x"09B" => DATA <= x"00";
when x"09C" => DATA <= x"6F";
when x"09D" => DATA <= x"20";
when x"09E" => DATA <= x"FF";
when x"09F" => DATA <= x"86";
when x"0A0" => DATA <= x"7E";
when x"0A1" => DATA <= x"BD";
when x"0A2" => DATA <= x"FF";
when x"0A3" => DATA <= x"F4";
when x"0A4" => DATA <= x"3F";
when x"0A5" => DATA <= x"11";
when x"0A6" => DATA <= x"45";
when x"0A7" => DATA <= x"73";
when x"0A8" => DATA <= x"63";
when x"0A9" => DATA <= x"61";
when x"0AA" => DATA <= x"70";
when x"0AB" => DATA <= x"65";
when x"0AC" => DATA <= x"00";
when x"0AD" => DATA <= x"10";
when x"0AE" => DATA <= x"FE";
when x"0AF" => DATA <= x"FF";
when x"0B0" => DATA <= x"8A";
when x"0B1" => DATA <= x"BD";
when x"0B2" => DATA <= x"FF";
when x"0B3" => DATA <= x"E7";
when x"0B4" => DATA <= x"A6";
when x"0B5" => DATA <= x"80";
when x"0B6" => DATA <= x"BD";
when x"0B7" => DATA <= x"F9";
when x"0B8" => DATA <= x"39";
when x"0B9" => DATA <= x"BD";
when x"0BA" => DATA <= x"FF";
when x"0BB" => DATA <= x"E7";
when x"0BC" => DATA <= x"20";
when x"0BD" => DATA <= x"C2";
when x"0BE" => DATA <= x"CC";
when x"0BF" => DATA <= x"00";
when x"0C0" => DATA <= x"00";
when x"0C1" => DATA <= x"FD";
when x"0C2" => DATA <= x"FF";
when x"0C3" => DATA <= x"88";
when x"0C4" => DATA <= x"CC";
when x"0C5" => DATA <= x"F8";
when x"0C6" => DATA <= x"00";
when x"0C7" => DATA <= x"FD";
when x"0C8" => DATA <= x"FF";
when x"0C9" => DATA <= x"8A";
when x"0CA" => DATA <= x"CC";
when x"0CB" => DATA <= x"F8";
when x"0CC" => DATA <= x"AD";
when x"0CD" => DATA <= x"FD";
when x"0CE" => DATA <= x"FF";
when x"0CF" => DATA <= x"FA";
when x"0D0" => DATA <= x"4D";
when x"0D1" => DATA <= x"26";
when x"0D2" => DATA <= x"06";
when x"0D3" => DATA <= x"FC";
when x"0D4" => DATA <= x"FF";
when x"0D5" => DATA <= x"8E";
when x"0D6" => DATA <= x"FD";
when x"0D7" => DATA <= x"FF";
when x"0D8" => DATA <= x"90";
when x"0D9" => DATA <= x"CC";
when x"0DA" => DATA <= x"FE";
when x"0DB" => DATA <= x"29";
when x"0DC" => DATA <= x"FD";
when x"0DD" => DATA <= x"FE";
when x"0DE" => DATA <= x"FA";
when x"0DF" => DATA <= x"8E";
when x"0E0" => DATA <= x"FF";
when x"0E1" => DATA <= x"FA";
when x"0E2" => DATA <= x"10";
when x"0E3" => DATA <= x"8E";
when x"0E4" => DATA <= x"FF";
when x"0E5" => DATA <= x"80";
when x"0E6" => DATA <= x"5F";
when x"0E7" => DATA <= x"4F";
when x"0E8" => DATA <= x"39";
when x"0E9" => DATA <= x"BD";
when x"0EA" => DATA <= x"FF";
when x"0EB" => DATA <= x"E0";
when x"0EC" => DATA <= x"7E";
when x"0ED" => DATA <= x"FF";
when x"0EE" => DATA <= x"EE";
when x"0EF" => DATA <= x"BD";
when x"0F0" => DATA <= x"FF";
when x"0F1" => DATA <= x"E7";
when x"0F2" => DATA <= x"A6";
when x"0F3" => DATA <= x"80";
when x"0F4" => DATA <= x"81";
when x"0F5" => DATA <= x"04";
when x"0F6" => DATA <= x"27";
when x"0F7" => DATA <= x"F0";
when x"0F8" => DATA <= x"BD";
when x"0F9" => DATA <= x"FF";
when x"0FA" => DATA <= x"EE";
when x"0FB" => DATA <= x"20";
when x"0FC" => DATA <= x"F5";
when x"0FD" => DATA <= x"34";
when x"0FE" => DATA <= x"32";
when x"0FF" => DATA <= x"86";
when x"100" => DATA <= x"80";
when x"101" => DATA <= x"8E";
when x"102" => DATA <= x"FF";
when x"103" => DATA <= x"FF";
when x"104" => DATA <= x"1F";
when x"105" => DATA <= x"12";
when x"106" => DATA <= x"BD";
when x"107" => DATA <= x"FF";
when x"108" => DATA <= x"F4";
when x"109" => DATA <= x"8C";
when x"10A" => DATA <= x"00";
when x"10B" => DATA <= x"00";
when x"10C" => DATA <= x"35";
when x"10D" => DATA <= x"B2";
when x"10E" => DATA <= x"34";
when x"10F" => DATA <= x"04";
when x"110" => DATA <= x"1F";
when x"111" => DATA <= x"10";
when x"112" => DATA <= x"8D";
when x"113" => DATA <= x"04";
when x"114" => DATA <= x"1F";
when x"115" => DATA <= x"98";
when x"116" => DATA <= x"35";
when x"117" => DATA <= x"04";
when x"118" => DATA <= x"34";
when x"119" => DATA <= x"02";
when x"11A" => DATA <= x"44";
when x"11B" => DATA <= x"44";
when x"11C" => DATA <= x"44";
when x"11D" => DATA <= x"44";
when x"11E" => DATA <= x"8D";
when x"11F" => DATA <= x"02";
when x"120" => DATA <= x"35";
when x"121" => DATA <= x"02";
when x"122" => DATA <= x"84";
when x"123" => DATA <= x"0F";
when x"124" => DATA <= x"81";
when x"125" => DATA <= x"0A";
when x"126" => DATA <= x"25";
when x"127" => DATA <= x"02";
when x"128" => DATA <= x"8B";
when x"129" => DATA <= x"07";
when x"12A" => DATA <= x"8B";
when x"12B" => DATA <= x"30";
when x"12C" => DATA <= x"7E";
when x"12D" => DATA <= x"FF";
when x"12E" => DATA <= x"EE";
when x"12F" => DATA <= x"35";
when x"130" => DATA <= x"10";
when x"131" => DATA <= x"8D";
when x"132" => DATA <= x"06";
when x"133" => DATA <= x"34";
when x"134" => DATA <= x"10";
when x"135" => DATA <= x"39";
when x"136" => DATA <= x"8E";
when x"137" => DATA <= x"F8";
when x"138" => DATA <= x"16";
when x"139" => DATA <= x"A6";
when x"13A" => DATA <= x"80";
when x"13B" => DATA <= x"27";
when x"13C" => DATA <= x"F8";
when x"13D" => DATA <= x"BD";
when x"13E" => DATA <= x"FF";
when x"13F" => DATA <= x"E3";
when x"140" => DATA <= x"20";
when x"141" => DATA <= x"F7";
when x"142" => DATA <= x"10";
when x"143" => DATA <= x"8E";
when x"144" => DATA <= x"00";
when x"145" => DATA <= x"00";
when x"146" => DATA <= x"A6";
when x"147" => DATA <= x"80";
when x"148" => DATA <= x"81";
when x"149" => DATA <= x"30";
when x"14A" => DATA <= x"25";
when x"14B" => DATA <= x"33";
when x"14C" => DATA <= x"81";
when x"14D" => DATA <= x"3A";
when x"14E" => DATA <= x"25";
when x"14F" => DATA <= x"0A";
when x"150" => DATA <= x"84";
when x"151" => DATA <= x"DF";
when x"152" => DATA <= x"80";
when x"153" => DATA <= x"07";
when x"154" => DATA <= x"25";
when x"155" => DATA <= x"29";
when x"156" => DATA <= x"81";
when x"157" => DATA <= x"40";
when x"158" => DATA <= x"24";
when x"159" => DATA <= x"25";
when x"15A" => DATA <= x"84";
when x"15B" => DATA <= x"0F";
when x"15C" => DATA <= x"1E";
when x"15D" => DATA <= x"02";
when x"15E" => DATA <= x"58";
when x"15F" => DATA <= x"49";
when x"160" => DATA <= x"58";
when x"161" => DATA <= x"49";
when x"162" => DATA <= x"58";
when x"163" => DATA <= x"49";
when x"164" => DATA <= x"58";
when x"165" => DATA <= x"49";
when x"166" => DATA <= x"1E";
when x"167" => DATA <= x"12";
when x"168" => DATA <= x"1E";
when x"169" => DATA <= x"01";
when x"16A" => DATA <= x"1E";
when x"16B" => DATA <= x"89";
when x"16C" => DATA <= x"3A";
when x"16D" => DATA <= x"1E";
when x"16E" => DATA <= x"12";
when x"16F" => DATA <= x"20";
when x"170" => DATA <= x"D5";
when x"171" => DATA <= x"A6";
when x"172" => DATA <= x"80";
when x"173" => DATA <= x"81";
when x"174" => DATA <= x"21";
when x"175" => DATA <= x"24";
when x"176" => DATA <= x"FA";
when x"177" => DATA <= x"30";
when x"178" => DATA <= x"1F";
when x"179" => DATA <= x"A6";
when x"17A" => DATA <= x"80";
when x"17B" => DATA <= x"81";
when x"17C" => DATA <= x"20";
when x"17D" => DATA <= x"27";
when x"17E" => DATA <= x"FA";
when x"17F" => DATA <= x"30";
when x"180" => DATA <= x"1F";
when x"181" => DATA <= x"81";
when x"182" => DATA <= x"21";
when x"183" => DATA <= x"39";
when x"184" => DATA <= x"34";
when x"185" => DATA <= x"7C";
when x"186" => DATA <= x"33";
when x"187" => DATA <= x"78";
when x"188" => DATA <= x"11";
when x"189" => DATA <= x"8C";
when x"18A" => DATA <= x"F8";
when x"18B" => DATA <= x"00";
when x"18C" => DATA <= x"24";
when x"18D" => DATA <= x"04";
when x"18E" => DATA <= x"10";
when x"18F" => DATA <= x"CE";
when x"190" => DATA <= x"FF";
when x"191" => DATA <= x"80";
when x"192" => DATA <= x"34";
when x"193" => DATA <= x"40";
when x"194" => DATA <= x"8D";
when x"195" => DATA <= x"13";
when x"196" => DATA <= x"35";
when x"197" => DATA <= x"40";
when x"198" => DATA <= x"32";
when x"199" => DATA <= x"48";
when x"19A" => DATA <= x"35";
when x"19B" => DATA <= x"FC";
when x"19C" => DATA <= x"47";
when x"19D" => DATA <= x"4F";
when x"19E" => DATA <= x"80";
when x"19F" => DATA <= x"48";
when x"1A0" => DATA <= x"45";
when x"1A1" => DATA <= x"4C";
when x"1A2" => DATA <= x"50";
when x"1A3" => DATA <= x"81";
when x"1A4" => DATA <= x"52";
when x"1A5" => DATA <= x"55";
when x"1A6" => DATA <= x"4E";
when x"1A7" => DATA <= x"82";
when x"1A8" => DATA <= x"00";
when x"1A9" => DATA <= x"8D";
when x"1AA" => DATA <= x"CE";
when x"1AB" => DATA <= x"A6";
when x"1AC" => DATA <= x"80";
when x"1AD" => DATA <= x"81";
when x"1AE" => DATA <= x"2A";
when x"1AF" => DATA <= x"27";
when x"1B0" => DATA <= x"F8";
when x"1B1" => DATA <= x"30";
when x"1B2" => DATA <= x"1F";
when x"1B3" => DATA <= x"34";
when x"1B4" => DATA <= x"10";
when x"1B5" => DATA <= x"81";
when x"1B6" => DATA <= x"2F";
when x"1B7" => DATA <= x"27";
when x"1B8" => DATA <= x"70";
when x"1B9" => DATA <= x"8D";
when x"1BA" => DATA <= x"B6";
when x"1BB" => DATA <= x"BF";
when x"1BC" => DATA <= x"FF";
when x"1BD" => DATA <= x"86";
when x"1BE" => DATA <= x"10";
when x"1BF" => DATA <= x"8E";
when x"1C0" => DATA <= x"F9";
when x"1C1" => DATA <= x"9C";
when x"1C2" => DATA <= x"AE";
when x"1C3" => DATA <= x"E4";
when x"1C4" => DATA <= x"A6";
when x"1C5" => DATA <= x"84";
when x"1C6" => DATA <= x"81";
when x"1C7" => DATA <= x"41";
when x"1C8" => DATA <= x"25";
when x"1C9" => DATA <= x"6A";
when x"1CA" => DATA <= x"A6";
when x"1CB" => DATA <= x"80";
when x"1CC" => DATA <= x"84";
when x"1CD" => DATA <= x"DF";
when x"1CE" => DATA <= x"A1";
when x"1CF" => DATA <= x"A0";
when x"1D0" => DATA <= x"27";
when x"1D1" => DATA <= x"F8";
when x"1D2" => DATA <= x"A6";
when x"1D3" => DATA <= x"A2";
when x"1D4" => DATA <= x"2B";
when x"1D5" => DATA <= x"16";
when x"1D6" => DATA <= x"A6";
when x"1D7" => DATA <= x"1F";
when x"1D8" => DATA <= x"81";
when x"1D9" => DATA <= x"2E";
when x"1DA" => DATA <= x"27";
when x"1DB" => DATA <= x"0A";
when x"1DC" => DATA <= x"A6";
when x"1DD" => DATA <= x"A0";
when x"1DE" => DATA <= x"2A";
when x"1DF" => DATA <= x"FC";
when x"1E0" => DATA <= x"A6";
when x"1E1" => DATA <= x"A4";
when x"1E2" => DATA <= x"26";
when x"1E3" => DATA <= x"DE";
when x"1E4" => DATA <= x"20";
when x"1E5" => DATA <= x"4E";
when x"1E6" => DATA <= x"A6";
when x"1E7" => DATA <= x"A0";
when x"1E8" => DATA <= x"2A";
when x"1E9" => DATA <= x"FC";
when x"1EA" => DATA <= x"20";
when x"1EB" => DATA <= x"06";
when x"1EC" => DATA <= x"E6";
when x"1ED" => DATA <= x"82";
when x"1EE" => DATA <= x"C1";
when x"1EF" => DATA <= x"21";
when x"1F0" => DATA <= x"24";
when x"1F1" => DATA <= x"42";
when x"1F2" => DATA <= x"81";
when x"1F3" => DATA <= x"81";
when x"1F4" => DATA <= x"27";
when x"1F5" => DATA <= x"30";
when x"1F6" => DATA <= x"24";
when x"1F7" => DATA <= x"33";
when x"1F8" => DATA <= x"BD";
when x"1F9" => DATA <= x"F9";
when x"1FA" => DATA <= x"79";
when x"1FB" => DATA <= x"10";
when x"1FC" => DATA <= x"BE";
when x"1FD" => DATA <= x"FF";
when x"1FE" => DATA <= x"90";
when x"1FF" => DATA <= x"81";
when x"200" => DATA <= x"0D";
when x"201" => DATA <= x"27";
when x"202" => DATA <= x"18";
when x"203" => DATA <= x"81";
when x"204" => DATA <= x"3B";
when x"205" => DATA <= x"27";
when x"206" => DATA <= x"12";
when x"207" => DATA <= x"BD";
when x"208" => DATA <= x"FF";
when x"209" => DATA <= x"A1";
when x"20A" => DATA <= x"24";
when x"20B" => DATA <= x"28";
when x"20C" => DATA <= x"BD";
when x"20D" => DATA <= x"F9";
when x"20E" => DATA <= x"79";
when x"20F" => DATA <= x"81";
when x"210" => DATA <= x"3B";
when x"211" => DATA <= x"27";
when x"212" => DATA <= x"06";
when x"213" => DATA <= x"81";
when x"214" => DATA <= x"0D";
when x"215" => DATA <= x"26";
when x"216" => DATA <= x"1D";
when x"217" => DATA <= x"30";
when x"218" => DATA <= x"1F";
when x"219" => DATA <= x"30";
when x"21A" => DATA <= x"01";
when x"21B" => DATA <= x"BF";
when x"21C" => DATA <= x"FF";
when x"21D" => DATA <= x"86";
when x"21E" => DATA <= x"35";
when x"21F" => DATA <= x"10";
when x"220" => DATA <= x"1F";
when x"221" => DATA <= x"21";
when x"222" => DATA <= x"1A";
when x"223" => DATA <= x"01";
when x"224" => DATA <= x"20";
when x"225" => DATA <= x"22";
when x"226" => DATA <= x"BD";
when x"227" => DATA <= x"F9";
when x"228" => DATA <= x"36";
when x"229" => DATA <= x"30";
when x"22A" => DATA <= x"01";
when x"22B" => DATA <= x"BD";
when x"22C" => DATA <= x"F9";
when x"22D" => DATA <= x"79";
when x"22E" => DATA <= x"BD";
when x"22F" => DATA <= x"F9";
when x"230" => DATA <= x"71";
when x"231" => DATA <= x"BF";
when x"232" => DATA <= x"FF";
when x"233" => DATA <= x"86";
when x"234" => DATA <= x"35";
when x"235" => DATA <= x"10";
when x"236" => DATA <= x"86";
when x"237" => DATA <= x"02";
when x"238" => DATA <= x"BD";
when x"239" => DATA <= x"FC";
when x"23A" => DATA <= x"F2";
when x"23B" => DATA <= x"BD";
when x"23C" => DATA <= x"FC";
when x"23D" => DATA <= x"9F";
when x"23E" => DATA <= x"1A";
when x"23F" => DATA <= x"01";
when x"240" => DATA <= x"BD";
when x"241" => DATA <= x"FA";
when x"242" => DATA <= x"C7";
when x"243" => DATA <= x"2A";
when x"244" => DATA <= x"53";
when x"245" => DATA <= x"BE";
when x"246" => DATA <= x"FF";
when x"247" => DATA <= x"8C";
when x"248" => DATA <= x"34";
when x"249" => DATA <= x"01";
when x"24A" => DATA <= x"1F";
when x"24B" => DATA <= x"12";
when x"24C" => DATA <= x"E6";
when x"24D" => DATA <= x"07";
when x"24E" => DATA <= x"3A";
when x"24F" => DATA <= x"CE";
when x"250" => DATA <= x"FA";
when x"251" => DATA <= x"A7";
when x"252" => DATA <= x"C6";
when x"253" => DATA <= x"04";
when x"254" => DATA <= x"A6";
when x"255" => DATA <= x"80";
when x"256" => DATA <= x"A1";
when x"257" => DATA <= x"C2";
when x"258" => DATA <= x"26";
when x"259" => DATA <= x"3F";
when x"25A" => DATA <= x"5A";
when x"25B" => DATA <= x"26";
when x"25C" => DATA <= x"F7";
when x"25D" => DATA <= x"A6";
when x"25E" => DATA <= x"26";
when x"25F" => DATA <= x"48";
when x"260" => DATA <= x"2A";
when x"261" => DATA <= x"45";
when x"262" => DATA <= x"84";
when x"263" => DATA <= x"1E";
when x"264" => DATA <= x"81";
when x"265" => DATA <= x"06";
when x"266" => DATA <= x"26";
when x"267" => DATA <= x"3F";
when x"268" => DATA <= x"30";
when x"269" => DATA <= x"1C";
when x"26A" => DATA <= x"BF";
when x"26B" => DATA <= x"FF";
when x"26C" => DATA <= x"82";
when x"26D" => DATA <= x"FE";
when x"26E" => DATA <= x"FF";
when x"26F" => DATA <= x"90";
when x"270" => DATA <= x"BE";
when x"271" => DATA <= x"FF";
when x"272" => DATA <= x"8A";
when x"273" => DATA <= x"35";
when x"274" => DATA <= x"02";
when x"275" => DATA <= x"34";
when x"276" => DATA <= x"50";
when x"277" => DATA <= x"10";
when x"278" => DATA <= x"8C";
when x"279" => DATA <= x"80";
when x"27A" => DATA <= x"00";
when x"27B" => DATA <= x"25";
when x"27C" => DATA <= x"04";
when x"27D" => DATA <= x"10";
when x"27E" => DATA <= x"BF";
when x"27F" => DATA <= x"FF";
when x"280" => DATA <= x"8A";
when x"281" => DATA <= x"10";
when x"282" => DATA <= x"BF";
when x"283" => DATA <= x"FF";
when x"284" => DATA <= x"8E";
when x"285" => DATA <= x"BE";
when x"286" => DATA <= x"FF";
when x"287" => DATA <= x"86";
when x"288" => DATA <= x"EE";
when x"289" => DATA <= x"66";
when x"28A" => DATA <= x"46";
when x"28B" => DATA <= x"86";
when x"28C" => DATA <= x"01";
when x"28D" => DATA <= x"AD";
when x"28E" => DATA <= x"A4";
when x"28F" => DATA <= x"35";
when x"290" => DATA <= x"60";
when x"291" => DATA <= x"10";
when x"292" => DATA <= x"BF";
when x"293" => DATA <= x"FF";
when x"294" => DATA <= x"8A";
when x"295" => DATA <= x"FF";
when x"296" => DATA <= x"FF";
when x"297" => DATA <= x"90";
when x"298" => DATA <= x"39";
when x"299" => DATA <= x"BE";
when x"29A" => DATA <= x"FF";
when x"29B" => DATA <= x"86";
when x"29C" => DATA <= x"EE";
when x"29D" => DATA <= x"63";
when x"29E" => DATA <= x"4F";
when x"29F" => DATA <= x"35";
when x"2A0" => DATA <= x"01";
when x"2A1" => DATA <= x"6E";
when x"2A2" => DATA <= x"A4";
when x"2A3" => DATA <= x"29";
when x"2A4" => DATA <= x"43";
when x"2A5" => DATA <= x"28";
when x"2A6" => DATA <= x"00";
when x"2A7" => DATA <= x"35";
when x"2A8" => DATA <= x"01";
when x"2A9" => DATA <= x"10";
when x"2AA" => DATA <= x"24";
when x"2AB" => DATA <= x"05";
when x"2AC" => DATA <= x"0C";
when x"2AD" => DATA <= x"BD";
when x"2AE" => DATA <= x"F8";
when x"2AF" => DATA <= x"CA";
when x"2B0" => DATA <= x"3F";
when x"2B1" => DATA <= x"F9";
when x"2B2" => DATA <= x"4E";
when x"2B3" => DATA <= x"6F";
when x"2B4" => DATA <= x"74";
when x"2B5" => DATA <= x"20";
when x"2B6" => DATA <= x"36";
when x"2B7" => DATA <= x"38";
when x"2B8" => DATA <= x"30";
when x"2B9" => DATA <= x"39";
when x"2BA" => DATA <= x"20";
when x"2BB" => DATA <= x"63";
when x"2BC" => DATA <= x"6F";
when x"2BD" => DATA <= x"64";
when x"2BE" => DATA <= x"65";
when x"2BF" => DATA <= x"00";
when x"2C0" => DATA <= x"4F";
when x"2C1" => DATA <= x"BD";
when x"2C2" => DATA <= x"FC";
when x"2C3" => DATA <= x"F2";
when x"2C4" => DATA <= x"8D";
when x"2C5" => DATA <= x"01";
when x"2C6" => DATA <= x"48";
when x"2C7" => DATA <= x"B6";
when x"2C8" => DATA <= x"FE";
when x"2C9" => DATA <= x"E2";
when x"2CA" => DATA <= x"2A";
when x"2CB" => DATA <= x"FB";
when x"2CC" => DATA <= x"B6";
when x"2CD" => DATA <= x"FE";
when x"2CE" => DATA <= x"E3";
when x"2CF" => DATA <= x"39";
when x"2D0" => DATA <= x"34";
when x"2D1" => DATA <= x"06";
when x"2D2" => DATA <= x"4D";
when x"2D3" => DATA <= x"2B";
when x"2D4" => DATA <= x"23";
when x"2D5" => DATA <= x"86";
when x"2D6" => DATA <= x"04";
when x"2D7" => DATA <= x"BD";
when x"2D8" => DATA <= x"FC";
when x"2D9" => DATA <= x"F2";
when x"2DA" => DATA <= x"1F";
when x"2DB" => DATA <= x"10";
when x"2DC" => DATA <= x"BD";
when x"2DD" => DATA <= x"FC";
when x"2DE" => DATA <= x"F0";
when x"2DF" => DATA <= x"35";
when x"2E0" => DATA <= x"06";
when x"2E1" => DATA <= x"34";
when x"2E2" => DATA <= x"06";
when x"2E3" => DATA <= x"BD";
when x"2E4" => DATA <= x"FC";
when x"2E5" => DATA <= x"F2";
when x"2E6" => DATA <= x"8D";
when x"2E7" => DATA <= x"DF";
when x"2E8" => DATA <= x"1F";
when x"2E9" => DATA <= x"89";
when x"2EA" => DATA <= x"4F";
when x"2EB" => DATA <= x"1F";
when x"2EC" => DATA <= x"01";
when x"2ED" => DATA <= x"35";
when x"2EE" => DATA <= x"86";
when x"2EF" => DATA <= x"8E";
when x"2F0" => DATA <= x"F8";
when x"2F1" => DATA <= x"16";
when x"2F2" => DATA <= x"BF";
when x"2F3" => DATA <= x"FF";
when x"2F4" => DATA <= x"86";
when x"2F5" => DATA <= x"7E";
when x"2F6" => DATA <= x"FA";
when x"2F7" => DATA <= x"3E";
when x"2F8" => DATA <= x"81";
when x"2F9" => DATA <= x"82";
when x"2FA" => DATA <= x"25";
when x"2FB" => DATA <= x"06";
when x"2FC" => DATA <= x"27";
when x"2FD" => DATA <= x"34";
when x"2FE" => DATA <= x"81";
when x"2FF" => DATA <= x"85";
when x"300" => DATA <= x"25";
when x"301" => DATA <= x"32";
when x"302" => DATA <= x"86";
when x"303" => DATA <= x"06";
when x"304" => DATA <= x"BD";
when x"305" => DATA <= x"FC";
when x"306" => DATA <= x"F2";
when x"307" => DATA <= x"1F";
when x"308" => DATA <= x"10";
when x"309" => DATA <= x"BD";
when x"30A" => DATA <= x"FC";
when x"30B" => DATA <= x"F0";
when x"30C" => DATA <= x"BD";
when x"30D" => DATA <= x"FC";
when x"30E" => DATA <= x"EE";
when x"30F" => DATA <= x"35";
when x"310" => DATA <= x"06";
when x"311" => DATA <= x"BD";
when x"312" => DATA <= x"FC";
when x"313" => DATA <= x"F2";
when x"314" => DATA <= x"81";
when x"315" => DATA <= x"9D";
when x"316" => DATA <= x"27";
when x"317" => DATA <= x"B7";
when x"318" => DATA <= x"81";
when x"319" => DATA <= x"8E";
when x"31A" => DATA <= x"27";
when x"31B" => DATA <= x"D3";
when x"31C" => DATA <= x"34";
when x"31D" => DATA <= x"06";
when x"31E" => DATA <= x"8D";
when x"31F" => DATA <= x"A7";
when x"320" => DATA <= x"48";
when x"321" => DATA <= x"34";
when x"322" => DATA <= x"01";
when x"323" => DATA <= x"8D";
when x"324" => DATA <= x"A2";
when x"325" => DATA <= x"1F";
when x"326" => DATA <= x"89";
when x"327" => DATA <= x"4F";
when x"328" => DATA <= x"1F";
when x"329" => DATA <= x"02";
when x"32A" => DATA <= x"8D";
when x"32B" => DATA <= x"9B";
when x"32C" => DATA <= x"1E";
when x"32D" => DATA <= x"89";
when x"32E" => DATA <= x"1F";
when x"32F" => DATA <= x"01";
when x"330" => DATA <= x"35";
when x"331" => DATA <= x"87";
when x"332" => DATA <= x"86";
when x"333" => DATA <= x"88";
when x"334" => DATA <= x"48";
when x"335" => DATA <= x"8E";
when x"336" => DATA <= x"FF";
when x"337" => DATA <= x"82";
when x"338" => DATA <= x"EC";
when x"339" => DATA <= x"86";
when x"33A" => DATA <= x"1F";
when x"33B" => DATA <= x"01";
when x"33C" => DATA <= x"1F";
when x"33D" => DATA <= x"89";
when x"33E" => DATA <= x"4F";
when x"33F" => DATA <= x"1F";
when x"340" => DATA <= x"02";
when x"341" => DATA <= x"35";
when x"342" => DATA <= x"86";
when x"343" => DATA <= x"4D";
when x"344" => DATA <= x"27";
when x"345" => DATA <= x"4B";
when x"346" => DATA <= x"34";
when x"347" => DATA <= x"26";
when x"348" => DATA <= x"34";
when x"349" => DATA <= x"10";
when x"34A" => DATA <= x"1F";
when x"34B" => DATA <= x"89";
when x"34C" => DATA <= x"86";
when x"34D" => DATA <= x"08";
when x"34E" => DATA <= x"BD";
when x"34F" => DATA <= x"FC";
when x"350" => DATA <= x"F2";
when x"351" => DATA <= x"BD";
when x"352" => DATA <= x"FC";
when x"353" => DATA <= x"F0";
when x"354" => DATA <= x"5D";
when x"355" => DATA <= x"2B";
when x"356" => DATA <= x"0A";
when x"357" => DATA <= x"86";
when x"358" => DATA <= x"10";
when x"359" => DATA <= x"C1";
when x"35A" => DATA <= x"15";
when x"35B" => DATA <= x"24";
when x"35C" => DATA <= x"06";
when x"35D" => DATA <= x"8E";
when x"35E" => DATA <= x"FB";
when x"35F" => DATA <= x"C0";
when x"360" => DATA <= x"3A";
when x"361" => DATA <= x"A6";
when x"362" => DATA <= x"84";
when x"363" => DATA <= x"1F";
when x"364" => DATA <= x"89";
when x"365" => DATA <= x"AE";
when x"366" => DATA <= x"E4";
when x"367" => DATA <= x"BD";
when x"368" => DATA <= x"FC";
when x"369" => DATA <= x"F0";
when x"36A" => DATA <= x"5A";
when x"36B" => DATA <= x"2B";
when x"36C" => DATA <= x"04";
when x"36D" => DATA <= x"5C";
when x"36E" => DATA <= x"BD";
when x"36F" => DATA <= x"FC";
when x"370" => DATA <= x"A8";
when x"371" => DATA <= x"E6";
when x"372" => DATA <= x"62";
when x"373" => DATA <= x"2B";
when x"374" => DATA <= x"0A";
when x"375" => DATA <= x"86";
when x"376" => DATA <= x"10";
when x"377" => DATA <= x"C1";
when x"378" => DATA <= x"15";
when x"379" => DATA <= x"24";
when x"37A" => DATA <= x"06";
when x"37B" => DATA <= x"8E";
when x"37C" => DATA <= x"FB";
when x"37D" => DATA <= x"D3";
when x"37E" => DATA <= x"3A";
when x"37F" => DATA <= x"A6";
when x"380" => DATA <= x"01";
when x"381" => DATA <= x"1F";
when x"382" => DATA <= x"89";
when x"383" => DATA <= x"35";
when x"384" => DATA <= x"10";
when x"385" => DATA <= x"BD";
when x"386" => DATA <= x"FC";
when x"387" => DATA <= x"F0";
when x"388" => DATA <= x"5A";
when x"389" => DATA <= x"2B";
when x"38A" => DATA <= x"04";
when x"38B" => DATA <= x"5C";
when x"38C" => DATA <= x"BD";
when x"38D" => DATA <= x"FC";
when x"38E" => DATA <= x"B1";
when x"38F" => DATA <= x"35";
when x"390" => DATA <= x"A6";
when x"391" => DATA <= x"86";
when x"392" => DATA <= x"0A";
when x"393" => DATA <= x"BD";
when x"394" => DATA <= x"FC";
when x"395" => DATA <= x"F2";
when x"396" => DATA <= x"34";
when x"397" => DATA <= x"04";
when x"398" => DATA <= x"30";
when x"399" => DATA <= x"02";
when x"39A" => DATA <= x"C6";
when x"39B" => DATA <= x"03";
when x"39C" => DATA <= x"BD";
when x"39D" => DATA <= x"FC";
when x"39E" => DATA <= x"A8";
when x"39F" => DATA <= x"86";
when x"3A0" => DATA <= x"07";
when x"3A1" => DATA <= x"BD";
when x"3A2" => DATA <= x"FC";
when x"3A3" => DATA <= x"F2";
when x"3A4" => DATA <= x"BD";
when x"3A5" => DATA <= x"FC";
when x"3A6" => DATA <= x"F0";
when x"3A7" => DATA <= x"BD";
when x"3A8" => DATA <= x"FA";
when x"3A9" => DATA <= x"C7";
when x"3AA" => DATA <= x"48";
when x"3AB" => DATA <= x"25";
when x"3AC" => DATA <= x"0D";
when x"3AD" => DATA <= x"AE";
when x"3AE" => DATA <= x"83";
when x"3AF" => DATA <= x"BD";
when x"3B0" => DATA <= x"FA";
when x"3B1" => DATA <= x"C7";
when x"3B2" => DATA <= x"A7";
when x"3B3" => DATA <= x"80";
when x"3B4" => DATA <= x"5C";
when x"3B5" => DATA <= x"81";
when x"3B6" => DATA <= x"0D";
when x"3B7" => DATA <= x"26";
when x"3B8" => DATA <= x"F6";
when x"3B9" => DATA <= x"5A";
when x"3BA" => DATA <= x"86";
when x"3BB" => DATA <= x"00";
when x"3BC" => DATA <= x"1F";
when x"3BD" => DATA <= x"02";
when x"3BE" => DATA <= x"35";
when x"3BF" => DATA <= x"04";
when x"3C0" => DATA <= x"39";
when x"3C1" => DATA <= x"00";
when x"3C2" => DATA <= x"05";
when x"3C3" => DATA <= x"00";
when x"3C4" => DATA <= x"05";
when x"3C5" => DATA <= x"04";
when x"3C6" => DATA <= x"05";
when x"3C7" => DATA <= x"08";
when x"3C8" => DATA <= x"0E";
when x"3C9" => DATA <= x"04";
when x"3CA" => DATA <= x"01";
when x"3CB" => DATA <= x"01";
when x"3CC" => DATA <= x"05";
when x"3CD" => DATA <= x"00";
when x"3CE" => DATA <= x"10";
when x"3CF" => DATA <= x"20";
when x"3D0" => DATA <= x"10";
when x"3D1" => DATA <= x"0D";
when x"3D2" => DATA <= x"00";
when x"3D3" => DATA <= x"04";
when x"3D4" => DATA <= x"80";
when x"3D5" => DATA <= x"05";
when x"3D6" => DATA <= x"00";
when x"3D7" => DATA <= x"05";
when x"3D8" => DATA <= x"00";
when x"3D9" => DATA <= x"05";
when x"3DA" => DATA <= x"00";
when x"3DB" => DATA <= x"00";
when x"3DC" => DATA <= x"00";
when x"3DD" => DATA <= x"05";
when x"3DE" => DATA <= x"09";
when x"3DF" => DATA <= x"05";
when x"3E0" => DATA <= x"00";
when x"3E1" => DATA <= x"08";
when x"3E2" => DATA <= x"19";
when x"3E3" => DATA <= x"00";
when x"3E4" => DATA <= x"01";
when x"3E5" => DATA <= x"0D";
when x"3E6" => DATA <= x"80";
when x"3E7" => DATA <= x"04";
when x"3E8" => DATA <= x"80";
when x"3E9" => DATA <= x"34";
when x"3EA" => DATA <= x"26";
when x"3EB" => DATA <= x"86";
when x"3EC" => DATA <= x"0C";
when x"3ED" => DATA <= x"BD";
when x"3EE" => DATA <= x"FC";
when x"3EF" => DATA <= x"F2";
when x"3F0" => DATA <= x"BD";
when x"3F1" => DATA <= x"FC";
when x"3F2" => DATA <= x"EE";
when x"3F3" => DATA <= x"5F";
when x"3F4" => DATA <= x"BD";
when x"3F5" => DATA <= x"FC";
when x"3F6" => DATA <= x"BB";
when x"3F7" => DATA <= x"35";
when x"3F8" => DATA <= x"02";
when x"3F9" => DATA <= x"BD";
when x"3FA" => DATA <= x"FC";
when x"3FB" => DATA <= x"F2";
when x"3FC" => DATA <= x"BD";
when x"3FD" => DATA <= x"FA";
when x"3FE" => DATA <= x"C7";
when x"3FF" => DATA <= x"34";
when x"400" => DATA <= x"02";
when x"401" => DATA <= x"5F";
when x"402" => DATA <= x"BD";
when x"403" => DATA <= x"FC";
when x"404" => DATA <= x"CD";
when x"405" => DATA <= x"35";
when x"406" => DATA <= x"A6";
when x"407" => DATA <= x"34";
when x"408" => DATA <= x"04";
when x"409" => DATA <= x"86";
when x"40A" => DATA <= x"0E";
when x"40B" => DATA <= x"BD";
when x"40C" => DATA <= x"FC";
when x"40D" => DATA <= x"F2";
when x"40E" => DATA <= x"BD";
when x"40F" => DATA <= x"FC";
when x"410" => DATA <= x"EE";
when x"411" => DATA <= x"35";
when x"412" => DATA <= x"04";
when x"413" => DATA <= x"7E";
when x"414" => DATA <= x"FA";
when x"415" => DATA <= x"C4";
when x"416" => DATA <= x"34";
when x"417" => DATA <= x"06";
when x"418" => DATA <= x"86";
when x"419" => DATA <= x"10";
when x"41A" => DATA <= x"BD";
when x"41B" => DATA <= x"FC";
when x"41C" => DATA <= x"F2";
when x"41D" => DATA <= x"BD";
when x"41E" => DATA <= x"FC";
when x"41F" => DATA <= x"EE";
when x"420" => DATA <= x"35";
when x"421" => DATA <= x"06";
when x"422" => DATA <= x"34";
when x"423" => DATA <= x"06";
when x"424" => DATA <= x"BD";
when x"425" => DATA <= x"FC";
when x"426" => DATA <= x"F2";
when x"427" => DATA <= x"BD";
when x"428" => DATA <= x"FA";
when x"429" => DATA <= x"C7";
when x"42A" => DATA <= x"35";
when x"42B" => DATA <= x"86";
when x"42C" => DATA <= x"34";
when x"42D" => DATA <= x"06";
when x"42E" => DATA <= x"86";
when x"42F" => DATA <= x"12";
when x"430" => DATA <= x"BD";
when x"431" => DATA <= x"FC";
when x"432" => DATA <= x"F2";
when x"433" => DATA <= x"35";
when x"434" => DATA <= x"06";
when x"435" => DATA <= x"BD";
when x"436" => DATA <= x"FC";
when x"437" => DATA <= x"F2";
when x"438" => DATA <= x"4D";
when x"439" => DATA <= x"27";
when x"43A" => DATA <= x"06";
when x"43B" => DATA <= x"BD";
when x"43C" => DATA <= x"FC";
when x"43D" => DATA <= x"9F";
when x"43E" => DATA <= x"7E";
when x"43F" => DATA <= x"FA";
when x"440" => DATA <= x"C7";
when x"441" => DATA <= x"34";
when x"442" => DATA <= x"04";
when x"443" => DATA <= x"BD";
when x"444" => DATA <= x"FC";
when x"445" => DATA <= x"EE";
when x"446" => DATA <= x"BD";
when x"447" => DATA <= x"FA";
when x"448" => DATA <= x"C7";
when x"449" => DATA <= x"4F";
when x"44A" => DATA <= x"35";
when x"44B" => DATA <= x"84";
when x"44C" => DATA <= x"34";
when x"44D" => DATA <= x"36";
when x"44E" => DATA <= x"86";
when x"44F" => DATA <= x"14";
when x"450" => DATA <= x"BD";
when x"451" => DATA <= x"FC";
when x"452" => DATA <= x"F2";
when x"453" => DATA <= x"30";
when x"454" => DATA <= x"02";
when x"455" => DATA <= x"C6";
when x"456" => DATA <= x"0C";
when x"457" => DATA <= x"BD";
when x"458" => DATA <= x"FC";
when x"459" => DATA <= x"BB";
when x"45A" => DATA <= x"AE";
when x"45B" => DATA <= x"83";
when x"45C" => DATA <= x"BD";
when x"45D" => DATA <= x"FC";
when x"45E" => DATA <= x"9F";
when x"45F" => DATA <= x"35";
when x"460" => DATA <= x"02";
when x"461" => DATA <= x"BD";
when x"462" => DATA <= x"FC";
when x"463" => DATA <= x"F2";
when x"464" => DATA <= x"BD";
when x"465" => DATA <= x"FA";
when x"466" => DATA <= x"C7";
when x"467" => DATA <= x"35";
when x"468" => DATA <= x"14";
when x"469" => DATA <= x"34";
when x"46A" => DATA <= x"06";
when x"46B" => DATA <= x"30";
when x"46C" => DATA <= x"02";
when x"46D" => DATA <= x"C6";
when x"46E" => DATA <= x"0C";
when x"46F" => DATA <= x"BD";
when x"470" => DATA <= x"FC";
when x"471" => DATA <= x"CD";
when x"472" => DATA <= x"30";
when x"473" => DATA <= x"1E";
when x"474" => DATA <= x"35";
when x"475" => DATA <= x"A6";
when x"476" => DATA <= x"34";
when x"477" => DATA <= x"26";
when x"478" => DATA <= x"86";
when x"479" => DATA <= x"16";
when x"47A" => DATA <= x"BD";
when x"47B" => DATA <= x"FC";
when x"47C" => DATA <= x"F2";
when x"47D" => DATA <= x"30";
when x"47E" => DATA <= x"01";
when x"47F" => DATA <= x"C6";
when x"480" => DATA <= x"08";
when x"481" => DATA <= x"BD";
when x"482" => DATA <= x"FC";
when x"483" => DATA <= x"BB";
when x"484" => DATA <= x"A6";
when x"485" => DATA <= x"82";
when x"486" => DATA <= x"BD";
when x"487" => DATA <= x"FC";
when x"488" => DATA <= x"F2";
when x"489" => DATA <= x"35";
when x"48A" => DATA <= x"02";
when x"48B" => DATA <= x"BD";
when x"48C" => DATA <= x"FC";
when x"48D" => DATA <= x"F2";
when x"48E" => DATA <= x"30";
when x"48F" => DATA <= x"01";
when x"490" => DATA <= x"C6";
when x"491" => DATA <= x"08";
when x"492" => DATA <= x"BD";
when x"493" => DATA <= x"FC";
when x"494" => DATA <= x"CD";
when x"495" => DATA <= x"BD";
when x"496" => DATA <= x"FA";
when x"497" => DATA <= x"C7";
when x"498" => DATA <= x"A7";
when x"499" => DATA <= x"82";
when x"49A" => DATA <= x"35";
when x"49B" => DATA <= x"24";
when x"49C" => DATA <= x"7E";
when x"49D" => DATA <= x"FA";
when x"49E" => DATA <= x"C4";
when x"49F" => DATA <= x"A6";
when x"4A0" => DATA <= x"80";
when x"4A1" => DATA <= x"8D";
when x"4A2" => DATA <= x"4F";
when x"4A3" => DATA <= x"81";
when x"4A4" => DATA <= x"0D";
when x"4A5" => DATA <= x"26";
when x"4A6" => DATA <= x"F8";
when x"4A7" => DATA <= x"39";
when x"4A8" => DATA <= x"3A";
when x"4A9" => DATA <= x"A6";
when x"4AA" => DATA <= x"82";
when x"4AB" => DATA <= x"8D";
when x"4AC" => DATA <= x"45";
when x"4AD" => DATA <= x"5A";
when x"4AE" => DATA <= x"26";
when x"4AF" => DATA <= x"F9";
when x"4B0" => DATA <= x"39";
when x"4B1" => DATA <= x"3A";
when x"4B2" => DATA <= x"BD";
when x"4B3" => DATA <= x"FA";
when x"4B4" => DATA <= x"C7";
when x"4B5" => DATA <= x"A7";
when x"4B6" => DATA <= x"82";
when x"4B7" => DATA <= x"5A";
when x"4B8" => DATA <= x"26";
when x"4B9" => DATA <= x"F8";
when x"4BA" => DATA <= x"39";
when x"4BB" => DATA <= x"3A";
when x"4BC" => DATA <= x"A6";
when x"4BD" => DATA <= x"80";
when x"4BE" => DATA <= x"8D";
when x"4BF" => DATA <= x"32";
when x"4C0" => DATA <= x"5A";
when x"4C1" => DATA <= x"C5";
when x"4C2" => DATA <= x"03";
when x"4C3" => DATA <= x"26";
when x"4C4" => DATA <= x"F7";
when x"4C5" => DATA <= x"30";
when x"4C6" => DATA <= x"18";
when x"4C7" => DATA <= x"5D";
when x"4C8" => DATA <= x"2A";
when x"4C9" => DATA <= x"F2";
when x"4CA" => DATA <= x"30";
when x"4CB" => DATA <= x"04";
when x"4CC" => DATA <= x"39";
when x"4CD" => DATA <= x"3A";
when x"4CE" => DATA <= x"BD";
when x"4CF" => DATA <= x"FA";
when x"4D0" => DATA <= x"C7";
when x"4D1" => DATA <= x"A7";
when x"4D2" => DATA <= x"80";
when x"4D3" => DATA <= x"5A";
when x"4D4" => DATA <= x"C5";
when x"4D5" => DATA <= x"03";
when x"4D6" => DATA <= x"26";
when x"4D7" => DATA <= x"F6";
when x"4D8" => DATA <= x"30";
when x"4D9" => DATA <= x"18";
when x"4DA" => DATA <= x"5D";
when x"4DB" => DATA <= x"2A";
when x"4DC" => DATA <= x"F1";
when x"4DD" => DATA <= x"30";
when x"4DE" => DATA <= x"04";
when x"4DF" => DATA <= x"39";
when x"4E0" => DATA <= x"34";
when x"4E1" => DATA <= x"02";
when x"4E2" => DATA <= x"B6";
when x"4E3" => DATA <= x"FE";
when x"4E4" => DATA <= x"E0";
when x"4E5" => DATA <= x"48";
when x"4E6" => DATA <= x"2A";
when x"4E7" => DATA <= x"FA";
when x"4E8" => DATA <= x"35";
when x"4E9" => DATA <= x"02";
when x"4EA" => DATA <= x"B7";
when x"4EB" => DATA <= x"FE";
when x"4EC" => DATA <= x"E1";
when x"4ED" => DATA <= x"39";
when x"4EE" => DATA <= x"1F";
when x"4EF" => DATA <= x"20";
when x"4F0" => DATA <= x"1F";
when x"4F1" => DATA <= x"98";
when x"4F2" => DATA <= x"34";
when x"4F3" => DATA <= x"02";
when x"4F4" => DATA <= x"B6";
when x"4F5" => DATA <= x"FE";
when x"4F6" => DATA <= x"E2";
when x"4F7" => DATA <= x"48";
when x"4F8" => DATA <= x"2A";
when x"4F9" => DATA <= x"FA";
when x"4FA" => DATA <= x"35";
when x"4FB" => DATA <= x"02";
when x"4FC" => DATA <= x"B7";
when x"4FD" => DATA <= x"FE";
when x"4FE" => DATA <= x"E3";
when x"4FF" => DATA <= x"39";
when x"500" => DATA <= x"34";
when x"501" => DATA <= x"02";
when x"502" => DATA <= x"B6";
when x"503" => DATA <= x"FE";
when x"504" => DATA <= x"E6";
when x"505" => DATA <= x"2B";
when x"506" => DATA <= x"51";
when x"507" => DATA <= x"B6";
when x"508" => DATA <= x"FE";
when x"509" => DATA <= x"E0";
when x"50A" => DATA <= x"2B";
when x"50B" => DATA <= x"06";
when x"50C" => DATA <= x"35";
when x"50D" => DATA <= x"02";
when x"50E" => DATA <= x"6E";
when x"50F" => DATA <= x"9F";
when x"510" => DATA <= x"FF";
when x"511" => DATA <= x"B1";
when x"512" => DATA <= x"B6";
when x"513" => DATA <= x"FE";
when x"514" => DATA <= x"E1";
when x"515" => DATA <= x"2B";
when x"516" => DATA <= x"1B";
when x"517" => DATA <= x"35";
when x"518" => DATA <= x"02";
when x"519" => DATA <= x"34";
when x"51A" => DATA <= x"76";
when x"51B" => DATA <= x"8D";
when x"51C" => DATA <= x"1C";
when x"51D" => DATA <= x"1F";
when x"51E" => DATA <= x"89";
when x"51F" => DATA <= x"4F";
when x"520" => DATA <= x"1F";
when x"521" => DATA <= x"02";
when x"522" => DATA <= x"8D";
when x"523" => DATA <= x"15";
when x"524" => DATA <= x"1F";
when x"525" => DATA <= x"89";
when x"526" => DATA <= x"4F";
when x"527" => DATA <= x"1F";
when x"528" => DATA <= x"01";
when x"529" => DATA <= x"8D";
when x"52A" => DATA <= x"0E";
when x"52B" => DATA <= x"AD";
when x"52C" => DATA <= x"9F";
when x"52D" => DATA <= x"FF";
when x"52E" => DATA <= x"FC";
when x"52F" => DATA <= x"35";
when x"530" => DATA <= x"76";
when x"531" => DATA <= x"3B";
when x"532" => DATA <= x"48";
when x"533" => DATA <= x"B7";
when x"534" => DATA <= x"FF";
when x"535" => DATA <= x"80";
when x"536" => DATA <= x"35";
when x"537" => DATA <= x"02";
when x"538" => DATA <= x"3B";
when x"539" => DATA <= x"B6";
when x"53A" => DATA <= x"FE";
when x"53B" => DATA <= x"E6";
when x"53C" => DATA <= x"2A";
when x"53D" => DATA <= x"02";
when x"53E" => DATA <= x"8D";
when x"53F" => DATA <= x"12";
when x"540" => DATA <= x"B6";
when x"541" => DATA <= x"FE";
when x"542" => DATA <= x"E0";
when x"543" => DATA <= x"2A";
when x"544" => DATA <= x"F4";
when x"545" => DATA <= x"B6";
when x"546" => DATA <= x"FE";
when x"547" => DATA <= x"E1";
when x"548" => DATA <= x"39";
when x"549" => DATA <= x"B6";
when x"54A" => DATA <= x"FE";
when x"54B" => DATA <= x"E6";
when x"54C" => DATA <= x"2A";
when x"54D" => DATA <= x"FB";
when x"54E" => DATA <= x"B6";
when x"54F" => DATA <= x"FE";
when x"550" => DATA <= x"E7";
when x"551" => DATA <= x"39";
when x"552" => DATA <= x"1C";
when x"553" => DATA <= x"7F";
when x"554" => DATA <= x"34";
when x"555" => DATA <= x"01";
when x"556" => DATA <= x"34";
when x"557" => DATA <= x"02";
when x"558" => DATA <= x"35";
when x"559" => DATA <= x"02";
when x"55A" => DATA <= x"34";
when x"55B" => DATA <= x"16";
when x"55C" => DATA <= x"B6";
when x"55D" => DATA <= x"FE";
when x"55E" => DATA <= x"E7";
when x"55F" => DATA <= x"2A";
when x"560" => DATA <= x"22";
when x"561" => DATA <= x"10";
when x"562" => DATA <= x"CE";
when x"563" => DATA <= x"FF";
when x"564" => DATA <= x"80";
when x"565" => DATA <= x"8E";
when x"566" => DATA <= x"FF";
when x"567" => DATA <= x"00";
when x"568" => DATA <= x"BD";
when x"569" => DATA <= x"FA";
when x"56A" => DATA <= x"C7";
when x"56B" => DATA <= x"86";
when x"56C" => DATA <= x"3F";
when x"56D" => DATA <= x"A7";
when x"56E" => DATA <= x"80";
when x"56F" => DATA <= x"BD";
when x"570" => DATA <= x"FA";
when x"571" => DATA <= x"C7";
when x"572" => DATA <= x"A7";
when x"573" => DATA <= x"80";
when x"574" => DATA <= x"BD";
when x"575" => DATA <= x"FA";
when x"576" => DATA <= x"C7";
when x"577" => DATA <= x"A7";
when x"578" => DATA <= x"80";
when x"579" => DATA <= x"26";
when x"57A" => DATA <= x"F9";
when x"57B" => DATA <= x"8E";
when x"57C" => DATA <= x"FF";
when x"57D" => DATA <= x"01";
when x"57E" => DATA <= x"34";
when x"57F" => DATA <= x"10";
when x"580" => DATA <= x"7E";
when x"581" => DATA <= x"FF";
when x"582" => DATA <= x"BC";
when x"583" => DATA <= x"34";
when x"584" => DATA <= x"02";
when x"585" => DATA <= x"8D";
when x"586" => DATA <= x"C2";
when x"587" => DATA <= x"35";
when x"588" => DATA <= x"02";
when x"589" => DATA <= x"81";
when x"58A" => DATA <= x"05";
when x"58B" => DATA <= x"26";
when x"58C" => DATA <= x"06";
when x"58D" => DATA <= x"7F";
when x"58E" => DATA <= x"FF";
when x"58F" => DATA <= x"94";
when x"590" => DATA <= x"35";
when x"591" => DATA <= x"16";
when x"592" => DATA <= x"3B";
when x"593" => DATA <= x"34";
when x"594" => DATA <= x"02";
when x"595" => DATA <= x"8D";
when x"596" => DATA <= x"B2";
when x"597" => DATA <= x"8D";
when x"598" => DATA <= x"B0";
when x"599" => DATA <= x"8D";
when x"59A" => DATA <= x"AE";
when x"59B" => DATA <= x"1E";
when x"59C" => DATA <= x"89";
when x"59D" => DATA <= x"8D";
when x"59E" => DATA <= x"AA";
when x"59F" => DATA <= x"1E";
when x"5A0" => DATA <= x"89";
when x"5A1" => DATA <= x"1F";
when x"5A2" => DATA <= x"01";
when x"5A3" => DATA <= x"86";
when x"5A4" => DATA <= x"FF";
when x"5A5" => DATA <= x"B7";
when x"5A6" => DATA <= x"FF";
when x"5A7" => DATA <= x"94";
when x"5A8" => DATA <= x"8D";
when x"5A9" => DATA <= x"9F";
when x"5AA" => DATA <= x"1C";
when x"5AB" => DATA <= x"BF";
when x"5AC" => DATA <= x"A6";
when x"5AD" => DATA <= x"E0";
when x"5AE" => DATA <= x"27";
when x"5AF" => DATA <= x"66";
when x"5B0" => DATA <= x"81";
when x"5B1" => DATA <= x"02";
when x"5B2" => DATA <= x"25";
when x"5B3" => DATA <= x"55";
when x"5B4" => DATA <= x"27";
when x"5B5" => DATA <= x"43";
when x"5B6" => DATA <= x"81";
when x"5B7" => DATA <= x"04";
when x"5B8" => DATA <= x"25";
when x"5B9" => DATA <= x"2F";
when x"5BA" => DATA <= x"27";
when x"5BB" => DATA <= x"67";
when x"5BC" => DATA <= x"5F";
when x"5BD" => DATA <= x"81";
when x"5BE" => DATA <= x"07";
when x"5BF" => DATA <= x"25";
when x"5C0" => DATA <= x"11";
when x"5C1" => DATA <= x"26";
when x"5C2" => DATA <= x"63";
when x"5C3" => DATA <= x"B6";
when x"5C4" => DATA <= x"FE";
when x"5C5" => DATA <= x"E4";
when x"5C6" => DATA <= x"2A";
when x"5C7" => DATA <= x"FB";
when x"5C8" => DATA <= x"B6";
when x"5C9" => DATA <= x"FE";
when x"5CA" => DATA <= x"E5";
when x"5CB" => DATA <= x"A7";
when x"5CC" => DATA <= x"80";
when x"5CD" => DATA <= x"5A";
when x"5CE" => DATA <= x"26";
when x"5CF" => DATA <= x"F3";
when x"5D0" => DATA <= x"20";
when x"5D1" => DATA <= x"54";
when x"5D2" => DATA <= x"B6";
when x"5D3" => DATA <= x"FE";
when x"5D4" => DATA <= x"E4";
when x"5D5" => DATA <= x"2A";
when x"5D6" => DATA <= x"FB";
when x"5D7" => DATA <= x"A6";
when x"5D8" => DATA <= x"80";
when x"5D9" => DATA <= x"B7";
when x"5DA" => DATA <= x"FE";
when x"5DB" => DATA <= x"E5";
when x"5DC" => DATA <= x"5A";
when x"5DD" => DATA <= x"26";
when x"5DE" => DATA <= x"F3";
when x"5DF" => DATA <= x"B6";
when x"5E0" => DATA <= x"FE";
when x"5E1" => DATA <= x"E4";
when x"5E2" => DATA <= x"2A";
when x"5E3" => DATA <= x"FB";
when x"5E4" => DATA <= x"B7";
when x"5E5" => DATA <= x"FE";
when x"5E6" => DATA <= x"E5";
when x"5E7" => DATA <= x"20";
when x"5E8" => DATA <= x"3D";
when x"5E9" => DATA <= x"13";
when x"5EA" => DATA <= x"B6";
when x"5EB" => DATA <= x"FF";
when x"5EC" => DATA <= x"94";
when x"5ED" => DATA <= x"27";
when x"5EE" => DATA <= x"37";
when x"5EF" => DATA <= x"B6";
when x"5F0" => DATA <= x"FE";
when x"5F1" => DATA <= x"E5";
when x"5F2" => DATA <= x"F6";
when x"5F3" => DATA <= x"FE";
when x"5F4" => DATA <= x"E5";
when x"5F5" => DATA <= x"ED";
when x"5F6" => DATA <= x"81";
when x"5F7" => DATA <= x"20";
when x"5F8" => DATA <= x"F0";
when x"5F9" => DATA <= x"13";
when x"5FA" => DATA <= x"B6";
when x"5FB" => DATA <= x"FF";
when x"5FC" => DATA <= x"94";
when x"5FD" => DATA <= x"27";
when x"5FE" => DATA <= x"27";
when x"5FF" => DATA <= x"EC";
when x"600" => DATA <= x"81";
when x"601" => DATA <= x"B7";
when x"602" => DATA <= x"FE";
when x"603" => DATA <= x"E5";
when x"604" => DATA <= x"F7";
when x"605" => DATA <= x"FE";
when x"606" => DATA <= x"E5";
when x"607" => DATA <= x"20";
when x"608" => DATA <= x"F0";
when x"609" => DATA <= x"13";
when x"60A" => DATA <= x"B6";
when x"60B" => DATA <= x"FF";
when x"60C" => DATA <= x"94";
when x"60D" => DATA <= x"27";
when x"60E" => DATA <= x"17";
when x"60F" => DATA <= x"B6";
when x"610" => DATA <= x"FE";
when x"611" => DATA <= x"E5";
when x"612" => DATA <= x"A7";
when x"613" => DATA <= x"80";
when x"614" => DATA <= x"20";
when x"615" => DATA <= x"F3";
when x"616" => DATA <= x"13";
when x"617" => DATA <= x"B6";
when x"618" => DATA <= x"FF";
when x"619" => DATA <= x"94";
when x"61A" => DATA <= x"27";
when x"61B" => DATA <= x"0A";
when x"61C" => DATA <= x"A6";
when x"61D" => DATA <= x"80";
when x"61E" => DATA <= x"B7";
when x"61F" => DATA <= x"FE";
when x"620" => DATA <= x"E5";
when x"621" => DATA <= x"20";
when x"622" => DATA <= x"F3";
when x"623" => DATA <= x"BF";
when x"624" => DATA <= x"FF";
when x"625" => DATA <= x"8C";
when x"626" => DATA <= x"35";
when x"627" => DATA <= x"16";
when x"628" => DATA <= x"3B";
when x"629" => DATA <= x"11";
when x"62A" => DATA <= x"A3";
when x"62B" => DATA <= x"6A";
when x"62C" => DATA <= x"26";
when x"62D" => DATA <= x"02";
when x"62E" => DATA <= x"32";
when x"62F" => DATA <= x"62";
when x"630" => DATA <= x"32";
when x"631" => DATA <= x"6A";
when x"632" => DATA <= x"35";
when x"633" => DATA <= x"10";
when x"634" => DATA <= x"BF";
when x"635" => DATA <= x"FF";
when x"636" => DATA <= x"82";
when x"637" => DATA <= x"1C";
when x"638" => DATA <= x"00";
when x"639" => DATA <= x"6E";
when x"63A" => DATA <= x"9F";
when x"63B" => DATA <= x"FF";
when x"63C" => DATA <= x"FA";
when x"63D" => DATA <= x"FF";
when x"63E" => DATA <= x"FF";
when x"63F" => DATA <= x"FF";
when x"640" => DATA <= x"FF";
when x"641" => DATA <= x"FF";
when x"642" => DATA <= x"FF";
when x"643" => DATA <= x"FF";
when x"644" => DATA <= x"FF";
when x"645" => DATA <= x"FF";
when x"646" => DATA <= x"FF";
when x"647" => DATA <= x"FF";
when x"648" => DATA <= x"FF";
when x"649" => DATA <= x"FF";
when x"64A" => DATA <= x"FF";
when x"64B" => DATA <= x"FF";
when x"64C" => DATA <= x"FF";
when x"64D" => DATA <= x"FF";
when x"64E" => DATA <= x"FF";
when x"64F" => DATA <= x"FF";
when x"650" => DATA <= x"FF";
when x"651" => DATA <= x"FF";
when x"652" => DATA <= x"FF";
when x"653" => DATA <= x"FF";
when x"654" => DATA <= x"FF";
when x"655" => DATA <= x"FF";
when x"656" => DATA <= x"FF";
when x"657" => DATA <= x"FF";
when x"658" => DATA <= x"FF";
when x"659" => DATA <= x"FF";
when x"65A" => DATA <= x"FF";
when x"65B" => DATA <= x"FF";
when x"65C" => DATA <= x"FF";
when x"65D" => DATA <= x"FF";
when x"65E" => DATA <= x"FF";
when x"65F" => DATA <= x"FF";
when x"660" => DATA <= x"FF";
when x"661" => DATA <= x"FF";
when x"662" => DATA <= x"FF";
when x"663" => DATA <= x"FF";
when x"664" => DATA <= x"FF";
when x"665" => DATA <= x"FF";
when x"666" => DATA <= x"FF";
when x"667" => DATA <= x"FF";
when x"668" => DATA <= x"FF";
when x"669" => DATA <= x"FF";
when x"66A" => DATA <= x"FF";
when x"66B" => DATA <= x"FF";
when x"66C" => DATA <= x"FF";
when x"66D" => DATA <= x"FF";
when x"66E" => DATA <= x"FF";
when x"66F" => DATA <= x"FF";
when x"670" => DATA <= x"FF";
when x"671" => DATA <= x"FF";
when x"672" => DATA <= x"FF";
when x"673" => DATA <= x"FF";
when x"674" => DATA <= x"FF";
when x"675" => DATA <= x"FF";
when x"676" => DATA <= x"FF";
when x"677" => DATA <= x"FF";
when x"678" => DATA <= x"FF";
when x"679" => DATA <= x"FF";
when x"67A" => DATA <= x"FF";
when x"67B" => DATA <= x"FF";
when x"67C" => DATA <= x"FF";
when x"67D" => DATA <= x"FF";
when x"67E" => DATA <= x"FF";
when x"67F" => DATA <= x"FF";
when x"680" => DATA <= x"FF";
when x"681" => DATA <= x"FF";
when x"682" => DATA <= x"FF";
when x"683" => DATA <= x"FF";
when x"684" => DATA <= x"FF";
when x"685" => DATA <= x"FF";
when x"686" => DATA <= x"FF";
when x"687" => DATA <= x"FF";
when x"688" => DATA <= x"FF";
when x"689" => DATA <= x"FF";
when x"68A" => DATA <= x"FF";
when x"68B" => DATA <= x"FF";
when x"68C" => DATA <= x"FF";
when x"68D" => DATA <= x"FF";
when x"68E" => DATA <= x"FF";
when x"68F" => DATA <= x"FF";
when x"690" => DATA <= x"FF";
when x"691" => DATA <= x"FF";
when x"692" => DATA <= x"FF";
when x"693" => DATA <= x"FF";
when x"694" => DATA <= x"FF";
when x"695" => DATA <= x"FF";
when x"696" => DATA <= x"FF";
when x"697" => DATA <= x"FF";
when x"698" => DATA <= x"FF";
when x"699" => DATA <= x"FF";
when x"69A" => DATA <= x"FF";
when x"69B" => DATA <= x"FF";
when x"69C" => DATA <= x"FF";
when x"69D" => DATA <= x"FF";
when x"69E" => DATA <= x"FF";
when x"69F" => DATA <= x"FF";
when x"6A0" => DATA <= x"FF";
when x"6A1" => DATA <= x"FF";
when x"6A2" => DATA <= x"FF";
when x"6A3" => DATA <= x"FF";
when x"6A4" => DATA <= x"FF";
when x"6A5" => DATA <= x"FF";
when x"6A6" => DATA <= x"FF";
when x"6A7" => DATA <= x"FF";
when x"6A8" => DATA <= x"FF";
when x"6A9" => DATA <= x"FF";
when x"6AA" => DATA <= x"FF";
when x"6AB" => DATA <= x"FF";
when x"6AC" => DATA <= x"FF";
when x"6AD" => DATA <= x"FF";
when x"6AE" => DATA <= x"FF";
when x"6AF" => DATA <= x"FF";
when x"6B0" => DATA <= x"FF";
when x"6B1" => DATA <= x"FF";
when x"6B2" => DATA <= x"FF";
when x"6B3" => DATA <= x"FF";
when x"6B4" => DATA <= x"FF";
when x"6B5" => DATA <= x"FF";
when x"6B6" => DATA <= x"FF";
when x"6B7" => DATA <= x"FF";
when x"6B8" => DATA <= x"FF";
when x"6B9" => DATA <= x"FF";
when x"6BA" => DATA <= x"FF";
when x"6BB" => DATA <= x"FF";
when x"6BC" => DATA <= x"FF";
when x"6BD" => DATA <= x"FF";
when x"6BE" => DATA <= x"FF";
when x"6BF" => DATA <= x"FF";
when x"6C0" => DATA <= x"FF";
when x"6C1" => DATA <= x"FF";
when x"6C2" => DATA <= x"FF";
when x"6C3" => DATA <= x"FF";
when x"6C4" => DATA <= x"FF";
when x"6C5" => DATA <= x"FF";
when x"6C6" => DATA <= x"FF";
when x"6C7" => DATA <= x"FF";
when x"6C8" => DATA <= x"FF";
when x"6C9" => DATA <= x"FF";
when x"6CA" => DATA <= x"FF";
when x"6CB" => DATA <= x"FF";
when x"6CC" => DATA <= x"FF";
when x"6CD" => DATA <= x"FF";
when x"6CE" => DATA <= x"FF";
when x"6CF" => DATA <= x"FF";
when x"6D0" => DATA <= x"FF";
when x"6D1" => DATA <= x"FF";
when x"6D2" => DATA <= x"FF";
when x"6D3" => DATA <= x"FF";
when x"6D4" => DATA <= x"FF";
when x"6D5" => DATA <= x"FF";
when x"6D6" => DATA <= x"FF";
when x"6D7" => DATA <= x"FF";
when x"6D8" => DATA <= x"FF";
when x"6D9" => DATA <= x"FF";
when x"6DA" => DATA <= x"FF";
when x"6DB" => DATA <= x"FF";
when x"6DC" => DATA <= x"FF";
when x"6DD" => DATA <= x"FF";
when x"6DE" => DATA <= x"FF";
when x"6DF" => DATA <= x"FF";
when x"6E0" => DATA <= x"00";
when x"6E1" => DATA <= x"00";
when x"6E2" => DATA <= x"00";
when x"6E3" => DATA <= x"00";
when x"6E4" => DATA <= x"00";
when x"6E5" => DATA <= x"00";
when x"6E6" => DATA <= x"00";
when x"6E7" => DATA <= x"00";
when x"6E8" => DATA <= x"FF";
when x"6E9" => DATA <= x"FF";
when x"6EA" => DATA <= x"FF";
when x"6EB" => DATA <= x"FF";
when x"6EC" => DATA <= x"FF";
when x"6ED" => DATA <= x"FF";
when x"6EE" => DATA <= x"FF";
when x"6EF" => DATA <= x"FF";
when x"6F0" => DATA <= x"FE";
when x"6F1" => DATA <= x"28";
when x"6F2" => DATA <= x"FE";
when x"6F3" => DATA <= x"28";
when x"6F4" => DATA <= x"FE";
when x"6F5" => DATA <= x"28";
when x"6F6" => DATA <= x"FD";
when x"6F7" => DATA <= x"00";
when x"6F8" => DATA <= x"FE";
when x"6F9" => DATA <= x"28";
when x"6FA" => DATA <= x"FE";
when x"6FB" => DATA <= x"29";
when x"6FC" => DATA <= x"FE";
when x"6FD" => DATA <= x"28";
when x"6FE" => DATA <= x"F8";
when x"6FF" => DATA <= x"2C";
when x"700" => DATA <= x"00";
when x"701" => DATA <= x"00";
when x"702" => DATA <= x"00";
when x"703" => DATA <= x"00";
when x"704" => DATA <= x"00";
when x"705" => DATA <= x"00";
when x"706" => DATA <= x"00";
when x"707" => DATA <= x"00";
when x"708" => DATA <= x"00";
when x"709" => DATA <= x"00";
when x"70A" => DATA <= x"00";
when x"70B" => DATA <= x"00";
when x"70C" => DATA <= x"00";
when x"70D" => DATA <= x"00";
when x"70E" => DATA <= x"00";
when x"70F" => DATA <= x"00";
when x"710" => DATA <= x"00";
when x"711" => DATA <= x"00";
when x"712" => DATA <= x"00";
when x"713" => DATA <= x"00";
when x"714" => DATA <= x"00";
when x"715" => DATA <= x"00";
when x"716" => DATA <= x"00";
when x"717" => DATA <= x"00";
when x"718" => DATA <= x"00";
when x"719" => DATA <= x"00";
when x"71A" => DATA <= x"00";
when x"71B" => DATA <= x"00";
when x"71C" => DATA <= x"00";
when x"71D" => DATA <= x"00";
when x"71E" => DATA <= x"00";
when x"71F" => DATA <= x"00";
when x"720" => DATA <= x"00";
when x"721" => DATA <= x"00";
when x"722" => DATA <= x"00";
when x"723" => DATA <= x"00";
when x"724" => DATA <= x"00";
when x"725" => DATA <= x"00";
when x"726" => DATA <= x"00";
when x"727" => DATA <= x"00";
when x"728" => DATA <= x"00";
when x"729" => DATA <= x"00";
when x"72A" => DATA <= x"00";
when x"72B" => DATA <= x"00";
when x"72C" => DATA <= x"00";
when x"72D" => DATA <= x"00";
when x"72E" => DATA <= x"00";
when x"72F" => DATA <= x"00";
when x"730" => DATA <= x"00";
when x"731" => DATA <= x"00";
when x"732" => DATA <= x"00";
when x"733" => DATA <= x"00";
when x"734" => DATA <= x"00";
when x"735" => DATA <= x"00";
when x"736" => DATA <= x"00";
when x"737" => DATA <= x"00";
when x"738" => DATA <= x"00";
when x"739" => DATA <= x"00";
when x"73A" => DATA <= x"00";
when x"73B" => DATA <= x"00";
when x"73C" => DATA <= x"00";
when x"73D" => DATA <= x"00";
when x"73E" => DATA <= x"00";
when x"73F" => DATA <= x"00";
when x"740" => DATA <= x"00";
when x"741" => DATA <= x"00";
when x"742" => DATA <= x"00";
when x"743" => DATA <= x"00";
when x"744" => DATA <= x"00";
when x"745" => DATA <= x"00";
when x"746" => DATA <= x"00";
when x"747" => DATA <= x"00";
when x"748" => DATA <= x"00";
when x"749" => DATA <= x"00";
when x"74A" => DATA <= x"00";
when x"74B" => DATA <= x"00";
when x"74C" => DATA <= x"00";
when x"74D" => DATA <= x"00";
when x"74E" => DATA <= x"00";
when x"74F" => DATA <= x"00";
when x"750" => DATA <= x"00";
when x"751" => DATA <= x"00";
when x"752" => DATA <= x"00";
when x"753" => DATA <= x"00";
when x"754" => DATA <= x"00";
when x"755" => DATA <= x"00";
when x"756" => DATA <= x"00";
when x"757" => DATA <= x"00";
when x"758" => DATA <= x"00";
when x"759" => DATA <= x"00";
when x"75A" => DATA <= x"00";
when x"75B" => DATA <= x"00";
when x"75C" => DATA <= x"00";
when x"75D" => DATA <= x"00";
when x"75E" => DATA <= x"00";
when x"75F" => DATA <= x"00";
when x"760" => DATA <= x"00";
when x"761" => DATA <= x"00";
when x"762" => DATA <= x"00";
when x"763" => DATA <= x"00";
when x"764" => DATA <= x"00";
when x"765" => DATA <= x"00";
when x"766" => DATA <= x"00";
when x"767" => DATA <= x"00";
when x"768" => DATA <= x"00";
when x"769" => DATA <= x"00";
when x"76A" => DATA <= x"00";
when x"76B" => DATA <= x"00";
when x"76C" => DATA <= x"00";
when x"76D" => DATA <= x"00";
when x"76E" => DATA <= x"00";
when x"76F" => DATA <= x"00";
when x"770" => DATA <= x"00";
when x"771" => DATA <= x"00";
when x"772" => DATA <= x"00";
when x"773" => DATA <= x"00";
when x"774" => DATA <= x"00";
when x"775" => DATA <= x"00";
when x"776" => DATA <= x"00";
when x"777" => DATA <= x"00";
when x"778" => DATA <= x"00";
when x"779" => DATA <= x"00";
when x"77A" => DATA <= x"00";
when x"77B" => DATA <= x"00";
when x"77C" => DATA <= x"00";
when x"77D" => DATA <= x"00";
when x"77E" => DATA <= x"00";
when x"77F" => DATA <= x"00";
when x"780" => DATA <= x"00";
when x"781" => DATA <= x"00";
when x"782" => DATA <= x"F8";
when x"783" => DATA <= x"16";
when x"784" => DATA <= x"F8";
when x"785" => DATA <= x"AD";
when x"786" => DATA <= x"F8";
when x"787" => DATA <= x"16";
when x"788" => DATA <= x"00";
when x"789" => DATA <= x"00";
when x"78A" => DATA <= x"F8";
when x"78B" => DATA <= x"00";
when x"78C" => DATA <= x"FF";
when x"78D" => DATA <= x"B9";
when x"78E" => DATA <= x"FF";
when x"78F" => DATA <= x"B9";
when x"790" => DATA <= x"FF";
when x"791" => DATA <= x"B9";
when x"792" => DATA <= x"00";
when x"793" => DATA <= x"00";
when x"794" => DATA <= x"00";
when x"795" => DATA <= x"7E";
when x"796" => DATA <= x"FA";
when x"797" => DATA <= x"98";
when x"798" => DATA <= x"7E";
when x"799" => DATA <= x"F8";
when x"79A" => DATA <= x"2C";
when x"79B" => DATA <= x"7E";
when x"79C" => DATA <= x"F9";
when x"79D" => DATA <= x"39";
when x"79E" => DATA <= x"7E";
when x"79F" => DATA <= x"FF";
when x"7A0" => DATA <= x"EE";
when x"7A1" => DATA <= x"7E";
when x"7A2" => DATA <= x"F9";
when x"7A3" => DATA <= x"42";
when x"7A4" => DATA <= x"7E";
when x"7A5" => DATA <= x"FA";
when x"7A6" => DATA <= x"98";
when x"7A7" => DATA <= x"7E";
when x"7A8" => DATA <= x"F8";
when x"7A9" => DATA <= x"6E";
when x"7AA" => DATA <= x"7E";
when x"7AB" => DATA <= x"F9";
when x"7AC" => DATA <= x"18";
when x"7AD" => DATA <= x"7E";
when x"7AE" => DATA <= x"F9";
when x"7AF" => DATA <= x"0E";
when x"7B0" => DATA <= x"7E";
when x"7B1" => DATA <= x"FE";
when x"7B2" => DATA <= x"28";
when x"7B3" => DATA <= x"7E";
when x"7B4" => DATA <= x"F9";
when x"7B5" => DATA <= x"2F";
when x"7B6" => DATA <= x"7E";
when x"7B7" => DATA <= x"FA";
when x"7B8" => DATA <= x"98";
when x"7B9" => DATA <= x"7E";
when x"7BA" => DATA <= x"F8";
when x"7BB" => DATA <= x"6E";
when x"7BC" => DATA <= x"7E";
when x"7BD" => DATA <= x"FE";
when x"7BE" => DATA <= x"32";
when x"7BF" => DATA <= x"7E";
when x"7C0" => DATA <= x"F8";
when x"7C1" => DATA <= x"D0";
when x"7C2" => DATA <= x"7E";
when x"7C3" => DATA <= x"FA";
when x"7C4" => DATA <= x"98";
when x"7C5" => DATA <= x"7E";
when x"7C6" => DATA <= x"F9";
when x"7C7" => DATA <= x"39";
when x"7C8" => DATA <= x"7E";
when x"7C9" => DATA <= x"FA";
when x"7CA" => DATA <= x"98";
when x"7CB" => DATA <= x"7E";
when x"7CC" => DATA <= x"FA";
when x"7CD" => DATA <= x"98";
when x"7CE" => DATA <= x"7E";
when x"7CF" => DATA <= x"FC";
when x"7D0" => DATA <= x"2C";
when x"7D1" => DATA <= x"7E";
when x"7D2" => DATA <= x"FC";
when x"7D3" => DATA <= x"76";
when x"7D4" => DATA <= x"7E";
when x"7D5" => DATA <= x"FC";
when x"7D6" => DATA <= x"16";
when x"7D7" => DATA <= x"7E";
when x"7D8" => DATA <= x"FC";
when x"7D9" => DATA <= x"07";
when x"7DA" => DATA <= x"7E";
when x"7DB" => DATA <= x"FB";
when x"7DC" => DATA <= x"E9";
when x"7DD" => DATA <= x"7E";
when x"7DE" => DATA <= x"FC";
when x"7DF" => DATA <= x"4C";
when x"7E0" => DATA <= x"7E";
when x"7E1" => DATA <= x"FA";
when x"7E2" => DATA <= x"C0";
when x"7E3" => DATA <= x"81";
when x"7E4" => DATA <= x"0D";
when x"7E5" => DATA <= x"26";
when x"7E6" => DATA <= x"07";
when x"7E7" => DATA <= x"86";
when x"7E8" => DATA <= x"0A";
when x"7E9" => DATA <= x"BD";
when x"7EA" => DATA <= x"FF";
when x"7EB" => DATA <= x"EE";
when x"7EC" => DATA <= x"86";
when x"7ED" => DATA <= x"0D";
when x"7EE" => DATA <= x"7E";
when x"7EF" => DATA <= x"FC";
when x"7F0" => DATA <= x"E0";
when x"7F1" => DATA <= x"7E";
when x"7F2" => DATA <= x"FB";
when x"7F3" => DATA <= x"43";
when x"7F4" => DATA <= x"7E";
when x"7F5" => DATA <= x"FA";
when x"7F6" => DATA <= x"D0";
when x"7F7" => DATA <= x"7E";
when x"7F8" => DATA <= x"F9";
when x"7F9" => DATA <= x"84";
when x"7FA" => DATA <= x"F8";
when x"7FB" => DATA <= x"AD";
when x"7FC" => DATA <= x"FA";
when x"7FD" => DATA <= x"98";
when x"7FE" => DATA <= x"F8";
when x"7FF" => DATA <= x"2C";
when others => DATA <= (others => '0');
end case;
end process;
end RTL;
| gpl-3.0 | 22dea8974239038418d9d7942ef382c8 | 0.358731 | 2.974517 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-xilinx-kc705/testbench.vhd | 1 | 15,921 | -----------------------------------------------------------------------------
-- LEON Demonstration design test bench
-- Copyright (C) 2013 Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use work.debug.all;
use work.config.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
USE_MIG_INTERFACE_MODEL : boolean := false
);
end;
architecture behav of testbench is
-- DDR3 Simulation parameters
constant SIM_BYPASS_INIT_CAL : string := "FAST";
-- # = "OFF" - Complete memory init &
-- calibration sequence
-- # = "SKIP" - Not supported
-- # = "FAST" - Complete memory init & use
-- abbreviated calib sequence
constant SIMULATION : string := "TRUE";
-- Should be TRUE during design simulations and
-- FALSE during implementations
constant promfile : string := "prom.srec"; -- rom contents
constant ramfile : string := "ram.srec"; -- ram contents
signal clk : std_logic := '0';
signal Rst : std_logic := '0';
signal address : std_logic_vector(25 downto 0);
signal data : std_logic_vector(15 downto 0);
signal button : std_logic_vector(3 downto 0) := "0000";
signal genio : std_logic_vector(59 downto 0);
signal romsn : std_logic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal adv : std_logic;
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal txd1 , rxd1 , dsurx : std_logic;
signal txd2 , rxd2 , dsutx : std_logic;
signal ctsn1 , rtsn1 , dsuctsn : std_ulogic;
signal ctsn2 , rtsn2 , dsurtsn : std_ulogic;
signal phy_gtxclk : std_logic := '0';
signal phy_txer : std_ulogic;
signal phy_txd : std_logic_vector(7 downto 0);
signal phy_txctl_txen : std_ulogic;
signal phy_txclk : std_ulogic;
signal phy_rxer : std_ulogic;
signal phy_rxd : std_logic_vector(7 downto 0);
signal phy_rxctl_rxdv : std_ulogic;
signal phy_rxclk : std_ulogic;
signal phy_reset : std_ulogic;
signal phy_mdio : std_logic;
signal phy_mdc : std_ulogic;
signal phy_crs : std_ulogic;
signal phy_col : std_ulogic;
signal phy_int : std_ulogic;
signal phy_rxdl : std_logic_vector(7 downto 0);
signal phy_txdl : std_logic_vector(7 downto 0);
signal clk27 : std_ulogic := '0';
signal clk200p : std_ulogic := '0';
signal clk200n : std_ulogic := '1';
signal clk33 : std_ulogic := '0';
signal clkethp : std_ulogic := '0';
signal clkethn : std_ulogic := '1';
signal txp1 : std_logic;
signal txn : std_logic;
signal rxp : std_logic := '1';
signal rxn : std_logic := '0';
signal iic_scl : std_ulogic;
signal iic_sda : std_ulogic;
signal ddc_scl : std_ulogic;
signal ddc_sda : std_ulogic;
signal dvi_iic_scl : std_logic;
signal dvi_iic_sda : std_logic;
signal tft_lcd_data : std_logic_vector(11 downto 0);
signal tft_lcd_clk_p : std_ulogic;
signal tft_lcd_clk_n : std_ulogic;
signal tft_lcd_hsync : std_ulogic;
signal tft_lcd_vsync : std_ulogic;
signal tft_lcd_de : std_ulogic;
signal tft_lcd_reset_b : std_ulogic;
-- DDR3 memory
signal ddr3_dq : std_logic_vector(63 downto 0);
signal ddr3_dqs_p : std_logic_vector(7 downto 0);
signal ddr3_dqs_n : std_logic_vector(7 downto 0);
signal ddr3_addr : std_logic_vector(13 downto 0);
signal ddr3_ba : std_logic_vector(2 downto 0);
signal ddr3_ras_n : std_logic;
signal ddr3_cas_n : std_logic;
signal ddr3_we_n : std_logic;
signal ddr3_reset_n : std_logic;
signal ddr3_ck_p : std_logic_vector(0 downto 0);
signal ddr3_ck_n : std_logic_vector(0 downto 0);
signal ddr3_cke : std_logic_vector(0 downto 0);
signal ddr3_cs_n : std_logic_vector(0 downto 0);
signal ddr3_dm : std_logic_vector(7 downto 0);
signal ddr3_odt : std_logic_vector(0 downto 0);
-- SPI flash
signal spi_sel_n : std_ulogic;
signal spi_clk : std_ulogic;
signal spi_mosi : std_ulogic;
signal dsurst : std_ulogic;
signal errorn : std_logic;
signal switch : std_logic_vector(3 downto 0); -- I/O port
signal led : std_logic_vector(6 downto 0); -- I/O port
constant lresp : boolean := false;
signal tdqs_n : std_logic;
signal gmii_tx_clk : std_logic;
signal gmii_rx_clk : std_logic;
signal gmii_txd : std_logic_vector(7 downto 0);
signal gmii_tx_en : std_logic;
signal gmii_tx_er : std_logic;
signal gmii_rxd : std_logic_vector(7 downto 0);
signal gmii_rx_dv : std_logic;
signal gmii_rx_er : std_logic;
begin
-- clock and reset
clk200p <= not clk200p after 2.5 ns;
clk200n <= not clk200n after 2.5 ns;
clkethp <= not clkethp after 4 ns;
clkethn <= not clkethp after 4 ns;
rst <= not dsurst;
rxd1 <= 'H'; ctsn1 <= '0';
rxd2 <= 'H'; ctsn2 <= '0';
button <= "0000";
switch(2 downto 0) <= "000";
cpu : entity work.leon3mp
generic map (
fabtech => fabtech,
memtech => memtech,
padtech => padtech,
clktech => clktech,
disas => disas,
dbguart => dbguart,
pclow => pclow,
SIM_BYPASS_INIT_CAL => SIM_BYPASS_INIT_CAL,
SIMULATION => SIMULATION,
USE_MIG_INTERFACE_MODEL => USE_MIG_INTERFACE_MODEL
)
port map (
reset => rst,
clk200p => clk200p,
clk200n => clk200n,
address => address,
data => data,
oen => oen,
writen => writen,
romsn => romsn,
adv => adv,
ddr3_dq => ddr3_dq,
ddr3_dqs_p => ddr3_dqs_p,
ddr3_dqs_n => ddr3_dqs_n,
ddr3_addr => ddr3_addr,
ddr3_ba => ddr3_ba,
ddr3_ras_n => ddr3_ras_n,
ddr3_cas_n => ddr3_cas_n,
ddr3_we_n => ddr3_we_n,
ddr3_reset_n => ddr3_reset_n,
ddr3_ck_p => ddr3_ck_p,
ddr3_ck_n => ddr3_ck_n,
ddr3_cke => ddr3_cke,
ddr3_cs_n => ddr3_cs_n,
ddr3_dm => ddr3_dm,
ddr3_odt => ddr3_odt,
dsurx => dsurx,
dsutx => dsutx,
dsuctsn => dsuctsn,
dsurtsn => dsurtsn,
button => button,
switch => switch,
led => led,
iic_scl => iic_scl,
iic_sda => iic_sda,
gtrefclk_p => clkethp,
gtrefclk_n => clkethn,
phy_gtxclk => phy_gtxclk,
--phy_txer => phy_txer,
phy_txd => phy_txd(3 downto 0),
phy_txctl_txen => phy_txctl_txen,
--phy_txclk => phy_txclk,
--phy_rxer => phy_rxer,
phy_rxd => phy_rxd(3 downto 0)'delayed(2 ns),
phy_rxctl_rxdv => phy_rxctl_rxdv'delayed(2 ns),
phy_rxclk => phy_rxclk,
phy_reset => phy_reset,
phy_mdio => phy_mdio,
phy_mdc => phy_mdc,
phy_int => phy_int
);
prom0 : for i in 0 to 1 generate
sr0 : sram generic map (index => i+4, abits => 22, fname => promfile)
port map (address(21 downto 0), data(15-i*8 downto 8-i*8), romsn,
writen, oen);
end generate;
-- Memory Models instantiations
gen_mem_model : if (USE_MIG_INTERFACE_MODEL /= true) generate
ddr3mem : if (CFG_MIG_7SERIES = 1) generate
u1 : ddr3ram
generic map (
width => 64,
abits => 14,
colbits => 10,
rowbits => 10,
implbanks => 1,
fname => ramfile,
lddelay => (0 ns),
ldguard => 1,
speedbin => 9, --DDR3-1600K
density => 3,
pagesize => 1,
changeendian => 8)
port map (
ck => ddr3_ck_p(0),
ckn => ddr3_ck_n(0),
cke => ddr3_cke(0),
csn => ddr3_cs_n(0),
odt => ddr3_odt(0),
rasn => ddr3_ras_n,
casn => ddr3_cas_n,
wen => ddr3_we_n,
dm => ddr3_dm,
ba => ddr3_ba,
a => ddr3_addr,
resetn => ddr3_reset_n,
dq => ddr3_dq,
dqs => ddr3_dqs_p,
dqsn => ddr3_dqs_n,
doload => led(3)
);
end generate ddr3mem;
end generate gen_mem_model;
mig_mem_model : if (USE_MIG_INTERFACE_MODEL = true) generate
ddr3_dq <= (others => 'Z');
ddr3_dqs_p <= (others => 'Z');
ddr3_dqs_n <= (others => 'Z');
end generate mig_mem_model;
errorn <= led(1);
errorn <= 'H'; -- ERROR pull-up
phy0 : if (CFG_GRETH = 1) generate
phy_mdio <= 'H';
phy_int <= '0';
p0: phy
generic map (
address => 7,
extended_regs => 1,
aneg => 1,
base100_t4 => 1,
base100_x_fd => 1,
base100_x_hd => 1,
fd_10 => 1,
hd_10 => 1,
base100_t2_fd => 1,
base100_t2_hd => 1,
base1000_x_fd => 1,
base1000_x_hd => 1,
base1000_t_fd => 1,
base1000_t_hd => 1,
rmii => 0,
rgmii => 1
)
port map(phy_reset, phy_mdio, phy_txclk, phy_rxclk, phy_rxd,
phy_rxctl_rxdv, phy_rxer, phy_col, phy_crs, phy_txd,
phy_txctl_txen, phy_txer, phy_mdc, phy_gtxclk);
end generate;
iuerr : process
begin
wait for 210 us; -- This is for proper DDR3 behaviour durign init phase not needed durin simulation
wait on led(3); -- DDR3 Memory Init ready
wait for 5000 ns;
if to_x01(errorn) = '1' then wait on errorn; end if;
assert (to_x01(errorn) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ; -- this should be a failure
end process;
data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 320 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
switch(3) <= '0';
wait for 2500 ns;
wait for 210 us; -- This is for proper DDR3 behaviour durign init phase not needed durin simulation
dsurst <= '1';
switch(3) <= '1';
if (USE_MIG_INTERFACE_MODEL /= true) then
wait on led(3); -- Wait for DDR3 Memory Init ready
end if;
report "Start DSU transfer";
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- Reads from memory and DSU register to mimic GRMON during simulation
l1 : loop
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#04#, txp);
rxi(dsurx, w32, txp, lresp);
--report "DSU read memory " & tost(w32);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
rxi(dsurx, w32, txp, lresp);
--report "DSU Break and Single Step register" & tost(w32);
end loop l1;
wait;
-- ** This is only kept for reference --
-- do test read and writes to DDR3 to check status
-- Write
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#01#, 16#23#, 16#45#, 16#67#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#04#, txp);
txa(dsutx, 16#89#, 16#AB#, 16#CD#, 16#EF#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#08#, txp);
txa(dsutx, 16#08#, 16#19#, 16#2A#, 16#3B#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#0C#, txp);
txa(dsutx, 16#4C#, 16#5D#, 16#6E#, 16#7F#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#04#, txp);
rxi(dsurx, w32, txp, lresp);
report "* Read " & tost(w32);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#08#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#0C#, txp);
rxi(dsurx, w32, txp, lresp);
wait;
-- Register 0x90000000 (DSU Control Register)
-- Data 0x0000202e (b0010 0000 0010 1110)
-- [0] - Trace Enable
-- [1] - Break On Error
-- [2] - Break on IU watchpoint
-- [3] - Break on s/w break points
--
-- [4] - (Break on trap)
-- [5] - Break on error traps
-- [6] - Debug mode (Read mode only)
-- [7] - DSUEN (read mode)
--
-- [8] - DSUBRE (read mode)
-- [9] - Processor mode error (clears error)
-- [10] - processor halt (returns 1 if processor halted)
-- [11] - power down mode (return 1 if processor in power down mode)
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#80#, 16#02#, txp);
wait;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#2e#, txp);
wait for 25000 ns;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0D#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#70#, 16#11#, 16#78#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#0D#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#00#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
wait;
end;
begin
dsuctsn <= '0';
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
| gpl-3.0 | edffb569b65a6aa0da7090db741548d8 | 0.531562 | 3.311356 | false | false | false | false |
pwsoft/fpga_examples | rtl/general/gen_counter_tb.vhd | 1 | 3,400 | -- -----------------------------------------------------------------------
--
-- Syntiac's generic VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2010 by Peter Wendrich ([email protected])
-- http://www.syntiac.com/fpga64.html
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
--
-- gen_counter_tb.vhd
--
-- -----------------------------------------------------------------------
--
-- Testbench for up/down counter
--
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- -----------------------------------------------------------------------
entity gen_counter_tb is
end entity;
-- -----------------------------------------------------------------------
architecture rtl of gen_counter_tb is
signal clk : std_logic := '0';
signal stop : std_logic := '0';
signal reset : std_logic := '0';
signal load : std_logic := '0';
signal up : std_logic := '0';
signal down : std_logic := '0';
signal counter : unsigned(7 downto 0);
signal counter_signed : signed(7 downto 0);
procedure waitRisingEdge is
begin
wait until clk = '0';
wait until clk = '1';
wait for 0.5 ns;
end procedure;
procedure waitEdgeAndCheck(expected:integer) is
begin
waitRisingEdge;
assert(counter = expected);
assert(counter_signed = expected);
end procedure;
procedure waitEdgeAndCheck(expected_unsigned:integer; expected_signed:integer) is
begin
waitRisingEdge;
assert(counter = expected_unsigned);
assert(counter_signed = expected_signed);
end procedure;
begin
myUpDownCounter : entity work.gen_counter
port map (
clk => clk,
reset => reset,
load => load,
up => up,
down => down,
d => to_unsigned(12, 8),
q => counter
);
myCounterSigned : entity work.gen_counter_signed
port map (
clk => clk,
reset => reset,
load => load,
up => up,
down => down,
d => to_signed(12, 8),
q => counter_signed
);
clk <= (not stop) and (not clk) after 5 ns;
process
begin
-- No counting with all control inputs 0
waitEdgeAndCheck(0);
-- Count up
up <= '1';
waitEdgeAndCheck(1);
waitEdgeAndCheck(2);
waitEdgeAndCheck(3);
-- Don't count with up+down
down <= '1';
waitEdgeAndCheck(3);
-- Count down
up <= '0';
waitEdgeAndCheck(2);
waitEdgeAndCheck(1);
waitEdgeAndCheck(0);
-- Roll-over
waitEdgeAndCheck(255, -1);
waitEdgeAndCheck(254, -2);
-- Load has priority over counting
load <= '1';
waitEdgeAndCheck(12);
-- Reset has priority over everything
reset <= '1';
waitEdgeAndCheck(0);
stop <= '1';
wait;
end process;
end architecture;
| lgpl-2.1 | f4ae04fc8c5621ab70f8c8ad50f9de84 | 0.572647 | 3.715847 | false | false | false | false |
ARC-Lab-UF/UAA | src/sga.vhd | 1 | 13,353 | -- Copyright (c) 2015 University of Florida
--
-- This file is part of uaa.
--
-- uaa is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- uaa is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with uaa. If not, see <http://www.gnu.org/licenses/>.
-- David Wilson
-- University of Florida
-- Description:
-- The sga entity implements a simple group adder similar to the architecture
-- described in the paper "Design and implementation of an FPGA-based high-
-- performance improved vector-reduction method" by Song et al. (2011)
-- Used entities:
-- add_wrapper
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.math_custom.all;
use work.flt_pkg.all;
-------------------------------------------------------------------------------
-- Generics Description
-- width : The width of the input and output in bits
-- add_core_name : A string representing different optimizations for the
-- actual adder core. See add_flt.vhd and flt_pkg.vhd for
-- more information.
-- use_bram : uses bram when true, uses LUTs or FFs when false
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Port Description:
-- clk : clock input
-- rst : reset input (asynchronous, active high)
-- hold_output : When asserted, this signal prevents the entity from
-- continuing past a valid output. When not asserted, the
-- output is valid for only a single cycle. This signal
-- makes it possible to stall the sga if downstream
-- components cannot receive another input (active high)
-- ready : when asserted, the sga is ready to accept new inputs. If not
-- asserted, external components must hold the current input or
-- it will be lost (active high)
-- end_of_group : should be asserted on the same cycle as the last input in a
-- group (active high)
-- input : sga input
-- output : sga output
-- valid_in : assert when the input to the sga is valid and ready is
-- asserted (active high)
-- valid_out : asserted when the output from the sga is valid. Unless
-- hold_output is asserted, valid_out is only asserted for
-- one cycle. (active high)
-------------------------------------------------------------------------------
entity sga is
generic (
width : positive := 32;
add_core_name : string := "speed";
use_bram : boolean := true);
port (
clk : in std_logic;
rst : in std_logic;
hold_output : in std_logic; -- '1' keeps outputs from disappearing
ready : out std_logic; -- '1' when sga can accept input
end_of_group : in std_logic; -- specifies last input in group
input : in std_logic_vector(width-1 downto 0);
output : out std_logic_vector(width-1 downto 0);
valid_in : in std_logic;
valid_out : out std_logic
);
end sga;
architecture RTL of sga is
type buf_array is array (natural range <>) of std_logic_vector(width downto 0);
--control signals
signal is_coalescing : std_logic;
signal stall : std_logic;
signal all_buffers_empty : std_logic;
signal ready_int : std_logic;
--ibuf signals
signal ibuf_sel : std_logic;
signal ibuf_rd : std_logic;
signal ibuf_out : buf_array(1 downto 0);
signal ibuf_ready : std_logic;
signal ibuf_ready_singleton : std_logic;
--buf signals
signal buf_sel : std_logic;
signal buf_rd : std_logic;
signal buf_out : buf_array(1 downto 0);
signal buf0_out : buf_array(1 downto 0);
signal buf0_rd_addr : std_logic;
signal buf0_wr_addr : std_logic;
signal buf_ready : std_logic;
--obuf signals
signal obuf_wr : std_logic;
signal valid_out_int : std_logic;
--adder signals
signal add_in1 : std_logic_vector(width-1 downto 0);
signal add_in2 : std_logic_vector(width-1 downto 0);
signal add_out : std_logic_vector(width-1 downto 0);
signal add_en : std_logic;
signal add_valid_in : std_logic;
signal add_valid_out : std_logic;
signal add_count : std_logic_vector(bitsNeeded(add_flt_latency(add_core_name))-1 downto 0);
begin
------------------------------------------------
-- IBUF
-- ibuf is ready to add when both ready bits of its output registers are asserted
ibuf_ready <= ibuf_out(0)(width) and ibuf_out(1)(width);
-- ibuf is ready to add single element when one ready bit is asserted and no more
-- elements are arriving
ibuf_ready_singleton <= '1' when (ibuf_out(0)(width) = '1' or ibuf_out(1)(width) = '1') and
is_coalescing = '1' else
'0';
-- create ibuf
process(clk, rst)
begin
if (rst = '1') then
ibuf_sel <= '0';
ibuf_out <= (others => (others => '0'));
elsif (rising_edge(clk)) then
if (stall = '0') then
-- zero out previous elements when reading
if (ibuf_rd = '1') then
ibuf_out <= (others => (others => '0'));
end if;
-- write to an ibuf register any time there is
-- valid data
if (valid_in = '1' and ready_int = '1') then
if (ibuf_sel = '0') then
ibuf_out(0) <= '1' & input;
else
ibuf_out(1) <= '1' & input;
end if;
-- switch between writing to ibuf0 and ibuf1
ibuf_sel <= not ibuf_sel;
end if;
end if;
end if;
end process;
------------------------------------------------
-- BUF
-- buf is ready to add when buf0 and buf1 ready bits are asserted
buf_ready <= buf_out(0)(width) and buf_out(1)(width);
-- create buf. Buf0 is implemented as two-register fifo to handle
-- when both ibuf and buf have two elements and two writes in the
-- same cycle.
process(clk, rst)
begin
if (rst = '1') then
buf0_rd_addr <= '0';
buf0_wr_addr <= '0';
buf0_out <= (others => (others => '0'));
buf_sel <= '0';
buf_out(1) <= (others => '0');
elsif (rising_edge(clk)) then
if (stall = '0') then
-- zero out previous elements when reading
if (buf_rd = '1') then
-- zero out only registers used in read
if (buf0_rd_addr = '0') then
buf0_out(0) <= (others => '0');
else
buf0_out(1) <= (others => '0');
end if;
buf_out(1) <= (others => '0');
-- pop the buf0 fifo by changing rd_addr
buf0_rd_addr <= not buf0_rd_addr;
end if;
-- write to buf any time there is valid adder output
-- that isn't the last element in the group
if (add_valid_out = '1' and obuf_wr = '0') then
-- switch between writing to buf0 and buf1
buf_sel <= not buf_sel;
if (buf_sel = '1') then
buf_out(1) <= '1' & add_out;
else
-- push element into buf0 fifo
if (buf0_wr_addr = '0') then
buf0_out(0) <= '1' & add_out;
else
buf0_out(1) <= '1' & add_out;
end if;
buf0_wr_addr <= not buf0_wr_addr;
end if;
end if;
end if;
end if;
end process;
-- multiplexer for buf0 output as a fifo
buf_out(0) <= buf0_out(0) when buf0_rd_addr <= '0' else buf0_out(1);
-------------------------------------------------
-- Control logic
-- determines adder scheduling
process(ibuf_ready, buf_ready, ibuf_ready_singleton)
begin
add_valid_in <= '0';
ibuf_rd <= '0';
buf_rd <= '0';
-- add using inputs from ibuf when ibuf is ready
if(ibuf_ready = '1') then
add_valid_in <= '1';
ibuf_rd <= '1';
-- add using inputs from buf when buf is ready
elsif(buf_ready = '1') then
add_valid_in <= '1';
buf_rd <= '1';
-- add using inputs from ibuf when ibuf has only one element and no more elements are arriving
elsif (ibuf_ready_singleton = '1') then
add_valid_in <= '1';
ibuf_rd <= '1';
end if;
end process;
-- buffers are empty if none of the registers have their ready bits asserted
all_buffers_empty <= '1' when buf0_out(0)(width) = '0' and buf0_out(1)(width) = '0' and buf_out(1)(width) = '0' and
ibuf_out(0)(width) = '0' and ibuf_out(1)(width) = '0' else
'0';
-- inputs are accepted when the architecture is not stalling or is coalescing the final sum of a group
ready_int <= '1' when stall = '0' and is_coalescing = '0' else '0';
ready <= ready_int;
-- stall the architecture when an output is being held and another final sum has been computed
stall <= '1' when (obuf_wr = '1' and valid_out_int = '1' and hold_output = '1') else '0';
-- indicates if the group's elements are being coalesced into one value
process(clk, rst)
begin
if (rst = '1') then
is_coalescing <= '0';
elsif (rising_edge(clk)) then
if (stall = '0') then
-- coalescing begins when the last element has arrived
if (valid_in = '1' and ready_int = '1' and end_of_group = '1') then
is_coalescing <= '1';
-- coalescing ends when the final sum has been computed
elsif (is_coalescing = '1' and obuf_wr = '1') then
is_coalescing <= '0';
end if;
end if;
end if;
end process;
------------------------------------------------
-- OBUF
-- the obuf is written to when the buffers are empty
-- and the adder output has the final sum
obuf_wr <= '1' when (unsigned(add_count) = 1 and
all_buffers_empty = '1' and
add_valid_out = '1' and
is_coalescing = '1') else
'0';
-- create obuf
process(clk, rst)
begin
if (rst = '1') then
output <= (others => '0');
valid_out_int <= '0';
elsif (rising_edge(clk)) then
if (stall = '0') then
-- only deassert valid_out when hold_output is deasserted
if (hold_output = '0') then
valid_out_int <= '0';
end if;
-- the final sum from adder is output when no elements remain in adders
-- and buffers, and no output is being held with hold_output asserted
if (obuf_wr = '1' and (hold_output = '0' or valid_out_int = '0')) then
output <= add_out;
valid_out_int <= '1';
end if;
end if;
end if;
end process;
valid_out <= valid_out_int;
------------------------------------------------
-- OBUF
-- enable adder when the architecture is not stalling
add_en <= not stall;
-- multiplexer for 1st adder input
add_in1 <= ibuf_out(0)(width-1 downto 0) when ibuf_rd = '1' else
buf_out(0)(width-1 downto 0);
-- multiplexer for 2nd adder input
add_in2 <= ibuf_out(1)(width-1 downto 0) when ibuf_rd = '1' else
buf_out(1)(width-1 downto 0);
U_ADD : entity work.add_wrapper
generic map (core_name => add_core_name,
width => width)
port map (clk => clk,
rst => rst,
en => add_en,
input1 => add_in1,
input2 => add_in2,
output => add_out,
valid_in => add_valid_in,
valid_out => add_valid_out,
count => add_count);
end RTL;
| gpl-3.0 | c588fb5a47f6708ff7640b152fecba9b | 0.495919 | 4.136617 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/maps/mul_61x61.vhd | 1 | 4,227 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mul_61x61
-- File: mul_61x61.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: 61x61 multiplier
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity mul_61x61 is
generic (multech : integer := 0;
fabtech : integer := 0);
port(A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end;
architecture rtl of mul_61x61 is
component dw_mul_61x61 is
port(A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end component;
component gen_mul_61x61 is
port(A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end component;
component axcel_mul_61x61 is
port(A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end component;
component virtex4_mul_61x61
port(
A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end component;
component virtex6_mul_61x61
port(
A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end component;
component virtex7_mul_61x61
port(
A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end component;
component kintex7_mul_61x61
port(
A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end component;
begin
gen0 : if multech = 0 generate
mul0 : gen_mul_61x61 port map (A, B, EN, CLK, PRODUCT);
end generate;
dw0 : if multech = 1 generate
mul0 : dw_mul_61x61 port map (A, B, CLK, PRODUCT);
end generate;
tech0 : if multech = 3 generate
axd0 : if fabtech = axdsp generate
mul0 : axcel_mul_61x61 port map (A, B, EN, CLK, PRODUCT);
end generate;
xc5v : if fabtech = virtex5 generate
mul0 : virtex4_mul_61x61 port map (A, B, EN, CLK, PRODUCT);
end generate;
xc6v : if fabtech = virtex6 generate
mul0 : virtex6_mul_61x61 port map (A, B, EN, CLK, PRODUCT);
end generate;
gen0 : if not ((fabtech = axdsp) or (fabtech = virtex5) or (fabtech = virtex6)) generate
mul0 : gen_mul_61x61 port map (A, B, EN, CLK, PRODUCT);
end generate;
end generate;
end;
| gpl-3.0 | 3363e016397b5367453b0e6c6ccc3518 | 0.611072 | 3.467596 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/unisim/tap_unisim.vhd | 1 | 24,355 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: tap_xilinx
-- File: tap_xilinx.vhd
-- Author: Edvin Catovic, Jiri Gaisler - Gaisler Research
-- Description: Xilinx TAP controllers wrappers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity virtex_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of virtex_tap is
component BSCAN_VIRTEX
port (CAPTURE : out STD_ULOGIC;
DRCK1 : out STD_ULOGIC;
DRCK2 : out STD_ULOGIC;
RESET : out STD_ULOGIC;
SEL1 : out STD_ULOGIC;
SEL2 : out STD_ULOGIC;
SHIFT : out STD_ULOGIC;
TDI : out STD_ULOGIC;
UPDATE : out STD_ULOGIC;
TDO1 : in STD_ULOGIC;
TDO2 : in STD_ULOGIC);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
begin
u0 : BSCAN_VIRTEX
port map (
DRCK1 => drck1,
DRCK2 => drck2,
RESET => tapo_rst,
SEL1 => sel1,
SEL2 => sel2,
SHIFT => tapo_shft,
TDI => tapo_tdi,
UPDATE => tapo_upd,
TDO1 => tapi_tdo1,
TDO2 => tapi_tdo2);
tapo_tck <= drck1 when sel1 = '1' else drck2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2; tapo_capt <= '0';
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity virtex2_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of virtex2_tap is
component BSCAN_VIRTEX2
port (CAPTURE : out STD_ULOGIC;
DRCK1 : out STD_ULOGIC;
DRCK2 : out STD_ULOGIC;
RESET : out STD_ULOGIC;
SEL1 : out STD_ULOGIC;
SEL2 : out STD_ULOGIC;
SHIFT : out STD_ULOGIC;
TDI : out STD_ULOGIC;
UPDATE : out STD_ULOGIC;
TDO1 : in STD_ULOGIC;
TDO2 : in STD_ULOGIC);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
begin
u0 : BSCAN_VIRTEX2
port map (CAPTURE => tapo_capt,
DRCK1 => drck1,
DRCK2 => drck2,
RESET => tapo_rst,
SEL1 => sel1,
SEL2 => sel2,
SHIFT => tapo_shft,
TDI => tapo_tdi,
UPDATE => tapo_upd,
TDO1 => tapi_tdo1,
TDO2 => tapi_tdo2);
tapo_tck <= drck1 when sel1 = '1' else drck2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BSCAN_SPARTAN3;
-- pragma translate_on
entity spartan3_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of spartan3_tap is
component BSCAN_SPARTAN3
port (CAPTURE : out STD_ULOGIC;
DRCK1 : out STD_ULOGIC;
DRCK2 : out STD_ULOGIC;
RESET : out STD_ULOGIC;
SEL1 : out STD_ULOGIC;
SEL2 : out STD_ULOGIC;
SHIFT : out STD_ULOGIC;
TDI : out STD_ULOGIC;
UPDATE : out STD_ULOGIC;
TDO1 : in STD_ULOGIC;
TDO2 : in STD_ULOGIC);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
begin
u0 : BSCAN_SPARTAN3
port map (CAPTURE => tapo_capt,
DRCK1 => drck1,
DRCK2 => drck2,
RESET => tapo_rst,
SEL1 => sel1,
SEL2 => sel2,
SHIFT => tapo_shft,
TDI => tapo_tdi,
UPDATE => tapo_upd,
TDO1 => tapi_tdo1,
TDO2 => tapi_tdo2);
tapo_tck <= drck1 when sel1 = '1' else drck2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BSCAN_VIRTEX4;
-- pragma translate_on
entity virtex4_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of virtex4_tap is
component BSCAN_VIRTEX4 generic ( JTAG_CHAIN : integer := 1);
port ( CAPTURE : out std_ulogic;
DRCK : out std_ulogic;
RESET : out std_ulogic;
SEL : out std_ulogic;
SHIFT : out std_ulogic;
TDI : out std_ulogic;
UPDATE : out std_ulogic;
TDO : in std_ulogic);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
signal capt1, capt2, rst1, rst2 : std_ulogic;
signal shift1, shift2, tdi1, tdi2 : std_ulogic;
signal update1, update2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
attribute dont_touch of u1 : label is true;
begin
u0 : BSCAN_VIRTEX4
generic map (JTAG_CHAIN => 1)
port map (
CAPTURE => capt1,
DRCK => drck1,
RESET => rst1,
SEL => sel1,
SHIFT => shift1,
TDI => tdi1,
UPDATE => update1,
TDO => tapi_tdo1
);
u1 : BSCAN_VIRTEX4
generic map (JTAG_CHAIN => 2)
port map (
CAPTURE => capt2,
DRCK => drck2,
RESET => rst2,
SEL => sel2,
SHIFT => shift2,
TDI => tdi2,
UPDATE => update2,
TDO => tapi_tdo2
);
tapo_capt <= capt1 when sel1 = '1' else capt2;
tapo_tck <= drck1 when sel1 = '1' else drck2;
tapo_rst <= rst1 when sel1 = '1' else rst2;
tapo_shft <= shift1 when sel1 = '1' else shift2;
tapo_tdi <= tdi1 when sel1 = '1' else tdi2;
tapo_upd <= update1 when sel1 ='1' else update2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BSCAN_VIRTEX5;
-- pragma translate_on
entity virtex5_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of virtex5_tap is
component BSCAN_VIRTEX5 generic ( JTAG_CHAIN : integer := 1);
port ( CAPTURE : out std_ulogic;
DRCK : out std_ulogic;
RESET : out std_ulogic;
SEL : out std_ulogic;
SHIFT : out std_ulogic;
TDI : out std_ulogic;
UPDATE : out std_ulogic;
TDO : in std_ulogic);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
signal capt1, capt2, rst1, rst2 : std_ulogic;
signal shift1, shift2, tdi1, tdi2 : std_ulogic;
signal update1, update2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
attribute dont_touch of u1 : label is true;
begin
u0 : BSCAN_VIRTEX5
generic map (JTAG_CHAIN => 1)
port map (
CAPTURE => capt1,
DRCK => drck1,
RESET => rst1,
SEL => sel1,
SHIFT => shift1,
TDI => tdi1,
UPDATE => update1,
TDO => tapi_tdo1
);
u1 : BSCAN_VIRTEX5
generic map (JTAG_CHAIN => 2)
port map (
CAPTURE => capt2,
DRCK => drck2,
RESET => rst2,
SEL => sel2,
SHIFT => shift2,
TDI => tdi2,
UPDATE => update2,
TDO => tapi_tdo2
);
tapo_capt <= capt1 when sel1 = '1' else capt2;
tapo_tck <= drck1 when sel1 = '1' else drck2;
tapo_rst <= rst1 when sel1 = '1' else rst2;
tapo_shft <= shift1 when sel1 = '1' else shift2;
tapo_tdi <= tdi1 when sel1 = '1' else tdi2;
tapo_upd <= update1 when sel1 ='1' else update2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity virtex6_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of virtex6_tap is
component BSCAN_VIRTEX6
generic (
DISABLE_JTAG : boolean := FALSE;
JTAG_CHAIN : integer := 1
);
port (
CAPTURE : out std_ulogic := 'H';
DRCK : out std_ulogic := 'H';
RESET : out std_ulogic := 'H';
RUNTEST : out std_ulogic := 'L';
SEL : out std_ulogic := 'L';
SHIFT : out std_ulogic := 'L';
TCK : out std_ulogic := 'L';
TDI : out std_ulogic := 'L';
TMS : out std_ulogic := 'L';
UPDATE : out std_ulogic := 'L';
TDO : in std_ulogic := 'X'
);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
signal capt1, capt2, rst1, rst2 : std_ulogic;
signal shift1, shift2, tdi1, tdi2 : std_ulogic;
signal update1, update2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
attribute dont_touch of u1 : label is true;
begin
u0 : BSCAN_VIRTEX6
generic map (JTAG_CHAIN => 1)
port map (
CAPTURE => capt1,
DRCK => drck1,
RESET => rst1,
SEL => sel1,
SHIFT => shift1,
TDI => tdi1,
UPDATE => update1,
TDO => tapi_tdo1,
TCK => tapo_tck
);
u1 : BSCAN_VIRTEX6
generic map (JTAG_CHAIN => 2)
port map (
CAPTURE => capt2,
DRCK => drck2,
RESET => rst2,
SEL => sel2,
SHIFT => shift2,
TDI => tdi2,
UPDATE => update2,
TDO => tapi_tdo2
);
tapo_capt <= capt1 when sel1 = '1' else capt2;
tapo_rst <= rst1 when sel1 = '1' else rst2;
tapo_shft <= shift1 when sel1 = '1' else shift2;
tapo_tdi <= tdi1 when sel1 = '1' else tdi2;
tapo_upd <= update1 when sel1 ='1' else update2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity spartan6_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of spartan6_tap is
component BSCAN_SPARTAN6
generic (
JTAG_CHAIN : integer := 1
);
port (
CAPTURE : out std_ulogic := 'H';
DRCK : out std_ulogic := 'H';
RESET : out std_ulogic := 'H';
RUNTEST : out std_ulogic := 'L';
SEL : out std_ulogic := 'L';
SHIFT : out std_ulogic := 'L';
TCK : out std_ulogic := 'L';
TDI : out std_ulogic := 'L';
TMS : out std_ulogic := 'L';
UPDATE : out std_ulogic := 'L';
TDO : in std_ulogic := 'X'
);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
signal capt1, capt2, rst1, rst2 : std_ulogic;
signal shift1, shift2, tdi1, tdi2 : std_ulogic;
signal update1, update2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
attribute dont_touch of u1 : label is true;
begin
u0 : BSCAN_SPARTAN6
generic map (JTAG_CHAIN => 1)
port map (
CAPTURE => capt1,
DRCK => drck1,
RESET => rst1,
SEL => sel1,
SHIFT => shift1,
TDI => tdi1,
UPDATE => update1,
TDO => tapi_tdo1,
TCK => tapo_tck
);
u1 : BSCAN_SPARTAN6
generic map (JTAG_CHAIN => 2)
port map (
CAPTURE => capt2,
DRCK => drck2,
RESET => rst2,
SEL => sel2,
SHIFT => shift2,
TDI => tdi2,
UPDATE => update2,
TDO => tapi_tdo2
);
tapo_capt <= capt1 when sel1 = '1' else capt2;
tapo_rst <= rst1 when sel1 = '1' else rst2;
tapo_shft <= shift1 when sel1 = '1' else shift2;
tapo_tdi <= tdi1 when sel1 = '1' else tdi2;
tapo_upd <= update1 when sel1 ='1' else update2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity virtex7_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of virtex7_tap is
component BSCANE2
generic (
DISABLE_JTAG : string := "FALSE";
JTAG_CHAIN : integer := 1
);
port (
CAPTURE : out std_ulogic := 'H';
DRCK : out std_ulogic := 'H';
RESET : out std_ulogic := 'H';
RUNTEST : out std_ulogic := 'L';
SEL : out std_ulogic := 'L';
SHIFT : out std_ulogic := 'L';
TCK : out std_ulogic := 'L';
TDI : out std_ulogic := 'L';
TMS : out std_ulogic := 'L';
UPDATE : out std_ulogic := 'L';
TDO : in std_ulogic := 'X'
);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
signal capt1, capt2, rst1, rst2 : std_ulogic;
signal shift1, shift2, tdi1, tdi2 : std_ulogic;
signal update1, update2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
attribute dont_touch of u1 : label is true;
begin
u0 : BSCANE2
generic map (JTAG_CHAIN => 1)
port map (
CAPTURE => capt1,
DRCK => drck1,
RESET => rst1,
SEL => sel1,
SHIFT => shift1,
TDI => tdi1,
UPDATE => update1,
TDO => tapi_tdo1,
TCK => tapo_tck
);
u1 : BSCANE2
generic map (JTAG_CHAIN => 2)
port map (
CAPTURE => capt2,
DRCK => drck2,
RESET => rst2,
SEL => sel2,
SHIFT => shift2,
TDI => tdi2,
UPDATE => update2,
TDO => tapi_tdo2
);
tapo_capt <= capt1 when sel1 = '1' else capt2;
tapo_rst <= rst1 when sel1 = '1' else rst2;
tapo_shft <= shift1 when sel1 = '1' else shift2;
tapo_tdi <= tdi1 when sel1 = '1' else tdi2;
tapo_upd <= update1 when sel1 ='1' else update2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity kintex7_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of kintex7_tap is
component BSCANE2
generic (
DISABLE_JTAG : string := "FALSE";
JTAG_CHAIN : integer := 1
);
port (
CAPTURE : out std_ulogic := 'H';
DRCK : out std_ulogic := 'H';
RESET : out std_ulogic := 'H';
RUNTEST : out std_ulogic := 'L';
SEL : out std_ulogic := 'L';
SHIFT : out std_ulogic := 'L';
TCK : out std_ulogic := 'L';
TDI : out std_ulogic := 'L';
TMS : out std_ulogic := 'L';
UPDATE : out std_ulogic := 'L';
TDO : in std_ulogic := 'X'
);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
signal capt1, capt2, rst1, rst2 : std_ulogic;
signal shift1, shift2, tdi1, tdi2 : std_ulogic;
signal update1, update2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
attribute dont_touch of u1 : label is true;
begin
u0 : BSCANE2
generic map (JTAG_CHAIN => 1)
port map (
CAPTURE => capt1,
DRCK => drck1,
RESET => rst1,
SEL => sel1,
SHIFT => shift1,
TDI => tdi1,
UPDATE => update1,
TDO => tapi_tdo1,
TCK => tapo_tck
);
u1 : BSCANE2
generic map (JTAG_CHAIN => 2)
port map (
CAPTURE => capt2,
DRCK => drck2,
RESET => rst2,
SEL => sel2,
SHIFT => shift2,
TDI => tdi2,
UPDATE => update2,
TDO => tapi_tdo2
);
tapo_capt <= capt1 when sel1 = '1' else capt2;
tapo_rst <= rst1 when sel1 = '1' else rst2;
tapo_shft <= shift1 when sel1 = '1' else shift2;
tapo_tdi <= tdi1 when sel1 = '1' else tdi2;
tapo_upd <= update1 when sel1 ='1' else update2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity artix7_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of artix7_tap is
component BSCANE2
generic (
DISABLE_JTAG : string := "FALSE";
JTAG_CHAIN : integer := 1
);
port (
CAPTURE : out std_ulogic := 'H';
DRCK : out std_ulogic := 'H';
RESET : out std_ulogic := 'H';
RUNTEST : out std_ulogic := 'L';
SEL : out std_ulogic := 'L';
SHIFT : out std_ulogic := 'L';
TCK : out std_ulogic := 'L';
TDI : out std_ulogic := 'L';
TMS : out std_ulogic := 'L';
UPDATE : out std_ulogic := 'L';
TDO : in std_ulogic := 'X'
);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
signal capt1, capt2, rst1, rst2 : std_ulogic;
signal shift1, shift2, tdi1, tdi2 : std_ulogic;
signal update1, update2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
attribute dont_touch of u1 : label is true;
begin
u0 : BSCANE2
generic map (JTAG_CHAIN => 1)
port map (
CAPTURE => capt1,
DRCK => drck1,
RESET => rst1,
SEL => sel1,
SHIFT => shift1,
TDI => tdi1,
UPDATE => update1,
TDO => tapi_tdo1,
TCK => tapo_tck
);
u1 : BSCANE2
generic map (JTAG_CHAIN => 2)
port map (
CAPTURE => capt2,
DRCK => drck2,
RESET => rst2,
SEL => sel2,
SHIFT => shift2,
TDI => tdi2,
UPDATE => update2,
TDO => tapi_tdo2
);
tapo_capt <= capt1 when sel1 = '1' else capt2;
tapo_rst <= rst1 when sel1 = '1' else rst2;
tapo_shft <= shift1 when sel1 = '1' else shift2;
tapo_tdi <= tdi1 when sel1 = '1' else tdi2;
tapo_upd <= update1 when sel1 ='1' else update2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
| gpl-3.0 | 3a06d64756cbb6abcee3083c3305a5e5 | 0.498337 | 3.750385 | false | false | false | false |
firecake/IRIS | FPGA/VHDL/ipcore_dir/RAM.vhd | 1 | 6,221 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2015 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file RAM.vhd when simulating
-- the core, RAM. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY RAM IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END RAM;
ARCHITECTURE RAM_a OF RAM IS
-- synthesis translate_off
COMPONENT wrapped_RAM
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_RAM USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 12,
c_addrb_width => 12,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 1,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan3",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "no_coe_file_loaded",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 0,
c_mem_type => 2,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 4096,
c_read_depth_b => 4096,
c_read_width_a => 32,
c_read_width_b => 32,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 1,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 4096,
c_write_depth_b => 4096,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 32,
c_write_width_b => 32,
c_xdevicefamily => "spartan3a"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_RAM
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb
);
-- synthesis translate_on
END RAM_a;
| gpl-3.0 | ea233dff61f879e46fde0fefc0d96631 | 0.521942 | 3.880848 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/sim/ddr2ram.vhd | 1 | 23,543 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr2ram
-- File: ddr2ram.vhd
-- Author: Magnus Hjorth, Aeroflex Gaisler
-- Description: Generic simulation model of DDR2 SDRAM (JESD79-2C)
------------------------------------------------------------------------------
--pragma translate_off
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdio.hread;
use grlib.stdlib.all;
entity ddr2ram is
generic (
width: integer := 32;
abits: integer range 13 to 16 := 13;
babits: integer range 2 to 3 := 3;
colbits: integer range 9 to 11 := 9;
rowbits: integer range 1 to 16 := 13;
implbanks: integer range 1 to 8 := 1;
swap : integer := 0; -- byte swap during srec load
fname: string;
lddelay: time := (0 ns);
ldguard: integer range 0 to 1 := 0; -- 1: wait for doload input before
-- loading RAM
-- Speed bins: 0:DDR2-400C,1:400B,2:533C,3:533B,4:667D,5:667C,6:800E,7:800D,8:800C
-- 9:800+ (MT47H-25E)
speedbin: integer range 0 to 9 := 0;
density: integer range 1 to 5 := 3; -- 1:256M 2:512M 3:1G 4:2G 5:4G bits/chip
pagesize: integer range 1 to 2 := 1 -- 1K/2K page size (controls tRRD)
);
port (
ck: in std_ulogic;
ckn: in std_ulogic;
cke: in std_ulogic;
csn: in std_ulogic;
odt: in std_ulogic;
rasn: in std_ulogic;
casn: in std_ulogic;
wen: in std_ulogic;
dm: in std_logic_vector(width/8-1 downto 0);
ba: in std_logic_vector(babits-1 downto 0);
a: in std_logic_vector(abits-1 downto 0);
dq: inout std_logic_vector(width-1 downto 0);
dqs: inout std_logic_vector(width/8-1 downto 0);
dqsn: inout std_logic_vector(width/8-1 downto 0);
doload: in std_ulogic := '1'
);
end;
architecture sim of ddr2ram is
type moderegs is record
-- Mode register (0)
pd: std_ulogic;
wr: std_logic_vector(2 downto 0);
dllres: std_ulogic;
tm: std_ulogic;
caslat: std_logic_vector(2 downto 0);
bt: std_ulogic;
blen: std_logic_vector(2 downto 0);
-- Extended mode register 1
qoff: std_ulogic;
rdqsen: std_ulogic;
dqsndis: std_ulogic;
ocdprog: std_logic_vector(2 downto 0);
al: std_logic_vector(2 downto 0);
rtt: std_logic_vector(1 downto 0);
ds: std_ulogic;
dlldis: std_ulogic;
-- Extended mode register 2
srf: std_ulogic;
dccen: std_ulogic;
pasr: std_logic_vector(2 downto 0);
-- Extended mode register 3
emr3: std_logic_vector(abits-1 downto 0);
end record;
-- Mode registers as signal, useful for debugging
signal mr: moderegs;
-- Handshaking between command and DQ/DQS processes
signal read_en, write_en: boolean := false;
signal read_data, write_data: std_logic_vector(2*width-1 downto 0);
signal write_mask: std_logic_vector(width/4-1 downto 0);
signal initdone: boolean := false;
-- Small delta-t to adjust calculations for jitter tol.
constant deltat: time := 50 ps;
-- Timing parameters
constant tWR: time := 15 ns;
constant tMRD_ck: integer := 2;
constant tRTP: time := 7.5 ns;
type timetab is array (0 to 9) of time;
-- 400C 400B 533C 533B 667D 667C 800E 800D 800C MT-2.5E
constant tRAS : timetab := (45 ns, 40 ns, 45 ns, 45 ns, 45 ns, 45 ns, 45 ns, 45 ns, 45 ns, 40 ns);
constant tRP : timetab := (20 ns, 15 ns, 15 ns, 11.25 ns, 15 ns, 12 ns, 15 ns, 12.5 ns, 10 ns, 12.5 ns);
constant tRCD: timetab := tRP;
type timetab2 is array(1 to 5) of time;
constant tRFC: timetab2 := (75 ns, 105 ns, 127.5 ns, 195 ns, 327.5 ns);
type timetab3 is array(1 to 2) of time;
constant tRRD: timetab3 := (7.5 ns, 10 ns);
begin
-----------------------------------------------------------------------------
-- Init sequence checker
-----------------------------------------------------------------------------
initp: process
variable cyctr: integer := 0;
procedure checkcmd(crasn,ccasn,cwen: std_ulogic;
cba: std_logic_vector(1 downto 0);
ca: std_logic_vector(15 downto 0)) is
variable amatch: boolean;
begin
wait until rising_edge(ck);
cyctr := cyctr+1;
while cke='1' and (csn='1' or (rasn='1' and casn='1' and wen='1')) loop
wait until rising_edge(ck);
cyctr := cyctr+1;
end loop;
amatch := true;
for x in a'range loop
if ca(x)/='-' and ca(x)/=a(x) then amatch:=false; end if;
end loop;
assert cke='1' and csn='0' and rasn=crasn and casn=ccasn and wen=cwen and
(cba="--" or cba=ba(1 downto 0)) and amatch
report "Wrong command during init sequence" severity warning;
end checkcmd;
variable t: time;
begin
initdone <= false;
-- Allow cke to be X or U for a while during sim start
if is_x(cke) then
wait until not is_x(cke);
end if;
assert cke='0' report "CKE not deasserted on power-up" severity warning;
wait until cke/='0' for 200 us;
assert cke='0' report "CKE raised with less than 200 us init delay" severity warning;
wait until cke/='0' and rising_edge(ck);
assert cke='1' and (csn='1' or (rasn='1' and casn='1' and wen='1'));
t := now;
-- Precharge all
checkcmd('0','1','0',"--","-----1----------");
assert (now-t) > 400 ns report "Less than 400 ns wait period after CKE high!" severity warning;
-- EMRS EMR2
checkcmd('0','0','0',"10","----------------");
-- EMRS EMR3
checkcmd('0','0','0',"11","----------------");
-- EMRS enable DLL
checkcmd('0','0','0',"01","000---000-------");
-- MRS reset DLL
checkcmd('0','0','0',"00","000----1--------");
cyctr := 0;
-- Precharge all
checkcmd('0','1','0',"--","-----1----------");
-- 2 x auto refresh
checkcmd('0','0','1',"--","----------------");
checkcmd('0','0','1',"--","----------------");
-- MRS !reset DLL
checkcmd('0','0','0',"00","-------0--------");
-- EMRS EMR1 OCD default, EMRS EMR1 exit OCD cal
-- (assume OCD impedance adjust not performed)
checkcmd('0','0','0',"01","------111-------");
assert cyctr >= 200 report "Less than 200 cycles (" & tost(cyctr) & ") between DLL reset and OCD cal" severity warning;
checkcmd('0','0','0',"01","------000-------");
initdone <= true;
wait;
end process;
-----------------------------------------------------------------------------
-- Command state machine
-----------------------------------------------------------------------------
cmdp: process(ck)
subtype coldata is std_logic_vector(width-1 downto 0);
type coldata_arr is array(0 to implbanks*(2**(colbits+rowbits))-1) of coldata;
variable memdata: coldata_arr;
procedure load_srec is
file TCF : text open read_mode is fname;
variable L1: line;
variable CH : character;
variable rectype : std_logic_vector(3 downto 0);
variable recaddr : std_logic_vector(31 downto 0);
variable reclen : std_logic_vector(7 downto 0);
variable recdata : std_logic_vector(0 to 16*8-1);
variable recdatatemp : std_logic_vector(0 to 63);
variable col, coloffs, len: integer;
begin
L1:= new string'("");
while not endfile(TCF) loop
readline(TCF,L1);
if (L1'length /= 0) then
while (not (L1'length=0)) and (L1(L1'left) = ' ') loop
std.textio.read(L1,CH);
end loop;
if L1'length > 0 then
read(L1, ch);
if (ch = 'S') or (ch = 's') then
hread(L1, rectype);
hread(L1, reclen);
len := to_integer(unsigned(reclen))-1;
recaddr := (others => '0');
case rectype is
when "0001" => hread(L1, recaddr(15 downto 0)); len := len - 2;
when "0010" => hread(L1, recaddr(23 downto 0)); len := len - 3;
when "0011" => hread(L1, recaddr); len := len - 4;
when others => next;
end case;
hread(L1, recdata(0 to len*8-1));
if swap=1 then -- byte swap during srec load
for i in 0 to 7 loop
recdatatemp(0 to 7) := recdata(i*16 to i*16+7);
recdata(i*16 to i*16+7) := recdata(i*16+8 to i*16+15);
recdata(i*16+8 to i*16+15) := recdatatemp(0 to 7);
end loop;
elsif swap = 2 then
recaddr(4) := not recaddr(4);
recdatatemp := recdata(0 to 63);
recdata(0 to 63) := recdata(64 to 127);
recdata(64 to 127) := recdatatemp;
end if;
col := to_integer(unsigned(recaddr(log2(width/8)+rowbits+colbits+1 downto log2(width/8))));
coloffs := 8*to_integer(unsigned(recaddr(log2(width/8)-1 downto 0)));
while len > width/8 loop
assert coloffs=0;
memdata(col) := recdata(0 to width-1);
col := col+1;
len := len-width/8;
recdata(0 to recdata'length-width-1) := recdata(width to recdata'length-1);
end loop;
memdata(col)(width-1-coloffs downto width-coloffs-len*8) := recdata(0 to len*8-1);
end if;
end if;
end if;
end loop;
end load_srec;
variable vmr: moderegs;
type bankstate is record
openrow: integer;
opentime: time;
closetime: time;
writetime: time;
readtime: time;
autopch: integer;
pchpush: boolean;
end record;
type bankstate_arr is array(natural range <>) of bankstate;
variable banks: bankstate_arr(7 downto 0) := (others => (-1, 0 ns, 0 ns, 0 ns, 0 ns, -1, false));
type int_arr is array(natural range <>) of integer;
type dataacc is record
r,w: boolean;
col: int_arr(0 to 1);
bank: integer;
end record;
type dataacc_arr is array(natural range <>) of dataacc;
variable accpipe: dataacc_arr(0 to 9);
variable cmd: std_logic_vector(2 downto 0);
variable bank: integer;
variable colv: unsigned(a'high-1 downto 0);
variable alow: unsigned(2 downto 0);
variable col: integer;
variable prev_re, re: time;
variable blen: integer;
variable lastref: time := 0 ns;
variable i, al, cl, wrap: integer;
variable b: boolean;
variable mrscount: integer := 0;
variable loaded: boolean := false;
procedure checktime(got, exp: time; gt: boolean; req: string) is
begin
assert (got + deltat > exp and gt) or (got-deltat < exp and not gt)
report (req & " violation, got: " & tost(got/(1 ps)) & " ps, exp: " & tost(exp/(1 ps)) & "ps")
severity warning;
end checktime;
begin
if rising_edge(ck) then
-- Update pipe regs
prev_re := re;
re := now;
accpipe(1 to accpipe'high) := accpipe(0 to accpipe'high-1);
accpipe(0).r:=false; accpipe(0).w:=false;
-- Parse MR fields
cmd := rasn & casn & wen;
if is_x(vmr.caslat) then cl:=0; else cl:=to_integer(unsigned(vmr.caslat)); end if;
if cl<2 or cl>6 then cl:=0; end if;
if is_x(vmr.al) then al:=0; else al:=to_integer(unsigned(vmr.al)); end if;
if al>5 then al:=0; end if;
if is_x(vmr.wr) then wrap:=0; else wrap:=1+to_integer(unsigned(vmr.wr)); end if;
if wrap<2 or wrap>6 then wrap:=0; end if;
-- Checks for all-bank commands
if mrscount > 0 then
mrscount := mrscount-1;
assert cke='1' and (csn='1' or cmd="111") report "tMRS violation!" severity warning;
end if;
if cke='1' and csn='0' and cmd/="111" then
checktime(now-lastref, tRFC(density), true, "tRFC");
end if;
-- Main command handler
if cke='1' and csn='0' then
case cmd is
when "111" => -- NOP
when "011" => -- RAS
assert initdone report "Opening row before init sequence done!" severity warning;
bank := to_integer(unsigned(ba));
assert banks(bank).openrow < 0
report "Row already open" severity warning;
checktime(now-banks(bank).closetime, tRP(speedbin), true, "tRP");
for x in 0 to 7 loop
checktime(now-banks(x).opentime, tRRD(pagesize), true, "tRRD");
end loop;
banks(bank).openrow := to_integer(unsigned(a(rowbits-1 downto 0)));
banks(bank).opentime := now;
when "101" | "100" => -- Read/Write
bank := to_integer(unsigned(ba));
-- Get additive latency
i := to_integer(unsigned(vmr.al));
assert banks(bank).openrow >= 0
report "Row not open" severity error;
checktime(now-banks(bank).opentime+al*(re-prev_re), tRCD(speedbin), true, "tRCD");
-- Allow interrupting read in case of middle of BL8 burst only
if (accpipe(3).r and accpipe(2).r and
not (accpipe(1).r or accpipe(1).w or accpipe(0).r or accpipe(0).w)) then
accpipe(3).r := false;
accpipe(2).r := false;
end if;
for x in 0 to 3 loop
assert not accpipe(x).r and not accpipe(x).w;
end loop;
if cmd(0)='1' then accpipe(3).r:=true; else accpipe(3).w:=true; end if;
colv := unsigned(std_logic_vector'(a(a'high downto 11) & a(9 downto 0)));
case vmr.blen is
when "010" => blen := 4;
when "011" => blen := 8;
when others => assert false report "Invalid burst length setting in MR!" severity error;
end case;
alow := unsigned(a(2 downto 0));
for x in 0 to blen-1 loop
accpipe(3-x/2).bank := bank;
if cmd(0)='1' then accpipe(3-x/2).r:=true; else accpipe(3-x/2).w:=true; end if;
if vmr.bt='0' then -- Sequential
colv(log2(blen)-1 downto 0) := alow(log2(blen)-1 downto 0) + x;
else -- Interleaved
colv(log2(blen)-1 downto 0) := alow(log2(blen)-1 downto 0) xor to_unsigned(x,log2(blen));
end if;
col := to_integer(unsigned(ba))*(2**(colbits+rowbits)) +
banks(bank).openrow * (2**colbits) + to_integer(colv(colbits-1 downto 0));
accpipe(3-x/2).col(x mod 2) := col;
end loop;
-- Auto precharge
if a(10)='1' then
if cmd(0)='1' then
banks(bank).autopch := al+blen/2;
else
banks(bank).autopch := cl+al-1+blen/2+wrap;
end if;
banks(bank).pchpush := true;
end if;
when "110" => -- Reserved (Burst terminate on DDR1)
assert false report "Invalid command RAS=1 CAS=1 WE=0" severity warning;
when "010" => -- Precharge
if a(10)='0' then bank := to_integer(unsigned(ba)); else bank:=0; end if;
for x in 3 downto 0 loop -- FIXME potential window which isn't checked if AL>0
assert (not (accpipe(x).r or accpipe(x).w)) or (a(10)='0' and bank/=accpipe(x).bank)
report "Precharging bank with access in progress"
severity warning;
end loop;
for x in 0 to (2**babits)-1 loop
if a(10)='1' or ba=std_logic_vector(to_unsigned(x,babits)) then
assert banks(x).autopch<0
report "Precharging bank that is auto-precharged!" severity note;
assert a(10)='1' or banks(x).openrow >= 0
report "Precharging single bank that is in idle state!" severity note;
banks(x).autopch := 0; -- Handled below case statement
banks(x).pchpush := false;
end if;
end loop;
when "001" => -- Auto refresh
for x in 0 to 7 loop
assert banks(x).openrow < 0
report "Bank in wrong state for auto refresh!" severity warning;
checktime(now-banks(x).closetime, tRP(speedbin), true, "tRP");
end loop;
lastref := now;
when "000" => -- MRS
for x in 0 to 7 loop
checktime(now-banks(x).closetime, tRP(speedbin), true, "tRP");
end loop;
bank := to_integer(unsigned(ba));
case bank is
when 0 =>
vmr.pd := a(12);
vmr.wr := a(11 downto 9);
vmr.dllres := a(8);
vmr.tm := a(7);
vmr.caslat := a(6 downto 4);
vmr.bt := a(3);
vmr.blen := a(2 downto 0);
when 1 =>
vmr.qoff := a(12);
vmr.rdqsen := a(11);
vmr.dqsndis := a(10);
vmr.ocdprog := a(9 downto 7);
vmr.al := a(5 downto 3);
vmr.rtt := a(6) & a(2);
vmr.ds := a(1);
vmr.dlldis := a(0);
when 2 =>
vmr.srf := a(7);
vmr.dccen := a(3);
vmr.pasr := a(2 downto 0);
when 3 =>
vmr.emr3 := a;
when others =>
assert false report ("MRS to invalid bank addr: " & std_logic'image(ba(1)) & std_logic'image(ba(0))) severity warning;
end case;
mrscount := tMRD_ck-1;
when others =>
assert false report ("Invalid command: " & std_logic'image(rasn) & std_logic'image(casn) & std_logic'image(wen)) severity warning;
end case;
end if;
-- Manual or auto precharge handling
for x in 0 to 7 loop
if banks(x).autopch=0 then
if banks(x).pchpush and (now-banks(x).opentime-deltat) < tRAS(speedbin) then
-- Auto delay auto-precharge to satisfy tRAS/tRC
banks(x).autopch := banks(x).autopch+1;
elsif banks(x).pchpush and (now-banks(x).readtime-deltat) < tRTP then
-- Auto delay auto-precharge to satisfy tRTP
banks(x).autopch := banks(x).autopch+1;
else
checktime(now-banks(x).writetime, tWR, true, "tWR");
checktime(now-banks(x).opentime, tRAS(speedbin), true, "tRAS");
checktime(now-banks(x).readtime, tRTP, true, "tRTP");
banks(x).openrow := -1;
banks(x).closetime := now;
end if;
end if;
if banks(x).autopch >= 0 then
banks(x).autopch := banks(x).autopch - 1;
end if;
end loop;
-- Read/write management
if not loaded and lddelay < now and (ldguard=0 or doload='1') then
load_srec;
loaded := true;
end if;
if accpipe(2+cl+al).r then
assert cl>1 report "Incorrect CL setting!" severity warning;
read_en <= true;
-- print("Reading from col " & tost(accpipe(2+i).col(0)) & " and " & tost(accpipe(2+i).col(1)));
-- col0 <= accpipe(2+i).col(0); col1 <= accpipe(2+i).col(1);
read_data <= memdata(accpipe(2+cl+al).col(0)) & memdata(accpipe(2+cl+al).col(1));
else
read_en <= false;
end if;
-- tRTP is counted from read command + AL for BL4, read command + AL + 2
-- for BL8. This check covers both cases by writing readtime on the next-to-last
-- transfer.
if accpipe(3+al).r and accpipe(2+al).r and accpipe(3+al).bank=accpipe(2+al).bank then
banks(accpipe(2+al).bank).readtime := now;
end if;
write_en <= accpipe(1+cl+al).w or accpipe(2+cl+al).w;
if accpipe(3+cl+al).w then
assert not is_x(write_mask) report "Write error!";
for x in 0 to 1 loop
for b in width/8-1 downto 0 loop
if write_mask((1-x)*width/8+b)='0' then
memdata(accpipe(3+cl+al).col(x))(8*b+7 downto 8*b) :=
write_data( (1-x)*width+b*8+7 downto (1-x)*width+b*8);
end if;
end loop;
end loop;
banks(accpipe(3+cl+al).bank).writetime := now;
end if;
end if;
mr <= vmr;
end process;
-----------------------------------------------------------------------------
-- DQS/DQ handling and data sampling process
-----------------------------------------------------------------------------
dqproc: process
variable rdata: std_logic_vector(2*width-1 downto 0);
variable hdata: std_logic_vector(width-1 downto 0);
variable hmask: std_logic_vector(width/8-1 downto 0);
variable prevdqs: std_logic_vector(width/8-1 downto 0);
begin
dq <= (others => 'Z');
dqs <= (others => 'Z');
dqsn <= (others => 'Z');
wait until read_en or write_en;
assert not (read_en and write_en);
if read_en then
dqs <= (others => '0');
dqsn <= (others => '1');
wait until falling_edge(ck);
while read_en loop
rdata := read_data;
wait until rising_edge(ck);
dqs <= (others => '1');
dqsn <= (others => '0');
dq <= rdata(2*width-1 downto width);
wait until falling_edge(ck);
dqs <= (others => '0');
dqsn <= (others => '1');
dq <= rdata(width-1 downto 0);
end loop;
wait until rising_edge(ck);
else
wait until falling_edge(ck);
assert (to_X01(dqs)=(dqs'range => '0')) or ((to_X01(dqs)=(dqs'range => '1')) and (to_X01(dm)=(dm'range => '1') or dm=(dm'range => 'Z')));
while write_en loop
prevdqs := to_X01(dqs);
wait until to_X01(dqs) /= prevdqs or not write_en or rising_edge(ck);
if rising_edge(ck) then
write_data <= (others => 'X');
write_mask <= (others => 'X');
end if;
for x in dqs'range loop
if prevdqs(x)='0' and to_X01(dqs(x))='1' then
hdata(8*x+7 downto 8*x) := dq(8*x+7 downto 8*x);
hmask(x) := dm(x);
elsif prevdqs(x)='1' and to_X01(dqs(x))='0' then
write_data(width+8*x+7 downto width+8*x) <= hdata(8*x+7 downto 8*x);
write_data(8*x+7 downto 8*x) <= dq(8*x+7 downto 8*x);
write_mask(width/8+x) <= hmask(x);
write_mask(x) <= dm(x);
end if;
end loop;
end loop;
end if;
end process;
end;
-- pragma translate_on
| gpl-3.0 | a4152557a82eac806e71b73607b0f7c6 | 0.529244 | 3.686658 | false | false | false | false |
hoglet67/CoPro6502 | client/6809/102e/tuberom_6809.vhd | 1 | 88,776 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tuberom_6809 is
port (
CLK : in std_logic;
ADDR : in std_logic_vector(10 downto 0);
DATA : out std_logic_vector(7 downto 0)
);
end;
architecture RTL of tuberom_6809 is
signal rom_addr : std_logic_vector(11 downto 0);
begin
p_addr : process(ADDR)
begin
rom_addr <= (others => '0');
rom_addr(10 downto 0) <= ADDR;
end process;
p_rom : process
begin
wait until rising_edge(CLK);
DATA <= (others => '0');
case rom_addr is
when x"000" => DATA <= x"F8";
when x"001" => DATA <= x"2C";
when x"002" => DATA <= x"F8";
when x"003" => DATA <= x"71";
when x"004" => DATA <= x"FF";
when x"005" => DATA <= x"E0";
when x"006" => DATA <= x"F8";
when x"007" => DATA <= x"EA";
when x"008" => DATA <= x"F8";
when x"009" => DATA <= x"FE";
when x"00A" => DATA <= x"FF";
when x"00B" => DATA <= x"EE";
when x"00C" => DATA <= x"F8";
when x"00D" => DATA <= x"F3";
when x"00E" => DATA <= x"FF";
when x"00F" => DATA <= x"E7";
when x"010" => DATA <= x"F8";
when x"011" => DATA <= x"F0";
when x"012" => DATA <= x"F8";
when x"013" => DATA <= x"E9";
when x"014" => DATA <= x"20";
when x"015" => DATA <= x"5B";
when x"016" => DATA <= x"0D";
when x"017" => DATA <= x"36";
when x"018" => DATA <= x"38";
when x"019" => DATA <= x"30";
when x"01A" => DATA <= x"39";
when x"01B" => DATA <= x"20";
when x"01C" => DATA <= x"54";
when x"01D" => DATA <= x"55";
when x"01E" => DATA <= x"42";
when x"01F" => DATA <= x"45";
when x"020" => DATA <= x"20";
when x"021" => DATA <= x"36";
when x"022" => DATA <= x"34";
when x"023" => DATA <= x"4B";
when x"024" => DATA <= x"20";
when x"025" => DATA <= x"31";
when x"026" => DATA <= x"2E";
when x"027" => DATA <= x"30";
when x"028" => DATA <= x"32";
when x"029" => DATA <= x"65";
when x"02A" => DATA <= x"0D";
when x"02B" => DATA <= x"00";
when x"02C" => DATA <= x"1A";
when x"02D" => DATA <= x"50";
when x"02E" => DATA <= x"10";
when x"02F" => DATA <= x"CE";
when x"030" => DATA <= x"F8";
when x"031" => DATA <= x"00";
when x"032" => DATA <= x"1F";
when x"033" => DATA <= x"41";
when x"034" => DATA <= x"EC";
when x"035" => DATA <= x"84";
when x"036" => DATA <= x"ED";
when x"037" => DATA <= x"81";
when x"038" => DATA <= x"8C";
when x"039" => DATA <= x"FE";
when x"03A" => DATA <= x"C0";
when x"03B" => DATA <= x"26";
when x"03C" => DATA <= x"03";
when x"03D" => DATA <= x"8E";
when x"03E" => DATA <= x"FE";
when x"03F" => DATA <= x"F0";
when x"040" => DATA <= x"8C";
when x"041" => DATA <= x"FF";
when x"042" => DATA <= x"8C";
when x"043" => DATA <= x"26";
when x"044" => DATA <= x"03";
when x"045" => DATA <= x"8E";
when x"046" => DATA <= x"FF";
when x"047" => DATA <= x"94";
when x"048" => DATA <= x"8C";
when x"049" => DATA <= x"00";
when x"04A" => DATA <= x"00";
when x"04B" => DATA <= x"26";
when x"04C" => DATA <= x"E7";
when x"04D" => DATA <= x"B6";
when x"04E" => DATA <= x"FE";
when x"04F" => DATA <= x"E0";
when x"050" => DATA <= x"1A";
when x"051" => DATA <= x"50";
when x"052" => DATA <= x"10";
when x"053" => DATA <= x"CE";
when x"054" => DATA <= x"FF";
when x"055" => DATA <= x"80";
when x"056" => DATA <= x"8D";
when x"057" => DATA <= x"69";
when x"058" => DATA <= x"BE";
when x"059" => DATA <= x"FF";
when x"05A" => DATA <= x"90";
when x"05B" => DATA <= x"BF";
when x"05C" => DATA <= x"FF";
when x"05D" => DATA <= x"8C";
when x"05E" => DATA <= x"1C";
when x"05F" => DATA <= x"00";
when x"060" => DATA <= x"8E";
when x"061" => DATA <= x"F8";
when x"062" => DATA <= x"16";
when x"063" => DATA <= x"BD";
when x"064" => DATA <= x"F9";
when x"065" => DATA <= x"35";
when x"066" => DATA <= x"BD";
when x"067" => DATA <= x"FF";
when x"068" => DATA <= x"E7";
when x"069" => DATA <= x"4F";
when x"06A" => DATA <= x"BD";
when x"06B" => DATA <= x"FF";
when x"06C" => DATA <= x"EE";
when x"06D" => DATA <= x"4F";
when x"06E" => DATA <= x"BD";
when x"06F" => DATA <= x"FA";
when x"070" => DATA <= x"43";
when x"071" => DATA <= x"10";
when x"072" => DATA <= x"CE";
when x"073" => DATA <= x"FF";
when x"074" => DATA <= x"80";
when x"075" => DATA <= x"8D";
when x"076" => DATA <= x"4A";
when x"077" => DATA <= x"10";
when x"078" => DATA <= x"FE";
when x"079" => DATA <= x"FF";
when x"07A" => DATA <= x"8A";
when x"07B" => DATA <= x"8E";
when x"07C" => DATA <= x"FF";
when x"07D" => DATA <= x"B9";
when x"07E" => DATA <= x"BF";
when x"07F" => DATA <= x"FF";
when x"080" => DATA <= x"90";
when x"081" => DATA <= x"1C";
when x"082" => DATA <= x"00";
when x"083" => DATA <= x"8E";
when x"084" => DATA <= x"F8";
when x"085" => DATA <= x"96";
when x"086" => DATA <= x"BD";
when x"087" => DATA <= x"F9";
when x"088" => DATA <= x"35";
when x"089" => DATA <= x"BD";
when x"08A" => DATA <= x"FF";
when x"08B" => DATA <= x"F1";
when x"08C" => DATA <= x"25";
when x"08D" => DATA <= x"14";
when x"08E" => DATA <= x"8E";
when x"08F" => DATA <= x"FF";
when x"090" => DATA <= x"00";
when x"091" => DATA <= x"BD";
when x"092" => DATA <= x"FF";
when x"093" => DATA <= x"F7";
when x"094" => DATA <= x"20";
when x"095" => DATA <= x"ED";
when x"096" => DATA <= x"36";
when x"097" => DATA <= x"38";
when x"098" => DATA <= x"30";
when x"099" => DATA <= x"39";
when x"09A" => DATA <= x"3E";
when x"09B" => DATA <= x"2A";
when x"09C" => DATA <= x"00";
when x"09D" => DATA <= x"FF";
when x"09E" => DATA <= x"00";
when x"09F" => DATA <= x"6F";
when x"0A0" => DATA <= x"20";
when x"0A1" => DATA <= x"FF";
when x"0A2" => DATA <= x"86";
when x"0A3" => DATA <= x"7E";
when x"0A4" => DATA <= x"BD";
when x"0A5" => DATA <= x"FF";
when x"0A6" => DATA <= x"F4";
when x"0A7" => DATA <= x"3F";
when x"0A8" => DATA <= x"11";
when x"0A9" => DATA <= x"45";
when x"0AA" => DATA <= x"73";
when x"0AB" => DATA <= x"63";
when x"0AC" => DATA <= x"61";
when x"0AD" => DATA <= x"70";
when x"0AE" => DATA <= x"65";
when x"0AF" => DATA <= x"00";
when x"0B0" => DATA <= x"10";
when x"0B1" => DATA <= x"FE";
when x"0B2" => DATA <= x"FF";
when x"0B3" => DATA <= x"8A";
when x"0B4" => DATA <= x"BD";
when x"0B5" => DATA <= x"FF";
when x"0B6" => DATA <= x"E7";
when x"0B7" => DATA <= x"A6";
when x"0B8" => DATA <= x"80";
when x"0B9" => DATA <= x"BD";
when x"0BA" => DATA <= x"F9";
when x"0BB" => DATA <= x"35";
when x"0BC" => DATA <= x"BD";
when x"0BD" => DATA <= x"FF";
when x"0BE" => DATA <= x"E7";
when x"0BF" => DATA <= x"20";
when x"0C0" => DATA <= x"C2";
when x"0C1" => DATA <= x"CC";
when x"0C2" => DATA <= x"00";
when x"0C3" => DATA <= x"00";
when x"0C4" => DATA <= x"FD";
when x"0C5" => DATA <= x"FF";
when x"0C6" => DATA <= x"88";
when x"0C7" => DATA <= x"CC";
when x"0C8" => DATA <= x"F8";
when x"0C9" => DATA <= x"00";
when x"0CA" => DATA <= x"FD";
when x"0CB" => DATA <= x"FF";
when x"0CC" => DATA <= x"8A";
when x"0CD" => DATA <= x"CC";
when x"0CE" => DATA <= x"F8";
when x"0CF" => DATA <= x"B0";
when x"0D0" => DATA <= x"FD";
when x"0D1" => DATA <= x"FF";
when x"0D2" => DATA <= x"FA";
when x"0D3" => DATA <= x"4D";
when x"0D4" => DATA <= x"2B";
when x"0D5" => DATA <= x"06";
when x"0D6" => DATA <= x"FC";
when x"0D7" => DATA <= x"FF";
when x"0D8" => DATA <= x"8E";
when x"0D9" => DATA <= x"FD";
when x"0DA" => DATA <= x"FF";
when x"0DB" => DATA <= x"90";
when x"0DC" => DATA <= x"CC";
when x"0DD" => DATA <= x"FE";
when x"0DE" => DATA <= x"2C";
when x"0DF" => DATA <= x"FD";
when x"0E0" => DATA <= x"FE";
when x"0E1" => DATA <= x"FA";
when x"0E2" => DATA <= x"8E";
when x"0E3" => DATA <= x"FF";
when x"0E4" => DATA <= x"FA";
when x"0E5" => DATA <= x"10";
when x"0E6" => DATA <= x"8E";
when x"0E7" => DATA <= x"FF";
when x"0E8" => DATA <= x"80";
when x"0E9" => DATA <= x"39";
when x"0EA" => DATA <= x"BD";
when x"0EB" => DATA <= x"FF";
when x"0EC" => DATA <= x"E0";
when x"0ED" => DATA <= x"7E";
when x"0EE" => DATA <= x"FF";
when x"0EF" => DATA <= x"EE";
when x"0F0" => DATA <= x"BD";
when x"0F1" => DATA <= x"FF";
when x"0F2" => DATA <= x"E7";
when x"0F3" => DATA <= x"A6";
when x"0F4" => DATA <= x"80";
when x"0F5" => DATA <= x"81";
when x"0F6" => DATA <= x"04";
when x"0F7" => DATA <= x"27";
when x"0F8" => DATA <= x"F0";
when x"0F9" => DATA <= x"BD";
when x"0FA" => DATA <= x"FF";
when x"0FB" => DATA <= x"EE";
when x"0FC" => DATA <= x"20";
when x"0FD" => DATA <= x"F5";
when x"0FE" => DATA <= x"34";
when x"0FF" => DATA <= x"32";
when x"100" => DATA <= x"86";
when x"101" => DATA <= x"80";
when x"102" => DATA <= x"8E";
when x"103" => DATA <= x"FF";
when x"104" => DATA <= x"FF";
when x"105" => DATA <= x"1F";
when x"106" => DATA <= x"12";
when x"107" => DATA <= x"BD";
when x"108" => DATA <= x"FF";
when x"109" => DATA <= x"F4";
when x"10A" => DATA <= x"8C";
when x"10B" => DATA <= x"00";
when x"10C" => DATA <= x"00";
when x"10D" => DATA <= x"35";
when x"10E" => DATA <= x"B2";
when x"10F" => DATA <= x"1F";
when x"110" => DATA <= x"10";
when x"111" => DATA <= x"8D";
when x"112" => DATA <= x"04";
when x"113" => DATA <= x"1F";
when x"114" => DATA <= x"10";
when x"115" => DATA <= x"1F";
when x"116" => DATA <= x"98";
when x"117" => DATA <= x"34";
when x"118" => DATA <= x"02";
when x"119" => DATA <= x"44";
when x"11A" => DATA <= x"44";
when x"11B" => DATA <= x"44";
when x"11C" => DATA <= x"44";
when x"11D" => DATA <= x"8D";
when x"11E" => DATA <= x"02";
when x"11F" => DATA <= x"35";
when x"120" => DATA <= x"02";
when x"121" => DATA <= x"84";
when x"122" => DATA <= x"0F";
when x"123" => DATA <= x"81";
when x"124" => DATA <= x"0A";
when x"125" => DATA <= x"25";
when x"126" => DATA <= x"02";
when x"127" => DATA <= x"8B";
when x"128" => DATA <= x"07";
when x"129" => DATA <= x"8B";
when x"12A" => DATA <= x"30";
when x"12B" => DATA <= x"7E";
when x"12C" => DATA <= x"FF";
when x"12D" => DATA <= x"EE";
when x"12E" => DATA <= x"35";
when x"12F" => DATA <= x"10";
when x"130" => DATA <= x"8D";
when x"131" => DATA <= x"03";
when x"132" => DATA <= x"34";
when x"133" => DATA <= x"10";
when x"134" => DATA <= x"39";
when x"135" => DATA <= x"A6";
when x"136" => DATA <= x"80";
when x"137" => DATA <= x"27";
when x"138" => DATA <= x"FB";
when x"139" => DATA <= x"BD";
when x"13A" => DATA <= x"FF";
when x"13B" => DATA <= x"E3";
when x"13C" => DATA <= x"20";
when x"13D" => DATA <= x"F7";
when x"13E" => DATA <= x"10";
when x"13F" => DATA <= x"8E";
when x"140" => DATA <= x"00";
when x"141" => DATA <= x"00";
when x"142" => DATA <= x"A6";
when x"143" => DATA <= x"80";
when x"144" => DATA <= x"81";
when x"145" => DATA <= x"30";
when x"146" => DATA <= x"25";
when x"147" => DATA <= x"33";
when x"148" => DATA <= x"81";
when x"149" => DATA <= x"3A";
when x"14A" => DATA <= x"25";
when x"14B" => DATA <= x"0A";
when x"14C" => DATA <= x"84";
when x"14D" => DATA <= x"DF";
when x"14E" => DATA <= x"80";
when x"14F" => DATA <= x"07";
when x"150" => DATA <= x"25";
when x"151" => DATA <= x"29";
when x"152" => DATA <= x"81";
when x"153" => DATA <= x"40";
when x"154" => DATA <= x"24";
when x"155" => DATA <= x"25";
when x"156" => DATA <= x"84";
when x"157" => DATA <= x"0F";
when x"158" => DATA <= x"1E";
when x"159" => DATA <= x"02";
when x"15A" => DATA <= x"58";
when x"15B" => DATA <= x"49";
when x"15C" => DATA <= x"58";
when x"15D" => DATA <= x"49";
when x"15E" => DATA <= x"58";
when x"15F" => DATA <= x"49";
when x"160" => DATA <= x"58";
when x"161" => DATA <= x"49";
when x"162" => DATA <= x"1E";
when x"163" => DATA <= x"12";
when x"164" => DATA <= x"1E";
when x"165" => DATA <= x"01";
when x"166" => DATA <= x"1E";
when x"167" => DATA <= x"89";
when x"168" => DATA <= x"3A";
when x"169" => DATA <= x"1E";
when x"16A" => DATA <= x"12";
when x"16B" => DATA <= x"20";
when x"16C" => DATA <= x"D5";
when x"16D" => DATA <= x"A6";
when x"16E" => DATA <= x"80";
when x"16F" => DATA <= x"81";
when x"170" => DATA <= x"21";
when x"171" => DATA <= x"24";
when x"172" => DATA <= x"FA";
when x"173" => DATA <= x"30";
when x"174" => DATA <= x"1F";
when x"175" => DATA <= x"A6";
when x"176" => DATA <= x"80";
when x"177" => DATA <= x"81";
when x"178" => DATA <= x"20";
when x"179" => DATA <= x"27";
when x"17A" => DATA <= x"FA";
when x"17B" => DATA <= x"30";
when x"17C" => DATA <= x"1F";
when x"17D" => DATA <= x"81";
when x"17E" => DATA <= x"21";
when x"17F" => DATA <= x"39";
when x"180" => DATA <= x"34";
when x"181" => DATA <= x"7C";
when x"182" => DATA <= x"33";
when x"183" => DATA <= x"78";
when x"184" => DATA <= x"11";
when x"185" => DATA <= x"8C";
when x"186" => DATA <= x"F8";
when x"187" => DATA <= x"00";
when x"188" => DATA <= x"24";
when x"189" => DATA <= x"04";
when x"18A" => DATA <= x"10";
when x"18B" => DATA <= x"CE";
when x"18C" => DATA <= x"FF";
when x"18D" => DATA <= x"80";
when x"18E" => DATA <= x"34";
when x"18F" => DATA <= x"40";
when x"190" => DATA <= x"8D";
when x"191" => DATA <= x"13";
when x"192" => DATA <= x"35";
when x"193" => DATA <= x"40";
when x"194" => DATA <= x"32";
when x"195" => DATA <= x"48";
when x"196" => DATA <= x"35";
when x"197" => DATA <= x"FC";
when x"198" => DATA <= x"48";
when x"199" => DATA <= x"45";
when x"19A" => DATA <= x"4C";
when x"19B" => DATA <= x"50";
when x"19C" => DATA <= x"80";
when x"19D" => DATA <= x"47";
when x"19E" => DATA <= x"4F";
when x"19F" => DATA <= x"81";
when x"1A0" => DATA <= x"52";
when x"1A1" => DATA <= x"55";
when x"1A2" => DATA <= x"4E";
when x"1A3" => DATA <= x"82";
when x"1A4" => DATA <= x"00";
when x"1A5" => DATA <= x"8D";
when x"1A6" => DATA <= x"CE";
when x"1A7" => DATA <= x"A6";
when x"1A8" => DATA <= x"80";
when x"1A9" => DATA <= x"81";
when x"1AA" => DATA <= x"2A";
when x"1AB" => DATA <= x"27";
when x"1AC" => DATA <= x"F8";
when x"1AD" => DATA <= x"30";
when x"1AE" => DATA <= x"1F";
when x"1AF" => DATA <= x"34";
when x"1B0" => DATA <= x"10";
when x"1B1" => DATA <= x"8D";
when x"1B2" => DATA <= x"BA";
when x"1B3" => DATA <= x"BF";
when x"1B4" => DATA <= x"FF";
when x"1B5" => DATA <= x"86";
when x"1B6" => DATA <= x"10";
when x"1B7" => DATA <= x"8E";
when x"1B8" => DATA <= x"F9";
when x"1B9" => DATA <= x"98";
when x"1BA" => DATA <= x"AE";
when x"1BB" => DATA <= x"E4";
when x"1BC" => DATA <= x"A6";
when x"1BD" => DATA <= x"84";
when x"1BE" => DATA <= x"81";
when x"1BF" => DATA <= x"41";
when x"1C0" => DATA <= x"25";
when x"1C1" => DATA <= x"75";
when x"1C2" => DATA <= x"A6";
when x"1C3" => DATA <= x"80";
when x"1C4" => DATA <= x"84";
when x"1C5" => DATA <= x"DF";
when x"1C6" => DATA <= x"A1";
when x"1C7" => DATA <= x"A0";
when x"1C8" => DATA <= x"27";
when x"1C9" => DATA <= x"F8";
when x"1CA" => DATA <= x"A6";
when x"1CB" => DATA <= x"A2";
when x"1CC" => DATA <= x"2B";
when x"1CD" => DATA <= x"16";
when x"1CE" => DATA <= x"A6";
when x"1CF" => DATA <= x"1F";
when x"1D0" => DATA <= x"81";
when x"1D1" => DATA <= x"2E";
when x"1D2" => DATA <= x"27";
when x"1D3" => DATA <= x"0A";
when x"1D4" => DATA <= x"A6";
when x"1D5" => DATA <= x"A0";
when x"1D6" => DATA <= x"2A";
when x"1D7" => DATA <= x"FC";
when x"1D8" => DATA <= x"A6";
when x"1D9" => DATA <= x"A4";
when x"1DA" => DATA <= x"26";
when x"1DB" => DATA <= x"DE";
when x"1DC" => DATA <= x"20";
when x"1DD" => DATA <= x"59";
when x"1DE" => DATA <= x"A6";
when x"1DF" => DATA <= x"A0";
when x"1E0" => DATA <= x"2A";
when x"1E1" => DATA <= x"FC";
when x"1E2" => DATA <= x"20";
when x"1E3" => DATA <= x"06";
when x"1E4" => DATA <= x"E6";
when x"1E5" => DATA <= x"82";
when x"1E6" => DATA <= x"C1";
when x"1E7" => DATA <= x"21";
when x"1E8" => DATA <= x"24";
when x"1E9" => DATA <= x"4D";
when x"1EA" => DATA <= x"81";
when x"1EB" => DATA <= x"80";
when x"1EC" => DATA <= x"27";
when x"1ED" => DATA <= x"31";
when x"1EE" => DATA <= x"81";
when x"1EF" => DATA <= x"82";
when x"1F0" => DATA <= x"27";
when x"1F1" => DATA <= x"3C";
when x"1F2" => DATA <= x"8D";
when x"1F3" => DATA <= x"81";
when x"1F4" => DATA <= x"10";
when x"1F5" => DATA <= x"BE";
when x"1F6" => DATA <= x"FF";
when x"1F7" => DATA <= x"90";
when x"1F8" => DATA <= x"81";
when x"1F9" => DATA <= x"0D";
when x"1FA" => DATA <= x"27";
when x"1FB" => DATA <= x"18";
when x"1FC" => DATA <= x"81";
when x"1FD" => DATA <= x"3B";
when x"1FE" => DATA <= x"27";
when x"1FF" => DATA <= x"12";
when x"200" => DATA <= x"BD";
when x"201" => DATA <= x"FF";
when x"202" => DATA <= x"A1";
when x"203" => DATA <= x"24";
when x"204" => DATA <= x"32";
when x"205" => DATA <= x"BD";
when x"206" => DATA <= x"F9";
when x"207" => DATA <= x"75";
when x"208" => DATA <= x"81";
when x"209" => DATA <= x"3B";
when x"20A" => DATA <= x"27";
when x"20B" => DATA <= x"06";
when x"20C" => DATA <= x"81";
when x"20D" => DATA <= x"0D";
when x"20E" => DATA <= x"26";
when x"20F" => DATA <= x"27";
when x"210" => DATA <= x"30";
when x"211" => DATA <= x"1F";
when x"212" => DATA <= x"30";
when x"213" => DATA <= x"01";
when x"214" => DATA <= x"BF";
when x"215" => DATA <= x"FF";
when x"216" => DATA <= x"86";
when x"217" => DATA <= x"35";
when x"218" => DATA <= x"10";
when x"219" => DATA <= x"1F";
when x"21A" => DATA <= x"21";
when x"21B" => DATA <= x"1A";
when x"21C" => DATA <= x"01";
when x"21D" => DATA <= x"20";
when x"21E" => DATA <= x"2C";
when x"21F" => DATA <= x"BD";
when x"220" => DATA <= x"F9";
when x"221" => DATA <= x"75";
when x"222" => DATA <= x"25";
when x"223" => DATA <= x"04";
when x"224" => DATA <= x"81";
when x"225" => DATA <= x"2E";
when x"226" => DATA <= x"26";
when x"227" => DATA <= x"0F";
when x"228" => DATA <= x"8E";
when x"229" => DATA <= x"F8";
when x"22A" => DATA <= x"16";
when x"22B" => DATA <= x"BD";
when x"22C" => DATA <= x"F9";
when x"22D" => DATA <= x"35";
when x"22E" => DATA <= x"BD";
when x"22F" => DATA <= x"F9";
when x"230" => DATA <= x"75";
when x"231" => DATA <= x"BD";
when x"232" => DATA <= x"F9";
when x"233" => DATA <= x"6D";
when x"234" => DATA <= x"BF";
when x"235" => DATA <= x"FF";
when x"236" => DATA <= x"86";
when x"237" => DATA <= x"35";
when x"238" => DATA <= x"10";
when x"239" => DATA <= x"86";
when x"23A" => DATA <= x"02";
when x"23B" => DATA <= x"BD";
when x"23C" => DATA <= x"FC";
when x"23D" => DATA <= x"F5";
when x"23E" => DATA <= x"BD";
when x"23F" => DATA <= x"FC";
when x"240" => DATA <= x"B9";
when x"241" => DATA <= x"1A";
when x"242" => DATA <= x"01";
when x"243" => DATA <= x"BD";
when x"244" => DATA <= x"FA";
when x"245" => DATA <= x"CB";
when x"246" => DATA <= x"2A";
when x"247" => DATA <= x"53";
when x"248" => DATA <= x"BE";
when x"249" => DATA <= x"FF";
when x"24A" => DATA <= x"8C";
when x"24B" => DATA <= x"34";
when x"24C" => DATA <= x"01";
when x"24D" => DATA <= x"1F";
when x"24E" => DATA <= x"12";
when x"24F" => DATA <= x"E6";
when x"250" => DATA <= x"07";
when x"251" => DATA <= x"3A";
when x"252" => DATA <= x"CE";
when x"253" => DATA <= x"FA";
when x"254" => DATA <= x"AA";
when x"255" => DATA <= x"C6";
when x"256" => DATA <= x"04";
when x"257" => DATA <= x"A6";
when x"258" => DATA <= x"80";
when x"259" => DATA <= x"A1";
when x"25A" => DATA <= x"C2";
when x"25B" => DATA <= x"26";
when x"25C" => DATA <= x"3F";
when x"25D" => DATA <= x"5A";
when x"25E" => DATA <= x"26";
when x"25F" => DATA <= x"F7";
when x"260" => DATA <= x"A6";
when x"261" => DATA <= x"26";
when x"262" => DATA <= x"48";
when x"263" => DATA <= x"2A";
when x"264" => DATA <= x"45";
when x"265" => DATA <= x"84";
when x"266" => DATA <= x"1E";
when x"267" => DATA <= x"81";
when x"268" => DATA <= x"06";
when x"269" => DATA <= x"26";
when x"26A" => DATA <= x"3F";
when x"26B" => DATA <= x"30";
when x"26C" => DATA <= x"1C";
when x"26D" => DATA <= x"BF";
when x"26E" => DATA <= x"FF";
when x"26F" => DATA <= x"82";
when x"270" => DATA <= x"FE";
when x"271" => DATA <= x"FF";
when x"272" => DATA <= x"90";
when x"273" => DATA <= x"BE";
when x"274" => DATA <= x"FF";
when x"275" => DATA <= x"8A";
when x"276" => DATA <= x"35";
when x"277" => DATA <= x"02";
when x"278" => DATA <= x"34";
when x"279" => DATA <= x"50";
when x"27A" => DATA <= x"10";
when x"27B" => DATA <= x"8C";
when x"27C" => DATA <= x"80";
when x"27D" => DATA <= x"00";
when x"27E" => DATA <= x"25";
when x"27F" => DATA <= x"04";
when x"280" => DATA <= x"10";
when x"281" => DATA <= x"BF";
when x"282" => DATA <= x"FF";
when x"283" => DATA <= x"8A";
when x"284" => DATA <= x"10";
when x"285" => DATA <= x"BF";
when x"286" => DATA <= x"FF";
when x"287" => DATA <= x"8E";
when x"288" => DATA <= x"BE";
when x"289" => DATA <= x"FF";
when x"28A" => DATA <= x"86";
when x"28B" => DATA <= x"EE";
when x"28C" => DATA <= x"66";
when x"28D" => DATA <= x"46";
when x"28E" => DATA <= x"86";
when x"28F" => DATA <= x"01";
when x"290" => DATA <= x"AD";
when x"291" => DATA <= x"A4";
when x"292" => DATA <= x"35";
when x"293" => DATA <= x"60";
when x"294" => DATA <= x"10";
when x"295" => DATA <= x"BF";
when x"296" => DATA <= x"FF";
when x"297" => DATA <= x"8A";
when x"298" => DATA <= x"FF";
when x"299" => DATA <= x"FF";
when x"29A" => DATA <= x"90";
when x"29B" => DATA <= x"39";
when x"29C" => DATA <= x"BE";
when x"29D" => DATA <= x"FF";
when x"29E" => DATA <= x"86";
when x"29F" => DATA <= x"EE";
when x"2A0" => DATA <= x"63";
when x"2A1" => DATA <= x"4F";
when x"2A2" => DATA <= x"35";
when x"2A3" => DATA <= x"01";
when x"2A4" => DATA <= x"6E";
when x"2A5" => DATA <= x"A4";
when x"2A6" => DATA <= x"29";
when x"2A7" => DATA <= x"43";
when x"2A8" => DATA <= x"28";
when x"2A9" => DATA <= x"00";
when x"2AA" => DATA <= x"35";
when x"2AB" => DATA <= x"01";
when x"2AC" => DATA <= x"10";
when x"2AD" => DATA <= x"24";
when x"2AE" => DATA <= x"05";
when x"2AF" => DATA <= x"09";
when x"2B0" => DATA <= x"BD";
when x"2B1" => DATA <= x"F8";
when x"2B2" => DATA <= x"CD";
when x"2B3" => DATA <= x"3F";
when x"2B4" => DATA <= x"F9";
when x"2B5" => DATA <= x"4E";
when x"2B6" => DATA <= x"6F";
when x"2B7" => DATA <= x"74";
when x"2B8" => DATA <= x"20";
when x"2B9" => DATA <= x"36";
when x"2BA" => DATA <= x"38";
when x"2BB" => DATA <= x"30";
when x"2BC" => DATA <= x"39";
when x"2BD" => DATA <= x"20";
when x"2BE" => DATA <= x"63";
when x"2BF" => DATA <= x"6F";
when x"2C0" => DATA <= x"64";
when x"2C1" => DATA <= x"65";
when x"2C2" => DATA <= x"00";
when x"2C3" => DATA <= x"4F";
when x"2C4" => DATA <= x"BD";
when x"2C5" => DATA <= x"FC";
when x"2C6" => DATA <= x"F5";
when x"2C7" => DATA <= x"8D";
when x"2C8" => DATA <= x"02";
when x"2C9" => DATA <= x"8B";
when x"2CA" => DATA <= x"80";
when x"2CB" => DATA <= x"B6";
when x"2CC" => DATA <= x"FE";
when x"2CD" => DATA <= x"E2";
when x"2CE" => DATA <= x"2A";
when x"2CF" => DATA <= x"FB";
when x"2D0" => DATA <= x"B6";
when x"2D1" => DATA <= x"FE";
when x"2D2" => DATA <= x"E3";
when x"2D3" => DATA <= x"39";
when x"2D4" => DATA <= x"34";
when x"2D5" => DATA <= x"06";
when x"2D6" => DATA <= x"4D";
when x"2D7" => DATA <= x"2B";
when x"2D8" => DATA <= x"23";
when x"2D9" => DATA <= x"86";
when x"2DA" => DATA <= x"04";
when x"2DB" => DATA <= x"BD";
when x"2DC" => DATA <= x"FC";
when x"2DD" => DATA <= x"F5";
when x"2DE" => DATA <= x"1F";
when x"2DF" => DATA <= x"10";
when x"2E0" => DATA <= x"BD";
when x"2E1" => DATA <= x"FC";
when x"2E2" => DATA <= x"F3";
when x"2E3" => DATA <= x"35";
when x"2E4" => DATA <= x"06";
when x"2E5" => DATA <= x"34";
when x"2E6" => DATA <= x"06";
when x"2E7" => DATA <= x"BD";
when x"2E8" => DATA <= x"FC";
when x"2E9" => DATA <= x"F5";
when x"2EA" => DATA <= x"8D";
when x"2EB" => DATA <= x"DF";
when x"2EC" => DATA <= x"1F";
when x"2ED" => DATA <= x"89";
when x"2EE" => DATA <= x"4F";
when x"2EF" => DATA <= x"1F";
when x"2F0" => DATA <= x"01";
when x"2F1" => DATA <= x"35";
when x"2F2" => DATA <= x"86";
when x"2F3" => DATA <= x"8E";
when x"2F4" => DATA <= x"F8";
when x"2F5" => DATA <= x"16";
when x"2F6" => DATA <= x"BF";
when x"2F7" => DATA <= x"FF";
when x"2F8" => DATA <= x"86";
when x"2F9" => DATA <= x"7E";
when x"2FA" => DATA <= x"FA";
when x"2FB" => DATA <= x"41";
when x"2FC" => DATA <= x"81";
when x"2FD" => DATA <= x"82";
when x"2FE" => DATA <= x"27";
when x"2FF" => DATA <= x"39";
when x"300" => DATA <= x"81";
when x"301" => DATA <= x"83";
when x"302" => DATA <= x"27";
when x"303" => DATA <= x"37";
when x"304" => DATA <= x"81";
when x"305" => DATA <= x"84";
when x"306" => DATA <= x"27";
when x"307" => DATA <= x"33";
when x"308" => DATA <= x"86";
when x"309" => DATA <= x"06";
when x"30A" => DATA <= x"BD";
when x"30B" => DATA <= x"FC";
when x"30C" => DATA <= x"F5";
when x"30D" => DATA <= x"1F";
when x"30E" => DATA <= x"10";
when x"30F" => DATA <= x"BD";
when x"310" => DATA <= x"FC";
when x"311" => DATA <= x"F3";
when x"312" => DATA <= x"BD";
when x"313" => DATA <= x"FC";
when x"314" => DATA <= x"F1";
when x"315" => DATA <= x"35";
when x"316" => DATA <= x"06";
when x"317" => DATA <= x"BD";
when x"318" => DATA <= x"FC";
when x"319" => DATA <= x"F5";
when x"31A" => DATA <= x"81";
when x"31B" => DATA <= x"9D";
when x"31C" => DATA <= x"27";
when x"31D" => DATA <= x"B5";
when x"31E" => DATA <= x"81";
when x"31F" => DATA <= x"8E";
when x"320" => DATA <= x"27";
when x"321" => DATA <= x"D1";
when x"322" => DATA <= x"34";
when x"323" => DATA <= x"06";
when x"324" => DATA <= x"8D";
when x"325" => DATA <= x"A5";
when x"326" => DATA <= x"8B";
when x"327" => DATA <= x"80";
when x"328" => DATA <= x"34";
when x"329" => DATA <= x"01";
when x"32A" => DATA <= x"8D";
when x"32B" => DATA <= x"9F";
when x"32C" => DATA <= x"1F";
when x"32D" => DATA <= x"89";
when x"32E" => DATA <= x"4F";
when x"32F" => DATA <= x"1F";
when x"330" => DATA <= x"02";
when x"331" => DATA <= x"8D";
when x"332" => DATA <= x"98";
when x"333" => DATA <= x"1E";
when x"334" => DATA <= x"89";
when x"335" => DATA <= x"1F";
when x"336" => DATA <= x"01";
when x"337" => DATA <= x"35";
when x"338" => DATA <= x"87";
when x"339" => DATA <= x"86";
when x"33A" => DATA <= x"88";
when x"33B" => DATA <= x"48";
when x"33C" => DATA <= x"8E";
when x"33D" => DATA <= x"FF";
when x"33E" => DATA <= x"82";
when x"33F" => DATA <= x"EC";
when x"340" => DATA <= x"86";
when x"341" => DATA <= x"1F";
when x"342" => DATA <= x"01";
when x"343" => DATA <= x"1F";
when x"344" => DATA <= x"89";
when x"345" => DATA <= x"4F";
when x"346" => DATA <= x"1F";
when x"347" => DATA <= x"02";
when x"348" => DATA <= x"35";
when x"349" => DATA <= x"86";
when x"34A" => DATA <= x"4D";
when x"34B" => DATA <= x"27";
when x"34C" => DATA <= x"5C";
when x"34D" => DATA <= x"34";
when x"34E" => DATA <= x"26";
when x"34F" => DATA <= x"34";
when x"350" => DATA <= x"10";
when x"351" => DATA <= x"1F";
when x"352" => DATA <= x"89";
when x"353" => DATA <= x"86";
when x"354" => DATA <= x"08";
when x"355" => DATA <= x"BD";
when x"356" => DATA <= x"FC";
when x"357" => DATA <= x"F5";
when x"358" => DATA <= x"BD";
when x"359" => DATA <= x"FC";
when x"35A" => DATA <= x"F3";
when x"35B" => DATA <= x"5D";
when x"35C" => DATA <= x"2A";
when x"35D" => DATA <= x"04";
when x"35E" => DATA <= x"A6";
when x"35F" => DATA <= x"84";
when x"360" => DATA <= x"20";
when x"361" => DATA <= x"0C";
when x"362" => DATA <= x"86";
when x"363" => DATA <= x"10";
when x"364" => DATA <= x"C1";
when x"365" => DATA <= x"15";
when x"366" => DATA <= x"24";
when x"367" => DATA <= x"06";
when x"368" => DATA <= x"8E";
when x"369" => DATA <= x"FB";
when x"36A" => DATA <= x"D8";
when x"36B" => DATA <= x"3A";
when x"36C" => DATA <= x"A6";
when x"36D" => DATA <= x"84";
when x"36E" => DATA <= x"35";
when x"36F" => DATA <= x"10";
when x"370" => DATA <= x"BD";
when x"371" => DATA <= x"FC";
when x"372" => DATA <= x"F5";
when x"373" => DATA <= x"1F";
when x"374" => DATA <= x"02";
when x"375" => DATA <= x"1E";
when x"376" => DATA <= x"89";
when x"377" => DATA <= x"4F";
when x"378" => DATA <= x"1E";
when x"379" => DATA <= x"02";
when x"37A" => DATA <= x"4A";
when x"37B" => DATA <= x"2B";
when x"37C" => DATA <= x"03";
when x"37D" => DATA <= x"BD";
when x"37E" => DATA <= x"FC";
when x"37F" => DATA <= x"C2";
when x"380" => DATA <= x"34";
when x"381" => DATA <= x"10";
when x"382" => DATA <= x"5D";
when x"383" => DATA <= x"2A";
when x"384" => DATA <= x"04";
when x"385" => DATA <= x"A6";
when x"386" => DATA <= x"01";
when x"387" => DATA <= x"20";
when x"388" => DATA <= x"0C";
when x"389" => DATA <= x"86";
when x"38A" => DATA <= x"10";
when x"38B" => DATA <= x"C1";
when x"38C" => DATA <= x"15";
when x"38D" => DATA <= x"24";
when x"38E" => DATA <= x"06";
when x"38F" => DATA <= x"8E";
when x"390" => DATA <= x"FB";
when x"391" => DATA <= x"EC";
when x"392" => DATA <= x"3A";
when x"393" => DATA <= x"A6";
when x"394" => DATA <= x"84";
when x"395" => DATA <= x"35";
when x"396" => DATA <= x"10";
when x"397" => DATA <= x"BD";
when x"398" => DATA <= x"FC";
when x"399" => DATA <= x"F5";
when x"39A" => DATA <= x"1F";
when x"39B" => DATA <= x"02";
when x"39C" => DATA <= x"1E";
when x"39D" => DATA <= x"89";
when x"39E" => DATA <= x"4F";
when x"39F" => DATA <= x"1E";
when x"3A0" => DATA <= x"02";
when x"3A1" => DATA <= x"4A";
when x"3A2" => DATA <= x"2B";
when x"3A3" => DATA <= x"03";
when x"3A4" => DATA <= x"BD";
when x"3A5" => DATA <= x"FC";
when x"3A6" => DATA <= x"D2";
when x"3A7" => DATA <= x"35";
when x"3A8" => DATA <= x"A6";
when x"3A9" => DATA <= x"86";
when x"3AA" => DATA <= x"0A";
when x"3AB" => DATA <= x"BD";
when x"3AC" => DATA <= x"FC";
when x"3AD" => DATA <= x"F5";
when x"3AE" => DATA <= x"30";
when x"3AF" => DATA <= x"02";
when x"3B0" => DATA <= x"10";
when x"3B1" => DATA <= x"8E";
when x"3B2" => DATA <= x"00";
when x"3B3" => DATA <= x"03";
when x"3B4" => DATA <= x"BD";
when x"3B5" => DATA <= x"FC";
when x"3B6" => DATA <= x"C2";
when x"3B7" => DATA <= x"30";
when x"3B8" => DATA <= x"1E";
when x"3B9" => DATA <= x"86";
when x"3BA" => DATA <= x"07";
when x"3BB" => DATA <= x"BD";
when x"3BC" => DATA <= x"FC";
when x"3BD" => DATA <= x"F5";
when x"3BE" => DATA <= x"4F";
when x"3BF" => DATA <= x"BD";
when x"3C0" => DATA <= x"FC";
when x"3C1" => DATA <= x"F5";
when x"3C2" => DATA <= x"BD";
when x"3C3" => DATA <= x"FA";
when x"3C4" => DATA <= x"CB";
when x"3C5" => DATA <= x"8B";
when x"3C6" => DATA <= x"80";
when x"3C7" => DATA <= x"25";
when x"3C8" => DATA <= x"0F";
when x"3C9" => DATA <= x"AE";
when x"3CA" => DATA <= x"84";
when x"3CB" => DATA <= x"BD";
when x"3CC" => DATA <= x"FA";
when x"3CD" => DATA <= x"CB";
when x"3CE" => DATA <= x"A7";
when x"3CF" => DATA <= x"80";
when x"3D0" => DATA <= x"31";
when x"3D1" => DATA <= x"21";
when x"3D2" => DATA <= x"81";
when x"3D3" => DATA <= x"0D";
when x"3D4" => DATA <= x"26";
when x"3D5" => DATA <= x"F5";
when x"3D6" => DATA <= x"31";
when x"3D7" => DATA <= x"3F";
when x"3D8" => DATA <= x"39";
when x"3D9" => DATA <= x"00";
when x"3DA" => DATA <= x"05";
when x"3DB" => DATA <= x"00";
when x"3DC" => DATA <= x"05";
when x"3DD" => DATA <= x"04";
when x"3DE" => DATA <= x"05";
when x"3DF" => DATA <= x"08";
when x"3E0" => DATA <= x"0E";
when x"3E1" => DATA <= x"04";
when x"3E2" => DATA <= x"01";
when x"3E3" => DATA <= x"01";
when x"3E4" => DATA <= x"05";
when x"3E5" => DATA <= x"00";
when x"3E6" => DATA <= x"10";
when x"3E7" => DATA <= x"20";
when x"3E8" => DATA <= x"10";
when x"3E9" => DATA <= x"0D";
when x"3EA" => DATA <= x"00";
when x"3EB" => DATA <= x"04";
when x"3EC" => DATA <= x"80";
when x"3ED" => DATA <= x"05";
when x"3EE" => DATA <= x"00";
when x"3EF" => DATA <= x"05";
when x"3F0" => DATA <= x"00";
when x"3F1" => DATA <= x"05";
when x"3F2" => DATA <= x"00";
when x"3F3" => DATA <= x"00";
when x"3F4" => DATA <= x"00";
when x"3F5" => DATA <= x"05";
when x"3F6" => DATA <= x"09";
when x"3F7" => DATA <= x"05";
when x"3F8" => DATA <= x"00";
when x"3F9" => DATA <= x"08";
when x"3FA" => DATA <= x"19";
when x"3FB" => DATA <= x"00";
when x"3FC" => DATA <= x"01";
when x"3FD" => DATA <= x"0D";
when x"3FE" => DATA <= x"80";
when x"3FF" => DATA <= x"04";
when x"400" => DATA <= x"80";
when x"401" => DATA <= x"34";
when x"402" => DATA <= x"26";
when x"403" => DATA <= x"86";
when x"404" => DATA <= x"0C";
when x"405" => DATA <= x"BD";
when x"406" => DATA <= x"FC";
when x"407" => DATA <= x"F5";
when x"408" => DATA <= x"BD";
when x"409" => DATA <= x"FC";
when x"40A" => DATA <= x"F1";
when x"40B" => DATA <= x"10";
when x"40C" => DATA <= x"8E";
when x"40D" => DATA <= x"00";
when x"40E" => DATA <= x"04";
when x"40F" => DATA <= x"BD";
when x"410" => DATA <= x"FC";
when x"411" => DATA <= x"C2";
when x"412" => DATA <= x"35";
when x"413" => DATA <= x"06";
when x"414" => DATA <= x"BD";
when x"415" => DATA <= x"FC";
when x"416" => DATA <= x"F5";
when x"417" => DATA <= x"BD";
when x"418" => DATA <= x"FA";
when x"419" => DATA <= x"CB";
when x"41A" => DATA <= x"34";
when x"41B" => DATA <= x"02";
when x"41C" => DATA <= x"10";
when x"41D" => DATA <= x"8E";
when x"41E" => DATA <= x"00";
when x"41F" => DATA <= x"04";
when x"420" => DATA <= x"BD";
when x"421" => DATA <= x"FC";
when x"422" => DATA <= x"D2";
when x"423" => DATA <= x"35";
when x"424" => DATA <= x"A2";
when x"425" => DATA <= x"34";
when x"426" => DATA <= x"04";
when x"427" => DATA <= x"86";
when x"428" => DATA <= x"0E";
when x"429" => DATA <= x"BD";
when x"42A" => DATA <= x"FC";
when x"42B" => DATA <= x"F5";
when x"42C" => DATA <= x"BD";
when x"42D" => DATA <= x"FC";
when x"42E" => DATA <= x"F1";
when x"42F" => DATA <= x"35";
when x"430" => DATA <= x"04";
when x"431" => DATA <= x"7E";
when x"432" => DATA <= x"FA";
when x"433" => DATA <= x"C7";
when x"434" => DATA <= x"34";
when x"435" => DATA <= x"06";
when x"436" => DATA <= x"86";
when x"437" => DATA <= x"10";
when x"438" => DATA <= x"BD";
when x"439" => DATA <= x"FC";
when x"43A" => DATA <= x"F5";
when x"43B" => DATA <= x"BD";
when x"43C" => DATA <= x"FC";
when x"43D" => DATA <= x"F1";
when x"43E" => DATA <= x"35";
when x"43F" => DATA <= x"06";
when x"440" => DATA <= x"34";
when x"441" => DATA <= x"06";
when x"442" => DATA <= x"BD";
when x"443" => DATA <= x"FC";
when x"444" => DATA <= x"F5";
when x"445" => DATA <= x"BD";
when x"446" => DATA <= x"FA";
when x"447" => DATA <= x"CB";
when x"448" => DATA <= x"35";
when x"449" => DATA <= x"86";
when x"44A" => DATA <= x"34";
when x"44B" => DATA <= x"06";
when x"44C" => DATA <= x"86";
when x"44D" => DATA <= x"12";
when x"44E" => DATA <= x"BD";
when x"44F" => DATA <= x"FC";
when x"450" => DATA <= x"F5";
when x"451" => DATA <= x"35";
when x"452" => DATA <= x"06";
when x"453" => DATA <= x"BD";
when x"454" => DATA <= x"FC";
when x"455" => DATA <= x"F5";
when x"456" => DATA <= x"4D";
when x"457" => DATA <= x"27";
when x"458" => DATA <= x"06";
when x"459" => DATA <= x"BD";
when x"45A" => DATA <= x"FC";
when x"45B" => DATA <= x"B9";
when x"45C" => DATA <= x"7E";
when x"45D" => DATA <= x"FA";
when x"45E" => DATA <= x"CB";
when x"45F" => DATA <= x"34";
when x"460" => DATA <= x"04";
when x"461" => DATA <= x"BD";
when x"462" => DATA <= x"FC";
when x"463" => DATA <= x"F1";
when x"464" => DATA <= x"BD";
when x"465" => DATA <= x"FA";
when x"466" => DATA <= x"CB";
when x"467" => DATA <= x"4F";
when x"468" => DATA <= x"35";
when x"469" => DATA <= x"84";
when x"46A" => DATA <= x"34";
when x"46B" => DATA <= x"32";
when x"46C" => DATA <= x"86";
when x"46D" => DATA <= x"14";
when x"46E" => DATA <= x"BD";
when x"46F" => DATA <= x"FC";
when x"470" => DATA <= x"F5";
when x"471" => DATA <= x"30";
when x"472" => DATA <= x"02";
when x"473" => DATA <= x"10";
when x"474" => DATA <= x"8E";
when x"475" => DATA <= x"00";
when x"476" => DATA <= x"10";
when x"477" => DATA <= x"BD";
when x"478" => DATA <= x"FC";
when x"479" => DATA <= x"C2";
when x"47A" => DATA <= x"30";
when x"47B" => DATA <= x"1E";
when x"47C" => DATA <= x"AE";
when x"47D" => DATA <= x"84";
when x"47E" => DATA <= x"BD";
when x"47F" => DATA <= x"FC";
when x"480" => DATA <= x"B9";
when x"481" => DATA <= x"35";
when x"482" => DATA <= x"02";
when x"483" => DATA <= x"BD";
when x"484" => DATA <= x"FC";
when x"485" => DATA <= x"F5";
when x"486" => DATA <= x"BD";
when x"487" => DATA <= x"FA";
when x"488" => DATA <= x"CB";
when x"489" => DATA <= x"35";
when x"48A" => DATA <= x"10";
when x"48B" => DATA <= x"34";
when x"48C" => DATA <= x"02";
when x"48D" => DATA <= x"30";
when x"48E" => DATA <= x"02";
when x"48F" => DATA <= x"10";
when x"490" => DATA <= x"8E";
when x"491" => DATA <= x"00";
when x"492" => DATA <= x"10";
when x"493" => DATA <= x"BD";
when x"494" => DATA <= x"FC";
when x"495" => DATA <= x"D2";
when x"496" => DATA <= x"30";
when x"497" => DATA <= x"1E";
when x"498" => DATA <= x"35";
when x"499" => DATA <= x"A2";
when x"49A" => DATA <= x"34";
when x"49B" => DATA <= x"22";
when x"49C" => DATA <= x"86";
when x"49D" => DATA <= x"16";
when x"49E" => DATA <= x"BD";
when x"49F" => DATA <= x"FC";
when x"4A0" => DATA <= x"F5";
when x"4A1" => DATA <= x"10";
when x"4A2" => DATA <= x"8E";
when x"4A3" => DATA <= x"00";
when x"4A4" => DATA <= x"0D";
when x"4A5" => DATA <= x"BD";
when x"4A6" => DATA <= x"FC";
when x"4A7" => DATA <= x"C2";
when x"4A8" => DATA <= x"35";
when x"4A9" => DATA <= x"02";
when x"4AA" => DATA <= x"BD";
when x"4AB" => DATA <= x"FC";
when x"4AC" => DATA <= x"F5";
when x"4AD" => DATA <= x"10";
when x"4AE" => DATA <= x"8E";
when x"4AF" => DATA <= x"00";
when x"4B0" => DATA <= x"0D";
when x"4B1" => DATA <= x"BD";
when x"4B2" => DATA <= x"FC";
when x"4B3" => DATA <= x"D2";
when x"4B4" => DATA <= x"35";
when x"4B5" => DATA <= x"20";
when x"4B6" => DATA <= x"7E";
when x"4B7" => DATA <= x"FA";
when x"4B8" => DATA <= x"C7";
when x"4B9" => DATA <= x"A6";
when x"4BA" => DATA <= x"80";
when x"4BB" => DATA <= x"8D";
when x"4BC" => DATA <= x"38";
when x"4BD" => DATA <= x"81";
when x"4BE" => DATA <= x"0D";
when x"4BF" => DATA <= x"26";
when x"4C0" => DATA <= x"F8";
when x"4C1" => DATA <= x"39";
when x"4C2" => DATA <= x"34";
when x"4C3" => DATA <= x"04";
when x"4C4" => DATA <= x"1F";
when x"4C5" => DATA <= x"20";
when x"4C6" => DATA <= x"3A";
when x"4C7" => DATA <= x"35";
when x"4C8" => DATA <= x"04";
when x"4C9" => DATA <= x"A6";
when x"4CA" => DATA <= x"82";
when x"4CB" => DATA <= x"8D";
when x"4CC" => DATA <= x"28";
when x"4CD" => DATA <= x"31";
when x"4CE" => DATA <= x"3F";
when x"4CF" => DATA <= x"26";
when x"4D0" => DATA <= x"F8";
when x"4D1" => DATA <= x"39";
when x"4D2" => DATA <= x"34";
when x"4D3" => DATA <= x"04";
when x"4D4" => DATA <= x"1F";
when x"4D5" => DATA <= x"20";
when x"4D6" => DATA <= x"3A";
when x"4D7" => DATA <= x"35";
when x"4D8" => DATA <= x"04";
when x"4D9" => DATA <= x"BD";
when x"4DA" => DATA <= x"FA";
when x"4DB" => DATA <= x"CB";
when x"4DC" => DATA <= x"A7";
when x"4DD" => DATA <= x"82";
when x"4DE" => DATA <= x"31";
when x"4DF" => DATA <= x"3F";
when x"4E0" => DATA <= x"26";
when x"4E1" => DATA <= x"F7";
when x"4E2" => DATA <= x"39";
when x"4E3" => DATA <= x"34";
when x"4E4" => DATA <= x"02";
when x"4E5" => DATA <= x"B6";
when x"4E6" => DATA <= x"FE";
when x"4E7" => DATA <= x"E0";
when x"4E8" => DATA <= x"48";
when x"4E9" => DATA <= x"2A";
when x"4EA" => DATA <= x"FA";
when x"4EB" => DATA <= x"35";
when x"4EC" => DATA <= x"02";
when x"4ED" => DATA <= x"B7";
when x"4EE" => DATA <= x"FE";
when x"4EF" => DATA <= x"E1";
when x"4F0" => DATA <= x"39";
when x"4F1" => DATA <= x"1F";
when x"4F2" => DATA <= x"20";
when x"4F3" => DATA <= x"1F";
when x"4F4" => DATA <= x"98";
when x"4F5" => DATA <= x"34";
when x"4F6" => DATA <= x"02";
when x"4F7" => DATA <= x"B6";
when x"4F8" => DATA <= x"FE";
when x"4F9" => DATA <= x"E2";
when x"4FA" => DATA <= x"48";
when x"4FB" => DATA <= x"2A";
when x"4FC" => DATA <= x"FA";
when x"4FD" => DATA <= x"35";
when x"4FE" => DATA <= x"02";
when x"4FF" => DATA <= x"B7";
when x"500" => DATA <= x"FE";
when x"501" => DATA <= x"E3";
when x"502" => DATA <= x"39";
when x"503" => DATA <= x"34";
when x"504" => DATA <= x"02";
when x"505" => DATA <= x"B6";
when x"506" => DATA <= x"FE";
when x"507" => DATA <= x"E6";
when x"508" => DATA <= x"2B";
when x"509" => DATA <= x"51";
when x"50A" => DATA <= x"B6";
when x"50B" => DATA <= x"FE";
when x"50C" => DATA <= x"E0";
when x"50D" => DATA <= x"2B";
when x"50E" => DATA <= x"06";
when x"50F" => DATA <= x"35";
when x"510" => DATA <= x"02";
when x"511" => DATA <= x"6E";
when x"512" => DATA <= x"9F";
when x"513" => DATA <= x"FF";
when x"514" => DATA <= x"B1";
when x"515" => DATA <= x"B6";
when x"516" => DATA <= x"FE";
when x"517" => DATA <= x"E1";
when x"518" => DATA <= x"2B";
when x"519" => DATA <= x"1B";
when x"51A" => DATA <= x"35";
when x"51B" => DATA <= x"02";
when x"51C" => DATA <= x"34";
when x"51D" => DATA <= x"76";
when x"51E" => DATA <= x"8D";
when x"51F" => DATA <= x"1C";
when x"520" => DATA <= x"1F";
when x"521" => DATA <= x"89";
when x"522" => DATA <= x"4F";
when x"523" => DATA <= x"1F";
when x"524" => DATA <= x"02";
when x"525" => DATA <= x"8D";
when x"526" => DATA <= x"15";
when x"527" => DATA <= x"1F";
when x"528" => DATA <= x"89";
when x"529" => DATA <= x"4F";
when x"52A" => DATA <= x"1F";
when x"52B" => DATA <= x"01";
when x"52C" => DATA <= x"8D";
when x"52D" => DATA <= x"0E";
when x"52E" => DATA <= x"AD";
when x"52F" => DATA <= x"9F";
when x"530" => DATA <= x"FF";
when x"531" => DATA <= x"FC";
when x"532" => DATA <= x"35";
when x"533" => DATA <= x"76";
when x"534" => DATA <= x"3B";
when x"535" => DATA <= x"48";
when x"536" => DATA <= x"B7";
when x"537" => DATA <= x"FF";
when x"538" => DATA <= x"80";
when x"539" => DATA <= x"35";
when x"53A" => DATA <= x"02";
when x"53B" => DATA <= x"3B";
when x"53C" => DATA <= x"B6";
when x"53D" => DATA <= x"FE";
when x"53E" => DATA <= x"E6";
when x"53F" => DATA <= x"2A";
when x"540" => DATA <= x"02";
when x"541" => DATA <= x"8D";
when x"542" => DATA <= x"12";
when x"543" => DATA <= x"B6";
when x"544" => DATA <= x"FE";
when x"545" => DATA <= x"E0";
when x"546" => DATA <= x"2A";
when x"547" => DATA <= x"F4";
when x"548" => DATA <= x"B6";
when x"549" => DATA <= x"FE";
when x"54A" => DATA <= x"E1";
when x"54B" => DATA <= x"39";
when x"54C" => DATA <= x"B6";
when x"54D" => DATA <= x"FE";
when x"54E" => DATA <= x"E6";
when x"54F" => DATA <= x"2A";
when x"550" => DATA <= x"FB";
when x"551" => DATA <= x"B6";
when x"552" => DATA <= x"FE";
when x"553" => DATA <= x"E7";
when x"554" => DATA <= x"39";
when x"555" => DATA <= x"1C";
when x"556" => DATA <= x"7F";
when x"557" => DATA <= x"34";
when x"558" => DATA <= x"01";
when x"559" => DATA <= x"34";
when x"55A" => DATA <= x"02";
when x"55B" => DATA <= x"35";
when x"55C" => DATA <= x"02";
when x"55D" => DATA <= x"34";
when x"55E" => DATA <= x"16";
when x"55F" => DATA <= x"B6";
when x"560" => DATA <= x"FE";
when x"561" => DATA <= x"E7";
when x"562" => DATA <= x"2A";
when x"563" => DATA <= x"22";
when x"564" => DATA <= x"10";
when x"565" => DATA <= x"CE";
when x"566" => DATA <= x"FF";
when x"567" => DATA <= x"80";
when x"568" => DATA <= x"8E";
when x"569" => DATA <= x"FF";
when x"56A" => DATA <= x"00";
when x"56B" => DATA <= x"BD";
when x"56C" => DATA <= x"FA";
when x"56D" => DATA <= x"CB";
when x"56E" => DATA <= x"86";
when x"56F" => DATA <= x"3F";
when x"570" => DATA <= x"A7";
when x"571" => DATA <= x"80";
when x"572" => DATA <= x"BD";
when x"573" => DATA <= x"FA";
when x"574" => DATA <= x"CB";
when x"575" => DATA <= x"A7";
when x"576" => DATA <= x"80";
when x"577" => DATA <= x"BD";
when x"578" => DATA <= x"FA";
when x"579" => DATA <= x"CB";
when x"57A" => DATA <= x"A7";
when x"57B" => DATA <= x"80";
when x"57C" => DATA <= x"26";
when x"57D" => DATA <= x"F9";
when x"57E" => DATA <= x"8E";
when x"57F" => DATA <= x"FF";
when x"580" => DATA <= x"01";
when x"581" => DATA <= x"34";
when x"582" => DATA <= x"10";
when x"583" => DATA <= x"7E";
when x"584" => DATA <= x"FF";
when x"585" => DATA <= x"BC";
when x"586" => DATA <= x"34";
when x"587" => DATA <= x"02";
when x"588" => DATA <= x"8D";
when x"589" => DATA <= x"C2";
when x"58A" => DATA <= x"35";
when x"58B" => DATA <= x"02";
when x"58C" => DATA <= x"81";
when x"58D" => DATA <= x"05";
when x"58E" => DATA <= x"26";
when x"58F" => DATA <= x"06";
when x"590" => DATA <= x"7F";
when x"591" => DATA <= x"FF";
when x"592" => DATA <= x"94";
when x"593" => DATA <= x"35";
when x"594" => DATA <= x"16";
when x"595" => DATA <= x"3B";
when x"596" => DATA <= x"34";
when x"597" => DATA <= x"02";
when x"598" => DATA <= x"8D";
when x"599" => DATA <= x"B2";
when x"59A" => DATA <= x"8D";
when x"59B" => DATA <= x"B0";
when x"59C" => DATA <= x"8D";
when x"59D" => DATA <= x"AE";
when x"59E" => DATA <= x"1E";
when x"59F" => DATA <= x"89";
when x"5A0" => DATA <= x"8D";
when x"5A1" => DATA <= x"AA";
when x"5A2" => DATA <= x"1E";
when x"5A3" => DATA <= x"89";
when x"5A4" => DATA <= x"1F";
when x"5A5" => DATA <= x"01";
when x"5A6" => DATA <= x"86";
when x"5A7" => DATA <= x"FF";
when x"5A8" => DATA <= x"B7";
when x"5A9" => DATA <= x"FF";
when x"5AA" => DATA <= x"94";
when x"5AB" => DATA <= x"8D";
when x"5AC" => DATA <= x"9F";
when x"5AD" => DATA <= x"1C";
when x"5AE" => DATA <= x"BF";
when x"5AF" => DATA <= x"A6";
when x"5B0" => DATA <= x"E0";
when x"5B1" => DATA <= x"27";
when x"5B2" => DATA <= x"66";
when x"5B3" => DATA <= x"81";
when x"5B4" => DATA <= x"02";
when x"5B5" => DATA <= x"25";
when x"5B6" => DATA <= x"55";
when x"5B7" => DATA <= x"27";
when x"5B8" => DATA <= x"43";
when x"5B9" => DATA <= x"81";
when x"5BA" => DATA <= x"04";
when x"5BB" => DATA <= x"25";
when x"5BC" => DATA <= x"2F";
when x"5BD" => DATA <= x"27";
when x"5BE" => DATA <= x"67";
when x"5BF" => DATA <= x"5F";
when x"5C0" => DATA <= x"81";
when x"5C1" => DATA <= x"07";
when x"5C2" => DATA <= x"25";
when x"5C3" => DATA <= x"11";
when x"5C4" => DATA <= x"26";
when x"5C5" => DATA <= x"63";
when x"5C6" => DATA <= x"B6";
when x"5C7" => DATA <= x"FE";
when x"5C8" => DATA <= x"E4";
when x"5C9" => DATA <= x"2A";
when x"5CA" => DATA <= x"FB";
when x"5CB" => DATA <= x"B6";
when x"5CC" => DATA <= x"FE";
when x"5CD" => DATA <= x"E5";
when x"5CE" => DATA <= x"A7";
when x"5CF" => DATA <= x"80";
when x"5D0" => DATA <= x"5A";
when x"5D1" => DATA <= x"26";
when x"5D2" => DATA <= x"F3";
when x"5D3" => DATA <= x"20";
when x"5D4" => DATA <= x"54";
when x"5D5" => DATA <= x"B6";
when x"5D6" => DATA <= x"FE";
when x"5D7" => DATA <= x"E4";
when x"5D8" => DATA <= x"2A";
when x"5D9" => DATA <= x"FB";
when x"5DA" => DATA <= x"A6";
when x"5DB" => DATA <= x"80";
when x"5DC" => DATA <= x"B7";
when x"5DD" => DATA <= x"FE";
when x"5DE" => DATA <= x"E5";
when x"5DF" => DATA <= x"5A";
when x"5E0" => DATA <= x"26";
when x"5E1" => DATA <= x"F3";
when x"5E2" => DATA <= x"B6";
when x"5E3" => DATA <= x"FE";
when x"5E4" => DATA <= x"E4";
when x"5E5" => DATA <= x"2A";
when x"5E6" => DATA <= x"FB";
when x"5E7" => DATA <= x"B7";
when x"5E8" => DATA <= x"FE";
when x"5E9" => DATA <= x"E5";
when x"5EA" => DATA <= x"20";
when x"5EB" => DATA <= x"3D";
when x"5EC" => DATA <= x"13";
when x"5ED" => DATA <= x"B6";
when x"5EE" => DATA <= x"FF";
when x"5EF" => DATA <= x"94";
when x"5F0" => DATA <= x"27";
when x"5F1" => DATA <= x"37";
when x"5F2" => DATA <= x"B6";
when x"5F3" => DATA <= x"FE";
when x"5F4" => DATA <= x"E5";
when x"5F5" => DATA <= x"F6";
when x"5F6" => DATA <= x"FE";
when x"5F7" => DATA <= x"E5";
when x"5F8" => DATA <= x"ED";
when x"5F9" => DATA <= x"81";
when x"5FA" => DATA <= x"20";
when x"5FB" => DATA <= x"F0";
when x"5FC" => DATA <= x"13";
when x"5FD" => DATA <= x"B6";
when x"5FE" => DATA <= x"FF";
when x"5FF" => DATA <= x"94";
when x"600" => DATA <= x"27";
when x"601" => DATA <= x"27";
when x"602" => DATA <= x"EC";
when x"603" => DATA <= x"81";
when x"604" => DATA <= x"B7";
when x"605" => DATA <= x"FE";
when x"606" => DATA <= x"E5";
when x"607" => DATA <= x"F7";
when x"608" => DATA <= x"FE";
when x"609" => DATA <= x"E5";
when x"60A" => DATA <= x"20";
when x"60B" => DATA <= x"F0";
when x"60C" => DATA <= x"13";
when x"60D" => DATA <= x"B6";
when x"60E" => DATA <= x"FF";
when x"60F" => DATA <= x"94";
when x"610" => DATA <= x"27";
when x"611" => DATA <= x"17";
when x"612" => DATA <= x"B6";
when x"613" => DATA <= x"FE";
when x"614" => DATA <= x"E5";
when x"615" => DATA <= x"A7";
when x"616" => DATA <= x"80";
when x"617" => DATA <= x"20";
when x"618" => DATA <= x"F3";
when x"619" => DATA <= x"13";
when x"61A" => DATA <= x"B6";
when x"61B" => DATA <= x"FF";
when x"61C" => DATA <= x"94";
when x"61D" => DATA <= x"27";
when x"61E" => DATA <= x"0A";
when x"61F" => DATA <= x"A6";
when x"620" => DATA <= x"80";
when x"621" => DATA <= x"B7";
when x"622" => DATA <= x"FE";
when x"623" => DATA <= x"E5";
when x"624" => DATA <= x"20";
when x"625" => DATA <= x"F3";
when x"626" => DATA <= x"BF";
when x"627" => DATA <= x"FF";
when x"628" => DATA <= x"8C";
when x"629" => DATA <= x"35";
when x"62A" => DATA <= x"16";
when x"62B" => DATA <= x"3B";
when x"62C" => DATA <= x"32";
when x"62D" => DATA <= x"6A";
when x"62E" => DATA <= x"35";
when x"62F" => DATA <= x"10";
when x"630" => DATA <= x"BF";
when x"631" => DATA <= x"FF";
when x"632" => DATA <= x"82";
when x"633" => DATA <= x"1C";
when x"634" => DATA <= x"00";
when x"635" => DATA <= x"6E";
when x"636" => DATA <= x"9F";
when x"637" => DATA <= x"FF";
when x"638" => DATA <= x"FA";
when x"639" => DATA <= x"FF";
when x"63A" => DATA <= x"FF";
when x"63B" => DATA <= x"FF";
when x"63C" => DATA <= x"FF";
when x"63D" => DATA <= x"FF";
when x"63E" => DATA <= x"FF";
when x"63F" => DATA <= x"FF";
when x"640" => DATA <= x"FF";
when x"641" => DATA <= x"FF";
when x"642" => DATA <= x"FF";
when x"643" => DATA <= x"FF";
when x"644" => DATA <= x"FF";
when x"645" => DATA <= x"FF";
when x"646" => DATA <= x"FF";
when x"647" => DATA <= x"FF";
when x"648" => DATA <= x"FF";
when x"649" => DATA <= x"FF";
when x"64A" => DATA <= x"FF";
when x"64B" => DATA <= x"FF";
when x"64C" => DATA <= x"FF";
when x"64D" => DATA <= x"FF";
when x"64E" => DATA <= x"FF";
when x"64F" => DATA <= x"FF";
when x"650" => DATA <= x"FF";
when x"651" => DATA <= x"FF";
when x"652" => DATA <= x"FF";
when x"653" => DATA <= x"FF";
when x"654" => DATA <= x"FF";
when x"655" => DATA <= x"FF";
when x"656" => DATA <= x"FF";
when x"657" => DATA <= x"FF";
when x"658" => DATA <= x"FF";
when x"659" => DATA <= x"FF";
when x"65A" => DATA <= x"FF";
when x"65B" => DATA <= x"FF";
when x"65C" => DATA <= x"FF";
when x"65D" => DATA <= x"FF";
when x"65E" => DATA <= x"FF";
when x"65F" => DATA <= x"FF";
when x"660" => DATA <= x"FF";
when x"661" => DATA <= x"FF";
when x"662" => DATA <= x"FF";
when x"663" => DATA <= x"FF";
when x"664" => DATA <= x"FF";
when x"665" => DATA <= x"FF";
when x"666" => DATA <= x"FF";
when x"667" => DATA <= x"FF";
when x"668" => DATA <= x"FF";
when x"669" => DATA <= x"FF";
when x"66A" => DATA <= x"FF";
when x"66B" => DATA <= x"FF";
when x"66C" => DATA <= x"FF";
when x"66D" => DATA <= x"FF";
when x"66E" => DATA <= x"FF";
when x"66F" => DATA <= x"FF";
when x"670" => DATA <= x"FF";
when x"671" => DATA <= x"FF";
when x"672" => DATA <= x"FF";
when x"673" => DATA <= x"FF";
when x"674" => DATA <= x"FF";
when x"675" => DATA <= x"FF";
when x"676" => DATA <= x"FF";
when x"677" => DATA <= x"FF";
when x"678" => DATA <= x"FF";
when x"679" => DATA <= x"FF";
when x"67A" => DATA <= x"FF";
when x"67B" => DATA <= x"FF";
when x"67C" => DATA <= x"FF";
when x"67D" => DATA <= x"FF";
when x"67E" => DATA <= x"FF";
when x"67F" => DATA <= x"FF";
when x"680" => DATA <= x"FF";
when x"681" => DATA <= x"FF";
when x"682" => DATA <= x"FF";
when x"683" => DATA <= x"FF";
when x"684" => DATA <= x"FF";
when x"685" => DATA <= x"FF";
when x"686" => DATA <= x"FF";
when x"687" => DATA <= x"FF";
when x"688" => DATA <= x"FF";
when x"689" => DATA <= x"FF";
when x"68A" => DATA <= x"FF";
when x"68B" => DATA <= x"FF";
when x"68C" => DATA <= x"FF";
when x"68D" => DATA <= x"FF";
when x"68E" => DATA <= x"FF";
when x"68F" => DATA <= x"FF";
when x"690" => DATA <= x"FF";
when x"691" => DATA <= x"FF";
when x"692" => DATA <= x"FF";
when x"693" => DATA <= x"FF";
when x"694" => DATA <= x"FF";
when x"695" => DATA <= x"FF";
when x"696" => DATA <= x"FF";
when x"697" => DATA <= x"FF";
when x"698" => DATA <= x"FF";
when x"699" => DATA <= x"FF";
when x"69A" => DATA <= x"FF";
when x"69B" => DATA <= x"FF";
when x"69C" => DATA <= x"FF";
when x"69D" => DATA <= x"FF";
when x"69E" => DATA <= x"FF";
when x"69F" => DATA <= x"FF";
when x"6A0" => DATA <= x"FF";
when x"6A1" => DATA <= x"FF";
when x"6A2" => DATA <= x"FF";
when x"6A3" => DATA <= x"FF";
when x"6A4" => DATA <= x"FF";
when x"6A5" => DATA <= x"FF";
when x"6A6" => DATA <= x"FF";
when x"6A7" => DATA <= x"FF";
when x"6A8" => DATA <= x"FF";
when x"6A9" => DATA <= x"FF";
when x"6AA" => DATA <= x"FF";
when x"6AB" => DATA <= x"FF";
when x"6AC" => DATA <= x"FF";
when x"6AD" => DATA <= x"FF";
when x"6AE" => DATA <= x"FF";
when x"6AF" => DATA <= x"FF";
when x"6B0" => DATA <= x"FF";
when x"6B1" => DATA <= x"FF";
when x"6B2" => DATA <= x"FF";
when x"6B3" => DATA <= x"FF";
when x"6B4" => DATA <= x"FF";
when x"6B5" => DATA <= x"FF";
when x"6B6" => DATA <= x"FF";
when x"6B7" => DATA <= x"FF";
when x"6B8" => DATA <= x"FF";
when x"6B9" => DATA <= x"FF";
when x"6BA" => DATA <= x"FF";
when x"6BB" => DATA <= x"FF";
when x"6BC" => DATA <= x"FF";
when x"6BD" => DATA <= x"FF";
when x"6BE" => DATA <= x"FF";
when x"6BF" => DATA <= x"FF";
when x"6C0" => DATA <= x"FF";
when x"6C1" => DATA <= x"FF";
when x"6C2" => DATA <= x"FF";
when x"6C3" => DATA <= x"FF";
when x"6C4" => DATA <= x"FF";
when x"6C5" => DATA <= x"FF";
when x"6C6" => DATA <= x"FF";
when x"6C7" => DATA <= x"FF";
when x"6C8" => DATA <= x"FF";
when x"6C9" => DATA <= x"FF";
when x"6CA" => DATA <= x"FF";
when x"6CB" => DATA <= x"FF";
when x"6CC" => DATA <= x"FF";
when x"6CD" => DATA <= x"FF";
when x"6CE" => DATA <= x"FF";
when x"6CF" => DATA <= x"FF";
when x"6D0" => DATA <= x"FF";
when x"6D1" => DATA <= x"FF";
when x"6D2" => DATA <= x"FF";
when x"6D3" => DATA <= x"FF";
when x"6D4" => DATA <= x"FF";
when x"6D5" => DATA <= x"FF";
when x"6D6" => DATA <= x"FF";
when x"6D7" => DATA <= x"FF";
when x"6D8" => DATA <= x"FF";
when x"6D9" => DATA <= x"FF";
when x"6DA" => DATA <= x"FF";
when x"6DB" => DATA <= x"FF";
when x"6DC" => DATA <= x"FF";
when x"6DD" => DATA <= x"FF";
when x"6DE" => DATA <= x"FF";
when x"6DF" => DATA <= x"FF";
when x"6E0" => DATA <= x"00";
when x"6E1" => DATA <= x"00";
when x"6E2" => DATA <= x"00";
when x"6E3" => DATA <= x"00";
when x"6E4" => DATA <= x"00";
when x"6E5" => DATA <= x"00";
when x"6E6" => DATA <= x"00";
when x"6E7" => DATA <= x"00";
when x"6E8" => DATA <= x"FF";
when x"6E9" => DATA <= x"FF";
when x"6EA" => DATA <= x"FF";
when x"6EB" => DATA <= x"FF";
when x"6EC" => DATA <= x"FF";
when x"6ED" => DATA <= x"FF";
when x"6EE" => DATA <= x"FF";
when x"6EF" => DATA <= x"FF";
when x"6F0" => DATA <= x"FE";
when x"6F1" => DATA <= x"2B";
when x"6F2" => DATA <= x"FE";
when x"6F3" => DATA <= x"2B";
when x"6F4" => DATA <= x"FE";
when x"6F5" => DATA <= x"2B";
when x"6F6" => DATA <= x"FD";
when x"6F7" => DATA <= x"03";
when x"6F8" => DATA <= x"FE";
when x"6F9" => DATA <= x"2B";
when x"6FA" => DATA <= x"FE";
when x"6FB" => DATA <= x"2C";
when x"6FC" => DATA <= x"FE";
when x"6FD" => DATA <= x"2B";
when x"6FE" => DATA <= x"F8";
when x"6FF" => DATA <= x"2C";
when x"700" => DATA <= x"00";
when x"701" => DATA <= x"00";
when x"702" => DATA <= x"00";
when x"703" => DATA <= x"00";
when x"704" => DATA <= x"00";
when x"705" => DATA <= x"00";
when x"706" => DATA <= x"00";
when x"707" => DATA <= x"00";
when x"708" => DATA <= x"00";
when x"709" => DATA <= x"00";
when x"70A" => DATA <= x"00";
when x"70B" => DATA <= x"00";
when x"70C" => DATA <= x"00";
when x"70D" => DATA <= x"00";
when x"70E" => DATA <= x"00";
when x"70F" => DATA <= x"00";
when x"710" => DATA <= x"00";
when x"711" => DATA <= x"00";
when x"712" => DATA <= x"00";
when x"713" => DATA <= x"00";
when x"714" => DATA <= x"00";
when x"715" => DATA <= x"00";
when x"716" => DATA <= x"00";
when x"717" => DATA <= x"00";
when x"718" => DATA <= x"00";
when x"719" => DATA <= x"00";
when x"71A" => DATA <= x"00";
when x"71B" => DATA <= x"00";
when x"71C" => DATA <= x"00";
when x"71D" => DATA <= x"00";
when x"71E" => DATA <= x"00";
when x"71F" => DATA <= x"00";
when x"720" => DATA <= x"00";
when x"721" => DATA <= x"00";
when x"722" => DATA <= x"00";
when x"723" => DATA <= x"00";
when x"724" => DATA <= x"00";
when x"725" => DATA <= x"00";
when x"726" => DATA <= x"00";
when x"727" => DATA <= x"00";
when x"728" => DATA <= x"00";
when x"729" => DATA <= x"00";
when x"72A" => DATA <= x"00";
when x"72B" => DATA <= x"00";
when x"72C" => DATA <= x"00";
when x"72D" => DATA <= x"00";
when x"72E" => DATA <= x"00";
when x"72F" => DATA <= x"00";
when x"730" => DATA <= x"00";
when x"731" => DATA <= x"00";
when x"732" => DATA <= x"00";
when x"733" => DATA <= x"00";
when x"734" => DATA <= x"00";
when x"735" => DATA <= x"00";
when x"736" => DATA <= x"00";
when x"737" => DATA <= x"00";
when x"738" => DATA <= x"00";
when x"739" => DATA <= x"00";
when x"73A" => DATA <= x"00";
when x"73B" => DATA <= x"00";
when x"73C" => DATA <= x"00";
when x"73D" => DATA <= x"00";
when x"73E" => DATA <= x"00";
when x"73F" => DATA <= x"00";
when x"740" => DATA <= x"00";
when x"741" => DATA <= x"00";
when x"742" => DATA <= x"00";
when x"743" => DATA <= x"00";
when x"744" => DATA <= x"00";
when x"745" => DATA <= x"00";
when x"746" => DATA <= x"00";
when x"747" => DATA <= x"00";
when x"748" => DATA <= x"00";
when x"749" => DATA <= x"00";
when x"74A" => DATA <= x"00";
when x"74B" => DATA <= x"00";
when x"74C" => DATA <= x"00";
when x"74D" => DATA <= x"00";
when x"74E" => DATA <= x"00";
when x"74F" => DATA <= x"00";
when x"750" => DATA <= x"00";
when x"751" => DATA <= x"00";
when x"752" => DATA <= x"00";
when x"753" => DATA <= x"00";
when x"754" => DATA <= x"00";
when x"755" => DATA <= x"00";
when x"756" => DATA <= x"00";
when x"757" => DATA <= x"00";
when x"758" => DATA <= x"00";
when x"759" => DATA <= x"00";
when x"75A" => DATA <= x"00";
when x"75B" => DATA <= x"00";
when x"75C" => DATA <= x"00";
when x"75D" => DATA <= x"00";
when x"75E" => DATA <= x"00";
when x"75F" => DATA <= x"00";
when x"760" => DATA <= x"00";
when x"761" => DATA <= x"00";
when x"762" => DATA <= x"00";
when x"763" => DATA <= x"00";
when x"764" => DATA <= x"00";
when x"765" => DATA <= x"00";
when x"766" => DATA <= x"00";
when x"767" => DATA <= x"00";
when x"768" => DATA <= x"00";
when x"769" => DATA <= x"00";
when x"76A" => DATA <= x"00";
when x"76B" => DATA <= x"00";
when x"76C" => DATA <= x"00";
when x"76D" => DATA <= x"00";
when x"76E" => DATA <= x"00";
when x"76F" => DATA <= x"00";
when x"770" => DATA <= x"00";
when x"771" => DATA <= x"00";
when x"772" => DATA <= x"00";
when x"773" => DATA <= x"00";
when x"774" => DATA <= x"00";
when x"775" => DATA <= x"00";
when x"776" => DATA <= x"00";
when x"777" => DATA <= x"00";
when x"778" => DATA <= x"00";
when x"779" => DATA <= x"00";
when x"77A" => DATA <= x"00";
when x"77B" => DATA <= x"00";
when x"77C" => DATA <= x"00";
when x"77D" => DATA <= x"00";
when x"77E" => DATA <= x"00";
when x"77F" => DATA <= x"00";
when x"780" => DATA <= x"00";
when x"781" => DATA <= x"00";
when x"782" => DATA <= x"F8";
when x"783" => DATA <= x"16";
when x"784" => DATA <= x"F8";
when x"785" => DATA <= x"B0";
when x"786" => DATA <= x"F8";
when x"787" => DATA <= x"16";
when x"788" => DATA <= x"00";
when x"789" => DATA <= x"00";
when x"78A" => DATA <= x"F8";
when x"78B" => DATA <= x"00";
when x"78C" => DATA <= x"FF";
when x"78D" => DATA <= x"B9";
when x"78E" => DATA <= x"FF";
when x"78F" => DATA <= x"B9";
when x"790" => DATA <= x"FF";
when x"791" => DATA <= x"B9";
when x"792" => DATA <= x"00";
when x"793" => DATA <= x"00";
when x"794" => DATA <= x"00";
when x"795" => DATA <= x"7E";
when x"796" => DATA <= x"FA";
when x"797" => DATA <= x"9B";
when x"798" => DATA <= x"7E";
when x"799" => DATA <= x"F8";
when x"79A" => DATA <= x"2C";
when x"79B" => DATA <= x"7E";
when x"79C" => DATA <= x"FA";
when x"79D" => DATA <= x"9B";
when x"79E" => DATA <= x"7E";
when x"79F" => DATA <= x"FA";
when x"7A0" => DATA <= x"9B";
when x"7A1" => DATA <= x"7E";
when x"7A2" => DATA <= x"F9";
when x"7A3" => DATA <= x"3E";
when x"7A4" => DATA <= x"7E";
when x"7A5" => DATA <= x"FA";
when x"7A6" => DATA <= x"9B";
when x"7A7" => DATA <= x"7E";
when x"7A8" => DATA <= x"F8";
when x"7A9" => DATA <= x"71";
when x"7AA" => DATA <= x"7E";
when x"7AB" => DATA <= x"F9";
when x"7AC" => DATA <= x"17";
when x"7AD" => DATA <= x"7E";
when x"7AE" => DATA <= x"F9";
when x"7AF" => DATA <= x"0F";
when x"7B0" => DATA <= x"7E";
when x"7B1" => DATA <= x"FE";
when x"7B2" => DATA <= x"2B";
when x"7B3" => DATA <= x"7E";
when x"7B4" => DATA <= x"F9";
when x"7B5" => DATA <= x"2E";
when x"7B6" => DATA <= x"7E";
when x"7B7" => DATA <= x"FA";
when x"7B8" => DATA <= x"9B";
when x"7B9" => DATA <= x"7E";
when x"7BA" => DATA <= x"F8";
when x"7BB" => DATA <= x"71";
when x"7BC" => DATA <= x"7E";
when x"7BD" => DATA <= x"FE";
when x"7BE" => DATA <= x"2E";
when x"7BF" => DATA <= x"7E";
when x"7C0" => DATA <= x"F8";
when x"7C1" => DATA <= x"D3";
when x"7C2" => DATA <= x"7E";
when x"7C3" => DATA <= x"FA";
when x"7C4" => DATA <= x"9B";
when x"7C5" => DATA <= x"7E";
when x"7C6" => DATA <= x"F9";
when x"7C7" => DATA <= x"35";
when x"7C8" => DATA <= x"7E";
when x"7C9" => DATA <= x"FA";
when x"7CA" => DATA <= x"9B";
when x"7CB" => DATA <= x"7E";
when x"7CC" => DATA <= x"FA";
when x"7CD" => DATA <= x"9B";
when x"7CE" => DATA <= x"7E";
when x"7CF" => DATA <= x"FC";
when x"7D0" => DATA <= x"4A";
when x"7D1" => DATA <= x"7E";
when x"7D2" => DATA <= x"FC";
when x"7D3" => DATA <= x"9A";
when x"7D4" => DATA <= x"7E";
when x"7D5" => DATA <= x"FC";
when x"7D6" => DATA <= x"34";
when x"7D7" => DATA <= x"7E";
when x"7D8" => DATA <= x"FC";
when x"7D9" => DATA <= x"25";
when x"7DA" => DATA <= x"7E";
when x"7DB" => DATA <= x"FC";
when x"7DC" => DATA <= x"01";
when x"7DD" => DATA <= x"7E";
when x"7DE" => DATA <= x"FC";
when x"7DF" => DATA <= x"6A";
when x"7E0" => DATA <= x"7E";
when x"7E1" => DATA <= x"FA";
when x"7E2" => DATA <= x"C3";
when x"7E3" => DATA <= x"81";
when x"7E4" => DATA <= x"0D";
when x"7E5" => DATA <= x"26";
when x"7E6" => DATA <= x"07";
when x"7E7" => DATA <= x"86";
when x"7E8" => DATA <= x"0A";
when x"7E9" => DATA <= x"BD";
when x"7EA" => DATA <= x"FF";
when x"7EB" => DATA <= x"EE";
when x"7EC" => DATA <= x"86";
when x"7ED" => DATA <= x"0D";
when x"7EE" => DATA <= x"7E";
when x"7EF" => DATA <= x"FC";
when x"7F0" => DATA <= x"E3";
when x"7F1" => DATA <= x"7E";
when x"7F2" => DATA <= x"FB";
when x"7F3" => DATA <= x"4A";
when x"7F4" => DATA <= x"7E";
when x"7F5" => DATA <= x"FA";
when x"7F6" => DATA <= x"D4";
when x"7F7" => DATA <= x"7E";
when x"7F8" => DATA <= x"F9";
when x"7F9" => DATA <= x"80";
when x"7FA" => DATA <= x"F8";
when x"7FB" => DATA <= x"B0";
when x"7FC" => DATA <= x"FA";
when x"7FD" => DATA <= x"9B";
when x"7FE" => DATA <= x"F8";
when x"7FF" => DATA <= x"2C";
when others => DATA <= (others => '0');
end case;
end process;
end RTL;
| gpl-3.0 | 8cf75208d1ebf4da236c598fd8c5ce31 | 0.350455 | 3.031243 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/leon3v3/libiu.vhd | 1 | 9,104 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: libiu
-- File: libiu.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: LEON3 IU types and components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libfpu.all;
use gaisler.arith.all;
use gaisler.mmuconfig.all;
package libiu is
constant RDBITS : integer := 32;
constant IDBITS : integer := 32;
subtype cword is std_logic_vector(IDBITS-1 downto 0);
type cdatatype is array (0 to 3) of cword;
type iregfile_in_type is record
raddr1 : std_logic_vector(9 downto 0); -- read address 1
raddr2 : std_logic_vector(9 downto 0); -- read address 2
waddr : std_logic_vector(9 downto 0); -- write address
wdata : std_logic_vector(31 downto 0); -- write data
ren1 : std_ulogic; -- read 1 enable
ren2 : std_ulogic; -- read 2 enable
wren : std_ulogic; -- write enable
end record;
type iregfile_out_type is record
data1 : std_logic_vector(RDBITS-1 downto 0); -- read data 1
data2 : std_logic_vector(RDBITS-1 downto 0); -- read data 2
end record;
type cctrltype is record
burst : std_ulogic; -- icache burst enable
dfrz : std_ulogic; -- dcache freeze enable
ifrz : std_ulogic; -- icache freeze enable
dsnoop : std_ulogic; -- data cache snooping
dcs : std_logic_vector(1 downto 0); -- dcache state
ics : std_logic_vector(1 downto 0); -- icache state
end record;
constant cctrl_none : cctrltype := (
burst => '0', dfrz => '0', ifrz => '0', dsnoop => '0',
dcs => (others => '0'), ics => (others => '0')
);
type icache_in_type is record
rpc : std_logic_vector(31 downto 0); -- raw address (npc)
fpc : std_logic_vector(31 downto 0); -- latched address (fpc)
dpc : std_logic_vector(31 downto 0); -- latched address (dpc)
rbranch : std_ulogic; -- Instruction branch
fbranch : std_ulogic; -- Instruction branch
inull : std_ulogic; -- instruction nullify
su : std_ulogic; -- super-user
flush : std_ulogic; -- flush icache
fline : std_logic_vector(31 downto 3); -- flush line offset
nobpmiss : std_ulogic; -- Predicted instruction, block hold
end record;
type icache_out_type is record
data : cdatatype;
set : std_logic_vector(1 downto 0);
mexc : std_ulogic;
hold : std_ulogic;
flush : std_ulogic; -- flush in progress
diagrdy : std_ulogic; -- diagnostic access ready
diagdata : std_logic_vector(IDBITS-1 downto 0);-- diagnostic data
mds : std_ulogic; -- memory data strobe
cfg : std_logic_vector(31 downto 0);
idle : std_ulogic; -- idle mode
cstat : l3_cstat_type;
bpmiss : std_ulogic;
eocl : std_ulogic;
end record;
type icdiag_in_type is record
addr : std_logic_vector(31 downto 0); -- memory stage address
enable : std_ulogic;
read : std_ulogic;
tag : std_ulogic;
ctx : std_ulogic;
flush : std_ulogic;
ilramen : std_ulogic;
cctrl : cctrltype;
pflush : std_ulogic;
pflushaddr : std_logic_vector(VA_I_U downto VA_I_D);
pflushtyp : std_ulogic;
end record;
type dcache_in_type is record
asi : std_logic_vector(7 downto 0);
maddress : std_logic_vector(31 downto 0);
eaddress : std_logic_vector(31 downto 0);
edata : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
enaddr : std_ulogic;
eenaddr : std_ulogic;
nullify : std_ulogic;
lock : std_ulogic;
read : std_ulogic;
write : std_ulogic;
flush : std_ulogic;
flushl : std_ulogic; -- flush line
dsuen : std_ulogic;
msu : std_ulogic; -- memory stage supervisor
esu : std_ulogic; -- execution stage supervisor
intack : std_ulogic;
mmucacheclr : std_ulogic;
end record;
type dcache_out_type is record
data : cdatatype;
set : std_logic_vector(1 downto 0);
mexc : std_ulogic;
hold : std_ulogic;
mds : std_ulogic;
werr : std_ulogic;
icdiag : icdiag_in_type;
cache : std_ulogic;
idle : std_ulogic; -- idle mode
hit : std_ulogic;
cstat : l3_cstat_type;
wbhold : std_ulogic;
end record;
component iu3
generic (
nwin : integer range 2 to 32 := 8;
isets : integer range 1 to 4 := 1;
dsets : integer range 1 to 4 := 1;
fpu : integer range 0 to 15 := 0;
v8 : integer range 0 to 63 := 0;
cp, mac : integer range 0 to 1 := 0;
dsu : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
index : integer range 0 to 15 := 0;
lddel : integer range 1 to 2 := 2;
irfwt : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0; -- trace buf size in kB (0 - no trace buffer)
pwd : integer range 0 to 2 := 0; -- power-down
svt : integer range 0 to 1 := 0; -- single-vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
fabtech : integer range 0 to NTECH := 0;
clk2x : integer := 0;
bp : integer := 1;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0;
rex : integer := 0;
altwin : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
holdn : in std_ulogic;
ici : out icache_in_type;
ico : in icache_out_type;
dci : out dcache_in_type;
dco : in dcache_out_type;
rfi : out iregfile_in_type;
rfo : in iregfile_out_type;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
muli : out mul32_in_type;
mulo : in mul32_out_type;
divi : out div32_in_type;
divo : in div32_out_type;
fpo : in fpc_out_type;
fpi : out fpc_in_type;
cpo : in fpc_out_type;
cpi : out fpc_in_type;
tbo : in tracebuf_out_type;
tbi : out tracebuf_in_type;
tbo_2p : in tracebuf_2p_out_type;
tbi_2p : out tracebuf_2p_in_type;
sclk : in std_ulogic
);
end component;
end;
| gpl-3.0 | a774ca7b9fae447febde1d2e3983ed39 | 0.489016 | 4.069736 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-xilinx-sp601/leon3mp.vhd | 1 | 24,274 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2006 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.ddrpkg.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
reset : in std_ulogic;
reset_o1 : out std_ulogic;
reset_o2 : out std_ulogic;
clk27 : in std_ulogic;
clk200_p : in std_ulogic;
clk200_n : in std_ulogic;
errorn : out std_ulogic;
-- PROM interface
address : out std_logic_vector(23 downto 0);
data : inout std_logic_vector(7 downto 0);
romsn : out std_ulogic;
oen : out std_ulogic;
writen : out std_ulogic;
-- pragma translate_off
iosn : out std_ulogic;
testdata : inout std_logic_vector(23 downto 0);
-- pragma translate_on
-- DDR2 memory
ddr_clk : out std_logic;
ddr_clkb : out std_logic;
ddr_cke : out std_logic;
ddr_we : out std_ulogic; -- write enable
ddr_ras : out std_ulogic; -- ras
ddr_cas : out std_ulogic; -- cas
ddr_dm : out std_logic_vector(1 downto 0); -- dm
ddr_dqs : inout std_logic_vector(1 downto 0); -- dqs
ddr_dqsn : inout std_logic_vector(1 downto 0); -- dqsn
ddr_ad : out std_logic_vector(12 downto 0); -- address
ddr_ba : out std_logic_vector(2 downto 0); -- bank address
ddr_dq : inout std_logic_vector(15 downto 0); -- data
ddr_odt : out std_logic;
ddr_rzq : inout std_logic;
ddr_zio : inout std_logic;
-- Debug support unit
dsubre : in std_ulogic; -- Debug Unit break (connect to button)
-- AHB Uart
dsurx : in std_ulogic;
dsutx : out std_ulogic;
-- Ethernet signals
etx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(7 downto 0);
erx_dv : in std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
etxd : out std_logic_vector(7 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
emdc : out std_ulogic;
emdio : inout std_logic;
-- SPI flash
-- spi_sel_n : inout std_ulogic;
-- spi_clk : out std_ulogic;
-- spi_mosi : out std_ulogic;
-- Output signals to LEDs
led : out std_logic_vector(2 downto 0)
);
end;
architecture rtl of leon3mp is
signal vcc : std_logic;
signal gnd : std_logic;
signal ddr_clk_fb_out : std_logic;
signal ddr_clk_fb : std_logic;
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal gpti : gptimer_in_type;
signal spii : spi_in_type;
signal spio : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal spmi : spimctrl_in_type;
signal spmo : spimctrl_out_type;
signal lclk, lclk200 : std_ulogic;
signal clkm, rstn, clkml : std_ulogic;
signal tck, tms, tdi, tdo : std_ulogic;
signal rstraw : std_logic;
signal lock : std_logic;
-- RS232 APB Uart
signal rxd1 : std_logic;
signal txd1 : std_logic;
-- Used for connecting input/output signals to the DDR2 controller
signal core_ddr_clk : std_logic_vector(2 downto 0);
signal core_ddr_clkb : std_logic_vector(2 downto 0);
signal core_ddr_cke : std_logic_vector(1 downto 0);
signal core_ddr_csb : std_logic_vector(1 downto 0);
signal core_ddr_ad : std_logic_vector(13 downto 0);
signal core_ddr_odt : std_logic_vector(1 downto 0);
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of lock : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_keep of clkm : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute keep of lock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
constant BOARD_FREQ : integer := 27000; -- CLK input frequency in KHz
constant DDR2_FREQ : integer := 200000; -- DDR2 input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1';
gnd <= '0';
cgi.pllctrl <= "00";
cgi.pllrst <= rstraw;
-- Glitch free reset that can be used for the Eth Phy and flash memory
reset_o1 <= rstn;
reset_o2 <= rstn;
rst0 : rstgen generic map (acthigh => 1)
port map (reset, clkm, lock, rstn, rstraw);
clk27_pad : clkpad generic map (tech => padtech) port map (clk27, lclk);
-- clock generator
clkgen0 : clkgen
generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd, clkm, open, open, open, open, cgi, cgo, open, open, open);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH,
nahbs => 8, devid => XILINX_SP601)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
-- LEON3 processor
leon3gen : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR,
CFG_NCPU-1, CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
error_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
-- LEON3 Debug Support Unit
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsui.enable <= '1';
led(2) <= dsuo.active;
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
-- Debug UART
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
led(0) <= not dui.rxd;
led(1) <= not duo.txd;
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd);
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 5, pindex => 0, paddr => 0,
ram8 => CFG_MCTRL_RAM8BIT, ram16 => CFG_MCTRL_RAM16BIT, rammask => 0)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(5), apbi, apbo(0), wpo, open);
end generate;
memi.brdyn <= '1';
memi.bexcn <= '1';
memi.writen <= '1';
memi.wrn <= "1111";
memi.bwidth <= "00";
mg0 : if (CFG_MCTRL_LEON2 = 0) generate
apbo(0) <= apb_none;
ahbso(5) <= ahbs_none;
roms_pad : outpad generic map (tech => padtech)
port map (romsn, vcc);
memo.bdrive(0) <= '1';
end generate;
mgpads : if (CFG_MCTRL_LEON2 /= 0) generate
addr_pad : outpadv generic map (tech => padtech, width => 24)
port map (address, memo.address(23 downto 0));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
-- pragma translate_off
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
tbdr : iopadv generic map (tech => padtech, width => 24)
port map (testdata(23 downto 0), memo.data(23 downto 0),
memo.bdrive(1), memi.data(23 downto 0));
-- pragma translate_on
end generate;
bdr : iopadv generic map (tech => padtech, width => 8)
port map (data(7 downto 0), memo.data(31 downto 24),
memo.bdrive(0), memi.data(31 downto 24));
----------------------------------------------------------------------
--- DDR2 memory controller ------------------------------------------
----------------------------------------------------------------------
ddr2sp0 : if (CFG_DDR2SP /= 0) generate
clk200_pad : inpad_ds generic map (tech => padtech, voltage => x25v)
port map (clk200_p, clk200_n, lclk200);
ddrc0 : ddr2spa generic map ( fabtech => fabtech, memtech => memtech,
hindex => 4, haddr => 16#400#, hmask => 16#F00#, ioaddr => 1,
pwron => CFG_DDR2SP_INIT, MHz => DDR2_FREQ/1000, clkmul => 5, clkdiv => 8,
TRFC => CFG_DDR2SP_TRFC,
ahbfreq => CPU_FREQ/1000, col => CFG_DDR2SP_COL, Mbyte => CFG_DDR2SP_SIZE,
ddrbits => 16, eightbanks => 1, odten => 0)
port map ( cgo.clklock, rstn, lclk200, clkm, vcc, lock, clkml, clkml, ahbsi, ahbso(4),
core_ddr_clk, core_ddr_clkb, ddr_clk_fb_out, ddr_clk_fb, core_ddr_cke,
core_ddr_csb, ddr_we, ddr_ras, ddr_cas, ddr_dm, ddr_dqs, ddr_dqsn,
core_ddr_ad, ddr_ba, ddr_dq, core_ddr_odt);
ddr_clk <= core_ddr_clk(0);
ddr_clkb <= core_ddr_clkb(0);
ddr_cke <= core_ddr_cke(0);
ddr_ad <= core_ddr_ad(12 downto 0);
ddr_odt <= core_ddr_odt(0);
end generate;
mig_gen : if (CFG_MIG_DDR2 = 1) generate
ddrc : entity work.ahb2mig_sp601 generic map(
hindex => 4, haddr => 16#400#, hmask => 16#F80#,
pindex => 5, paddr => 5)
port map(
mcb3_dram_dq => ddr_dq,
mcb3_dram_a => ddr_ad,
mcb3_dram_ba => ddr_ba,
mcb3_dram_ras_n => ddr_ras,
mcb3_dram_cas_n => ddr_cas,
mcb3_dram_we_n => ddr_we,
mcb3_dram_odt => ddr_odt,
mcb3_dram_cke => ddr_cke,
mcb3_dram_dm => ddr_dm(0),
mcb3_dram_udqs => ddr_dqs(1),
mcb3_dram_udqs_n => ddr_dqsn(1),
mcb3_rzq => ddr_rzq,
mcb3_zio => ddr_zio,
mcb3_dram_udm => ddr_dm(1),
mcb3_dram_dqs => ddr_dqs(0),
mcb3_dram_dqs_n => ddr_dqsn(0),
mcb3_dram_ck => ddr_clk,
mcb3_dram_ck_n => ddr_clkb,
ahbsi => ahbsi,
ahbso => ahbso(4),
apbi => apbi,
apbo => apbo(5),
calib_done => lock,
rst_n_syn => rstn,
rst_n_async => rstraw,
clk_amba => clkm,
clk_mem_n => clk200_n,
clk_mem_p => clk200_p,
test_error => open
);
end generate;
noddr : if (CFG_DDR2SP+CFG_MIG_DDR2) = 0 generate lock <= '1'; end generate;
----------------------------------------------------------------------
--- SPI Memory Controller--------------------------------------------
----------------------------------------------------------------------
-- spimc: if CFG_SPICTRL_ENABLE = 0 and CFG_SPIMCTRL = 1 generate
-- spimctrl0 : spimctrl -- SPI Memory Controller
-- generic map (hindex => 7, hirq => 11, faddr => 16#e00#, fmask => 16#ff8#,
-- ioaddr => 16#002#, iomask => 16#fff#,
-- spliten => CFG_SPLIT, oepol => 0,
-- sdcard => CFG_SPIMCTRL_SDCARD,
-- readcmd => CFG_SPIMCTRL_READCMD,
-- dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
-- dualoutput => CFG_SPIMCTRL_DUALOUTPUT,
-- scaler => CFG_SPIMCTRL_SCALER,
-- altscaler => CFG_SPIMCTRL_ASCALER,
-- pwrupcnt => CFG_SPIMCTRL_PWRUPCNT)
-- port map (rstn, clkm, ahbsi, ahbso(7), spmi, spmo);
--
-- -- MISO is shared with Flash data 0
-- spmi.miso <= memi.data(24);
-- mosi_pad : outpad generic map (tech => padtech)
-- port map (spi_mosi, spmo.mosi);
-- sck_pad : outpad generic map (tech => padtech)
-- port map (spi_clk, spmo.sck);
-- slvsel0_pad : odpad generic map (tech => padtech)
-- port map (spi_sel_n, spmo.csn);
-- end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
-- APB Bridge
apb0 : apbctrl
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
-- Interrupt controller
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
-- Time Unit
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW,
ntimers => CFG_GPT_NTIM, nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti <= gpti_dhalt_drive(dsuo.tstop);
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
-- GPIO Unit
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate
grgpio0: grgpio
generic map(pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 12)
port map(rstn, clkm, apbi, apbo(11), gpioi, gpioo);
end generate;
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1;
u1i.ctsn <= '0';
u1i.extclk <= '0';
txd1 <= u1o.txd;
serrx_pad : inpad generic map (tech => padtech) port map (dsurx, rxd1);
sertx_pad : outpad generic map (tech => padtech) port map (dsutx, txd1);
led(0) <= not rxd1;
led(1) <= not txd1;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
-- spic: if CFG_SPICTRL_ENABLE = 1 generate -- SPI controller
-- spi1 : spictrl
-- generic map (pindex => 7, paddr => 7, pmask => 16#fff#, pirq => 11,
-- fdepth => CFG_SPICTRL_FIFO, slvselen => CFG_SPICTRL_SLVREG,
-- slvselsz => CFG_SPICTRL_SLVS, odmode => 0)
-- port map (rstn, clkm, apbi, apbo(7), spii, spio, slvsel);
-- spii.spisel <= '1'; -- Master only
-- -- MISO is shared with Flash data 0
-- spii.miso <= memi.data(24);
-- mosi_pad : outpad generic map (tech => padtech)
-- port map (spi_mosi, spio.mosi);
-- sck_pad : outpad generic map (tech => padtech)
-- port map (spi_clk, spio.sck);
-- slvsel_pad : odpad generic map (tech => padtech)
-- port map (spi_sel_n, slvsel(0));
-- end generate spic;
nospi: if CFG_SPICTRL_ENABLE = 0 and CFG_SPIMCTRL = 0 generate
apbo(7) <= apb_none;
-- mosi_pad : outpad generic map (tech => padtech)
-- port map (spi_mosi, gnd);
-- sck_pad : outpad generic map (tech => padtech)
-- port map (spi_clk, gnd);
-- slvsel_pad : odpad generic map (tech => padtech)
-- port map (spi_sel_n, vcc);
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm
generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 15, paddr => 15, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 7,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G)
port map(rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
apbi => apbi, apbo => apbo(15), ethi => ethi, etho => etho);
end generate;
ethpads : if (CFG_GRETH = 1) generate -- eth pads
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 8)
port map (erxd, ethi.rxd(7 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 8)
port map (etxd, etho.txd(7 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram
generic map (hindex => 3, haddr => CFG_AHBRADDR, tech => CFG_MEMTECH,
kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+1) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Demonstration design for Xilinx Spartan6 SP601 board",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end rtl;
| gpl-3.0 | 123302203b0d8814cc4b0f8424445381 | 0.53201 | 3.671204 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3mp/config.vhd | 1 | 9,003 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := inferred;
constant CFG_MEMTECH : integer := inferred;
constant CFG_PADTECH : integer := inferred;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := inferred;
constant CFG_CLKMUL : integer := 2;
constant CFG_CLKDIV : integer := 2;
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 0 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (0);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 1;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 0*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 0;
constant CFG_ITBSZ : integer := 0 + 64*0;
constant CFG_ATBSZ : integer := 0;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 0;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 0 + 0 + 0;
constant CFG_ETH_BUF : integer := 1;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000009#;
-- PROM/SRAM controller
constant CFG_SRCTRL : integer := 0;
constant CFG_SRCTRL_PROMWS : integer := 0;
constant CFG_SRCTRL_RAMWS : integer := 0;
constant CFG_SRCTRL_IOWS : integer := 0;
constant CFG_SRCTRL_RMW : integer := 0;
constant CFG_SRCTRL_8BIT : integer := 0;
constant CFG_SRCTRL_SRBANKS : integer := 1;
constant CFG_SRCTRL_BANKSZ : integer := 0;
constant CFG_SRCTRL_ROMASEL : integer := 0;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 1 + 0;
-- SDRAM controller
constant CFG_SDCTRL : integer := 0;
constant CFG_SDCTRL_INVCLK : integer := 0;
constant CFG_SDCTRL_SD64 : integer := 0;
constant CFG_SDCTRL_PAGE : integer := 0 + 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 0;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 8;
-- CAN 2.0 interface
constant CFG_CAN : integer := 0;
constant CFG_CANIO : integer := 16#0#;
constant CFG_CANIRQ : integer := 0;
constant CFG_CANLOOP : integer := 0;
constant CFG_CAN_SYNCRST : integer := 0;
constant CFG_CANFT : integer := 0;
-- GRPCI2 interface
constant CFG_GRPCI2_MASTER : integer := 0;
constant CFG_GRPCI2_TARGET : integer := 0;
constant CFG_GRPCI2_DMA : integer := 0;
constant CFG_GRPCI2_VID : integer := 16#0#;
constant CFG_GRPCI2_DID : integer := 16#0#;
constant CFG_GRPCI2_CLASS : integer := 16#0#;
constant CFG_GRPCI2_RID : integer := 16#0#;
constant CFG_GRPCI2_CAP : integer := 16#40#;
constant CFG_GRPCI2_NCAP : integer := 16#0#;
constant CFG_GRPCI2_BAR0 : integer := 0;
constant CFG_GRPCI2_BAR1 : integer := 0;
constant CFG_GRPCI2_BAR2 : integer := 0;
constant CFG_GRPCI2_BAR3 : integer := 0;
constant CFG_GRPCI2_BAR4 : integer := 0;
constant CFG_GRPCI2_BAR5 : integer := 0;
constant CFG_GRPCI2_FDEPTH : integer := 3;
constant CFG_GRPCI2_FCOUNT : integer := 2;
constant CFG_GRPCI2_ENDIAN : integer := 0;
constant CFG_GRPCI2_DEVINT : integer := 0;
constant CFG_GRPCI2_DEVINTMSK : integer := 16#0#;
constant CFG_GRPCI2_HOSTINT : integer := 0;
constant CFG_GRPCI2_HOSTINTMSK: integer := 16#0#;
constant CFG_GRPCI2_TRACE : integer := 0;
constant CFG_GRPCI2_TRACEAPB : integer := 0;
constant CFG_GRPCI2_BYPASS : integer := 0;
constant CFG_GRPCI2_EXTCFG : integer := (0);
-- PCI arbiter
constant CFG_PCI_ARB : integer := 0;
constant CFG_PCI_ARBAPB : integer := 0;
constant CFG_PCI_ARB_NGNT : integer := 4;
-- Spacewire interface
constant CFG_SPW_EN : integer := 0;
constant CFG_SPW_NUM : integer := 1;
constant CFG_SPW_AHBFIFO : integer := 4;
constant CFG_SPW_RXFIFO : integer := 16;
constant CFG_SPW_RMAP : integer := 0;
constant CFG_SPW_RMAPBUF : integer := 4;
constant CFG_SPW_RMAPCRC : integer := 0;
constant CFG_SPW_NETLIST : integer := 0;
constant CFG_SPW_FT : integer := 0;
constant CFG_SPW_GRSPW : integer := 2;
constant CFG_SPW_RXUNAL : integer := 0;
constant CFG_SPW_DMACHAN : integer := 1;
constant CFG_SPW_PORTS : integer := 1;
constant CFG_SPW_INPUT : integer := 2;
constant CFG_SPW_OUTPUT : integer := 0;
constant CFG_SPW_RTSAME : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- UART 2
constant CFG_UART2_ENABLE : integer := 0;
constant CFG_UART2_FIFO : integer := 1;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 1;
constant CFG_GPT_WDOG : integer := 16#FFFF#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-3.0 | a9c24691b7e13b1957c10d80970cd1c6 | 0.65256 | 3.551479 | false | false | false | false |
hoglet67/CoPro6502 | src/DCM/dcm_32_120.vhd | 1 | 2,191 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity dcm_32_120 is
port (CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic);
end dcm_32_120;
architecture BEHAVIORAL of dcm_32_120 is
signal CLKFX_BUF : std_logic;
signal CLK2X_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKFX_BUFG_INST : BUFG
port map (I => CLKFX_BUF, O => CLK0_OUT);
CLK2X_BUFG_INST : BUFG
port map (I => CLK2X_BUF, O => CLK2X_OUT);
DCM_INST : DCM
generic map(CLK_FEEDBACK => "NONE",
CLKDV_DIVIDE => 4.0, -- 120.00 = 32.000 * 15 / 4
CLKFX_MULTIPLY => 15,
CLKFX_DIVIDE => 4,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => 31.25,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => true,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => false)
port map (CLKFB => GND_BIT,
CLKIN => CLKIN_IN,
DSSEN => GND_BIT,
PSCLK => GND_BIT,
PSEN => GND_BIT,
PSINCDEC => GND_BIT,
RST => GND_BIT,
CLKDV => open,
CLKFX => CLKFX_BUF,
CLKFX180 => open,
CLK0 => open,
CLK2X => CLK2X_BUF,
CLK2X180 => open,
CLK90 => open,
CLK180 => open,
CLK270 => open,
LOCKED => open,
PSDONE => open,
STATUS => open);
end BEHAVIORAL;
| gpl-3.0 | 19d2e29bb84688274e84d638f11307c1 | 0.413966 | 4.095327 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-xilinx-ml501/leon3mp.vhd | 1 | 35,688 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.i2c.all;
use gaisler.net.all;
use gaisler.jtag.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
use work.ml50x.all;
-- pragma translate_off
library unisim;
use unisim.ODDR;
-- pragma translate_on
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
sys_rst_in : in std_ulogic;
clk_100 : in std_ulogic; -- 100 MHz main clock
clk_200_p : in std_ulogic; -- 200 MHz
clk_200_n : in std_ulogic; -- 200 MHz
sysace_clk_in : in std_ulogic; -- System ACE clock
sram_flash_addr : out std_logic_vector(23 downto 0);
sram_flash_data : inout std_logic_vector(31 downto 0);
sram_cen : out std_logic;
sram_bw : out std_logic_vector (0 to 3);
sram_oen : out std_ulogic;
sram_flash_we_n : out std_ulogic;
flash_ce : out std_logic;
flash_oen : out std_logic;
flash_adv_n : out std_logic;
sram_clk : out std_ulogic;
sram_clk_fb : in std_ulogic;
sram_mode : out std_ulogic;
sram_adv_ld_n : out std_ulogic;
--pragma translate_off
iosn : out std_ulogic;
--pragma translate_on
ddr2_ck : out std_logic_vector(1 downto 0);
ddr2_ck_n : out std_logic_vector(1 downto 0);
ddr2_cke : out std_logic_vector(1 downto 0);
ddr2_cs_n : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(1 downto 0);
ddr2_we_n : out std_ulogic; -- ddr write enable
ddr2_ras_n : out std_ulogic; -- ddr ras
ddr2_cas_n : out std_ulogic; -- ddr cas
ddr2_dm : out std_logic_vector (7 downto 0); -- ddr dm
ddr2_dqs : inout std_logic_vector (7 downto 0); -- ddr dqs
ddr2_dqs_n : inout std_logic_vector (7 downto 0); -- ddr dqs
ddr2_a : out std_logic_vector (13 downto 0); -- ddr address
ddr2_ba : out std_logic_vector (1+CFG_DDR2SP downto 0); -- ddr bank address
ddr2_dq : inout std_logic_vector (63 downto 0); -- ddr data
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
-- txd2 : out std_ulogic; -- UART2 tx data
-- rxd2 : in std_ulogic; -- UART2 rx data
gpio : inout std_logic_vector(13 downto 0); -- I/O port
led : out std_logic_vector(12 downto 0);
bus_error : out std_logic_vector(1 downto 0);
phy_gtx_clk : out std_logic;
phy_mii_data : inout std_logic; -- ethernet PHY interface
phy_tx_clk : in std_ulogic;
phy_rx_clk : in std_ulogic;
phy_rx_data : in std_logic_vector(7 downto 0);
phy_dv : in std_ulogic;
phy_rx_er : in std_ulogic;
phy_col : in std_ulogic;
phy_crs : in std_ulogic;
phy_tx_data : out std_logic_vector(7 downto 0);
phy_tx_en : out std_ulogic;
phy_tx_er : out std_ulogic;
phy_mii_clk : out std_ulogic;
phy_rst_n : out std_ulogic;
phy_int : in std_ulogic;
ps2_keyb_clk : inout std_logic;
ps2_keyb_data : inout std_logic;
ps2_mouse_clk : inout std_logic;
ps2_mouse_data : inout std_logic;
usb_csn : out std_logic;
usb_rstn : out std_logic;
iic_scl : inout std_ulogic;
iic_sda : inout std_ulogic;
dvi_iic_scl : inout std_logic;
dvi_iic_sda : inout std_logic;
tft_lcd_data : out std_logic_vector(11 downto 0);
tft_lcd_clk_p : out std_ulogic;
tft_lcd_clk_n : out std_ulogic;
tft_lcd_hsync : out std_ulogic;
tft_lcd_vsync : out std_ulogic;
tft_lcd_de : out std_ulogic;
tft_lcd_reset_b : out std_ulogic;
sace_usb_a : out std_logic_vector(6 downto 0);
sace_mpce : out std_ulogic;
sace_usb_d : inout std_logic_vector(15 downto 0);
sace_usb_oen : out std_ulogic;
sace_usb_wen : out std_ulogic;
sysace_mpirq : in std_ulogic
);
end;
architecture rtl of leon3mp is
component ODDR
generic
( DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
-- INIT : bit := '0';
SRTYPE : string := "SYNC");
port
(
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
component svga2ch7301c
generic (
tech : integer := 0;
idf : integer := 0;
dynamic : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
clksel : in std_logic_vector(1 downto 0);
vgao : in apbvga_out_type;
vgaclk_fb : in std_ulogic;
clk25_fb : in std_ulogic;
clk40_fb : in std_ulogic;
clk65_fb : in std_ulogic;
vgaclk : out std_ulogic;
clk25 : out std_ulogic;
clk40 : out std_ulogic;
clk65 : out std_ulogic;
dclk_p : out std_ulogic;
dclk_n : out std_ulogic;
locked : out std_ulogic;
data : out std_logic_vector(11 downto 0);
hsync : out std_ulogic;
vsync : out std_ulogic;
de : out std_ulogic
);
end component;
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := NCPU+CFG_AHB_UART
+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE;
signal ddr_clk_fb : std_logic;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdctrl_out_type;
signal sdo2 : sdctrl_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, srclkl : std_ulogic;
signal clk_200 : std_ulogic;
signal clk25, clk40, clk65 : std_ulogic;
signal cgi, cgi2 : clkgen_in_type;
signal cgo, cgo2 : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal clklock, lock, lclk, clkml, rst, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal ddrclk, ddrrst : std_ulogic;
signal egtx_clk_fb : std_ulogic;
signal egtx_clk, legtx_clk, l2egtx_clk : std_ulogic;
signal kbdi : ps2_in_type;
signal kbdo : ps2_out_type;
signal moui : ps2_in_type;
signal mouo : ps2_out_type;
signal vgao : apbvga_out_type;
signal lcd_datal : std_logic_vector(11 downto 0);
signal lcd_hsyncl, lcd_vsyncl, lcd_del, lcd_reset_bl : std_ulogic;
signal clk_sel : std_logic_vector(1 downto 0);
signal vgalock : std_ulogic;
signal clkvga, clkvga_p, clkvga_n : std_ulogic;
signal i2ci, dvi_i2ci : i2c_in_type;
signal i2co, dvi_i2co : i2c_out_type;
constant BOARD_FREQ_200 : integer := 200000; -- input frequency in KHz
constant BOARD_FREQ : integer := 100000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant I2C_FILTER : integer := (CPU_FREQ*5+50000)/100000+1;
constant IOAEN : integer := CFG_DDR2SP + CFG_GRACECTRL;
signal stati : ahbstat_in_type;
signal ssrclkfb : std_ulogic;
-- Used for connecting input/output signals to the DDR3 controller
signal migi : mig_app_in_type;
signal migo : mig_app_out_type;
signal phy_init_done : std_ulogic;
signal clk0_tb, rst0_tb, rst0_tbn : std_ulogic;
signal sysmoni : grsysmon_in_type;
signal sysmono : grsysmon_out_type;
signal clkace : std_ulogic;
signal acei : gracectrl_in_type;
signal aceo : gracectrl_out_type;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of clkml : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute syn_keep of clkm : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute syn_keep of egtx_clk : signal is true;
attribute syn_preserve of egtx_clk : signal is true;
attribute syn_keep of clkvga : signal is true;
attribute syn_preserve of clkvga : signal is true;
attribute syn_keep of clk25 : signal is true;
attribute syn_preserve of clk25 : signal is true;
attribute syn_keep of clk40 : signal is true;
attribute syn_preserve of clk40 : signal is true;
attribute syn_keep of clk65 : signal is true;
attribute syn_preserve of clk65 : signal is true;
attribute syn_keep of clk_200 : signal is true;
attribute syn_preserve of clk_200 : signal is true;
attribute syn_preserve of phy_init_done : signal is true;
attribute keep : boolean;
attribute keep of lock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
attribute keep of egtx_clk : signal is true;
attribute keep of clkvga : signal is true;
attribute keep of clk25 : signal is true;
attribute keep of clk40 : signal is true;
attribute keep of clk65 : signal is true;
attribute keep of clk_200 : signal is true;
attribute keep of phy_init_done : signal is true;
attribute syn_noprune : boolean;
attribute syn_noprune of sysace_clk_in_pad : label is true;
begin
usb_csn <= '1';
usb_rstn <= rstn;
rst0_tbn <= not rst0_tb;
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; cgi.pllref <= ssrclkfb;
ssrref_pad : clkpad generic map (tech => padtech)
port map (sram_clk_fb, ssrclkfb);
clk_pad : clkpad generic map (tech => padtech, arch => 2)
port map (clk_100, lclk);
clk200_pad : clkpad_ds generic map (tech => padtech, level => lvds, voltage => x25v)
port map (clk_200_p, clk_200_n, clk_200);
srclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (sram_clk, srclkl);
sysace_clk_in_pad : clkpad generic map (tech => padtech)
port map (sysace_clk_in, clkace);
clkgen0 : clkgen -- system clock generator
generic map (CFG_FABTECH, CFG_CLKMUL, CFG_CLKDIV, 1, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd(0), clkm, open, open, srclkl, open, cgi, cgo);
gclk : if CFG_GRETH1G /= 0 generate
clkgen1 : clkgen -- Ethernet 1G PHY clock generator
generic map (CFG_FABTECH, 5, 4, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd(0), egtx_clk, open, open, open, open, cgi2, cgo2);
cgi2.pllctrl <= "00"; cgi2.pllrst <= rstraw; --cgi2.pllref <= egtx_clk_fb;
x0 : ODDR port map ( Q => phy_gtx_clk, C => egtx_clk, CE => vcc(0),
-- D1 => gnd(0), D2 => vcc(0), R => gnd(0), S => gnd(0));
D1 => vcc(0), D2 => gnd(0), R => gnd(0), S => gnd(0));
end generate;
nogclk : if CFG_GRETH1G = 0 generate
cgo2.clklock <= '1'; phy_gtx_clk <= '0';
end generate;
resetn_pad : inpad generic map (tech => padtech) port map (sys_rst_in, rst);
rst0 : rstgen -- reset generator
port map (rst, clkm, clklock, rstn, rstraw);
clklock <= lock and cgo.clklock and cgo2.clklock and vgalock;
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, devid => XILINX_ML501,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
bus_error(0) <= not dbgo(0).error;
bus_error(1) <= rstn;
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
-- dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsui.break <= gpioo.val(11); -- South Button
-- dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, ndsuact);
led(4) <= dsuo.active;
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(NCPU));
-- dsurx_pad : inpad generic map (tech => padtech) port map (rxd1, dui.rxd);
-- dsutx_pad : outpad generic map (tech => padtech) port map (txd1, duo.txd);
dui.rxd <= rxd1 when gpioo.val(0) = '1' else '1';
end generate;
txd1 <= duo.txd when gpioo.val(0) = '1' else u1o.txd;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
memi.brdyn <= '1'; memi.bexcn <= '1';
mctrl0 : if CFG_MCTRL_LEON2 = 1 generate
mctrl0 : mctrl generic map (hindex => 3, pindex => 0,
ramaddr => 16#400# + (CFG_DDR2SP+CFG_MIG_DDR2)*16#800#, rammask => 16#FE0#,
paddr => 0, srbanks => 1, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN,
invclk => CFG_MCTRL_INVCLK, sepbus => CFG_MCTRL_SEPBUS)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(3), apbi, apbo(0), wpo, open);
end generate;
flash_adv_n_pad : outpad generic map (tech => padtech)
port map (flash_adv_n, gnd(0));
sram_adv_ld_n_pad : outpad generic map (tech => padtech)
port map (sram_adv_ld_n, gnd(0));
sram_mode_pad : outpad generic map (tech => padtech)
port map (sram_mode, gnd(0));
addr_pad : outpadv generic map (width => 24, tech => padtech)
port map (sram_flash_addr, memo.address(24 downto 1));
rams_pad : outpad generic map ( tech => padtech)
port map (sram_cen, memo.ramsn(0));
roms_pad : outpad generic map (tech => padtech)
port map (flash_ce, memo.romsn(0));
ramoen_pad : outpad generic map (tech => padtech)
port map (sram_oen, memo.ramoen(0));
flash_oen_pad : outpad generic map (tech => padtech)
port map (flash_oen, memo.oen);
--pragma translate_off
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
--pragma translate_on
rwen_pad : outpadv generic map (width => 2, tech => padtech)
port map (sram_bw(0 to 1), memo.wrn(3 downto 2));
rwen_pad2 : outpadv generic map (width => 2, tech => padtech)
port map (sram_bw(2 to 3), memo.wrn(1 downto 0));
wri_pad : outpad generic map (tech => padtech)
port map (sram_flash_we_n, memo.writen);
data_pads : iopadvv generic map (tech => padtech, width => 16)
port map (sram_flash_data(15 downto 0), memo.data(31 downto 16),
memo.vbdrive(31 downto 16), memi.data(31 downto 16));
data_pads2 : iopadvv generic map (tech => padtech, width => 16)
port map (sram_flash_data(31 downto 16), memo.data(15 downto 0),
memo.vbdrive(15 downto 0), memi.data(15 downto 0));
migsp0 : if (CFG_MIG_DDR2 = 1) generate
ahb2mig0 : entity work.ahb2mig_ml50x
generic map ( hindex => 0, haddr => 16#400#, hmask => MIGHMASK,
MHz => 400, Mbyte => 512, nosync => 0) --boolean'pos(CFG_MIG_CLK4=12)) --CFG_CLKDIV/12)
port map (
rst_ahb => rstn, rst_ddr => rst0_tbn, clk_ahb => clkm, clk_ddr => clk0_tb,
ahbsi => ahbsi, ahbso => ahbso(0), migi => migi, migo => migo);
migv5 : mig_36_1
generic map (
CKE_WIDTH => CKE_WIDTH, CS_NUM => CS_NUM, CS_WIDTH => CS_WIDTH, CS_BITS => CS_BITS,
COL_WIDTH => COL_WIDTH, ROW_WIDTH => ROW_WIDTH,
NOCLK200 => true, SIM_ONLY => 1)
port map(
ddr2_dq => ddr2_dq(DQ_WIDTH-1 downto 0),
ddr2_a => ddr2_a(ROW_WIDTH-1 downto 0),
ddr2_ba => ddr2_ba(1 downto 0), ddr2_ras_n => ddr2_ras_n,
ddr2_cas_n => ddr2_cas_n, ddr2_we_n => ddr2_we_n,
ddr2_cs_n => ddr2_cs_n(CS_NUM-1 downto 0), ddr2_odt => ddr2_odt(0 downto 0),
ddr2_cke => ddr2_cke(CKE_WIDTH-1 downto 0),
ddr2_dm => ddr2_dm(DM_WIDTH-1 downto 0),
sys_clk => clk_200, idly_clk_200 => clk_200, sys_rst_n => rstraw,
phy_init_done => phy_init_done,
rst0_tb => rst0_tb, clk0_tb => clk0_tb,
app_wdf_afull => migo.app_wdf_afull,
app_af_afull => migo.app_af_afull,
rd_data_valid => migo.app_rd_data_valid,
app_wdf_wren => migi.app_wdf_wren,
app_af_wren => migi.app_en, app_af_addr => migi.app_addr,
app_af_cmd => migi.app_cmd,
rd_data_fifo_out => migo.app_rd_data, app_wdf_data => migi.app_wdf_data,
app_wdf_mask_data => migi.app_wdf_mask,
ddr2_dqs => ddr2_dqs(DQS_WIDTH-1 downto 0),
ddr2_dqs_n => ddr2_dqs_n(DQS_WIDTH-1 downto 0),
ddr2_ck => ddr2_ck((CLK_WIDTH-1) downto 0),
ddr2_ck_n => ddr2_ck_n((CLK_WIDTH-1) downto 0)
);
lock <= phy_init_done;
led(5) <= phy_init_done;
ddr2_a(13) <= '0';
ddr2_odt(1) <= '0';
ddr2_cs_n(1) <= '0';
end generate;
ddrsp0 : if (CFG_DDR2SP /= 0) and (CFG_MIG_DDR2 = 0) generate
ddrc0 : ddr2spa generic map ( fabtech => fabtech, memtech => memtech,
hindex => 0, haddr => 16#400#, hmask => 16#E00#, ioaddr => 1,
pwron => CFG_DDR2SP_INIT, MHz => BOARD_FREQ_200/1000, TRFC => CFG_DDR2SP_TRFC,
clkmul => CFG_DDR2SP_FREQ/10, clkdiv => 20, ahbfreq => CPU_FREQ/1000,
col => CFG_DDR2SP_COL, Mbyte => CFG_DDR2SP_SIZE, ddrbits => 64,
ddelayb0 => CFG_DDR2SP_DELAY0, ddelayb1 => CFG_DDR2SP_DELAY1,
ddelayb2 => CFG_DDR2SP_DELAY2, ddelayb3 => CFG_DDR2SP_DELAY3,
ddelayb4 => CFG_DDR2SP_DELAY4, ddelayb5 => CFG_DDR2SP_DELAY5,
ddelayb6 => CFG_DDR2SP_DELAY6, ddelayb7 => CFG_DDR2SP_DELAY7,
numidelctrl => 1, norefclk => 0, odten => 3, nclk => 2,
eightbanks => 1)
port map ( rst, rstn, clk_200, clkm, clk_200, lock,
clkml, clkml, ahbsi, ahbso(0),
ddr2_ck, ddr2_ck_n, ddr_clk_fb, ddr_clk_fb, ddr2_cke, ddr2_cs_n,
ddr2_we_n, ddr2_ras_n, ddr2_cas_n,
ddr2_dm, ddr2_dqs, ddr2_dqs_n, ddr2_a, ddr2_ba, ddr2_dq, ddr2_odt);
end generate;
noddr : if (CFG_DDR2SP = 0) and (CFG_MIG_DDR2 = 0) generate lock <= '1'; end generate;
----------------------------------------------------------------------
--- System ACE I/F Controller ---------------------------------------
----------------------------------------------------------------------
grace: if CFG_GRACECTRL = 1 generate
grace0 : gracectrl generic map (hindex => 4, hirq => 3,
haddr => 16#002#, hmask => 16#fff#, split => CFG_SPLIT)
port map (rstn, clkm, clkace, ahbsi, ahbso(4), acei, aceo);
end generate;
nograce: if CFG_GRACECTRL /= 1 generate
aceo <= gracectrl_none;
end generate;
sace_usb_a_pads : outpadv generic map (width => 7, tech => padtech)
port map (sace_usb_a, aceo.addr);
sace_mpce_pad : outpad generic map (tech => padtech)
port map (sace_mpce, aceo.cen);
sace_usb_d_pads : iopadv generic map (tech => padtech, width => 16)
port map (sace_usb_d, aceo.do, aceo.doen, acei.di);
sace_usb_oen_pad : outpad generic map (tech => padtech)
port map (sace_usb_oen, aceo.oen);
sace_usb_wen_pad : outpad generic map (tech => padtech)
port map (sace_usb_wen, aceo.wen);
sysace_mpirq_pad : inpad generic map (tech => padtech)
port map (sysace_mpirq, acei.irq);
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0'; u1i.ctsn <= '0';
u1i.rxd <= rxd1 when gpioo.val(0) = '0' else '1';
end generate;
led(0) <= gpioo.val(0); led(1) <= not rxd1;
led(2) <= not duo.txd when gpioo.val(0) = '1' else not u1o.txd;
led (12 downto 6) <= (others => '0');
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
gpti <= gpti_dhalt_drive(dsuo.tstop);
led(3) <= gpto.wdog;
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
kbd : if CFG_KBD_ENABLE /= 0 generate
ps21 : apbps2 generic map(pindex => 4, paddr => 4, pirq => 4)
port map(rstn, clkm, apbi, apbo(4), moui, mouo);
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
end generate;
nokbd : if CFG_KBD_ENABLE = 0 generate apbo(5) <= apb_none; kbdo <= ps2o_none; end generate;
kbdclk_pad : iopad generic map (tech => padtech)
port map (ps2_keyb_clk,kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
kbdata_pad : iopad generic map (tech => padtech)
port map (ps2_keyb_data, kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
mouclk_pad : iopad generic map (tech => padtech)
port map (ps2_mouse_clk, mouo.ps2_clk_o, mouo.ps2_clk_oe, moui.ps2_clk_i);
mouata_pad : iopad generic map (tech => padtech)
port map (ps2_mouse_data, mouo.ps2_data_o, mouo.ps2_data_oe, moui.ps2_data_i);
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, clkvga, apbi, apbo(6), vgao);
clk_sel <= "00";
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
clk0 => 40000, clk1 => 40000, clk2 => 25000, clk3 => 15385, burstlen => 6)
port map(rstn, clkm, clkvga, apbi, apbo(6), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), clk_sel);
end generate;
vgadvi : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) /= 0 generate
dvi0 : svga2ch7301c generic map (tech => fabtech, dynamic => 1)
port map (lclk, rstraw, clk_sel, vgao, clkvga, clk25, clk40, clk65,
clkvga, clk25, clk40, clk65, clkvga_p, clkvga_n,
vgalock, lcd_datal, lcd_hsyncl, lcd_vsyncl, lcd_del);
i2cdvi : i2cmst
generic map (pindex => 9, paddr => 9, pmask => 16#FFF#,
pirq => 6, filter => I2C_FILTER)
port map (rstn, clkm, apbi, apbo(9), dvi_i2ci, dvi_i2co);
end generate;
novga : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) = 0 generate
apbo(6) <= apb_none; vgalock <= '1';
lcd_datal <= (others => '0'); clkvga_p <= '0'; clkvga_n <= '0';
lcd_hsyncl <= '0'; lcd_vsyncl <= '0'; lcd_del <= '0';
dvi_i2co.scloen <= '1'; dvi_i2co.sdaoen <= '1';
end generate;
tft_lcd_data_pad : outpadv generic map (width => 12, tech => padtech)
port map (tft_lcd_data, lcd_datal);
tft_lcd_clkp_pad : outpad generic map (tech => padtech)
port map (tft_lcd_clk_p, clkvga_p);
tft_lcd_clkn_pad : outpad generic map (tech => padtech)
port map (tft_lcd_clk_n, clkvga_n);
tft_lcd_hsync_pad : outpad generic map (tech => padtech)
port map (tft_lcd_hsync, lcd_hsyncl);
tft_lcd_vsync_pad : outpad generic map (tech => padtech)
port map (tft_lcd_vsync, lcd_vsyncl);
tft_lcd_de_pad : outpad generic map (tech => padtech)
port map (tft_lcd_de, lcd_del);
tft_lcd_reset_pad : outpad generic map (tech => padtech)
port map (tft_lcd_reset_b, rstn);
dvi_i2c_scl_pad : iopad generic map (tech => padtech)
port map (dvi_iic_scl, dvi_i2co.scl, dvi_i2co.scloen, dvi_i2ci.scl);
dvi_i2c_sda_pad : iopad generic map (tech => padtech)
port map (dvi_iic_sda, dvi_i2co.sda, dvi_i2co.sdaoen, dvi_i2ci.sda);
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 8, paddr => 8, imask => 16#00F0#, nbits => 14)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(8),
gpioi => gpioi, gpioo => gpioo);
gpio_pads : iopadvv generic map (tech => padtech, width => 14)
port map (gpio, gpioo.dout(13 downto 0), gpioo.oen(13 downto 0),
gpioi.din(13 downto 0));
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
stati <= ahbstat_in_none;
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master
i2c0 : i2cmst
generic map (pindex => 12, paddr => 12, pmask => 16#FFF#,
pirq => 11, filter => I2C_FILTER)
port map (rstn, clkm, apbi, apbo(12), i2ci, i2co);
i2c_scl_pad : iopad generic map (tech => padtech)
port map (iic_scl, i2co.scl, i2co.scloen, i2ci.scl);
i2c_sda_pad : iopad generic map (tech => padtech)
port map (iic_sda, i2co.sda, i2co.sdaoen, i2ci.sda);
end generate i2cm;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth1 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(hindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 11, paddr => 11, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 7,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G,
enable_mdint => 1)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
apbi => apbi, apbo => apbo(11), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (phy_mii_data, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (phy_tx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (phy_rx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 8)
port map (phy_rx_data, ethi.rxd(7 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (phy_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (phy_rx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (phy_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (phy_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 8)
port map (phy_tx_data, etho.txd(7 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( phy_tx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (phy_tx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (phy_mii_clk, etho.mdc);
erst_pad : outpad generic map (tech => padtech)
port map (phy_rst_n, rstn);
emdintn_pad : inpad generic map (tech => padtech)
port map (phy_int, ethi.mdint);
ethi.gtx_clk <= egtx_clk;
end generate;
-----------------------------------------------------------------------
--- SYSTEM MONITOR ---------------------------------------------------
-----------------------------------------------------------------------
grsmon: if CFG_GRSYSMON = 1 generate
sysm0 : grsysmon generic map (tech => fabtech, hindex => 5,
hirq => 10, caddr => 16#003#, cmask => 16#fff#,
saddr => 16#004#, smask => 16#ffe#, split => CFG_SPLIT,
extconvst => 0, wrdalign => 1, INIT_40 => X"0000",
INIT_41 => X"0000", INIT_42 => X"0800", INIT_43 => X"0000",
INIT_44 => X"0000", INIT_45 => X"0000", INIT_46 => X"0000",
INIT_47 => X"0000", INIT_48 => X"0000", INIT_49 => X"0000",
INIT_4A => X"0000", INIT_4B => X"0000", INIT_4C => X"0000",
INIT_4D => X"0000", INIT_4E => X"0000", INIT_4F => X"0000",
INIT_50 => X"0000", INIT_51 => X"0000", INIT_52 => X"0000",
INIT_53 => X"0000", INIT_54 => X"0000", INIT_55 => X"0000",
INIT_56 => X"0000", INIT_57 => X"0000",
SIM_MONITOR_FILE => "sysmon.txt")
port map (rstn, clkm, ahbsi, ahbso(5), sysmoni, sysmono);
sysmoni <= grsysmon_in_gnd;
end generate grsmon;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- AHB DEBUG --------------------------------------------------------
-----------------------------------------------------------------------
-- dma0 : ahbdma
-- generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG,
-- pindex => 13, paddr => 13, dbuf => 6)
-- port map (rstn, clkm, apbi, apbo(13), ahbmi,
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+CFG_GRETH));
-- at0 : ahbtrace
-- generic map ( hindex => 7, ioaddr => 16#200#, iomask => 16#E00#,
-- tech => memtech, irq => 0, kbytes => 8)
-- port map ( rstn, clkm, ahbmi, ahbsi, ahbso(7));
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+CFG_GRETH) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => system_table(XILINX_ML501),
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-3.0 | bf80bb8e0bdbf4d14f4767e53fc42d99 | 0.573358 | 3.303833 | false | false | false | false |
hoglet67/CoPro6502 | src/ROM/tuberom_65c102_banner_distram.vhd | 1 | 53,969 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity tuberom_65c102_banner is
port (
CLK : in std_logic;
ADDR : in std_logic_vector(10 downto 0);
DATA : out std_logic_vector(7 downto 0)
);
end;
architecture RTL of tuberom_65c102_banner is
type ram_type is array (0 to 2047) of std_logic_vector (7 downto 0);
signal RAM : ram_type := (
16#000# => x"a2",
16#001# => x"00",
16#002# => x"bd",
16#003# => x"00",
16#004# => x"ff",
16#005# => x"9d",
16#006# => x"00",
16#007# => x"ff",
16#008# => x"ca",
16#009# => x"d0",
16#00a# => x"f7",
16#00b# => x"a2",
16#00c# => x"36",
16#00d# => x"bd",
16#00e# => x"80",
16#00f# => x"ff",
16#010# => x"9d",
16#011# => x"00",
16#012# => x"02",
16#013# => x"ca",
16#014# => x"10",
16#015# => x"f7",
16#016# => x"9a",
16#017# => x"a2",
16#018# => x"f0",
16#019# => x"bd",
16#01a# => x"ff",
16#01b# => x"fd",
16#01c# => x"9d",
16#01d# => x"ff",
16#01e# => x"fd",
16#01f# => x"ca",
16#020# => x"d0",
16#021# => x"f7",
16#022# => x"a0",
16#023# => x"00",
16#024# => x"84",
16#025# => x"f8",
16#026# => x"a9",
16#027# => x"f8",
16#028# => x"85",
16#029# => x"f9",
16#02a# => x"b1",
16#02b# => x"f8",
16#02c# => x"91",
16#02d# => x"f8",
16#02e# => x"c8",
16#02f# => x"d0",
16#030# => x"f9",
16#031# => x"e6",
16#032# => x"f9",
16#033# => x"a5",
16#034# => x"f9",
16#035# => x"c9",
16#036# => x"fe",
16#037# => x"d0",
16#038# => x"f1",
16#039# => x"a2",
16#03a# => x"10",
16#03b# => x"bd",
16#03c# => x"59",
16#03d# => x"f8",
16#03e# => x"9d",
16#03f# => x"00",
16#040# => x"01",
16#041# => x"ca",
16#042# => x"10",
16#043# => x"f7",
16#044# => x"a5",
16#045# => x"ee",
16#046# => x"85",
16#047# => x"f6",
16#048# => x"a5",
16#049# => x"ef",
16#04a# => x"85",
16#04b# => x"f7",
16#04c# => x"a9",
16#04d# => x"00",
16#04e# => x"85",
16#04f# => x"ff",
16#050# => x"85",
16#051# => x"f2",
16#052# => x"a9",
16#053# => x"f8",
16#054# => x"85",
16#055# => x"f3",
16#056# => x"4c",
16#057# => x"00",
16#058# => x"01",
16#059# => x"ad",
16#05a# => x"f8",
16#05b# => x"fe",
16#05c# => x"58",
16#05d# => x"4c",
16#05e# => x"60",
16#05f# => x"f8",
16#060# => x"20",
16#061# => x"a5",
16#062# => x"fe",
16#063# => x"0a",
16#064# => x"41",
16#065# => x"63",
16#066# => x"6f",
16#067# => x"72",
16#068# => x"6e",
16#069# => x"20",
16#06a# => x"54",
16#06b# => x"55",
16#06c# => x"42",
16#06d# => x"45",
16#06e# => x"20",
16#06f# => x"3f",
16#070# => x"3f",
16#071# => x"4d",
16#072# => x"48",
16#073# => x"7a",
16#074# => x"20",
16#075# => x"36",
16#076# => x"35",
16#077# => x"43",
16#078# => x"31",
16#079# => x"30",
16#07a# => x"32",
16#07b# => x"20",
16#07c# => x"43",
16#07d# => x"6f",
16#07e# => x"2d",
16#07f# => x"50",
16#080# => x"72",
16#081# => x"6f",
16#082# => x"0a",
16#083# => x"0a",
16#084# => x"0d",
16#085# => x"00",
16#086# => x"ea",
16#087# => x"a9",
16#088# => x"98",
16#089# => x"8d",
16#08a# => x"5e",
16#08b# => x"f8",
16#08c# => x"a9",
16#08d# => x"f8",
16#08e# => x"8d",
16#08f# => x"5f",
16#090# => x"f8",
16#091# => x"20",
16#092# => x"80",
16#093# => x"f9",
16#094# => x"c9",
16#095# => x"80",
16#096# => x"f0",
16#097# => x"28",
16#098# => x"a9",
16#099# => x"2a",
16#09a# => x"20",
16#09b# => x"ee",
16#09c# => x"ff",
16#09d# => x"a2",
16#09e# => x"68",
16#09f# => x"a0",
16#0a0# => x"f9",
16#0a1# => x"a9",
16#0a2# => x"00",
16#0a3# => x"20",
16#0a4# => x"f1",
16#0a5# => x"ff",
16#0a6# => x"b0",
16#0a7# => x"0a",
16#0a8# => x"a2",
16#0a9# => x"36",
16#0aa# => x"a0",
16#0ab# => x"02",
16#0ac# => x"20",
16#0ad# => x"f7",
16#0ae# => x"ff",
16#0af# => x"4c",
16#0b0# => x"98",
16#0b1# => x"f8",
16#0b2# => x"a9",
16#0b3# => x"7e",
16#0b4# => x"20",
16#0b5# => x"f4",
16#0b6# => x"ff",
16#0b7# => x"00",
16#0b8# => x"11",
16#0b9# => x"45",
16#0ba# => x"73",
16#0bb# => x"63",
16#0bc# => x"61",
16#0bd# => x"70",
16#0be# => x"65",
16#0bf# => x"00",
16#0c0# => x"a5",
16#0c1# => x"f6",
16#0c2# => x"85",
16#0c3# => x"ee",
16#0c4# => x"85",
16#0c5# => x"f2",
16#0c6# => x"a5",
16#0c7# => x"f7",
16#0c8# => x"85",
16#0c9# => x"ef",
16#0ca# => x"85",
16#0cb# => x"f3",
16#0cc# => x"a0",
16#0cd# => x"07",
16#0ce# => x"b1",
16#0cf# => x"ee",
16#0d0# => x"d8",
16#0d1# => x"18",
16#0d2# => x"65",
16#0d3# => x"ee",
16#0d4# => x"85",
16#0d5# => x"fd",
16#0d6# => x"a9",
16#0d7# => x"00",
16#0d8# => x"65",
16#0d9# => x"ef",
16#0da# => x"85",
16#0db# => x"fe",
16#0dc# => x"a0",
16#0dd# => x"00",
16#0de# => x"b1",
16#0df# => x"fd",
16#0e0# => x"d0",
16#0e1# => x"23",
16#0e2# => x"c8",
16#0e3# => x"b1",
16#0e4# => x"fd",
16#0e5# => x"c9",
16#0e6# => x"28",
16#0e7# => x"d0",
16#0e8# => x"1c",
16#0e9# => x"c8",
16#0ea# => x"b1",
16#0eb# => x"fd",
16#0ec# => x"c9",
16#0ed# => x"43",
16#0ee# => x"d0",
16#0ef# => x"15",
16#0f0# => x"c8",
16#0f1# => x"b1",
16#0f2# => x"fd",
16#0f3# => x"c9",
16#0f4# => x"29",
16#0f5# => x"d0",
16#0f6# => x"0e",
16#0f7# => x"a0",
16#0f8# => x"06",
16#0f9# => x"b1",
16#0fa# => x"ee",
16#0fb# => x"29",
16#0fc# => x"4f",
16#0fd# => x"c9",
16#0fe# => x"40",
16#0ff# => x"90",
16#100# => x"09",
16#101# => x"29",
16#102# => x"0d",
16#103# => x"d0",
16#104# => x"28",
16#105# => x"a9",
16#106# => x"01",
16#107# => x"6c",
16#108# => x"f2",
16#109# => x"00",
16#10a# => x"a9",
16#10b# => x"50",
16#10c# => x"8d",
16#10d# => x"02",
16#10e# => x"02",
16#10f# => x"a9",
16#110# => x"f9",
16#111# => x"8d",
16#112# => x"03",
16#113# => x"02",
16#114# => x"00",
16#115# => x"00",
16#116# => x"54",
16#117# => x"68",
16#118# => x"69",
16#119# => x"73",
16#11a# => x"20",
16#11b# => x"69",
16#11c# => x"73",
16#11d# => x"20",
16#11e# => x"6e",
16#11f# => x"6f",
16#120# => x"74",
16#121# => x"20",
16#122# => x"61",
16#123# => x"20",
16#124# => x"6c",
16#125# => x"61",
16#126# => x"6e",
16#127# => x"67",
16#128# => x"75",
16#129# => x"61",
16#12a# => x"67",
16#12b# => x"65",
16#12c# => x"00",
16#12d# => x"a9",
16#12e# => x"50",
16#12f# => x"8d",
16#130# => x"02",
16#131# => x"02",
16#132# => x"a9",
16#133# => x"f9",
16#134# => x"8d",
16#135# => x"03",
16#136# => x"02",
16#137# => x"00",
16#138# => x"00",
16#139# => x"49",
16#13a# => x"20",
16#13b# => x"63",
16#13c# => x"61",
16#13d# => x"6e",
16#13e# => x"6e",
16#13f# => x"6f",
16#140# => x"74",
16#141# => x"20",
16#142# => x"72",
16#143# => x"75",
16#144# => x"6e",
16#145# => x"20",
16#146# => x"74",
16#147# => x"68",
16#148# => x"69",
16#149# => x"73",
16#14a# => x"20",
16#14b# => x"63",
16#14c# => x"6f",
16#14d# => x"64",
16#14e# => x"65",
16#14f# => x"00",
16#150# => x"a2",
16#151# => x"ff",
16#152# => x"9a",
16#153# => x"20",
16#154# => x"e7",
16#155# => x"ff",
16#156# => x"a0",
16#157# => x"01",
16#158# => x"b1",
16#159# => x"fd",
16#15a# => x"f0",
16#15b# => x"06",
16#15c# => x"20",
16#15d# => x"ee",
16#15e# => x"ff",
16#15f# => x"c8",
16#160# => x"d0",
16#161# => x"f6",
16#162# => x"20",
16#163# => x"e7",
16#164# => x"ff",
16#165# => x"4c",
16#166# => x"98",
16#167# => x"f8",
16#168# => x"36",
16#169# => x"02",
16#16a# => x"ca",
16#16b# => x"20",
16#16c# => x"ff",
16#16d# => x"2c",
16#16e# => x"f8",
16#16f# => x"fe",
16#170# => x"ea",
16#171# => x"50",
16#172# => x"fa",
16#173# => x"8d",
16#174# => x"f9",
16#175# => x"fe",
16#176# => x"60",
16#177# => x"a9",
16#178# => x"00",
16#179# => x"20",
16#17a# => x"57",
16#17b# => x"fc",
16#17c# => x"20",
16#17d# => x"80",
16#17e# => x"f9",
16#17f# => x"0a",
16#180# => x"2c",
16#181# => x"fa",
16#182# => x"fe",
16#183# => x"10",
16#184# => x"fb",
16#185# => x"ad",
16#186# => x"fb",
16#187# => x"fe",
16#188# => x"60",
16#189# => x"c8",
16#18a# => x"b1",
16#18b# => x"f8",
16#18c# => x"c9",
16#18d# => x"20",
16#18e# => x"f0",
16#18f# => x"f9",
16#190# => x"60",
16#191# => x"a2",
16#192# => x"00",
16#193# => x"86",
16#194# => x"f0",
16#195# => x"86",
16#196# => x"f1",
16#197# => x"b1",
16#198# => x"f8",
16#199# => x"c9",
16#19a# => x"30",
16#19b# => x"90",
16#19c# => x"1f",
16#19d# => x"c9",
16#19e# => x"3a",
16#19f# => x"90",
16#1a0# => x"0a",
16#1a1# => x"29",
16#1a2# => x"df",
16#1a3# => x"e9",
16#1a4# => x"07",
16#1a5# => x"90",
16#1a6# => x"15",
16#1a7# => x"c9",
16#1a8# => x"40",
16#1a9# => x"b0",
16#1aa# => x"11",
16#1ab# => x"0a",
16#1ac# => x"0a",
16#1ad# => x"0a",
16#1ae# => x"0a",
16#1af# => x"a2",
16#1b0# => x"03",
16#1b1# => x"0a",
16#1b2# => x"26",
16#1b3# => x"f0",
16#1b4# => x"26",
16#1b5# => x"f1",
16#1b6# => x"ca",
16#1b7# => x"10",
16#1b8# => x"f8",
16#1b9# => x"c8",
16#1ba# => x"d0",
16#1bb# => x"db",
16#1bc# => x"60",
16#1bd# => x"86",
16#1be# => x"f8",
16#1bf# => x"84",
16#1c0# => x"f9",
16#1c1# => x"a0",
16#1c2# => x"00",
16#1c3# => x"2c",
16#1c4# => x"fa",
16#1c5# => x"fe",
16#1c6# => x"50",
16#1c7# => x"fb",
16#1c8# => x"b1",
16#1c9# => x"f8",
16#1ca# => x"8d",
16#1cb# => x"fb",
16#1cc# => x"fe",
16#1cd# => x"c8",
16#1ce# => x"c9",
16#1cf# => x"0d",
16#1d0# => x"d0",
16#1d1# => x"f1",
16#1d2# => x"a4",
16#1d3# => x"f9",
16#1d4# => x"60",
16#1d5# => x"48",
16#1d6# => x"86",
16#1d7# => x"f8",
16#1d8# => x"84",
16#1d9# => x"f9",
16#1da# => x"a0",
16#1db# => x"00",
16#1dc# => x"20",
16#1dd# => x"8a",
16#1de# => x"f9",
16#1df# => x"c8",
16#1e0# => x"c9",
16#1e1# => x"2a",
16#1e2# => x"f0",
16#1e3# => x"f8",
16#1e4# => x"29",
16#1e5# => x"df",
16#1e6# => x"aa",
16#1e7# => x"b1",
16#1e8# => x"f8",
16#1e9# => x"e0",
16#1ea# => x"47",
16#1eb# => x"f0",
16#1ec# => x"5e",
16#1ed# => x"e0",
16#1ee# => x"48",
16#1ef# => x"d0",
16#1f0# => x"49",
16#1f1# => x"c9",
16#1f2# => x"2e",
16#1f3# => x"f0",
16#1f4# => x"2d",
16#1f5# => x"29",
16#1f6# => x"df",
16#1f7# => x"c9",
16#1f8# => x"45",
16#1f9# => x"d0",
16#1fa# => x"3f",
16#1fb# => x"c8",
16#1fc# => x"b1",
16#1fd# => x"f8",
16#1fe# => x"c9",
16#1ff# => x"2e",
16#200# => x"f0",
16#201# => x"20",
16#202# => x"29",
16#203# => x"df",
16#204# => x"c9",
16#205# => x"4c",
16#206# => x"d0",
16#207# => x"32",
16#208# => x"c8",
16#209# => x"b1",
16#20a# => x"f8",
16#20b# => x"c9",
16#20c# => x"2e",
16#20d# => x"f0",
16#20e# => x"13",
16#20f# => x"29",
16#210# => x"df",
16#211# => x"c9",
16#212# => x"50",
16#213# => x"d0",
16#214# => x"25",
16#215# => x"c8",
16#216# => x"b1",
16#217# => x"f8",
16#218# => x"29",
16#219# => x"df",
16#21a# => x"c9",
16#21b# => x"41",
16#21c# => x"90",
16#21d# => x"04",
16#21e# => x"c9",
16#21f# => x"5b",
16#220# => x"90",
16#221# => x"18",
16#222# => x"20",
16#223# => x"a5",
16#224# => x"fe",
16#225# => x"0a",
16#226# => x"0d",
16#227# => x"36",
16#228# => x"35",
16#229# => x"43",
16#22a# => x"31",
16#22b# => x"30",
16#22c# => x"32",
16#22d# => x"20",
16#22e# => x"54",
16#22f# => x"55",
16#230# => x"42",
16#231# => x"45",
16#232# => x"20",
16#233# => x"31",
16#234# => x"2e",
16#235# => x"31",
16#236# => x"30",
16#237# => x"0a",
16#238# => x"0d",
16#239# => x"ea",
16#23a# => x"a9",
16#23b# => x"02",
16#23c# => x"20",
16#23d# => x"57",
16#23e# => x"fc",
16#23f# => x"20",
16#240# => x"c1",
16#241# => x"f9",
16#242# => x"20",
16#243# => x"80",
16#244# => x"f9",
16#245# => x"c9",
16#246# => x"80",
16#247# => x"f0",
16#248# => x"20",
16#249# => x"68",
16#24a# => x"60",
16#24b# => x"29",
16#24c# => x"df",
16#24d# => x"c9",
16#24e# => x"4f",
16#24f# => x"d0",
16#250# => x"e9",
16#251# => x"20",
16#252# => x"89",
16#253# => x"f9",
16#254# => x"20",
16#255# => x"91",
16#256# => x"f9",
16#257# => x"20",
16#258# => x"8a",
16#259# => x"f9",
16#25a# => x"c9",
16#25b# => x"0d",
16#25c# => x"d0",
16#25d# => x"dc",
16#25e# => x"8a",
16#25f# => x"f0",
16#260# => x"08",
16#261# => x"a5",
16#262# => x"f0",
16#263# => x"85",
16#264# => x"f6",
16#265# => x"a5",
16#266# => x"f1",
16#267# => x"85",
16#268# => x"f7",
16#269# => x"a5",
16#26a# => x"ef",
16#26b# => x"48",
16#26c# => x"a5",
16#26d# => x"ee",
16#26e# => x"48",
16#26f# => x"20",
16#270# => x"c0",
16#271# => x"f8",
16#272# => x"68",
16#273# => x"85",
16#274# => x"ee",
16#275# => x"85",
16#276# => x"f2",
16#277# => x"68",
16#278# => x"85",
16#279# => x"ef",
16#27a# => x"85",
16#27b# => x"f3",
16#27c# => x"68",
16#27d# => x"60",
16#27e# => x"f0",
16#27f# => x"c2",
16#280# => x"c9",
16#281# => x"80",
16#282# => x"b0",
16#283# => x"25",
16#284# => x"48",
16#285# => x"a9",
16#286# => x"04",
16#287# => x"2c",
16#288# => x"fa",
16#289# => x"fe",
16#28a# => x"50",
16#28b# => x"fb",
16#28c# => x"8d",
16#28d# => x"fb",
16#28e# => x"fe",
16#28f# => x"2c",
16#290# => x"fa",
16#291# => x"fe",
16#292# => x"50",
16#293# => x"fb",
16#294# => x"8e",
16#295# => x"fb",
16#296# => x"fe",
16#297# => x"68",
16#298# => x"2c",
16#299# => x"fa",
16#29a# => x"fe",
16#29b# => x"50",
16#29c# => x"fb",
16#29d# => x"8d",
16#29e# => x"fb",
16#29f# => x"fe",
16#2a0# => x"2c",
16#2a1# => x"fa",
16#2a2# => x"fe",
16#2a3# => x"10",
16#2a4# => x"fb",
16#2a5# => x"ae",
16#2a6# => x"fb",
16#2a7# => x"fe",
16#2a8# => x"60",
16#2a9# => x"c9",
16#2aa# => x"82",
16#2ab# => x"f0",
16#2ac# => x"5a",
16#2ad# => x"c9",
16#2ae# => x"83",
16#2af# => x"f0",
16#2b0# => x"51",
16#2b1# => x"c9",
16#2b2# => x"84",
16#2b3# => x"f0",
16#2b4# => x"48",
16#2b5# => x"48",
16#2b6# => x"a9",
16#2b7# => x"06",
16#2b8# => x"2c",
16#2b9# => x"fa",
16#2ba# => x"fe",
16#2bb# => x"50",
16#2bc# => x"fb",
16#2bd# => x"8d",
16#2be# => x"fb",
16#2bf# => x"fe",
16#2c0# => x"2c",
16#2c1# => x"fa",
16#2c2# => x"fe",
16#2c3# => x"50",
16#2c4# => x"fb",
16#2c5# => x"8e",
16#2c6# => x"fb",
16#2c7# => x"fe",
16#2c8# => x"2c",
16#2c9# => x"fa",
16#2ca# => x"fe",
16#2cb# => x"50",
16#2cc# => x"fb",
16#2cd# => x"8c",
16#2ce# => x"fb",
16#2cf# => x"fe",
16#2d0# => x"68",
16#2d1# => x"2c",
16#2d2# => x"fa",
16#2d3# => x"fe",
16#2d4# => x"50",
16#2d5# => x"fb",
16#2d6# => x"8d",
16#2d7# => x"fb",
16#2d8# => x"fe",
16#2d9# => x"c9",
16#2da# => x"8e",
16#2db# => x"f0",
16#2dc# => x"a1",
16#2dd# => x"c9",
16#2de# => x"9d",
16#2df# => x"f0",
16#2e0# => x"1b",
16#2e1# => x"48",
16#2e2# => x"2c",
16#2e3# => x"fa",
16#2e4# => x"fe",
16#2e5# => x"10",
16#2e6# => x"fb",
16#2e7# => x"ad",
16#2e8# => x"fb",
16#2e9# => x"fe",
16#2ea# => x"0a",
16#2eb# => x"68",
16#2ec# => x"2c",
16#2ed# => x"fa",
16#2ee# => x"fe",
16#2ef# => x"10",
16#2f0# => x"fb",
16#2f1# => x"ac",
16#2f2# => x"fb",
16#2f3# => x"fe",
16#2f4# => x"2c",
16#2f5# => x"fa",
16#2f6# => x"fe",
16#2f7# => x"10",
16#2f8# => x"fb",
16#2f9# => x"ae",
16#2fa# => x"fb",
16#2fb# => x"fe",
16#2fc# => x"60",
16#2fd# => x"a6",
16#2fe# => x"f2",
16#2ff# => x"a4",
16#300# => x"f3",
16#301# => x"60",
16#302# => x"a2",
16#303# => x"00",
16#304# => x"a0",
16#305# => x"08",
16#306# => x"60",
16#307# => x"a2",
16#308# => x"00",
16#309# => x"a0",
16#30a# => x"00",
16#30b# => x"60",
16#30c# => x"86",
16#30d# => x"f8",
16#30e# => x"84",
16#30f# => x"f9",
16#310# => x"a8",
16#311# => x"f0",
16#312# => x"71",
16#313# => x"48",
16#314# => x"a0",
16#315# => x"08",
16#316# => x"2c",
16#317# => x"fa",
16#318# => x"fe",
16#319# => x"50",
16#31a# => x"fb",
16#31b# => x"8c",
16#31c# => x"fb",
16#31d# => x"fe",
16#31e# => x"2c",
16#31f# => x"fa",
16#320# => x"fe",
16#321# => x"50",
16#322# => x"fb",
16#323# => x"8d",
16#324# => x"fb",
16#325# => x"fe",
16#326# => x"aa",
16#327# => x"10",
16#328# => x"08",
16#329# => x"a0",
16#32a# => x"00",
16#32b# => x"b1",
16#32c# => x"f8",
16#32d# => x"a8",
16#32e# => x"4c",
16#32f# => x"3a",
16#330# => x"fb",
16#331# => x"bc",
16#332# => x"c9",
16#333# => x"fc",
16#334# => x"e0",
16#335# => x"15",
16#336# => x"90",
16#337# => x"02",
16#338# => x"a0",
16#339# => x"10",
16#33a# => x"2c",
16#33b# => x"fa",
16#33c# => x"fe",
16#33d# => x"50",
16#33e# => x"fb",
16#33f# => x"8c",
16#340# => x"fb",
16#341# => x"fe",
16#342# => x"88",
16#343# => x"30",
16#344# => x"0d",
16#345# => x"2c",
16#346# => x"fa",
16#347# => x"fe",
16#348# => x"50",
16#349# => x"fb",
16#34a# => x"b1",
16#34b# => x"f8",
16#34c# => x"8d",
16#34d# => x"fb",
16#34e# => x"fe",
16#34f# => x"88",
16#350# => x"10",
16#351# => x"f3",
16#352# => x"8a",
16#353# => x"10",
16#354# => x"08",
16#355# => x"a0",
16#356# => x"01",
16#357# => x"b1",
16#358# => x"f8",
16#359# => x"a8",
16#35a# => x"4c",
16#35b# => x"66",
16#35c# => x"fb",
16#35d# => x"bc",
16#35e# => x"dd",
16#35f# => x"fc",
16#360# => x"e0",
16#361# => x"15",
16#362# => x"90",
16#363# => x"02",
16#364# => x"a0",
16#365# => x"10",
16#366# => x"2c",
16#367# => x"fa",
16#368# => x"fe",
16#369# => x"50",
16#36a# => x"fb",
16#36b# => x"8c",
16#36c# => x"fb",
16#36d# => x"fe",
16#36e# => x"88",
16#36f# => x"30",
16#370# => x"0d",
16#371# => x"2c",
16#372# => x"fa",
16#373# => x"fe",
16#374# => x"10",
16#375# => x"fb",
16#376# => x"ad",
16#377# => x"fb",
16#378# => x"fe",
16#379# => x"91",
16#37a# => x"f8",
16#37b# => x"88",
16#37c# => x"10",
16#37d# => x"f3",
16#37e# => x"a4",
16#37f# => x"f9",
16#380# => x"a6",
16#381# => x"f8",
16#382# => x"68",
16#383# => x"60",
16#384# => x"a9",
16#385# => x"0a",
16#386# => x"20",
16#387# => x"57",
16#388# => x"fc",
16#389# => x"a0",
16#38a# => x"04",
16#38b# => x"2c",
16#38c# => x"fa",
16#38d# => x"fe",
16#38e# => x"50",
16#38f# => x"fb",
16#390# => x"b1",
16#391# => x"f8",
16#392# => x"8d",
16#393# => x"fb",
16#394# => x"fe",
16#395# => x"88",
16#396# => x"c0",
16#397# => x"01",
16#398# => x"d0",
16#399# => x"f1",
16#39a# => x"a9",
16#39b# => x"07",
16#39c# => x"20",
16#39d# => x"57",
16#39e# => x"fc",
16#39f# => x"b1",
16#3a0# => x"f8",
16#3a1# => x"48",
16#3a2# => x"88",
16#3a3# => x"2c",
16#3a4# => x"fa",
16#3a5# => x"fe",
16#3a6# => x"50",
16#3a7# => x"fb",
16#3a8# => x"8c",
16#3a9# => x"fb",
16#3aa# => x"fe",
16#3ab# => x"b1",
16#3ac# => x"f8",
16#3ad# => x"48",
16#3ae# => x"a2",
16#3af# => x"ff",
16#3b0# => x"20",
16#3b1# => x"80",
16#3b2# => x"f9",
16#3b3# => x"c9",
16#3b4# => x"80",
16#3b5# => x"b0",
16#3b6# => x"1d",
16#3b7# => x"68",
16#3b8# => x"85",
16#3b9# => x"f8",
16#3ba# => x"68",
16#3bb# => x"85",
16#3bc# => x"f9",
16#3bd# => x"a0",
16#3be# => x"00",
16#3bf# => x"2c",
16#3c0# => x"fa",
16#3c1# => x"fe",
16#3c2# => x"10",
16#3c3# => x"fb",
16#3c4# => x"ad",
16#3c5# => x"fb",
16#3c6# => x"fe",
16#3c7# => x"91",
16#3c8# => x"f8",
16#3c9# => x"c8",
16#3ca# => x"c9",
16#3cb# => x"0d",
16#3cc# => x"d0",
16#3cd# => x"f1",
16#3ce# => x"a9",
16#3cf# => x"00",
16#3d0# => x"88",
16#3d1# => x"18",
16#3d2# => x"e8",
16#3d3# => x"60",
16#3d4# => x"68",
16#3d5# => x"68",
16#3d6# => x"a9",
16#3d7# => x"00",
16#3d8# => x"60",
16#3d9# => x"48",
16#3da# => x"a9",
16#3db# => x"0c",
16#3dc# => x"20",
16#3dd# => x"57",
16#3de# => x"fc",
16#3df# => x"2c",
16#3e0# => x"fa",
16#3e1# => x"fe",
16#3e2# => x"50",
16#3e3# => x"fb",
16#3e4# => x"8c",
16#3e5# => x"fb",
16#3e6# => x"fe",
16#3e7# => x"b5",
16#3e8# => x"03",
16#3e9# => x"20",
16#3ea# => x"57",
16#3eb# => x"fc",
16#3ec# => x"b5",
16#3ed# => x"02",
16#3ee# => x"20",
16#3ef# => x"57",
16#3f0# => x"fc",
16#3f1# => x"b5",
16#3f2# => x"01",
16#3f3# => x"20",
16#3f4# => x"57",
16#3f5# => x"fc",
16#3f6# => x"b5",
16#3f7# => x"00",
16#3f8# => x"20",
16#3f9# => x"57",
16#3fa# => x"fc",
16#3fb# => x"68",
16#3fc# => x"20",
16#3fd# => x"57",
16#3fe# => x"fc",
16#3ff# => x"20",
16#400# => x"80",
16#401# => x"f9",
16#402# => x"48",
16#403# => x"20",
16#404# => x"80",
16#405# => x"f9",
16#406# => x"95",
16#407# => x"03",
16#408# => x"20",
16#409# => x"80",
16#40a# => x"f9",
16#40b# => x"95",
16#40c# => x"02",
16#40d# => x"20",
16#40e# => x"80",
16#40f# => x"f9",
16#410# => x"95",
16#411# => x"01",
16#412# => x"20",
16#413# => x"80",
16#414# => x"f9",
16#415# => x"95",
16#416# => x"00",
16#417# => x"68",
16#418# => x"60",
16#419# => x"48",
16#41a# => x"a9",
16#41b# => x"12",
16#41c# => x"20",
16#41d# => x"57",
16#41e# => x"fc",
16#41f# => x"68",
16#420# => x"20",
16#421# => x"57",
16#422# => x"fc",
16#423# => x"c9",
16#424# => x"00",
16#425# => x"d0",
16#426# => x"0a",
16#427# => x"48",
16#428# => x"98",
16#429# => x"20",
16#42a# => x"57",
16#42b# => x"fc",
16#42c# => x"20",
16#42d# => x"80",
16#42e# => x"f9",
16#42f# => x"68",
16#430# => x"60",
16#431# => x"20",
16#432# => x"bd",
16#433# => x"f9",
16#434# => x"4c",
16#435# => x"80",
16#436# => x"f9",
16#437# => x"a9",
16#438# => x"0e",
16#439# => x"20",
16#43a# => x"57",
16#43b# => x"fc",
16#43c# => x"98",
16#43d# => x"20",
16#43e# => x"57",
16#43f# => x"fc",
16#440# => x"4c",
16#441# => x"7c",
16#442# => x"f9",
16#443# => x"48",
16#444# => x"a9",
16#445# => x"10",
16#446# => x"20",
16#447# => x"57",
16#448# => x"fc",
16#449# => x"98",
16#44a# => x"20",
16#44b# => x"57",
16#44c# => x"fc",
16#44d# => x"68",
16#44e# => x"20",
16#44f# => x"57",
16#450# => x"fc",
16#451# => x"48",
16#452# => x"20",
16#453# => x"80",
16#454# => x"f9",
16#455# => x"68",
16#456# => x"60",
16#457# => x"2c",
16#458# => x"fa",
16#459# => x"fe",
16#45a# => x"50",
16#45b# => x"fb",
16#45c# => x"8d",
16#45d# => x"fb",
16#45e# => x"fe",
16#45f# => x"60",
16#460# => x"84",
16#461# => x"fb",
16#462# => x"86",
16#463# => x"fa",
16#464# => x"48",
16#465# => x"a9",
16#466# => x"14",
16#467# => x"20",
16#468# => x"57",
16#469# => x"fc",
16#46a# => x"a0",
16#46b# => x"11",
16#46c# => x"b1",
16#46d# => x"fa",
16#46e# => x"20",
16#46f# => x"57",
16#470# => x"fc",
16#471# => x"88",
16#472# => x"c0",
16#473# => x"01",
16#474# => x"d0",
16#475# => x"f6",
16#476# => x"88",
16#477# => x"b1",
16#478# => x"fa",
16#479# => x"aa",
16#47a# => x"c8",
16#47b# => x"b1",
16#47c# => x"fa",
16#47d# => x"a8",
16#47e# => x"20",
16#47f# => x"bd",
16#480# => x"f9",
16#481# => x"68",
16#482# => x"20",
16#483# => x"57",
16#484# => x"fc",
16#485# => x"20",
16#486# => x"80",
16#487# => x"f9",
16#488# => x"48",
16#489# => x"a0",
16#48a# => x"11",
16#48b# => x"20",
16#48c# => x"80",
16#48d# => x"f9",
16#48e# => x"91",
16#48f# => x"fa",
16#490# => x"88",
16#491# => x"c0",
16#492# => x"01",
16#493# => x"d0",
16#494# => x"f6",
16#495# => x"a4",
16#496# => x"fb",
16#497# => x"a6",
16#498# => x"fa",
16#499# => x"68",
16#49a# => x"60",
16#49b# => x"84",
16#49c# => x"fb",
16#49d# => x"86",
16#49e# => x"fa",
16#49f# => x"48",
16#4a0# => x"a9",
16#4a1# => x"16",
16#4a2# => x"20",
16#4a3# => x"57",
16#4a4# => x"fc",
16#4a5# => x"a0",
16#4a6# => x"0c",
16#4a7# => x"b1",
16#4a8# => x"fa",
16#4a9# => x"20",
16#4aa# => x"57",
16#4ab# => x"fc",
16#4ac# => x"88",
16#4ad# => x"10",
16#4ae# => x"f8",
16#4af# => x"68",
16#4b0# => x"20",
16#4b1# => x"57",
16#4b2# => x"fc",
16#4b3# => x"a0",
16#4b4# => x"0c",
16#4b5# => x"20",
16#4b6# => x"80",
16#4b7# => x"f9",
16#4b8# => x"91",
16#4b9# => x"fa",
16#4ba# => x"88",
16#4bb# => x"10",
16#4bc# => x"f8",
16#4bd# => x"a4",
16#4be# => x"fb",
16#4bf# => x"a6",
16#4c0# => x"fa",
16#4c1# => x"4c",
16#4c2# => x"7c",
16#4c3# => x"f9",
16#4c4# => x"00",
16#4c5# => x"ff",
16#4c6# => x"42",
16#4c7# => x"61",
16#4c8# => x"64",
16#4c9# => x"00",
16#4ca# => x"00",
16#4cb# => x"05",
16#4cc# => x"00",
16#4cd# => x"05",
16#4ce# => x"04",
16#4cf# => x"05",
16#4d0# => x"08",
16#4d1# => x"0e",
16#4d2# => x"04",
16#4d3# => x"01",
16#4d4# => x"01",
16#4d5# => x"05",
16#4d6# => x"00",
16#4d7# => x"01",
16#4d8# => x"20",
16#4d9# => x"10",
16#4da# => x"0d",
16#4db# => x"00",
16#4dc# => x"04",
16#4dd# => x"80",
16#4de# => x"05",
16#4df# => x"00",
16#4e0# => x"05",
16#4e1# => x"00",
16#4e2# => x"05",
16#4e3# => x"00",
16#4e4# => x"00",
16#4e5# => x"00",
16#4e6# => x"05",
16#4e7# => x"09",
16#4e8# => x"05",
16#4e9# => x"00",
16#4ea# => x"08",
16#4eb# => x"18",
16#4ec# => x"00",
16#4ed# => x"01",
16#4ee# => x"0d",
16#4ef# => x"80",
16#4f0# => x"04",
16#4f1# => x"80",
16#4f2# => x"85",
16#4f3# => x"fc",
16#4f4# => x"68",
16#4f5# => x"48",
16#4f6# => x"29",
16#4f7# => x"10",
16#4f8# => x"d0",
16#4f9# => x"10",
16#4fa# => x"6c",
16#4fb# => x"04",
16#4fc# => x"02",
16#4fd# => x"2c",
16#4fe# => x"fe",
16#4ff# => x"fe",
16#500# => x"30",
16#501# => x"4a",
16#502# => x"2c",
16#503# => x"f8",
16#504# => x"fe",
16#505# => x"30",
16#506# => x"1e",
16#507# => x"6c",
16#508# => x"06",
16#509# => x"02",
16#50a# => x"8a",
16#50b# => x"48",
16#50c# => x"ba",
16#50d# => x"bd",
16#50e# => x"03",
16#50f# => x"01",
16#510# => x"d8",
16#511# => x"38",
16#512# => x"e9",
16#513# => x"01",
16#514# => x"85",
16#515# => x"fd",
16#516# => x"bd",
16#517# => x"04",
16#518# => x"01",
16#519# => x"e9",
16#51a# => x"00",
16#51b# => x"85",
16#51c# => x"fe",
16#51d# => x"68",
16#51e# => x"aa",
16#51f# => x"a5",
16#520# => x"fc",
16#521# => x"58",
16#522# => x"6c",
16#523# => x"02",
16#524# => x"02",
16#525# => x"ad",
16#526# => x"f9",
16#527# => x"fe",
16#528# => x"30",
16#529# => x"1c",
16#52a# => x"98",
16#52b# => x"48",
16#52c# => x"8a",
16#52d# => x"48",
16#52e# => x"20",
16#52f# => x"8d",
16#530# => x"fe",
16#531# => x"a8",
16#532# => x"20",
16#533# => x"8d",
16#534# => x"fe",
16#535# => x"aa",
16#536# => x"20",
16#537# => x"8d",
16#538# => x"fe",
16#539# => x"20",
16#53a# => x"43",
16#53b# => x"fd",
16#53c# => x"68",
16#53d# => x"aa",
16#53e# => x"68",
16#53f# => x"a8",
16#540# => x"a5",
16#541# => x"fc",
16#542# => x"40",
16#543# => x"6c",
16#544# => x"20",
16#545# => x"02",
16#546# => x"0a",
16#547# => x"85",
16#548# => x"ff",
16#549# => x"a5",
16#54a# => x"fc",
16#54b# => x"40",
16#54c# => x"ad",
16#54d# => x"ff",
16#54e# => x"fe",
16#54f# => x"10",
16#550# => x"21",
16#551# => x"58",
16#552# => x"2c",
16#553# => x"fa",
16#554# => x"fe",
16#555# => x"10",
16#556# => x"fb",
16#557# => x"ad",
16#558# => x"fb",
16#559# => x"fe",
16#55a# => x"a9",
16#55b# => x"00",
16#55c# => x"8d",
16#55d# => x"36",
16#55e# => x"02",
16#55f# => x"a8",
16#560# => x"20",
16#561# => x"80",
16#562# => x"f9",
16#563# => x"8d",
16#564# => x"37",
16#565# => x"02",
16#566# => x"c8",
16#567# => x"20",
16#568# => x"80",
16#569# => x"f9",
16#56a# => x"99",
16#56b# => x"37",
16#56c# => x"02",
16#56d# => x"d0",
16#56e# => x"f7",
16#56f# => x"4c",
16#570# => x"36",
16#571# => x"02",
16#572# => x"8d",
16#573# => x"fa",
16#574# => x"ff",
16#575# => x"98",
16#576# => x"48",
16#577# => x"ac",
16#578# => x"fa",
16#579# => x"ff",
16#57a# => x"b9",
16#57b# => x"7d",
16#57c# => x"fe",
16#57d# => x"8d",
16#57e# => x"fa",
16#57f# => x"ff",
16#580# => x"b9",
16#581# => x"85",
16#582# => x"fe",
16#583# => x"8d",
16#584# => x"fb",
16#585# => x"ff",
16#586# => x"b9",
16#587# => x"6d",
16#588# => x"fe",
16#589# => x"85",
16#58a# => x"f4",
16#58b# => x"b9",
16#58c# => x"75",
16#58d# => x"fe",
16#58e# => x"85",
16#58f# => x"f5",
16#590# => x"2c",
16#591# => x"fe",
16#592# => x"fe",
16#593# => x"10",
16#594# => x"fb",
16#595# => x"ad",
16#596# => x"ff",
16#597# => x"fe",
16#598# => x"c0",
16#599# => x"05",
16#59a# => x"f0",
16#59b# => x"58",
16#59c# => x"98",
16#59d# => x"48",
16#59e# => x"a0",
16#59f# => x"01",
16#5a0# => x"2c",
16#5a1# => x"fe",
16#5a2# => x"fe",
16#5a3# => x"10",
16#5a4# => x"fb",
16#5a5# => x"ad",
16#5a6# => x"ff",
16#5a7# => x"fe",
16#5a8# => x"2c",
16#5a9# => x"fe",
16#5aa# => x"fe",
16#5ab# => x"10",
16#5ac# => x"fb",
16#5ad# => x"ad",
16#5ae# => x"ff",
16#5af# => x"fe",
16#5b0# => x"2c",
16#5b1# => x"fe",
16#5b2# => x"fe",
16#5b3# => x"10",
16#5b4# => x"fb",
16#5b5# => x"ad",
16#5b6# => x"ff",
16#5b7# => x"fe",
16#5b8# => x"91",
16#5b9# => x"f4",
16#5ba# => x"88",
16#5bb# => x"2c",
16#5bc# => x"fe",
16#5bd# => x"fe",
16#5be# => x"10",
16#5bf# => x"fb",
16#5c0# => x"ad",
16#5c1# => x"ff",
16#5c2# => x"fe",
16#5c3# => x"91",
16#5c4# => x"f4",
16#5c5# => x"2c",
16#5c6# => x"fd",
16#5c7# => x"fe",
16#5c8# => x"2c",
16#5c9# => x"fd",
16#5ca# => x"fe",
16#5cb# => x"2c",
16#5cc# => x"fe",
16#5cd# => x"fe",
16#5ce# => x"10",
16#5cf# => x"fb",
16#5d0# => x"ad",
16#5d1# => x"ff",
16#5d2# => x"fe",
16#5d3# => x"68",
16#5d4# => x"c9",
16#5d5# => x"06",
16#5d6# => x"90",
16#5d7# => x"1c",
16#5d8# => x"d0",
16#5d9# => x"1f",
16#5da# => x"a0",
16#5db# => x"00",
16#5dc# => x"ad",
16#5dd# => x"fc",
16#5de# => x"fe",
16#5df# => x"29",
16#5e0# => x"80",
16#5e1# => x"10",
16#5e2# => x"f9",
16#5e3# => x"b9",
16#5e4# => x"ff",
16#5e5# => x"ff",
16#5e6# => x"8d",
16#5e7# => x"fd",
16#5e8# => x"fe",
16#5e9# => x"c8",
16#5ea# => x"d0",
16#5eb# => x"f0",
16#5ec# => x"2c",
16#5ed# => x"fc",
16#5ee# => x"fe",
16#5ef# => x"10",
16#5f0# => x"fb",
16#5f1# => x"8d",
16#5f2# => x"fd",
16#5f3# => x"fe",
16#5f4# => x"68",
16#5f5# => x"a8",
16#5f6# => x"a5",
16#5f7# => x"fc",
16#5f8# => x"40",
16#5f9# => x"a0",
16#5fa# => x"00",
16#5fb# => x"ad",
16#5fc# => x"fc",
16#5fd# => x"fe",
16#5fe# => x"29",
16#5ff# => x"80",
16#600# => x"10",
16#601# => x"f9",
16#602# => x"ad",
16#603# => x"fd",
16#604# => x"fe",
16#605# => x"99",
16#606# => x"ff",
16#607# => x"ff",
16#608# => x"c8",
16#609# => x"d0",
16#60a# => x"f0",
16#60b# => x"f0",
16#60c# => x"e7",
16#60d# => x"48",
16#60e# => x"ad",
16#60f# => x"ff",
16#610# => x"ff",
16#611# => x"8d",
16#612# => x"fd",
16#613# => x"fe",
16#614# => x"ee",
16#615# => x"0f",
16#616# => x"fe",
16#617# => x"d0",
16#618# => x"03",
16#619# => x"ee",
16#61a# => x"10",
16#61b# => x"fe",
16#61c# => x"68",
16#61d# => x"40",
16#61e# => x"48",
16#61f# => x"ad",
16#620# => x"fd",
16#621# => x"fe",
16#622# => x"8d",
16#623# => x"ff",
16#624# => x"ff",
16#625# => x"ee",
16#626# => x"23",
16#627# => x"fe",
16#628# => x"d0",
16#629# => x"03",
16#62a# => x"ee",
16#62b# => x"24",
16#62c# => x"fe",
16#62d# => x"68",
16#62e# => x"40",
16#62f# => x"48",
16#630# => x"98",
16#631# => x"48",
16#632# => x"a0",
16#633# => x"00",
16#634# => x"b1",
16#635# => x"f6",
16#636# => x"8d",
16#637# => x"fd",
16#638# => x"fe",
16#639# => x"e6",
16#63a# => x"f6",
16#63b# => x"d0",
16#63c# => x"02",
16#63d# => x"e6",
16#63e# => x"f7",
16#63f# => x"b1",
16#640# => x"f6",
16#641# => x"8d",
16#642# => x"fd",
16#643# => x"fe",
16#644# => x"e6",
16#645# => x"f6",
16#646# => x"d0",
16#647# => x"02",
16#648# => x"e6",
16#649# => x"f7",
16#64a# => x"68",
16#64b# => x"a8",
16#64c# => x"68",
16#64d# => x"40",
16#64e# => x"48",
16#64f# => x"98",
16#650# => x"48",
16#651# => x"a0",
16#652# => x"00",
16#653# => x"ad",
16#654# => x"fd",
16#655# => x"fe",
16#656# => x"91",
16#657# => x"f6",
16#658# => x"e6",
16#659# => x"f6",
16#65a# => x"d0",
16#65b# => x"02",
16#65c# => x"e6",
16#65d# => x"f7",
16#65e# => x"ad",
16#65f# => x"fd",
16#660# => x"fe",
16#661# => x"91",
16#662# => x"f6",
16#663# => x"e6",
16#664# => x"f6",
16#665# => x"d0",
16#666# => x"02",
16#667# => x"e6",
16#668# => x"f7",
16#669# => x"68",
16#66a# => x"a8",
16#66b# => x"68",
16#66c# => x"40",
16#66d# => x"0f",
16#66e# => x"23",
16#66f# => x"f6",
16#670# => x"f6",
16#671# => x"f6",
16#672# => x"f6",
16#673# => x"e4",
16#674# => x"06",
16#675# => x"fe",
16#676# => x"fe",
16#677# => x"00",
16#678# => x"00",
16#679# => x"00",
16#67a# => x"00",
16#67b# => x"fd",
16#67c# => x"fe",
16#67d# => x"0d",
16#67e# => x"1e",
16#67f# => x"2f",
16#680# => x"4e",
16#681# => x"c0",
16#682# => x"c0",
16#683# => x"c0",
16#684# => x"c0",
16#685# => x"fe",
16#686# => x"fe",
16#687# => x"fe",
16#688# => x"fe",
16#689# => x"fe",
16#68a# => x"fe",
16#68b# => x"fe",
16#68c# => x"fe",
16#68d# => x"2c",
16#68e# => x"f8",
16#68f# => x"fe",
16#690# => x"30",
16#691# => x"0f",
16#692# => x"2c",
16#693# => x"fe",
16#694# => x"fe",
16#695# => x"10",
16#696# => x"f6",
16#697# => x"a5",
16#698# => x"fc",
16#699# => x"08",
16#69a# => x"58",
16#69b# => x"28",
16#69c# => x"85",
16#69d# => x"fc",
16#69e# => x"4c",
16#69f# => x"8d",
16#6a0# => x"fe",
16#6a1# => x"ad",
16#6a2# => x"f9",
16#6a3# => x"fe",
16#6a4# => x"60",
16#6a5# => x"68",
16#6a6# => x"85",
16#6a7# => x"fa",
16#6a8# => x"68",
16#6a9# => x"85",
16#6aa# => x"fb",
16#6ab# => x"a0",
16#6ac# => x"00",
16#6ad# => x"e6",
16#6ae# => x"fa",
16#6af# => x"d0",
16#6b0# => x"02",
16#6b1# => x"e6",
16#6b2# => x"fb",
16#6b3# => x"b1",
16#6b4# => x"fa",
16#6b5# => x"30",
16#6b6# => x"06",
16#6b7# => x"20",
16#6b8# => x"ee",
16#6b9# => x"ff",
16#6ba# => x"4c",
16#6bb# => x"ad",
16#6bc# => x"fe",
16#6bd# => x"6c",
16#6be# => x"fa",
16#6bf# => x"00",
16#6c0# => x"8d",
16#6c1# => x"fd",
16#6c2# => x"fe",
16#6c3# => x"40",
16#6c4# => x"ff",
16#6c5# => x"ff",
16#6c6# => x"ff",
16#6c7# => x"ff",
16#6c8# => x"ff",
16#6c9# => x"ff",
16#6ca# => x"ff",
16#6cb# => x"ff",
16#6cc# => x"ff",
16#6cd# => x"ff",
16#6ce# => x"ff",
16#6cf# => x"ff",
16#6d0# => x"ff",
16#6d1# => x"ff",
16#6d2# => x"ff",
16#6d3# => x"ff",
16#6d4# => x"ff",
16#6d5# => x"ff",
16#6d6# => x"ff",
16#6d7# => x"ff",
16#6d8# => x"ff",
16#6d9# => x"ff",
16#6da# => x"ff",
16#6db# => x"ff",
16#6dc# => x"ff",
16#6dd# => x"ff",
16#6de# => x"ff",
16#6df# => x"ff",
16#6e0# => x"ff",
16#6e1# => x"ff",
16#6e2# => x"ff",
16#6e3# => x"ff",
16#6e4# => x"ff",
16#6e5# => x"ff",
16#6e6# => x"ff",
16#6e7# => x"ff",
16#6e8# => x"ff",
16#6e9# => x"ff",
16#6ea# => x"ff",
16#6eb# => x"ff",
16#6ec# => x"ff",
16#6ed# => x"ff",
16#6ee# => x"ff",
16#6ef# => x"ff",
16#6f0# => x"00",
16#6f1# => x"00",
16#6f2# => x"00",
16#6f3# => x"00",
16#6f4# => x"00",
16#6f5# => x"00",
16#6f6# => x"00",
16#6f7# => x"00",
16#6f8# => x"00",
16#6f9# => x"00",
16#6fa# => x"00",
16#6fb# => x"00",
16#6fc# => x"00",
16#6fd# => x"00",
16#6fe# => x"00",
16#6ff# => x"00",
16#700# => x"ff",
16#701# => x"ff",
16#702# => x"ff",
16#703# => x"ff",
16#704# => x"ff",
16#705# => x"ff",
16#706# => x"ff",
16#707# => x"ff",
16#708# => x"ff",
16#709# => x"ff",
16#70a# => x"ff",
16#70b# => x"ff",
16#70c# => x"ff",
16#70d# => x"ff",
16#70e# => x"ff",
16#70f# => x"ff",
16#710# => x"ff",
16#711# => x"ff",
16#712# => x"ff",
16#713# => x"ff",
16#714# => x"ff",
16#715# => x"ff",
16#716# => x"ff",
16#717# => x"ff",
16#718# => x"ff",
16#719# => x"ff",
16#71a# => x"ff",
16#71b# => x"ff",
16#71c# => x"ff",
16#71d# => x"ff",
16#71e# => x"ff",
16#71f# => x"ff",
16#720# => x"ff",
16#721# => x"ff",
16#722# => x"ff",
16#723# => x"ff",
16#724# => x"ff",
16#725# => x"ff",
16#726# => x"ff",
16#727# => x"ff",
16#728# => x"ff",
16#729# => x"ff",
16#72a# => x"ff",
16#72b# => x"ff",
16#72c# => x"ff",
16#72d# => x"ff",
16#72e# => x"ff",
16#72f# => x"ff",
16#730# => x"ff",
16#731# => x"ff",
16#732# => x"ff",
16#733# => x"ff",
16#734# => x"ff",
16#735# => x"ff",
16#736# => x"ff",
16#737# => x"ff",
16#738# => x"ff",
16#739# => x"ff",
16#73a# => x"ff",
16#73b# => x"ff",
16#73c# => x"ff",
16#73d# => x"ff",
16#73e# => x"ff",
16#73f# => x"ff",
16#740# => x"ff",
16#741# => x"ff",
16#742# => x"ff",
16#743# => x"ff",
16#744# => x"ff",
16#745# => x"ff",
16#746# => x"ff",
16#747# => x"ff",
16#748# => x"ff",
16#749# => x"ff",
16#74a# => x"ff",
16#74b# => x"ff",
16#74c# => x"ff",
16#74d# => x"ff",
16#74e# => x"ff",
16#74f# => x"ff",
16#750# => x"ff",
16#751# => x"ff",
16#752# => x"ff",
16#753# => x"ff",
16#754# => x"ff",
16#755# => x"ff",
16#756# => x"ff",
16#757# => x"ff",
16#758# => x"ff",
16#759# => x"ff",
16#75a# => x"ff",
16#75b# => x"ff",
16#75c# => x"ff",
16#75d# => x"ff",
16#75e# => x"ff",
16#75f# => x"ff",
16#760# => x"ff",
16#761# => x"ff",
16#762# => x"ff",
16#763# => x"ff",
16#764# => x"ff",
16#765# => x"ff",
16#766# => x"ff",
16#767# => x"ff",
16#768# => x"ff",
16#769# => x"ff",
16#76a# => x"ff",
16#76b# => x"ff",
16#76c# => x"ff",
16#76d# => x"ff",
16#76e# => x"ff",
16#76f# => x"ff",
16#770# => x"ff",
16#771# => x"ff",
16#772# => x"ff",
16#773# => x"ff",
16#774# => x"ff",
16#775# => x"ff",
16#776# => x"ff",
16#777# => x"ff",
16#778# => x"ff",
16#779# => x"ff",
16#77a# => x"ff",
16#77b# => x"ff",
16#77c# => x"ff",
16#77d# => x"ff",
16#77e# => x"ff",
16#77f# => x"ff",
16#780# => x"c4",
16#781# => x"fc",
16#782# => x"50",
16#783# => x"f9",
16#784# => x"fd",
16#785# => x"fc",
16#786# => x"c4",
16#787# => x"fc",
16#788# => x"d5",
16#789# => x"f9",
16#78a# => x"80",
16#78b# => x"fa",
16#78c# => x"0c",
16#78d# => x"fb",
16#78e# => x"6d",
16#78f# => x"f9",
16#790# => x"77",
16#791# => x"f9",
16#792# => x"60",
16#793# => x"fc",
16#794# => x"d9",
16#795# => x"fb",
16#796# => x"37",
16#797# => x"fc",
16#798# => x"43",
16#799# => x"fc",
16#79a# => x"9b",
16#79b# => x"fc",
16#79c# => x"19",
16#79d# => x"fc",
16#79e# => x"c4",
16#79f# => x"fc",
16#7a0# => x"88",
16#7a1# => x"f9",
16#7a2# => x"c4",
16#7a3# => x"fc",
16#7a4# => x"c4",
16#7a5# => x"fc",
16#7a6# => x"c4",
16#7a7# => x"fc",
16#7a8# => x"c4",
16#7a9# => x"fc",
16#7aa# => x"c4",
16#7ab# => x"fc",
16#7ac# => x"c4",
16#7ad# => x"fc",
16#7ae# => x"c4",
16#7af# => x"fc",
16#7b0# => x"88",
16#7b1# => x"f9",
16#7b2# => x"88",
16#7b3# => x"f9",
16#7b4# => x"88",
16#7b5# => x"f9",
16#7b6# => x"36",
16#7b7# => x"80",
16#7b8# => x"ff",
16#7b9# => x"4c",
16#7ba# => x"c4",
16#7bb# => x"fc",
16#7bc# => x"4c",
16#7bd# => x"c4",
16#7be# => x"fc",
16#7bf# => x"4c",
16#7c0# => x"c4",
16#7c1# => x"fc",
16#7c2# => x"4c",
16#7c3# => x"c4",
16#7c4# => x"fc",
16#7c5# => x"4c",
16#7c6# => x"c4",
16#7c7# => x"fc",
16#7c8# => x"4c",
16#7c9# => x"77",
16#7ca# => x"f9",
16#7cb# => x"4c",
16#7cc# => x"6d",
16#7cd# => x"f9",
16#7ce# => x"6c",
16#7cf# => x"1c",
16#7d0# => x"02",
16#7d1# => x"6c",
16#7d2# => x"1a",
16#7d3# => x"02",
16#7d4# => x"6c",
16#7d5# => x"18",
16#7d6# => x"02",
16#7d7# => x"6c",
16#7d8# => x"16",
16#7d9# => x"02",
16#7da# => x"6c",
16#7db# => x"14",
16#7dc# => x"02",
16#7dd# => x"6c",
16#7de# => x"12",
16#7df# => x"02",
16#7e0# => x"6c",
16#7e1# => x"10",
16#7e2# => x"02",
16#7e3# => x"c9",
16#7e4# => x"0d",
16#7e5# => x"d0",
16#7e6# => x"07",
16#7e7# => x"a9",
16#7e8# => x"0a",
16#7e9# => x"20",
16#7ea# => x"ee",
16#7eb# => x"ff",
16#7ec# => x"a9",
16#7ed# => x"0d",
16#7ee# => x"6c",
16#7ef# => x"0e",
16#7f0# => x"02",
16#7f1# => x"6c",
16#7f2# => x"0c",
16#7f3# => x"02",
16#7f4# => x"6c",
16#7f5# => x"0a",
16#7f6# => x"02",
16#7f7# => x"6c",
16#7f8# => x"08",
16#7f9# => x"02",
16#7fa# => x"0d",
16#7fb# => x"fe",
16#7fc# => x"00",
16#7fd# => x"f8",
16#7fe# => x"f2",
16#7ff# => x"fc"
);
attribute ram_style : string;
attribute ram_style of RAM : signal is "distributed";
begin
process (CLK)
begin
if rising_edge(CLK) then
DATA <= RAM(conv_integer(ADDR));
end if;
end process;
end RTL;
| gpl-3.0 | 3f087f29140fe9c9bd46ca7c1e674960 | 0.311234 | 2.334501 | false | false | false | false |
hoglet67/CoPro6502 | src/LX9Co_CoPro6809.vhd | 1 | 8,378 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity LX9CoPro6809 is
port (
-- GOP Signals
fastclk : in std_logic;
test : inout std_logic_vector(8 downto 1);
sw : in std_logic_vector(3 downto 0);
-- Tube signals (use 16 out of 22 DIL pins)
h_phi2 : in std_logic; -- 1,2,12,21,23 are global clocks
h_addr : in std_logic_vector(2 downto 0);
h_data : inout std_logic_vector(7 downto 0);
h_rdnw : in std_logic;
h_cs_b : in std_logic;
h_rst_b : in std_logic;
h_irq_b : inout std_logic;
-- Ram Signals
ram_ub_b : out std_logic;
ram_lb_b : out std_logic;
ram_cs : out std_logic;
ram_oe : out std_logic;
ram_wr : out std_logic;
ram_addr : out std_logic_vector (18 downto 0);
ram_data : inout std_logic_vector (7 downto 0)
);
end LX9CoPro6809;
architecture BEHAVIORAL of LX9CoPro6809 is
-------------------------------------------------
-- clock and reset signals
-------------------------------------------------
signal cpu_clk : std_logic;
signal cpu_clken : std_logic;
signal clken_counter : std_logic_vector (1 downto 0);
signal bootmode : std_logic;
signal RSTn : std_logic;
signal RSTn_sync : std_logic;
signal bs : std_logic;
signal ba : std_logic;
signal vma : std_logic;
signal ifetch : std_logic;
signal opfetch : std_logic;
-------------------------------------------------
-- parasite signals
-------------------------------------------------
signal p_cs_b : std_logic;
signal tube_cs_b : std_logic;
signal p_data_out : std_logic_vector (7 downto 0);
-------------------------------------------------
-- ram/rom signals
-------------------------------------------------
signal ram_cs_b : std_logic;
signal ram_oe_int : std_logic;
signal ram_wr_int : std_logic;
signal rom_cs_b : std_logic;
signal rom_data_out : std_logic_vector (7 downto 0);
-------------------------------------------------
-- cpu signals
-------------------------------------------------
signal cpu_R_W_n : std_logic;
signal cpu_addr_int : std_logic_vector (15 downto 0);
signal cpu_addr : std_logic_vector (15 downto 0);
signal cpu_din : std_logic_vector (7 downto 0);
signal cpu_dout : std_logic_vector (7 downto 0);
signal cpu_IRQ_n : std_logic;
signal cpu_NMI_n : std_logic;
signal cpu_IRQ_sync : std_logic;
signal cpu_NMI_sync : std_logic;
begin
---------------------------------------------------------------------
-- instantiated components
---------------------------------------------------------------------
inst_ICAP_config : entity work.ICAP_config port map (
fastclk => fastclk,
sw_in => sw,
sw_out => open,
h_addr => h_addr,
h_cs_b => h_cs_b,
h_data => h_data,
h_phi2 => h_phi2,
h_rdnw => h_rdnw,
h_rst_b => h_rst_b
);
inst_dcm_32_16 : entity work.dcm_32_16 port map (
CLKIN_IN => fastclk,
CLK0_OUT => cpu_clk,
CLK0_OUT1 => open,
CLK2X_OUT => open);
inst_tuberom : entity work.tuberom_6809 port map (
CLK => cpu_clk,
ADDR => cpu_addr(10 downto 0),
DATA => rom_data_out
);
Inst_cpu09: entity work.cpu09 PORT MAP(
clk => cpu_clk, -- E clock input (rising edge)
rst => not RSTn_sync, -- reset input (active high)
vma => vma, -- valid memory address (active high)
lic_out => open, -- last instruction cycle (active high)
ifetch => ifetch, -- instruction fetch cycle (active high)
opfetch => opfetch, -- opcode fetch (active high)
ba => ba, -- bus available (high on sync wait or DMA grant)
bs => bs, -- bus status (high on interrupt or reset vector fetch or DMA grant)
addr => cpu_addr_int, -- address bus output
rw => cpu_R_W_n, -- read not write output
data_out => cpu_dout, -- data bus output
data_in => cpu_din, -- data bus input
irq => cpu_NMI_sync, -- interrupt request input (active high)
firq => cpu_IRQ_sync, -- fast interrupt request input (active high)
nmi => '0', -- non maskable interrupt request input (active high)
halt => '0', -- halt input (active high) grants DMA
hold => not cpu_clken -- hold input (active high) extend bus cycle, basically an inverted clock enable
);
-- Remap the hardware vectors from 0xFFFx to 0xFEFx
cpu_addr <= cpu_addr_int when bs = '0'
else cpu_addr_int(15 downto 9) & '0' & cpu_addr_int(7 downto 0);
inst_tube: entity work.tube port map (
h_addr => h_addr,
h_cs_b => h_cs_b,
h_data => h_data,
h_phi2 => h_phi2,
h_rdnw => h_rdnw,
h_rst_b => h_rst_b,
h_irq_b => h_irq_b,
p_addr => cpu_addr(2 downto 0),
p_cs_b => tube_cs_b,
p_data_in => cpu_dout,
p_data_out => p_data_out,
p_rdnw => cpu_R_W_n,
p_phi2 => cpu_clk,
p_rst_b => RSTn,
p_nmi_b => cpu_NMI_n,
p_irq_b => cpu_IRQ_n
);
tube_cs_b <= not ((not p_cs_b) and cpu_clken);
p_cs_b <= '0' when vma = '1' and cpu_addr(15 downto 4) = "111111101110" else '1';
rom_cs_b <= '0' when vma = '1' and cpu_addr(15 downto 11) = "11111" and cpu_R_W_n = '1' and bootmode = '1' else '1';
ram_cs_b <= '0' when vma = '1' and p_cs_b = '1' and rom_cs_b = '1' else '1';
cpu_din <=
p_data_out when p_cs_b = '0' else
rom_data_out when rom_cs_b = '0' else
ram_data when ram_cs_b = '0' else
x"f1";
ram_ub_b <= '0';
ram_lb_b <= '0';
ram_cs <= ram_cs_b;
ram_oe_int <= not ((not ram_cs_b) and cpu_R_W_n);
ram_oe <= ram_oe_int;
ram_wr_int <= not ((not ram_cs_b) and (not cpu_R_W_n) and cpu_clken);
ram_wr <= ram_wr_int;
ram_addr <= "000" & cpu_addr(15 downto 0);
ram_data <= cpu_dout when cpu_R_W_n = '0' else "ZZZZZZZZ";
--------------------------------------------------------
-- test signals
--------------------------------------------------------
-- default to hi-impedence, to avoid conflicts with
-- a Raspberry Pi connected to the test connector
test <= (others => 'Z');
--------------------------------------------------------
-- boot mode generator
--------------------------------------------------------
boot_gen : process(cpu_clk, RSTn_sync)
begin
if RSTn_sync = '0' then
bootmode <= '1';
elsif rising_edge(cpu_clk) then
if p_cs_b = '0' then
bootmode <= '0';
end if;
end if;
end process;
--------------------------------------------------------
-- synchronize interrupts etc into 6809 core
--------------------------------------------------------
sync_gen : process(cpu_clk, RSTn_sync)
begin
if RSTn_sync = '0' then
cpu_NMI_sync <= '0';
cpu_IRQ_sync <= '0';
elsif rising_edge(cpu_clk) then
cpu_NMI_sync <= not cpu_NMI_n;
cpu_IRQ_sync <= not cpu_IRQ_n;
end if;
end process;
--------------------------------------------------------
-- clock enable generator
--------------------------------------------------------
-- TODO If the clock speed is increased from 4MHz to 8MHz
-- e.g. with cpu_clken <= not cpu_clken
-- then *SAVE skips every other byte
clk_gen : process(cpu_clk)
begin
if rising_edge(cpu_clk) then
clken_counter <= clken_counter + 1;
cpu_clken <= clken_counter(0) and clken_counter(1);
RSTn_sync <= RSTn;
end if;
end process;
end BEHAVIORAL;
| gpl-3.0 | cdf5ce3a55bd6da57cf91eb772e725e9 | 0.454882 | 3.644193 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-xilinx-kc705/leon3mp.vhd | 1 | 40,507 | -----------------------------------------------------------------------------
-- LEON3/LEON4 Xilinx KC705 Demonstration design
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.leon4.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.i2c.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.l2cache.all;
use gaisler.subsys.all;
-- pragma translate_off
use gaisler.sim.all;
library unisim;
use unisim.all;
-- pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
SIM_BYPASS_INIT_CAL : string := "OFF";
SIMULATION : string := "FALSE";
USE_MIG_INTERFACE_MODEL : boolean := false
);
port (
reset : in std_ulogic;
clk200p : in std_ulogic; -- 200 MHz clock
clk200n : in std_ulogic; -- 200 MHz clock
address : out std_logic_vector(25 downto 0);
data : inout std_logic_vector(15 downto 0);
oen : out std_ulogic;
writen : out std_ulogic;
romsn : out std_logic;
adv : out std_logic;
ddr3_dq : inout std_logic_vector(63 downto 0);
ddr3_dqs_p : inout std_logic_vector(7 downto 0);
ddr3_dqs_n : inout std_logic_vector(7 downto 0);
ddr3_addr : out std_logic_vector(13 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(7 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0);
dsurx : in std_ulogic;
dsutx : out std_ulogic;
dsuctsn : in std_ulogic;
dsurtsn : out std_ulogic;
button : in std_logic_vector(3 downto 0);
switch : inout std_logic_vector(3 downto 0);
led : out std_logic_vector(6 downto 0);
iic_scl : inout std_ulogic;
iic_sda : inout std_ulogic;
gtrefclk_p : in std_logic;
gtrefclk_n : in std_logic;
phy_gtxclk : out std_logic;
phy_txd : out std_logic_vector(3 downto 0);
phy_txctl_txen : out std_ulogic;
phy_rxd : in std_logic_vector(3 downto 0);
phy_rxctl_rxdv : in std_ulogic;
phy_rxclk : in std_ulogic;
phy_reset : out std_ulogic;
phy_mdio : inout std_logic;
phy_mdc : out std_ulogic;
phy_int : in std_ulogic
);
end;
architecture rtl of leon3mp is
component ahb2mig_7series
generic(
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
SIM_BYPASS_INIT_CAL : string := "OFF";
SIMULATION : string := "FALSE";
USE_MIG_INTERFACE_MODEL : boolean := false
);
port(
ddr3_dq : inout std_logic_vector(63 downto 0);
ddr3_dqs_p : inout std_logic_vector(7 downto 0);
ddr3_dqs_n : inout std_logic_vector(7 downto 0);
ddr3_addr : out std_logic_vector(13 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(7 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0);
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
calib_done : out std_logic;
rst_n_syn : in std_logic;
rst_n_async : in std_logic;
clk_amba : in std_logic;
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
clk_ref_i : in std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic
);
end component ;
component ddr_dummy
port (
ddr_dq : inout std_logic_vector(63 downto 0);
ddr_dqs : inout std_logic_vector(7 downto 0);
ddr_dqs_n : inout std_logic_vector(7 downto 0);
ddr_addr : out std_logic_vector(13 downto 0);
ddr_ba : out std_logic_vector(2 downto 0);
ddr_ras_n : out std_logic;
ddr_cas_n : out std_logic;
ddr_we_n : out std_logic;
ddr_reset_n : out std_logic;
ddr_ck_p : out std_logic_vector(0 downto 0);
ddr_ck_n : out std_logic_vector(0 downto 0);
ddr_cke : out std_logic_vector(0 downto 0);
ddr_cs_n : out std_logic_vector(0 downto 0);
ddr_dm : out std_logic_vector(7 downto 0);
ddr_odt : out std_logic_vector(0 downto 0)
);
end component ;
component IBUFDS_GTE2
port (
O : out std_ulogic;
ODIV2 : out std_ulogic;
CEB : in std_ulogic;
I : in std_ulogic;
IB : in std_ulogic
);
end component;
component IDELAYCTRL
port (
RDY : out std_ulogic;
REFCLK : in std_ulogic;
RST : in std_ulogic
);
end component;
component IODELAYE1
generic (
DELAY_SRC : string := "I";
IDELAY_TYPE : string := "DEFAULT";
IDELAY_VALUE : integer := 0
);
port (
CNTVALUEOUT : out std_logic_vector(4 downto 0);
DATAOUT : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
CINVCTRL : in std_ulogic;
CLKIN : in std_ulogic;
CNTVALUEIN : in std_logic_vector(4 downto 0);
DATAIN : in std_ulogic;
IDATAIN : in std_ulogic;
INC : in std_ulogic;
ODATAIN : in std_ulogic;
RST : in std_ulogic;
T : in std_ulogic
);
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
----- component STARTUPE2 -----
component STARTUPE2
generic (
PROG_USR : string := "FALSE";
SIM_CCLK_FREQ : real := 0.0
);
port (
CFGCLK : out std_ulogic;
CFGMCLK : out std_ulogic;
EOS : out std_ulogic;
PREQ : out std_ulogic;
CLK : in std_ulogic;
GSR : in std_ulogic;
GTS : in std_ulogic;
KEYCLEARB : in std_ulogic;
PACK : in std_ulogic;
USRCCLKO : in std_ulogic;
USRCCLKTS : in std_ulogic;
USRDONEO : in std_ulogic;
USRDONETS : in std_ulogic
);
end component;
constant maxahbm : integer := 16;
constant maxahbs : integer := 16;
constant maxapbs : integer := CFG_IRQ3_ENABLE+CFG_GPT_ENABLE+CFG_GRGPIO_ENABLE+CFG_AHBSTAT+CFG_AHBSTAT;
signal vcc, gnd : std_logic;
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal mig_ahbsi : ahb_slv_in_type;
signal mig_ahbso : ahb_slv_out_type;
signal sysi : leon_dsu_stat_base_in_type;
signal syso : leon_dsu_stat_base_out_type;
signal perf : l3stat_in_type;
signal ui_clk : std_ulogic;
signal clkm : std_ulogic := '0';
signal rstn, rstraw, sdclkl : std_ulogic;
signal clk_200 : std_ulogic;
signal clk25, clk40, clk65 : std_ulogic;
signal cgi, cgi2 : clkgen_in_type;
signal cgo, cgo2 : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal gmiii : eth_in_type;
signal gmiio : eth_out_type;
signal rgmiii,rgmiii_buf : eth_in_type;
signal rgmiio : eth_out_type;
signal ethernet_phy_int : std_logic;
signal rxd1 : std_logic;
signal txd1 : std_logic;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal gtx_clk,gtx_clk_nobuf,gtx_clk90 : std_ulogic;
signal rstgtxn : std_logic;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal clklock, elock, ulock : std_ulogic;
signal lock, calib_done, clkml, lclk, rst, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal i2ci, dvi_i2ci : i2c_in_type;
signal i2co, dvi_i2co : i2c_out_type;
constant BOARD_FREQ : integer := 200000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
signal stati : ahbstat_in_type;
signal dsurx_int : std_logic;
signal dsutx_int : std_logic;
signal dsuctsn_int : std_logic;
signal dsurtsn_int : std_logic;
signal dsu_sel : std_logic;
signal idelay_reset_cnt : std_logic_vector(3 downto 0);
signal idelayctrl_reset : std_logic;
signal io_ref : std_logic;
signal clkref : std_logic;
signal migrstn : std_logic;
signal spmi : spimctrl_in_type;
signal spmo : spimctrl_out_type;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1'; gnd <= '0';
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
clk_gen0 : if (CFG_MIG_7SERIES = 0) generate
clk_pad_ds : clkpad_ds generic map (tech => padtech, level => sstl, voltage => x15v)
port map (clk200p, clk200n, lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,CFG_CLK_NOFB, 0, 0, 0, BOARD_FREQ)
port map (lclk, lclk, clkm, open, open, open, open, cgi, cgo, open, open, open);
end generate;
reset_pad : inpad generic map (tech => padtech, level => cmos, voltage => x15v)
port map (reset, rst);
rst0 : rstgen -- reset generator
generic map (acthigh => 1, syncin => 1)
port map (rst, clkm, lock, rstn, rstraw);
lock <= calib_done when CFG_MIG_7SERIES = 1 else cgo.clklock;
rst1 : rstgen -- reset generator
generic map (acthigh => 1)
port map (rst, clkm, '1', migrstn, open);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, fpnpen => CFG_FPNPEN,
nahbm => maxahbm, nahbs => maxahbs, devid => XILINX_KC705)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON processor, DSU and performance counters --------------------
----------------------------------------------------------------------
leon : leon_dsu_stat_base
generic map (
leon => CFG_LEON, ncpu => CFG_NCPU, fabtech => fabtech, memtech => memtech,
nwindows => CFG_NWIN, dsu => CFG_DSU, fpu => CFG_FPU, v8 => CFG_V8, cp => 0,
mac => CFG_MAC, pclow => pclow, notag => 0, nwp => CFG_NWP, icen => CFG_ICEN,
irepl => CFG_IREPL, isets => CFG_ISETS, ilinesize => CFG_ILINE,
isetsize => CFG_ISETSZ, isetlock => CFG_ILOCK, dcen => CFG_DCEN,
drepl => CFG_DREPL, dsets => CFG_DSETS, dlinesize => CFG_DLINE,
dsetsize => CFG_DSETSZ, dsetlock => CFG_DLOCK, dsnoop => CFG_DSNOOP,
ilram => CFG_ILRAMEN, ilramsize => CFG_ILRAMSZ, ilramstart => CFG_ILRAMADDR,
dlram => CFG_DLRAMEN, dlramsize => CFG_DLRAMSZ, dlramstart => CFG_DLRAMADDR,
mmuen => CFG_MMUEN, itlbnum => CFG_ITLBNUM, dtlbnum => CFG_DTLBNUM,
tlb_type => CFG_TLB_TYPE, tlb_rep => CFG_TLB_REP, lddel => CFG_LDDEL,
disas => disas, tbuf => CFG_ITBSZ, pwd => CFG_PWD, svt => CFG_SVT,
rstaddr => CFG_RSTADDR, smp => CFG_NCPU-1, cached => CFG_DFIXED,
wbmask => CFG_BWMASK, busw => CFG_CACHEBW, netlist => CFG_LEON_NETLIST,
ft => CFG_LEONFT_EN, npasi => CFG_NP_ASI, pwrpsr => CFG_WRPSR,
rex => CFG_REX, altwin => CFG_ALTWIN, grfpush => CFG_GRFPUSH,
dsu_hindex => 2, dsu_haddr => 16#D00#, dsu_hmask => 16#F00#, atbsz => CFG_ATBSZ,
stat => CFG_STAT_ENABLE, stat_pindex => 13, stat_paddr => 16#100#,
stat_pmask => 16#ffc#, stat_ncnt => CFG_STAT_CNT, stat_nmax => CFG_STAT_NMAX)
port map (
rstn => rstn, ahbclk => clkm, cpuclk => clkm, hclken => vcc,
leon_ahbmi => ahbmi, leon_ahbmo => ahbmo(CFG_NCPU-1 downto 0),
leon_ahbsi => ahbsi, leon_ahbso => ahbso,
irqi => irqi, irqo => irqo,
stat_apbi => apbi, stat_apbo => apbo(13), stat_ahbsi => ahbsi,
stati => perf,
dsu_ahbsi => ahbsi, dsu_ahbso => ahbso(2),
dsu_tahbmi => ahbmi, dsu_tahbsi => ahbsi,
sysi => sysi, syso => syso);
led1_pad : outpad generic map (tech => padtech, level => cmos, voltage => x15v)
port map (led(1), syso.proc_error);
sysi.dsu_enable <= '1';
dsui_break_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (button(0), sysi.dsu_break);
dsuact_pad : outpad generic map (tech => padtech, level => cmos, voltage => x15v)
port map (led(0), ndsuact);
ndsuact <= not syso.dsu_active;
-----------------------------------------------------------------------------
-- Debug UART
-----------------------------------------------------------------------------
-- And multiplexing with APBUART
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
dui.extclk <= '0';
end generate;
nouah : if CFG_AHB_UART = 0 generate
apbo(7) <= apb_none;
duo.txd <= '0';
duo.rtsn <= '0';
dui.extclk <= '0';
end generate;
sw4_pad : iopad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (switch(3), '0', '1', dsu_sel);
dsutx_int <= duo.txd when dsu_sel = '1' else u1o.txd;
dui.rxd <= dsurx_int when dsu_sel = '1' else '1';
u1i.rxd <= dsurx_int when dsu_sel = '0' else '1';
dsurtsn_int <= duo.rtsn when dsu_sel = '1' else u1o.rtsn;
dui.ctsn <= dsuctsn_int when dsu_sel = '1' else '1';
u1i.ctsn <= dsuctsn_int when dsu_sel = '0' else '1';
dsurx_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (dsurx, dsurx_int);
dsutx_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (dsutx, dsutx_int);
dsuctsn_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (dsuctsn, dsuctsn_int);
dsurtsn_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (dsurtsn, dsurtsn_int);
-----------------------------------------------------------------------------
-- JTAG debug link
-----------------------------------------------------------------------------
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+1)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+1),
open, open, open, open, open, open, open, gnd);
end generate;
nojtag : if CFG_AHB_JTAG = 0 generate ahbmo(CFG_NCPU+1) <= ahbm_none; end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
memi.brdyn <= '0'; memi.bexcn <= '1';
mctrl_gen : if CFG_MCTRL_LEON2 /= 0 and CFG_SPIMCTRL = 0 generate
mctrl0 : mctrl generic map (hindex => 0, pindex => 0,
paddr => 0, srbanks => 2, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN,
invclk => CFG_CLK_NOFB, sepbus => CFG_MCTRL_SEPBUS,
pageburst => CFG_MCTRL_PAGE, rammask => 0, iomask => 0)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, open);
addr_pad : outpadv generic map (width => 26, tech => padtech, level => cmos, voltage => x25v)
port map (address(25 downto 0), memo.address(26 downto 1));
roms_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (oen, memo.oen);
adv_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (adv, '0');
wri_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (writen, memo.writen);
data_pad : iopadvv generic map (tech => padtech, width => 16, level => cmos, voltage => x25v)
port map (data(15 downto 0), memo.data(31 downto 16),
memo.vbdrive(31 downto 16), memi.data(31 downto 16));
end generate;
----------------------------------------------------------------------
--- SPI Memory Controller--------------------------------------------
----------------------------------------------------------------------
spimc: if CFG_SPIMCTRL = 1 and CFG_MCTRL_LEON2 = 0 generate
spimctrl0 : spimctrl -- SPI Memory Controller
generic map (hindex => 0, hirq => 1, faddr => 16#100#, fmask => 16#ff8#,
ioaddr => 16#002#, iomask => 16#fff#,
spliten => CFG_SPLIT, oepol => 0,
sdcard => CFG_SPIMCTRL_SDCARD,
readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => CFG_SPIMCTRL_DUALOUTPUT,
scaler => CFG_SPIMCTRL_SCALER,
altscaler => CFG_SPIMCTRL_ASCALER,
pwrupcnt => CFG_SPIMCTRL_PWRUPCNT)
port map (rstn, clkm, ahbsi, ahbso(0), spmi, spmo);
miso_pad : inpad generic map (tech => padtech)
port map (data(1), spmi.miso);
mosi_pad : outpad generic map (tech => padtech)
port map (data(0), spmo.mosi);
slvsel0_pad : odpad generic map (tech => padtech)
port map (romsn, spmo.csn);
-- To output SPI clock use Xilinx STARTUPE2 primitive
STARTUPE2_inst : STARTUPE2
generic map (
PROG_USR => "FALSE",
SIM_CCLK_FREQ => 10.0
)
port map (
CFGCLK => open ,
CFGMCLK => open ,
EOS => open ,
PREQ => open ,
CLK => '0',
GSR => '0',
GTS => '0',
KEYCLEARB => '0',
PACK => '0',
USRCCLKO => spmo.sck,
USRCCLKTS => '0',
USRDONEO => '1',
USRDONETS => '1'
);
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
nomctrl : if CFG_MCTRL_LEON2 = 0 and CFG_SPIMCTRL = 0 generate
roms_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (romsn, vcc); --ahbso(0) <= ahbso_none;
end generate;
mctrl_error_gen : if CFG_MCTRL_LEON2 /= 0 and CFG_SPIMCTRL = 1 generate
x : process
begin
assert false
report "Xilins KC705 Ref design do not support Quad SPI Flash Memory and Linear BPI flash memory at the same time"
severity failure;
wait;
end process;
end generate;
-----------------------------------------------------------------------------
-- L2 cache, optionally covering DDR3 SDRAM memory controller
-----------------------------------------------------------------------------
l2cen : if CFG_L2_EN /= 0 generate
l2cblock : block
signal mem_ahbsi : ahb_slv_in_type;
signal mem_ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal mem_ahbmi : ahb_mst_in_type;
signal mem_ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal l2c_stato : std_logic_vector(10 downto 0);
begin
l2c0 : l2c generic map (
hslvidx => 4, hmstidx => 0, cen => CFG_L2_PEN,
haddr => 16#400#, hmask => 16#c00#, ioaddr => 16#FF0#,
cached => CFG_L2_MAP, repl => CFG_L2_RAN, ways => CFG_L2_WAYS,
linesize => CFG_L2_LSZ, waysize => CFG_L2_SIZE,
memtech => memtech, bbuswidth => AHBDW,
bioaddr => 16#FFE#, biomask => 16#fff#,
sbus => 0, mbus => 1, arch => CFG_L2_SHARE,
ft => CFG_L2_EDAC)
port map(rst => rstn, clk => clkm, ahbsi => ahbsi, ahbso => ahbso(4),
ahbmi => mem_ahbmi, ahbmo => mem_ahbmo(0), ahbsov => mem_ahbso,
sto => l2c_stato);
memahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => 16#FFE#,
ioen => 1, nahbm => 1, nahbs => 1)
port map (rstn, clkm, mem_ahbmi, mem_ahbmo, mem_ahbsi, mem_ahbso);
mem_ahbso(0) <= mig_ahbso;
mig_ahbsi <= mem_ahbsi;
perf.event(15 downto 7) <= (others => '0');
perf.esource(15 downto 7) <= (others => (others => '0'));
perf.event(6) <= l2c_stato(10); -- Data uncorrectable error
perf.event(5) <= l2c_stato(9); -- Data correctable error
perf.event(4) <= l2c_stato(8); -- Tag uncorrectable error
perf.event(3) <= l2c_stato(7); -- Tag correctable error
perf.event(2) <= l2c_stato(2); -- Bus access
perf.event(1) <= l2c_stato(1); -- Miss
perf.event(0) <= l2c_stato(0); -- Hit
perf.esource(6 downto 3) <= (others => (others => '0'));
perf.esource(2 downto 0) <= (others => l2c_stato(6 downto 3));
perf.req <= (others => '0');
perf.sel <= (others => '0');
perf.latcnt <= '0';
--perf.timer <= dbgi(0).timer(31 downto 0);
end block l2cblock;
end generate l2cen;
nol2c : if CFG_L2_EN = 0 generate
ahbso(4) <= mig_ahbso;
mig_ahbsi <= ahbsi;
perf <= l3stat_in_none;
end generate;
----------------------------------------------------------------------
--- DDR3 memory controller ------------------------------------------
----------------------------------------------------------------------
mig_gen : if (CFG_MIG_7SERIES = 1) generate
gen_mig : if (USE_MIG_INTERFACE_MODEL /= true) generate
ddrc : ahb2mig_7series generic map(
hindex => 4*(1-CFG_L2_EN), haddr => 16#400#, hmask => 16#C00#,
pindex => 4, paddr => 4,
SIM_BYPASS_INIT_CAL => SIM_BYPASS_INIT_CAL,
SIMULATION => SIMULATION, USE_MIG_INTERFACE_MODEL => USE_MIG_INTERFACE_MODEL)
port map(
ddr3_dq => ddr3_dq,
ddr3_dqs_p => ddr3_dqs_p,
ddr3_dqs_n => ddr3_dqs_n,
ddr3_addr => ddr3_addr,
ddr3_ba => ddr3_ba,
ddr3_ras_n => ddr3_ras_n,
ddr3_cas_n => ddr3_cas_n,
ddr3_we_n => ddr3_we_n,
ddr3_reset_n => ddr3_reset_n,
ddr3_ck_p => ddr3_ck_p,
ddr3_ck_n => ddr3_ck_n,
ddr3_cke => ddr3_cke,
ddr3_cs_n => ddr3_cs_n,
ddr3_dm => ddr3_dm,
ddr3_odt => ddr3_odt,
ahbsi => mig_ahbsi,
ahbso => mig_ahbso,
apbi => apbi,
apbo => apbo(4),
calib_done => calib_done,
rst_n_syn => migrstn,
rst_n_async => rstraw,
clk_amba => clkm,
sys_clk_p => clk200p,
sys_clk_n => clk200n,
clk_ref_i => clkref,
ui_clk => clkm,
ui_clk_sync_rst => open
);
clkgenmigref0 : clkgen
generic map (clktech, 16, 8, 0,CFG_CLK_NOFB, 0, 0, 0, 100000)
port map (clkm, clkm, clkref, open, open, open, open, cgi, cgo, open, open, open);
end generate gen_mig;
gen_mig_model : if (USE_MIG_INTERFACE_MODEL = true) generate
-- pragma translate_off
mig_ahbram : ahbram_sim
generic map (
hindex => 4*(1-CFG_L2_EN),
haddr => 16#400#,
hmask => 16#C00#,
tech => 0,
kbytes => 1000,
pipe => 0,
maccsz => AHBDW,
fname => "ram.srec")
port map(
rst => rstn,
clk => clkm,
ahbsi => mig_ahbsi,
ahbso => mig_ahbso);
ddr3_dq <= (others => 'Z');
ddr3_dqs_p <= (others => 'Z');
ddr3_dqs_n <= (others => 'Z');
ddr3_addr <= (others => '0');
ddr3_ba <= (others => '0');
ddr3_ras_n <= '0';
ddr3_cas_n <= '0';
ddr3_we_n <= '0';
ddr3_reset_n <= '1';
ddr3_ck_p <= (others => '0');
ddr3_ck_n <= (others => '0');
ddr3_cke <= (others => '0');
ddr3_cs_n <= (others => '0');
ddr3_dm <= (others => '0');
ddr3_odt <= (others => '0');
calib_done <= '1';
clkm <= not clkm after 5.0 ns;
-- pragma translate_on
end generate gen_mig_model;
end generate;
no_mig_gen : if (CFG_MIG_7SERIES = 0) generate
ahbram0 : ahbram
generic map (hindex => 4*(1-CFG_L2_EN), haddr => 16#400#, tech => CFG_MEMTECH, kbytes => 128)
port map ( rstn, clkm, mig_ahbsi, mig_ahbso);
--pragma translate_off
-- LOC for DDR3 i/f not included when MIG is disabled.
ddrdummy0 : ddr_dummy
port map (
ddr_dq => ddr3_dq,
ddr_dqs => ddr3_dqs_p,
ddr_dqs_n => ddr3_dqs_n,
ddr_addr => ddr3_addr,
ddr_ba => ddr3_ba,
ddr_ras_n => ddr3_ras_n,
ddr_cas_n => ddr3_cas_n,
ddr_we_n => ddr3_we_n,
ddr_reset_n => ddr3_reset_n,
ddr_ck_p => ddr3_ck_p,
ddr_ck_n => ddr3_ck_n,
ddr_cke => ddr3_cke,
ddr_cs_n => ddr3_cs_n,
ddr_dm => ddr3_dm,
ddr_odt => ddr3_odt
);
--pragma translate_on
calib_done <= '1';
end generate no_mig_gen;
led2_pad : outpad generic map (tech => padtech, level => cmos, voltage => x15v)
port map (led(2), calib_done);
led3_pad : outpad generic map (tech => padtech, level => cmos, voltage => x15v)
port map (led(3), lock);
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm
generic map(
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 14, paddr => 16#C00#, pmask => 16#C00#, pirq => 3, memtech => memtech,
mdcscaler => CPU_FREQ/1000, rmii => 0, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 2, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF, phyrstadr => 7,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, enable_mdint => 1,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL,
giga => CFG_GRETH1G, ramdebug => 0, gmiimode => 1)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
apbi => apbi, apbo => apbo(14), ethi => ethi, etho => etho);
-----------------------------------------------------------------------------
-- An IDELAYCTRL primitive needs to be instantiated for the Fixed Tap Delay
-- mode of the IDELAY.
-- All IDELAYs in Fixed Tap Delay mode and the IDELAYCTRL primitives have
-- to be LOC'ed in the UCF file.
-----------------------------------------------------------------------------
dlyctrl0 : IDELAYCTRL port map (
RDY => OPEN,
REFCLK => io_ref,
RST => idelayctrl_reset
);
delay_rgmii_rx_ctl0 : IODELAYE1 generic map(
DELAY_SRC => "I",
IDELAY_TYPE => "FIXED",
IDELAY_VALUE => 20
)
port map(
IDATAIN => rgmiii_buf.rx_dv,
ODATAIN => '0',
DATAOUT => rgmiii.rx_dv,
DATAIN => '0',
C => '0',
T => '1',
CE => '0',
INC => '0',
CINVCTRL => '0',
CLKIN => '0',
CNTVALUEIN => "00000",
CNTVALUEOUT => OPEN,
RST => '0'
);
rgmii_rxd : for i in 0 to 3 generate
delay_rgmii_rxd0 : IODELAYE1 generic map(
DELAY_SRC => "I",
IDELAY_TYPE => "FIXED",
IDELAY_VALUE => 20
)
port map(
IDATAIN => rgmiii_buf.rxd(i),
ODATAIN => '0',
DATAOUT => rgmiii.rxd(i),
DATAIN => '0',
C => '0',
T => '1',
CE => '0',
INC => '0',
CINVCTRL => '0',
CLKIN => '0',
CNTVALUEIN => "00000",
CNTVALUEOUT => OPEN,
RST => '0'
);
end generate;
-- Generate a synchron delayed reset for Xilinx IO delay
rst1 : rstgen
generic map (acthigh => 1)
port map (rst, io_ref, lock, rstgtxn, OPEN);
process (io_ref,rstgtxn)
begin
if (rstgtxn = '0') then
idelay_reset_cnt <= (others => '0');
idelayctrl_reset <= '1';
elsif rising_edge(io_ref) then
if (idelay_reset_cnt > "1110") then
idelay_reset_cnt <= (others => '1');
idelayctrl_reset <= '0';
else
idelay_reset_cnt <= idelay_reset_cnt + 1;
idelayctrl_reset <= '1';
end if;
end if;
end process;
-- RGMII Interface
rgmii0 : rgmii generic map (pindex => 11, paddr => 16#010#, pmask => 16#ff0#, tech => fabtech,
gmii => CFG_GRETH1G, debugmem => 1, abits => 8, no_clk_mux => 1,
pirq => 11, use90degtxclk => 1)
port map (rstn, ethi, etho, rgmiii, rgmiio, clkm, rstn, apbi, apbo(11));
egtxc_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v, slew => 1)
port map (phy_gtxclk, rgmiio.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, level => cmos, voltage => x25v, arch => 4)
port map (phy_rxclk, rgmiii.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, level => cmos, voltage => x25v, width => 4)
port map (phy_rxd, rgmiii_buf.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (phy_rxctl_rxdv, rgmiii_buf.rx_dv);
etxd_pad : outpadv generic map (tech => padtech, level => cmos, voltage => x25v, slew => 1, width => 4)
port map (phy_txd, rgmiio.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v, slew => 1)
port map (phy_txctl_txen, rgmiio.tx_en);
emdio_pad : iopad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (phy_mdio, rgmiio.mdio_o, rgmiio.mdio_oe, rgmiii.mdio_i);
emdc_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (phy_mdc, rgmiio.mdc);
eint_pad : inpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (phy_int, rgmiii.mdint);
erst_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (phy_reset, rgmiio.reset);
-- GTX Clock
rgmiii.gtx_clk <= gtx_clk;
-- 125MHz input clock
ibufds_gtrefclk : IBUFDS_GTE2
port map (
I => gtrefclk_p,
IB => gtrefclk_n,
CEB => '0',
O => gtx_clk_nobuf,
ODIV2 => open
);
cgi2.pllctrl <= "00"; cgi2.pllrst <= rstraw;
clkgen_gtrefclk : clkgen
generic map (clktech, 8, 8, 0, 0, 0, 0, 0, 125000)
port map (gtx_clk_nobuf, gtx_clk_nobuf, gtx_clk, rgmiii.tx_clk_90, io_ref, open, open, cgi2, cgo2, open, open, open);
end generate;
noeth0 : if CFG_GRETH = 0 generate
-- TODO:
end generate;
----------------------------------------------------------------------
--- I2C Controller --------------------------------------------------
----------------------------------------------------------------------
--i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master
i2c0 : i2cmst generic map (pindex => 9, paddr => 9, pmask => 16#FFF#, pirq => 4, filter => 9)
port map (rstn, clkm, apbi, apbo(9), i2ci, i2co);
i2c_scl_pad : iopad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (iic_scl, i2co.scl, i2co.scloen, i2ci.scl);
i2c_sda_pad : iopad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (iic_sda, i2co.sda, i2co.sdaoen, i2ci.sda);
--end generate i2cm;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16, debug => 2)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW, wdog => CFG_GPT_WDOGEN*CFG_GPT_WDOG)
port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
gpti <= gpti_dhalt_drive(syso.dsu_tstop);
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 10, paddr => 10, imask => CFG_GRGPIO_IMASK, nbits => 7)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(10),
gpioi => gpioi, gpioo => gpioo);
pio_pads : for i in 0 to 2 generate
pio_pad : iopad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (switch(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
pio_pads2 : for i in 3 to 5 generate
pio_pad : inpad generic map (tech => padtech, level => cmos, voltage => x15v)
port map (button(i-2), gpioi.din(i));
end generate;
end generate;
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0';
serrx_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (led(5), rxd1);
sertx_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (led(6), txd1);
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
stati <= ahbstat_in_none;
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 7, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 5, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(5));
end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0 : ahbrep generic map (hindex => 3, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(3));
-- pragma translate_on
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+1) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON/GRLIB Xilinx KC705 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-3.0 | 6fb10728813a03c4c85a0be2196b0d0d | 0.510208 | 3.67911 | false | false | false | false |
GLADICOS/SPACEWIRESYSTEMC | rtl/RTL_SL/spwlink.vhd | 2 | 10,334 | --
-- SpaceWire Exchange Level Controller.
--
-- This entity implements exchange level aspects of the SpaceWire protocol.
-- It handles connection setup, error detection and flow control.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.spwpkg.all;
entity spwlink is
generic (
-- Reset time expressed in system clock cycles.
-- Should be 6.4 us (5.82 us .. 7.2 us) according to the standard.
reset_time: integer
);
port (
-- System clock.
clk: in std_logic;
-- Synchronous reset (active-high).
-- Disconnects, resets error conditions, puts the link state machine
-- in state ErrorReset.
rst: in std_logic;
-- Link level inputs.
linki: in spw_link_in_type;
-- Link level outputs.
linko: out spw_link_out_type;
-- Receiver enable signal to spwrecv.
rxen: out std_logic;
-- Output signals from spwrecv.
recvo: in spw_recv_out_type;
-- Input signals for spwxmit.
xmiti: out spw_xmit_in_type;
-- Output signals from spwxmit.
xmito: in spw_xmit_out_type
);
end entity spwlink;
architecture spwlink_arch of spwlink is
-- Convert boolean to std_logic.
type bool_to_logic_type is array(boolean) of std_ulogic;
constant bool_to_logic: bool_to_logic_type := (false => '0', true => '1');
-- State machine.
type state_type is (
S_ErrorReset, S_ErrorWait, S_Ready, S_Started, S_Connecting, S_Run );
-- Registers
type regs_type is record
-- state machine
state: state_type;
-- credit accounting
tx_credit: unsigned(5 downto 0);
rx_credit: unsigned(5 downto 0);
errcred: std_ulogic;
-- reset timer
timercnt: unsigned(10 downto 0);
timerdone: std_ulogic;
-- signal to transmitter
xmit_fct_in: std_ulogic;
end record;
-- Initial state
constant regs_reset: regs_type := (
state => S_ErrorReset,
tx_credit => "000000",
rx_credit => "000000",
errcred => '0',
timercnt => to_unsigned(reset_time, 11),
timerdone => '0',
xmit_fct_in => '0' );
signal r: regs_type := regs_reset;
signal rin: regs_type;
begin
-- Combinatorial process
process (r, rst, linki, recvo, xmito) is
variable v: regs_type;
variable v_timerrst: std_logic;
begin
v := r;
v_timerrst := '0';
-- State machine.
case r.state is
when S_ErrorReset =>
-- Wait for timer.
if r.timercnt = 0 then
v.state := S_ErrorWait;
v_timerrst := '1';
end if;
v.errcred := '0';
v.xmit_fct_in := '0';
when S_ErrorWait =>
-- Wait for 2 timer periods.
if ((recvo.errdisc or recvo.errpar or recvo.erresc) = '1') or
((recvo.gotfct or recvo.tick_out or recvo.rxchar) = '1') then
-- Note: spwrecv will never issue errpar, erresc, gotfct,
-- tick_out or rxchar before the first NULL has been seen.
-- Therefore it's ok here to bail on those conditions
-- without explicitly testing got_null.
v.state := S_ErrorReset; -- error, go back to reset
v_timerrst := '1';
elsif r.timercnt = 0 then
if r.timerdone = '1' then
v.state := S_Ready;
v_timerrst := '1';
end if;
end if;
when S_Ready =>
-- Wait for link start.
if ((recvo.errdisc or recvo.errpar or recvo.erresc) = '1') or
((recvo.gotfct or recvo.tick_out or recvo.rxchar) = '1') then
v.state := S_ErrorReset; -- error, go back to reset
v_timerrst := '1';
elsif (linki.linkdis = '0') and (r.xmit_fct_in = '1') and
((linki.linkstart or (linki.autostart and recvo.gotnull)) = '1') then
v.state := S_Started; -- link enabled; start sending NULL
v_timerrst := '1';
end if;
when S_Started =>
-- Wait for NULL.
if ((recvo.errdisc or recvo.errpar or recvo.erresc) = '1') or
((recvo.gotfct or recvo.tick_out or recvo.rxchar) = '1') or
((r.timercnt = 0) and r.timerdone = '1') then
v.state := S_ErrorReset; -- error, go back to reset
v_timerrst := '1';
elsif recvo.gotnull = '1' then
v.state := S_Connecting; -- received null, continue
v_timerrst := '1';
end if;
when S_Connecting =>
-- Wait for FCT.
if ((recvo.errdisc or recvo.errpar or recvo.erresc) = '1') or
((recvo.tick_out or recvo.rxchar) = '1') or
((r.timercnt = 0) and r.timerdone = '1') then
v.state := S_ErrorReset; -- error, go back to reset
v_timerrst := '1';
elsif recvo.gotfct = '1' then
v.state := S_Run; -- got FCT, init completed
end if;
when S_Run =>
-- All is well.
if ((recvo.errdisc or recvo.errpar or recvo.erresc) = '1') or
(r.errcred = '1') or
(linki.linkdis = '1') then
v.state := S_ErrorReset; -- error, go back to reset
v_timerrst := '1';
end if;
when others =>
v.state := S_ErrorReset; -- recover from invalid state
v_timerrst := '1';
end case;
-- Update credit counters.
if r.state = S_ErrorReset then
-- reset credit
v.tx_credit := to_unsigned(0, v.tx_credit'length);
v.rx_credit := to_unsigned(0, v.rx_credit'length);
else
-- update TX credit
if recvo.gotfct = '1' then
-- just received a FCT token
v.tx_credit := v.tx_credit + to_unsigned(8, v.tx_credit'length);
if r.tx_credit > 48 then
-- received too many FCT tokens
v.errcred := '1';
end if;
end if;
if xmito.txack = '1' then
-- just sent one byte
v.tx_credit := v.tx_credit - to_unsigned(1, v.tx_credit'length);
end if;
-- update RX credit after sending FCT
if xmito.fctack = '1' then
-- just sent a FCT token
v.rx_credit := v.rx_credit + to_unsigned(8, v.rx_credit'length);
end if;
-- decide about sending FCT tokens
v.xmit_fct_in := bool_to_logic( (v.rx_credit <= 48) and
(v.rx_credit + to_unsigned(8, v.rx_credit'length) <= unsigned(linki.rxroom)) );
-- update RX credit after receiving character
if recvo.rxchar = '1' then
-- just received a character
v.rx_credit := v.rx_credit - to_unsigned(1, v.rx_credit'length);
if r.rx_credit = 0 then
-- remote transmitter violated its credit
v.errcred := '1';
end if;
end if;
end if;
-- Update the initializaton reset timer.
if v_timerrst = '1' then
v.timercnt := to_unsigned(reset_time, v.timercnt'length);
v.timerdone := '0';
else
if r.timercnt = 0 then
v.timercnt := to_unsigned(reset_time, v.timercnt'length);
v.timerdone := '1';
else
v.timercnt := r.timercnt - 1;
end if;
end if;
-- Reset
if rst = '1' then
v := regs_reset;
end if;
-- Drive link level outputs.
linko.started <= bool_to_logic(r.state = S_Started);
linko.connecting <= bool_to_logic(r.state = S_Connecting);
linko.running <= bool_to_logic(r.state = S_Run);
linko.errdisc <= recvo.errdisc and bool_to_logic(r.state = S_Run);
linko.errpar <= recvo.errpar and bool_to_logic(r.state = S_Run);
linko.erresc <= recvo.erresc and bool_to_logic(r.state = S_Run);
linko.errcred <= r.errcred;
linko.txack <= xmito.txack;
linko.tick_out <= recvo.tick_out and bool_to_logic(r.state = S_Run);
linko.ctrl_out <= recvo.ctrl_out;
linko.time_out <= recvo.time_out;
linko.rxchar <= recvo.rxchar and bool_to_logic(r.state = S_Run);
linko.rxflag <= recvo.rxflag;
linko.rxdata <= recvo.rxdata;
-- Drive receiver inputs.
rxen <= bool_to_logic(r.state /= S_ErrorReset);
-- Drive transmitter input signals.
xmiti.txen <= bool_to_logic(r.state = S_Started or
r.state = S_Connecting or
r.state = S_Run);
xmiti.stnull <= bool_to_logic(r.state = S_Started);
xmiti.stfct <= bool_to_logic(r.state = S_Connecting);
xmiti.fct_in <= r.xmit_fct_in;
xmiti.tick_in <= linki.tick_in and bool_to_logic(r.state = S_Run);
xmiti.ctrl_in <= linki.ctrl_in;
xmiti.time_in <= linki.time_in;
xmiti.txwrite <= linki.txwrite and bool_to_logic(r.tx_credit /= 0);
xmiti.txflag <= linki.txflag;
xmiti.txdata <= linki.txdata;
-- Update registers.
rin <= v;
end process;
-- Update registers.
process (clk) is
begin
if rising_edge(clk) then
r <= rin;
end if;
end process;
end architecture spwlink_arch;
| gpl-3.0 | 9fceea1abbf140baaac9b0d0b0e53f4f | 0.488872 | 3.740138 | false | false | false | false |
GLADICOS/SPACEWIRESYSTEMC | rtl/RTL_SL/spwamba.vhd | 1 | 35,180 | --
-- SpaceWire core with AMBA interface.
--
-- APB registers:
--
-- Address 0x00: Control Register
-- bit 0 Reset spwamba core (auto-clear)
-- bit 1 Reset DMA engines (auto-clear)
-- bit 2 Link start
-- bit 3 Link autostart
-- bit 4 Link disable
-- bit 5 Enable timecode transmission through tick_in signal
-- bit 6 Start RX DMA (auto-clear)
-- bit 7 Start TX DMA (auto-clear)
-- bit 8 Cancel TX DMA and discard TX data queue (auto-clear)
-- bit 9 Enable interrupt on link up/down
-- bit 10 Enable interrupt on time code received
-- bit 11 Enable interrupt on RX descriptor
-- bit 12 Enable interrupt on TX descriptor
-- bit 13 Enable interrupt on RX packet
-- bit 27:24 desctablesize (read-only)
--
-- Address 0x04: Status Register
-- bit 1:0 Link status: 0=off, 1=started, 2=connecting, 3=run
-- bit 2 Got disconnect error (sticky)
-- bit 3 Got parity error (sticky)
-- bit 4 Got escape error (sticky)
-- bit 5 Got credit error (sticky)
-- bit 6 RX DMA enabled
-- bit 7 TX DMA enabled
-- bit 8 AHB error occurred (reset DMA engine to clear)
-- bit 9 Reserved
-- bit 10 Received timecode (sticky)
-- bit 11 Finished RX descriptor with IE='1' (sticky)
-- bit 12 Finished TX descriptor with IE='1' (sticky)
-- bit 13 Received packet (sticky)
-- bit 14 RX buffer empty after packet
--
-- Sticky bits are reset by writing a '1' bit to the corresponding
-- bit position(s).
--
-- Address 0x08: Transmission Clock Scaler
-- bit 7:0 txclk division factor minus 1
--
-- Address 0x0c: Timecode Register
-- bit 5:0 Last received timecode value (read-only)
-- bit 7:6 Control bits received with last timecode (read-only)
-- bit 13:8 Timecode value to send on next tick_in (auto-increment)
-- bit 15:14 Reserved (write as zero)
-- bit 16 Write '1' to send a timecode (auto-clear)
--
-- Address 0x10: Descriptor pointer for RX DMA
-- bit 2:0 Reserved, write as zero
-- bit desctablesize+2:3 Descriptor index (auto-increment)
-- bit 31:desctablesize+3 Fixed address bits of descriptor table
--
-- For example, if desctablesize = 10, a 8192-byte area is
-- determined by bits 31:13. This area has room for 1024 descriptors
-- of 8 bytes each. Bits 12:3 point to the current descriptor within
-- the table.
--
-- Address 0x14: Descriptor pointer for TX DMA
-- bit 2:0 Reserved, write as zero
-- bit desctablesize+2:3 Descriptor index (auto-increment)
-- bit 31:desctablesize+3 Fixed address bits of descriptor table
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
use work.spwpkg.all;
use work.spwambapkg.all;
entity spwamba is
generic (
-- Technology selection for FIFO memories.
tech: integer range 0 to NTECH := DEFFABTECH;
-- AHB master index.
hindex: integer;
-- APB slave index.
pindex: integer;
-- Bits 19 to 8 of the APB address range.
paddr: integer;
-- Mask for APB address bits 19 to 8.
pmask: integer := 16#fff#;
-- Index of the interrupt request line.
pirq: integer;
-- System clock frequency in Hz.
-- This must be set to the frequency of "clk". It is used to setup
-- counters for reset timing, disconnect timeout and to transmit
-- at 10 Mbit/s during the link handshake.
sysfreq: real;
-- Transmit clock frequency in Hz (only if tximpl = impl_fast).
-- This must be set to the frequency of "txclk". It is used to
-- transmit at 10 Mbit/s during the link handshake.
txclkfreq: real := 0.0;
-- Selection of a receiver front-end implementation.
rximpl: spw_implementation_type := impl_generic;
-- Maximum number of bits received per system clock
-- (must be 1 in case of impl_generic).
rxchunk: integer range 1 to 4 := 1;
-- Selection of a transmitter implementation.
tximpl: spw_implementation_type := impl_generic;
-- Enable capability to generate time-codes.
timecodegen: boolean := true;
-- Size of the receive FIFO as the 2-logarithm of the number of words.
-- Must be at least 6 (64 words = 256 bytes).
rxfifosize: integer range 6 to 12 := 8;
-- Size of the transmit FIFO as the 2-logarithm of the number of words.
txfifosize: integer range 2 to 12 := 8;
-- Size of the DMA descriptor tables as the 2-logarithm of the number
-- of descriptors.
desctablesize: integer range 4 to 14 := 10;
-- Maximum burst length as the 2-logarithm of the number of words (default 8 words).
maxburst: integer range 1 to 8 := 3
);
port (
-- System clock.
clk: in std_logic;
-- Receiver sample clock (only for impl_fast)
rxclk: in std_logic;
-- Transmit clock (only for impl_fast)
txclk: in std_logic;
-- Synchronous reset (active-low).
rstn: in std_logic;
-- APB slave input signals.
apbi: in apb_slv_in_type;
-- APB slave output signals.
apbo: out apb_slv_out_type;
-- AHB master input signals.
ahbi: in ahb_mst_in_type;
-- AHB master output signals.
ahbo: out ahb_mst_out_type;
-- Pulse for TimeCode generation.
tick_in: in std_logic;
-- High for one clock cycle if a TimeCode was just received.
tick_out: out std_logic;
-- Data In signal from SpaceWire bus.
spw_di: in std_logic;
-- Strobe In signal from SpaceWire bus.
spw_si: in std_logic;
-- Data Out signal to SpaceWire bus.
spw_do: out std_logic;
-- Strobe Out signal to SpaceWire bus.
spw_so: out std_logic
);
end entity spwamba;
architecture spwamba_arch of spwamba is
-- Reset time (6.4 us) in system clocks
constant reset_time: integer := integer(sysfreq * 6.4e-6);
-- Disconnect time (850 ns) in system clocks
constant disconnect_time: integer := integer(sysfreq * 850.0e-9);
-- Initial tx clock scaler (10 Mbit).
type impl_to_real_type is array(spw_implementation_type) of real;
constant tximpl_to_txclk_freq: impl_to_real_type :=
(impl_generic => sysfreq, impl_fast => txclkfreq);
constant effective_txclk_freq: real := tximpl_to_txclk_freq(tximpl);
constant default_divcnt: std_logic_vector(7 downto 0) :=
std_logic_vector(to_unsigned(integer(effective_txclk_freq / 10.0e6 - 1.0), 8));
-- Registers.
type regs_type is record
-- packet state
rxpacket: std_logic; -- '1' when receiving a packet
rxeep: std_logic; -- '1' when rx EEP character pending
txpacket: std_logic; -- '1' when transmitting a packet
txdiscard: std_logic; -- '1' when discarding a tx packet
-- RX fifo state
rxfifo_raddr: std_logic_vector(rxfifosize-1 downto 0);
rxfifo_waddr: std_logic_vector(rxfifosize-1 downto 0);
rxfifo_wdata: std_logic_vector(35 downto 0);
rxfifo_write: std_ulogic;
rxfifo_empty: std_ulogic;
rxfifo_bytemsk: std_logic_vector(2 downto 0);
rxroom: std_logic_vector(5 downto 0);
-- TX fifo state
txfifo_raddr: std_logic_vector(txfifosize-1 downto 0);
txfifo_waddr: std_logic_vector(txfifosize-1 downto 0);
txfifo_empty: std_ulogic;
txfifo_nxfull: std_ulogic;
txfifo_highw: std_ulogic;
txfifo_bytepos: std_logic_vector(1 downto 0);
-- APB registers
ctl_reset: std_ulogic;
ctl_resetdma: std_ulogic;
ctl_linkstart: std_ulogic;
ctl_autostart: std_ulogic;
ctl_linkdis: std_ulogic;
ctl_ticken: std_ulogic;
ctl_rxstart: std_ulogic;
ctl_txstart: std_ulogic;
ctl_txcancel: std_ulogic;
ctl_ielink: std_ulogic;
ctl_ietick: std_ulogic;
ctl_ierxdesc: std_ulogic;
ctl_ietxdesc: std_ulogic;
ctl_ierxpacket: std_ulogic;
sta_link: std_logic_vector(1 downto 0);
sta_errdisc: std_ulogic;
sta_errpar: std_ulogic;
sta_erresc: std_ulogic;
sta_errcred: std_ulogic;
sta_gottick: std_ulogic;
sta_rxdesc: std_ulogic;
sta_txdesc: std_ulogic;
sta_rxpacket: std_ulogic;
sta_rxempty: std_ulogic;
txdivcnt: std_logic_vector(7 downto 0);
time_in: std_logic_vector(5 downto 0);
tick_in: std_ulogic;
rxdesc_ptr: std_logic_vector(31 downto 3);
txdesc_ptr: std_logic_vector(31 downto 3);
-- APB interrupt request
irq: std_ulogic;
end record;
constant regs_reset: regs_type := (
rxpacket => '0',
rxeep => '0',
txpacket => '0',
txdiscard => '0',
rxfifo_raddr => (others => '0'),
rxfifo_waddr => (others => '0'),
rxfifo_wdata => (others => '0'),
rxfifo_write => '0',
rxfifo_empty => '1',
rxfifo_bytemsk => "111",
rxroom => (others => '1'),
txfifo_raddr => (others => '0'),
txfifo_waddr => (others => '0'),
txfifo_empty => '1',
txfifo_nxfull => '0',
txfifo_highw => '0',
txfifo_bytepos => "00",
ctl_reset => '0',
ctl_resetdma => '0',
ctl_linkstart => '0',
ctl_autostart => '0',
ctl_linkdis => '0',
ctl_ticken => '0',
ctl_rxstart => '0',
ctl_txstart => '0',
ctl_txcancel => '0',
ctl_ielink => '0',
ctl_ietick => '0',
ctl_ierxdesc => '0',
ctl_ietxdesc => '0',
ctl_ierxpacket => '0',
sta_link => "00",
sta_errdisc => '0',
sta_errpar => '0',
sta_erresc => '0',
sta_errcred => '0',
sta_gottick => '0',
sta_rxdesc => '0',
sta_txdesc => '0',
sta_rxpacket => '0',
sta_rxempty => '1',
txdivcnt => default_divcnt,
time_in => (others => '0'),
tick_in => '0',
rxdesc_ptr => (others => '0'),
txdesc_ptr => (others => '0'),
irq => '0' );
signal r: regs_type := regs_reset;
signal rin: regs_type;
-- Component interface signals.
signal recv_rxen: std_logic;
signal recvo: spw_recv_out_type;
signal recv_inact: std_logic;
signal recv_inbvalid: std_logic;
signal recv_inbits: std_logic_vector(rxchunk-1 downto 0);
signal xmit_rst: std_logic;
signal xmiti: spw_xmit_in_type;
signal xmito: spw_xmit_out_type;
signal xmit_divcnt: std_logic_vector(7 downto 0);
signal link_rst: std_logic;
signal linki: spw_link_in_type;
signal linko: spw_link_out_type;
signal msti: spw_ahbmst_in_type;
signal msto: spw_ahbmst_out_type;
signal ahbmst_rstn: std_logic;
-- Memory interface signals.
signal s_rxfifo_raddr: std_logic_vector(rxfifosize-1 downto 0);
signal s_rxfifo_rdata: std_logic_vector(35 downto 0);
signal s_rxfifo_wen: std_logic;
signal s_rxfifo_waddr: std_logic_vector(rxfifosize-1 downto 0);
signal s_rxfifo_wdata: std_logic_vector(35 downto 0);
signal s_txfifo_raddr: std_logic_vector(txfifosize-1 downto 0);
signal s_txfifo_rdata: std_logic_vector(35 downto 0);
signal s_txfifo_wen: std_logic;
signal s_txfifo_waddr: std_logic_vector(txfifosize-1 downto 0);
signal s_txfifo_wdata: std_logic_vector(35 downto 0);
-- APB slave plug&play configuration
constant REVISION: integer := 0;
constant pconfig: apb_config_type := (
0 => ahb_device_reg(VENDOR_OPENCORES, DEVICE_SPACEWIRELIGHT, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask) );
-- AHB master plug&play configuration
constant hconfig: ahb_config_type := (
0 => ahb_device_reg(VENDOR_OPENCORES, DEVICE_SPACEWIRELIGHT, 0, REVISION, 0),
others => zero32 );
begin
-- Instantiate link controller.
link_inst: spwlink
generic map (
reset_time => reset_time )
port map (
clk => clk,
rst => link_rst,
linki => linki,
linko => linko,
rxen => recv_rxen,
recvo => recvo,
xmiti => xmiti,
xmito => xmito );
-- Instantiate receiver.
recv_inst: spwrecv
generic map(
disconnect_time => disconnect_time,
rxchunk => rxchunk )
port map (
clk => clk,
rxen => recv_rxen,
recvo => recvo,
inact => recv_inact,
inbvalid => recv_inbvalid,
inbits => recv_inbits );
-- Instantiate receiver front-end.
recvfront_sel0: if rximpl = impl_generic generate
recvfront_generic_inst: spwrecvfront_generic
port map (
clk => clk,
rxen => recv_rxen,
inact => recv_inact,
inbvalid => recv_inbvalid,
inbits => recv_inbits,
spw_di => spw_di,
spw_si => spw_si );
end generate;
recvfront_sel1: if rximpl = impl_fast generate
recvfront_fast_inst: spwrecvfront_fast
generic map (
rxchunk => rxchunk )
port map (
clk => clk,
rxclk => rxclk,
rxen => recv_rxen,
inact => recv_inact,
inbvalid => recv_inbvalid,
inbits => recv_inbits,
spw_di => spw_di,
spw_si => spw_si );
end generate;
-- Instantiate transmitter.
xmit_sel0: if tximpl = impl_generic generate
xmit_inst: spwxmit
port map (
clk => clk,
rst => xmit_rst,
divcnt => xmit_divcnt,
xmiti => xmiti,
xmito => xmito,
spw_do => spw_do,
spw_so => spw_so );
end generate;
xmit_sel1: if tximpl = impl_fast generate
xmit_fast_inst: spwxmit_fast
port map (
clk => clk,
txclk => txclk,
rst => xmit_rst,
divcnt => xmit_divcnt,
xmiti => xmiti,
xmito => xmito,
spw_do => spw_do,
spw_so => spw_so );
end generate;
-- Instantiate RX FIFO.
rxfifo: syncram_2p
generic map (
tech => tech,
abits => rxfifosize,
dbits => 36,
sepclk => 0 )
port map (
rclk => clk,
renable => '1',
raddress => s_rxfifo_raddr,
dataout => s_rxfifo_rdata,
wclk => clk,
write => s_rxfifo_wen,
waddress => s_rxfifo_waddr,
datain => s_rxfifo_wdata );
-- Instantiate TX FIFO.
txfifo: syncram_2p
generic map (
tech => tech,
abits => txfifosize,
dbits => 36,
sepclk => 0 )
port map (
rclk => clk,
renable => '1',
raddress => s_txfifo_raddr,
dataout => s_txfifo_rdata,
wclk => clk,
write => s_txfifo_wen,
waddress => s_txfifo_waddr,
datain => s_txfifo_wdata );
-- Instantiate AHB master.
ahbmst: spwahbmst
generic map (
hindex => hindex,
hconfig => hconfig,
maxburst => maxburst )
port map (
clk => clk,
rstn => ahbmst_rstn,
msti => msti,
msto => msto,
ahbi => ahbi,
ahbo => ahbo );
--
-- Combinatorial process
--
process (r, linko, msto, s_rxfifo_rdata, s_txfifo_rdata, rstn, apbi, tick_in) is
variable v: regs_type;
variable v_tmprxroom: unsigned(rxfifosize-1 downto 0);
variable v_prdata: std_logic_vector(31 downto 0);
variable v_irq: std_logic_vector(NAHBIRQ-1 downto 0);
variable v_txfifo_bytepos: integer range 0 to 3;
begin
v := r;
v_tmprxroom := to_unsigned(0, rxfifosize);
v_prdata := (others => '0');
v_irq := (others => '0');
v_irq(pirq) := r.irq;
-- Convert RX/TX byte index to integer.
v_txfifo_bytepos := to_integer(unsigned(r.txfifo_bytepos));
-- Reset auto-clearing registers.
v.ctl_reset := '0';
v.ctl_resetdma := '0';
v.ctl_rxstart := '0';
v.ctl_txstart := '0';
-- Register external timecode trigger (if enabled).
if timecodegen and r.ctl_ticken = '1' then
v.tick_in := tick_in;
else
v.tick_in := '0';
end if;
-- Auto-increment timecode counter.
if r.tick_in = '1' then
v.time_in := std_logic_vector(unsigned(r.time_in) + 1);
end if;
-- Keep track of whether we are sending and/or receiving a packet.
if linko.rxchar = '1' then
-- got character
v.rxpacket := not linko.rxflag;
end if;
if linko.txack = '1' then
-- send character
v.txpacket := not s_txfifo_rdata(35-v_txfifo_bytepos);
end if;
-- Accumulate a word to write to the RX fifo.
-- Note: If the EOP/EEP marker falls in the middle of a word,
-- subsequent bytes must be a copy of the marker, otherwise
-- the AHB master may not work correctly.
v.rxfifo_write := '0';
for i in 3 downto 0 loop
if (i = 0) or (r.rxfifo_bytemsk(i-1) = '1') then
if r.rxeep = '1' then
v.rxfifo_wdata(32+i) := '1';
v.rxfifo_wdata(7+8*i downto 8*i) := "00000001";
else
v.rxfifo_wdata(32+i) := linko.rxflag;
v.rxfifo_wdata(7+8*i downto 8*i) := linko.rxdata;
end if;
end if;
end loop;
if linko.rxchar = '1' or (r.rxeep = '1' and unsigned(r.rxroom) /= 0) then
v.rxeep := '0';
if r.rxfifo_bytemsk(0) = '0' or linko.rxflag = '1' or r.rxeep = '1' then
-- Flush the current word to the FIFO.
v.rxfifo_write := '1';
v.rxfifo_bytemsk := "111";
else
-- Store one byte.
v.rxfifo_bytemsk := '0' & r.rxfifo_bytemsk(2 downto 1);
end if;
end if;
-- Read from TX fifo.
if (r.txfifo_empty = '0') and (linko.txack = '1' or r.txdiscard = '1') then
-- Update byte pointer.
if r.txfifo_bytepos = "11" or
s_txfifo_rdata(35-v_txfifo_bytepos) = '1' or
(v_txfifo_bytepos < 3 and
s_txfifo_rdata(34-v_txfifo_bytepos) = '1' and
s_txfifo_rdata(23-8*v_txfifo_bytepos) = '1') then
-- This is the last byte in the current word;
-- OR the current byte is an EOP/EEP marker;
-- OR the next byte in the current word is a non-EOP end-of-frame marker.
v.txfifo_bytepos := "00";
v.txfifo_raddr := std_logic_vector(unsigned(r.txfifo_raddr) + 1);
else
-- Move to next byte.
v.txfifo_bytepos := std_logic_vector(unsigned(r.txfifo_bytepos) + 1);
end if;
-- Clear discard flag when past EOP.
if s_txfifo_rdata(35-v_txfifo_bytepos) = '1' then
v.txdiscard := '0';
end if;
end if;
-- Update RX fifo pointers.
if msto.rxfifo_read = '1' then
-- Read one word.
v.rxfifo_raddr := std_logic_vector(unsigned(r.rxfifo_raddr) + 1);
end if;
if r.rxfifo_write = '1' then
-- Write one word.
v.rxfifo_waddr := std_logic_vector(unsigned(r.rxfifo_waddr) + 1);
end if;
-- Detect RX fifo empty (using new value of rxfifo_raddr).
-- Note: The FIFO is empty if head and tail pointer are equal.
v.rxfifo_empty := conv_std_logic(v.rxfifo_raddr = r.rxfifo_waddr);
-- Indicate RX fifo room for SpaceWire flow control.
-- The flow control window is normally expressed as a number of bytes,
-- but we don't know how many bytes we can fit in each word because
-- some words are only partially used. So we report FIFO room as if
-- each FIFO word can hold only one byte, which is an overly
-- pessimistic estimate.
-- (Use the new value of rxfifo_waddr.)
v_tmprxroom := unsigned(r.rxfifo_raddr) - unsigned(v.rxfifo_waddr) - 1;
if v_tmprxroom > 63 then
-- at least 64 bytes room.
v.rxroom := "111111";
else
-- less than 64 bytes room.
-- If linko.rxchar = '1', decrease rxroom by one to account for
-- the pipeline delay through r.rxfifo_write.
v.rxroom := std_logic_vector(v_tmprxroom(5 downto 0) -
to_unsigned(conv_integer(linko.rxchar), 6));
end if;
-- Update TX fifo write pointer.
if msto.txfifo_write = '1' then
-- write one word.
v.txfifo_waddr := std_logic_vector(unsigned(r.txfifo_waddr) + 1);
end if;
-- Detect TX fifo empty.
-- Note: The FIFO may be either full or empty if head and tail pointer
-- are equal, hence the additional test for txfifo_nxfull.
v.txfifo_empty := conv_std_logic(v.txfifo_raddr = r.txfifo_waddr) and not r.txfifo_nxfull;
-- Detect TX fifo full after one more write.
if unsigned(r.txfifo_raddr) - unsigned(r.txfifo_waddr) = to_unsigned(2, txfifosize) then
-- currently exactly 2 words left.
v.txfifo_nxfull := msto.txfifo_write;
end if;
-- Detect TX fifo high water mark.
if txfifosize > maxburst then
-- Indicate high water when there is no room for a maximum burst.
if unsigned(r.txfifo_raddr) - unsigned(r.txfifo_waddr) = to_unsigned(2**maxburst + 1, txfifosize) then
-- currently room for exactly one maximum burst.
v.txfifo_highw := msto.txfifo_write;
end if;
else
-- Indicate high water when more than half full.
if unsigned(r.txfifo_raddr) - unsigned(r.txfifo_waddr) = to_unsigned(2**(txfifosize-1), txfifosize) then
-- currently exactly half full.
v.txfifo_highw := msto.txfifo_write;
end if;
end if;
-- Update descriptor pointers.
if msto.rxdesc_next = '1' then
if msto.rxdesc_wrap = '1' then
v.rxdesc_ptr(desctablesize+2 downto 3) := (others => '0');
else
v.rxdesc_ptr(desctablesize+2 downto 3) :=
std_logic_vector(unsigned(r.rxdesc_ptr(desctablesize+2 downto 3)) + 1);
end if;
end if;
if msto.txdesc_next = '1' then
if msto.txdesc_wrap = '1' then
v.txdesc_ptr(desctablesize+2 downto 3) := (others => '0');
else
v.txdesc_ptr(desctablesize+2 downto 3) :=
std_logic_vector(unsigned(r.txdesc_ptr(desctablesize+2 downto 3)) + 1);
end if;
end if;
-- If the link is lost, set a flag to discard the current packet.
if linko.running = '0' then
v.rxeep := v.rxeep or v.rxpacket; -- use new value of rxpacket
v.txdiscard := v.txdiscard or v.txpacket; -- use new value of txpacket
v.rxpacket := '0';
v.txpacket := '0';
end if;
-- Clear the discard flag when the link is explicitly disabled.
if r.ctl_linkdis = '1' then
v.txdiscard := '0';
end if;
-- Extend TX cancel command until TX DMA has stopped.
if msto.txdma_act = '0' then
v.ctl_txcancel := '0';
end if;
-- Update status registers.
v.sta_link(0) := linko.running or linko.started;
v.sta_link(1) := linko.running or linko.connecting;
if linko.errdisc = '1' then v.sta_errdisc := '1'; end if;
if linko.errpar = '1' then v.sta_errpar := '1'; end if;
if linko.erresc = '1' then v.sta_erresc := '1'; end if;
if linko.errcred = '1' then v.sta_errcred := '1'; end if;
if linko.tick_out = '1' then v.sta_gottick := '1'; end if;
if msto.int_rxdesc = '1' then v.sta_rxdesc := '1'; end if;
if msto.int_txdesc = '1' then v.sta_txdesc := '1'; end if;
if msto.int_rxpacket = '1' then v.sta_rxpacket := '1'; end if;
if msto.int_rxpacket = '1' and r.rxfifo_empty = '1' then
v.sta_rxempty := '1';
elsif r.rxfifo_empty = '0' then
v.sta_rxempty := '0';
end if;
-- Generate interrupt requests.
v.irq :=
(r.ctl_ielink and (linko.running xor (r.sta_link(0) and r.sta_link(1)))) or
(r.ctl_ietick and linko.tick_out) or
(r.ctl_ierxdesc and msto.int_rxdesc) or
(r.ctl_ietxdesc and msto.int_txdesc) or
(r.ctl_ierxpacket and msto.int_rxpacket);
-- APB read access.
if apbi.psel(pindex) = '1' then
case apbi.paddr(4 downto 2) is
when "000" => -- read control register
v_prdata(0) := '0';
v_prdata(1) := '0';
v_prdata(2) := r.ctl_linkstart;
v_prdata(3) := r.ctl_autostart;
v_prdata(4) := r.ctl_linkdis;
v_prdata(5) := r.ctl_ticken;
v_prdata(6) := '0';
v_prdata(7) := '0';
v_prdata(8) := r.ctl_txcancel;
v_prdata(9) := r.ctl_ielink;
v_prdata(10) := r.ctl_ietick;
v_prdata(11) := r.ctl_ierxdesc;
v_prdata(12) := r.ctl_ietxdesc;
v_prdata(13) := r.ctl_ierxpacket;
v_prdata(27 downto 24) := std_logic_vector(to_unsigned(desctablesize, 4));
when "001" => -- read status register
v_prdata(1 downto 0) := r.sta_link;
v_prdata(2) := r.sta_errdisc;
v_prdata(3) := r.sta_errpar;
v_prdata(4) := r.sta_erresc;
v_prdata(5) := r.sta_errcred;
v_prdata(6) := msto.rxdma_act;
v_prdata(7) := msto.txdma_act;
v_prdata(8) := msto.ahberror;
v_prdata(10) := r.sta_gottick;
v_prdata(11) := r.sta_rxdesc;
v_prdata(12) := r.sta_txdesc;
v_prdata(13) := r.sta_rxpacket;
v_prdata(14) := r.sta_rxempty;
when "010" => -- read transmission clock scaler
v_prdata(7 downto 0) := r.txdivcnt;
when "011" => -- read timecode register
v_prdata(5 downto 0) := linko.time_out;
v_prdata(7 downto 6) := linko.ctrl_out;
v_prdata(13 downto 8) := r.time_in;
v_prdata(16 downto 14) := "000";
when "100" => -- read rx descriptor pointer
v_prdata(2 downto 0) := (others => '0');
v_prdata(31 downto 3) := r.rxdesc_ptr;
when "101" => -- read tx descriptor pointer
v_prdata(2 downto 0) := (others => '0');
v_prdata(31 downto 3) := r.txdesc_ptr;
when others =>
null;
end case;
end if;
-- APB write access.
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(4 downto 2) is
when "000" => -- write control register
v.ctl_reset := apbi.pwdata(0);
v.ctl_resetdma := apbi.pwdata(1);
v.ctl_linkstart := apbi.pwdata(2);
v.ctl_autostart := apbi.pwdata(3);
v.ctl_linkdis := apbi.pwdata(4);
v.ctl_ticken := apbi.pwdata(5);
v.ctl_rxstart := apbi.pwdata(6);
v.ctl_txstart := apbi.pwdata(7);
if apbi.pwdata(8) = '1' then v.ctl_txcancel := '1'; end if;
v.ctl_ielink := apbi.pwdata(9);
v.ctl_ietick := apbi.pwdata(10);
v.ctl_ierxdesc := apbi.pwdata(11);
v.ctl_ietxdesc := apbi.pwdata(12);
v.ctl_ierxpacket := apbi.pwdata(13);
when "001" => -- write status register
if apbi.pwdata(2) = '1' then v.sta_errdisc := '0'; end if;
if apbi.pwdata(3) = '1' then v.sta_errpar := '0'; end if;
if apbi.pwdata(4) = '1' then v.sta_erresc := '0'; end if;
if apbi.pwdata(5) = '1' then v.sta_errcred := '0'; end if;
if apbi.pwdata(10) = '1' then v.sta_gottick := '0'; end if;
if apbi.pwdata(11) = '1' then v.sta_rxdesc := '0'; end if;
if apbi.pwdata(12) = '1' then v.sta_txdesc := '0'; end if;
if apbi.pwdata(13) = '1' then v.sta_rxpacket := '0'; end if;
when "010" => -- write transmission clock scaler
v.txdivcnt := apbi.pwdata(7 downto 0);
when "011" => -- write timecode register
v.time_in := apbi.pwdata(13 downto 8);
if apbi.pwdata(16) = '1' then v.tick_in := '1'; end if;
when "100" => -- write rx descriptor pointer
v.rxdesc_ptr := apbi.pwdata(31 downto 3);
when "101" => -- write tx descriptor pointer
v.txdesc_ptr := apbi.pwdata(31 downto 3);
when others =>
null;
end case;
end if;
-- Drive control signals to RX fifo.
s_rxfifo_raddr <= v.rxfifo_raddr; -- new value of rxfifo_raddr
s_rxfifo_wen <= r.rxfifo_write;
s_rxfifo_waddr <= r.rxfifo_waddr;
s_rxfifo_wdata <= r.rxfifo_wdata;
-- Drive control signals to TX fifo.
s_txfifo_raddr <= v.txfifo_raddr; -- new value of txfifo_raddr
s_txfifo_wen <= msto.txfifo_write;
s_txfifo_waddr <= r.txfifo_waddr;
s_txfifo_wdata <= msto.txfifo_wdata;
-- Drive inputs to spwlink.
linki.autostart <= r.ctl_autostart;
linki.linkstart <= r.ctl_linkstart;
linki.linkdis <= r.ctl_linkdis;
linki.rxroom <= r.rxroom;
linki.tick_in <= r.tick_in;
linki.ctrl_in <= "00";
linki.time_in <= r.time_in;
linki.txwrite <= (not r.txfifo_empty) and (not r.txdiscard);
linki.txflag <= s_txfifo_rdata(35-v_txfifo_bytepos);
linki.txdata <= s_txfifo_rdata(31-8*v_txfifo_bytepos downto 24-8*v_txfifo_bytepos);
-- Drive divcnt input to spwxmit.
if linko.running = '1' then
xmit_divcnt <= r.txdivcnt;
else
xmit_divcnt <= default_divcnt;
end if;
-- Drive inputs to AHB master.
msti.rxdma_start <= r.ctl_rxstart;
msti.txdma_start <= r.ctl_txstart;
msti.txdma_cancel <= r.ctl_txcancel;
msti.rxdesc_ptr <= r.rxdesc_ptr;
msti.txdesc_ptr <= r.txdesc_ptr;
msti.rxfifo_rdata <= s_rxfifo_rdata;
msti.rxfifo_empty <= r.rxfifo_empty;
msti.rxfifo_nxempty <= v.rxfifo_empty; -- new value of rxfifo_empty
msti.txfifo_nxfull <= r.txfifo_nxfull;
msti.txfifo_highw <= r.txfifo_highw;
-- Pass tick_out signal to output port.
tick_out <= linko.tick_out;
-- Drive APB output signals.
apbo.prdata <= v_prdata;
apbo.pirq <= v_irq;
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
-- Reset components.
ahbmst_rstn <= rstn and (not r.ctl_reset) and (not r.ctl_resetdma);
link_rst <= (not rstn) or r.ctl_reset;
xmit_rst <= not rstn;
-- Clear TX fifo on cancel request.
if r.ctl_txcancel = '1' then
v.txfifo_raddr := (others => '0');
v.txfifo_waddr := (others => '0');
v.txfifo_empty := '1';
v.txfifo_nxfull := '0';
v.txfifo_highw := '0';
v.txfifo_bytepos := "00";
v.txpacket := '0';
v.txdiscard := '0';
end if;
-- Reset registers.
if rstn = '0' or r.ctl_reset = '1' then
v := regs_reset;
end if;
-- Update registers.
rin <= v;
end process;
--
-- Update registers.
--
process (clk) is
begin
if rising_edge(clk) then
r <= rin;
end if;
end process;
end architecture spwamba_arch;
| gpl-3.0 | eba5c5828a67027e7c83f210a3871a19 | 0.504235 | 3.738576 | false | false | false | false |
EliasLuiz/TCC | Teste/MemoTableTLRUCounterWay.vhd | 1 | 10,505 | -- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: MemoTableTLRUCounter.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any LRUCounter files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
use work.Constants.all;
use work.DefTypes.all;
ENTITY MemoTableTLRUCounterWay IS
--ENTITY TraceMemory IS
PORT
(
Clock : IN STD_LOGIC := '1';
WAddress : IN STD_LOGIC_VECTOR (MemoTableTWayAddressLenght-1 DOWNTO 0);
WData : IN MemoTableTLRUCounterEntry;
--WData : IN STD_LOGIC_VECTOR (MemoTableTLRUCounterEntryWidth-1 DOWNTO 0);
WEnable : IN STD_LOGIC := '0';
RAddress : IN STD_LOGIC_VECTOR (MemoTableTWayAddressLenght-1 DOWNTO 0);
RData : OUT MemoTableTLRUCounterEntry
--RData : OUT STD_LOGIC_VECTOR (MemoTableTLRUCounterEntryWidth-1 DOWNTO 0)
);
END MemoTableTLRUCounterWay;
--END TraceMemory;
ARCHITECTURE SYN OF MemoTableTLRUCounterWay IS
--ARCHITECTURE SYN OF TraceMemory IS
SIGNAL RAuxVector : STD_LOGIC_VECTOR (MemoTableTLRUCounterEntryWidth-1 DOWNTO 0);
SIGNAL WAuxObject : MemoTableTLRUCounterEntry;
SIGNAL WAuxVector : STD_LOGIC_VECTOR (MemoTableTLRUCounterEntryWidth-1 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_b : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_mixed_ports : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a: IN STD_LOGIC_VECTOR (MemoTableTWayAddressLenght-1 DOWNTO 0);
clock0 : IN STD_LOGIC;
data_a : IN STD_LOGIC_VECTOR (MemoTableTLRUCounterEntryWidth-1 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (MemoTableTLRUCounterEntryWidth-1 DOWNTO 0);
wren_a : IN STD_LOGIC;
address_b: IN STD_LOGIC_VECTOR (MemoTableTWayAddressLenght-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
--RData <= RAuxVector;
RData <= StdLogicToLRUCounter(RAuxVector);
--WAuxVector <= WData;
WAuxObject <= WData;
WAuxVector <= LRUCounterToStdLogic(WAuxObject);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK0",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
intended_device_family => "Cyclone II",
lpm_type => "altsyncram",
numwords_a => MemoTableTWayLenght,
numwords_b => MemoTableTWayLenght,
operation_mode => "DUAL_PORT",
outdata_aclr_b => "NONE",
outdata_reg_b => "CLOCK0",
power_up_uninitialized => "FALSE",
read_during_write_mode_mixed_ports => "DONT_CARE",
widthad_a => MemoTableTWayAddressLenght,
widthad_b => MemoTableTWayAddressLenght,
width_a => MemoTableTLRUCounterEntryWidth,
width_b => MemoTableTLRUCounterEntryWidth,
width_byteena_a => 1
)
PORT MAP (
address_a => WAddress,
clock0 => Clock,
data_a => WAuxVector,
wren_a => WEnable,
address_b => RAddress,
q_b => RAuxVector
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_LRUCounter_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_LRUCounter_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "4096"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "1"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "1"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "64"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "64"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "64"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "64"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_LRUCounter_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_LRUCounter_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "64"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "64"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "6"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "6"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "64"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "64"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 64 0 INPUT NODEFVAL "data[MemoTableTLRUCounterEntryWidth-1..0]"
-- Retrieval info: USED_PORT: q 0 0 64 0 LRUCounter NODEFVAL "q[MemoTableTLRUCounterEntryWidth-1..0]"
-- Retrieval info: USED_PORT: rdaddress 0 0 6 0 INPUT NODEFVAL "rdaddress[MemoTableTWayAddressLenght-1..0]"
-- Retrieval info: USED_PORT: wraddress 0 0 6 0 INPUT NODEFVAL "wraddress[MemoTableTWayAddressLenght-1..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
-- Retrieval info: CONNECT: @address_a 0 0 6 0 wraddress 0 0 6 0
-- Retrieval info: CONNECT: @address_b 0 0 6 0 rdaddress 0 0 6 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 64 0 data 0 0 64 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 64 0 @q_b 0 0 64 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL MemoTableTLRUCounter.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL MemoTableTLRUCounter.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL MemoTableTLRUCounter.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL MemoTableTLRUCounter.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL MemoTableTLRUCounter_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL MemoTableTLRUCounter_syn.v TRUE
-- Retrieval info: LIB_FILE: altera_mf
| gpl-3.0 | a68543328be112727462a57b03672553 | 0.702142 | 3.386525 | false | false | false | false |
hoglet67/CoPro6502 | src/CoPro6502.vhd | 1 | 10,512 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity CoPro6502 is
generic (
UseT65Core : boolean := false;
UseJensCore : boolean := true;
UseAlanDCore : boolean := false
);
port (
-- GOP Signals
fastclk : in std_logic;
tp : out std_logic_vector(8 downto 2);
test : out std_logic_vector(6 downto 1);
sw : in std_logic_vector(2 downto 1);
fcs : out std_logic;
-- Tube signals (use 16 out of 22 DIL pins)
h_phi2 : in std_logic; -- 1,2,12,21,23 are global clocks
h_addr : in std_logic_vector(2 downto 0);
h_data : inout std_logic_vector(7 downto 0);
h_rdnw : in std_logic;
h_cs_b : in std_logic;
h_rst_b : in std_logic;
h_irq_b : inout std_logic;
-- Ram Signals
ram_cs : out std_logic;
ram_oe : out std_logic;
ram_wr : out std_logic;
ram_addr : out std_logic_vector (18 downto 0);
ram_data : inout std_logic_vector (7 downto 0)
);
end CoPro6502;
architecture BEHAVIORAL of CoPro6502 is
component tube
port(
h_addr : in std_logic_vector(2 downto 0);
h_cs_b : in std_logic;
h_data : inout std_logic_vector(7 downto 0);
h_phi2 : in std_logic;
h_rdnw : in std_logic;
h_rst_b : in std_logic;
h_irq_b : inout std_logic;
-- drq : out std_logic;
-- dackb : in std_logic;
p_addr : in std_logic_vector(2 downto 0);
p_cs_b : in std_logic;
p_data_in : in std_logic_vector(7 downto 0);
p_data_out : out std_logic_vector(7 downto 0);
p_rdnw : in std_logic;
p_phi2 : in std_logic;
p_rst_b : out std_logic;
p_nmi_b : inout std_logic;
p_irq_b : inout std_logic
);
end component;
-------------------------------------------------
-- clock and reset signals
-------------------------------------------------
signal clk_16M00 : std_logic;
signal phi0 : std_logic;
signal phi1 : std_logic;
signal phi2 : std_logic;
signal phi3 : std_logic;
signal cpu_clken : std_logic;
signal clken_counter : std_logic_vector (1 downto 0);
signal bootmode : std_logic;
signal RSTn : std_logic;
signal RSTn_sync : std_logic;
-------------------------------------------------
-- parasite signals
-------------------------------------------------
signal p_cs_b_en : std_logic;
signal p_cs_b : std_logic;
signal p_data_out : std_logic_vector (7 downto 0);
-------------------------------------------------
-- ram/rom signals
-------------------------------------------------
signal ram_cs_b : std_logic;
signal ram_oe_int : std_logic;
signal ram_wr_int : std_logic;
signal rom_cs_b : std_logic;
signal rom_data_out : std_logic_vector (7 downto 0);
-------------------------------------------------
-- cpu signals
-------------------------------------------------
signal debug_clk : std_logic;
signal cpu_R_W_n : std_logic;
signal cpu_addr : std_logic_vector (23 downto 0);
signal cpu_addr_us: unsigned (23 downto 0);
signal cpu_din : std_logic_vector (7 downto 0);
signal cpu_dout : std_logic_vector (7 downto 0);
signal cpu_dout_us: unsigned (7 downto 0);
signal cpu_IRQ_n : std_logic;
signal cpu_NMI_n : std_logic;
signal cpu_IRQ_n_sync : std_logic;
signal cpu_NMI_n_sync : std_logic;
signal sync : std_logic;
signal sample_reg : std_logic_vector(11 downto 0);
begin
---------------------------------------------------------------------
-- instantiated components
---------------------------------------------------------------------
inst_dcm_49_16 : entity work.dcm_49_16 port map (
CLKIN_IN => fastclk,
CLK0_OUT => clk_16M00,
CLK0_OUT1 => open,
CLK2X_OUT => open
);
inst_tuberom : entity work.tuberom_65c102 port map (
CLK => clk_16M00,
ADDR => cpu_addr(10 downto 0),
DATA => rom_data_out
);
GenT65Core: if UseT65Core generate
inst_T65 : entity work.T65 port map (
Mode => "01",
Abort_n => '1',
SO_n => '1',
Res_n => RSTn_sync,
Enable => cpu_clken,
Clk => clk_16M00,
Rdy => '1',
IRQ_n => cpu_IRQ_n_sync,
NMI_n => cpu_NMI_n_sync,
R_W_n => cpu_R_W_n,
Sync => sync,
A(23 downto 0) => cpu_addr,
DI(7 downto 0) => cpu_din,
DO(7 downto 0) => cpu_dout
);
-- For debugging only
debug_clk <= cpu_clken;
end generate;
GenJensCore: if UseJensCore generate
Inst_r65c02_tc: entity work.r65c02_tc PORT MAP(
clk_clk_i => phi0,
d_i => cpu_din,
irq_n_i => cpu_IRQ_n_sync,
nmi_n_i => cpu_NMI_n_sync,
rdy_i => '1',
rst_rst_n_i => RSTn_sync,
so_n_i => '1',
a_o => cpu_addr(15 downto 0),
d_o => cpu_dout,
rd_o => open,
sync_o => sync,
wr_n_o => cpu_R_W_n,
wr_o => open
);
-- For debugging only
debug_clk <= phi0;
end generate;
GenAlanDCore: if UseAlanDCore generate
inst_r65c02: entity work.r65c02 port map(
reset => RSTn_sync,
clk => clk_16M00,
enable => cpu_clken,
nmi_n => cpu_NMI_n_sync,
irq_n => cpu_IRQ_n_sync,
di => unsigned(cpu_din),
do => cpu_dout_us,
addr => cpu_addr_us(15 downto 0),
nwe => cpu_R_W_n,
sync => sync,
sync_irq => open
);
cpu_dout <= std_logic_vector(cpu_dout_us);
cpu_addr <= std_logic_vector(cpu_addr_us);
-- For debugging only
debug_clk <= cpu_clken;
end generate;
inst_tube: tube port map (
h_addr => h_addr,
h_cs_b => h_cs_b,
h_data => h_data,
h_phi2 => h_phi2,
h_rdnw => h_rdnw,
h_rst_b => h_rst_b,
h_irq_b => h_irq_b,
p_addr => cpu_addr(2 downto 0),
p_cs_b => p_cs_b_en,
p_data_in => cpu_dout,
p_data_out => p_data_out,
p_rdnw => cpu_R_W_n,
p_phi2 => clk_16M00,
p_rst_b => RSTn,
p_nmi_b => cpu_NMI_n,
p_irq_b => cpu_IRQ_n
);
p_cs_b_en <= not((not p_cs_b) and cpu_clken);
p_cs_b <= '0' when cpu_addr(15 downto 3) = "1111111011111" else '1';
rom_cs_b <= '0' when cpu_addr(15 downto 11) = "11111" and cpu_R_W_n = '1' and bootmode = '1' else '1';
ram_cs_b <= '0' when p_cs_b = '1' and rom_cs_b = '1' else '1';
cpu_din <=
p_data_out when p_cs_b = '0' else
rom_data_out when rom_cs_b = '0' else
ram_data when ram_cs_b = '0' else
x"f1";
ram_cs <= ram_cs_b;
ram_oe_int <= not ((not ram_cs_b) and cpu_R_W_n);
ram_oe <= ram_oe_int;
ram_wr_int <= not ((not ram_cs_b) and (not cpu_R_W_n) and phi1);
ram_wr <= ram_wr_int;
ram_addr <= "000" & cpu_addr(15 downto 0);
ram_data <= cpu_dout when cpu_R_W_n = '0' else "ZZZZZZZZ";
sample_gen : process(debug_clk)
begin
if rising_edge(debug_clk) then
if cpu_R_W_n = '0' then
sample_reg(7 downto 0) <= cpu_dout;
else
sample_reg(7 downto 0) <= cpu_din;
end if;
sample_reg(8) <= cpu_R_W_n;
sample_reg(9) <= sync;
sample_reg(10) <= RSTn_sync; -- cpu_NMI_n_sync;
sample_reg(11) <= cpu_IRQ_n_sync;
end if;
end process;
fcs <= '1';
test(6) <= debug_clk;
test(5) <= sample_reg(11);
test(4) <= sample_reg(10);
test(3) <= sample_reg(9);
test(2) <= sample_reg(8);
test(1) <= sample_reg(7);
tp(8) <= sample_reg(6);
tp(7) <= sample_reg(5);
tp(6) <= sample_reg(4);
tp(5) <= sample_reg(3);
tp(4) <= sample_reg(2);
tp(3) <= sample_reg(1);
tp(2) <= sample_reg(0);
--------------------------------------------------------
-- boot mode generator
--------------------------------------------------------
boot_gen : process(clk_16M00, RSTn_sync)
begin
if RSTn_sync = '0' then
bootmode <= '1';
elsif rising_edge(clk_16M00) then
if p_cs_b = '0' then
bootmode <= '0';
end if;
end if;
end process;
sync_gen : process(clk_16M00, RSTn_sync)
begin
if RSTn_sync = '0' then
cpu_NMI_n_sync <= '1';
cpu_IRQ_n_sync <= '1';
elsif rising_edge(clk_16M00) then
if (cpu_clken = '1') then
cpu_NMI_n_sync <= cpu_NMI_n;
cpu_IRQ_n_sync <= cpu_IRQ_n;
end if;
end if;
end process;
--------------------------------------------------------
-- clock enable generator
-- 4MHz
-- cpu_clken active on cycle 0, 4, 8, 12
-- address/data changes on cycle 1, 5, 9, 13
-- phi0 active on cycle 1..2
-- phi1 active on cycle 2..3
-- phi2 active on cycle 3..0
-- phi3 active on cycle 0..1
--------------------------------------------------------
clk_gen : process(clk_16M00, RSTn)
begin
if rising_edge(clk_16M00) then
clken_counter <= clken_counter + 1;
cpu_clken <= clken_counter(0) and clken_counter(1);
phi0 <= not clken_counter(1);
phi1 <= phi0;
phi2 <= phi1;
phi3 <= phi2;
end if;
RSTn_sync <= RSTn;
end process;
end BEHAVIORAL;
| gpl-3.0 | a7c01d8ed639093e138e8eb2644df8d1 | 0.435407 | 3.415205 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/maps/lvds_combo.vhd | 1 | 3,925 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: lvds_combo.vhd
-- File: lvds_combo.vhd.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Differential input/output pads with IREF/OREF logic wrapper
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.allpads.all;
entity lvds_combo is
generic (tech : integer := 0; voltage : integer := 0; width : integer := 1;
oepol : integer := 0; term : integer := 0);
port (odpadp, odpadn, ospadp, ospadn : out std_logic_vector(0 to width-1);
odval, osval, en : in std_logic_vector(0 to width-1);
idpadp, idpadn, ispadp, ispadn : in std_logic_vector(0 to width-1);
idval, isval : out std_logic_vector(0 to width-1);
powerdown : in std_logic_vector(0 to width-1) := (others => '0');
powerdownrx : in std_logic_vector(0 to width-1) := (others => '0');
lvdsref : in std_logic := '1';
lvdsrefo : out std_logic
);
end ;
architecture rtl of lvds_combo is
signal gnd : std_ulogic;
signal oen : std_logic_vector(0 to width-1);
constant level : integer := lvds;
begin
gnd <= '0';
gen0 : if has_ds_combo(tech) = 0 generate
swloop : for i in 0 to width-1 generate
od0 : outpad_ds generic map (tech, level, voltage, oepol) port map (odpadp(i), odpadn(i), odval(i), en(i));
os0 : outpad_ds generic map (tech, level, voltage, oepol) port map (ospadp(i), ospadn(i), osval(i), en(i));
id0 : inpad_ds generic map (tech, level, voltage) port map (idpadp(i), idpadn(i), idval(i));
is0 : inpad_ds generic map (tech, level, voltage) port map (ispadp(i), ispadn(i), isval(i));
end generate;
end generate;
combo : if has_ds_combo(tech) /= 0 generate
oen <= not en when oepol /= padoen_polarity(tech) else en;
ut025 : if tech = ut25 generate
u0: ut025crh_lvds_combo generic map (voltage, width)
port map (odpadp, odpadn, ospadp, ospadn, odval, osval, oen,
idpadp, idpadn, ispadp, ispadn, idval, isval);
end generate;
ut13 : if tech = ut130 generate
u0: ut130hbd_lvds_combo generic map (voltage, width)
port map (odpadp, odpadn, ospadp, ospadn, odval, osval, oen,
idpadp, idpadn, ispadp, ispadn, idval, isval, powerdown, powerdownrx, lvdsrefo);
end generate;
um : if tech = umc generate
u0: umc_lvds_combo generic map (voltage, width)
port map (odpadp, odpadn, ospadp, ospadn, odval, osval, oen,
idpadp, idpadn, ispadp, ispadn, idval, isval, lvdsref);
end generate;
rhu : if tech = rhumc generate
u0: rhumc_lvds_combo generic map (voltage, width)
port map (odpadp, odpadn, ospadp, ospadn, odval, osval, oen,
idpadp, idpadn, ispadp, ispadn, idval, isval, powerdown, powerdownrx, lvdsrefo);
end generate;
end generate;
end;
| gpl-3.0 | c5776b931172d9a04c7a1f2c5dd86599 | 0.633885 | 3.69934 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/inferred/ddr_phy_inferred.vhd | 1 | 16,495 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: generic_ddr_phy
-- File: ddr_phy_inferred.vhd
-- Author: Nils-Johan Wessman - Gaisler Research
-- Modified: Magnus Hjorth - Aeroflex Gaisler
-- Description: Generic DDR PHY (simulation only)
------------------------------------------------------------------------------
--###################################################################################
-- Generic DDR1 PHY
--###################################################################################
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.stdlib.all;
entity generic_ddr_phy_wo_pads is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0; mobile : integer := 0;
abits: integer := 14; nclk: integer := 3; ncs: integer := 2);
port(
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clk0r : in std_ulogic;
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb: in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (abits-1 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
ck : in std_logic_vector(nclk-1 downto 0);
moben : in std_logic -- Mobile DDR enable
);
end;
architecture rtl of generic_ddr_phy_wo_pads is
component sim_pll
generic (
clkmul: integer := 1;
clkdiv1: integer := 1;
clkphase1: integer := 0;
clkdiv2: integer := 1;
clkphase2: integer := 0;
clkdiv3: integer := 1;
clkphase3: integer := 0;
clkdiv4: integer := 1;
clkphase4: integer := 0;
minfreq: integer := 0;
maxfreq: integer := 10000000
);
port (
i: in std_logic;
o1: out std_logic;
o2: out std_logic;
o3: out std_logic;
o4: out std_logic;
lock: out std_logic;
rst: in std_logic
);
end component;
constant freq_khz: integer := (1000*MHz*clk_mul)/(clk_div);
constant freq_mhz: integer := freq_khz / 1000;
constant td90: time := 250 us * (1.0 / real(freq_khz));
signal vcc, gnd : std_logic; -- VCC and GND
signal clk0, clk90r, clk180r, clk270r : std_ulogic;
signal lockl,vlockl,locked: std_ulogic;
signal dqs90,dqs90n: std_logic_vector(dbits/8-1 downto 0);
signal ckl: std_logic_vector(nclk-1 downto 0);
signal ckel: std_logic_vector(ncs-1 downto 0);
begin
vcc <= '1'; gnd <= '0';
-----------------------------------------------------------------------------------
-- Clock generation (Only for simulation)
-----------------------------------------------------------------------------------
-- Phase shifted clocks
--pragma translate_off
-- To avoid jitter problems when using ddr without sync regs we shift
-- 10 degrees extra.
pll0: sim_pll
generic map (
clkmul => clk_mul,
clkdiv1 => clk_div,
clkphase1 => 0-10+360,
clkdiv2 => clk_div,
clkphase2 => 90-10,
clkdiv3 => clk_div,
clkphase3 => 180-10,
clkdiv4 => clk_div,
clkphase4 => 270-10,
minfreq => MHz*1000,
maxfreq => MHz*1000
)
port map (
i => clk,
o1 => clk0,
o2 => clk90r,
o3 => clk180r,
o4 => clk270r,
lock => lockl,
rst => rst);
--pragma translate_on
-- Clock to DDR controller
clkout <= clk0;
ddr_clk_fb_out <= '0';
-----------------------------------------------------------------------------------
-- Lock delay
-----------------------------------------------------------------------------------
rdel : if rstdelay /= 0 generate
rcnt : process (clk0r, lockl, rst)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*FREQ_MHZ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' or rst='0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-----------------------------------------------------------------------------
-- DQS shifting
-----------------------------------------------------------------------------
-- pragma translate_off
dqs90 <= transport ddr_dqs_in after td90;
dqs90n <= not dqs90;
-- pragma translate_on
-----------------------------------------------------------------------------
-- Data path
-----------------------------------------------------------------------------
-- For mobile SDRAM, force Cke high during reset and reset-delay,
-- For regular SDRAM, force Cke low
-- also disable outgoing clock until we have achieved PLL lock
mobgen: if mobile > 1 generate
ckel <= cke or (cke'range => not locked);
end generate;
nmobgen: if mobile < 2 generate
ckel <= cke and (cke'range => locked);
end generate;
ckl <= ck and (ck'range => lockl);
dp0: ddrphy_datapath
generic map (
regtech => inferred, dbits => dbits, abits => abits,
bankbits => 2, ncs => ncs, nclk => nclk,
resync => 2 )
port map (
clk0 => clk0r,
clk90 => clk90r,
clk180 => clk180r,
clk270 => clk270r,
clkresync => gnd,
ddr_clk => ddr_clk,
ddr_clkb => ddr_clkb,
ddr_dq_in => ddr_dq_in,
ddr_dq_out => ddr_dq_out,
ddr_dq_oen => ddr_dq_oen,
ddr_dqs_in90 => dqs90,
ddr_dqs_in90n => dqs90n,
ddr_dqs_out => ddr_dqs_out,
ddr_dqs_oen => ddr_dqs_oen,
ddr_cke => ddr_cke,
ddr_csb => ddr_csb,
ddr_web => ddr_web,
ddr_rasb => ddr_rasb,
ddr_casb => ddr_casb,
ddr_ad => ddr_ad,
ddr_ba => ddr_ba,
ddr_dm => ddr_dm,
ddr_odt => open,
dqin => dqin,
dqout => dqout,
addr => addr,
ba => ba,
dm => dm,
oen => oen,
rasn => rasn,
casn => casn,
wen => wen,
csn => csn,
cke => ckel,
odt => (others => '0'),
dqs_en => dqs,
dqs_oen => dqsoen,
ddrclk_en => ckl
);
end;
--###################################################################################
-- Generic DDR2 PHY
--###################################################################################
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.stdlib.all;
entity generic_ddr2_phy_wo_pads is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0;
eightbanks: integer := 0; abits: integer := 14;
cben: integer := 0; chkbits: integer := 8;
nclk: integer := 3; ncs: integer := 2);
port(
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clk0r : in std_ulogic; -- system clock returned
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0); -- ddr odt
addr : in std_logic_vector (abits-1 downto 0); -- data mask
ba : in std_logic_vector (2 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
ck : in std_logic_vector(2 downto 0);
odt : in std_logic_vector(1 downto 0)
);
end;
architecture rtl of generic_ddr2_phy_wo_pads is
component sim_pll
generic (
clkmul: integer := 1;
clkdiv1: integer := 1;
clkphase1: integer := 0;
clkdiv2: integer := 1;
clkphase2: integer := 0;
clkdiv3: integer := 1;
clkphase3: integer := 0;
clkdiv4: integer := 1;
clkphase4: integer := 0;
minfreq: integer := 0;
maxfreq: integer := 10000000
);
port (
i: in std_logic;
o1: out std_logic;
o2: out std_logic;
o3: out std_logic;
o4: out std_logic;
lock: out std_logic;
rst: in std_logic
);
end component;
constant freq_khz: integer := (1000*MHz*clk_mul)/(clk_div);
constant freq_mhz: integer := freq_khz / 1000;
constant td90: time := 250 us * (1.0 / real(freq_khz));
signal vcc, gnd : std_logic; -- VCC and GND
signal clk0, clk90r, clk180r, clk270r : std_ulogic;
signal lockl,vlockl,locked: std_ulogic;
signal dqs90,dqs90n: std_logic_vector(dbits/8-1 downto 0);
begin
vcc <= '1'; gnd <= '0';
-----------------------------------------------------------------------------------
-- Clock generation (Only for simulation)
-----------------------------------------------------------------------------------
-- Phase shifted clocks
--pragma translate_off
-- To avoid jitter problems when using ddr2 without sync regs we shift
-- 10 degrees extra.
pll0: sim_pll
generic map (
clkmul => clk_mul,
clkdiv1 => clk_div,
clkphase1 => 0-10+360,
clkdiv2 => clk_div,
clkphase2 => 90-10,
clkdiv3 => clk_div,
clkphase3 => 180-10,
clkdiv4 => clk_div,
clkphase4 => 270-10,
minfreq => MHz*1000,
maxfreq => MHz*1000
)
port map (
i => clk,
o1 => clk0,
o2 => clk90r,
o3 => clk180r,
o4 => clk270r,
lock => lockl,
rst => rst);
--pragma translate_on
-- Clock to DDR controller
clkout <= clk0;
ddr_clk_fb_out <= '0';
-----------------------------------------------------------------------------------
-- Lock delay
-----------------------------------------------------------------------------------
rdel : if rstdelay /= 0 generate
rcnt : process (clk0r, lockl)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*FREQ_MHZ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-----------------------------------------------------------------------------
-- DQS shifting
-----------------------------------------------------------------------------
-- pragma translate_off
dqs90 <= transport ddr_dqs_in after td90;
dqs90n <= not dqs90;
-- pragma translate_on
-----------------------------------------------------------------------------
-- Data path
-----------------------------------------------------------------------------
dp0: ddrphy_datapath
generic map (
regtech => inferred, dbits => dbits, abits => abits,
bankbits => 2+EIGHTBANKS, ncs => ncs, nclk => nclk,
resync => 0 )
port map (
clk0 => clk0r,
clk90 => clk90r,
clk180 => clk180r,
clk270 => clk270r,
clkresync => gnd,
ddr_clk => ddr_clk,
ddr_clkb => ddr_clkb,
ddr_dq_in => ddr_dq_in,
ddr_dq_out => ddr_dq_out,
ddr_dq_oen => ddr_dq_oen,
ddr_dqs_in90 => dqs90,
ddr_dqs_in90n => dqs90n,
ddr_dqs_out => ddr_dqs_out,
ddr_dqs_oen => ddr_dqs_oen,
ddr_cke => ddr_cke,
ddr_csb => ddr_csb,
ddr_web => ddr_web,
ddr_rasb => ddr_rasb,
ddr_casb => ddr_casb,
ddr_ad => ddr_ad,
ddr_ba => ddr_ba,
ddr_dm => ddr_dm,
ddr_odt => ddr_odt,
dqin => dqin,
dqout => dqout,
addr => addr,
ba => ba(1+eightbanks downto 0),
dm => dm,
oen => oen,
rasn => rasn,
casn => casn,
wen => wen,
csn => csn,
cke => cke,
odt => odt,
dqs_en => dqs,
dqs_oen => dqsoen,
ddrclk_en => ck(nclk-1 downto 0)
);
end;
| gpl-3.0 | 4ec0b63727b4e4e6acd594aa9a8c95d1 | 0.500818 | 3.7319 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/greth/greth.vhd | 1 | 12,447 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: greth
-- File: greth.vhd
-- Author: Marko Isomaki
-- Description: Ethernet Media Access Controller with Ethernet Debug
-- Communication Link
------------------------------------------------------------------------------
library ieee;
library grlib;
library gaisler;
use ieee.std_logic_1164.all;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use gaisler.net.all;
use gaisler.ethernet_mac.all;
library eth;
use eth.ethcomp.all;
entity greth is
generic(
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 512 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
rmii : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 2 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
maxsize : integer := 1518;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ethi : in eth_in_type;
etho : out eth_out_type
);
end entity;
architecture rtl of greth is
function getfifosize(edcl, fifosize, ebufsize : in integer) return integer is
begin
if (edcl /= 0) and (ebufsize > fifosize) then
return ebufsize;
else
return fifosize;
end if;
end function;
constant fabits : integer := log2(fifosize);
type szvct is array (0 to 6) of integer;
constant ebuf : szvct := (64, 128, 128, 256, 256, 256, 256);
constant eabits : integer := log2(edclbufsz) + 8;
constant bufsize : std_logic_vector(2 downto 0) :=
conv_std_logic_vector(log2(edclbufsz), 3);
constant ebufsize : integer := ebuf(log2(edclbufsz));
constant txfifosize : integer := getfifosize(edcl, fifosize, ebufsize);
constant txfabits : integer := log2(txfifosize);
constant REVISION : amba_version_type := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_ETHMAC, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_ETHMAC, 0, revision, 0),
others => zero32);
constant ehconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_EDCLMST, 0, REVISION, 0),
others => zero32);
signal irq : std_ulogic;
--rx ahb fifo
signal rxrenable : std_ulogic;
signal rxraddress : std_logic_vector(10 downto 0);
signal rxwrite : std_ulogic;
signal rxwdata : std_logic_vector(31 downto 0);
signal rxwaddress : std_logic_vector(10 downto 0);
signal rxrdata : std_logic_vector(31 downto 0);
--tx ahb fifo
signal txrenable : std_ulogic;
signal txraddress : std_logic_vector(10 downto 0);
signal txwrite : std_ulogic;
signal txwdata : std_logic_vector(31 downto 0);
signal txwaddress : std_logic_vector(10 downto 0);
signal txrdata : std_logic_vector(31 downto 0);
--edcl buf
signal erenable : std_ulogic;
signal eraddress : std_logic_vector(15 downto 0);
signal ewritem : std_ulogic;
signal ewritel : std_ulogic;
signal ewaddressm : std_logic_vector(15 downto 0);
signal ewaddressl : std_logic_vector(15 downto 0);
signal ewdata : std_logic_vector(31 downto 0);
signal erdata : std_logic_vector(31 downto 0);
signal lmdio_oe : std_ulogic;
-- Fix for wider bus
signal hwdata : std_logic_vector(31 downto 0);
signal hrdata : std_logic_vector(31 downto 0);
begin
ethc0: grethc
generic map(
ifg_gap => ifg_gap,
attempt_limit => attempt_limit,
backoff_limit => backoff_limit,
mdcscaler => mdcscaler,
enable_mdio => enable_mdio,
fifosize => fifosize,
nsync => nsync,
edcl => edcl,
edclbufsz => edclbufsz,
macaddrh => macaddrh,
macaddrl => macaddrl,
ipaddrh => ipaddrh,
ipaddrl => ipaddrl,
phyrstadr => phyrstadr,
rmii => rmii,
oepol => oepol,
scanen => scanen,
mdint_pol => mdint_pol,
enable_mdint => enable_mdint,
multicast => multicast,
edclsepahbg => 0,
ramdebug => ramdebug,
mdiohold => mdiohold,
maxsize => maxsize,
gmiimode => gmiimode
)
port map(
rst => rst,
clk => clk,
--ahb mst in
hgrant => ahbmi.hgrant(hindex),
hready => ahbmi.hready,
hresp => ahbmi.hresp,
hrdata => hrdata,
--ahb mst out
hbusreq => ahbmo.hbusreq,
hlock => ahbmo.hlock,
htrans => ahbmo.htrans,
haddr => ahbmo.haddr,
hwrite => ahbmo.hwrite,
hsize => ahbmo.hsize,
hburst => ahbmo.hburst,
hprot => ahbmo.hprot,
hwdata => hwdata,
--edcl ahb mst in
ehgrant => ahbmi.hgrant(hindex),
ehready => ahbmi.hready,
ehresp => ahbmi.hresp,
ehrdata => hrdata,
--edcl ahb mst out
ehbusreq => open,
ehlock => open,
ehtrans => open,
ehaddr => open,
ehwrite => open,
ehsize => open,
ehburst => open,
ehprot => open,
ehwdata => open,
--apb slv in
psel => apbi.psel(pindex),
penable => apbi.penable,
paddr => apbi.paddr,
pwrite => apbi.pwrite,
pwdata => apbi.pwdata,
--apb slv out
prdata => apbo.prdata,
--irq
irq => irq,
--rx ahb fifo
rxrenable => rxrenable,
rxraddress => rxraddress,
rxwrite => rxwrite,
rxwdata => rxwdata,
rxwaddress => rxwaddress,
rxrdata => rxrdata,
--tx ahb fifo
txrenable => txrenable,
txraddress => txraddress,
txwrite => txwrite,
txwdata => txwdata,
txwaddress => txwaddress,
txrdata => txrdata,
--edcl buf
erenable => erenable,
eraddress => eraddress,
ewritem => ewritem,
ewritel => ewritel,
ewaddressm => ewaddressm,
ewaddressl => ewaddressl,
ewdata => ewdata,
erdata => erdata,
--ethernet input signals
rmii_clk => ethi.rmii_clk,
tx_clk => ethi.tx_clk,
tx_dv => ethi.tx_dv,
rx_clk => ethi.rx_clk,
rxd => ethi.rxd(3 downto 0),
rx_dv => ethi.rx_dv,
rx_er => ethi.rx_er,
rx_col => ethi.rx_col,
rx_crs => ethi.rx_crs,
rx_en => ethi.rx_en,
mdio_i => ethi.mdio_i,
phyrstaddr => ethi.phyrstaddr,
mdint => ethi.mdint,
--ethernet output signals
reset => etho.reset,
txd => etho.txd(3 downto 0),
tx_en => etho.tx_en,
tx_er => etho.tx_er,
mdc => etho.mdc,
mdio_o => etho.mdio_o,
mdio_oe => lmdio_oe,
--scantest
testrst => ahbmi.testrst,
testen => ahbmi.testen,
testoen => ahbmi.testoen,
edcladdr => ethi.edcladdr,
edclsepahb => ethi.edclsepahb,
edcldisable => ethi.edcldisable,
speed => etho.speed);
etho.txd(7 downto 4) <= "0000";
etho.mdio_oe <= ahbmi.testoen when (scanen = 1) and (ahbmi.testen = '1')
else lmdio_oe;
etho.gbit <= '0';
etho.tx_clk <= '0'; -- driven in rgmii component
irqdrv : process(irq)
begin
apbo.pirq <= (others => '0');
apbo.pirq(pirq) <= irq;
end process;
hrdata <= ahbreadword(ahbmi.hrdata);
ahbmo.hwdata <= ahbdrivedata(hwdata);
ahbmo.hconfig <= hconfig;
ahbmo.hindex <= hindex;
ahbmo.hirq <= (others => '0');
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
-------------------------------------------------------------------------------
-- FIFOS ----------------------------------------------------------------------
-------------------------------------------------------------------------------
nft : if ft = 0 generate
tx_fifo0 : syncram_2p generic map(tech => memtech, abits => txfabits,
dbits => 32, sepclk => 0)
port map(clk, txrenable, txraddress(txfabits-1 downto 0), txrdata, clk,
txwrite, txwaddress(txfabits-1 downto 0), txwdata);
rx_fifo0 : syncram_2p generic map(tech => memtech, abits => fabits,
dbits => 32, sepclk => 0)
port map(clk, rxrenable, rxraddress(fabits-1 downto 0), rxrdata, clk,
rxwrite, rxwaddress(fabits-1 downto 0), rxwdata);
end generate;
-------------------------------------------------------------------------------
-- EDCL buffer ram ------------------------------------------------------------
-------------------------------------------------------------------------------
edclramnft : if (edcl /= 0) and (edclft = 0) generate
r0 : syncram_2p generic map (memtech, eabits, 16) port map(
clk, erenable, eraddress(eabits-1 downto 0), erdata(31 downto 16), clk,
ewritem, ewaddressm(eabits-1 downto 0), ewdata(31 downto 16));
r1 : syncram_2p generic map (memtech, eabits, 16) port map(
clk, erenable, eraddress(eabits-1 downto 0), erdata(15 downto 0), clk,
ewritel, ewaddressl(eabits-1 downto 0), ewdata(15 downto 0));
end generate;
-- pragma translate_off
bootmsg : report_version
generic map (
"greth" & tost(hindex) & ": 10/100 Mbit Ethernet MAC rev " & tost(REVISION)
& tost(hindex) & ", EDCL " & tost(edcl) & ", buffer " &
tost(edclbufsz) & " kbyte " & tost(txfifosize) & " txfifo," &
" irq " & tost(pirq)
);
-- pragma translate_on
end architecture;
| gpl-3.0 | 98c1cac3ce6c55eaa1e87ffacd6e8a69 | 0.521571 | 4.165663 | false | false | false | false |
GLADICOS/SPACEWIRESYSTEMC | rtl/RTL_SL/spwrecvfront_generic.vhd | 2 | 2,592 | --
-- Front-end for SpaceWire Receiver
--
-- This entity samples the input signals DataIn and StrobeIn to detect
-- valid bit transitions. Received bits are handed to the application.
--
-- Inputs are sampled on the rising edge of the system clock, therefore
-- the maximum bitrate of the incoming signal must be significantly lower
-- than system clock frequency.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity spwrecvfront_generic is
port (
-- System clock.
clk: in std_logic;
-- High to enable receiver; low to disable and reset receiver.
rxen: in std_logic;
-- High if there has been recent activity on the input lines.
inact: out std_logic;
-- High if inbits contains a valid received bit.
-- If inbvalid='1', the application must sample inbits on
-- the rising edge of clk.
inbvalid: out std_logic;
-- Received bit
inbits: out std_logic_vector(0 downto 0);
-- Data In signal from SpaceWire bus.
spw_di: in std_logic;
-- Strobe In signal from SpaceWire bus.
spw_si: in std_logic );
end entity spwrecvfront_generic;
architecture spwrecvfront_arch of spwrecvfront_generic is
-- input flip-flops
signal s_spwdi1: std_ulogic;
signal s_spwsi1: std_ulogic;
signal s_spwdi2: std_ulogic;
signal s_spwsi2: std_ulogic;
-- data/strobe decoding
signal s_spwsi3: std_ulogic;
-- output registers
signal s_inbvalid: std_ulogic;
signal s_inbit: std_ulogic;
begin
-- drive outputs
inact <= s_inbvalid;
inbvalid <= s_inbvalid;
inbits(0) <= s_inbit;
-- synchronous process
process (clk) is
begin
if rising_edge(clk) then
-- sample input signal
s_spwdi1 <= spw_di;
s_spwsi1 <= spw_si;
-- more flip-flops for safe synchronization
s_spwdi2 <= s_spwdi1;
s_spwsi2 <= s_spwsi1;
-- keep strobe signal for data/strobe decoding
s_spwsi3 <= s_spwsi2;
-- keep data bit for data/strobe decoding
s_inbit <= s_spwdi2;
if rxen = '1' then
-- data/strobe decoding
s_inbvalid <= s_spwdi2 xor s_spwsi2 xor s_inbit xor s_spwsi3;
else
-- reset receiver
s_inbvalid <= '0';
end if;
end if;
end process;
end architecture spwrecvfront_arch;
| gpl-3.0 | 8b31954f55cb182b4c0d8fe1e49258dc | 0.582176 | 3.778426 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/maps/outpad_ds.vhd | 1 | 3,797 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: outpad_ds
-- File: outpad_ds.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Differential output pad with technology wrapper
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.allpads.all;
entity outpad_ds is
generic (tech : integer := 0; level : integer := lvds;
voltage : integer := x33v; oepol : integer := 0; slew : integer := 0);
port (padp, padn : out std_ulogic; i, en : in std_ulogic);
end;
architecture rtl of outpad_ds is
signal gnd, oen : std_ulogic;
begin
gnd <= '0';
oen <= not en when oepol /= padoen_polarity(tech) else en;
gen0 : if has_ds_pads(tech) = 0 generate
padp <= i
-- pragma translate_off
after 1 ns
-- pragma translate_on
;
padn <= not i
-- pragma translate_off
after 1 ns
-- pragma translate_on
;
end generate;
xcv : if (is_unisim(tech) = 1) generate
u0 : unisim_outpad_ds generic map (level, slew, voltage) port map (padp, padn, i);
end generate;
axc : if (tech = axcel) or (tech = axdsp) generate
u0 : axcel_outpad_ds generic map (level, voltage) port map (padp, padn, i);
end generate;
pa3 : if (tech = apa3) generate
u0 : apa3_outpad_ds generic map (level) port map (padp, padn, i);
end generate;
igl2 : if (tech = igloo2) or (tech = rtg4) generate
u0 : igloo2_outpad_ds port map (padp, padn, i);
end generate;
pa3e : if (tech = apa3e) generate
u0 : apa3e_outpad_ds generic map (level) port map (padp, padn, i);
end generate;
pa3l : if (tech = apa3l) generate
u0 : apa3l_outpad_ds generic map (level) port map (padp, padn, i);
end generate;
fus : if (tech = actfus) generate
u0 : fusion_outpad_ds generic map (level) port map (padp, padn, i);
end generate;
rht : if (tech = rhlib18t) generate
u0 : rh_lib18t_outpad_ds port map (padp, padn, i, oen);
end generate;
n2x : if (tech = easic45) generate
u0 : n2x_outpad_ds generic map (level, voltage) port map (padp, padn, i);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity outpad_dsv is
generic (tech : integer := 0; level : integer := x33v;
voltage : integer := lvds; width : integer := 1;
oepol : integer := 0; slew : integer := 0);
port (
padp : out std_logic_vector(width-1 downto 0);
padn : out std_logic_vector(width-1 downto 0);
i, en: in std_logic_vector(width-1 downto 0));
end;
architecture rtl of outpad_dsv is
begin
v : for j in width-1 downto 0 generate
u0 : outpad_ds generic map (tech, level, voltage, oepol, slew)
port map (padp(j), padn(j), i(j), en(j));
end generate;
end;
| gpl-3.0 | fdbb7f71af9f53219d47270304a60af4 | 0.636819 | 3.48989 | false | false | false | false |
GLADICOS/SPACEWIRESYSTEMC | rtl/RTL_VJ/SpaceWireCODECIPTimer.vhdl | 1 | 4,428 | ------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) <2013> <Shimafuji Electric Inc., Osaka University, JAXA>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity SpaceWireCODECIPTimer is
generic (
gTimer6p4usValue : integer := 640;
gTimer12p8usValue : integer := 1280
);
port (
clock : in std_logic;
reset : in std_logic;
timer6p4usReset : in std_logic;
timer12p8usStart : in std_logic;
after6p4us : out std_logic;
after12p8us : out std_logic
);
end SpaceWireCODECIPTimer;
architecture Behavioral of SpaceWireCODECIPTimer is
signal iTimerState12p8us : std_logic;
signal iTimerCount6p4us : std_logic_vector (9 downto 0);
signal iTimerCount12p8us : std_logic_vector (10 downto 0);
signal iAfter6p4us : std_logic;
signal iAfter12p8us : std_logic;
begin
after6p4us <= iAfter6p4us;
after12p8us <= iAfter12p8us;
----------------------------------------------------------------------
-- ECSS-E-ST-50-12C 8.4.7 Timer.
-- The timer provides the After 6.4 us and After 12.8 us timeouts used
-- in link initialization.
----------------------------------------------------------------------
----------------------------------------------------------------------
-- After 6.4us.
----------------------------------------------------------------------
controlTimer64 : process (clock, reset, timer6p4usReset)
begin
if (reset = '1' or timer6p4usReset = '1') then
iTimerCount6p4us <= (others => '0');
iAfter6p4us <= '0';
elsif (clock'event and clock = '1') then
if (iTimerCount6p4us < gTimer6p4usValue) then
iTimerCount6p4us <= iTimerCount6p4us + 1;
iAfter6p4us <= '0';
else
iTimerCount6p4us <= (others => '0');
iAfter6p4us <= '1';
end if;
end if;
end process;
----------------------------------------------------------------------
-- After 12.8us.
----------------------------------------------------------------------
controlTimer128 : process (clock, reset, timer12p8usStart, timer6p4usReset)
begin
if (reset = '1' or timer6p4usReset = '1') then
iTimerState12p8us <= '0';
iTimerCount12p8us <= (others => '0');
iAfter12p8us <= '0';
elsif (clock'event and clock = '1') then
if (iTimerState12p8us = '0') then
iAfter12p8us <= '0';
if (timer12p8usStart = '1') then
iTimerState12p8us <= '1';
end if;
else
if (iTimerCount12p8us < gTimer12p8usValue) then
iTimerCount12p8us <= iTimerCount12p8us + 1;
iAfter12p8us <= '0';
else
iTimerCount12p8us <= (others => '0');
iTimerState12p8us <= '0';
iAfter12p8us <= '1';
end if;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | 4c70cdea049295028fc24be1c5a04fd8 | 0.528004 | 4.111421 | false | false | false | false |
EliasLuiz/TCC | Leon3/boards/terasic-de4/uniphy_333.vhd | 1 | 40,587 | -- megafunction wizard: %DDR2 SDRAM Controller with UniPHY v15.0%
-- GENERATION: XML
-- uniphy.vhd
-- Generated using ACDS version 15.0 145
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity uniphy is
port (
pll_ref_clk : in std_logic := '0'; -- pll_ref_clk.clk
global_reset_n : in std_logic := '0'; -- global_reset.reset_n
soft_reset_n : in std_logic := '0'; -- soft_reset.reset_n
afi_clk : out std_logic; -- afi_clk.clk
afi_half_clk : out std_logic; -- afi_half_clk.clk
afi_reset_n : out std_logic; -- afi_reset.reset_n
afi_reset_export_n : out std_logic; -- afi_reset_export.reset_n
mem_a : out std_logic_vector(13 downto 0); -- memory.mem_a
mem_ba : out std_logic_vector(2 downto 0); -- .mem_ba
mem_ck : out std_logic_vector(1 downto 0); -- .mem_ck
mem_ck_n : out std_logic_vector(1 downto 0); -- .mem_ck_n
mem_cke : out std_logic_vector(0 downto 0); -- .mem_cke
mem_cs_n : out std_logic_vector(0 downto 0); -- .mem_cs_n
mem_dm : out std_logic_vector(7 downto 0); -- .mem_dm
mem_ras_n : out std_logic_vector(0 downto 0); -- .mem_ras_n
mem_cas_n : out std_logic_vector(0 downto 0); -- .mem_cas_n
mem_we_n : out std_logic_vector(0 downto 0); -- .mem_we_n
mem_dq : inout std_logic_vector(63 downto 0) := (others => '0'); -- .mem_dq
mem_dqs : inout std_logic_vector(7 downto 0) := (others => '0'); -- .mem_dqs
mem_dqs_n : inout std_logic_vector(7 downto 0) := (others => '0'); -- .mem_dqs_n
mem_odt : out std_logic_vector(0 downto 0); -- .mem_odt
afi_addr : in std_logic_vector(13 downto 0) := (others => '0'); -- afi.afi_addr
afi_ba : in std_logic_vector(2 downto 0) := (others => '0'); -- .afi_ba
afi_cke : in std_logic_vector(0 downto 0) := (others => '0'); -- .afi_cke
afi_cs_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .afi_cs_n
afi_ras_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .afi_ras_n
afi_we_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .afi_we_n
afi_cas_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .afi_cas_n
afi_odt : in std_logic_vector(0 downto 0) := (others => '0'); -- .afi_odt
afi_dqs_burst : in std_logic_vector(7 downto 0) := (others => '0'); -- .afi_dqs_burst
afi_wdata_valid : in std_logic_vector(7 downto 0) := (others => '0'); -- .afi_wdata_valid
afi_wdata : in std_logic_vector(127 downto 0) := (others => '0'); -- .afi_wdata
afi_dm : in std_logic_vector(15 downto 0) := (others => '0'); -- .afi_dm
afi_rdata : out std_logic_vector(127 downto 0); -- .afi_rdata
afi_rdata_en : in std_logic_vector(0 downto 0) := (others => '0'); -- .afi_rdata_en
afi_rdata_en_full : in std_logic_vector(0 downto 0) := (others => '0'); -- .afi_rdata_en_full
afi_rdata_valid : out std_logic_vector(0 downto 0); -- .afi_rdata_valid
afi_mem_clk_disable : in std_logic_vector(1 downto 0) := (others => '0'); -- .afi_mem_clk_disable
afi_init_req : in std_logic := '0'; -- .afi_init_req
afi_cal_req : in std_logic := '0'; -- .afi_cal_req
afi_wlat : out std_logic_vector(5 downto 0); -- .afi_wlat
afi_rlat : out std_logic_vector(5 downto 0); -- .afi_rlat
afi_cal_success : out std_logic; -- .afi_cal_success
afi_cal_fail : out std_logic; -- .afi_cal_fail
oct_rdn : in std_logic := '0'; -- oct.rdn
oct_rup : in std_logic := '0' -- .rup
);
end entity uniphy;
architecture rtl of uniphy is
component uniphy_0002 is
port (
pll_ref_clk : in std_logic := 'X'; -- clk
global_reset_n : in std_logic := 'X'; -- reset_n
soft_reset_n : in std_logic := 'X'; -- reset_n
afi_clk : out std_logic; -- clk
afi_half_clk : out std_logic; -- clk
afi_reset_n : out std_logic; -- reset_n
afi_reset_export_n : out std_logic; -- reset_n
mem_a : out std_logic_vector(13 downto 0); -- mem_a
mem_ba : out std_logic_vector(2 downto 0); -- mem_ba
mem_ck : out std_logic_vector(1 downto 0); -- mem_ck
mem_ck_n : out std_logic_vector(1 downto 0); -- mem_ck_n
mem_cke : out std_logic_vector(0 downto 0); -- mem_cke
mem_cs_n : out std_logic_vector(0 downto 0); -- mem_cs_n
mem_dm : out std_logic_vector(7 downto 0); -- mem_dm
mem_ras_n : out std_logic_vector(0 downto 0); -- mem_ras_n
mem_cas_n : out std_logic_vector(0 downto 0); -- mem_cas_n
mem_we_n : out std_logic_vector(0 downto 0); -- mem_we_n
mem_dq : inout std_logic_vector(63 downto 0) := (others => 'X'); -- mem_dq
mem_dqs : inout std_logic_vector(7 downto 0) := (others => 'X'); -- mem_dqs
mem_dqs_n : inout std_logic_vector(7 downto 0) := (others => 'X'); -- mem_dqs_n
mem_odt : out std_logic_vector(0 downto 0); -- mem_odt
afi_addr : in std_logic_vector(13 downto 0) := (others => 'X'); -- afi_addr
afi_ba : in std_logic_vector(2 downto 0) := (others => 'X'); -- afi_ba
afi_cke : in std_logic_vector(0 downto 0) := (others => 'X'); -- afi_cke
afi_cs_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- afi_cs_n
afi_ras_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- afi_ras_n
afi_we_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- afi_we_n
afi_cas_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- afi_cas_n
afi_odt : in std_logic_vector(0 downto 0) := (others => 'X'); -- afi_odt
afi_dqs_burst : in std_logic_vector(7 downto 0) := (others => 'X'); -- afi_dqs_burst
afi_wdata_valid : in std_logic_vector(7 downto 0) := (others => 'X'); -- afi_wdata_valid
afi_wdata : in std_logic_vector(127 downto 0) := (others => 'X'); -- afi_wdata
afi_dm : in std_logic_vector(15 downto 0) := (others => 'X'); -- afi_dm
afi_rdata : out std_logic_vector(127 downto 0); -- afi_rdata
afi_rdata_en : in std_logic_vector(0 downto 0) := (others => 'X'); -- afi_rdata_en
afi_rdata_en_full : in std_logic_vector(0 downto 0) := (others => 'X'); -- afi_rdata_en_full
afi_rdata_valid : out std_logic_vector(0 downto 0); -- afi_rdata_valid
afi_mem_clk_disable : in std_logic_vector(1 downto 0) := (others => 'X'); -- afi_mem_clk_disable
afi_init_req : in std_logic := 'X'; -- afi_init_req
afi_cal_req : in std_logic := 'X'; -- afi_cal_req
afi_wlat : out std_logic_vector(5 downto 0); -- afi_wlat
afi_rlat : out std_logic_vector(5 downto 0); -- afi_rlat
afi_cal_success : out std_logic; -- afi_cal_success
afi_cal_fail : out std_logic; -- afi_cal_fail
oct_rdn : in std_logic := 'X'; -- rdn
oct_rup : in std_logic := 'X' -- rup
);
end component uniphy_0002;
begin
uniphy_inst : component uniphy_0002
port map (
pll_ref_clk => pll_ref_clk, -- pll_ref_clk.clk
global_reset_n => global_reset_n, -- global_reset.reset_n
soft_reset_n => soft_reset_n, -- soft_reset.reset_n
afi_clk => afi_clk, -- afi_clk.clk
afi_half_clk => afi_half_clk, -- afi_half_clk.clk
afi_reset_n => afi_reset_n, -- afi_reset.reset_n
afi_reset_export_n => afi_reset_export_n, -- afi_reset_export.reset_n
mem_a => mem_a, -- memory.mem_a
mem_ba => mem_ba, -- .mem_ba
mem_ck => mem_ck, -- .mem_ck
mem_ck_n => mem_ck_n, -- .mem_ck_n
mem_cke => mem_cke, -- .mem_cke
mem_cs_n => mem_cs_n, -- .mem_cs_n
mem_dm => mem_dm, -- .mem_dm
mem_ras_n => mem_ras_n, -- .mem_ras_n
mem_cas_n => mem_cas_n, -- .mem_cas_n
mem_we_n => mem_we_n, -- .mem_we_n
mem_dq => mem_dq, -- .mem_dq
mem_dqs => mem_dqs, -- .mem_dqs
mem_dqs_n => mem_dqs_n, -- .mem_dqs_n
mem_odt => mem_odt, -- .mem_odt
afi_addr => afi_addr, -- afi.afi_addr
afi_ba => afi_ba, -- .afi_ba
afi_cke => afi_cke, -- .afi_cke
afi_cs_n => afi_cs_n, -- .afi_cs_n
afi_ras_n => afi_ras_n, -- .afi_ras_n
afi_we_n => afi_we_n, -- .afi_we_n
afi_cas_n => afi_cas_n, -- .afi_cas_n
afi_odt => afi_odt, -- .afi_odt
afi_dqs_burst => afi_dqs_burst, -- .afi_dqs_burst
afi_wdata_valid => afi_wdata_valid, -- .afi_wdata_valid
afi_wdata => afi_wdata, -- .afi_wdata
afi_dm => afi_dm, -- .afi_dm
afi_rdata => afi_rdata, -- .afi_rdata
afi_rdata_en => afi_rdata_en, -- .afi_rdata_en
afi_rdata_en_full => afi_rdata_en_full, -- .afi_rdata_en_full
afi_rdata_valid => afi_rdata_valid, -- .afi_rdata_valid
afi_mem_clk_disable => afi_mem_clk_disable, -- .afi_mem_clk_disable
afi_init_req => afi_init_req, -- .afi_init_req
afi_cal_req => afi_cal_req, -- .afi_cal_req
afi_wlat => afi_wlat, -- .afi_wlat
afi_rlat => afi_rlat, -- .afi_rlat
afi_cal_success => afi_cal_success, -- .afi_cal_success
afi_cal_fail => afi_cal_fail, -- .afi_cal_fail
oct_rdn => oct_rdn, -- oct.rdn
oct_rup => oct_rup -- .rup
);
end architecture rtl; -- of uniphy
-- Retrieval info: <?xml version="1.0"?>
--<!--
-- Generated by Altera MegaWizard Launcher Utility version 1.0
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- ************************************************************
-- Copyright (C) 1991-2015 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
---->
-- Retrieval info: <instance entity-name="altera_mem_if_ddr2_emif" version="15.0" >
-- Retrieval info: <generic name="RATE" value="Full" />
-- Retrieval info: <generic name="MEM_CLK_FREQ" value="333.3333" />
-- Retrieval info: <generic name="USE_MEM_CLK_FREQ" value="false" />
-- Retrieval info: <generic name="FORCE_DQS_TRACKING" value="AUTO" />
-- Retrieval info: <generic name="FORCE_SHADOW_REGS" value="AUTO" />
-- Retrieval info: <generic name="MRS_MIRROR_PING_PONG_ATSO" value="false" />
-- Retrieval info: <generic name="MEM_VENDOR" value="Micron" />
-- Retrieval info: <generic name="MEM_FORMAT" value="UNBUFFERED" />
-- Retrieval info: <generic name="DISCRETE_FLY_BY" value="true" />
-- Retrieval info: <generic name="DEVICE_DEPTH" value="1" />
-- Retrieval info: <generic name="MEM_MIRROR_ADDRESSING" value="0" />
-- Retrieval info: <generic name="MEM_CLK_FREQ_MAX" value="400.0" />
-- Retrieval info: <generic name="MEM_ROW_ADDR_WIDTH" value="14" />
-- Retrieval info: <generic name="MEM_COL_ADDR_WIDTH" value="10" />
-- Retrieval info: <generic name="MEM_DQ_WIDTH" value="64" />
-- Retrieval info: <generic name="MEM_DQ_PER_DQS" value="8" />
-- Retrieval info: <generic name="MEM_BANKADDR_WIDTH" value="3" />
-- Retrieval info: <generic name="MEM_IF_DM_PINS_EN" value="true" />
-- Retrieval info: <generic name="MEM_IF_DQSN_EN" value="true" />
-- Retrieval info: <generic name="MEM_NUMBER_OF_DIMMS" value="1" />
-- Retrieval info: <generic name="MEM_NUMBER_OF_RANKS_PER_DIMM" value="1" />
-- Retrieval info: <generic name="MEM_NUMBER_OF_RANKS_PER_DEVICE" value="1" />
-- Retrieval info: <generic name="MEM_RANK_MULTIPLICATION_FACTOR" value="1" />
-- Retrieval info: <generic name="MEM_CK_WIDTH" value="2" />
-- Retrieval info: <generic name="MEM_CS_WIDTH" value="1" />
-- Retrieval info: <generic name="MEM_CLK_EN_WIDTH" value="1" />
-- Retrieval info: <generic name="ALTMEMPHY_COMPATIBLE_MODE" value="false" />
-- Retrieval info: <generic name="NEXTGEN" value="true" />
-- Retrieval info: <generic name="MEM_IF_BOARD_BASE_DELAY" value="10" />
-- Retrieval info: <generic name="MEM_IF_SIM_VALID_WINDOW" value="0" />
-- Retrieval info: <generic name="MEM_GUARANTEED_WRITE_INIT" value="false" />
-- Retrieval info: <generic name="MEM_VERBOSE" value="true" />
-- Retrieval info: <generic name="PINGPONGPHY_EN" value="false" />
-- Retrieval info: <generic name="DUPLICATE_AC" value="false" />
-- Retrieval info: <generic name="REFRESH_BURST_VALIDATION" value="false" />
-- Retrieval info: <generic name="AP_MODE_EN" value="0" />
-- Retrieval info: <generic name="AP_MODE" value="false" />
-- Retrieval info: <generic name="MEM_BL" value="4" />
-- Retrieval info: <generic name="MEM_BT" value="Sequential" />
-- Retrieval info: <generic name="MEM_ASR" value="Manual" />
-- Retrieval info: <generic name="MEM_SRT" value="2x refresh rate" />
-- Retrieval info: <generic name="MEM_PD" value="Fast exit" />
-- Retrieval info: <generic name="MEM_DRV_STR" value="Full" />
-- Retrieval info: <generic name="MEM_DLL_EN" value="true" />
-- Retrieval info: <generic name="MEM_RTT_NOM" value="50" />
-- Retrieval info: <generic name="MEM_ATCL" value="0" />
-- Retrieval info: <generic name="MEM_TCL" value="6" />
-- Retrieval info: <generic name="MEM_AUTO_LEVELING_MODE" value="true" />
-- Retrieval info: <generic name="MEM_USER_LEVELING_MODE" value="Leveling" />
-- Retrieval info: <generic name="MEM_INIT_EN" value="false" />
-- Retrieval info: <generic name="MEM_INIT_FILE" value="" />
-- Retrieval info: <generic name="DAT_DATA_WIDTH" value="32" />
-- Retrieval info: <generic name="TIMING_TIS" value="375" />
-- Retrieval info: <generic name="TIMING_TIH" value="500" />
-- Retrieval info: <generic name="TIMING_TDS" value="250" />
-- Retrieval info: <generic name="TIMING_TDH" value="300" />
-- Retrieval info: <generic name="TIMING_TDQSQ" value="200" />
-- Retrieval info: <generic name="TIMING_TQHS" value="300" />
-- Retrieval info: <generic name="TIMING_TDQSCK" value="350" />
-- Retrieval info: <generic name="TIMING_TDQSCKDS" value="450" />
-- Retrieval info: <generic name="TIMING_TDQSCKDM" value="900" />
-- Retrieval info: <generic name="TIMING_TDQSCKDL" value="1200" />
-- Retrieval info: <generic name="TIMING_TDQSS" value="0.25" />
-- Retrieval info: <generic name="TIMING_TDQSH" value="0.35" />
-- Retrieval info: <generic name="TIMING_TDSH" value="0.2" />
-- Retrieval info: <generic name="TIMING_TDSS" value="0.2" />
-- Retrieval info: <generic name="MEM_TINIT_US" value="200" />
-- Retrieval info: <generic name="MEM_TMRD_CK" value="5" />
-- Retrieval info: <generic name="MEM_TRAS_NS" value="40.0" />
-- Retrieval info: <generic name="MEM_TRCD_NS" value="15.0" />
-- Retrieval info: <generic name="MEM_TRP_NS" value="15.0" />
-- Retrieval info: <generic name="MEM_TREFI_US" value="7.8" />
-- Retrieval info: <generic name="MEM_TRFC_NS" value="127.5" />
-- Retrieval info: <generic name="CFG_TCCD_NS" value="2.5" />
-- Retrieval info: <generic name="MEM_TWR_NS" value="15.0" />
-- Retrieval info: <generic name="MEM_TWTR" value="3" />
-- Retrieval info: <generic name="MEM_TFAW_NS" value="37.5" />
-- Retrieval info: <generic name="MEM_TRRD_NS" value="7.5" />
-- Retrieval info: <generic name="MEM_TRTP_NS" value="7.5" />
-- Retrieval info: <generic name="SYS_INFO_DEVICE_FAMILY" value="Stratix IV" />
-- Retrieval info: <generic name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID" value="false" />
-- Retrieval info: <generic name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM" value="" />
-- Retrieval info: <generic name="DEVICE_FAMILY_PARAM" value="" />
-- Retrieval info: <generic name="SPEED_GRADE" value="2" />
-- Retrieval info: <generic name="IS_ES_DEVICE" value="false" />
-- Retrieval info: <generic name="DISABLE_CHILD_MESSAGING" value="false" />
-- Retrieval info: <generic name="HARD_EMIF" value="false" />
-- Retrieval info: <generic name="HHP_HPS" value="false" />
-- Retrieval info: <generic name="HHP_HPS_VERIFICATION" value="false" />
-- Retrieval info: <generic name="HHP_HPS_SIMULATION" value="false" />
-- Retrieval info: <generic name="HPS_PROTOCOL" value="DEFAULT" />
-- Retrieval info: <generic name="CUT_NEW_FAMILY_TIMING" value="true" />
-- Retrieval info: <generic name="POWER_OF_TWO_BUS" value="false" />
-- Retrieval info: <generic name="SOPC_COMPAT_RESET" value="false" />
-- Retrieval info: <generic name="AVL_MAX_SIZE" value="8" />
-- Retrieval info: <generic name="BYTE_ENABLE" value="true" />
-- Retrieval info: <generic name="ENABLE_CTRL_AVALON_INTERFACE" value="true" />
-- Retrieval info: <generic name="CTL_DEEP_POWERDN_EN" value="false" />
-- Retrieval info: <generic name="CTL_SELF_REFRESH_EN" value="false" />
-- Retrieval info: <generic name="AUTO_POWERDN_EN" value="false" />
-- Retrieval info: <generic name="AUTO_PD_CYCLES" value="0" />
-- Retrieval info: <generic name="CTL_USR_REFRESH_EN" value="false" />
-- Retrieval info: <generic name="CTL_AUTOPCH_EN" value="false" />
-- Retrieval info: <generic name="CTL_ZQCAL_EN" value="false" />
-- Retrieval info: <generic name="ADDR_ORDER" value="0" />
-- Retrieval info: <generic name="CTL_LOOK_AHEAD_DEPTH" value="4" />
-- Retrieval info: <generic name="CONTROLLER_LATENCY" value="5" />
-- Retrieval info: <generic name="CFG_REORDER_DATA" value="false" />
-- Retrieval info: <generic name="STARVE_LIMIT" value="10" />
-- Retrieval info: <generic name="CTL_CSR_ENABLED" value="false" />
-- Retrieval info: <generic name="CTL_CSR_CONNECTION" value="INTERNAL_JTAG" />
-- Retrieval info: <generic name="CTL_ECC_ENABLED" value="false" />
-- Retrieval info: <generic name="CTL_HRB_ENABLED" value="false" />
-- Retrieval info: <generic name="CTL_ECC_AUTO_CORRECTION_ENABLED" value="false" />
-- Retrieval info: <generic name="MULTICAST_EN" value="false" />
-- Retrieval info: <generic name="CTL_DYNAMIC_BANK_ALLOCATION" value="false" />
-- Retrieval info: <generic name="CTL_DYNAMIC_BANK_NUM" value="4" />
-- Retrieval info: <generic name="DEBUG_MODE" value="false" />
-- Retrieval info: <generic name="ENABLE_BURST_MERGE" value="false" />
-- Retrieval info: <generic name="CTL_ENABLE_BURST_INTERRUPT" value="true" />
-- Retrieval info: <generic name="CTL_ENABLE_BURST_TERMINATE" value="true" />
-- Retrieval info: <generic name="LOCAL_ID_WIDTH" value="8" />
-- Retrieval info: <generic name="WRBUFFER_ADDR_WIDTH" value="6" />
-- Retrieval info: <generic name="MAX_PENDING_WR_CMD" value="8" />
-- Retrieval info: <generic name="MAX_PENDING_RD_CMD" value="16" />
-- Retrieval info: <generic name="USE_MM_ADAPTOR" value="true" />
-- Retrieval info: <generic name="USE_AXI_ADAPTOR" value="false" />
-- Retrieval info: <generic name="HCX_COMPAT_MODE" value="false" />
-- Retrieval info: <generic name="CTL_CMD_QUEUE_DEPTH" value="8" />
-- Retrieval info: <generic name="CTL_CSR_READ_ONLY" value="1" />
-- Retrieval info: <generic name="CFG_DATA_REORDERING_TYPE" value="INTER_BANK" />
-- Retrieval info: <generic name="NUM_OF_PORTS" value="1" />
-- Retrieval info: <generic name="ENABLE_BONDING" value="false" />
-- Retrieval info: <generic name="ENABLE_USER_ECC" value="false" />
-- Retrieval info: <generic name="AVL_DATA_WIDTH_PORT" value="32,32,32,32,32,32" />
-- Retrieval info: <generic name="PRIORITY_PORT" value="1,1,1,1,1,1" />
-- Retrieval info: <generic name="WEIGHT_PORT" value="0,0,0,0,0,0" />
-- Retrieval info: <generic name="CPORT_TYPE_PORT" value="Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional" />
-- Retrieval info: <generic name="ENABLE_EMIT_BFM_MASTER" value="false" />
-- Retrieval info: <generic name="FORCE_SEQUENCER_TCL_DEBUG_MODE" value="false" />
-- Retrieval info: <generic name="ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT" value="false" />
-- Retrieval info: <generic name="REF_CLK_FREQ" value="50.0" />
-- Retrieval info: <generic name="REF_CLK_FREQ_PARAM_VALID" value="false" />
-- Retrieval info: <generic name="REF_CLK_FREQ_MIN_PARAM" value="0.0" />
-- Retrieval info: <generic name="REF_CLK_FREQ_MAX_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_DR_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_DR_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_DR_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_DR_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_DR_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_MEM_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_MEM_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_MEM_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_MEM_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_MEM_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_AFI_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_AFI_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_AFI_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_WRITE_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_WRITE_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_WRITE_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_WRITE_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_HALF_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_AFI_HALF_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_AFI_HALF_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_HALF_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_NIOS_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_NIOS_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_NIOS_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_NIOS_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_NIOS_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_CONFIG_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_CONFIG_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_CONFIG_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_CONFIG_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_P2C_READ_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_P2C_READ_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_P2C_READ_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_P2C_READ_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_HR_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_HR_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_HR_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_HR_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_HR_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_PHY_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_AFI_PHY_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_AFI_PHY_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_PHY_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_CLK_PARAM_VALID" value="false" />
-- Retrieval info: <generic name="ENABLE_EXTRA_REPORTING" value="false" />
-- Retrieval info: <generic name="NUM_EXTRA_REPORT_PATH" value="10" />
-- Retrieval info: <generic name="ENABLE_ISS_PROBES" value="false" />
-- Retrieval info: <generic name="CALIB_REG_WIDTH" value="8" />
-- Retrieval info: <generic name="USE_SEQUENCER_BFM" value="false" />
-- Retrieval info: <generic name="PLL_SHARING_MODE" value="None" />
-- Retrieval info: <generic name="NUM_PLL_SHARING_INTERFACES" value="1" />
-- Retrieval info: <generic name="EXPORT_AFI_HALF_CLK" value="false" />
-- Retrieval info: <generic name="ABSTRACT_REAL_COMPARE_TEST" value="false" />
-- Retrieval info: <generic name="INCLUDE_BOARD_DELAY_MODEL" value="false" />
-- Retrieval info: <generic name="INCLUDE_MULTIRANK_BOARD_DELAY_MODEL" value="false" />
-- Retrieval info: <generic name="USE_FAKE_PHY" value="false" />
-- Retrieval info: <generic name="FORCE_MAX_LATENCY_COUNT_WIDTH" value="0" />
-- Retrieval info: <generic name="ENABLE_NON_DESTRUCTIVE_CALIB" value="false" />
-- Retrieval info: <generic name="ENABLE_DELAY_CHAIN_WRITE" value="false" />
-- Retrieval info: <generic name="TRACKING_ERROR_TEST" value="false" />
-- Retrieval info: <generic name="TRACKING_WATCH_TEST" value="false" />
-- Retrieval info: <generic name="MARGIN_VARIATION_TEST" value="false" />
-- Retrieval info: <generic name="AC_ROM_USER_ADD_0" value="0_0000_0000_0000" />
-- Retrieval info: <generic name="AC_ROM_USER_ADD_1" value="0_0000_0000_1000" />
-- Retrieval info: <generic name="TREFI" value="35100" />
-- Retrieval info: <generic name="REFRESH_INTERVAL" value="15000" />
-- Retrieval info: <generic name="ENABLE_NON_DES_CAL_TEST" value="false" />
-- Retrieval info: <generic name="TRFC" value="350" />
-- Retrieval info: <generic name="ENABLE_NON_DES_CAL" value="false" />
-- Retrieval info: <generic name="EXTRA_SETTINGS" value="" />
-- Retrieval info: <generic name="MEM_DEVICE" value="MISSING_MODEL" />
-- Retrieval info: <generic name="FORCE_SYNTHESIS_LANGUAGE" value="" />
-- Retrieval info: <generic name="FORCED_NUM_WRITE_FR_CYCLE_SHIFTS" value="0" />
-- Retrieval info: <generic name="SEQUENCER_TYPE" value="NIOS" />
-- Retrieval info: <generic name="ADVERTIZE_SEQUENCER_SW_BUILD_FILES" value="false" />
-- Retrieval info: <generic name="FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT" value="false" />
-- Retrieval info: <generic name="PHY_ONLY" value="true" />
-- Retrieval info: <generic name="SEQ_MODE" value="0" />
-- Retrieval info: <generic name="ADVANCED_CK_PHASES" value="false" />
-- Retrieval info: <generic name="COMMAND_PHASE" value="0.0" />
-- Retrieval info: <generic name="MEM_CK_PHASE" value="0.0" />
-- Retrieval info: <generic name="P2C_READ_CLOCK_ADD_PHASE" value="0.0" />
-- Retrieval info: <generic name="C2P_WRITE_CLOCK_ADD_PHASE" value="0.0" />
-- Retrieval info: <generic name="ACV_PHY_CLK_ADD_FR_PHASE" value="0.0" />
-- Retrieval info: <generic name="PLL_LOCATION" value="Top_Bottom" />
-- Retrieval info: <generic name="SKIP_MEM_INIT" value="true" />
-- Retrieval info: <generic name="READ_DQ_DQS_CLOCK_SOURCE" value="INVERTED_DQS_BUS" />
-- Retrieval info: <generic name="DQ_INPUT_REG_USE_CLKN" value="false" />
-- Retrieval info: <generic name="DQS_DQSN_MODE" value="DIFFERENTIAL" />
-- Retrieval info: <generic name="AFI_DEBUG_INFO_WIDTH" value="32" />
-- Retrieval info: <generic name="CALIBRATION_MODE" value="Skip" />
-- Retrieval info: <generic name="NIOS_ROM_DATA_WIDTH" value="32" />
-- Retrieval info: <generic name="READ_FIFO_SIZE" value="8" />
-- Retrieval info: <generic name="PHY_CSR_ENABLED" value="false" />
-- Retrieval info: <generic name="PHY_CSR_CONNECTION" value="INTERNAL_JTAG" />
-- Retrieval info: <generic name="USER_DEBUG_LEVEL" value="0" />
-- Retrieval info: <generic name="TIMING_BOARD_DERATE_METHOD" value="AUTO" />
-- Retrieval info: <generic name="TIMING_BOARD_CK_CKN_SLEW_RATE" value="2.0" />
-- Retrieval info: <generic name="TIMING_BOARD_AC_SLEW_RATE" value="1.0" />
-- Retrieval info: <generic name="TIMING_BOARD_DQS_DQSN_SLEW_RATE" value="2.0" />
-- Retrieval info: <generic name="TIMING_BOARD_DQ_SLEW_RATE" value="1.0" />
-- Retrieval info: <generic name="TIMING_BOARD_TIS" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_TIH" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_TDS" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_TDH" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_ISI_METHOD" value="AUTO" />
-- Retrieval info: <generic name="TIMING_BOARD_AC_EYE_REDUCTION_SU" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_AC_EYE_REDUCTION_H" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_DQ_EYE_REDUCTION" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_READ_DQ_EYE_REDUCTION" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME" value="0.0" />
-- Retrieval info: <generic name="PACKAGE_DESKEW" value="false" />
-- Retrieval info: <generic name="AC_PACKAGE_DESKEW" value="false" />
-- Retrieval info: <generic name="TIMING_BOARD_MAX_CK_DELAY" value="0.6" />
-- Retrieval info: <generic name="TIMING_BOARD_MAX_DQS_DELAY" value="0.6" />
-- Retrieval info: <generic name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN" value="-0.01" />
-- Retrieval info: <generic name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX" value="0.01" />
-- Retrieval info: <generic name="TIMING_BOARD_SKEW_BETWEEN_DIMMS" value="0.05" />
-- Retrieval info: <generic name="TIMING_BOARD_SKEW_WITHIN_DQS" value="0.02" />
-- Retrieval info: <generic name="TIMING_BOARD_SKEW_BETWEEN_DQS" value="0.02" />
-- Retrieval info: <generic name="TIMING_BOARD_DQ_TO_DQS_SKEW" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_AC_SKEW" value="0.02" />
-- Retrieval info: <generic name="TIMING_BOARD_AC_TO_CK_SKEW" value="0.6" />
-- Retrieval info: <generic name="ENABLE_EXPORT_SEQ_DEBUG_BRIDGE" value="false" />
-- Retrieval info: <generic name="CORE_DEBUG_CONNECTION" value="EXPORT" />
-- Retrieval info: <generic name="ADD_EXTERNAL_SEQ_DEBUG_NIOS" value="false" />
-- Retrieval info: <generic name="ED_EXPORT_SEQ_DEBUG" value="false" />
-- Retrieval info: <generic name="ADD_EFFICIENCY_MONITOR" value="false" />
-- Retrieval info: <generic name="ENABLE_ABS_RAM_MEM_INIT" value="false" />
-- Retrieval info: <generic name="ABS_RAM_MEM_INIT_FILENAME" value="meminit" />
-- Retrieval info: <generic name="DLL_SHARING_MODE" value="None" />
-- Retrieval info: <generic name="NUM_DLL_SHARING_INTERFACES" value="1" />
-- Retrieval info: <generic name="OCT_SHARING_MODE" value="None" />
-- Retrieval info: <generic name="NUM_OCT_SHARING_INTERFACES" value="1" />
-- Retrieval info: <generic name="AUTO_DEVICE" value="Unknown" />
-- Retrieval info: <generic name="AUTO_DEVICE_SPEEDGRADE" value="Unknown" />
-- Retrieval info: </instance>
-- IPFS_FILES : uniphy.vho
-- RELATED_FILES: uniphy.vhd, uniphy_0002.v, uniphy_pll0.sv, uniphy_p0_clock_pair_generator.v, uniphy_p0_read_valid_selector.v, uniphy_p0_addr_cmd_datapath.v, uniphy_p0_reset.v, uniphy_p0_acv_ldc.v, uniphy_p0_memphy.sv, uniphy_p0_reset_sync.v, uniphy_p0_new_io_pads.v, uniphy_p0_fr_cycle_shifter.v, uniphy_p0_fr_cycle_extender.v, uniphy_p0_read_datapath.sv, uniphy_p0_write_datapath.v, uniphy_p0_simple_ddio_out.sv, uniphy_p0_phy_csr.sv, uniphy_p0_iss_probe.v, uniphy_p0_addr_cmd_pads.v, uniphy_p0_flop_mem.v, uniphy_p0.sv, uniphy_p0_altdqdqs.v, altdq_dqs2_ddio_3reg_stratixiv.sv, afi_mux_ddrx.v, uniphy_s0.v, altera_mem_if_sequencer_rst.sv, altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst.v, altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst_test_bench.v, sequencer_scc_mgr.sv, sequencer_scc_siii_wrapper.sv, sequencer_scc_siii_phase_decode.v, sequencer_scc_sv_wrapper.sv, sequencer_scc_sv_phase_decode.v, sequencer_scc_acv_wrapper.sv, sequencer_scc_acv_phase_decode.v, sequencer_scc_reg_file.v, sequencer_reg_file.sv, sequencer_phy_mgr.sv, sequencer_data_mgr.sv, rw_manager_ddr2.v, rw_manager_ac_ROM_reg.v, rw_manager_bitcheck.v, rw_manager_core.sv, rw_manager_data_broadcast.v, rw_manager_data_decoder.v, rw_manager_datamux.v, rw_manager_di_buffer.v, rw_manager_di_buffer_wrap.v, rw_manager_dm_decoder.v, rw_manager_generic.sv, rw_manager_inst_ROM_reg.v, rw_manager_jumplogic.v, rw_manager_lfsr72.v, rw_manager_lfsr36.v, rw_manager_lfsr12.v, rw_manager_pattern_fifo.v, rw_manager_ram.v, rw_manager_ram_csr.v, rw_manager_read_datapath.v, rw_manager_write_decoder.v, rw_manager_ac_ROM_no_ifdef_params.v, rw_manager_inst_ROM_no_ifdef_params.v, altera_mem_if_sequencer_mem_no_ifdef_params.sv, uniphy_s0_mm_interconnect_0.v, uniphy_s0_irq_mapper.sv, altera_merlin_master_translator.sv, altera_merlin_slave_translator.sv, altera_merlin_master_agent.sv, altera_merlin_slave_agent.sv, altera_merlin_burst_uncompressor.sv, altera_avalon_sc_fifo.v, uniphy_s0_mm_interconnect_0_router.sv, uniphy_s0_mm_interconnect_0_router_001.sv, uniphy_s0_mm_interconnect_0_router_002.sv, uniphy_s0_mm_interconnect_0_router_005.sv, uniphy_s0_mm_interconnect_0_cmd_demux.sv, uniphy_s0_mm_interconnect_0_cmd_demux_001.sv, altera_merlin_arbitrator.sv, uniphy_s0_mm_interconnect_0_cmd_mux.sv, uniphy_s0_mm_interconnect_0_cmd_mux_003.sv, uniphy_s0_mm_interconnect_0_rsp_demux_003.sv, uniphy_s0_mm_interconnect_0_rsp_mux.sv, uniphy_s0_mm_interconnect_0_rsp_mux_001.sv, uniphy_s0_mm_interconnect_0_avalon_st_adapter.v, uniphy_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv, altera_mem_if_oct_stratixiv.sv, altera_mem_if_dll_stratixiv.sv
| gpl-3.0 | 2dccab8aa082ccd17c924d082d9200e0 | 0.58913 | 3.093286 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/memctrl/memctrl.vhd | 1 | 20,700 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: memctrl
-- File: memctrl.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Memory controller package
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.log2;
library techmap;
use techmap.gencomp.all;
package memctrl is
type memory_in_type is record
data : std_logic_vector(31 downto 0); -- Data bus address
brdyn : std_logic;
bexcn : std_logic;
writen : std_logic;
wrn : std_logic_vector(3 downto 0);
bwidth : std_logic_vector(1 downto 0);
sd : std_logic_vector(63 downto 0);
cb : std_logic_vector(15 downto 0);
scb : std_logic_vector(15 downto 0);
edac : std_logic;
end record;
constant memory_in_none : memory_in_type :=
((others => '0'), '0', '0', '0', (others => '0'), (others => '0'),
(others => '0'), (others => '0'), (others => '0'), '0');
type memory_out_type is record
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
sddata : std_logic_vector(63 downto 0);
ramsn : std_logic_vector(7 downto 0);
ramoen : std_logic_vector(7 downto 0);
ramn : std_ulogic;
romn : std_ulogic;
mben : std_logic_vector(3 downto 0);
iosn : std_logic;
romsn : std_logic_vector(7 downto 0);
oen : std_logic;
writen : std_logic;
wrn : std_logic_vector(3 downto 0);
bdrive : std_logic_vector(3 downto 0);
vbdrive : std_logic_vector(31 downto 0); --vector bus drive
svbdrive : std_logic_vector(63 downto 0); --vector bus drive sdram
read : std_logic;
sa : std_logic_vector(14 downto 0);
cb : std_logic_vector(15 downto 0);
scb : std_logic_vector(15 downto 0);
vcdrive : std_logic_vector(15 downto 0); --vector bus drive cb
svcdrive : std_logic_vector(15 downto 0); --vector bus drive cb sdram
ce : std_ulogic;
sdram_en : std_ulogic; -- SDRAM enabled
rs_edac_en : std_ulogic; -- Reed-Solomon enabled
end record;
constant memory_out_none : memory_out_type :=
((others => '0'), (others => '0'), (others => '0'), (others => '1'),
(others => '1'), '1', '1', (others => '1'), '1', (others => '1'),
'1', '1', (others => '1'), (others => '1'), (others => '1'),
(others => '1'), '0', (others => '0'), (others => '1'), (others => '1'),
(others => '1'), (others => '1'), '0', '0', '0');
type sdctrl_in_type is record
wprot : std_ulogic;
data : std_logic_vector (127 downto 0); -- data in
cb : std_logic_vector(63 downto 0);
regrdata : std_logic_vector(63 downto 0); -- PHY-specific reg in
datavalid : std_logic; -- Data-valid signal
end record;
constant sdctrl_in_none : sdctrl_in_type :=
('0', (others => '0'), (others => '0'), (others => '0'), '0');
type sdctrl_out_type is record
sdcke : std_logic_vector ( 1 downto 0); -- clk en
sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
xsdcsn : std_logic_vector ( 7 downto 0); -- ext. chip sel
sdwen : std_ulogic; -- write en
rasn : std_ulogic; -- row addr stb
casn : std_ulogic; -- col addr stb
dqm : std_logic_vector ( 15 downto 0); -- data i/o mask
bdrive : std_ulogic; -- bus drive
qdrive : std_ulogic; -- bus drive
nbdrive : std_ulogic; -- bdrive 1 cycle early
vbdrive : std_logic_vector(63 downto 0); -- vector bus drive
address : std_logic_vector (16 downto 2); -- address out
data : std_logic_vector (127 downto 0); -- data out
cb : std_logic_vector(63 downto 0);
ce : std_ulogic;
ba : std_logic_vector (2 downto 0); -- bank address
sdck : std_logic_vector(2 downto 0);
moben : std_logic; -- Mobile support
cal_en : std_logic_vector(7 downto 0); -- enable delay calibration
cal_inc : std_logic_vector(7 downto 0); -- inc/dec delay
cal_pll : std_logic_vector(1 downto 0); -- (enable,inc/dec) pll phase
cal_rst : std_logic; -- calibration reset
odt : std_logic_vector(1 downto 0); -- In Die Termination
conf : std_logic_vector(63 downto 0);
oct : std_logic; -- On Chip Termination
vcbdrive : std_logic_vector(31 downto 0); -- cb vector bus drive
dqs_gate : std_logic;
cbdqm : std_logic_vector(7 downto 0);
cbcal_en : std_logic_vector(3 downto 0);
cbcal_inc : std_logic_vector(3 downto 0);
read_pend : std_logic_vector(7 downto 0); -- Read pending within 7...0
-- cycles (not including phy delays)
-- PHY-specific register interface
regwdata : std_logic_vector(63 downto 0);
regwrite : std_logic_vector(1 downto 0);
end record;
constant sdctrl_out_none : sdctrl_out_type :=
((others => '0'), (others => '1'), (others => '1'), '0', '0', '0', (others => '0'),
'0', '0', '0', (others => '0'), (others => '0'), (others => '0'),
(others => '0'), '0', (others => '0'), (others => '0'), '0',
(others => '0'), (others => '0'), (others => '0'), '0',
(others => '0'), (others => '0'), '0', (others => '0'), '0',
(others => '0'), (others => '0'), (others => '0'), "00000000",
(others => '0'), "00");
type sdram_out_type is record
sdcke : std_logic_vector ( 1 downto 0); -- clk en
sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
sdwen : std_ulogic; -- write en
rasn : std_ulogic; -- row addr stb
casn : std_ulogic; -- col addr stb
dqm : std_logic_vector ( 7 downto 0); -- data i/o mask
end record;
constant sdram_out_none : sdram_out_type := (
sdcke => (others => '0'),
sdcsn => (others => '0'),
sdwen => '0',
rasn => '0',
casn => '0',
dqm => (others => '0'));
type zbtssram_out_type is record
cen : std_ulogic;
oen : std_ulogic;
wen : std_ulogic;
advld : std_ulogic;
addr : std_logic_vector(22 downto 0);
bwn : std_logic_vector(15 downto 0);
data : std_logic_vector(127 downto 0);
dqoen : std_logic_vector(127 downto 0);
zz : std_ulogic;
shutdown : std_ulogic;
end record;
constant zbtssram_out_none : zbtssram_out_type := (
'1','1','1','1',(others => '0'),(others => '1'),(others => '0'),(others => '1'),'0','0');
type zbtssram_in_type is record
data : std_logic_vector(127 downto 0);
mbe : std_logic_vector(7 downto 0);
end record;
constant zbtssram_in_none : zbtssram_in_type := ( data => (others => '0'), mbe => (others => '0') );
component sdctrl
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
pwron : integer := 0;
sdbits : integer := 32;
oepol : integer := 0;
pageburst : integer := 0;
mobile : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component sdctrl64
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
pwron : integer := 0;
oepol : integer := 0;
pageburst : integer := 0;
mobile : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component ftsdctrl is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
pwron : integer := 0;
sdbits : integer := 32;
edacen : integer := 1;
errcnt : integer := 0;
cntbits : integer range 1 to 8 := 1;
oepol : integer := 0;
pageburst : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component ftsdctrl64
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
pwron : integer := 0;
oepol : integer := 0;
pageburst : integer := 0;
mobile : integer := 0;
edac : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component srctrl
generic (
hindex : integer := 0;
romaddr : integer := 0;
rommask : integer := 16#ff0#;
ramaddr : integer := 16#400#;
rammask : integer := 16#ff0#;
ioaddr : integer := 16#200#;
iomask : integer := 16#ff0#;
ramws : integer := 0;
romws : integer := 2;
iows : integer := 2;
rmw : integer := 0;
prom8en : integer := 0;
oepol : integer := 0;
srbanks : integer range 1 to 5 := 1;
banksz : integer range 0 to 13 := 13;
romasel : integer range 0 to 28 := 19
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sri : in memory_in_type;
sro : out memory_out_type;
sdo : out sdctrl_out_type
);
end component;
component ftsrctrl is
generic (
hindex : integer := 0;
romaddr : integer := 0;
rommask : integer := 16#ff0#;
ramaddr : integer := 16#400#;
rammask : integer := 16#ff0#;
ioaddr : integer := 16#200#;
iomask : integer := 16#ff0#;
ramws : integer := 0;
romws : integer := 2;
iows : integer := 2;
rmw : integer := 0;
srbanks : integer range 1 to 8 := 1;
banksz : integer range 0 to 15 := 15;
rombanks : integer range 1 to 8 := 1;
rombanksz : integer range 0 to 15 := 15;
rombankszdef : integer range 0 to 15 := 15;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
edacen : integer range 0 to 1 := 1;
errcnt : integer range 0 to 1 := 0;
cntbits : integer range 1 to 8 := 1;
wsreg : integer := 0;
oepol : integer := 0;
prom8en : integer := 0;
netlist : integer := 0;
tech : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
sri : in memory_in_type;
sro : out memory_out_type;
sdo : out sdctrl_out_type
);
end component;
type sdram_in_type is record
haddr : std_logic_vector(31 downto 0); -- memory address
rhaddr : std_logic_vector(31 downto 0); -- latched memory address
hready : std_ulogic;
hsize : std_logic_vector(1 downto 0);
hsel : std_ulogic;
hwrite : std_ulogic;
htrans : std_logic_vector(1 downto 0);
rhtrans : std_logic_vector(1 downto 0);
nhtrans : std_logic_vector(1 downto 0);
idle : std_ulogic;
enable : std_ulogic;
error : std_ulogic;
merror : std_ulogic;
brmw : std_ulogic;
edac : std_ulogic;
srdis : std_logic;
end record;
type sdram_mctrl_out_type is record
address : std_logic_vector(16 downto 2);
busy : std_ulogic;
aload : std_ulogic;
bdrive : std_ulogic;
hready : std_ulogic;
hsel : std_ulogic;
bsel : std_ulogic;
hresp : std_logic_vector (1 downto 0);
vhready : std_ulogic;
prdata : std_logic_vector (31 downto 0);
end record;
type wprot_out_type is record
wprothit : std_ulogic;
end record;
component sdmctrl
generic (
pindex : integer := 0;
invclk : integer := 0;
fast : integer := 0;
wprot : integer := 0;
sdbits : integer := 32;
pageburst : integer := 0;
mobile : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
sdi : in sdram_in_type;
sdo : out sdram_out_type;
apbi : in apb_slv_in_type;
wpo : in wprot_out_type;
sdmo : out sdram_mctrl_out_type
);
end component;
component ftsdmctrl
generic (
pindex : integer := 0;
invclk : integer := 0;
fast : integer := 0;
wprot : integer := 0;
sdbits : integer := 32;
syncrst : integer := 0;
pageburst : integer := 0;
edac : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
sdi : in sdram_in_type;
sdo : out sdram_out_type;
apbi : in apb_slv_in_type;
wpo : in wprot_out_type;
sdmo : out sdram_mctrl_out_type
);
end component;
component ftmctrl
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 16#000#;
rommask : integer := 16#E00#;
ioaddr : integer := 16#200#;
iomask : integer := 16#E00#;
ramaddr : integer := 16#400#;
rammask : integer := 16#C00#;
paddr : integer := 0;
pmask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
romasel : integer := 28;
sdrasel : integer := 29;
srbanks : integer := 4;
ram8 : integer := 0;
ram16 : integer := 0;
sden : integer := 0;
sepbus : integer := 0;
sdbits : integer := 32;
sdlsb : integer := 2; -- set to 12 for the GE-HPE board
oepol : integer := 0;
edac : integer := 0;
syncrst : integer := 0;
pageburst : integer := 0;
scantest : integer := 0;
writefb : integer := 0;
netlist : integer := 0;
tech : integer := 0;
rahold : integer := 0;
wsshift : integer := 0;
brdynto : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
memi : in memory_in_type;
memo : out memory_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
wpo : in wprot_out_type;
sdo : out sdram_out_type
);
end component;
component ssrctrl
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 0;
rommask : integer := 16#ff0#;
ramaddr : integer := 16#400#;
rammask : integer := 16#ff0#;
ioaddr : integer := 16#200#;
iomask : integer := 16#ff0#;
paddr : integer := 0;
pmask : integer := 16#fff#;
oepol : integer := 0;
bus16 : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
sri : in memory_in_type;
sro : out memory_out_type
);
end component;
component ftsrctrl_v1
generic (
hindex: Integer := 1;
romaddr: Integer := 16#000#;
rommask: Integer := 16#ff0#;
ramaddr: Integer := 16#400#;
rammask: Integer := 16#ff0#;
ioaddr: Integer := 16#200#;
iomask: Integer := 16#ff0#;
ramws: Integer := 0;
romws: Integer := 0;
iows: Integer := 0;
rmw: Integer := 1;
srbanks: Integer range 1 to 8 := 8;
banksz: Integer range 0 to 13 := 0;
rombanks: Integer range 1 to 8 := 8;
rombanksz: Integer range 0 to 13 := 0;
rombankszdef: Integer range 0 to 13 := 6;
romasel: Integer range 0 to 28 := 0;
pindex: Integer := 0;
paddr: Integer := 16#000#;
pmask: Integer := 16#fff#;
edacen: Integer range 0 to 1 := 1;
errcnt: Integer range 0 to 1 := 0;
cntbits: Integer range 1 to 8 := 1;
wsreg: Integer := 1;
oepol: Integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
sri : in memory_in_type;
sro : out memory_out_type;
sdo : out sdctrl_out_type
);
end component;
component ftsrctrl8 is
generic (
hindex : integer := 0;
ramaddr : integer := 16#400#;
rammask : integer := 16#ff0#;
ioaddr : integer := 16#200#;
iomask : integer := 16#ff0#;
ramws : integer := 0;
iows : integer := 2;
srbanks : integer range 1 to 8 := 1;
banksz : integer range 0 to 15 := 15;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
edacen : integer range 0 to 1 := 1;
errcnt : integer range 0 to 1 := 1;
cntbits : integer range 1 to 8 := 1;
wsreg : integer := 0;
oepol : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
sri : in memory_in_type;
sro : out memory_out_type
);
end component;
component p8ctrl
generic (
hindex : integer := 0;
romaddr : integer := 0;
rommask : integer := 16#ff0#;
ramaddr : integer := 0;
iomask : integer := 16#ff0#;
ioaddr : integer := 0;
rammask : integer := 16#ff0#;
romws : integer := 15;
ramws : integer := 15;
prom8en : integer := 0;
rmw : integer := 0;
oepol : integer := 0;
romasel : integer range 0 to 28 := 23
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sri : in memory_in_type;
sro : out memory_out_type;
sdo : out sdctrl_out_type
);
end component;
end;
| gpl-3.0 | 1926dfc0693f29fbd8c01bcfbc775e31 | 0.516184 | 3.464435 | false | false | false | false |
kdgwill/VHDL_Framer_Example | VHDL_Framer_Example/Example1/receiver.vhd | 1 | 2,533 | ---------------------------------------------------------------------------------
--Receiver------------------------------------------------------------
--By Kyle Williams, 04/07/2011--------------------------------------------------
--CLASS DESCRIPTION------------------------------------------------------------
--2--Detect a start of Frame whose pattern is 10101011----------------------------
--3--After frame detect take every 8 bits and store them in a ram----------------
----------------Define Libraries to be used--------------------------------------
LIBRARY IEEE ;
USE IEEE.std_logic_1164.all ;
USE IEEE.std_logic_unsigned.all;
-----------------ENTITY FOR RECEIVER------------------------------------------
ENTITY receiver is
GENERIC ( bits : INTEGER := 8); -- # of bits per word
PORT ( reset : IN STD_Logic;
clock : IN STD_LOGIC;
rec_in : IN STD_LOGIC;
enable : OUT STD_LOGIC;
rec_out : OUT STD_LOGIC_VECTOR (bits -1 DOWNTO 0)
);
END receiver;
-----------------BEHAVIOR OF RECEIVER-----------------------------------------
ARCHITECTURE receiver of receiver IS
-------------------VARIABLE DECLARATION----------------------------------------
SIGNAL bit_counter : INTEGER;
SIGNAL S_enable : STD_LOGIC;
SIGNAL shiftreg : STD_LOGIC_VECTOR((bits-1) downto 0);
-------------------PROCEDURE------------------------------
BEGIN
enable <= S_enable;
SHIFTIN: PROCESS(clock, reset)
BEGIN
IF(reset = '0')THEN
shiftreg <= (others => '0');
ELSIF rising_edge(CLOCK)THEN
shiftreg <= shiftreg((bits-2) downto 0) & rec_in;
END IF;
END PROCESS shiftin;
Output: PROCESS(clock, reset)
BEGIN
IF (reset = '0') THEN
rec_out <= (others => '0');
ELSIF rising_edge (clock)THEN
------COMPRESS LOOK AT THIS SECTION!!!
IF(bit_counter = (bits-1) AND S_enable='1')THEN
rec_out <= shiftreg;
END IF;
END IF;
END PROCESS Output;
CheckAndEnable:PROCESS(clock, reset)
BEGIN
IF (reset = '0')THEN
S_enable <= '0';
ELSIF rising_edge (clock)THEN
IF (shiftreg = "10101011")THEN
S_enable <= '1';
END IF;
END IF;
END PROCESS CheckAndEnable;
COUNT_BITS:PROCESS(clock, reset)
BEGIN
IF (reset = '0')THEN
bit_counter <= 0;
ELSIF rising_edge (clock)THEN
IF (bit_counter = bits - 1)THEN
bit_counter <= 0;
ELSE
bit_counter <= bit_counter + 1;
END IF;
END IF;
END PROCESS COUNT_BITS;
END receiver; | gpl-3.0 | e7324bd56f146e4a77c7b22becc7cbc9 | 0.475326 | 4.397569 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/uart/uart.vhd | 1 | 2,866 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- package: uart
-- File: uart.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: UART types and components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
package uart is
type uart_in_type is record
rxd : std_ulogic;
ctsn : std_ulogic;
extclk : std_ulogic;
end record;
type uart_in_vector_type is array (natural range <>) of uart_in_type;
type uart_out_type is record
rtsn : std_ulogic;
txd : std_ulogic;
scaler : std_logic_vector(31 downto 0);
txen : std_ulogic;
flow : std_ulogic;
rxen : std_ulogic;
end record;
type uart_out_vector_type is array (natural range <>) of uart_out_type;
component apbuart
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
console : integer := 0;
pirq : integer := 0;
parity : integer := 1;
flow : integer := 1;
fifosize : integer range 1 to 32 := 1;
abits : integer := 8;
sbits : integer range 12 to 32 := 12);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
uarti : in uart_in_type;
uarto : out uart_out_type);
end component;
component ahbuart
generic (
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
uarti : in uart_in_type;
uarto : out uart_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type);
end component;
end;
| gpl-3.0 | 6c856cae2d95f451a4705c3339d3fce1 | 0.584438 | 3.660281 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/i2c/i2c2ahbx.vhd | 1 | 18,529 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: i2c2ahbx
-- File: i2c2ahbx.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- Contact: [email protected]
-- Description: Simple I2C-slave providing a bridge to AMBA AHB
-- This entity is typically wrapped with i2c2ahb or i2c2ahb_apb
-- before use.
-------------------------------------------------------------------------------
--
-- Short core documentation, for additional information see the GRLIB IP
-- Library User's Manual (GRIP):
--
-- The core functions as a I2C memory device. To write to the core, issue the
-- following I2C bus sequence:
--
-- 0. START condition
-- 1. Send core's I2C address with direction = write
-- 2. Send 32-bit address to be used for AMBA bus
-- 3. Send data to be written
--
-- The core will expect 32-bits of data and write these as a word. This can be
-- changed by writing to the core's control register. See documentation further
-- down. When the core's internal FIFO is full, the core will use clock
-- stretching to stall the transfer.
--
-- To write to the core, issue the following I2C bus sequence:
--
-- 0. START condition
-- 1. Send core's I2C address with direction = write
-- 2. Send 32-bit address to be used for AMBA bus
-- 3. Send repeated start condition
-- 4. Send core's I2C address with direction = read
-- 5. Read bytes
--
-- The core will perform 32-bit data accesses to fill its internal buffer. This
-- can be changed by writing to the core's control register (see documentation
-- further down). When the buffer is empty the core will use clock stretching
-- to stall the transfer.
--
-- The cores control/status register is accessed via address i2caddr + 1. The
-- register has the following layout:
--
-- +--------+-----------------------------------------------------------------+
-- | Bit(s) | Description |
-- +--------+-----------------------------------------------------------------+
-- | 7:6 | Reserved, always zero (RO) |
-- | 5 | PROT: Memory protection triggered. Last access was outside |
-- | | range. Updated after each AMBA access (RO) |
-- | 4 | MEXC: Memory exception. Gets set if core receives AMBA ERROR |
-- | | response. Updated after each AMBA access. (RO) |
-- | 3 | DMAACT: Core is currently performing DMA (RO) |
-- | 2 | NACK: NACK instead of using clock stretching (RW) |
-- | 1:0 | HSIZE: Controls the access size core will use for AMBA accesses |
-- | | Default is HSIZE = WORD. HSIZE 11 is illegal (RW) |
-- +--------+-----------------------------------------------------------------+
--
-- Documentation of generics:
--
-- [hindex] AHB master index
--
-- [oepol] Output enable polarity
--
-- [filter] Length of filters used on SCL and SDA
--
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.i2c.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
entity i2c2ahbx is
generic (
-- AHB configuration
hindex : integer := 0;
oepol : integer range 0 to 1 := 0;
filter : integer range 2 to 512 := 2
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
-- I2C signals
i2ci : in i2c_in_type;
i2co : out i2c_out_type;
--
i2c2ahbi : in i2c2ahb_in_type;
i2c2ahbo : out i2c2ahb_out_type
);
end entity i2c2ahbx;
architecture rtl of i2c2ahbx is
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
constant OEPOL_LEVEL : std_ulogic := conv_std_logic(oepol = 1);
constant I2C_LOW : std_ulogic := OEPOL_LEVEL; -- OE
constant I2C_HIZ : std_ulogic := not OEPOL_LEVEL;
constant I2C_ACK : std_ulogic := '0';
-----------------------------------------------------------------------------
-- Types
-----------------------------------------------------------------------------
type i2c_in_array is array (filter downto 0) of i2c_in_type;
type state_type is (idle, checkaddr, sclhold, movebyte, handshake);
type i2c2ahb_reg_type is record
state : state_type;
--
haddr : std_logic_vector(31 downto 0);
hdata : std_logic_vector(31 downto 0);
hsize : std_logic_vector(1 downto 0);
hwrite : std_ulogic;
mexc : std_ulogic;
dodma : std_ulogic;
nack : std_ulogic;
prot : std_ulogic;
-- Transfer phase
i2caddr : std_ulogic;
ahbacc : std_ulogic;
ahbadd : std_ulogic;
rec : std_ulogic;
bcnt : std_logic_vector(1 downto 0);
-- Shift register
sreg : std_logic_vector(7 downto 0);
cnt : std_logic_vector(2 downto 0);
-- Synchronizers for inputs SCL and SDA
scl : std_ulogic;
sda : std_ulogic;
i2ci : i2c_in_array;
-- Output enables
scloen : std_ulogic;
sdaoen : std_ulogic;
end record;
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal ami : ahb_dma_in_type;
signal amo : ahb_dma_out_type;
signal r, rin : i2c2ahb_reg_type;
begin
-- Generic AHB master interface
ahbmst0 : ahbmst
generic map (hindex => hindex, hirq => 0, venid => VENDOR_GAISLER,
devid => GAISLER_I2C2AHB, version => 0,
chprot => 3, incaddr => 0)
port map (rstn, clk, ami, amo, ahbi, ahbo);
comb: process (r, rstn, i2ci, amo, i2c2ahbi)
variable v : i2c2ahb_reg_type;
variable sclfilt : std_logic_vector(filter-1 downto 0);
variable sdafilt : std_logic_vector(filter-1 downto 0);
variable hrdata : std_logic_vector(31 downto 0);
variable ahbreq : std_ulogic;
variable slv : std_ulogic;
variable cfg : std_ulogic;
variable lb : std_ulogic;
begin
v := r; ahbreq := '0'; slv := '0'; cfg := '0'; lb := '0';
hrdata := (others => '0');
v.i2ci(0) := i2ci; v.i2ci(filter downto 1) := r.i2ci(filter-1 downto 0);
----------------------------------------------------------------------------
-- Bus filtering
----------------------------------------------------------------------------
for i in 0 to filter-1 loop
sclfilt(i) := r.i2ci(i+1).scl; sdafilt(i) := r.i2ci(i+1).sda;
end loop; -- i
if andv(sclfilt) = '1' then v.scl := '1'; end if;
if orv(sclfilt) = '0' then v.scl := '0'; end if;
if andv(sdafilt) = '1' then v.sda := '1'; end if;
if orv(sdafilt) = '0' then v.sda := '0'; end if;
---------------------------------------------------------------------------
-- DMA control
---------------------------------------------------------------------------
if r.dodma = '1' then
if amo.active = '1' then
if amo.ready = '1' then
hrdata := ahbreadword(amo.rdata);
case r.hsize is
when "00" =>
v.haddr := r.haddr + 1;
for i in 1 to 3 loop
if i = conv_integer(r.haddr(1 downto 0)) then
hrdata(31 downto 24) := hrdata(31-8*i downto 24-8*i);
end if;
end loop;
when "01" =>
v.haddr := r.haddr + 2;
if r.haddr(1) = '1' then
hrdata(31 downto 16) := hrdata(15 downto 0);
end if;
when others =>
v.haddr := r.haddr + 4;
end case;
v.sreg := hrdata(31 downto 24);
v.hdata(31 downto 8) := hrdata(23 downto 0);
v.mexc := '0';
v.dodma := '0';
end if;
if amo.mexc = '1' then
v.mexc := '1';
v.dodma := '0';
end if;
else
ahbreq := '1';
end if;
end if;
---------------------------------------------------------------------------
-- I2C slave control FSM
---------------------------------------------------------------------------
case r.state is
when idle =>
-- Release bus
if (r.scl and not v.scl) = '1' then
v.sdaoen := I2C_HIZ;
end if;
when checkaddr =>
if r.sreg(7 downto 1) = i2c2ahbi.slvaddr then slv := '1'; end if;
if r.sreg(7 downto 1) = i2c2ahbi.cfgaddr then cfg := '1'; end if;
v.rec := not r.sreg(0);
if (slv or cfg) = '1' then
if (slv and r.dodma) = '1' then
-- Core is busy performing DMA
if r.nack = '1' then v.state := idle;
else v.state := sclhold; end if;
else
v.state := handshake;
end if;
else
-- Slave address did not match
v.state := idle;
end if;
v.hwrite := v.rec;
if (slv and not r.dodma) = '1' then v.dodma := not v.rec; end if;
v.ahbacc := slv; v.bcnt := "00"; v.ahbadd := '0';
when sclhold =>
-- This state is used when the device has been addressed to see if SCL
-- should be kept low until the core is ready to process another
-- transfer. It is also used when a data byte has been transmitted or
-- received to keep SCL low until a DMA operation has completed.
-- In the transmit case we keep SCL low before the rising edge of the
-- first byte, so we go directly to move byte. In the receive case we
-- stretch the ACK cycle so we jump to handshake next.
if (r.scl and not v.scl) = '1' then
v.scloen := I2C_LOW;
v.sdaoen := I2C_HIZ;
end if;
if r.dodma = '0' then
if (not r.rec and not r.i2caddr) = '1' then
v.state := movebyte;
else
v.state := handshake;
end if;
v.scloen := I2C_HIZ;
-- Falling edge that should be detected in movebyte may have passed
if (r.i2caddr or r.rec or v.scl) = '0' then
v.sdaoen := r.sreg(7) xor OEPOL_LEVEL;
end if;
end if;
when movebyte =>
if (r.scl and not v.scl) = '1' then
if (r.i2caddr or r.rec) = '0' then
v.sdaoen := r.sreg(7) xor OEPOL_LEVEL;
else
v.sdaoen := I2C_HIZ;
end if;
end if;
if (not r.scl and v.scl) = '1' then
v.sreg := r.sreg(6 downto 0) & r.sda;
if r.cnt = "111" then
if r.i2caddr = '1' then
v.state := checkaddr;
else
v.state := handshake;
end if;
v.cnt := (others => '0');
else
v.cnt := r.cnt + 1;
end if;
end if;
when handshake =>
if ((r.hsize = "00") or ((r.hsize(0) and r.bcnt(0)) = '1') or
(r.bcnt = "11")) then
lb := '1';
end if;
-- Falling edge
if (r.scl and not v.scl) = '1' then
if (r.i2caddr or not r.ahbacc) = '1' then
-- Also handles first byte on AHB read access
if (r.rec or r.i2caddr) = '1' then
v.sdaoen := I2C_LOW;
else
v.sdaoen := I2C_HIZ;
end if;
if (not r.i2caddr and r.rec) = '1' then
-- Control register access
v.nack := r.sreg(2);
v.hsize := r.sreg(1 downto 0);
end if;
else
-- AHB access
if r.rec = '1' then
-- First we need a 4 byte address, then we handle data.
v.bcnt := r.bcnt + 1;
if r.ahbadd = '0' then
-- We could check if the address is within the allowed memory
-- area here, and nack otherwise, but we do it when the access
-- is performed instead, to have one check for all cases.
v.haddr := r.haddr(23 downto 0) & r.sreg;
if r.bcnt = "11" then v.ahbadd := '1'; end if;
v.sdaoen := I2C_LOW;
elsif r.dodma = '0' then
if r.bcnt = "00" then v.hdata(31 downto 24) := r.sreg; end if;
if r.bcnt(1) = '0' then v.hdata(23 downto 16) := r.sreg; end if;
if r.bcnt(0) = '0' then v.hdata(15 downto 8) := r.sreg; end if;
v.hdata(7 downto 0) := r.sreg;
if lb = '1' then v.dodma := '1'; v.bcnt := "00"; end if;
v.sdaoen := I2C_LOW;
end if;
else
-- Transmit, release bus
v.sdaoen := I2C_HIZ;
end if;
end if;
-- Previous DMA is not finished yet
if (r.dodma and r.ahbacc) = '1' then
if r.nack = '0' then
-- Hold clock low and handle data when DMA is finished
v.state := sclhold;
v.scloen := I2C_LOW;
else
-- NAK byte
v.sdaoen := I2C_HIZ;
v.state := idle;
end if;
end if;
end if;
-- Risinge edge
if (not r.scl and v.scl) = '1' then
if (r.i2caddr or not r.ahbacc) = '1' then
if r.sda = I2C_ACK then
v.state := movebyte;
else
v.state := idle;
end if;
else
if r.rec = '1' then
v.state := movebyte;
else
-- Transmit, check ACK/NAK from master
-- If the master NAKs the transmitted byte the transfer has ended
-- and we should wait for the master's next action. If the master
-- ACKs the byte the core we will continue to transmit data until
-- we reach the last available byte. When the last byte has been
-- transmitted we will act depending on if we are allowed to enter
-- sclhold. If we can, we enter sclhold and start a new DMA
-- operation, otherwise we stop communicating until the next start
-- condition.
v.bcnt := r.bcnt + 1;
if r.sda = I2C_ACK then
if lb = '1' then
if r.nack = '1' then
v.state := idle;
else
v.dodma := '1'; v.bcnt := "00";
v.state := sclhold;
end if;
else
v.state := movebyte;
end if;
else
v.state := idle;
end if;
v.hdata(31 downto 8) := r.hdata(23 downto 0);
v.sreg := r.hdata(31 downto 24);
end if;
end if;
v.i2caddr := '0';
if r.ahbacc = '0' then
-- Control register access
v.sreg := zero32(7 downto 6) & r.prot & r.mexc &
r.dodma & r.nack & r.hsize;
end if;
end if;
end case;
if i2c2ahbi.hmask /= zero32 then
if v.dodma = '1' then
if ((i2c2ahbi.haddr xor r.haddr) and i2c2ahbi.hmask) /= zero32 then
v.dodma := '0';
v.prot := '1';
v.state := idle;
else
v.prot := '0';
end if;
end if;
else
v.prot := '0';
end if;
if i2c2ahbi.en = '1' then
-- STOP condition
if (r.scl and v.scl and not r.sda and v.sda) = '1' then
v.state := idle;
end if;
-- START or repeated START condition
if (r.scl and v.scl and r.sda and not v.sda) = '1' then
v.state := movebyte;
v.cnt := (others => '0');
v.i2caddr := '1';
end if;
end if;
----------------------------------------------------------------------------
-- Reset
----------------------------------------------------------------------------
if rstn = '0' then
v.state := idle;
v.hsize := HSIZE_WORD(1 downto 0);
v.mexc := '0';
v.dodma := '0';
v.nack := '0';
v.prot := '0';
v.scl := '0';
v.scloen := I2C_HIZ; v.sdaoen := I2C_HIZ;
end if;
if i2c2ahbi.hmask = zero32 then v.prot := '0'; end if;
----------------------------------------------------------------------------
-- Signal assignments
----------------------------------------------------------------------------
-- Core registers
rin <= v;
-- AHB master control
ami.address <= r.haddr;
ami.wdata <= ahbdrivedata(r.hdata);
ami.start <= ahbreq;
ami.burst <= '0';
ami.write <= r.hwrite;
ami.busy <= '0';
ami.irq <= '0';
ami.size <= '0' & r.hsize;
-- Update outputs
i2c2ahbo.dma <= r.dodma;
i2c2ahbo.wr <= r.hwrite;
i2c2ahbo.prot <= r.prot;
i2co.scl <= '0';
i2co.scloen <= r.scloen;
i2co.sda <= '0';
i2co.sdaoen <= r.sdaoen;
i2co.enable <= i2c2ahbi.en;
end process comb;
reg: process (clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process reg;
-- Boot message
-- pragma translate_off
bootmsg : report_version
generic map ("i2c2ahb" & tost(hindex) & ": I2C to AHB bridge");
-- pragma translate_on
end architecture rtl;
| gpl-3.0 | 69eebd93d673866e0db25d8afdd2e2a4 | 0.475309 | 3.889379 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/jtag/jtagcom2.vhd | 1 | 10,083 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: jtagcom
-- File: jtagcom.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: JTAG Debug Interface with AHB master interface
-- Redesigned to work for TCK both slower and faster than AHB
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.libjtagcom.all;
use gaisler.misc.all;
entity jtagcom2 is
generic (
gatetech: integer := 0;
isel : integer range 0 to 1 := 0;
ainst : integer range 0 to 255 := 2;
dinst : integer range 0 to 255 := 3);
port (
rst : in std_ulogic;
clk : in std_ulogic;
tapo : in tap_out_type;
tapi : out tap_in_type;
dmao : in ahb_dma_out_type;
dmai : out ahb_dma_in_type;
tckp : in std_ulogic;
tckn : in std_ulogic;
trst : in std_ulogic
);
attribute sync_set_reset of rst : signal is "true";
end;
architecture rtl of jtagcom2 is
constant ADDBITS : integer := 10;
constant NOCMP : boolean := (isel /= 0);
type tckpreg_type is record
addr : std_logic_vector(34 downto 0);
datashft : std_logic_vector(32 downto 0);
done_sync : std_ulogic;
prun : std_ulogic;
inshift : std_ulogic;
holdn : std_ulogic;
end record;
type tcknreg_type is record
run: std_ulogic;
done_sync1: std_ulogic;
qual_rdata: std_ulogic;
addrlo : std_logic_vector(ADDBITS-1 downto 2);
data : std_logic_vector(32 downto 0);
end record;
type ahbreg_type is record
run_sync: std_logic_vector(2 downto 0);
qual_dreg: std_ulogic;
qual_areg: std_ulogic;
areg: std_logic_vector(34 downto 0);
dreg: std_logic_vector(31 downto 0);
done: std_ulogic;
dmastart: std_ulogic;
wdone: std_ulogic;
end record;
signal ar, arin : ahbreg_type;
signal tpr, tprin: tckpreg_type;
signal tnr, tnrin: tcknreg_type;
signal qual_rdata, rdataq: std_logic_vector(31 downto 0);
signal qual_dreg, dregq: std_logic_vector(31 downto 0);
signal qual_areg, aregqin, aregq: std_logic_vector(34 downto 0);
attribute syn_keep: boolean;
attribute syn_keep of rdataq : signal is true;
attribute syn_keep of dregq : signal is true;
attribute syn_keep of aregq : signal is true;
----
attribute syn_preserve: boolean;
attribute syn_keep of ar : signal is true;
attribute syn_keep of tnr : signal is true;
attribute syn_keep of tpr : signal is true;
attribute syn_keep of arin : signal is true;
attribute syn_keep of tnrin : signal is true;
attribute syn_preserve of ar : signal is true;
attribute syn_preserve of tnr : signal is true;
attribute syn_preserve of tpr : signal is true;
attribute syn_preserve of rdataq : signal is true;
attribute syn_preserve of dregq : signal is true;
attribute syn_preserve of aregq : signal is true;
----
begin
rdqgen: for x in 31 downto 0 generate
rdq: grnand2 generic map (tech => gatetech) port map (ar.dreg(x), qual_rdata(x), rdataq(x));
end generate;
dqgen: for x in 31 downto 0 generate
dq: grnand2 generic map (tech => gatetech) port map (tnr.data(x), qual_dreg(x), dregq(x));
end generate;
aregqin <= tpr.addr(34 downto ADDBITS) &
tnr.addrlo(ADDBITS-1 downto 2) &
tpr.addr(1 downto 0);
aqgen: for x in 34 downto 0 generate
aq: grnand2 generic map (tech => gatetech) port map (aregqin(x), qual_areg(x), aregq(x));
end generate;
comb : process (rst, ar, tapo, dmao, tpr, tnr, aregq, dregq, rdataq)
variable av : ahbreg_type;
variable tpv : tckpreg_type;
variable tnv : tcknreg_type;
variable vdmai : ahb_dma_in_type;
variable asel, dsel : std_ulogic;
variable vtapi : tap_in_type;
variable write, seq : std_ulogic;
begin
av := ar; tpv := tpr; tnv := tnr;
---------------------------------------------------------------------------
-- TCK side logic
---------------------------------------------------------------------------
if NOCMP then
asel := tapo.asel; dsel := tapo.dsel;
else
if tapo.inst = conv_std_logic_vector(ainst, 8) then asel := '1'; else asel := '0'; end if;
if tapo.inst = conv_std_logic_vector(dinst, 8) then dsel := '1'; else dsel := '0'; end if;
end if;
vtapi.en := asel or dsel;
vtapi.tdo:=tpr.addr(0);
if dsel='1' then
vtapi.tdo:=tpr.datashft(0) and tpr.holdn;
end if;
write := tpr.addr(34); seq := tpr.datashft(32);
-- Sync regs using alternating phases
tnv.done_sync1 := ar.done;
tpv.done_sync := tnr.done_sync1;
-- Data CDC
qual_rdata <= (others => tnr.qual_rdata);
if tnr.qual_rdata='1' then tpv.datashft(32 downto 0) := '1' & (not rdataq); end if;
if tapo.capt='1' then tpv.addr(ADDBITS-1 downto 2) := tnr.addrlo; end if;
-- Track whether we're in the middle of shifting
if tapo.shift='1' then tpv.inshift:='1'; end if;
if tapo.upd='1' then tpv.inshift:='0'; end if;
if tapo.shift='1' then
if asel = '1' and tpr.prun='0' then tpv.addr(34 downto 0) := tapo.tdi & tpr.addr(34 downto 1); end if;
if dsel = '1' and tpr.holdn='1' then tpv.datashft(32 downto 0) := tapo.tdi & tpr.datashft(32 downto 1); end if;
end if;
if tnr.run='0' then tpv.holdn:='1'; end if;
tpv.prun := tnr.run;
if tpr.prun='0' then
tnv.qual_rdata := '0';
if tapo.shift='0' and tapo.upd = '1' then
if asel='1' then tnv.addrlo := tpr.addr(ADDBITS-1 downto 2); end if;
if dsel='1' then tnv.data := tpr.datashft; end if;
if (asel and not write) = '1' then tpv.holdn := '0'; tnv.run := '1'; end if;
if (dsel and (write or (not write and seq))) = '1' then
tnv.run := '1';
if (seq and not write) = '1' then
if tpr.inshift='1' then
tnv.addrlo := tnr.addrlo + 1;
end if;
tpv.holdn := '0';
end if;
end if;
end if;
else
if tpr.done_sync='1' and (tpv.inshift='0' or write='1') then
tnv.run := '0';
if write='0' then
tnv.qual_rdata := '1';
end if;
if (write and tnr.data(32)) = '1' then
tnv.addrlo := tnr.addrlo + 1;
end if;
end if;
end if;
if tapo.reset='1' then
tpv.inshift := '0';
tnv.run := '0';
end if;
---------------------------------------------------------------------------
-- AHB side logic
---------------------------------------------------------------------------
-- Sync regs and CDC transfer
av.run_sync := tnr.run & ar.run_sync(2) & ar.run_sync(1);
qual_dreg <= (others => ar.qual_dreg);
if ar.qual_dreg='1' then av.dreg:=not dregq; end if;
qual_areg <= (others => ar.qual_areg);
if ar.qual_areg='1' then av.areg:=not aregq; end if;
vdmai.address := ar.areg(31 downto 0);
vdmai.wdata := ahbdrivedata(ar.dreg(31 downto 0));
vdmai.start := '0'; vdmai.burst := '0';
vdmai.write := ar.areg(34);
vdmai.busy := '0'; vdmai.irq := '0';
vdmai.size := '0' & ar.areg(33 downto 32);
av.qual_dreg := '0';
av.qual_areg := '0';
vdmai.start := '0';
if ar.dmastart='1' then
if dmao.active='1' then
if dmao.ready='1' then
av.dreg := ahbreadword(dmao.rdata);
if ar.areg(34)='0' then
av.done := '1';
end if;
av.dmastart := '0';
end if;
else
vdmai.start := '1';
if ar.areg(34)='1' and ar.wdone='0' then
av.done := '1';
av.wdone := '1';
end if;
end if;
end if;
if ar.qual_areg='1' then
av.dmastart := '1';
av.wdone := '0';
end if;
if ar.run_sync(0)='1' and ar.qual_areg='0' and ar.dmastart='0' and ar.done='0' then
av.qual_dreg := '1';
av.qual_areg := '1';
end if;
if ar.run_sync(0)='0' and ar.done='1' then
av.done := '0';
end if;
if (rst = '0') then
av.qual_dreg := '0';
av.qual_areg := '0';
av.done := '0';
av.areg := (others => '0');
av.dreg := (others => '0');
av.dmastart := '0';
av.run_sync := (others => '0');
end if;
tprin <= tpv; tnrin <= tnv; arin <= av; dmai <= vdmai; tapi <= vtapi;
end process;
ahbreg : process(clk)
begin
if rising_edge(clk) then ar <= arin; end if;
end process;
tckpreg: process(tckp,trst)
begin
if rising_edge(tckp) then
tpr <= tprin;
end if;
if trst='0' then
tpr.done_sync <= '0';
tpr.prun <= '0';
tpr.inshift <= '0';
tpr.holdn <= '1';
tpr.datashft(0) <= '0';
end if;
end process;
tcknreg: process(tckn,trst)
begin
if rising_edge(tckn) then
tnr <= tnrin;
end if;
if trst='0' then
tnr.run <= '0';
tnr.done_sync1 <= '0';
tnr.qual_rdata <= '0';
end if;
end process;
end;
| gpl-3.0 | 946fa67f6a4a0bf540edde24a95841f0 | 0.563523 | 3.406419 | false | false | false | false |
hoglet67/CoPro6502 | src/T80/DebugSystem.vhd | 1 | 3,942 | -- Z80, Monitor ROM, 4k RAM and two 16450 UARTs
-- that can be synthesized and used with
-- the NoICE debugger that can be found at
-- http://www.noicedebugger.com/
library IEEE;
use IEEE.std_logic_1164.all;
entity DebugSystem is
port(
Reset_n : in std_logic;
Clk : in std_logic;
NMI_n : in std_logic;
RXD0 : in std_logic;
CTS0 : in std_logic;
DSR0 : in std_logic;
RI0 : in std_logic;
DCD0 : in std_logic;
RXD1 : in std_logic;
CTS1 : in std_logic;
DSR1 : in std_logic;
RI1 : in std_logic;
DCD1 : in std_logic;
TXD0 : out std_logic;
RTS0 : out std_logic;
DTR0 : out std_logic;
TXD1 : out std_logic;
RTS1 : out std_logic;
DTR1 : out std_logic
);
end DebugSystem;
architecture struct of DebugSystem is
signal M1_n : std_logic;
signal MREQ_n : std_logic;
signal IORQ_n : std_logic;
signal RD_n : std_logic;
signal WR_n : std_logic;
signal RFSH_n : std_logic;
signal HALT_n : std_logic;
signal WAIT_n : std_logic;
signal INT_n : std_logic;
signal RESET_s : std_logic;
signal BUSRQ_n : std_logic;
signal BUSAK_n : std_logic;
signal A : std_logic_vector(15 downto 0);
signal D : std_logic_vector(7 downto 0);
signal ROM_D : std_logic_vector(7 downto 0);
signal SRAM_D : std_logic_vector(7 downto 0);
signal UART0_D : std_logic_vector(7 downto 0);
signal UART1_D : std_logic_vector(7 downto 0);
signal CPU_D : std_logic_vector(7 downto 0);
signal Mirror : std_logic;
signal IOWR_n : std_logic;
signal RAMCS_n : std_logic;
signal UART0CS_n : std_logic;
signal UART1CS_n : std_logic;
signal BaudOut0 : std_logic;
signal BaudOut1 : std_logic;
begin
Wait_n <= '1';
BusRq_n <= '1';
INT_n <= '1';
process (Reset_n, Clk)
begin
if Reset_n = '0' then
Reset_s <= '0';
Mirror <= '0';
elsif Clk'event and Clk = '1' then
Reset_s <= '1';
if IORQ_n = '0' and A(7 downto 4) = "1111" then
Mirror <= D(0);
end if;
end if;
end process;
IOWR_n <= WR_n or IORQ_n;
RAMCS_n <= (not Mirror and not A(15)) or MREQ_n;
UART0CS_n <= '0' when IORQ_n = '0' and A(7 downto 3) = "00000" else '1';
UART1CS_n <= '0' when IORQ_n = '0' and A(7 downto 3) = "10000" else '1';
CPU_D <=
SRAM_D when RAMCS_n = '0' else
UART0_D when UART0CS_n = '0' else
UART1_D when UART1CS_n = '0' else
ROM_D;
u0 : entity work.T80s
generic map(Mode => 1, T2Write => 1, IOWait => 0)
port map(
RESET_n => RESET_s,
CLK_n => Clk,
WAIT_n => WAIT_n,
INT_n => INT_n,
NMI_n => NMI_n,
BUSRQ_n => BUSRQ_n,
M1_n => M1_n,
MREQ_n => MREQ_n,
IORQ_n => IORQ_n,
RD_n => RD_n,
WR_n => WR_n,
RFSH_n => RFSH_n,
HALT_n => HALT_n,
BUSAK_n => BUSAK_n,
A => A,
DI => CPU_D,
DO => D);
u1 : entity work.MonZ80
port map(
Clk => Clk,
A => A(10 downto 0),
D => ROM_D);
u2 : entity work.SSRAM
generic map(
AddrWidth => 12)
port map(
Clk => Clk,
CE_n => RAMCS_n,
WE_n => WR_n,
A => A(11 downto 0),
DIn => D,
DOut => SRAM_D);
u3 : entity work.T16450
port map(
MR_n => Reset_s,
XIn => Clk,
RClk => BaudOut0,
CS_n => UART0CS_n,
Rd_n => RD_n,
Wr_n => IOWR_n,
A => A(2 downto 0),
D_In => D,
D_Out => UART0_D,
SIn => RXD0,
CTS_n => CTS0,
DSR_n => DSR0,
RI_n => RI0,
DCD_n => DCD0,
SOut => TXD0,
RTS_n => RTS0,
DTR_n => DTR0,
OUT1_n => open,
OUT2_n => open,
BaudOut => BaudOut0,
Intr => open);
u4 : entity work.T16450
port map(
MR_n => Reset_s,
XIn => Clk,
RClk => BaudOut1,
CS_n => UART1CS_n,
Rd_n => RD_n,
Wr_n => IOWR_n,
A => A(2 downto 0),
D_In => D,
D_Out => UART1_D,
SIn => RXD1,
CTS_n => CTS1,
DSR_n => DSR1,
RI_n => RI1,
DCD_n => DCD1,
SOut => TXD1,
RTS_n => RTS1,
DTR_n => DTR1,
OUT1_n => open,
OUT2_n => open,
BaudOut => BaudOut1,
Intr => open);
end;
| gpl-3.0 | 0e09116203dfdd276fdc84f3c7b3ef83 | 0.554541 | 2.277296 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/leon3v3/iu3.vhd | 1 | 185,772 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iu3
-- File: iu3.vhd
-- Author: Jiri Gaisler, Edvin Catovic, Gaisler Research
-- Modified: Magnus Hjorth, Cobham Gaisler (LEON-REX extension)
-- Description: LEON3 7-stage integer pipline
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.sparc.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libiu.all;
use gaisler.libfpu.all;
use gaisler.arith.all;
-- pragma translate_off
use grlib.sparc_disas.all;
-- pragma translate_on
entity iu3 is
generic (
nwin : integer range 2 to 32 := 8;
isets : integer range 1 to 4 := 1;
dsets : integer range 1 to 4 := 1;
fpu : integer range 0 to 15 := 0;
v8 : integer range 0 to 63 := 0;
cp, mac : integer range 0 to 1 := 0;
dsu : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
index : integer range 0 to 15:= 0;
lddel : integer range 1 to 2 := 2;
irfwt : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0; -- trace buf size in kB (0 - no trace buffer)
pwd : integer range 0 to 2 := 0; -- power-down
svt : integer range 0 to 1 := 0; -- single-vector trapping
rstaddr : integer := 16#00000#; -- reset vector MSB address
smp : integer range 0 to 15 := 0; -- support SMP systems
fabtech : integer range 0 to NTECH := 0;
clk2x : integer := 0;
bp : integer range 0 to 2 := 1;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0;
rex : integer range 0 to 1 := 0;
altwin : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
holdn : in std_ulogic;
ici : out icache_in_type;
ico : in icache_out_type;
dci : out dcache_in_type;
dco : in dcache_out_type;
rfi : out iregfile_in_type;
rfo : in iregfile_out_type;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
muli : out mul32_in_type;
mulo : in mul32_out_type;
divi : out div32_in_type;
divo : in div32_out_type;
fpo : in fpc_out_type;
fpi : out fpc_in_type;
cpo : in fpc_out_type;
cpi : out fpc_in_type;
tbo : in tracebuf_out_type;
tbi : out tracebuf_in_type;
tbo_2p : in tracebuf_2p_out_type;
tbi_2p : out tracebuf_2p_in_type;
sclk : in std_ulogic
);
attribute sync_set_reset of rstn : signal is "true";
end;
architecture rtl of iu3 is
function get_tbuf(tracebuf_2p: boolean; tbuf: integer) return integer is
begin
if (TRACEBUF_2P) then
return(tbuf-64);
else
return(tbuf);
end if;
end function get_tbuf;
constant ISETMSB : integer := log2x(isets)-1;
constant DSETMSB : integer := log2x(dsets)-1;
constant RFBITS : integer range 6 to 10 := log2(NWIN+1) + 4;
constant NWINLOG2 : integer range 1 to 5 := log2(NWIN);
constant CWPOPT : boolean := (NWIN = (2**NWINLOG2));
constant CWPMIN : std_logic_vector(NWINLOG2-1 downto 0) := (others => '0');
constant CWPMAX : std_logic_vector(NWINLOG2-1 downto 0) :=
conv_std_logic_vector(NWIN-1, NWINLOG2);
constant CWPGLB : std_logic_vector(NWINLOG2-1 downto 0) :=
conv_std_logic_vector(NWIN, NWINLOG2);
constant FPEN : boolean := (fpu /= 0);
constant CPEN : boolean := (cp = 1);
constant MULEN : boolean := (v8 /= 0);
constant MULTYPE: integer := (v8 / 16);
constant DIVEN : boolean := (v8 /= 0);
constant MACEN : boolean := (mac = 1);
constant MACPIPE: boolean := (mac = 1) and (v8/2 = 1);
constant IMPL : integer := 15;
constant VER : integer := 3;
constant DBGUNIT : boolean := (dsu = 1);
constant TRACEBUF : boolean := (tbuf /= 0);
constant TRACEBUF_2P : boolean := (tbuf > 64);
constant TBUFBITS : integer := 10 + log2(get_tbuf(TRACEBUF_2P, tbuf)) - 4;
constant PWRD1 : boolean := false; --(pwd = 1) and not (index /= 0);
constant PWRD2 : boolean := (pwd /= 0); --(pwd = 2) or (index /= 0);
constant RS1OPT : boolean := (is_fpga(FABTECH) /= 0);
constant DYNRST : boolean := (rstaddr = 16#FFFFF#);
constant CASAEN : boolean := (notag = 0);
signal BPRED : std_logic;
signal BLOCKBPMISS: std_logic;
constant REXPIPE : boolean := (REX=1) and (is_fpga(FABTECH)/=0);
constant AWPEN : boolean := (altwin /= 0);
constant RFPART : boolean := (altwin /= 0);
subtype word is std_logic_vector(31 downto 0);
subtype pctype is std_logic_vector(31 downto PCLOW);
subtype rfatype is std_logic_vector(RFBITS-1 downto 0);
subtype cwptype is std_logic_vector(NWINLOG2-1 downto 0);
type icdtype is array (0 to isets-1) of word;
type dcdtype is array (0 to dsets-1) of word;
type dc_in_type is record
signed, enaddr, read, write, lock, dsuen : std_ulogic;
size : std_logic_vector(1 downto 0);
asi : std_logic_vector(7 downto 0);
end record;
type pipeline_ctrl_type is record
pc : pctype;
inst : word;
cnt : std_logic_vector(1 downto 0);
rd : rfatype;
tt : std_logic_vector(5 downto 0);
trap : std_ulogic;
annul : std_ulogic;
wreg : std_ulogic;
wicc : std_ulogic;
wy : std_ulogic;
ld : std_ulogic;
pv : std_ulogic;
rett : std_ulogic;
itovr : std_ulogic;
end record;
type fetch_reg_type is record
pc : pctype;
branch : std_ulogic;
end record;
type rex_pipeline_reg_type is record
opout: std_logic_vector(31 downto 0);
szout: std_logic_vector(1 downto 0);
ncntout: std_logic_vector(0 downto 0);
baddr1: std_ulogic;
immexp: std_ulogic;
immval: std_logic_vector(31 downto 13);
getpc: std_ulogic;
maskpv: std_ulogic;
illinst: std_ulogic;
nostep: std_ulogic;
itovr: std_ulogic;
leave: std_ulogic;
end record;
type decode_reg_type is record
pc : pctype;
inst : icdtype;
cwp : cwptype;
awp : cwptype;
aw : std_ulogic;
paw : std_ulogic;
stwin : cwptype;
cwpmax: cwptype;
set : std_logic_vector(ISETMSB downto 0);
mexc : std_ulogic;
cnt : std_logic_vector(1 downto 0);
pv : std_ulogic;
annul : std_ulogic;
inull : std_ulogic;
step : std_ulogic;
divrdy: std_ulogic;
pcheld: std_ulogic;
rexen : std_ulogic;
rexpos: std_logic_vector(1 downto 0);
rexbuf: std_logic_vector(31 downto 0);
rexcnt: std_logic_vector(0 downto 0);
rexpl : rex_pipeline_reg_type;
end record;
type regacc_reg_type is record
ctrl : pipeline_ctrl_type;
rs1 : std_logic_vector(4 downto 0);
rfa1, rfa2 : rfatype;
rsel1, rsel2 : std_logic_vector(2 downto 0);
rfe1, rfe2 : std_ulogic;
cwp : cwptype;
awp : cwptype;
aw : std_ulogic;
paw : std_ulogic;
imm : word;
ldcheck1 : std_ulogic;
ldcheck2 : std_ulogic;
ldchkra : std_ulogic;
ldchkex : std_ulogic;
su : std_ulogic;
et : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
jmpl : std_ulogic;
step : std_ulogic;
mulstart : std_ulogic;
divstart : std_ulogic;
bp, nobp : std_ulogic;
bpimiss : std_ulogic;
getpc : std_ulogic;
decill: std_ulogic;
end record;
type execute_reg_type is record
ctrl : pipeline_ctrl_type;
op1 : word;
op2 : word;
aluop : std_logic_vector(2 downto 0); -- Alu operation
alusel : std_logic_vector(1 downto 0); -- Alu result select
aluadd : std_ulogic;
alucin : std_ulogic;
ldbp1, ldbp2 : std_ulogic;
invop2 : std_ulogic;
shcnt : std_logic_vector(4 downto 0); -- shift count
sari : std_ulogic; -- shift msb
shleft : std_ulogic; -- shift left/right
ymsb : std_ulogic; -- shift left/right
rd : std_logic_vector(4 downto 0);
jmpl : std_ulogic;
su : std_ulogic;
et : std_ulogic;
cwp : cwptype;
awp : cwptype;
aw : std_ulogic;
paw : std_ulogic;
icc : std_logic_vector(3 downto 0);
mulstep: std_ulogic;
mul : std_ulogic;
mac : std_ulogic;
bp : std_ulogic;
rfe1, rfe2 : std_ulogic;
end record;
type memory_reg_type is record
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector(3 downto 0);
nalign : std_ulogic;
dci : dc_in_type;
werr : std_ulogic;
wcwp : std_ulogic;
wawp : std_ulogic;
irqen : std_ulogic;
irqen2 : std_ulogic;
mac : std_ulogic;
divz : std_ulogic;
su : std_ulogic;
mul : std_ulogic;
casa : std_ulogic;
casaz : std_ulogic;
rexnalign : std_ulogic;
end record;
type exception_state is (run, trap, dsu1, dsu2);
type exception_reg_type is record
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector( 3 downto 0);
annul_all : std_ulogic;
data : dcdtype;
set : std_logic_vector(DSETMSB downto 0);
mexc : std_ulogic;
dci : dc_in_type;
laddr : std_logic_vector(1 downto 0);
rstate : exception_state;
npc : std_logic_vector(2 downto 0);
intack : std_ulogic;
ipend : std_ulogic;
mac : std_ulogic;
debug : std_ulogic;
nerror : std_ulogic;
end record;
type dsu_registers is record
tt : std_logic_vector(7 downto 0);
err : std_ulogic;
tbufcnt : std_logic_vector(TBUFBITS-1 downto 0);
asi : std_logic_vector(7 downto 0);
crdy : std_logic_vector(2 downto 1); -- diag cache access ready
tfilt : std_logic_vector(3 downto 0); -- trace filter
cfc : std_logic_vector(4 downto 0); -- control-flow change
tlim : std_logic_vector(2 downto 0);
tov : std_ulogic;
tovb : std_ulogic;
end record;
type irestart_register is record
addr : pctype;
pwd : std_ulogic;
end record;
type pwd_register_type is record
pwd : std_ulogic;
error : std_ulogic;
end record;
type special_register_type is record
cwp : cwptype; -- current window pointer
icc : std_logic_vector(3 downto 0); -- integer condition codes
tt : std_logic_vector(7 downto 0); -- trap type
tba : std_logic_vector(19 downto 0); -- trap base address
wim : std_logic_vector(NWIN-1 downto 0); -- window invalid mask
pil : std_logic_vector(3 downto 0); -- processor interrupt level
ec : std_ulogic; -- enable CP
ef : std_ulogic; -- enable FP
ps : std_ulogic; -- previous supervisor flag
s : std_ulogic; -- supervisor flag
et : std_ulogic; -- enable traps
y : word;
asr18 : word;
svt : std_ulogic; -- enable traps
dwt : std_ulogic; -- disable write error trap
dbp : std_ulogic; -- disable branch prediction
dbprepl: std_ulogic; -- Disable speculative Icache miss/replacement
rexdis : std_ulogic; -- allow entering REX mode
rextrap: std_ulogic; -- trap on saverex/addrex instructions
aw : std_ulogic; -- use alternative window pointer
paw : std_ulogic; -- previous aw (for trap handler)
awp : cwptype; -- alternative window pointer
stwin : cwptype; -- starting window
cwpmax : cwptype; -- max cwp value
end record;
type write_reg_type is record
s : special_register_type;
result : word;
wa : rfatype;
wreg : std_ulogic;
except : std_ulogic;
twcwp : cwptype; -- trap wrap CWP (for regfile partitioning)
end record;
type registers is record
f : fetch_reg_type;
d : decode_reg_type;
a : regacc_reg_type;
e : execute_reg_type;
m : memory_reg_type;
x : exception_reg_type;
w : write_reg_type;
end record;
type exception_type is record
pri : std_ulogic;
ill : std_ulogic;
fpdis : std_ulogic;
cpdis : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
end record;
type watchpoint_register is record
addr : std_logic_vector(31 downto 2); -- watchpoint address
mask : std_logic_vector(31 downto 2); -- watchpoint mask
exec : std_ulogic; -- trap on instruction
load : std_ulogic; -- trap on load
store : std_ulogic; -- trap on store
end record;
type watchpoint_registers is array (0 to 3) of watchpoint_register;
function dbgexc(
r : registers; dbgi : l3_debug_in_type;
trap : std_ulogic;
tt : std_logic_vector(7 downto 0);
dsur : dsu_registers) return std_ulogic is
variable dmode : std_ulogic;
begin
dmode := '0';
if (not r.x.ctrl.annul and trap) = '1' then
if (((tt = "00" & TT_WATCH) and (dbgi.bwatch = '1')) or
((dbgi.bsoft = '1') and (tt = "10000001")) or
(dbgi.btrapa = '1') or
((dbgi.btrape = '1') and not ((tt(5 downto 0) = TT_PRIV) or
(tt(5 downto 0) = TT_FPDIS) or (tt(5 downto 0) = TT_WINOF) or
(tt(5 downto 0) = TT_WINUF) or (tt(5 downto 4) = "01") or (tt(7) = '1'))) or
(((not r.w.s.et) and dbgi.berror) = '1')) then
dmode := '1';
end if;
end if;
return(dmode);
end;
function dbgerr(r : registers; dbgi : l3_debug_in_type;
tt : std_logic_vector(7 downto 0))
return std_ulogic is
variable err : std_ulogic;
begin
err := not r.w.s.et;
if (((dbgi.dbreak = '1') and (tt = ("00" & TT_WATCH))) or
((dbgi.bsoft = '1') and (tt = ("10000001")))) then
err := '0';
end if;
return(err);
end;
procedure diagwr(r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
dbg : in l3_debug_in_type;
wpr : in watchpoint_registers;
s : out special_register_type;
vwpr : out watchpoint_registers;
asi : out std_logic_vector(7 downto 0);
pc, npc : out pctype;
tbufcnt : out std_logic_vector(TBUFBITS-1 downto 0);
tfilt : out std_logic_vector(3 downto 0);
wr : out std_ulogic;
addr : out std_logic_vector(9 downto 0);
data : out word;
fpcwr : out std_ulogic) is
variable i : integer range 0 to 3;
begin
s := r.w.s; pc := r.f.pc; npc := ir.addr; wr := '0';
vwpr := wpr; asi := dsur.asi; addr := (others => '0');
data := dbg.ddata;
tbufcnt := dsur.tbufcnt; fpcwr := '0'; tfilt := dsur.tfilt;
if (dbg.dsuen and dbg.denable and dbg.dwrite) = '1' then
case dbg.daddr(23 downto 20) is
when "0001" =>
if (dbg.daddr(16) = '1' and dbg.daddr(2) = '0' ) and TRACEBUF then -- trace buffer control reg
tbufcnt := dbg.ddata(TBUFBITS-1 downto 0);
tfilt := dbg.ddata(31 downto 28);
end if;
when "0011" => -- IU reg file
if dbg.daddr(12) = '0' then
wr := '1';
addr := (others => '0');
addr(RFBITS-1 downto 0) := dbg.daddr(RFBITS+1 downto 2);
else -- FPC
fpcwr := '1';
end if;
when "0100" => -- IU special registers
case dbg.daddr(7 downto 6) is
when "00" => -- IU regs Y - TBUF ctrl reg
case dbg.daddr(5 downto 2) is
when "0000" => -- Y
s.y := dbg.ddata;
when "0001" => -- PSR
s.cwp := dbg.ddata(NWINLOG2-1 downto 0);
s.icc := dbg.ddata(23 downto 20);
s.ec := dbg.ddata(13);
if FPEN then s.ef := dbg.ddata(12); end if;
s.pil := dbg.ddata(11 downto 8);
s.s := dbg.ddata(7);
s.ps := dbg.ddata(6);
s.et := dbg.ddata(5);
if AWPEN then
s.aw := dbg.ddata(15);
s.paw := dbg.ddata(14);
end if;
when "0010" => -- WIM
s.wim := dbg.ddata(NWIN-1 downto 0);
when "0011" => -- TBR
s.tba := dbg.ddata(31 downto 12);
s.tt := dbg.ddata(11 downto 4);
when "0100" => -- PC
pc := dbg.ddata(31 downto PCLOW);
when "0101" => -- NPC
npc := dbg.ddata(31 downto PCLOW);
when "0110" => --FSR
fpcwr := '1';
when "0111" => --CFSR
when "1001" => -- ASI reg
asi := dbg.ddata(7 downto 0);
when others =>
end case;
when "01" => -- ASR16 - ASR31
case dbg.daddr(5 downto 2) is
when "0001" => -- %ASR17
if bp = 2 then s.dbp := dbg.ddata(27); end if;
if bp = 2 then s.dbprepl := dbg.ddata(25); end if;
if rex=1 then
s.rexdis := dbg.ddata(22);
s.rextrap := dbg.ddata(21);
end if;
s.dwt := dbg.ddata(14);
s.svt := dbg.ddata(13);
when "0010" => -- %ASR18
if MACEN then s.asr18 := dbg.ddata; end if;
when "0100" => -- %ASR20
if AWPEN then
s.awp := dbg.ddata(NWINLOG2-1 downto 0);
end if;
if RFPART then
if dbg.ddata(15+NWINLOG2 downto 16) /= CWPMIN then
s.stwin := dbg.ddata(20+NWINLOG2 downto 21);
s.cwpmax := dbg.ddata(15+NWINLOG2 downto 16);
end if;
end if;
when "1000" => -- %ASR24 - %ASR31
vwpr(0).addr := dbg.ddata(31 downto 2);
vwpr(0).exec := dbg.ddata(0);
when "1001" =>
vwpr(0).mask := dbg.ddata(31 downto 2);
vwpr(0).load := dbg.ddata(1);
vwpr(0).store := dbg.ddata(0);
when "1010" =>
vwpr(1).addr := dbg.ddata(31 downto 2);
vwpr(1).exec := dbg.ddata(0);
when "1011" =>
vwpr(1).mask := dbg.ddata(31 downto 2);
vwpr(1).load := dbg.ddata(1);
vwpr(1).store := dbg.ddata(0);
when "1100" =>
vwpr(2).addr := dbg.ddata(31 downto 2);
vwpr(2).exec := dbg.ddata(0);
when "1101" =>
vwpr(2).mask := dbg.ddata(31 downto 2);
vwpr(2).load := dbg.ddata(1);
vwpr(2).store := dbg.ddata(0);
when "1110" =>
vwpr(3).addr := dbg.ddata(31 downto 2);
vwpr(3).exec := dbg.ddata(0);
when "1111" => --
vwpr(3).mask := dbg.ddata(31 downto 2);
vwpr(3).load := dbg.ddata(1);
vwpr(3).store := dbg.ddata(0);
when others => --
end case;
-- disabled due to bug in XST
-- i := conv_integer(dbg.daddr(4 downto 3));
-- if dbg.daddr(2) = '0' then
-- vwpr(i).addr := dbg.ddata(31 downto 2);
-- vwpr(i).exec := dbg.ddata(0);
-- else
-- vwpr(i).mask := dbg.ddata(31 downto 2);
-- vwpr(i).load := dbg.ddata(1);
-- vwpr(i).store := dbg.ddata(0);
-- end if;
when others =>
end case;
when others =>
end case;
end if;
end;
function asr17_gen ( r : in registers) return word is
variable asr17 : word;
variable fpu2 : integer range 0 to 3;
begin
asr17 := zero32;
asr17(31 downto 28) := conv_std_logic_vector(index, 4);
if bp = 2 then asr17(27) := r.w.s.dbp; end if;
if notag = 0 then asr17(26) := '1'; end if; -- CASA and tagged arith
if bp = 2 then asr17(25) := r.w.s.dbprepl;
elsif bp = 1 then asr17(25) := '1'; end if;
if rex=1 then
asr17(24 downto 23) := "01";
asr17(22) := r.w.s.rexdis;
asr17(21) := r.w.s.rextrap;
else
asr17(24 downto 23) := "00";
end if;
if (clk2x > 8) then
asr17(16 downto 15) := conv_std_logic_vector(clk2x-8, 2);
asr17(17) := '1';
elsif (clk2x > 0) then
asr17(16 downto 15) := conv_std_logic_vector(clk2x, 2);
end if;
asr17(14) := r.w.s.dwt;
if svt = 1 then asr17(13) := r.w.s.svt; end if;
if lddel = 2 then asr17(12) := '1'; end if;
if (fpu > 0) and (fpu < 8) then fpu2 := 1;
elsif (fpu >= 8) and (fpu < 15) then fpu2 := 3;
elsif fpu = 15 then fpu2 := 2;
else fpu2 := 0; end if;
asr17(11 downto 10) := conv_std_logic_vector(fpu2, 2);
if mac = 1 then asr17(9) := '1'; end if;
if v8 /= 0 then asr17(8) := '1'; end if;
asr17(7 downto 5) := conv_std_logic_vector(nwp, 3);
asr17(4 downto 0) := conv_std_logic_vector(nwin-1, 5);
return(asr17);
end;
procedure diagread(dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
wpr : in watchpoint_registers;
dco : in dcache_out_type;
tbufo : in tracebuf_out_type;
tbufo_2p : in tracebuf_2p_out_type;
xc_wimmask: in std_logic_vector;
data : out word) is
variable cwp : std_logic_vector(4 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable i : integer range 0 to 3;
begin
data := (others => '0'); cwp := (others => '0');
cwp(NWINLOG2-1 downto 0) := r.w.s.cwp;
case dbgi.daddr(22 downto 20) is
when "001" => -- trace buffer
if TRACEBUF then
if dbgi.daddr(16) = '1' then -- trace buffer control reg
if dbgi.daddr(2) = '0' then
data(TBUFBITS-1 downto 0) := dsur.tbufcnt;
data(31 downto 28) := dsur.tfilt;
else
data(23) := dsur.tov;
data(26 downto 24) := dsur.tlim;
data(27) := dsur.tovb;
end if;
else
if TRACEBUF_2P then
case dbgi.daddr(3 downto 2) is
when "00" => data := tbufo_2p.data(127 downto 96);
when "01" => data := tbufo_2p.data(95 downto 64);
when "10" => data := tbufo_2p.data(63 downto 32);
when others => data := tbufo_2p.data(31 downto 0);
end case;
else
case dbgi.daddr(3 downto 2) is
when "00" => data := tbufo.data(127 downto 96);
when "01" => data := tbufo.data(95 downto 64);
when "10" => data := tbufo.data(63 downto 32);
when others => data := tbufo.data(31 downto 0);
end case;
end if;
end if;
end if;
when "011" => -- IU reg file
if dbgi.daddr(12) = '0' then
if dbgi.daddr(11) = '0' then
data := rfo.data1(31 downto 0);
else data := rfo.data2(31 downto 0); end if;
else
data := fpo.dbg.data;
end if;
when "100" => -- IU regs
case dbgi.daddr(7 downto 6) is
when "00" => -- IU regs Y - TBUF ctrl reg
case dbgi.daddr(5 downto 2) is
when "0000" =>
data := r.w.s.y;
when "0001" =>
data := conv_std_logic_vector(IMPL, 4) & conv_std_logic_vector(VER, 4) &
r.w.s.icc & "000000" & r.w.s.ec & r.w.s.ef & r.w.s.pil &
r.w.s.s & r.w.s.ps & r.w.s.et & cwp;
if AWPEN then
data(15) := r.w.s.aw;
data(14) := r.w.s.paw;
end if;
when "0010" =>
data(NWIN-1 downto 0) := r.w.s.wim;
if RFPART then data(NWIN-1 downto 0) := r.w.s.wim and not xc_wimmask; end if;
when "0011" =>
data := r.w.s.tba & r.w.s.tt & "0000";
when "0100" =>
data(31 downto PCLOW) := r.f.pc;
when "0101" =>
data(31 downto PCLOW) := ir.addr;
when "0110" => -- FSR
data := fpo.dbg.data;
when "0111" => -- CPSR
when "1000" => -- TT reg
data(12 downto 4) := dsur.err & dsur.tt;
when "1001" => -- ASI reg
data(7 downto 0) := dsur.asi;
when others =>
end case;
when "01" =>
if dbgi.daddr(5) = '0' then
if dbgi.daddr(4 downto 2) = "001" then -- %ASR17
data := asr17_gen(r);
elsif MACEN and dbgi.daddr(4 downto 2) = "010" then -- %ASR18
data := r.w.s.asr18;
elsif (AWPEN or RFPART) and dbgi.daddr(4 downto 2) = "100" then -- %ASR20
if AWPEN then
data(NWINLOG2-1 downto 0) := r.w.s.awp;
end if;
if RFPART then
data(15+NWINLOG2 downto 16) := r.w.s.cwpmax;
data(20+NWINLOG2 downto 21) := r.w.s.stwin;
end if;
end if;
else -- %ASR24 - %ASR31
i := conv_integer(dbgi.daddr(4 downto 3)); --
if dbgi.daddr(2) = '0' then
data(31 downto 2) := wpr(i).addr;
data(0) := wpr(i).exec;
else
data(31 downto 2) := wpr(i).mask;
data(1) := wpr(i).load;
data(0) := wpr(i).store;
end if;
end if;
when others =>
end case;
when "111" =>
data := r.x.data(conv_integer(r.x.set));
when others =>
end case;
end;
function itfilt (inst : word; filter : std_logic_vector(3 downto 0); trap, cfc : std_logic) return std_ulogic is
variable tren : std_ulogic;
begin
tren := '0';
case filter is
when "0001" => -- Bicc, SETHI
if inst(31 downto 30) = "00" then tren := '1'; end if;
when "0010" => -- Control-flow change
if (inst(31 downto 30) = "01") -- Call
or ((inst(31 downto 30) = "00") and (inst(23 downto 22) /= "00")) --Bicc
or ((inst(31 downto 30) = "10") and (inst(24 downto 19) = JMPL)) --Jmpl
or ((inst(31 downto 30) = "10") and (inst(24 downto 19) = RETT)) --Rett
or (trap = '1') or (cfc = '1')
then tren := '1'; end if;
when "0100" => -- Call
if inst(31 downto 30) = "01" then tren := '1'; end if;
when "1000" => -- Normal instructions
if inst(31 downto 30) = "10" then tren := '1'; end if;
when "1100" => -- LDST
if inst(31 downto 30) = "11" then tren := '1'; end if;
when "1101" => -- LDST from alternate space
if inst(31 downto 30) = "11" and inst(24 downto 23) = "01" then tren := '1'; end if;
when "1110" => -- LDST from alternate space 0x80 - 0xFF
if inst(31 downto 30) = "11" and inst(24 downto 23) = "01" and inst(12) = '1' then tren := '1'; end if;
when others => tren := '1';
end case;
return(tren);
end;
procedure itrace(r : in registers;
dsur : in dsu_registers;
vdsu : in dsu_registers;
res : in word;
exc : in std_ulogic;
dbgi : in l3_debug_in_type;
error : in std_ulogic;
trap : in std_ulogic;
tbufcnt : out std_logic_vector(TBUFBITS-1 downto 0);
ov : out std_ulogic;
di : out tracebuf_in_type;
di_2p : out tracebuf_2p_in_type;
ierr : in std_ulogic;
derr : in std_ulogic
) is
variable meminst : std_ulogic;
variable tfen : std_ulogic;
variable vdi_2p : tracebuf_2p_in_type;
variable vdi : tracebuf_in_type;
variable indata : std_logic_vector(255 downto 0);
variable write : std_logic_vector(7 downto 0);
variable tov : std_ulogic;
begin
vdi_2p := tracebuf_2p_in_type_none;
vdi := tracebuf_in_type_none;
indata := (others => '0');
write := (others => '0');
tbufcnt := vdsu.tbufcnt;
meminst := r.x.ctrl.inst(31) and r.x.ctrl.inst(30);
tov := vdsu.tov;
if TRACEBUF then
if dbgi.tenable = '1' then
if dsur.tbufcnt(TBUFBITS-1 downto TBUFBITS-3) = dsur.tlim(2 downto 0) then
tov := '1';
end if;
end if;
indata(127) := tov;
indata(126) := not r.x.ctrl.pv;
indata(125 downto 96) := dbgi.timer(29 downto 0);
if REX=1 then
indata(125) := r.x.ctrl.pc(2-2*REX);
indata(124) := r.x.ctrl.pc(2-1*REX);
end if;
indata(95 downto 64) := res;
indata(63 downto 34) := r.x.ctrl.pc(31 downto 2);
indata(33) := trap;
indata(32) := error;
indata(31 downto 0) := r.x.ctrl.inst;
vdi.addr(TBUFBITS-1 downto 0) := dsur.tbufcnt;
vdi.data := indata;
if (dbgi.tenable = '0') or (r.x.rstate = dsu2) then
if ((dbgi.dsuen and dbgi.denable) = '1') and (dbgi.daddr(23 downto 20) & dbgi.daddr(16) = "00010") then
vdi.enable := '1';
vdi.addr(TBUFBITS-1 downto 0) := dbgi.daddr(TBUFBITS-1+4 downto 4);
vdi_2p.renable := '1';
vdi_2p.raddr(TBUFBITS-1 downto 0) := dbgi.daddr(TBUFBITS-1+4 downto 4);
if dbgi.dwrite = '1' then
case dbgi.daddr(3 downto 2) is
when "00" => write(3) := '1';
when "01" => write(2) := '1';
when "10" => write(1) := '1';
when others => write(0) := '1';
end case;
indata(127 downto 0) := dbgi.ddata & dbgi.ddata & dbgi.ddata & dbgi.ddata;
vdi.write := write;
vdi.data := indata;
vdi_2p.renable := '0';
vdi_2p.write := write;
vdi_2p.waddr(TBUFBITS-1 downto 0) := dbgi.daddr(TBUFBITS-1+4 downto 4);
vdi_2p.data := indata;
end if;
end if;
elsif (not r.x.ctrl.annul and (r.x.ctrl.pv or meminst or r.x.ctrl.itovr) and not r.x.debug and
itfilt(r.x.ctrl.inst, dsur.tfilt, trap, dsur.cfc(4))) = '1' then
vdi.enable := holdn;
vdi.write := (others => '1');
vdi_2p.write := (others => '1');
vdi_2p.waddr(TBUFBITS-1 downto 0) := dsur.tbufcnt;
vdi_2p.data := indata;
tbufcnt := dsur.tbufcnt + 1;
end if;
if TRACEBUF_2P and ((dbgi.dsuen and dbgi.denable) = '1') and (dbgi.daddr(23 downto 20) & dbgi.daddr(16) = "00010") then
vdi_2p.renable := '1';
vdi_2p.raddr(TBUFBITS-1 downto 0) := dbgi.daddr(TBUFBITS-1+4 downto 4);
end if;
end if;
ov := tov;
di := vdi;
di_2p := vdi_2p;
end;
procedure dbg_cache(holdn : in std_ulogic;
dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
mresult : in word;
dci : in dc_in_type;
mresult2 : out word;
dci2 : out dc_in_type
) is
begin
mresult2 := mresult; dci2 := dci; dci2.dsuen := '0';
if DBGUNIT then
if (r.x.rstate = dsu2)
then
dci2.asi := dsur.asi;
if (dbgi.daddr(22 downto 20) = "111") and (dbgi.dsuen = '1') then
dci2.dsuen := (dbgi.denable or r.m.dci.dsuen) and not dsur.crdy(2);
dci2.enaddr := dbgi.denable;
dci2.size := "10"; dci2.read := '1'; dci2.write := '0';
if (dbgi.denable and not r.m.dci.enaddr) = '1' then
mresult2 := (others => '0'); mresult2(19 downto 2) := dbgi.daddr(19 downto 2);
else
mresult2 := dbgi.ddata;
end if;
if dbgi.dwrite = '1' then
dci2.read := '0'; dci2.write := '1';
end if;
end if;
end if;
end if;
end;
procedure fpexack(r : in registers; fpexc : out std_ulogic) is
begin
fpexc := '0';
if FPEN then
if r.x.ctrl.tt = TT_FPEXC then fpexc := '1'; end if;
end if;
end;
procedure diagrdy(denable : in std_ulogic;
dsur : in dsu_registers;
dci : in dc_in_type;
mds : in std_ulogic;
ico : in icache_out_type;
crdy : out std_logic_vector(2 downto 1)) is
begin
crdy := dsur.crdy(1) & '0';
if dci.dsuen = '1' then
case dsur.asi(4 downto 0) is
when ASI_ITAG | ASI_IDATA | ASI_UINST | ASI_SINST =>
crdy(2) := ico.diagrdy and not dsur.crdy(2);
when ASI_DTAG | ASI_MMUSNOOP_DTAG | ASI_DDATA | ASI_UDATA | ASI_SDATA =>
crdy(1) := not denable and dci.enaddr and not dsur.crdy(1);
when others =>
crdy(2) := dci.enaddr and denable;
end case;
end if;
end;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant dc_in_res : dc_in_type := (
signed => '0',
enaddr => '0',
read => '0',
write => '0',
lock => '0',
dsuen => '0',
size => (others => '0'),
asi => (others => '0'));
constant pipeline_ctrl_res : pipeline_ctrl_type := (
pc => (others => '0'),
inst => (others => '0'),
cnt => (others => '0'),
rd => (others => '0'),
tt => (others => '0'),
trap => '0',
annul => '1',
wreg => '0',
wicc => '0',
wy => '0',
ld => '0',
pv => '0',
rett => '0',
itovr => '0');
constant fpc_res : pctype := conv_std_logic_vector(rstaddr, 20) & zero32(11 downto PCLOW);
constant fetch_reg_res : fetch_reg_type := (
pc => fpc_res, -- Needs special handling
branch => '0'
);
constant decode_reg_res : decode_reg_type := (
pc => (others => '0'),
inst => (others => (others => '0')),
cwp => (others => '0'),
awp => (others => '0'),
aw => '0',
paw => '0',
stwin => (others => '0'),
cwpmax => CWPMAX,
set => (others => '0'),
mexc => '0',
cnt => (others => '0'),
pv => '0',
annul => '1',
inull => '0',
step => '0',
divrdy => '0',
pcheld => '0',
rexen => '0',
rexpos => "10",
rexbuf => (others => '0'),
rexcnt => (others => '0'),
rexpl => ((others => '0'),"00","0",'0','0',(others => '0'),'0','0','0','0','0','0')
);
constant regacc_reg_res : regacc_reg_type := (
ctrl => pipeline_ctrl_res,
rs1 => (others => '0'),
rfa1 => (others => '0'),
rfa2 => (others => '0'),
rsel1 => (others => '0'),
rsel2 => (others => '0'),
rfe1 => '0',
rfe2 => '0',
cwp => (others => '0'),
awp => (others => '0'),
aw => '0',
paw => '0',
imm => (others => '0'),
ldcheck1 => '0',
ldcheck2 => '0',
ldchkra => '1',
ldchkex => '1',
su => '1',
et => '0',
wovf => '0',
wunf => '0',
ticc => '0',
jmpl => '0',
step => '0',
mulstart => '0',
divstart => '0',
bp => '0',
nobp => '0',
bpimiss => '0',
getpc => '0',
decill => '0'
);
constant execute_reg_res : execute_reg_type := (
ctrl => pipeline_ctrl_res,
op1 => (others => '0'),
op2 => (others => '0'),
aluop => (others => '0'),
alusel => "11",
aluadd => '1',
alucin => '0',
ldbp1 => '0',
ldbp2 => '0',
invop2 => '0',
shcnt => (others => '0'),
sari => '0',
shleft => '0',
ymsb => '0',
rd => (others => '0'),
jmpl => '0',
su => '0',
et => '0',
cwp => (others => '0'),
awp => (others => '0'),
aw => '0',
paw => '0',
icc => (others => '0'),
mulstep => '0',
mul => '0',
mac => '0',
bp => '0',
rfe1 => '0',
rfe2 => '0'
);
constant memory_reg_res : memory_reg_type := (
ctrl => pipeline_ctrl_res,
result => (others => '0'),
y => (others => '0'),
icc => (others => '0'),
nalign => '0',
dci => dc_in_res,
werr => '0',
wcwp => '0',
wawp => '0',
irqen => '0',
irqen2 => '0',
mac => '0',
divz => '0',
su => '0',
mul => '0',
casa => '0',
casaz => '0',
rexnalign => '0'
);
function xnpc_res return std_logic_vector is
begin
if v8 /= 0 then return "100"; end if;
return "011";
end function xnpc_res;
constant exception_reg_res : exception_reg_type := (
ctrl => pipeline_ctrl_res,
result => (others => '0'),
y => (others => '0'),
icc => (others => '0'),
annul_all => '1',
data => (others => (others => '0')),
set => (others => '0'),
mexc => '0',
dci => dc_in_res,
laddr => (others => '0'),
rstate => run, -- Has special handling
npc => xnpc_res,
intack => '0',
ipend => '0',
mac => '0',
debug => '0', -- Has special handling
nerror => '0'
);
constant DRES : dsu_registers := (
tt => (others => '0'),
err => '0',
tbufcnt => (others => '0'),
asi => (others => '0'),
crdy => (others => '0'),
tfilt => (others => '0'),
cfc => (others => '0'),
tlim => (others => '0'),
tov => '0',
tovb => '0'
);
constant IRES : irestart_register := (
addr => (others => '0'), pwd => '0'
);
constant PRES : pwd_register_type := (
pwd => '0', -- Needs special handling
error => '0'
);
--constant special_register_res : special_register_type := (
-- cwp => zero32(NWINLOG2-1 downto 0),
-- icc => (others => '0'),
-- tt => (others => '0'),
-- tba => fpc_res(31 downto 12),
-- wim => (others => '0'),
-- pil => (others => '0'),
-- ec => '0',
-- ef => '0',
-- ps => '1',
-- s => '1',
-- et => '0',
-- y => (others => '0'),
-- asr18 => (others => '0'),
-- svt => '0',
-- dwt => '0',
-- dbp => '0'
-- );
--XST workaround:
function special_register_res return special_register_type is
variable s : special_register_type;
begin
s.cwp := zero32(NWINLOG2-1 downto 0);
s.icc := (others => '0');
s.tt := (others => '0');
s.tba := fpc_res(31 downto 12);
s.wim := (others => '0');
s.pil := (others => '0');
s.ec := '0';
s.ef := '0';
s.ps := '1';
s.s := '1';
s.et := '0';
s.y := (others => '0');
s.asr18 := (others => '0');
s.svt := '0';
s.dwt := '0';
s.dbp := '0';
s.dbprepl := '1';
s.rexdis :='1';
s.rextrap:='1';
s.aw := '0';
s.paw := '0';
s.awp := (others => '0');
s.stwin := (others => '0');
s.cwpmax := CWPMAX;
return s;
end function special_register_res;
--constant write_reg_res : write_reg_type := (
-- s => special_register_res,
-- result => (others => '0'),
-- wa => (others => '0'),
-- wreg => '0',
-- except => '0'
-- );
-- XST workaround:
function write_reg_res return write_reg_type is
variable w : write_reg_type;
begin
w.s := special_register_res;
w.result := (others => '0');
w.wa := (others => '0');
w.wreg := '0';
w.except := '0';
w.twcwp:= (others => '0');
return w;
end function write_reg_res;
constant RRES : registers := (
f => fetch_reg_res,
d => decode_reg_res,
a => regacc_reg_res,
e => execute_reg_res,
m => memory_reg_res,
x => exception_reg_res,
w => write_reg_res
);
constant exception_res : exception_type := (
pri => '0',
ill => '0',
fpdis => '0',
cpdis => '0',
wovf => '0',
wunf => '0',
ticc => '0'
);
constant wpr_none : watchpoint_register := (
addr => zero32(31 downto 2),
mask => zero32(31 downto 2),
exec => '0',
load => '0',
store => '0');
signal r, rin : registers;
signal wpr, wprin : watchpoint_registers;
signal dsur, dsuin : dsu_registers;
signal ir, irin : irestart_register;
signal rp, rpin : pwd_register_type;
-- execute stage operations
constant EXE_AND : std_logic_vector(2 downto 0) := "000";
constant EXE_XOR : std_logic_vector(2 downto 0) := "001"; -- must be equal to EXE_PASS2
constant EXE_OR : std_logic_vector(2 downto 0) := "010";
constant EXE_XNOR : std_logic_vector(2 downto 0) := "011";
constant EXE_ANDN : std_logic_vector(2 downto 0) := "100";
constant EXE_ORN : std_logic_vector(2 downto 0) := "101";
constant EXE_DIV : std_logic_vector(2 downto 0) := "110";
constant EXE_PASS1 : std_logic_vector(2 downto 0) := "000";
constant EXE_PASS2 : std_logic_vector(2 downto 0) := "001";
constant EXE_STB : std_logic_vector(2 downto 0) := "010";
constant EXE_STH : std_logic_vector(2 downto 0) := "011";
constant EXE_ONES : std_logic_vector(2 downto 0) := "100";
constant EXE_RDY : std_logic_vector(2 downto 0) := "101";
constant EXE_SPR : std_logic_vector(2 downto 0) := "110";
constant EXE_LINK : std_logic_vector(2 downto 0) := "111";
constant EXE_SLL : std_logic_vector(2 downto 0) := "001";
constant EXE_SRL : std_logic_vector(2 downto 0) := "010";
constant EXE_SRA : std_logic_vector(2 downto 0) := "100";
constant EXE_NOP : std_logic_vector(2 downto 0) := "000";
-- EXE result select
constant EXE_RES_ADD : std_logic_vector(1 downto 0) := "00";
constant EXE_RES_SHIFT : std_logic_vector(1 downto 0) := "01";
constant EXE_RES_LOGIC : std_logic_vector(1 downto 0) := "10";
constant EXE_RES_MISC : std_logic_vector(1 downto 0) := "11";
-- Load types
constant SZBYTE : std_logic_vector(1 downto 0) := "00";
constant SZHALF : std_logic_vector(1 downto 0) := "01";
constant SZWORD : std_logic_vector(1 downto 0) := "10";
constant SZDBL : std_logic_vector(1 downto 0) := "11";
-- calculate register file address
procedure regaddr(cwp : std_logic_vector; reg : std_logic_vector(4 downto 0);
stwin, de_cwpmax: std_logic_vector;
rao : out rfatype) is
variable ra : rfatype;
constant globals : std_logic_vector(RFBITS-5 downto 0) :=
conv_std_logic_vector(NWIN, RFBITS-4);
variable vcwp: cwptype;
begin
vcwp := cwp;
ra := (others => '0'); ra(4 downto 0) := reg;
if RFPART then
if ra(4)='0' and cwp=CWPMIN then
ra(4):='1';
vcwp := std_logic_vector(unsigned(de_cwpmax) + unsigned(stwin));
else
vcwp := std_logic_vector(unsigned(cwp) + unsigned(stwin));
end if;
end if;
if reg(4 downto 3) = "00" then ra(RFBITS -1 downto 4) := globals;
else
ra(NWINLOG2+3 downto 4) := vcwp + ra(4);
if ra(RFBITS-1 downto 4) = globals then
ra(RFBITS-1 downto 4) := (others => '0');
end if;
end if;
rao := ra;
end;
-- branch adder
function branch_address(inst : word; pc : pctype; de_rexbaddr1, de_rexen: std_logic) return std_logic_vector is
variable baddr: std_logic_vector(31 downto 0);
variable caddr, tmp : pctype;
begin
caddr := (others => '0'); caddr(31 downto 2) := inst(29 downto 0);
caddr(31 downto 2) := caddr(31 downto 2) + pc(31 downto 2);
baddr := (others => '0'); baddr(31 downto 24) := (others => inst(21));
baddr(23 downto 2) := inst(21 downto 0);
baddr(1) := de_rexbaddr1;
baddr(0) := de_rexen;
baddr(31 downto 1+(1-REX)) := baddr(31 downto 1+(1-REX)) + pc(31 downto 1+(1-REX));
if inst(30) = '1' then tmp := caddr; else tmp := baddr(31 downto PCLOW); end if;
return(tmp);
end;
-- evaluate branch condition
function branch_true(icc : std_logic_vector(3 downto 0); inst : word)
return std_ulogic is
variable n, z, v, c, branch : std_ulogic;
begin
n := icc(3); z := icc(2); v := icc(1); c := icc(0);
case inst(27 downto 25) is
when "000" => branch := inst(28) xor '0'; -- bn, ba
when "001" => branch := inst(28) xor z; -- be, bne
when "010" => branch := inst(28) xor (z or (n xor v)); -- ble, bg
when "011" => branch := inst(28) xor (n xor v); -- bl, bge
when "100" => branch := inst(28) xor (c or z); -- bleu, bgu
when "101" => branch := inst(28) xor c; -- bcs, bcc
when "110" => branch := inst(28) xor n; -- bneg, bpos
when others => branch := inst(28) xor v; -- bvs, bvc
end case;
return(branch);
end;
-- detect RETT instruction in the pipeline and set the local psr.su and psr.et
procedure su_et_select(r : in registers; xc_ps, xc_s, xc_et : in std_ulogic;
su, et : out std_ulogic) is
begin
if ((r.a.ctrl.rett or r.e.ctrl.rett or r.m.ctrl.rett or r.x.ctrl.rett) = '1')
and (r.x.annul_all = '0')
then su := xc_ps; et := '1';
else su := xc_s; et := xc_et; end if;
end;
-- detect watchpoint trap
function wphit(r : registers; wpr : watchpoint_registers; debug : l3_debug_in_type;
dsur : dsu_registers)
return std_ulogic is
variable exc : std_ulogic;
begin
exc := '0';
for i in 1 to NWP loop
if ((wpr(i-1).exec and r.a.ctrl.pv and not r.a.ctrl.annul) = '1') then
if (((wpr(i-1).addr xor r.a.ctrl.pc(31 downto 2)) and wpr(i-1).mask) = Zero32(31 downto 2)) then
exc := '1';
end if;
end if;
end loop;
if DBGUNIT then
if (debug.dsuen and not r.a.ctrl.annul) = '1' then
exc := exc or (r.a.ctrl.pv and ((((debug.dbreak and debug.bwatch) or r.a.step)) or
(debug.bwatch and dsur.tovb and dsur.tov)));
end if;
end if;
return(exc);
end;
-- 32-bit shifter
function shift3(r : registers; aluin1, aluin2 : word) return word is
variable shiftin : unsigned(63 downto 0);
variable shiftout : unsigned(63 downto 0);
variable cnt : natural range 0 to 31;
begin
cnt := conv_integer(r.e.shcnt);
if r.e.shleft = '1' then
shiftin(30 downto 0) := (others => '0');
shiftin(63 downto 31) := '0' & unsigned(aluin1);
else
shiftin(63 downto 32) := (others => r.e.sari);
shiftin(31 downto 0) := unsigned(aluin1);
end if;
shiftout := SHIFT_RIGHT(shiftin, cnt);
return(std_logic_vector(shiftout(31 downto 0)));
end;
function shift2(r : registers; aluin1, aluin2 : word) return word is
variable ushiftin : unsigned(31 downto 0);
variable sshiftin : signed(32 downto 0);
variable cnt : natural range 0 to 31;
variable resleft, resright : word;
begin
cnt := conv_integer(r.e.shcnt);
ushiftin := unsigned(aluin1);
sshiftin := signed('0' & aluin1);
if r.e.shleft = '1' then
resleft := std_logic_vector(SHIFT_LEFT(ushiftin, cnt));
return(resleft);
else
if r.e.sari = '1' then sshiftin(32) := aluin1(31); end if;
sshiftin := SHIFT_RIGHT(sshiftin, cnt);
resright := std_logic_vector(sshiftin(31 downto 0));
return(resright);
end if;
end;
function shift(r : registers; aluin1, aluin2 : word;
shiftcnt : std_logic_vector(4 downto 0); sari : std_ulogic ) return word is
variable shiftin : std_logic_vector(63 downto 0);
begin
shiftin := zero32 & aluin1;
if r.e.shleft = '1' then
shiftin(31 downto 0) := zero32; shiftin(63 downto 31) := '0' & aluin1;
else shiftin(63 downto 32) := (others => sari); end if;
if shiftcnt (4) = '1' then shiftin(47 downto 0) := shiftin(63 downto 16); end if;
if shiftcnt (3) = '1' then shiftin(39 downto 0) := shiftin(47 downto 8); end if;
if shiftcnt (2) = '1' then shiftin(35 downto 0) := shiftin(39 downto 4); end if;
if shiftcnt (1) = '1' then shiftin(33 downto 0) := shiftin(35 downto 2); end if;
if shiftcnt (0) = '1' then shiftin(31 downto 0) := shiftin(32 downto 1); end if;
return(shiftin(31 downto 0));
end;
-- Check for illegal and privileged instructions
procedure exception_detect(r : registers; wpr : watchpoint_registers; dbgi : l3_debug_in_type;
trapin : in std_ulogic; ttin : in std_logic_vector(5 downto 0);
trap : out std_ulogic; tt : out std_logic_vector(5 downto 0)) is
variable illegal_inst, privileged_inst : std_ulogic;
variable cp_disabled, fp_disabled, fpop : std_ulogic;
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable inst : word;
variable wph : std_ulogic;
begin
inst := r.a.ctrl.inst; trap := trapin; tt := ttin;
if r.a.ctrl.annul = '0' then
op := inst(31 downto 30); op2 := inst(24 downto 22);
op3 := inst(24 downto 19); rd := inst(29 downto 25);
illegal_inst := '0'; privileged_inst := '0'; cp_disabled := '0';
fp_disabled := '0'; fpop := '0';
case op is
when CALL => null;
when FMT2 =>
case op2 is
when SETHI | BICC => null;
when FBFCC =>
if FPEN then fp_disabled := not r.w.s.ef; else fp_disabled := '1'; end if;
when CBCCC =>
if (not CPEN) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
when FMT3 =>
case op3 is
when IAND | ANDCC | ANDN | ANDNCC | IOR | ORCC | ORN | ORNCC | IXOR |
XORCC | IXNOR | XNORCC | ISLL | ISRL | ISRA | MULSCC | IADD | ADDX |
ADDCC | ADDXCC | ISUB | SUBX | SUBCC | SUBXCC | FLUSH | JMPL | TICC |
SAVE | RESTORE | RDY => null;
when TADDCC | TADDCCTV | TSUBCC | TSUBCCTV =>
if notag = 1 then illegal_inst := '1'; end if;
when UMAC | SMAC =>
if not MACEN then illegal_inst := '1'; end if;
when UMUL | SMUL | UMULCC | SMULCC =>
if not MULEN then illegal_inst := '1'; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if not DIVEN then illegal_inst := '1'; end if;
when RETT => illegal_inst := r.a.et; privileged_inst := not r.a.su;
when RDPSR | RDTBR | RDWIM => privileged_inst := not r.a.su;
when WRY =>
if rd(4) = '1' and rd(3 downto 0) /= "0010" then -- %ASR16-17, %ASR19-31
privileged_inst := not r.a.su;
end if;
when WRPSR =>
privileged_inst := not r.a.su;
when WRWIM | WRTBR => privileged_inst := not r.a.su;
when FPOP1 | FPOP2 =>
if FPEN then fp_disabled := not r.w.s.ef; fpop := '1';
else fp_disabled := '1'; fpop := '0'; end if;
when CPOP1 | CPOP2 =>
if (not CPEN) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
when others => -- LDST
case op3 is
when LDD | ISTD => illegal_inst := rd(0); -- trap if odd destination register
when LD | LDUB | LDSTUB | LDUH | LDSB | LDSH | ST | STB | STH | SWAP =>
null;
when LDDA | STDA =>
illegal_inst := inst(13) or rd(0);
if (npasi = 0) or (inst(12) = '0') then
privileged_inst := not r.a.su;
end if;
when LDA | LDUBA| LDSTUBA | LDUHA | LDSBA | LDSHA | STA | STBA | STHA |
SWAPA =>
illegal_inst := inst(13);
if (npasi = 0) or (inst(12) = '0') then
privileged_inst := not r.a.su;
end if;
when CASA =>
if CASAEN then
illegal_inst := inst(13);
if (inst(12 downto 5) /= X"0A") then privileged_inst := not r.a.su; end if;
else illegal_inst := '1'; end if;
when LDDF | STDF | LDF | LDFSR | STF | STFSR =>
if FPEN then fp_disabled := not r.w.s.ef;
else fp_disabled := '1'; end if;
when STDFQ =>
privileged_inst := not r.a.su;
if (not FPEN) or (r.w.s.ef = '0') then fp_disabled := '1'; end if;
when STDCQ =>
privileged_inst := not r.a.su;
if (not CPEN) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when LDC | LDCSR | LDDC | STC | STCSR | STDC =>
if (not CPEN) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
end case;
wph := wphit(r, wpr, dbgi, dsur);
trap := '1';
if r.a.ctrl.trap = '1' then tt := r.a.ctrl.tt;
elsif privileged_inst = '1' then tt := TT_PRIV;
elsif illegal_inst = '1' or r.a.decill = '1' then tt := TT_IINST;
elsif fp_disabled = '1' then tt := TT_FPDIS;
elsif cp_disabled = '1' then tt := TT_CPDIS;
elsif wph = '1' then tt := TT_WATCH;
elsif r.a.wovf= '1' then tt := TT_WINOF;
elsif r.a.wunf= '1' then tt := TT_WINUF;
elsif r.a.ticc= '1' then tt := TT_TICC;
else trap := '0'; tt:= (others => '0'); end if;
end if;
end;
-- instructions that write the condition codes (psr.icc)
procedure wicc_y_gen(inst : word; wicc, wy : out std_ulogic) is
begin
wicc := '0'; wy := '0';
if inst(31 downto 30) = FMT3 then
case inst(24 downto 19) is
when SUBCC | TSUBCC | TSUBCCTV | ADDCC | ANDCC | ORCC | XORCC | ANDNCC |
ORNCC | XNORCC | TADDCC | TADDCCTV | ADDXCC | SUBXCC | WRPSR =>
wicc := '1';
when WRY =>
if r.d.inst(conv_integer(r.d.set))(29 downto 25) = "00000" then wy := '1'; end if;
when MULSCC =>
wicc := '1'; wy := '1';
when UMAC | SMAC =>
if MACEN then wy := '1'; end if;
when UMULCC | SMULCC =>
if MULEN and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (MULTYPE /= 0)) then
wicc := '1'; wy := '1';
end if;
when UMUL | SMUL =>
if MULEN and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (MULTYPE /= 0)) then
wy := '1';
end if;
when UDIVCC | SDIVCC =>
if DIVEN and (divo.nready = '1') and (r.d.cnt /= "00") then
wicc := '1';
end if;
when others =>
end case;
end if;
end;
-- select cwp
procedure cwp_gen(r, v : registers; annul, wcwp : std_ulogic; ncwp : cwptype;
cwp : out cwptype; awp: out cwptype; aw,paw: out std_ulogic;
stwin,de_cwpmax: out cwptype) is
begin
if (r.x.rstate = trap) or
(r.x.rstate = dsu2)
or (rstn = '0') then cwp := v.w.s.cwp;
elsif (wcwp = '1') and (annul = '0') and ((not AWPEN) or r.d.aw='0') then cwp := ncwp;
elsif r.m.wcwp = '1' then cwp := r.m.result(NWINLOG2-1 downto 0);
else cwp := r.d.cwp; end if;
if AWPEN and ((r.x.rstate = trap) or
(r.x.rstate = dsu2)
or (rstn = '0')) then awp := v.w.s.awp;
elsif AWPEN and r.d.aw='1' and (wcwp = '1') and (annul = '0') then awp := ncwp;
elsif AWPEN and r.m.wawp = '1' then awp := r.m.result(NWINLOG2-1 downto 0);
elsif AWPEN and (r.d.aw='0' and r.d.paw='0') then awp := r.d.cwp;
else awp := r.d.awp; end if;
if AWPEN and (
(r.x.rstate = trap) or
(r.x.rstate = dsu2)
or (rstn = '0') ) then aw := v.w.s.aw; paw := v.w.s.paw;
elsif AWPEN and (v.a.ctrl.rett='1') then
aw := r.d.paw; paw := r.d.paw;
elsif AWPEN and r.m.wcwp='1' then aw:=r.m.result(15); paw:=r.m.result(14);
else aw:=r.d.aw; paw:=r.d.paw; end if;
if RFPART and (
(r.x.rstate = trap) or
(r.x.rstate = dsu2)
or (rstn = '0') ) then
stwin := v.w.s.stwin; de_cwpmax:=v.w.s.cwpmax;
elsif RFPART and r.m.wawp='1' and r.m.result(15+NWINLOG2 downto 16)/=CWPMIN then
stwin:=r.m.result(20+NWINLOG2 downto 21); de_cwpmax:=r.m.result(15+NWINLOG2 downto 16);
else
stwin := r.d.stwin; de_cwpmax:=r.d.cwpmax;
end if;
end;
-- generate wcwp in ex stage
procedure cwp_ex(r : in registers; wcwp : out std_ulogic; wawp : out std_ulogic) is
variable vwcwp, vwawp: std_ulogic;
begin
vwcwp := '0'; vwawp := '0';
if (r.e.ctrl.inst(31 downto 30) = FMT3) and
(r.e.ctrl.inst(24 downto 19) = WRPSR)
then vwcwp := not r.e.ctrl.annul; else vwcwp := '0'; end if;
if AWPEN and
(r.e.ctrl.inst(31 downto 30) = FMT3) and
(r.e.ctrl.inst(24 downto 19) = WRY) and
(r.e.ctrl.inst(29 downto 25) = "10100")
then
vwawp := not r.e.ctrl.annul;
vwcwp := vwcwp or (r.e.op1(5) and not r.e.ctrl.annul);
else vwawp := '0';
end if;
wcwp := vwcwp;
wawp := vwawp;
end;
-- generate next cwp & window under- and overflow traps
procedure cwp_ctrl(r : in registers; rcwp: in cwptype; xc_wim : in std_logic_vector(NWIN-1 downto 0);
inst : word; de_cwp : out cwptype; wovf_exc, wunf_exc, wcwp : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable wim : word;
variable ncwp : cwptype;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
wovf_exc := '0'; wunf_exc := '0'; wim := (others => '0');
wim(NWIN-1 downto 0) := xc_wim; wcwp := '0';
ncwp := rcwp;
if (op = FMT3) and ((op3 = RETT) or (op3 = RESTORE) or (op3 = SAVE)) then
wcwp := '1';
if (op3 = SAVE) then
if RFPART and (rcwp=CWPMIN) then ncwp := r.w.s.cwpmax;
elsif (not CWPOPT) and (rcwp = CWPMIN) then ncwp := CWPMAX;
else ncwp := rcwp - 1 ; end if;
else
if RFPART and (rcwp = r.w.s.cwpmax) then ncwp := CWPMIN;
elsif (not CWPOPT) and (rcwp = CWPMAX) then ncwp := CWPMIN;
else ncwp := rcwp + 1; end if;
end if;
if wim(conv_integer(ncwp)) = '1' then
if op3 = SAVE then wovf_exc := '1'; else wunf_exc := '1'; end if;
end if;
end if;
de_cwp := ncwp;
end;
-- generate register read address 1
procedure rs1_gen(r : registers; inst : word; rs1 : out std_logic_vector(4 downto 0);
rs1mod : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
rs1 := inst(18 downto 14); rs1mod := '0';
if (op = LDST) then
if ((r.d.cnt = "01") and ((op3(2) and not op3(3)) = '1')) or
((r.d.cnt = "10") and (not (CASAEN and LDDEL=2 and op3(5 downto 3)="111"))) or
((r.d.cnt = "11") and ( (CASAEN and LDDEL=2)))
then rs1mod := '1'; rs1 := inst(29 downto 25); end if;
if ((r.d.cnt = "10") and (op3(3 downto 0) = "0111")) then
rs1(0) := '1';
end if;
end if;
end;
-- load/icc interlock detection
function icc_valid(r : registers) return std_logic is
variable not_valid : std_logic;
begin
not_valid := '0';
if MULEN or DIVEN then
not_valid := r.m.ctrl.wicc and (r.m.ctrl.cnt(0) or r.m.mul);
end if;
not_valid := not_valid or (r.a.ctrl.wicc or r.e.ctrl.wicc);
return(not not_valid);
end;
procedure bp_miss_ex(r : registers; icc : std_logic_vector(3 downto 0);
ex_bpmiss, ra_bpannul : out std_logic) is
variable miss : std_logic;
begin
miss := (not r.e.ctrl.annul) and r.e.bp and not branch_true(icc, r.e.ctrl.inst);
ra_bpannul := miss and r.e.ctrl.inst(29);
ex_bpmiss := miss;
end;
procedure bp_miss_ra(r : registers; ra_bpmiss, de_bpannul : out std_logic) is
variable miss : std_logic;
begin
miss := ((not r.a.ctrl.annul) and r.a.bp and icc_valid(r) and not branch_true(r.m.icc, r.a.ctrl.inst));
de_bpannul := miss and r.a.ctrl.inst(29);
ra_bpmiss := miss;
end;
procedure lock_gen(r : registers; rs2, rd : std_logic_vector(4 downto 0);
rfa1, rfa2, rfrd : rfatype; inst : word; fpc_lock, mulinsn, divinsn, de_wcwp : std_ulogic;
lldcheck1, lldcheck2, lldlock, lldchkra, lldchkex, bp, nobp, de_fins_hold : out std_ulogic;
iperr : std_logic; icbpmiss: std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable rs1 : std_logic_vector(4 downto 0);
variable i, ldcheck1, ldcheck2, ldchkra, ldchkex, ldcheck3 : std_ulogic;
variable ldlock, icc_check, bicc_hold, chkmul, y_check : std_logic;
variable icc_check_bp, y_hold, mul_hold, bicc_hold_bp, fins, call_hold : std_ulogic;
variable de_fins_holdx : std_ulogic;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
op2 := inst(24 downto 22); cond := inst(28 downto 25);
rs1 := inst(18 downto 14); i := inst(13);
ldcheck1 := '0'; ldcheck2 := '0'; ldcheck3 := '0'; ldlock := '0';
ldchkra := '1'; ldchkex := '1'; icc_check := '0'; bicc_hold := '0';
y_check := '0'; y_hold := '0'; bp := '0'; mul_hold := '0';
icc_check_bp := '0'; nobp := '0'; fins := '0'; call_hold := '0';
if (r.d.annul = '0') and (icbpmiss='0')
then
case op is
when CALL =>
call_hold := '1'; nobp := BPRED;
when FMT2 =>
if (op2 = BICC) and (cond(2 downto 0) /= "000") then
icc_check_bp := '1';
end if;
if (op2 = BICC) then nobp := BPRED; end if;
when FMT3 =>
ldcheck1 := '1'; ldcheck2 := not i;
case op3 is
when TICC =>
if (cond(2 downto 0) /= "000") then icc_check := '1'; end if;
nobp := BPRED;
when RDY =>
ldcheck1 := '0'; ldcheck2 := '0';
if MACPIPE then y_check := '1'; end if;
when RDWIM | RDTBR =>
ldcheck1 := '0'; ldcheck2 := '0';
when RDPSR =>
ldcheck1 := '0'; ldcheck2 := '0'; icc_check := '1';
when SDIV | SDIVCC | UDIV | UDIVCC =>
if DIVEN then y_check := '1'; nobp := op3(4); end if; -- no BP on divcc
when FPOP1 | FPOP2 => ldcheck1:= '0'; ldcheck2 := '0'; fins := BPRED;
when JMPL => call_hold := '1'; nobp := BPRED;
when others =>
end case;
when LDST =>
ldcheck1 := '1'; ldchkra := '0';
case r.d.cnt is
when "00" =>
if (lddel = 2) and (op3(2) = '1') and (op3(5) = '0') then ldcheck3 := '1'; end if;
ldcheck2 := not i; ldchkra := '1';
when "01" =>
ldcheck2 := not i;
if (op3(5) and op3(2) and not op3(3)) = '1' then ldcheck1 := '0'; ldcheck2 := '0'; end if; -- STF/STC
when others => ldchkex := '0';
if CASAEN and (op3(5 downto 3) = "111") then
if lddel=2 then
ldcheck2 := r.d.cnt(0);
else
ldcheck2 := '1';
end if;
elsif (op3(5) = '1') or ((op3(5) & op3(3 downto 1)) = "0110") -- LDST
then ldcheck1 := '0'; ldcheck2 := '0'; end if;
end case;
if op3(5) = '1' then fins := BPRED; end if; -- no BP on FPU/CP LD/ST
when others => null;
end case;
end if;
if MULEN or DIVEN then
chkmul := mulinsn;
mul_hold := (r.a.mulstart and r.a.ctrl.wicc) or (r.m.ctrl.wicc and (r.m.ctrl.cnt(0) or r.m.mul));
if (MULTYPE = 0) and ((icc_check_bp and BPRED and r.a.ctrl.wicc and r.a.ctrl.wy) = '1')
then mul_hold := '1'; end if;
else chkmul := '0'; end if;
if DIVEN then
y_hold := y_check and (r.a.ctrl.wy or r.e.ctrl.wy);
chkmul := chkmul or divinsn;
end if;
bicc_hold := icc_check and not icc_valid(r);
bicc_hold_bp := icc_check_bp and not icc_valid(r);
if (((r.a.ctrl.ld or chkmul) and r.a.ctrl.wreg and ldchkra) = '1') and
(((ldcheck1 = '1') and (r.a.ctrl.rd = rfa1)) or
((ldcheck2 = '1') and (r.a.ctrl.rd = rfa2)) or
((ldcheck3 = '1') and (r.a.ctrl.rd = rfrd)))
then ldlock := '1'; end if;
if (((r.e.ctrl.ld or r.e.mac) and r.e.ctrl.wreg and ldchkex) = '1') and
((lddel = 2) or (MACPIPE and (r.e.mac = '1')) or ((MULTYPE = 3) and (r.e.mul = '1'))) and
(((ldcheck1 = '1') and (r.e.ctrl.rd = rfa1)) or
((ldcheck2 = '1') and (r.e.ctrl.rd = rfa2)))
then ldlock := '1'; end if;
de_fins_holdx := BPRED and fins and (r.a.bp or r.e.bp); -- skip BP on FPU inst in branch target address
de_fins_hold := de_fins_holdx;
ldlock := ldlock or y_hold or fpc_lock or (BPRED and r.a.bp and r.a.ctrl.inst(29) and de_wcwp) or de_fins_holdx;
if ((icc_check_bp and BPRED) = '1') and ((r.a.nobp or mul_hold) = '0') then
bp := bicc_hold_bp;
else ldlock := ldlock or bicc_hold or bicc_hold_bp; end if;
lldcheck1 := ldcheck1; lldcheck2:= ldcheck2; lldlock := ldlock;
lldchkra := ldchkra; lldchkex := ldchkex;
end;
procedure fpbranch(inst : in word; fcc : in std_logic_vector(1 downto 0);
branch : out std_ulogic) is
variable cond : std_logic_vector(3 downto 0);
variable fbres : std_ulogic;
begin
cond := inst(28 downto 25);
case cond(2 downto 0) is
when "000" => fbres := '0'; -- fba, fbn
when "001" => fbres := fcc(1) or fcc(0);
when "010" => fbres := fcc(1) xor fcc(0);
when "011" => fbres := fcc(0);
when "100" => fbres := (not fcc(1)) and fcc(0);
when "101" => fbres := fcc(1);
when "110" => fbres := fcc(1) and not fcc(0);
when others => fbres := fcc(1) and fcc(0);
end case;
branch := cond(3) xor fbres;
end;
-- PC generation
procedure ic_ctrl(r : registers; inst : word; annul_all, ldlock, de_rexhold, de_rexbubble, de_rexmaskpv, de_rexillinst, branch_true,
fbranch_true, cbranch_true, fccv, cccv : in std_ulogic;
cnt : out std_logic_vector(1 downto 0);
de_pc : out pctype; de_branch, ctrl_annul, de_annul, jmpl_inst, inull,
de_pv, ctrl_pv, de_hold_pc, ticc_exception, rett_inst, mulstart,
divstart : out std_ulogic; rabpmiss, exbpmiss, iperr : std_logic;
icbpmiss, eocl: std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable hold_pc, annul_current, annul_next, branch, annul, pv : std_ulogic;
variable de_jmpl, inhibit_current : std_ulogic;
begin
branch := '0'; annul_next := '0'; annul_current := '0'; pv := '1';
hold_pc := '0'; ticc_exception := '0'; rett_inst := '0';
op := inst(31 downto 30); op3 := inst(24 downto 19);
op2 := inst(24 downto 22); cond := inst(28 downto 25);
annul := inst(29); de_jmpl := '0'; cnt := "00";
mulstart := '0'; divstart := '0'; inhibit_current := '0';
if (r.d.annul = '0') and not (icbpmiss = '1' and r.d.pcheld='0') and (REX=0 or de_rexbubble='0')
then
case inst(31 downto 30) is
when CALL =>
branch := '1';
if r.d.inull = '1' then
hold_pc := '1'; annul_current := '1';
end if;
when FMT2 =>
if (op2 = BICC) or (FPEN and (op2 = FBFCC)) or (CPEN and (op2 = CBCCC)) then
if (FPEN and (op2 = FBFCC)) then
branch := fbranch_true;
if fccv /= '1' then hold_pc := '1'; annul_current := '1'; end if;
elsif (CPEN and (op2 = CBCCC)) then
branch := cbranch_true;
if cccv /= '1' then hold_pc := '1'; annul_current := '1'; end if;
else branch := branch_true or (BPRED and orv(cond) and not icc_valid(r)); end if;
if hold_pc = '0' then
if (branch = '1') then
if (cond = BA) and (annul = '1') then annul_next := '1'; end if;
else annul_next := annul_next or annul; end if;
if r.d.inull = '1' then -- contention with JMPL
hold_pc := '1'; annul_current := '1'; annul_next := '0';
end if;
end if;
end if;
when FMT3 =>
case op3 is
when UMUL | SMUL | UMULCC | SMULCC =>
if MULEN and (MULTYPE /= 0) then mulstart := '1'; end if;
if MULEN and (MULTYPE = 0) then
case r.d.cnt is
when "00" =>
cnt := "01"; hold_pc := '1'; pv := '0'; mulstart := '1';
when "01" =>
if mulo.nready = '1' then cnt := "00";
else cnt := "01"; pv := '0'; hold_pc := '1'; end if;
when others => null;
end case;
end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if DIVEN then
case r.d.cnt is
when "00" =>
hold_pc := '1'; pv := '0';
if r.d.divrdy = '0' then
cnt := "01"; divstart := '1';
end if;
when "01" =>
if divo.nready = '1' then cnt := "00";
else cnt := "01"; pv := '0'; hold_pc := '1'; end if;
when others => null;
end case;
end if;
when TICC =>
if branch_true = '1' then ticc_exception := '1'; end if;
when RETT =>
rett_inst := '1'; --su := sregs.ps;
when JMPL =>
de_jmpl := '1';
if (BLOCKBPMISS and (eocl or r.f.branch) and r.e.bp)='1' then
hold_pc := '1'; annul_current := '1';
end if;
when WRY =>
if PWRD1 then
if inst(29 downto 25) = "10011" then -- %ASR19
case r.d.cnt is
when "00" =>
pv := '0'; cnt := "00"; hold_pc := '1';
if r.x.ipend = '1' then cnt := "01"; end if;
when "01" =>
cnt := "00";
when others =>
end case;
end if;
end if;
when others => null;
end case;
when others => -- LDST
case r.d.cnt is
when "00" =>
if (op3(2) = '1') or (op3(1 downto 0) = "11") then -- ST/LDST/SWAP/LDD/CASA
cnt := "01"; hold_pc := '1'; pv := '0';
end if;
when "01" =>
if (op3(2 downto 0) = "111") or (op3(3 downto 0) = "1101") or
(CASAEN and (op3(5 downto 4) = "11")) or -- CASA
((CPEN or FPEN) and ((op3(5) & op3(2 downto 0)) = "1110"))
then -- LDD/STD/LDSTUB/SWAP
cnt := "10"; pv := '0'; hold_pc := '1';
else
cnt := "00";
end if;
when "10" =>
if (CASAEN and LDDEL=2 and op3(5 downto 4)="11") then -- CASA
cnt := "11"; hold_pc := '1'; pv := '0';
else
cnt := "00";
end if;
when others => null;
end case;
end case;
end if;
if ldlock = '1' then
cnt := r.d.cnt; annul_next := '0'; pv := '1';
end if;
hold_pc := (hold_pc or ldlock) and not annul_all;
if icbpmiss='1' and r.d.annul='0' then
annul_current := '1'; annul_next := '1'; pv := '0'; hold_pc := '0';
end if;
if ((exbpmiss and r.a.ctrl.annul and r.d.pv and not hold_pc) = '1') then
annul_next := '1'; pv := '0';
end if;
if ((exbpmiss and not r.a.ctrl.annul and r.d.pv) = '1') then
annul_next := '1'; pv := '0'; annul_current := '1';
end if;
if ((exbpmiss and not r.a.ctrl.annul and not r.d.pv and not hold_pc) = '1') then
annul_next := '1'; pv := '0';
end if;
if ((exbpmiss and r.e.ctrl.inst(29) and not r.a.ctrl.annul and not r.d.pv ) = '1')
and (r.d.cnt = "01") then
annul_next := '1'; annul_current := '1'; pv := '0';
end if;
if (exbpmiss and r.e.ctrl.inst(29) and r.a.ctrl.annul and r.d.pv) = '1' then
annul_next := '1'; pv := '0'; inhibit_current := '1';
end if;
if (exbpmiss and r.e.ctrl.inst(29) and BLOCKBPMISS and r.a.bpimiss) = '1' then
annul_next := '1'; pv := '0';
end if;
if (rabpmiss and not r.a.ctrl.inst(29) and not r.d.annul and r.d.pv and not hold_pc) = '1' then
annul_next := '1'; pv := '0';
end if;
if (rabpmiss and r.a.ctrl.inst(29) and not r.d.annul and r.d.pv ) = '1' then
annul_next := '1'; pv := '0'; inhibit_current := '1';
end if;
if (hold_pc or de_rexhold) = '1' then de_pc := r.d.pc; else de_pc := r.f.pc; end if;
annul_current := (annul_current or (ldlock and not inhibit_current) or annul_all or de_rexbubble);
annul_current := annul_current and not de_rexillinst;
ctrl_annul := r.d.annul or annul_all or annul_current or inhibit_current;
pv := pv and not ((r.d.inull and not hold_pc) or annul_all or de_rexmaskpv);
jmpl_inst := de_jmpl and not annul_current and not inhibit_current;
annul_next := (r.d.inull and not hold_pc) or annul_next or annul_all;
if (annul_next = '1') or (rstn = '0') then
cnt := (others => '0');
end if;
de_hold_pc := hold_pc; de_branch := branch; de_annul := annul_next;
de_pv := pv; ctrl_pv := r.d.pv and
not ((r.d.annul and not r.d.pv) or annul_all or annul_current);
inull := (not rstn) or r.d.inull or hold_pc or annul_all;
end;
-- register write address generation
procedure rd_gen(r : registers; inst : word; wreg, ld : out std_ulogic;
rdo : out std_logic_vector(4 downto 0); rexen: out std_ulogic) is
variable write_reg : std_ulogic;
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable vrexen: std_ulogic;
begin
op := inst(31 downto 30);
op2 := inst(24 downto 22);
op3 := inst(24 downto 19);
write_reg := '0'; rd := inst(29 downto 25); ld := '0';
vrexen := '0';
case op is
when CALL =>
write_reg := '1'; rd := "01111"; -- CALL saves PC in r[15] (%o7)
when FMT2 =>
if (op2 = SETHI) then write_reg := '1'; end if;
when FMT3 =>
case op3 is
when UMUL | SMUL | UMULCC | SMULCC =>
if MULEN then
if (((mulo.nready = '1') and (r.d.cnt /= "00")) or (MULTYPE /= 0)) then
write_reg := '1';
end if;
else write_reg := '1'; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if DIVEN then
if (divo.nready = '1') and (r.d.cnt /= "00") then
write_reg := '1';
end if;
else write_reg := '1'; end if;
when RETT | WRPSR | WRY | WRWIM | WRTBR | TICC | FLUSH => null;
when FPOP1 | FPOP2 => null;
when CPOP1 | CPOP2 => null;
when SAVE | IADD =>
write_reg := '1';
if REX /= 0 and inst(13)='0' and inst(12)='1' then
vrexen := '1';
end if;
when others => write_reg := '1';
end case;
when others => -- LDST
ld := not op3(2);
if (op3(2) = '0') and not ((CPEN or FPEN) and (op3(5) = '1'))
then write_reg := '1'; end if;
case op3 is
when SWAP | SWAPA | LDSTUB | LDSTUBA | CASA =>
if r.d.cnt = "00" then write_reg := '1'; ld := '1'; end if;
when others => null;
end case;
if r.d.cnt = "01" then
case op3 is
when LDD | LDDA | LDDC | LDDF => rd(0) := '1';
when others =>
end case;
end if;
end case;
if (rd = "00000") then write_reg := '0'; end if;
wreg := write_reg; rdo := rd; rexen := vrexen;
end;
-- immediate data generation
function imm_data (r : registers; insn : word; de_reximmexp: std_ulogic; de_reximmval: std_logic_vector(31 downto 13))
return word is
variable immediate_data, inst : word;
begin
immediate_data := (others => '0'); inst := insn;
case inst(31 downto 30) is
when FMT2 =>
immediate_data := inst(21 downto 0) & "0000000000";
when others => -- LDST
immediate_data(31 downto 13) := (others => inst(12));
immediate_data(12 downto 0) := inst(12 downto 0);
end case;
if REX=1 and de_reximmexp='1' then
immediate_data(31 downto 13) := de_reximmval(31 downto 13);
end if;
return(immediate_data);
end;
-- read special registers
function get_spr (r : registers; xc_wimmask: std_logic_vector) return word is
variable spr : word;
begin
spr := (others => '0');
case r.e.ctrl.inst(24 downto 19) is
when RDPSR => spr(31 downto 5) := conv_std_logic_vector(IMPL,4) &
conv_std_logic_vector(VER,4) & r.m.icc & "000000" & r.w.s.ec & r.w.s.ef &
r.w.s.pil & r.e.su & r.w.s.ps & r.e.et;
spr(NWINLOG2-1 downto 0) := r.e.cwp;
if AWPEN then spr(15 downto 14) := r.e.aw & r.e.paw; end if;
when RDTBR => spr(31 downto 4) := r.w.s.tba & r.w.s.tt;
when RDWIM => spr(NWIN-1 downto 0) := r.w.s.wim;
if RFPART then spr(NWIN-1 downto 0) := r.w.s.wim and not xc_wimmask; end if;
when others =>
end case;
return(spr);
end;
-- immediate data select
function imm_select(inst : word; de_rexen: std_ulogic) return boolean is
variable imm : boolean;
begin
imm := false;
if REX=1 and de_rexen='1' then imm:=true; end if;
case inst(31 downto 30) is
when FMT2 =>
case inst(24 downto 22) is
when SETHI => imm := true;
when others =>
end case;
when FMT3 =>
case inst(24 downto 19) is
when RDWIM | RDPSR | RDTBR => imm := true;
when others => if (inst(13) = '1') then imm := true; end if;
end case;
when LDST =>
if (inst(13) = '1') then imm := true; end if;
when others =>
end case;
return(imm);
end;
-- EXE operation
procedure alu_op(r : in registers; iop1, iop2 : in word; me_icc : std_logic_vector(3 downto 0);
my, ldbp : std_ulogic; aop1, aop2 : out word; aluop : out std_logic_vector(2 downto 0);
alusel : out std_logic_vector(1 downto 0); aluadd : out std_ulogic;
shcnt : out std_logic_vector(4 downto 0); sari, shleft, ymsb,
mulins, divins, mulstep, macins, ldbp2, invop2 : out std_logic
) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rs1, rs2, rd : std_logic_vector(4 downto 0);
variable icc : std_logic_vector(3 downto 0);
variable y0, i : std_ulogic;
begin
op := r.a.ctrl.inst(31 downto 30);
op2 := r.a.ctrl.inst(24 downto 22);
op3 := r.a.ctrl.inst(24 downto 19);
rs1 := r.a.ctrl.inst(18 downto 14); i := r.a.ctrl.inst(13);
rs2 := r.a.ctrl.inst(4 downto 0); rd := r.a.ctrl.inst(29 downto 25);
aop1 := iop1; aop2 := iop2; ldbp2 := ldbp;
aluop := EXE_NOP; alusel := EXE_RES_MISC; aluadd := '1';
shcnt := iop2(4 downto 0); sari := '0'; shleft := '0'; invop2 := '0';
ymsb := iop1(0); mulins := '0'; divins := '0'; mulstep := '0';
macins := '0';
if r.e.ctrl.wy = '1' then y0 := my;
elsif r.m.ctrl.wy = '1' then y0 := r.m.y(0);
elsif r.x.ctrl.wy = '1' then y0 := r.x.y(0);
else y0 := r.w.s.y(0); end if;
if r.e.ctrl.wicc = '1' then icc := me_icc;
elsif r.m.ctrl.wicc = '1' then icc := r.m.icc;
elsif r.x.ctrl.wicc = '1' then icc := r.x.icc;
else icc := r.w.s.icc; end if;
case op is
when CALL =>
aluop := EXE_LINK;
when FMT2 =>
case op2 is
when SETHI => aluop := EXE_PASS2;
when others =>
end case;
when FMT3 =>
case op3 is
when IADD | ADDX | ADDCC | ADDXCC | TADDCC | TADDCCTV | SAVE | RESTORE |
TICC | JMPL | RETT => alusel := EXE_RES_ADD;
when ISUB | SUBX | SUBCC | SUBXCC | TSUBCC | TSUBCCTV =>
alusel := EXE_RES_ADD; aluadd := '0'; aop2 := not iop2; invop2 := '1';
when MULSCC => alusel := EXE_RES_ADD;
aop1 := (icc(3) xor icc(1)) & iop1(31 downto 1);
if y0 = '0' then aop2 := (others => '0'); ldbp2 := '0'; end if;
mulstep := '1';
when UMUL | UMULCC | SMUL | SMULCC =>
if MULEN then mulins := '1'; end if;
when UMAC | SMAC =>
if MACEN then mulins := '1'; macins := '1'; end if;
when UDIV | UDIVCC | SDIV | SDIVCC =>
if DIVEN then
aluop := EXE_DIV; alusel := EXE_RES_LOGIC; divins := '1';
end if;
when IAND | ANDCC => aluop := EXE_AND; alusel := EXE_RES_LOGIC;
when ANDN | ANDNCC => aluop := EXE_ANDN; alusel := EXE_RES_LOGIC;
when IOR | ORCC => aluop := EXE_OR; alusel := EXE_RES_LOGIC;
when ORN | ORNCC => aluop := EXE_ORN; alusel := EXE_RES_LOGIC;
when IXNOR | XNORCC => aluop := EXE_XNOR; alusel := EXE_RES_LOGIC;
when XORCC | IXOR | WRPSR | WRWIM | WRTBR | WRY =>
aluop := EXE_XOR; alusel := EXE_RES_LOGIC;
when RDPSR | RDTBR | RDWIM => aluop := EXE_SPR;
when RDY => aluop := EXE_RDY;
when ISLL => aluop := EXE_SLL; alusel := EXE_RES_SHIFT; shleft := '1';
shcnt := not iop2(4 downto 0); invop2 := '1';
when ISRL => aluop := EXE_SRL; alusel := EXE_RES_SHIFT;
when ISRA => aluop := EXE_SRA; alusel := EXE_RES_SHIFT; sari := iop1(31);
when FPOP1 | FPOP2 =>
when others =>
end case;
when others => -- LDST
case r.a.ctrl.cnt is
when "00" =>
alusel := EXE_RES_ADD;
when "01" =>
case op3 is
when LDD | LDDA | LDDC => alusel := EXE_RES_ADD;
when LDDF => alusel := EXE_RES_ADD;
when SWAP | SWAPA | LDSTUB | LDSTUBA | CASA => alusel := EXE_RES_ADD;
when STF | STDF =>
when others =>
aluop := EXE_PASS1;
if op3(2) = '1' then
if op3(1 downto 0) = "01" then aluop := EXE_STB;
elsif op3(1 downto 0) = "10" then aluop := EXE_STH; end if;
end if;
end case;
when "10" =>
aluop := EXE_PASS1;
if op3(2) = '1' then -- ST
if (op3(3) and not op3(5) and not op3(1))= '1' then aluop := EXE_ONES; end if; -- LDSTUB
end if;
if CASAEN and (r.m.casa = '1') and LDDEL=1 then
alusel := EXE_RES_ADD; aluadd := '0'; aop2 := not iop2; invop2 := '1';
end if;
when others =>
end case;
end case;
end;
function ra_inull_gen(r, v : registers) return std_ulogic is
variable de_inull : std_ulogic;
begin
de_inull := '0';
if ((v.e.jmpl or v.e.ctrl.rett) and not v.e.ctrl.annul and not (r.e.jmpl and not r.e.ctrl.annul)) = '1' then de_inull := '1'; end if;
if ((v.a.jmpl or v.a.ctrl.rett) and not v.a.ctrl.annul and not (r.a.jmpl and not r.a.ctrl.annul)) = '1' then de_inull := '1'; end if;
return(de_inull);
end;
-- operand generation
procedure op_mux(r : in registers; rfd, ed, md, xd, im : in word;
rsel : in std_logic_vector(2 downto 0);
ldbp : out std_ulogic; d : out word; id : std_logic) is
begin
ldbp := '0';
case rsel is
when "000" => d := rfd;
when "001" => d := ed;
when "010" => d := md; if lddel = 1 then ldbp := r.m.ctrl.ld; end if;
when "011" => d := xd;
if (CASAEN and lddel=2) and (r.m.casa='1' and r.a.ctrl.cnt="11" and id='1') then d:=xd xor rfd; end if;
when "100" => d := im;
when "101" => d := (others => '0');
when "110" => d := r.w.result;
when others => d := (others => '-');
end case;
if CASAEN and (r.a.ctrl.cnt = "10") and ((r.m.casa and not id) = '1') then ldbp := '1'; end if;
if REX=1 and r.a.getpc='1' and id='0' then
d := r.a.ctrl.pc;
d(0) := '0';
end if;
end;
procedure op_find(r : in registers; ldchkra : std_ulogic; ldchkex : std_ulogic;
rs1 : std_logic_vector(4 downto 0); ra : rfatype; im : boolean; rfe : out std_ulogic;
osel : out std_logic_vector(2 downto 0); ldcheck : std_ulogic) is
begin
rfe := '0';
if im then osel := "100";
elsif rs1 = "00000" then osel := "101"; -- %g0
elsif ((r.a.ctrl.wreg and ldchkra) = '1') and (ra = r.a.ctrl.rd) then osel := "001";
elsif ((r.e.ctrl.wreg and ldchkex) = '1') and (ra = r.e.ctrl.rd) then osel := "010";
elsif (r.m.ctrl.wreg = '1') and (ra = r.m.ctrl.rd) then osel := "011";
elsif (irfwt = 0) and (r.x.ctrl.wreg = '1') and (ra = r.x.ctrl.rd) then osel := "110";
else osel := "000"; rfe := ldcheck; end if;
end;
-- generate carry-in for alu
procedure cin_gen(r : registers; me_cin : in std_ulogic; cin : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable ncin : std_ulogic;
begin
op := r.a.ctrl.inst(31 downto 30); op3 := r.a.ctrl.inst(24 downto 19);
if r.e.ctrl.wicc = '1' then ncin := me_cin;
else ncin := r.m.icc(0); end if;
cin := '0';
case op is
when FMT3 =>
case op3 is
when ISUB | SUBCC | TSUBCC | TSUBCCTV => cin := '1';
when ADDX | ADDXCC => cin := ncin;
when SUBX | SUBXCC => cin := not ncin;
when others => null;
end case;
when LDST =>
if CASAEN and (r.m.casa = '1') and
((r.a.ctrl.cnt = "10" and LDDEL=1) or (r.a.ctrl.cnt = "11" and LDDEL=2)) then
cin := '1';
end if;
when others => null;
end case;
end;
procedure logic_op(r : registers; aluin1, aluin2, mey : word;
ymsb : std_ulogic; logicres, y : out word) is
variable logicout : word;
begin
case r.e.aluop is
when EXE_AND => logicout := aluin1 and aluin2;
when EXE_ANDN => logicout := aluin1 and not aluin2;
when EXE_OR => logicout := aluin1 or aluin2;
when EXE_ORN => logicout := aluin1 or not aluin2;
when EXE_XOR => logicout := aluin1 xor aluin2;
when EXE_XNOR => logicout := aluin1 xor not aluin2;
when EXE_DIV =>
if DIVEN then logicout := aluin2;
else logicout := (others => '-'); end if;
when others => logicout := (others => '-');
end case;
if (r.e.ctrl.wy and r.e.mulstep) = '1' then
y := ymsb & r.m.y(31 downto 1);
elsif r.e.ctrl.wy = '1' then y := logicout;
elsif r.m.ctrl.wy = '1' then y := mey;
elsif MACPIPE and (r.x.mac = '1') then y := mulo.result(63 downto 32);
elsif r.x.ctrl.wy = '1' then y := r.x.y;
else y := r.w.s.y; end if;
logicres := logicout;
end;
function st_align(size : std_logic_vector(1 downto 0); bpdata : word) return word is
variable edata : word;
begin
case size is
when "01" => edata := bpdata(7 downto 0) & bpdata(7 downto 0) &
bpdata(7 downto 0) & bpdata(7 downto 0);
when "10" => edata := bpdata(15 downto 0) & bpdata(15 downto 0);
when others => edata := bpdata;
end case;
return(edata);
end;
procedure misc_op(r : registers; wpr : watchpoint_registers;
aluin1, aluin2, ldata, mey : word; xc_wimmask: std_logic_vector;
mout, edata : out word) is
variable miscout, bpdata, stdata : word;
variable wpi : integer;
begin
wpi := 0;
miscout := (others => '0');
miscout(31 downto PCLOW) := r.e.ctrl.pc(31 downto PCLOW);
if REX/=0 and r.e.ctrl.pc(PCLOW)='1' then
miscout(31 downto 2) := miscout(31 downto 2)-1;
end if;
edata := aluin1; bpdata := aluin1;
if ((r.x.ctrl.wreg and r.x.ctrl.ld and not r.x.ctrl.annul) = '1') and
(r.x.ctrl.rd = r.e.ctrl.rd) and (r.e.ctrl.inst(31 downto 30) = LDST) and
(r.e.ctrl.cnt /= "10")
then bpdata := ldata; end if;
case r.e.aluop is
when EXE_STB => miscout := bpdata(7 downto 0) & bpdata(7 downto 0) &
bpdata(7 downto 0) & bpdata(7 downto 0);
edata := miscout;
when EXE_STH => miscout := bpdata(15 downto 0) & bpdata(15 downto 0);
edata := miscout;
when EXE_PASS1 => miscout := bpdata; edata := miscout;
when EXE_PASS2 => miscout := aluin2;
when EXE_ONES => miscout := (others => '1');
edata := miscout;
when EXE_RDY =>
if MULEN and (r.m.ctrl.wy = '1') then miscout := mey;
else miscout := r.m.y; end if;
if (NWP > 0) and (r.e.ctrl.inst(18 downto 17) = "11") then
wpi := conv_integer(r.e.ctrl.inst(16 downto 15));
if r.e.ctrl.inst(14) = '0' then miscout := wpr(wpi).addr & '0' & wpr(wpi).exec;
else miscout := wpr(wpi).mask & wpr(wpi).load & wpr(wpi).store; end if;
end if;
if (r.e.ctrl.inst(18 downto 17) = "10") and (r.e.ctrl.inst(14) = '1') then --%ASR17
miscout := asr17_gen(r);
end if;
if MACEN then
if (r.e.ctrl.inst(18 downto 14) = "10010") then --%ASR18
if ((r.m.mac = '1') and not MACPIPE) or ((r.x.mac = '1') and MACPIPE) then
miscout := mulo.result(31 downto 0); -- data forward of asr18
else miscout := r.w.s.asr18; end if;
else
if ((r.m.mac = '1') and not MACPIPE) or ((r.x.mac = '1') and MACPIPE) then
miscout := mulo.result(63 downto 32); -- data forward Y
end if;
end if;
end if;
if AWPEN or RFPART then
if (r.e.ctrl.inst(18 downto 14) = "10100") then -- %asr20
miscout := (others => '0');
if AWPEN then
miscout(NWINLOG2-1 downto 0) := r.e.awp;
end if;
if RFPART then
miscout(20+NWINLOG2 downto 21) := r.w.s.stwin;
miscout(15+NWINLOG2 downto 16) := r.w.s.cwpmax;
end if;
end if;
end if;
when EXE_SPR =>
miscout := get_spr(r, xc_wimmask);
when others => null;
end case;
mout := miscout;
end;
procedure alu_select(r : registers; addout : std_logic_vector(32 downto 0);
op1, op2 : word; shiftout, logicout, miscout : word; res : out word;
me_icc : std_logic_vector(3 downto 0);
icco : out std_logic_vector(3 downto 0); divz, mzero : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable icc : std_logic_vector(3 downto 0);
variable aluresult : word;
variable azero : std_logic;
begin
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
icc := (others => '0');
if addout(32 downto 1) = zero32 then azero := '1'; else azero := '0'; end if;
mzero := azero;
case r.e.alusel is
when EXE_RES_ADD =>
aluresult := addout(32 downto 1);
if r.e.aluadd = '0' then
icc(0) := ((not op1(31)) and not op2(31)) or -- Carry
(addout(32) and ((not op1(31)) or not op2(31)));
icc(1) := (op1(31) and (op2(31)) and not addout(32)) or -- Overflow
(addout(32) and (not op1(31)) and not op2(31));
else
icc(0) := (op1(31) and op2(31)) or -- Carry
((not addout(32)) and (op1(31) or op2(31)));
icc(1) := (op1(31) and op2(31) and not addout(32)) or -- Overflow
(addout(32) and (not op1(31)) and (not op2(31)));
end if;
if notag = 0 then
case op is
when FMT3 =>
case op3 is
when TADDCC | TADDCCTV =>
icc(1) := op1(0) or op1(1) or op2(0) or op2(1) or icc(1);
when TSUBCC | TSUBCCTV =>
icc(1) := op1(0) or op1(1) or (not op2(0)) or (not op2(1)) or icc(1);
when others => null;
end case;
when others => null;
end case;
end if;
-- if aluresult = zero32 then icc(2) := '1'; end if;
icc(2) := azero;
when EXE_RES_SHIFT => aluresult := shiftout;
when EXE_RES_LOGIC => aluresult := logicout;
if aluresult = zero32 then icc(2) := '1'; end if;
when others => aluresult := miscout;
end case;
if r.e.jmpl = '1' then aluresult := r.e.ctrl.pc(31 downto 2) & "00"; end if;
icc(3) := aluresult(31); divz := icc(2);
if r.e.ctrl.wicc = '1' then
if (op = FMT3) and (op3 = WRPSR) then icco := logicout(23 downto 20);
else icco := icc; end if;
elsif r.m.ctrl.wicc = '1' then icco := me_icc;
elsif r.x.ctrl.wicc = '1' then icco := r.x.icc;
else icco := r.w.s.icc; end if;
res := aluresult;
end;
procedure dcache_gen(r, v : registers; dci : out dc_in_type;
link_pc, jump, force_a2, load, mcasa : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable su, lock : std_ulogic;
begin
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
dci.signed := '0'; dci.lock := '0'; dci.dsuen := '0'; dci.size := SZWORD;
mcasa := '0';
if op = LDST then
case op3 is
when LDUB | LDUBA => dci.size := SZBYTE;
when LDSTUB | LDSTUBA => dci.size := SZBYTE; dci.lock := '1';
when LDUH | LDUHA => dci.size := SZHALF;
when LDSB | LDSBA => dci.size := SZBYTE; dci.signed := '1';
when LDSH | LDSHA => dci.size := SZHALF; dci.signed := '1';
when LD | LDA | LDF | LDC => dci.size := SZWORD;
when SWAP | SWAPA => dci.size := SZWORD; dci.lock := '1';
when CASA => if CASAEN then dci.size := SZWORD; dci.lock := '1'; end if;
when LDD | LDDA | LDDF | LDDC => dci.size := SZDBL;
when STB | STBA => dci.size := SZBYTE;
when STH | STHA => dci.size := SZHALF;
when ST | STA | STF => dci.size := SZWORD;
when ISTD | STDA => dci.size := SZDBL;
when STDF | STDFQ => if FPEN then dci.size := SZDBL; end if;
when STDC | STDCQ => if CPEN then dci.size := SZDBL; end if;
when others => dci.size := SZWORD; dci.lock := '0'; dci.signed := '0';
end case;
end if;
link_pc := '0'; jump:= '0'; force_a2 := '0'; load := '0';
dci.write := '0'; dci.enaddr := '0'; dci.read := not op3(2);
-- load/store control decoding
if (r.e.ctrl.annul or r.e.ctrl.trap) = '0' then
case op is
when CALL => link_pc := '1';
when FMT3 =>
if r.e.ctrl.trap = '0' then
case op3 is
when JMPL => jump := '1'; link_pc := '1';
when RETT => if REX=0 or r.f.pc(0+2*(1-REX))='0' then jump := '1'; end if;
when others => null;
end case;
end if;
when LDST =>
case r.e.ctrl.cnt is
when "00" =>
dci.read := op3(3) or not op3(2); -- LD/LDST/SWAP/CASA
load := op3(3) or not op3(2);
--dci.enaddr := '1';
dci.enaddr := (not op3(2)) or op3(2)
or (op3(3) and op3(2));
when "01" =>
force_a2 := not op3(2); -- LDD
load := not op3(2); dci.enaddr := not op3(2);
if op3(3 downto 2) = "01" then -- ST/STD
dci.write := '1';
end if;
if (op3(3 downto 2) = "11") and -- LDST/SWAP/CASA
not (CASAEN and LDDEL=2 and op3(5 downto 4)="11")
then
dci.enaddr := '1';
end if;
if (CASAEN and LDDEL=2 and op3(5 downto 4)="11") then
dci.read := '1';
end if;
when "10" => -- STD/LDST/SWAP/CASA
dci.write := '1';
if (CASAEN and LDDEL=2 and (op3(5 downto 4) = "11")) then -- CASA
dci.enaddr := '1';
dci.write := '0';
end if;
when others =>
if (CASAEN and LDDEL=2 and (op3(5 downto 4) = "11")) then -- CASA
dci.write := '1';
end if;
end case;
if (r.e.ctrl.trap or (v.x.ctrl.trap and not v.x.ctrl.annul)) = '1' then
dci.enaddr := '0';
end if;
if (CASAEN and (op3(5 downto 4) = "11")) then mcasa := '1'; end if;
when others => null;
end case;
end if;
if ((r.x.ctrl.rett and not r.x.ctrl.annul) = '1') then su := r.w.s.ps;
else su := r.w.s.s; end if;
if su = '1' then dci.asi := "00001011"; else dci.asi := "00001010"; end if;
if (op3(4) = '1') and ((op3(5) = '0') or not CPEN) then
dci.asi := r.e.ctrl.inst(12 downto 5);
if r.e.ctrl.inst(12 downto 10) /= "000" then dci.enaddr := '0'; end if;
end if;
end;
procedure fpstdata(r : in registers; edata, eres : in word; fpstdata : in std_logic_vector(31 downto 0);
edata2, eres2 : out word) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
edata2 := edata; eres2 := eres;
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
if FPEN then
if FPEN and (op = LDST) and ((op3(5 downto 4) & op3(2)) = "101") and (r.e.ctrl.cnt /= "00") then
edata2 := fpstdata; eres2 := fpstdata;
end if;
end if;
if CASAEN and (r.m.casa = '1') and r.e.ctrl.cnt(1)='1' then
edata2 := r.e.op1; eres2 := r.e.op1;
end if;
end;
function ld_align(data : dcdtype; set : std_logic_vector(DSETMSB downto 0);
size, laddr : std_logic_vector(1 downto 0); signed : std_ulogic) return word is
variable align_data, rdata : word;
begin
align_data := data(conv_integer(set)); rdata := (others => '0');
case size is
when "00" => -- byte read
case laddr is
when "00" =>
rdata(7 downto 0) := align_data(31 downto 24);
if signed = '1' then rdata(31 downto 8) := (others => align_data(31)); end if;
when "01" =>
rdata(7 downto 0) := align_data(23 downto 16);
if signed = '1' then rdata(31 downto 8) := (others => align_data(23)); end if;
when "10" =>
rdata(7 downto 0) := align_data(15 downto 8);
if signed = '1' then rdata(31 downto 8) := (others => align_data(15)); end if;
when others =>
rdata(7 downto 0) := align_data(7 downto 0);
if signed = '1' then rdata(31 downto 8) := (others => align_data(7)); end if;
end case;
when "01" => -- half-word read
if laddr(1) = '1' then
rdata(15 downto 0) := align_data(15 downto 0);
if signed = '1' then rdata(31 downto 15) := (others => align_data(15)); end if;
else
rdata(15 downto 0) := align_data(31 downto 16);
if signed = '1' then rdata(31 downto 15) := (others => align_data(31)); end if;
end if;
when others => -- single and double word read
rdata := align_data;
end case;
return(rdata);
end;
procedure mem_trap(r : registers; wpr : watchpoint_registers;
annul, holdn : in std_ulogic;
trapout, iflush, nullify, werrout : out std_ulogic;
tt : out std_logic_vector(5 downto 0)) is
variable cwp : std_logic_vector(NWINLOG2-1 downto 0);
variable cwpx : std_logic_vector(5 downto NWINLOG2);
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable nalign_d : std_ulogic;
variable trap, werr : std_ulogic;
begin
op := r.m.ctrl.inst(31 downto 30); op2 := r.m.ctrl.inst(24 downto 22);
op3 := r.m.ctrl.inst(24 downto 19);
cwpx := r.m.result(5 downto NWINLOG2); cwpx(5) := '0';
iflush := '0'; trap := r.m.ctrl.trap; nullify := annul;
tt := r.m.ctrl.tt; werr := (dco.werr or r.m.werr) and not r.w.s.dwt;
nalign_d := r.m.nalign or r.m.result(2);
if (trap = '1') and (r.m.ctrl.pv = '1') then
if op = LDST then nullify := '1'; end if;
end if;
if ((annul or trap) /= '1') and (r.m.ctrl.pv = '1') then
if (werr and holdn) = '1' then
trap := '1'; tt := TT_DSEX; werr := '0';
if op = LDST then nullify := '1'; end if;
end if;
end if;
if ((annul or trap) /= '1') then
case op is
when FMT2 =>
case op2 is
when FBFCC =>
if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if;
when CBCCC =>
if CPEN and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if;
when others => null;
end case;
when FMT3 =>
case op3 is
when WRPSR =>
if (orv(cwpx) = '1') then trap := '1'; tt := TT_IINST; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if DIVEN then
if r.m.divz = '1' then trap := '1'; tt := TT_DIV; end if;
end if;
when JMPL | RETT =>
if (REX=1 and r.m.rexnalign='1') or (REX=0 and r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA;
end if;
when TADDCCTV | TSUBCCTV =>
if (notag = 0) and (r.m.icc(1) = '1') then
trap := '1'; tt := TT_TAG;
end if;
when FLUSH => iflush := '1';
when FPOP1 | FPOP2 =>
if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if;
when CPOP1 | CPOP2 =>
if CPEN and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if;
when others => null;
end case;
when LDST =>
if r.m.ctrl.cnt = "00" then
case op3 is
when LDDF | STDF | STDFQ =>
if FPEN then
if nalign_d = '1' then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif (fpo.exc and r.m.ctrl.pv) = '1'
then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if;
end if;
when LDDC | STDC | STDCQ =>
if CPEN then
if nalign_d = '1' then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif ((cpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if;
end if;
when LDD | ISTD | LDDA | STDA =>
if r.m.result(2 downto 0) /= "000" then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when LDF | LDFSR | STFSR | STF =>
if FPEN and (r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif FPEN and ((fpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if;
when LDC | LDCSR | STCSR | STC =>
if CPEN and (r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif CPEN and ((cpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if;
when LD | LDA | ST | STA | SWAP | SWAPA | CASA =>
if r.m.result(1 downto 0) /= "00" then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when LDUH | LDUHA | LDSH | LDSHA | STH | STHA =>
if r.m.result(0) /= '0' then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when others => null;
end case;
for i in 1 to NWP loop
if ((((wpr(i-1).load and not op3(2)) or (wpr(i-1).store and op3(2))) = '1') and
(((wpr(i-1).addr xor r.m.result(31 downto 2)) and wpr(i-1).mask) = zero32(31 downto 2)))
then trap := '1'; tt := TT_WATCH; nullify := '1'; end if;
end loop;
end if;
when others => null;
end case;
end if;
if (rstn = '0') or (r.x.rstate = dsu2) then werr := '0'; end if;
trapout := trap; werrout := werr;
end;
procedure irq_trap(r : in registers;
ir : in irestart_register;
irl : in std_logic_vector(3 downto 0);
annul : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic;
tt : in std_logic_vector(5 downto 0);
nullify : in std_ulogic;
irqen : out std_ulogic;
irqen2 : out std_ulogic;
nullify2 : out std_ulogic;
trap2, ipend : out std_ulogic;
tt2 : out std_logic_vector(5 downto 0)) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable pend : std_ulogic;
begin
nullify2 := nullify; trap2 := trap; tt2 := tt;
op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19);
irqen := '1'; irqen2 := r.m.irqen;
if (annul or trap) = '0' then
if ((op = FMT3) and (op3 = WRPSR)) then irqen := '0'; end if;
end if;
if (irl = "1111") or (irl > r.w.s.pil) then
pend := r.m.irqen and r.m.irqen2 and r.w.s.et and not ir.pwd
;
else pend := '0'; end if;
ipend := pend;
if ((not annul) and pv and (not trap) and pend) = '1' then
trap2 := '1'; tt2 := "01" & irl;
if op = LDST then nullify2 := '1'; end if;
end if;
end;
procedure irq_intack(r : in registers; holdn : in std_ulogic; intack: out std_ulogic) is
begin
intack := '0';
if r.x.rstate = trap then
if r.w.s.tt(7 downto 4) = "0001" then intack := '1'; end if;
end if;
end;
-- write special registers
procedure sp_write (r : registers; wpr : watchpoint_registers;
s : out special_register_type; vwpr : out watchpoint_registers) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable i : integer range 0 to 3;
begin
op := r.x.ctrl.inst(31 downto 30);
op2 := r.x.ctrl.inst(24 downto 22);
op3 := r.x.ctrl.inst(24 downto 19);
s := r.w.s;
rd := r.x.ctrl.inst(29 downto 25);
vwpr := wpr;
if AWPEN then
if r.w.s.aw='0' and r.w.s.paw='0' then
s.awp := r.w.s.cwp;
end if;
end if;
case op is
when FMT3 =>
case op3 is
when WRY =>
if rd = "00000" then
s.y := r.x.result;
elsif MACEN and (rd = "10010") then
s.asr18 := r.x.result;
elsif (rd = "10001") then
if bp = 2 then s.dbp := r.x.result(27); end if;
if bp = 2 then s.dbprepl := r.x.result(25); end if;
s.dwt := r.x.result(14);
if (svt = 1) then s.svt := r.x.result(13); end if;
if rex=1 then
s.rexdis:=r.x.result(22);
s.rextrap:=r.x.result(21);
end if;
elsif (AWPEN or RFPART) and rd="10100" then -- %ASR20
if AWPEN then
s.awp := r.x.result(NWINLOG2-1 downto 0);
if r.x.result(5)='1' then
s.cwp := r.x.result(NWINLOG2-1 downto 0);
end if;
end if;
if RFPART then
if r.x.result(15+NWINLOG2 downto 16)/=CWPMIN then
s.stwin := r.x.result(20+NWINLOG2 downto 21);
s.cwpmax := r.x.result(15+NWINLOG2 downto 16);
end if;
end if;
elsif rd(4 downto 3) = "11" then -- %ASR24 - %ASR31
case rd(2 downto 0) is
when "000" =>
vwpr(0).addr := r.x.result(31 downto 2);
vwpr(0).exec := r.x.result(0);
when "001" =>
vwpr(0).mask := r.x.result(31 downto 2);
vwpr(0).load := r.x.result(1);
vwpr(0).store := r.x.result(0);
when "010" =>
vwpr(1).addr := r.x.result(31 downto 2);
vwpr(1).exec := r.x.result(0);
when "011" =>
vwpr(1).mask := r.x.result(31 downto 2);
vwpr(1).load := r.x.result(1);
vwpr(1).store := r.x.result(0);
when "100" =>
vwpr(2).addr := r.x.result(31 downto 2);
vwpr(2).exec := r.x.result(0);
when "101" =>
vwpr(2).mask := r.x.result(31 downto 2);
vwpr(2).load := r.x.result(1);
vwpr(2).store := r.x.result(0);
when "110" =>
vwpr(3).addr := r.x.result(31 downto 2);
vwpr(3).exec := r.x.result(0);
when others => -- "111"
vwpr(3).mask := r.x.result(31 downto 2);
vwpr(3).load := r.x.result(1);
vwpr(3).store := r.x.result(0);
end case;
end if;
when WRPSR =>
if pwrpsr = 0 or rd = "00000" then
s.cwp := r.x.result(NWINLOG2-1 downto 0);
s.icc := r.x.result(23 downto 20);
s.ec := r.x.result(13);
if FPEN then s.ef := r.x.result(12); end if;
s.pil := r.x.result(11 downto 8);
s.s := r.x.result(7);
s.ps := r.x.result(6);
if AWPEN then
s.aw := r.x.result(15);
s.paw := r.x.result(14);
end if;
end if;
s.et := r.x.result(5);
when WRWIM =>
s.wim := r.x.result(NWIN-1 downto 0);
when WRTBR =>
s.tba := r.x.result(31 downto 12);
when SAVE =>
if (not AWPEN) or r.w.s.aw='0' then
if RFPART and (r.w.s.cwp=CWPMIN) then s.cwp := r.w.s.cwpmax;
elsif (not CWPOPT) and (r.w.s.cwp = CWPMIN) then s.cwp := CWPMAX;
else s.cwp := r.w.s.cwp - 1 ; end if;
end if;
if AWPEN and r.w.s.aw='1' then
if RFPART and (r.w.s.awp=CWPMIN) then s.awp := r.w.s.cwpmax;
elsif (not CWPOPT) and (r.w.s.awp = CWPMIN) then s.awp := CWPMAX;
else s.awp := r.w.s.awp - 1 ; end if;
end if;
when RESTORE =>
if (not AWPEN) or r.w.s.aw='0' then
if RFPART and (r.w.s.cwp=r.w.s.cwpmax) then s.cwp := CWPMIN;
elsif (not CWPOPT) and (r.w.s.cwp = CWPMAX) then s.cwp := CWPMIN;
else s.cwp := r.w.s.cwp + 1; end if;
end if;
if AWPEN and r.w.s.aw='1' then
if RFPART and (r.w.s.awp=r.w.s.cwpmax) then s.awp := CWPMIN;
elsif (not CWPOPT) and (r.w.s.awp = CWPMAX) then s.awp := CWPMIN;
else s.awp := r.w.s.awp + 1; end if;
end if;
when RETT =>
if ((not CWPOPT) and (r.w.s.cwp = CWPMAX)) or (RFPART and (r.w.s.cwp=r.w.s.cwpmax)) then s.cwp := CWPMIN;
else s.cwp := r.w.s.cwp + 1; end if;
s.s := r.w.s.ps;
s.et := '1';
if AWPEN then
s.aw := r.w.s.paw;
end if;
when others => null;
end case;
when others => null;
end case;
if r.x.ctrl.wicc = '1' then s.icc := r.x.icc; end if;
if r.x.ctrl.wy = '1' then s.y := r.x.y; end if;
if MACPIPE and (r.x.mac = '1') then
s.asr18 := mulo.result(31 downto 0);
s.y := mulo.result(63 downto 32);
end if;
end;
function npc_find (r : registers) return std_logic_vector is
variable npc : std_logic_vector(2 downto 0);
begin
npc := "011";
if r.m.ctrl.pv = '1' then npc := "000";
elsif r.e.ctrl.pv = '1' then npc := "001";
elsif r.a.ctrl.pv = '1' then npc := "010";
elsif r.d.pv = '1' then npc := "011";
elsif v8 /= 0 then npc := "100"; end if;
return(npc);
end;
function npc_gen (r : registers; de_pcout: std_logic_vector) return word is
variable npc : std_logic_vector(31 downto 0);
begin
npc := (others => '0');
npc(31 downto PCLOW) := r.a.ctrl.pc(31 downto PCLOW);
case r.x.npc is
when "000" => npc(31 downto PCLOW) := r.x.ctrl.pc(31 downto PCLOW);
when "001" => npc(31 downto PCLOW) := r.m.ctrl.pc(31 downto PCLOW);
when "010" => npc(31 downto PCLOW) := r.e.ctrl.pc(31 downto PCLOW);
when "011" => npc(31 downto PCLOW) := r.a.ctrl.pc(31 downto PCLOW);
when others =>
if v8 /= 0 then npc(31 downto PCLOW) := de_pcout(31 downto PCLOW); end if;
end case;
return(npc);
end;
procedure mul_res(r : registers; asr18in : word; result, y, asr18 : out word;
icc : out std_logic_vector(3 downto 0)) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19);
result := r.m.result; y := r.m.y; icc := r.m.icc; asr18 := asr18in;
case op is
when FMT3 =>
case op3 is
when UMUL | SMUL =>
if MULEN then
result := mulo.result(31 downto 0);
y := mulo.result(63 downto 32);
end if;
when UMULCC | SMULCC =>
if MULEN then
result := mulo.result(31 downto 0); icc := mulo.icc;
y := mulo.result(63 downto 32);
end if;
when UMAC | SMAC =>
if MACEN and not MACPIPE then
result := mulo.result(31 downto 0);
asr18 := mulo.result(31 downto 0);
y := mulo.result(63 downto 32);
end if;
when UDIV | SDIV =>
if DIVEN then
result := divo.result(31 downto 0);
end if;
when UDIVCC | SDIVCC =>
if DIVEN then
result := divo.result(31 downto 0); icc := divo.icc;
end if;
when others => null;
end case;
when others => null;
end case;
end;
function powerdwn(r : registers; trap : std_ulogic; rp : pwd_register_type) return std_ulogic is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable pd : std_ulogic;
begin
op := r.x.ctrl.inst(31 downto 30);
op3 := r.x.ctrl.inst(24 downto 19);
rd := r.x.ctrl.inst(29 downto 25);
pd := '0';
if (not (r.x.ctrl.annul or trap) and r.x.ctrl.pv) = '1' then
if ((op = FMT3) and (op3 = WRY) and (rd = "10011")) then pd := '1'; end if;
pd := pd or rp.pwd;
end if;
return(pd);
end;
function rex_dpc(pcin: pctype; rexen: std_ulogic; rexpos: std_logic_vector(1 downto 0))
return std_logic_vector is
variable vpcout: std_logic_vector(31 downto 0);
begin
vpcout := pcin(31 downto 2) & rexpos(0) & rexen;
if rexpos(1)='0' then
vpcout(31 downto 2) := vpcout(31 downto 2)-1;
end if;
return vpcout;
end;
function rex_regunp(rn: std_logic_vector(3 downto 0))
return std_logic_vector is
variable y: std_logic_vector(4 downto 0);
begin
y := "00" & rn(2 downto 0);
y(4) := rn(3) or rn(2);
y(3) := rn(3) or (not rn(2));
return y;
end rex_regunp;
procedure rex_decode_main(opin: std_logic_vector(47 downto 0);
cntin: std_logic_vector(0 downto 0);
opout: out std_logic_vector(31 downto 0);
szout: out std_logic_vector(1 downto 0);
ncntout: out std_logic_vector(0 downto 0);
baddr1: out std_ulogic;
immexp: out std_ulogic;
immval: out std_logic_vector(31 downto 13);
getpc: out std_ulogic;
maskpv: out std_ulogic;
illinst: out std_ulogic;
nostep: out std_ulogic;
itovr: out std_ulogic;
leave: out std_ulogic) is
variable vinst48 : std_logic_vector(47 downto 0);
variable vinst : std_logic_vector(31 downto 0);
-- fields extracted from vinst48
variable rop: std_logic_vector(1 downto 0);
variable rimm: std_ulogic;
variable rop3: std_logic_vector(3 downto 0);
variable rop4: std_logic_vector(4 downto 0);
variable rop4_4: std_logic_vector(3 downto 0);
variable rop3l: std_ulogic;
variable rrd,rrs: std_logic_vector(3 downto 0);
variable ximm: std_ulogic;
variable xop3: std_logic_vector(5 downto 0);
variable xfpop: std_logic_vector(6 downto 0);
variable xrdalt: std_ulogic;
variable xrs1alt: std_ulogic;
variable xrs2imm: std_logic_vector(6 downto 0);
-- computed from fields
variable isz: std_logic_vector(1 downto 0);
variable vpos: std_logic_vector(1 downto 0);
variable vhold,vbubble,vexpand,villinst,vnostep: std_ulogic;
variable vbaddr1, vbitop, veximm, vmask, vgetpc: std_ulogic;
variable eximmval: std_logic_vector(31 downto 13);
variable dop: std_logic_vector(1 downto 0);
variable drd, drs1, drs2: std_logic_vector(4 downto 0);
variable drs1_ldst, drs2_ldst, drd_ldst: std_logic_vector(4 downto 0);
variable vexpand_ldst, dimm_ldst: std_ulogic;
variable ncnt_ldst: std_logic_vector(0 downto 0);
variable drs2i: std_logic_vector(12 downto 5);
variable dop3: std_logic_vector(5 downto 0);
variable dimm: std_ulogic;
variable dbaddr: std_logic_vector(21 downto 0);
variable ncnt: std_logic_vector(0 downto 0);
variable opvec: std_logic_vector(6 downto 0);
variable bitop_imm, maskop_imm, bit_mask_imm: std_logic_vector(31 downto 0);
variable vmaskpv, vitovr: std_ulogic;
variable vleave: std_ulogic;
begin
vinst48 := opin;
rop := vinst48(47 downto 46);
rrd := vinst48(45 downto 42);
rimm := vinst48(41);
rop3 := vinst48(40 downto 37);
rop3l := vinst48(36);
rrs := vinst48(35 downto 32);
rop4 := vinst48(36 downto 32);
rop4_4 := rop4(3 downto 0);
ximm := vinst48(31);
xop3 := vinst48(30 downto 25);
xfpop := vinst48(31 downto 25);
xrdalt := vinst48(24);
xrs1alt := vinst48(23);
xrs2imm := vinst48(22 downto 16);
vbaddr1 := vinst48(32);
vbitop := '0';
vmask := '0';
vgetpc := '0';
veximm := '0';
eximmval := vinst48(31 downto 13);
dimm := '0';
ncnt := "0";
vexpand := '0';
vmaskpv := not cntin(0) and rop(1) and rop(0) and rop3l;
vitovr := cntin(0) and rop(1) and rop(0) and rop3l;
villinst := '0';
vnostep := '0';
vleave := '0';
-- Generate unpacked op parts for ALU / LDST instructions
drd := rex_regunp(rrd);
drs1 := drd;
dimm := rimm;
drs2 := rop3l & rrs;
-- Generate immediate for bit/mask operations */
bitop_imm := (others => '0');
bitop_imm(to_integer(unsigned(drs2))) := '1';
maskop_imm := (others => '0');
for x in 0 to 31 loop
if unsigned(drs2) >= to_unsigned(x,5) then
maskop_imm(x) := '1';
end if;
end loop;
bit_mask_imm := bitop_imm;
if rop3="0010" then bit_mask_imm := maskop_imm; end if;
if rimm='0' then
drs2 := rex_regunp(rrs);
end if;
drs2i := (others => rop3l);
if rimm='0' then
-- Set drs2i(12) to 0 Prevent decoding to saverex/addrex ops
-- Also set whole vector to ensure offset calc for self-inc ops
drs2i(12 downto 5):=(others => '0');
end if;
dop3 := (rop3(0) and rop(0)) & (rop3l and not rimm and not rop(0)) & "0" & rop3(3) & rop3(2) & rop3(1);
dop := rop;
opvec := rop(0) & rimm & rop3 & rop3l;
-- Common subexpr for LDST with rimm='0'
drs1_ldst := "00000";
ncnt_ldst := (others => '0');
ncnt_ldst(0) := opvec(0) and not cntin(0);
vexpand_ldst := opvec(0) and not cntin(0);
dimm_ldst := dimm or cntin(0);
drs2_ldst := drs2;
drd_ldst := drd;
drd_ldst(4) := drd_ldst(4) xor rop3(0);
drd_ldst(3) := drd_ldst(3) xor rop3(0);
if cntin/="0" then
drs1_ldst := drs2;
drs2_ldst := "0" & (rop3(2) and rop3(1)) & (not rop3(2) and not rop3(1)) & (rop3(2) and not rop3(1)) & (not rop3(2) and rop3(1));
drd_ldst := drs2;
end if;
case opvec is
-------------------------------------------------------------------------
-- ALU with reg operand
when "0000000" | "0000001" => null; -- r_add(cc)
when "0000010" | "0000011" => dop3(2):='1'; -- r_sub(cc)
when "0000100" | "0000101" => null; -- r_and(cc)
when "0000110" | "0000111" => villinst := '1'; -- undef
when "0001000" | "0001001" => null; -- r_or(cc)
when "0001010" | "0001011" => villinst:='1'; -- undef
when "0001100" | "0001101" => null; -- r_xor(cc)
when "0001110" | "0001111" | "1001110" | "1001111" => -- r_iop /r_flop / r_ldop (32-bit!)
drs1 := drs2;
drs2 := xrs2imm(4 downto 0);
drs2i(6 downto 5) := xrs2imm(6 downto 5);
if ximm='1' then
drs2i(12 downto 7) := (others => xrs2imm(6));
end if;
dop3 := xop3;
dimm := ximm;
if opvec(0)='1' then
dop3(5 downto 1) := "11010";
dop3(0) := xfpop(6) and (not xfpop(5)) and (not xfpop(4));
dimm := '0';
drs2i(12) := xfpop(6) and (xfpop(5) or xfpop(4));
drs2i(11) := xfpop(5) or xfpop(6);
drs2i(10) := xfpop(4) and not xfpop(6);
drs2i(9) := xfpop(6) and xfpop(4);
drs2i(8 downto 5) := xfpop(3 downto 0);
end if;
drd(4) := drd(4) xor (opvec(0) xor xrdalt);
drd(3) := drd(3) xor (opvec(0) xor xrdalt);
drs1(4) := drs1(4) xor (opvec(0) xor xrs1alt);
drs1(3) := drs1(3) xor (opvec(0) xor xrs1alt);
villinst := opvec(0) and opvec(6);
when "0010000" | "0010001" | "0010010" | "0010011" => -- r_mov
dop3 := "000000";
drs1 := "00000";
drs2(4) := drs2(4) xor opvec(0);
drs2(3) := drs2(3) xor opvec(0);
drd(4) := drd(4) xor opvec(1);
drd(3) := drd(3) xor opvec(1);
when "0010100" | "0010101" => null; -- r_andn(cc)
when "0010110" => dop3(5):='1'; -- r_sll
when "0010111" => -- r_cmp
dop3(0):='0';
drd := "00000";
when "0011000" | "0011001" => null; -- r_orn(cc)
when "0011010" | "0011011" => dop3(5):='1'; villinst:=opvec(0); -- r_srl / undef
when "0011100" | "0011101" => null; -- r_xnor(cc)
when "0011110" | "0011111" => villinst:='1'; -- undef
-------------------------------------------------------------------------
-- ALU with imm operand (note opvec(0) is top of immediate, so both opvec(0)=0 and
-- opvec(0)=1 cases must be decoded the same way)
when "0100000" | "0100001" => -- r_addcc(imm)
dop3(4) := '1';
when "0100010" | "0100011" => -- r_set5
drs1 := "00000";
when "0100100" | "0100101" => -- r_masklo
vmask := '1';
vbitop := '1';
when "0100110" | "0100111" => -- r_tstbit
dop3(4) := '1';
drd := "00000";
vbitop := '1';
when "0101000" | "0101001" => -- r_setbit
vbitop := '1';
when "0101010" | "0101011" => -- r_one
vbitop := '1';
drs1 := "00000";
when "0101100" | "0101101" => -- r_invbit
vbitop := '1';
when "0101110" | "0101111" => -- r_set21 (32-bit!)
dop3 := "000000";
drs1 := "00000";
veximm := '1';
eximmval(31 downto 21) := (others => vinst48(31));
eximmval(20 downto 13) := vinst48(31 downto 24);
drs2i(12 downto 5) := vinst48(23 downto 16);
when "0110000" | "0110001" => -- r_cmp(imm)
drd := "00000";
dop3(4):='1';
when "0110010" | "0110011" => -- undef
villinst := '1';
when "0110100" | "0110101" => -- r_clrbit
vbitop := '1';
when "0110110" | "0110111" => dop3(5):='1'; -- r_sll(imm)
when "0111000" | "0111001" => villinst:='1'; -- undef
when "0111010" | "0111011" => dop3(5):='1'; -- r_srl(imm)
when "0111100" | "0111101" => -- Misc ops
if rop4(4)='1' then
villinst := '1';
end if;
vgetpc := rop4(3) and rop4(0);
case rop4_4 is
when "0000" => -- r_retrest
drd := "00000";
drs1 := "11111";
drs2 := "01000";
if cntin="0" then
dop3 := "111000"; -- ret
vexpand := '1';
ncnt := "1";
vnostep := '1';
else
dop3 := "111101"; -- restore
end if;
when "0001" => -- r_retl
drd := "00000";
drs1 := "01111";
drs2 := "01000";
if cntin="0" then
dop3 := "111000"; -- ret
vexpand := '1';
ncnt := "1";
vnostep := '1';
end if;
when "0010" => -- r_push
drs2i := "11111111";
drs2 := "11100";
drs1 := "01110";
if cntin="0" then
ncnt := "1";
vexpand := '1';
dop3 := "000100"; -- Store
dop(0) := '1';
vmaskpv := '1';
else
dop3 := "000000"; -- Add
drd := "01110";
vitovr := '1';
end if;
when "0011" => -- r_pop
drs1 := "01110"; -- %sp=%r14
drs2i := "00000000";
drs2 := "00000";
if cntin="0" then
ncnt := "1";
vexpand := '1';
dop3 := "000000"; -- Load
dop(0) := '1';
vmaskpv := '1';
else
dop3 := "000000"; -- Add
drs2 := "00100";
drd := "01110";
vitovr := '1';
end if;
when "0100" => -- r_neg
drs2 := drs1;
drs1 := "00000";
dimm := '0';
dop3 := "000100";
when "0101" => -- r_not
drs2 := drs1;
drs1 := "00000";
dimm := '0';
dop3 := "000110";
when "0110" => -- r_ta0..7
drs2 := drs1;
drs2(4 downto 3) := "00";
drd := "01000";
drs1 := "00000";
dop3 := "111010";
when "0111" => -- r_leave
vleave := '1';
-- vbubbble := '1';
drd := "00000";
dop3 := "000000";
when "1001" => -- r_getpc
dop3 := "000000"; -- Add
drs2 := "00000";
when others => villinst := '1';
end case;
when "0111110" | "0111111" => -- Big ops (48-bit!)
-- r_set32/set32pc/ld32/ld32pc
if rop4(4 downto 2)/="010" then villinst:='1'; end if;
drs2i := vinst48(12 downto 5);
drs2 := vinst48(4 downto 0);
vgetpc := rop4(3) and rop4(0);
veximm := '1';
dop3 := "000000";
drs1 := "00000";
if rop4(1)='1' then dop(0):='1'; end if;
-------------------------------------------------------------------------
-- LDST with reg operand
when "1000000" | "1000001" => -- r_ld / r_ldinc
drs1:=drs1_ldst; drs2:=drs2_ldst; drd:=drd_ldst; dimm:=dimm_ldst;
vexpand:=vexpand_ldst; ncnt:=ncnt_ldst;
if cntin/="0" then dop3 := "000000"; dop(0):='0'; end if;
when "1000010" | "1000011" => -- r_ldf / r_ldfinc
drs1:=drs1_ldst; drs2:=drs2_ldst; drd:=drd_ldst; dimm:=dimm_ldst;
vexpand:=vexpand_ldst; ncnt:=ncnt_ldst;
if cntin/="0" then dop3 := "000000"; dop(0):='0'; end if;
when "1000100" | "1000101" => -- r_ldub / r_ldubinc
drs1:=drs1_ldst; drs2:=drs2_ldst; drd:=drd_ldst; dimm:=dimm_ldst;
vexpand:=vexpand_ldst; ncnt:=ncnt_ldst;
if cntin/="0" then dop3 := "000000"; dop(0):='0'; end if;
when "1000110" | "1000111" => -- Undef
drs1:=drs1_ldst; drs2:=drs2_ldst; drd:=drd_ldst; dimm:=dimm_ldst;
vexpand:=vexpand_ldst; ncnt:=ncnt_ldst;
if cntin/="0" then dop3 := "000000"; dop(0):='0'; end if;
when "1001000" | "1001001" => -- p_lduh / p_lduhinc
drs1:=drs1_ldst; drs2:=drs2_ldst; drd:=drd_ldst; dimm:=dimm_ldst;
vexpand:=vexpand_ldst; ncnt:=ncnt_ldst;
if cntin/="0" then dop3 := "000000"; dop(0):='0'; end if;
when "1001010" | "1001011" => -- p_lddf / p_lddfinc
drs1:=drs1_ldst; drs2:=drs2_ldst; drd:=drd_ldst; dimm:=dimm_ldst;
vexpand:=vexpand_ldst; ncnt:=ncnt_ldst;
if cntin/="0" then dop3 := "000000"; dop(0):='0'; end if;
dop3(0):='1';
when "1001100" | "1001101" => -- p_ldd / p_lddinc
drs1:=drs1_ldst; drs2:=drs2_ldst; drd:=drd_ldst; dimm:=dimm_ldst;
vexpand:=vexpand_ldst; ncnt:=ncnt_ldst;
if cntin/="0" then dop3 := "000000"; dop(0):='0'; end if;
-- when "1001110" | "1001111" => -- r_ldop covered in same case as iop
when "1010000" | "1010001" => -- p_st / p_stinc
drs1:=drs1_ldst; drs2:=drs2_ldst; drd:=drd_ldst; dimm:=dimm_ldst;
vexpand:=vexpand_ldst; ncnt:=ncnt_ldst;
if cntin/="0" then dop3 := "000000"; dop(0):='0'; end if;
when "1010010" | "1010011" => -- p_stf / p_stfinc
drs1:=drs1_ldst; drs2:=drs2_ldst; drd:=drd_ldst; dimm:=dimm_ldst;
vexpand:=vexpand_ldst; ncnt:=ncnt_ldst;
if cntin/="0" then dop3 := "000000"; dop(0):='0'; end if;
when "1010100" | "1010101" => -- p_stb / p_stbinc
drs1:=drs1_ldst; drs2:=drs2_ldst; drd:=drd_ldst; dimm:=dimm_ldst;
vexpand:=vexpand_ldst; ncnt:=ncnt_ldst;
if cntin/="0" then dop3 := "000000"; dop(0):='0'; end if;
when "1010110" | "1010111" => -- Undef
drs1:=drs1_ldst; drs2:=drs2_ldst; drd:=drd_ldst; dimm:=dimm_ldst;
vexpand:=vexpand_ldst; ncnt:=ncnt_ldst;
if cntin/="0" then dop3 := "000000"; dop(0):='0'; end if;
villinst := '1';
when "1011000" | "1011001" => -- p_sth / p_sthinc
drs1:=drs1_ldst; drs2:=drs2_ldst; drd:=drd_ldst; dimm:=dimm_ldst;
vexpand:=vexpand_ldst; ncnt:=ncnt_ldst;
if cntin/="0" then dop3 := "000000"; dop(0):='0'; end if;
when "1011010" | "1011011" => -- p_stdf / p_stdfinc
drs1:=drs1_ldst; drs2:=drs2_ldst; drd:=drd_ldst; dimm:=dimm_ldst;
vexpand:=vexpand_ldst; ncnt:=ncnt_ldst;
if cntin/="0" then dop3 := "000000"; dop(0):='0'; end if;
dop3(0) := '1';
when "1011100" | "1011101" => -- p_std / p_stdinc
drs1:=drs1_ldst; drs2:=drs2_ldst; drd:=drd_ldst; dimm:=dimm_ldst;
vexpand:=vexpand_ldst; ncnt:=ncnt_ldst;
if cntin/="0" then dop3 := "000000"; dop(0):='0'; end if;
when "1011110" | "1011111" => -- Undef
drs1:=drs1_ldst; drs2:=drs2_ldst; drd:=drd_ldst; dimm:=dimm_ldst;
vexpand:=vexpand_ldst; ncnt:=ncnt_ldst;
if cntin/="0" then dop3 := "000000"; dop(0):='0'; end if;
villinst := '1';
-------------------------------------------------------------------------
-- LDST with imm operand
when "1100000" | "1100001" | "1100010" | "1100011" => -- p_ldfp / p_ldffp
dop3(1 downto 0) := "00";
drs1 := "11110";
drs2i := "000000" & drs2(4 downto 3);
drs2 := drs2(2 downto 0) & "00";
drd(4) := drd(4) xor opvec(1); drd(3) := drd(3) xor opvec(1);
when "1100100" | "1100101" | "1100110" | "1100111" => -- p_ldsp / p_ldfsp
dop3(1 downto 0) := "00";
drs1 := "01110";
drs2i := "000000" & drs2(4 downto 3);
drs2 := drs2(2 downto 0) & "00";
drd(4) := drd(4) xor opvec(1); drd(3) := drd(3) xor opvec(1);
when "1101000" | "1101001" | "1101010" | "1101011" => -- p_ldi0 / p_ldfi0
dop3(1 downto 0) := "00";
drs1 := "11000";
drs2i := "000000" & drs2(4 downto 3);
drs2 := drs2(2 downto 0) & "00";
drd(4) := drd(4) xor opvec(1); drd(3) := drd(3) xor opvec(1);
when "1101100" | "1101101" => -- p_ldo0
dop3(1 downto 0) := "00";
drs1 := "01000";
drs2i := "000000" & drs2(4 downto 3);
drs2 := drs2(2 downto 0) & "00";
drd(4) := drd(4) xor opvec(1); drd(3) := drd(3) xor opvec(1);
when "1101110" | "1101111" => -- Undef (32-bit!)
dop3(1 downto 0) := "00";
drs1 := "01000";
drs2i := "000000" & drs2(4 downto 3);
drs2 := drs2(2 downto 0) & "00";
drd(4) := drd(4) xor opvec(1); drd(3) := drd(3) xor opvec(1);
villinst := '1';
when "1110000" | "1110001" => -- p_stfp
dop3(1 downto 0) := "00";
drs1 := "11110";
drs2i := "000000" & drs2(4 downto 3);
drs2 := drs2(2 downto 0) & "00";
drd(4) := drd(4) xor opvec(1); drd(3) := drd(3) xor opvec(1);
when "1110010" | "1110011" => -- p_stffp
dop3(1 downto 0) := "00";
drs1 := "11110";
drs2i := "000000" & drs2(4 downto 3);
drs2 := drs2(2 downto 0) & "00";
drd(4) := drd(4) xor opvec(1); drd(3) := drd(3) xor opvec(1);
when "1110100" | "1110101" => -- p_stsp
dop3(1 downto 0) := "00";
drs1 := "01110";
drs2i := "000000" & drs2(4 downto 3);
drs2 := drs2(2 downto 0) & "00";
drd(4) := drd(4) xor opvec(1); drd(3) := drd(3) xor opvec(1);
when "1110110" | "1110111" => -- p_stfsp
dop3(1 downto 0) := "00";
drs1 := "01110";
drs2i := "000000" & drs2(4 downto 3);
drs2 := drs2(2 downto 0) & "00";
drd(4) := drd(4) xor opvec(1); drd(3) := drd(3) xor opvec(1);
when "1111000" | "1111001" => -- p_sti0
dop3(1 downto 0) := "00";
drs1 := "11000";
drs2i := "000000" & drs2(4 downto 3);
drs2 := drs2(2 downto 0) & "00";
drd(4) := drd(4) xor opvec(1); drd(3) := drd(3) xor opvec(1);
when "1111010" | "1111011" => -- p_stfi0
dop3(1 downto 0) := "00";
drs1 := "11000";
drs2i := "000000" & drs2(4 downto 3);
drs2 := drs2(2 downto 0) & "00";
drd(4) := drd(4) xor opvec(1); drd(3) := drd(3) xor opvec(1);
when "1111100" | "1111101" => -- p_sto0
dop3(1 downto 0) := "00";
drs1 := "01000";
drs2i := "000000" & drs2(4 downto 3);
drs2 := drs2(2 downto 0) & "00";
drd(4) := drd(4) xor opvec(1); drd(3) := drd(3) xor opvec(1);
when others => -- Undef (48-bit!)
dop3(1 downto 0) := "00";
drs1 := "01000";
drs2i := "000000" & drs2(4 downto 3);
drs2 := drs2(2 downto 0) & "00";
drd(4) := drd(4) xor opvec(1); drd(3) := drd(3) xor opvec(1);
villinst := '1';
end case;
if vbitop='1' then
veximm := '1';
eximmval(31 downto 13) := bit_mask_imm(31 downto 13);
drs2i(12 downto 5) := bit_mask_imm(12 downto 5);
drs2 := bit_mask_imm(4 downto 0);
end if;
-- Generate unpacked op parts for branch
dbaddr := vinst48(30 downto 16) & vinst48(39 downto 33);
if rimm='0' then
dbaddr(21 downto 7) := (others => vinst48(39));
end if;
-- Generate instruction and calculate packed insn size for buffer mgmt
vinst := vinst48(47 downto 16);
isz := "01"; -- 00=16, 01=32, 10=48
case rop is
when "00" =>
-- Branch
-- 765 4321 0
-- 00x<cond>0<disp8>
-- 00x<cond>1<disp24>
isz := "0" & rimm;
vinst := vinst48(47 downto 46) & '0' & vinst48(45 downto 42) & vinst48(40) & "10" & dbaddr;
villinst := '0';
when "01" =>
-- Call
villinst := '0';
when others =>
-- ALU / LDST
-- 10<rd>01110x<rs1><+16> - 32-bit
-- 10<rd>01111<imm21> - 32-bit
-- 10<rd>11111<arg><+32> -48-bit
isz := "00";
if rop3(2 downto 0)="111" then
isz := rop3(3) & (not rop3(3));
end if;
vinst := dop & drd & dop3 & drs1 & dimm & drs2i & drs2;
end case;
opout := vinst;
szout := isz;
ncntout := ncnt;
baddr1 := vbaddr1;
immexp := veximm;
immval := eximmval;
getpc := vgetpc;
maskpv := vmaskpv;
illinst := villinst;
nostep := vnostep;
itovr := vitovr;
leave := vleave;
end rex_decode_main;
procedure rex_decode(r: registers;
de_inst1: std_logic_vector(31 downto 0);
de_inst: out std_logic_vector(31 downto 0);
de_nrexen: out std_ulogic;
de_nbufpos16: out std_logic_vector(1 downto 0);
de_ncnt16: out std_logic_vector(0 downto 0);
de_rexhold,de_rexbubble: out std_ulogic;
de_rexbaddr1: out std_ulogic;
de_reximmexp: out std_ulogic;
de_reximmval: out std_logic_vector(31 downto 13);
de_rexgetpc: out std_ulogic;
de_rexmaskpv: out std_ulogic;
de_rexillinst: out std_ulogic;
de_rexnostep: out std_ulogic;
de_rexitovr: out std_ulogic) is
variable vinst: std_logic_vector(31 downto 0); -- inst going out
variable vinst48: std_logic_vector(47 downto 0); -- raw inst buffer
variable nrexen: std_ulogic;
-- computed from fields
variable isz: std_logic_vector(1 downto 0);
variable vpos: std_logic_vector(1 downto 0);
variable vexpand,villinst,vnostep: std_ulogic;
variable vbaddr1, vbitop, veximm, vmask, vgetpc: std_ulogic;
variable eximmval: std_logic_vector(31 downto 13);
variable ncnt: std_logic_vector(0 downto 0);
variable vmaskpv, vitovr, vleave: std_ulogic;
-- Flow control
variable vhold,vbubble: std_ulogic;
begin
nrexen := r.d.rexen;
case r.d.rexpos is
when "00" => vinst48 := r.d.rexbuf(31 downto 16) & r.d.rexbuf(15 downto 0) & de_inst1(31 downto 16);
when "01" => vinst48 := r.d.rexbuf(15 downto 0) & de_inst1(31 downto 16) & de_inst1(15 downto 0);
when "10" => vinst48 := de_inst1(31 downto 16) & de_inst1(15 downto 0) & de_inst1(31 downto 16);
when others => vinst48 := de_inst1(15 downto 0) & de_inst1(15 downto 0) & de_inst1(15 downto 0);
end case;
vinst := vinst48(47 downto 16);
if REXPIPE then vinst:=de_inst1; end if;
isz := "01";
ncnt := "0";
vbaddr1 := '0';
veximm := '0';
if REXPIPE then
eximmval := r.d.rexpl.immval;
else
eximmval := vinst48(31 downto 13);
end if;
vgetpc := '0';
vmaskpv := '0';
villinst := '0';
vnostep := '0';
vitovr := '0';
vleave := '0';
vexpand := '0';
if r.d.rexen='1' then
if REXPIPE then
vinst := r.d.rexpl.opout;
isz := r.d.rexpl.szout;
ncnt := r.d.rexpl.ncntout;
vbaddr1 := r.d.rexpl.baddr1;
veximm := r.d.rexpl.immexp;
eximmval := r.d.rexpl.immval;
vgetpc := r.d.rexpl.getpc;
vmaskpv := r.d.rexpl.maskpv;
villinst := r.d.rexpl.illinst;
vnostep := r.d.rexpl.nostep;
vitovr := r.d.rexpl.itovr;
vleave := r.d.rexpl.leave;
else
rex_decode_main(vinst48, r.d.rexcnt, vinst, isz, ncnt,
vbaddr1, veximm, eximmval, vgetpc, vmaskpv,
villinst, vnostep, vitovr, vleave);
end if;
end if;
nrexen := nrexen and not vleave;
vexpand := ncnt(0);
-- Check size and current buffer loc. and decide on bubble or hold
-- bubble will insert annuled cycle in regfile stage
-- hold will hold the fetch,decode stages and insert vinst into regfile stage
-- rexpos isz | bubble hold n16pos
-- 00 00 | 0 1 01 (already has 48 bits left to process)
-- 00 01 | 0 0 00
-- 00 10 | 0 0 01
-- 01 00 | 0 0 00
-- 01 01 | 0 0 01
-- 01 10 | 0 0 10
-- 10 00 | 0 0 01
-- 10 01 | 0 0 10
-- 10 10 | 1 0 00 (need more data, 48 bit insn got 32)
-- 11 00 | 0 0 10 (special case after branch to "odd" addr)
-- 11 01 | 1 0 01 (special case after branch to "odd" addr)
-- 11 10 | 1 0 01 (special case after branch to "odd" addr)
vhold := '0'; vbubble := '0';
if r.d.rexpos="00" and isz="00" then vhold := '1'; end if;
if r.d.rexpos(1)='1' and (isz(1)='1' or (isz(0)='1' and r.d.rexpos(0)='1')) then vbubble:='1'; end if;
vpos := "00";
if (r.d.rexpos="11" and isz="00") or (r.d.rexpos="10" and isz(0)='1') or (isz(1)='1' and r.d.rexpos="01") then
vpos(1) := '1';
end if;
vpos(0) := r.d.rexpos(0) xor ((not isz(0)) and (not vbubble));
if REXPIPE and vleave='1' and r.d.rexpos(1)='0' then vhold:='1'; vpos(1):='1'; end if;
if REX=1 and r.f.branch='1' then
vpos := "1" & r.f.pc(1+(1-REX));
nrexen := r.f.pc(0);
-- Drop delay slot insn on taken branch
if r.d.rexen='1' then
vbubble := '1';
vhold := '0';
end if;
elsif r.d.rexen='1' and vexpand='1' then
vhold := '1';
vbubble := '0';
vpos := r.d.rexpos;
end if;
if vbubble='1' or r.d.annul='1' then ncnt:="0"; villinst:='0'; vnostep:='1'; end if;
if r.d.cnt/="00" then vitovr:='0'; end if;
if r.d.rexen='0' then vgetpc:='0'; villinst:='0'; vnostep:='0'; vmaskpv:='0'; vitovr:='0'; end if;
de_inst := vinst;
de_nrexen := nrexen;
de_nbufpos16 := vpos;
de_ncnt16 := ncnt;
de_rexhold := vhold;
de_rexbubble := vbubble;
de_rexbaddr1 := vbaddr1;
de_reximmexp := r.d.rexen and veximm;
de_reximmval := eximmval;
de_rexgetpc := vgetpc;
de_rexmaskpv := vmaskpv;
de_rexillinst := villinst;
de_rexnostep := vnostep;
de_rexitovr := vitovr;
end rex_decode;
procedure rex_pl_fetch(ndregs: decode_reg_type;
dregs: decode_reg_type;
holdn: std_ulogic;
plreg: out rex_pipeline_reg_type) is
variable ninst, oinst: std_logic_vector(31 downto 0);
variable pos: std_logic_vector(1 downto 0);
variable cnt: std_logic_vector(0 downto 0);
variable vinst48: std_logic_vector(47 downto 0); -- raw inst buffer
begin
if ISETS > 1 then ninst := ndregs.inst(conv_integer(ndregs.set));
else ninst := ndregs.inst(0); end if;
oinst := ndregs.rexbuf;
pos := ndregs.rexpos;
cnt := ndregs.rexcnt;
if holdn='0' then
oinst := dregs.rexbuf;
pos := dregs.rexpos;
cnt := dregs.rexcnt;
end if;
case pos is
when "00" => vinst48 := oinst(31 downto 16) & oinst(15 downto 0) & ninst(31 downto 16);
when "01" => vinst48 := oinst(15 downto 0) & ninst(31 downto 16) & ninst(15 downto 0);
when "10" => vinst48 := ninst(31 downto 16) & ninst(15 downto 0) & ninst(31 downto 16);
when others => vinst48 := ninst(15 downto 0) & ninst(31 downto 16) & ninst(15 downto 0);
end case;
rex_decode_main(vinst48, cnt,
plreg.opout, plreg.szout, plreg.ncntout,
plreg.baddr1, plreg.immexp, plreg.immval,
plreg.getpc, plreg.maskpv, plreg.illinst, plreg.nostep, plreg.itovr, plreg.leave);
end rex_pl_fetch;
signal dummy : std_ulogic;
signal cpu_index : std_logic_vector(3 downto 0);
signal disasen : std_ulogic;
begin
BPRED <= '0' when bp = 0 else not r.d.rexen when bp = 1 else not (r.w.s.dbp or r.d.rexen);
BLOCKBPMISS <= '0' when bp = 0 else '1' when bp = 1 else r.w.s.dbprepl;
comb : process(ico, dco, rfo, r, wpr, ir, dsur, rstn, holdn, irqi, dbgi, fpo, cpo, tbo, tbo_2p,
mulo, divo, dummy, rp, BPRED, BLOCKBPMISS)
variable v : registers;
variable vp : pwd_register_type;
variable vwpr : watchpoint_registers;
variable vdsu : dsu_registers;
variable fe_pc, fe_npc : std_logic_vector(31 downto PCLOW);
variable npc : std_logic_vector(31 downto PCLOW);
variable de_raddr1, de_raddr2 : std_logic_vector(9 downto 0);
variable de_rs2, de_rd : std_logic_vector(4 downto 0);
variable de_hold_pc, de_branch, de_ldlock : std_ulogic;
variable de_cwp, de_rcwp : cwptype;
variable de_inull : std_ulogic;
variable de_ren1, de_ren2 : std_ulogic;
variable de_wcwp : std_ulogic;
variable de_inst1, de_inst : word;
variable de_icc : std_logic_vector(3 downto 0);
variable de_fbranch, de_cbranch : std_ulogic;
variable de_rs1mod : std_ulogic;
variable de_bpannul : std_ulogic;
variable de_fins_hold : std_ulogic;
variable de_iperr : std_ulogic;
variable de_rexen, de_nrexen, de_rexhold, de_rexbubble, de_rexbaddr1 : std_ulogic;
variable de_rexmaskpv, de_rexnostep : std_ulogic;
variable de_rexillinst: std_ulogic;
variable de_nbufpos16: std_logic_vector(1 downto 0);
variable de_ncnt16: std_logic_vector(0 downto 0);
variable de_pcout: std_logic_vector(31 downto 0);
variable de_reximmexp: std_ulogic;
variable de_reximmval: std_logic_vector(31 downto 13);
variable ra_op1, ra_op2 : word;
variable ra_div : std_ulogic;
variable ra_bpmiss : std_ulogic;
variable ra_bpannul : std_ulogic;
variable ex_jump, ex_link_pc : std_ulogic;
variable ex_jump_address : pctype;
variable ex_add_res : std_logic_vector(32 downto 0);
variable ex_shift_res, ex_logic_res, ex_misc_res : word;
variable ex_edata, ex_edata2 : word;
variable ex_dci : dc_in_type;
variable ex_force_a2, ex_load, ex_ymsb : std_ulogic;
variable ex_op1, ex_op2, ex_result, ex_result2, ex_result3, mul_op2 : word;
variable ex_shcnt : std_logic_vector(4 downto 0);
variable ex_dsuen : std_ulogic;
variable ex_ldbp2 : std_ulogic;
variable ex_sari : std_ulogic;
variable ex_bpmiss : std_ulogic;
variable ex_cdata : std_logic_vector(31 downto 0);
variable ex_mulop1, ex_mulop2 : std_logic_vector(32 downto 0);
variable me_bp_res : word;
variable me_inull, me_nullify, me_nullify2 : std_ulogic;
variable me_iflush : std_ulogic;
variable me_newtt : std_logic_vector(5 downto 0);
variable me_asr18 : word;
variable me_signed : std_ulogic;
variable me_size, me_laddr : std_logic_vector(1 downto 0);
variable me_icc : std_logic_vector(3 downto 0);
variable xc_result : word;
variable xc_df_result : word;
variable xc_waddr : std_logic_vector(9 downto 0);
variable xc_exception, xc_wreg : std_ulogic;
variable xc_trap_address : pctype;
variable xc_newtt, xc_vectt : std_logic_vector(7 downto 0);
variable xc_trap : std_ulogic;
variable xc_fpexack : std_ulogic;
variable xc_rstn, xc_halt : std_ulogic;
variable xc_inull : std_ulogic;
variable xc_mmucacheclr : std_ulogic;
variable xc_wimmask: std_logic_vector(NWIN-1 downto 0);
variable xc_trapcwp: cwptype;
variable diagdata : word;
variable tbufi : tracebuf_in_type;
variable tbufi_2p : tracebuf_2p_in_type;
variable dbgm : std_ulogic;
variable fpcdbgwr : std_ulogic;
variable vfpi : fpc_in_type;
variable dsign : std_ulogic;
variable pwrd, sidle : std_ulogic;
variable vir : irestart_register;
variable xc_dflushl : std_ulogic;
variable xc_dcperr : std_ulogic;
variable st : std_ulogic;
variable icnt, fcnt : std_ulogic;
variable tbufcntx : std_logic_vector(TBUFBITS-1 downto 0);
variable tovx : std_ulogic;
variable bpmiss : std_ulogic;
begin
v := r; vwpr := wpr; vdsu := dsur; vp := rp;
xc_fpexack := '0'; sidle := '0';
fpcdbgwr := '0'; vir := ir; xc_rstn := rstn;
de_pcout := rex_dpc(r.d.pc, r.d.rexen, r.d.rexpos);
-----------------------------------------------------------------------
-- EXCEPTION STAGE
-----------------------------------------------------------------------
xc_exception := '0'; xc_halt := '0'; icnt := '0'; fcnt := '0';
xc_waddr := (others => '0');
xc_waddr(RFBITS-1 downto 0) := r.x.ctrl.rd(RFBITS-1 downto 0);
xc_trap := r.x.mexc or r.x.ctrl.trap;
v.x.nerror := rp.error; xc_dflushl := '0';
xc_mmucacheclr := '0';
xc_inull := '0';
if r.x.mexc = '1' then xc_vectt := "00" & TT_DAEX;
elsif r.x.ctrl.tt = TT_TICC then
xc_vectt := '1' & r.x.result(6 downto 0);
else xc_vectt := "00" & r.x.ctrl.tt; end if;
if r.w.s.svt = '0' then
xc_trap_address(31 downto 2) := r.w.s.tba & xc_vectt & "00";
else
xc_trap_address(31 downto 2) := r.w.s.tba & "00000000" & "00";
end if;
xc_trap_address(2 downto PCLOW) := (others => '0');
xc_wreg := '0'; v.x.annul_all := '0';
if (not r.x.ctrl.annul and r.x.ctrl.ld) = '1' then
if (lddel = 2) then
xc_result := ld_align(r.x.data, r.x.set, r.x.dci.size, r.x.laddr, r.x.dci.signed);
else
xc_result := r.x.data(0);
end if;
elsif MACEN and MACPIPE and ((not r.x.ctrl.annul and r.x.mac) = '1') then
xc_result := mulo.result(31 downto 0);
else xc_result := r.x.result; end if;
xc_df_result := xc_result;
xc_wimmask := (others => '0');
if RFPART then
for x in NWIN-1 downto 1 loop
if unsigned(r.w.s.cwpmax) < to_unsigned(x,NWINLOG2) then xc_wimmask(x) := '1'; end if;
end loop;
end if;
xc_trapcwp := r.w.s.cwp;
if RFPART then
if r.w.s.cwp=CWPMIN then
xc_trapcwp := r.w.twcwp;
else
xc_trapcwp := std_logic_vector(unsigned(r.w.s.stwin) + unsigned(r.w.s.cwp));
end if;
end if;
if DBGUNIT
then
dbgm := dbgexc(r, dbgi, xc_trap, xc_vectt, dsur);
if (dbgi.dsuen and dbgi.dbreak) = '0'then v.x.debug := '0'; end if;
else dbgm := '0'; v.x.debug := '0'; end if;
if PWRD2 then pwrd := powerdwn(r, xc_trap, rp); else pwrd := '0'; end if;
case r.x.rstate is
when run =>
if (dbgm
) /= '0' then
v.x.annul_all := '1'; vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1;
v.x.debug := '1';
v.x.npc := npc_find(r);
vdsu.tt := xc_vectt; vdsu.err := dbgerr(r, dbgi, xc_vectt);
elsif ((pwrd = '1') or (smp/=0 and irqi.forceerr='1')) and (ir.pwd = '0') then
v.x.annul_all := '1'; vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1; v.x.npc := npc_find(r); vp.pwd := '1';
elsif (r.x.ctrl.annul or xc_trap) = '0' then
xc_wreg := r.x.ctrl.wreg;
sp_write (r, wpr, v.w.s, vwpr);
vir.pwd := '0';
if (r.x.ctrl.pv and not r.x.debug) = '1' then
icnt := holdn;
if (r.x.ctrl.inst(31 downto 30) = FMT3) and
((r.x.ctrl.inst(24 downto 19) = FPOP1) or
(r.x.ctrl.inst(24 downto 19) = FPOP2))
then fcnt := holdn; end if;
end if;
elsif ((not r.x.ctrl.annul) and xc_trap) = '1' then
xc_exception := '1';
xc_result := (others => '0'); xc_result(31 downto PCLOW) := r.x.ctrl.pc(31 downto PCLOW);
xc_wreg := '1'; v.w.s.tt := xc_vectt; v.w.s.ps := r.w.s.s;
v.w.s.s := '1'; v.x.annul_all := '1'; v.x.rstate := trap;
xc_waddr := (others => '0');
xc_waddr(NWINLOG2 + 3 downto 0) := xc_trapcwp & "0001";
v.x.npc := npc_find(r);
fpexack(r, xc_fpexack);
if r.w.s.et = '0' then
-- v.x.rstate := dsu1; xc_wreg := '0'; vp.error := '1';
xc_wreg := '0';
end if;
end if;
when trap =>
xc_result := npc_gen(r,de_pcout); xc_wreg := '1';
xc_waddr := (others => '0');
xc_waddr(NWINLOG2 + 3 downto 0) := xc_trapcwp & "0010";
if r.w.s.et = '1' then
v.w.s.et := '0'; v.x.rstate := run;
if RFPART and (r.w.s.cwp = CWPMIN) then v.w.s.cwp := r.w.s.cwpmax;
elsif (not CWPOPT) and (r.w.s.cwp = CWPMIN) then v.w.s.cwp := CWPMAX;
else v.w.s.cwp := r.w.s.cwp - 1 ; end if;
if AWPEN then
v.w.s.aw := '0';
v.w.s.paw := r.w.s.aw;
end if;
else
xc_inull := '1';
v.x.rstate := dsu1; xc_wreg := '0'; vp.error := '1';
end if;
when dsu1 =>
xc_exception := '1'; v.x.annul_all := '1';
xc_trap_address(31 downto PCLOW) := r.f.pc;
if DBGUNIT or PWRD2 or (smp /= 0)
then
xc_trap_address(31 downto PCLOW) := ir.addr;
vir.addr := npc_gen(r,de_pcout)(31 downto PCLOW);
v.x.rstate := dsu2;
end if;
if DBGUNIT then v.x.debug := r.x.debug; end if;
when dsu2 =>
xc_exception := '1'; v.x.annul_all := '1';
xc_trap_address(31 downto PCLOW) := r.f.pc;
if DBGUNIT or PWRD2 or (smp /= 0)
then
sidle := (rp.pwd or rp.error) and ico.idle and dco.idle and not r.x.debug;
if DBGUNIT then
if dbgi.reset = '1' then
if smp /=0 then vp.pwd := not irqi.rstrun; else vp.pwd := '0'; end if;
vp.error := '0';
end if;
if (dbgi.dsuen and dbgi.dbreak) = '1'then v.x.debug := '1'; end if;
diagwr(r, dsur, ir, dbgi, wpr, v.w.s, vwpr, vdsu.asi, xc_trap_address,
vir.addr, vdsu.tbufcnt, vdsu.tfilt, xc_wreg, xc_waddr, xc_result, fpcdbgwr);
xc_halt := dbgi.halt;
end if;
if smp/=0 and (rp.pwd or rp.error)='1' and irqi.pwdsetaddr='1' then
xc_trap_address(31 downto PCLOW) := ir.addr;
vir.addr := (others => '0');
vir.addr(31 downto 2) := irqi.pwdnewaddr;
end if;
if (smp /= 0) and irqi.forceerr='1' then
vp.error := '1'; v.w.s.et := '0'; v.w.s.s := '1';
xc_mmucacheclr := '1';
end if;
if r.x.ipend = '1' then vp.pwd := '0'; end if;
if (rp.error or rp.pwd or r.x.debug or xc_halt) = '0' then
v.x.rstate := run; v.x.annul_all := '0'; vp.error := '0';
xc_trap_address(31 downto PCLOW) := ir.addr; v.x.debug := '0';
vir.pwd := '1';
if REX=1 and r.f.pc(2-2*REX)='1' then xc_exception:='0'; end if;
end if;
if (smp /= 0) and (irqi.resume = '1') then
vp.pwd := '0'; vp.error := '0';
end if;
end if;
when others =>
end case;
if DBGUNIT and TRACEBUF then
if (dbgi.dsuen and dbgi.denable and dbgi.dwrite) = '1' then
if (dbgi.daddr(23 downto 20) = "0001" and dbgi.daddr(16) = '1' and
dbgi.daddr(2) = '1') then
vdsu.tov := dbgi.ddata(23);
vdsu.tlim := dbgi.ddata(26 downto 24);
vdsu.tovb := dbgi.ddata(27);
end if;
end if;
end if;
dci.flushl <= xc_dflushl;
dci.mmucacheclr <= xc_mmucacheclr;
irq_intack(r, holdn, v.x.intack);
itrace(r, dsur, vdsu, xc_result, xc_exception, dbgi, rp.error, xc_trap, tbufcntx, tovx, tbufi, tbufi_2p, '0', xc_dcperr);
vdsu.tbufcnt := tbufcntx; vdsu.tov := tovx;
v.w.except := xc_exception; v.w.result := xc_result;
if (r.x.rstate = dsu2) then v.w.except := '0'; end if;
v.w.wa := xc_waddr(RFBITS-1 downto 0); v.w.wreg := xc_wreg and holdn;
if RFPART then
v.w.twcwp := std_logic_vector(unsigned(v.w.s.stwin) + unsigned(v.w.s.cwpmax) + 1);
if (not CWPOPT) and v.w.twcwp=CWPGLB then v.w.twcwp:=CWPMIN; end if;
end if;
rfi.wdata <= xc_result; rfi.waddr <= xc_waddr;
irqo.intack <= r.x.intack and holdn;
irqo.irl <= r.w.s.tt(3 downto 0);
irqo.pwd <= rp.pwd;
irqo.fpen <= r.w.s.ef;
irqo.err <= r.x.nerror;
dbgo.halt <= xc_halt;
dbgo.pwd <= rp.pwd;
dbgo.idle <= sidle;
dbgo.icnt <= icnt;
dbgo.fcnt <= fcnt;
dbgo.optype <= r.x.ctrl.inst(31 downto 30) & r.x.ctrl.inst(24 downto 21);
dci.intack <= r.x.intack and holdn;
if (not RESET_ALL) and (xc_rstn = '0') then
v.w.except := RRES.w.except; v.w.s.et := RRES.w.s.et;
v.w.s.svt := RRES.w.s.svt; v.w.s.dwt := RRES.w.s.dwt;
v.w.s.ef := RRES.w.s.ef;
if RFPART then
v.w.s.stwin := RRES.w.s.stwin;
v.w.s.cwpmax := RRES.w.s.cwpmax;
end if;
if need_extra_sync_reset(fabtech) /= 0 then
v.w.s.cwp := RRES.w.s.cwp;
v.w.s.icc := RRES.w.s.icc;
end if;
v.w.s.dbp := RRES.w.s.dbp;
v.w.s.dbprepl := RRES.w.s.dbprepl;
v.w.s.rexdis := RRES.w.s.rexdis;
v.w.s.rextrap := RRES.w.s.rextrap;
v.w.s.tba := RRES.w.s.tba;
v.x.annul_all := RRES.x.annul_all;
v.x.rstate := RRES.x.rstate; vir.pwd := IRES.pwd;
vp.pwd := PRES.pwd; v.x.debug := RRES.x.debug;
v.x.nerror := RRES.x.nerror;
if svt = 1 then v.w.s.tt := RRES.w.s.tt; end if;
if DBGUNIT then
if (dbgi.dsuen and dbgi.dbreak) = '1' then
v.x.rstate := dsu1; v.x.debug := '1';
end if;
vdsu.tfilt := DRES.tfilt; vdsu.tovb := DRES.tovb;
end if;
if (smp /= 0) and (irqi.rstrun = '0') and (rstn = '0') then
v.x.rstate := dsu1; vp.pwd := '1';
end if;
v.x.npc := "100";
end if;
-- kill off unused regs
if not FPEN then v.w.s.ef := '0'; end if;
if not CPEN then v.w.s.ec := '0'; end if;
-----------------------------------------------------------------------
-- MEMORY STAGE
-----------------------------------------------------------------------
v.x.ctrl := r.m.ctrl; v.x.dci := r.m.dci;
v.x.ctrl.rett := r.m.ctrl.rett and not r.m.ctrl.annul;
v.x.mac := r.m.mac; v.x.laddr := r.m.result(1 downto 0);
v.x.ctrl.annul := r.m.ctrl.annul or v.x.annul_all;
st := '0';
if CASAEN and (r.m.casa = '1') and (r.m.ctrl.cnt = "00") then
v.x.ctrl.inst(4 downto 0) := r.a.ctrl.inst(4 downto 0); -- restore rs2 for trace log
end if;
mul_res(r, v.w.s.asr18, v.x.result, v.x.y, me_asr18, me_icc);
mem_trap(r, wpr, v.x.ctrl.annul, holdn, v.x.ctrl.trap, me_iflush,
me_nullify, v.m.werr, v.x.ctrl.tt);
me_newtt := v.x.ctrl.tt;
irq_trap(r, ir, irqi.irl, v.x.ctrl.annul, v.x.ctrl.pv, v.x.ctrl.trap, me_newtt, me_nullify,
v.m.irqen, v.m.irqen2, me_nullify2, v.x.ctrl.trap,
v.x.ipend, v.x.ctrl.tt);
if (r.m.ctrl.ld or st or not dco.mds) = '1' then
for i in 0 to dsets-1 loop
v.x.data(i) := dco.data(i);
end loop;
v.x.set := dco.set(DSETMSB downto 0);
if dco.mds = '0' then
me_size := r.x.dci.size; me_laddr := r.x.laddr; me_signed := r.x.dci.signed;
else
me_size := v.x.dci.size; me_laddr := v.x.laddr; me_signed := v.x.dci.signed;
end if;
if (lddel /= 2) then
v.x.data(0) := ld_align(v.x.data, v.x.set, me_size, me_laddr, me_signed);
end if;
end if;
if (not RESET_ALL) and (is_fpga(fabtech) = 0) and (xc_rstn = '0') then
v.x.data := (others => (others => '0')); --v.x.ldc := '0';
end if;
v.x.mexc := dco.mexc;
v.x.icc := me_icc;
v.x.ctrl.wicc := r.m.ctrl.wicc and not v.x.annul_all;
if MACEN and ((v.x.ctrl.annul or v.x.ctrl.trap) = '0') then
v.w.s.asr18 := me_asr18;
end if;
if (r.x.rstate = dsu2)
then
me_nullify2 := '0'; v.x.set := dco.set(DSETMSB downto 0);
end if;
if (not RESET_ALL) and (xc_rstn = '0') then
v.x.ctrl.trap := '0'; v.x.ctrl.annul := '1';
end if;
dci.maddress <= r.m.result;
dci.enaddr <= r.m.dci.enaddr;
dci.asi <= r.m.dci.asi;
dci.size <= r.m.dci.size;
dci.lock <= (r.m.dci.lock and not r.m.ctrl.annul);
dci.read <= r.m.dci.read;
dci.write <= r.m.dci.write;
dci.flush <= me_iflush;
dci.dsuen <= r.m.dci.dsuen;
dci.msu <= r.m.su;
dci.esu <= r.e.su;
dbgo.ipend <= v.x.ipend or irqi.forceerr or irqi.pwdsetaddr;
-----------------------------------------------------------------------
-- EXECUTE STAGE
-----------------------------------------------------------------------
v.m.ctrl := r.e.ctrl; ex_op1 := r.e.op1; ex_op2 := r.e.op2;
v.m.ctrl.rett := r.e.ctrl.rett and not r.e.ctrl.annul;
v.m.ctrl.wreg := r.e.ctrl.wreg and not v.x.annul_all;
ex_ymsb := r.e.ymsb; mul_op2 := ex_op2; ex_shcnt := r.e.shcnt;
v.e.cwp := r.a.cwp; ex_sari := r.e.sari;
v.m.su := r.e.su;
if MULTYPE = 3 then v.m.mul := r.e.mul; else v.m.mul := '0'; end if;
if lddel = 1 then
if r.e.ldbp1 = '1' then
ex_op1 := r.x.data(0);
ex_sari := r.x.data(0)(31) and r.e.ctrl.inst(19) and r.e.ctrl.inst(20);
end if;
if r.e.ldbp2 = '1' then
ex_op2 := r.x.data(0); ex_ymsb := r.x.data(0)(0);
mul_op2 := ex_op2; ex_shcnt := r.x.data(0)(4 downto 0);
if r.e.invop2 = '1' then
ex_op2 := not ex_op2; ex_shcnt := not ex_shcnt;
end if;
end if;
end if;
ex_add_res := (ex_op1 & '1') + (ex_op2 & r.e.alucin);
if ex_add_res(2 downto 1) = "00" then v.m.nalign := '0';
else v.m.nalign := '1'; end if;
if REX=1 then
if ex_add_res(2 downto 1) /= "10" then v.m.rexnalign := '0';
else v.m.rexnalign := '1'; end if;
end if;
dcache_gen(r, v, ex_dci, ex_link_pc, ex_jump, ex_force_a2, ex_load, v.m.casa);
ex_jump_address := ex_add_res(32 downto PCLOW+1);
logic_op(r, ex_op1, ex_op2, v.x.y, ex_ymsb, ex_logic_res, v.m.y);
ex_shift_res := shift(r, ex_op1, ex_op2, ex_shcnt, ex_sari);
misc_op(r, wpr, ex_op1, ex_op2, xc_df_result, v.x.y, xc_wimmask, ex_misc_res, ex_edata);
ex_add_res(3):= ex_add_res(3) or ex_force_a2;
if CASAEN and LDDEL=2 and (r.m.casa='1' and r.e.ctrl.cnt="11") then
ex_add_res(32 downto 1) := r.e.op2;
end if;
alu_select(r, ex_add_res, ex_op1, ex_op2, ex_shift_res, ex_logic_res,
ex_misc_res, ex_result, me_icc, v.m.icc, v.m.divz, v.m.casaz);
dbg_cache(holdn, dbgi, r, dsur, ex_result, ex_dci, ex_result2, v.m.dci);
fpstdata(r, ex_edata, ex_result2, fpo.data, ex_edata2, ex_result3);
v.m.result := ex_result3;
cwp_ex(r, v.m.wcwp, v.m.wawp);
if CASAEN and ( (LDDEL=1 and (r.m.casa='1' and r.e.ctrl.cnt="10")) or
(LDDEL=2 and (r.m.casa='1' and r.e.ctrl.cnt="11")))
and v.m.casaz='0' then
me_nullify2 := '1';
end if;
dci.nullify <= me_nullify2;
ex_mulop1 := (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
ex_mulop2 := (mul_op2(31) and r.e.ctrl.inst(19)) & mul_op2;
if is_fpga(fabtech) = 0 and (r.e.mul = '0') then -- power-save for mul
-- if (r.e.mul = '0') then
ex_mulop1 := (others => '0'); ex_mulop2 := (others => '0');
end if;
v.m.ctrl.annul := v.m.ctrl.annul or v.x.annul_all;
v.m.ctrl.wicc := r.e.ctrl.wicc and not v.x.annul_all;
v.m.mac := r.e.mac;
if (DBGUNIT and (r.x.rstate = dsu2)) then v.m.ctrl.ld := '1'; end if;
dci.eenaddr <= v.m.dci.enaddr;
dci.eaddress <= ex_add_res(32 downto 1);
dci.edata <= ex_edata2;
bp_miss_ex(r, r.m.icc, ex_bpmiss, ra_bpannul);
-----------------------------------------------------------------------
-- REGFILE STAGE
-----------------------------------------------------------------------
v.e.ctrl := r.a.ctrl; v.e.jmpl := r.a.jmpl and not r.a.ctrl.trap;
v.e.ctrl.annul := r.a.ctrl.annul or ra_bpannul or v.x.annul_all;
v.e.ctrl.rett := r.a.ctrl.rett and not r.a.ctrl.annul and not r.a.ctrl.trap;
v.e.ctrl.wreg := r.a.ctrl.wreg and not (ra_bpannul or v.x.annul_all);
v.e.su := r.a.su; v.e.et := r.a.et;
v.e.ctrl.wicc := r.a.ctrl.wicc and not (ra_bpannul or v.x.annul_all);
v.e.rfe1 := r.a.rfe1; v.e.rfe2 := r.a.rfe2;
exception_detect(r, wpr, dbgi, r.a.ctrl.trap, r.a.ctrl.tt,
v.e.ctrl.trap, v.e.ctrl.tt);
op_mux(r, rfo.data1, ex_result3, v.x.result, xc_df_result, zero32,
r.a.rsel1, v.e.ldbp1, ra_op1, '0');
op_mux(r, rfo.data2, ex_result3, v.x.result, xc_df_result, r.a.imm,
r.a.rsel2, ex_ldbp2, ra_op2, '1');
alu_op(r, ra_op1, ra_op2, v.m.icc, v.m.y(0), ex_ldbp2, v.e.op1, v.e.op2,
v.e.aluop, v.e.alusel, v.e.aluadd, v.e.shcnt, v.e.sari, v.e.shleft,
v.e.ymsb, v.e.mul, ra_div, v.e.mulstep, v.e.mac, v.e.ldbp2, v.e.invop2
);
cin_gen(r, v.m.icc(0), v.e.alucin);
bp_miss_ra(r, ra_bpmiss, de_bpannul);
v.e.bp := r.a.bp and not ra_bpmiss;
-----------------------------------------------------------------------
-- DECODE STAGE
-----------------------------------------------------------------------
if ISETS > 1 then de_inst1 := r.d.inst(conv_integer(r.d.set));
else de_inst1 := r.d.inst(0); end if;
de_nrexen := '0'; de_nbufpos16:="10"; de_ncnt16:="0"; de_rexhold:='0';
de_rexbubble := '0'; de_rexbaddr1:='0'; de_reximmexp:='0'; de_reximmval:=(others => '0');
de_rexmaskpv := '0'; de_rexillinst:='0'; de_rexnostep:='0';
if REX=1 then
rex_decode(r, de_inst1, de_inst, de_nrexen, de_nbufpos16, de_ncnt16,
de_rexhold, de_rexbubble, de_rexbaddr1, de_reximmexp,
de_reximmval, v.a.getpc, de_rexmaskpv, de_rexillinst,
de_rexnostep, v.a.ctrl.itovr);
else
de_inst := de_inst1;
end if;
de_icc := r.m.icc; v.a.cwp := r.d.cwp;
if AWPEN then
v.a.awp:=r.d.awp; v.a.aw:=r.d.aw; v.a.paw:=r.d.paw;
v.e.awp:=r.a.awp; v.e.aw:=r.a.aw; v.e.paw:=r.a.paw;
end if;
su_et_select(r, v.w.s.ps, v.w.s.s, v.w.s.et, v.a.su, v.a.et);
wicc_y_gen(de_inst, v.a.ctrl.wicc, v.a.ctrl.wy);
de_rcwp := r.d.cwp;
if AWPEN and r.d.aw='1' then de_rcwp := r.d.awp; end if;
cwp_ctrl(r, de_rcwp, v.w.s.wim, de_inst, de_cwp, v.a.wovf, v.a.wunf, de_wcwp);
if AWPEN and (r.d.aw='1' or (r.d.paw='1' and de_inst(24 downto 19)=RETT)) then v.a.wovf:='0'; v.a.wunf:='0'; end if;
if CASAEN and (de_inst(31 downto 30) = LDST) and (de_inst(24 downto 19) = CASA) then
case r.d.cnt is
when "00" | "01" => de_inst(4 downto 0) := "00000"; -- rs2=0
when others =>
end case;
end if;
rs1_gen(r, de_inst, v.a.rs1, de_rs1mod);
de_rs2 := de_inst(4 downto 0);
de_raddr1 := (others => '0'); de_raddr2 := (others => '0');
if RS1OPT then
if de_rs1mod = '1' then
regaddr(de_rcwp, de_inst(29 downto 26) & v.a.rs1(0), r.d.stwin, r.d.cwpmax, de_raddr1(RFBITS-1 downto 0));
else
regaddr(de_rcwp, de_inst(18 downto 15) & v.a.rs1(0), r.d.stwin, r.d.cwpmax, de_raddr1(RFBITS-1 downto 0));
end if;
else
regaddr(de_rcwp, v.a.rs1, r.d.stwin, r.d.cwpmax, de_raddr1(RFBITS-1 downto 0));
end if;
regaddr(de_rcwp, de_rs2, r.d.stwin, r.d.cwpmax, de_raddr2(RFBITS-1 downto 0));
v.a.rfa1 := de_raddr1(RFBITS-1 downto 0);
v.a.rfa2 := de_raddr2(RFBITS-1 downto 0);
rd_gen(r, de_inst, v.a.ctrl.wreg, v.a.ctrl.ld, de_rd, de_rexen);
if r.d.annul='1' then de_rexen:='0'; end if;
regaddr(de_cwp, de_rd, r.d.stwin, r.d.cwpmax, v.a.ctrl.rd);
fpbranch(de_inst, fpo.cc, de_fbranch);
fpbranch(de_inst, cpo.cc, de_cbranch);
v.a.imm := imm_data(r, de_inst, de_reximmexp, de_reximmval);
de_iperr := '0';
lock_gen(r, de_rs2, de_rd, v.a.rfa1, v.a.rfa2, v.a.ctrl.rd, de_inst,
fpo.ldlock, v.e.mul, ra_div, de_wcwp, v.a.ldcheck1, v.a.ldcheck2, de_ldlock,
v.a.ldchkra, v.a.ldchkex, v.a.bp, v.a.nobp, de_fins_hold, de_iperr, ico.bpmiss);
ic_ctrl(r, de_inst, v.x.annul_all, de_ldlock, de_rexhold, de_rexbubble, de_rexmaskpv, de_rexillinst, branch_true(de_icc, de_inst),
de_fbranch, de_cbranch, fpo.ccv, cpo.ccv, v.d.cnt, v.d.pc, de_branch,
v.a.ctrl.annul, v.d.annul, v.a.jmpl, de_inull, v.d.pv, v.a.ctrl.pv,
de_hold_pc, v.a.ticc, v.a.ctrl.rett, v.a.mulstart, v.a.divstart,
ra_bpmiss, ex_bpmiss, de_iperr, ico.bpmiss, ico.eocl);
v.d.pcheld := de_hold_pc;
v.a.bp := v.a.bp and not v.a.ctrl.annul;
v.a.nobp := v.a.nobp and not v.a.ctrl.annul;
v.a.ctrl.inst := de_inst;
v.a.decill := de_rexillinst or (de_rexen and r.w.s.rextrap);
cwp_gen(r, v, v.a.ctrl.annul, de_wcwp, de_cwp, v.d.cwp, v.d.awp, v.d.aw, v.d.paw, v.d.stwin, v.d.cwpmax);
v.d.inull := ra_inull_gen(r, v);
op_find(r, v.a.ldchkra, v.a.ldchkex, v.a.rs1, v.a.rfa1,
false, v.a.rfe1, v.a.rsel1, v.a.ldcheck1);
op_find(r, v.a.ldchkra, v.a.ldchkex, de_rs2, v.a.rfa2,
imm_select(de_inst,(de_rexen and not r.w.s.rexdis)), v.a.rfe2, v.a.rsel2, v.a.ldcheck2);
if CASAEN and lddel=2 and r.a.ctrl.cnt="10" and v.m.casa='1' then
v.a.rsel1 := "000";
v.a.rsel2 := "011";
v.a.rfe1 := '1';
end if;
v.a.ctrl.wicc := v.a.ctrl.wicc and (not v.a.ctrl.annul)
;
v.a.ctrl.wreg := v.a.ctrl.wreg and (not v.a.ctrl.annul)
;
v.a.ctrl.rett := v.a.ctrl.rett and (not v.a.ctrl.annul)
;
v.a.ctrl.wy := v.a.ctrl.wy and (not v.a.ctrl.annul)
;
v.a.ctrl.trap := r.d.mexc
;
v.a.ctrl.tt := "000000";
if r.d.mexc = '1' then
v.a.ctrl.tt := "000001";
end if;
v.a.ctrl.pc := de_pcout(31 downto PCLOW);
v.a.ctrl.cnt := r.d.cnt;
v.a.step := r.d.step;
if holdn = '0' then
de_raddr1(RFBITS-1 downto 0) := r.a.rfa1;
de_raddr2(RFBITS-1 downto 0) := r.a.rfa2;
de_ren1 := r.a.rfe1; de_ren2 := r.a.rfe2;
else
de_ren1 := v.a.rfe1; de_ren2 := v.a.rfe2;
end if;
if DBGUNIT then
if (dbgi.denable = '1') and (r.x.rstate = dsu2) then
de_raddr1(RFBITS-1 downto 0) := dbgi.daddr(RFBITS+1 downto 2); de_ren1 := '1';
de_raddr2 := de_raddr1; de_ren2 := '1';
end if;
v.d.step := dbgi.step and not r.d.annul and not de_rexnostep;
end if;
if de_hold_pc='0' then
v.d.rexen := de_nrexen or de_rexen;
v.d.rexpos := de_nbufpos16;
v.d.rexcnt := de_ncnt16;
end if;
if (de_rexhold='1' and de_branch='0') then de_hold_pc:='1'; de_inull:='1'; end if;
if v.x.annul_all='1' then
v.d.rexen := '0';
v.d.rexpos := "10";
end if;
rfi.wren <= (xc_wreg and holdn);
rfi.raddr1 <= de_raddr1; rfi.raddr2 <= de_raddr2;
rfi.ren1 <= de_ren1;
rfi.ren2 <= de_ren2;
ici.inull <= de_inull or xc_inull
;
ici.flush <= me_iflush;
v.d.divrdy := divo.nready;
ici.fline <= r.x.ctrl.pc(31 downto 3);
ici.nobpmiss <= (r.a.bp or r.e.bp) and BLOCKBPMISS;
dbgo.bpmiss <= bpmiss and holdn;
if (xc_rstn = '0') then
v.d.cnt := (others => '0');
v.d.rexen := '0';
v.d.rexpos := "10";
if need_extra_sync_reset(fabtech) /= 0 then
v.d.cwp := (others => '0');
end if;
end if;
-----------------------------------------------------------------------
-- FETCH STAGE
-----------------------------------------------------------------------
bpmiss := ex_bpmiss or ra_bpmiss;
npc := r.f.pc; fe_pc := r.f.pc;
if ra_bpmiss = '1' then fe_pc := r.d.pc; end if;
if ex_bpmiss = '1' then fe_pc := r.a.ctrl.pc; end if;
fe_npc := zero32(31 downto PCLOW);
fe_npc(31 downto 2) := fe_pc(31 downto 2) + 1; -- Address incrementer
v.a.bpimiss := '0';
if (xc_rstn = '0') then
if (not RESET_ALL) then
v.f.pc := (others => '0'); v.f.branch := '0';
if DYNRST then v.f.pc(31 downto 12) := irqi.rstvec;
else
v.f.pc(31 downto 12) := conv_std_logic_vector(rstaddr, 20);
end if;
end if;
elsif xc_exception = '1' then -- exception
v.f.branch := '1'; v.f.pc := xc_trap_address;
npc := v.f.pc;
elsif de_hold_pc = '1' then
v.f.pc := r.f.pc; v.f.branch := r.f.branch;
if bpmiss = '1' then
v.f.pc := fe_npc; v.f.branch := '1';
npc := v.f.pc;
elsif ex_jump = '1' then
v.f.pc := ex_jump_address; v.f.branch := '1';
npc := v.f.pc;
end if;
elsif (ex_jump and not bpmiss) = '1' then
v.f.pc := ex_jump_address; v.f.branch := '1';
npc := v.f.pc;
elsif (((ico.bpmiss and not r.d.annul) or r.a.bpimiss) and not bpmiss) = '1' then
v.f.pc := r.d.pc; v.f.branch := '1';
npc := v.f.pc;
v.a.bpimiss := ico.bpmiss and not r.d.annul;
elsif (de_branch and not bpmiss
) = '1'
then
v.f.pc := branch_address(de_inst, de_pcout(31 downto PCLOW), de_rexbaddr1, r.d.rexen); v.f.branch := '1';
npc := v.f.pc;
else
v.f.branch := bpmiss; v.f.pc := fe_npc; npc := v.f.pc;
end if;
ici.dpc <= r.d.pc(31 downto 2) & "00";
ici.fpc <= r.f.pc(31 downto 2) & "00";
ici.rpc <= npc(31 downto 2) & "00";
ici.fbranch <= r.f.branch;
ici.rbranch <= v.f.branch;
ici.su <= v.a.su;
if (ico.mds and de_hold_pc) = '0' then
v.d.rexbuf := de_inst1;
for i in 0 to isets-1 loop
v.d.inst(i) := ico.data(i); -- latch instruction
end loop;
v.d.set := ico.set(ISETMSB downto 0); -- latch instruction
v.d.mexc := ico.mexc; -- latch instruction
end if;
-- For pipelined REX implementation
if REX/=0 and REXPIPE then
rex_pl_fetch(v.d,r.d,holdn,
v.d.rexpl);
end if;
-----------------------------------------------------------------------
-----------------------------------------------------------------------
if DBGUNIT then -- DSU diagnostic read
diagread(dbgi, r, dsur, ir, wpr, dco, tbo, tbo_2p, xc_wimmask, diagdata);
diagrdy(dbgi.denable, dsur, r.m.dci, dco.mds, ico, vdsu.crdy);
vdsu.cfc := dsur.cfc(3 downto 0) & r.f.branch;
end if;
-----------------------------------------------------------------------
-- OUTPUTS
-----------------------------------------------------------------------
rin <= v; wprin <= vwpr; dsuin <= vdsu; irin <= vir;
muli.start <= r.a.mulstart and not r.a.ctrl.annul and
not r.a.ctrl.trap and not ra_bpannul;
muli.signed <= r.e.ctrl.inst(19);
muli.op1 <= ex_mulop1; --(ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
muli.op2 <= ex_mulop2; --(mul_op2(31) and r.e.ctrl.inst(19)) & mul_op2;
muli.mac <= r.e.ctrl.inst(24);
if MACPIPE then muli.acc(39 downto 32) <= r.w.s.y(7 downto 0);
else muli.acc(39 downto 32) <= r.x.y(7 downto 0); end if;
muli.acc(31 downto 0) <= r.w.s.asr18;
muli.flush <= r.x.annul_all;
divi.start <= r.a.divstart and not r.a.ctrl.annul and
not r.a.ctrl.trap and not ra_bpannul;
divi.signed <= r.e.ctrl.inst(19);
divi.flush <= r.x.annul_all;
divi.op1 <= (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
divi.op2 <= (ex_op2(31) and r.e.ctrl.inst(19)) & ex_op2;
if (r.a.divstart and not r.a.ctrl.annul) = '1' then
dsign := r.a.ctrl.inst(19);
else dsign := r.e.ctrl.inst(19); end if;
divi.y <= (r.m.y(31) and dsign) & r.m.y;
rpin <= vp;
if DBGUNIT then
dbgo.dsu <= '1'; dbgo.dsumode <= r.x.debug; dbgo.crdy <= dsur.crdy(2);
dbgo.data <= diagdata;
if TRACEBUF then
tbi <= tbufi;
if TRACEBUF_2P then tbi_2p <= tbufi_2p; else tbi_2p <= tracebuf_2p_in_type_none; end if;
else
tbi <= tracebuf_in_type_none;
tbi_2p <= tracebuf_2p_in_type_none;
end if;
else
dbgo.dsu <= '0'; dbgo.data <= (others => '0'); dbgo.crdy <= '0';
dbgo.dsumode <= '0'; tbi.addr <= (others => '0');
tbi.data <= (others => '0'); tbi.enable <= '0';
tbi.write <= (others => '0');
end if;
dbgo.error <= dummy and not r.x.nerror;
dbgo.istat <= ico.cstat;
dbgo.dstat <= dco.cstat;
dbgo.wbhold <= dco.wbhold;
dbgo.su <= r.w.s.s;
if FPEN then
if (r.x.rstate = dsu2) then vfpi.flush := '1'; else vfpi.flush := v.x.annul_all and holdn; end if;
vfpi.exack := xc_fpexack; vfpi.a_rs1 := r.a.rs1; vfpi.d.inst := de_inst;
vfpi.d.cnt := r.d.cnt;
vfpi.d.annul := v.x.annul_all or de_bpannul or r.d.annul or de_fins_hold or (ico.bpmiss and not r.d.pcheld)
;
vfpi.d.trap := r.d.mexc;
vfpi.d.pc(1 downto 0) := (others => '0'); vfpi.d.pc(31 downto PCLOW) := r.d.pc(31 downto PCLOW);
vfpi.d.pv := r.d.pv;
vfpi.a.pc(1 downto 0) := (others => '0'); vfpi.a.pc(31 downto PCLOW) := r.a.ctrl.pc(31 downto PCLOW);
vfpi.a.inst := r.a.ctrl.inst; vfpi.a.cnt := r.a.ctrl.cnt; vfpi.a.trap := r.a.ctrl.trap;
vfpi.a.annul := r.a.ctrl.annul or (ex_bpmiss and r.e.ctrl.inst(29))
;
vfpi.a.pv := r.a.ctrl.pv;
vfpi.e.pc(1 downto 0) := (others => '0'); vfpi.e.pc(31 downto PCLOW) := r.e.ctrl.pc(31 downto PCLOW);
vfpi.e.inst := r.e.ctrl.inst; vfpi.e.cnt := r.e.ctrl.cnt; vfpi.e.trap := r.e.ctrl.trap; vfpi.e.annul := r.e.ctrl.annul;
vfpi.e.pv := r.e.ctrl.pv;
vfpi.m.pc(1 downto 0) := (others => '0'); vfpi.m.pc(31 downto PCLOW) := r.m.ctrl.pc(31 downto PCLOW);
vfpi.m.inst := r.m.ctrl.inst; vfpi.m.cnt := r.m.ctrl.cnt; vfpi.m.trap := r.m.ctrl.trap; vfpi.m.annul := r.m.ctrl.annul;
vfpi.m.pv := r.m.ctrl.pv;
vfpi.x.pc(1 downto 0) := (others => '0'); vfpi.x.pc(31 downto PCLOW) := r.x.ctrl.pc(31 downto PCLOW);
vfpi.x.inst := r.x.ctrl.inst; vfpi.x.cnt := r.x.ctrl.cnt; vfpi.x.trap := xc_trap;
vfpi.x.annul := r.x.ctrl.annul; vfpi.x.pv := r.x.ctrl.pv;
if (lddel = 2) then vfpi.lddata := r.x.data(conv_integer(r.x.set)); else vfpi.lddata := r.x.data(0); end if;
if (r.x.rstate = dsu2)
then vfpi.dbg.enable := dbgi.denable;
else vfpi.dbg.enable := '0'; end if;
vfpi.dbg.write := fpcdbgwr;
vfpi.dbg.fsr := dbgi.daddr(22); -- IU reg access
vfpi.dbg.addr := dbgi.daddr(6 downto 2);
vfpi.dbg.data := dbgi.ddata;
fpi <= vfpi;
cpi <= vfpi; -- dummy, just to kill some warnings ...
end if;
end process;
preg : process (sclk)
begin
if rising_edge(sclk) then
rp <= rpin;
if rstn = '0' then
rp.error <= PRES.error;
if RESET_ALL then
if (smp /= 0) and (irqi.rstrun = '0') then
rp.pwd <= '1';
else
rp.pwd <= '0';
end if;
end if;
end if;
end if;
end process;
reg : process (clk)
begin
if rising_edge(clk) then
if (holdn = '1') then
r <= rin;
else
r.x.ipend <= rin.x.ipend;
r.m.werr <= rin.m.werr;
if (holdn or ico.mds) = '0' then
r.d.inst <= rin.d.inst; r.d.mexc <= rin.d.mexc;
r.d.set <= rin.d.set;
r.d.rexpl <= rin.d.rexpl;
end if;
if (holdn or dco.mds) = '0' then
r.x.data <= rin.x.data; r.x.mexc <= rin.x.mexc;
r.x.set <= rin.x.set;
end if;
end if;
if rstn = '0' then
if RESET_ALL then
r <= RRES;
if DYNRST then
r.f.pc(31 downto 12) <= irqi.rstvec;
r.w.s.tba <= irqi.rstvec;
end if;
if DBGUNIT then
if (dbgi.dsuen and dbgi.dbreak) = '1' then
r.x.rstate <= dsu1; r.x.debug <= '1';
end if;
end if;
if (smp /= 0) and irqi.rstrun = '0' then
r.x.rstate <= dsu1;
end if;
else
r.w.s.s <= '1'; r.w.s.ps <= '1';
if need_extra_sync_reset(fabtech) /= 0 then
r.d.inst <= (others => (others => '0'));
r.x.mexc <= '0';
end if;
end if;
end if;
if REX=0 then
r.d.rexen <= RRES.d.rexen;
r.d.rexpos <= RRES.d.rexpos;
r.d.rexbuf <= RRES.d.rexbuf;
r.d.rexcnt <= RRES.d.rexcnt;
r.a.getpc <= RRES.a.getpc;
r.a.decill <= RRES.a.decill;
r.m.rexnalign <= RRES.m.rexnalign;
r.a.ctrl.itovr <= RRES.a.ctrl.itovr;
r.e.ctrl.itovr <= RRES.e.ctrl.itovr;
r.m.ctrl.itovr <= RRES.m.ctrl.itovr;
r.x.ctrl.itovr <= RRES.x.ctrl.itovr;
end if;
if not REXPIPE then r.d.rexpl <= RRES.d.rexpl; end if;
if not AWPEN then
r.w.s.aw <= RRES.w.s.aw;
r.w.s.paw <= RRES.w.s.paw;
r.w.s.awp <= RRES.w.s.awp;
r.d.awp <= RRES.d.awp;
r.d.aw <= RRES.d.aw;
r.d.paw <= RRES.d.paw;
r.a.awp <= RRES.a.awp;
r.a.aw <= RRES.a.aw;
r.a.paw <= RRES.a.paw;
r.m.wawp <= RRES.m.wawp;
end if;
if not RFPART then
r.w.s.stwin <= RRES.w.s.stwin;
r.w.s.cwpmax <= RRES.w.s.cwpmax;
r.w.twcwp <= RRES.w.twcwp;
r.d.stwin <= RRES.d.stwin;
r.d.cwpmax <= RRES.d.cwpmax;
end if;
end if;
end process;
dsugen : if DBGUNIT generate
dsureg : process(clk) begin
if rising_edge(clk) then
if holdn = '1' then
dsur <= dsuin;
else
dsur.crdy <= dsuin.crdy;
end if;
if rstn = '0' then
if RESET_ALL then
dsur <= DRES;
elsif need_extra_sync_reset(fabtech) /= 0 then
dsur.err <= '0'; dsur.tbufcnt <= (others => '0'); dsur.tt <= (others => '0');
dsur.asi <= (others => '0'); dsur.crdy <= (others => '0');
end if;
end if;
end if;
end process;
end generate;
nodsugen : if not DBGUNIT generate
dsur.err <= '0'; dsur.tbufcnt <= (others => '0'); dsur.tt <= (others => '0');
dsur.asi <= (others => '0'); dsur.crdy <= (others => '0');
dsur.tfilt <= (others => '0'); dsur.cfc <= (others => '0');
dsur.tlim <= (others => '0'); dsur.tov <= '0'; dsur.tovb <= '0';
end generate;
irreg : if DBGUNIT or PWRD2
generate
dsureg : process(clk) begin
if rising_edge(clk) then
if holdn = '1' then ir <= irin; end if;
if RESET_ALL and rstn = '0' then ir <= IRES; end if;
end if;
end process;
end generate;
nirreg : if not (DBGUNIT or PWRD2
)
generate
ir.pwd <= '0'; ir.addr <= (others => '0');
end generate;
wpgen : for i in 0 to 3 generate
wpg0 : if nwp > i generate
wpreg : process(clk) begin
if rising_edge(clk) then
if holdn = '1' then wpr(i) <= wprin(i); end if;
if rstn = '0' then
if RESET_ALL then
wpr(i) <= wpr_none;
else
wpr(i).exec <= '0'; wpr(i).load <= '0'; wpr(i).store <= '0';
end if;
end if;
end if;
end process;
end generate;
wpg1 : if nwp <= i generate
wpr(i) <= wpr_none;
end generate;
end generate;
-- pragma translate_off
trc : process(clk)
variable valid : boolean;
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable fpins, fpld : boolean;
variable pc: std_logic_vector(31 downto 0);
variable rexen: boolean;
begin
if (fpu /= 0) then
op := r.x.ctrl.inst(31 downto 30); op3 := r.x.ctrl.inst(24 downto 19);
fpins := (op = FMT3) and ((op3 = FPOP1) or (op3 = FPOP2));
fpld := (op = LDST) and ((op3 = LDF) or (op3 = LDDF) or (op3 = LDFSR));
else
fpins := false; fpld := false;
end if;
valid := (((not r.x.ctrl.annul) and (r.x.ctrl.pv or r.x.ctrl.itovr)) = '1') and (not ((fpins or fpld) and (r.x.ctrl.trap = '0')));
valid := valid and (holdn = '1');
pc := r.x.ctrl.pc(31 downto 2) & "00";
rexen:=false;
if rex=1 then pc(1):=r.x.ctrl.pc(2-1*REX); rexen:=(r.x.ctrl.pc(2-2*REX)='1'); end if;
if (disas = 1) and rising_edge(clk) and (rstn = '1') then
print_insn (index, pc, r.x.ctrl.inst,
rin.w.result, valid, r.x.ctrl.trap = '1', rin.w.wreg = '1',
rexen);
end if;
end process;
-- pragma translate_on
dis0 : if disas < 2 generate dummy <= '1'; end generate;
dis2 : if disas > 1 generate
disasen <= '1' when disas /= 0 else '0';
cpu_index <= conv_std_logic_vector(index, 4);
x0 : cpu_disasx
port map (clk, rstn, dummy, r.x.ctrl.inst, r.x.ctrl.pc(31 downto 2),
rin.w.result, cpu_index, rin.w.wreg, r.x.ctrl.annul, holdn,
r.x.ctrl.pv, r.x.ctrl.trap, disasen);
end generate;
end;
| gpl-3.0 | 2c72912157669decbfb75613b33d21ce | 0.513269 | 3.060847 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-altera-ep3c25/config.vhd | 1 | 5,954 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := cyclone3;
constant CFG_MEMTECH : integer := cyclone3;
constant CFG_PADTECH : integer := cyclone3;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := cyclone3;
constant CFG_CLKMUL : integer := (10);
constant CFG_CLKDIV : integer := (10);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- SSRAM controller
constant CFG_SSCTRL : integer := 0;
constant CFG_SSCTRLP16 : integer := 0;
-- DDR controller
constant CFG_DDRSP : integer := 1;
constant CFG_DDRSP_INIT : integer := 1;
constant CFG_DDRSP_FREQ : integer := (100);
constant CFG_DDRSP_COL : integer := (9);
constant CFG_DDRSP_SIZE : integer := (32);
constant CFG_DDRSP_RSKEW : integer := (2500);
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#6#;
constant CFG_GRGPIO_WIDTH : integer := (3);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-3.0 | a64084bfb1d869ad556d1fc44114bf3f | 0.643937 | 3.637141 | false | false | false | false |
ARC-Lab-UF/UAA | src/dsa_pkg.vhd | 1 | 1,315 | -- Copyright (c) 2015 University of Florida
--
-- This file is part of uaa.
--
-- uaa is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- uaa is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with uaa. If not, see <http://www.gnu.org/licenses/>.
-- Greg Stitt
-- University of Florida
-- Description:
-- The dsa_pkg entity provides the constants for the select signals of the DSA's
-- muxes for adder inputs.
library ieee;
use ieee.std_logic_1164.all;
package dsa_pkg is
-- select values for DSA muxes
constant SEL_IBUF_L : std_logic := '0';
constant SEL_OBUF : std_logic := '1';
constant SEL_IBUF_R : std_logic_vector(1 downto 0) := "00";
constant SEL_ADD_OUT : std_logic_vector(1 downto 0) := "01";
constant SEL_ZERO : std_logic_vector(1 downto 0) := "10";
end dsa_pkg;
package body dsa_pkg is
end package body;
| gpl-3.0 | 950636176c5b6a6b650247ebdb2d7509 | 0.697338 | 3.49734 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-altera-ep2sgx90-av/testbench.vhd | 1 | 13,557 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Aeroflex Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library cypress;
use cypress.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 10; -- system clock period
romwidth : integer := 8; -- rom data width (8/32)
romdepth : integer := 21; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 20; -- ram address depth
srambanks : integer := 4 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal clkout, pllref : std_ulogic;
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal dsuen, dsutx, dsurx, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal error : std_logic;
signal gpio : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal debugout : std_logic_vector(31 downto 0);
-- External Adress/data bus, flash+ssram
signal fs_addr : std_logic_vector(24 downto 0);
signal fs_data : std_logic_vector(31 downto 0);
signal io_cen : std_logic;
signal flash_cen : std_ulogic;
signal flash_oen : std_ulogic;
signal flash_wen : std_ulogic;
signal ssram_cen : std_logic;
signal ssram_wen : std_logic;
signal ssram_bw : std_logic_vector (0 to 3);
signal ssram_oen : std_ulogic;
signal ssram_clk : std_ulogic;
signal ssram_adscn : std_ulogic;
signal ssram_adspn : std_ulogic;
signal ssram_advn : std_ulogic;
signal datazz : std_logic_vector(3 downto 0);
signal flash_addr : std_logic_vector(romdepth downto 0);
-- muxed data bus
signal prd : std_logic_vector(31 downto 0);
signal ssd : std_logic_vector(31 downto 0);
-- ddr memory
signal ddr_clk : std_logic_vector(2 downto 0);
signal ddr_clkb : std_logic_vector(2 downto 0);
signal ddr_cke : std_logic_vector(1 downto 0);
signal ddr_csb : std_logic_vector(1 downto 0);
signal ddr_odt : std_logic_vector(1 downto 0);
signal ddr_web : std_ulogic; -- ddr write enable
signal ddr_rasb : std_ulogic; -- ddr ras
signal ddr_casb : std_ulogic; -- ddr cas
signal ddr_dm : std_logic_vector (7 downto 0); -- ddr dm
signal ddr_dqs : std_logic_vector (7 downto 0); -- ddr dqs
signal ddr_dqsn : std_logic_vector (7 downto 0); -- ddr dqs
signal ddr_rdqs : std_logic_vector (7 downto 0); -- ddr dqs
signal ddr_ad : std_logic_vector (13 downto 0); -- ddr address
signal ddr_ba : std_logic_vector (1 downto 0); -- ddr bank address
signal ddr_dq, ddr_dq2 : std_logic_vector (63 downto 0); -- ddr data
signal phy_gtx_clk : std_logic;
signal phy_mii_data : std_logic; -- ethernet PHY interface
signal phy_tx_clk : std_ulogic;
signal phy_rx_clk : std_ulogic;
signal phy_rx_data : std_logic_vector(7 downto 0);
signal phy_dv : std_ulogic;
signal phy_rx_er : std_ulogic;
signal phy_col : std_ulogic;
signal phy_crs : std_ulogic;
signal phy_tx_data : std_logic_vector(7 downto 0);
signal phy_tx_en : std_ulogic;
signal phy_tx_er : std_ulogic;
signal phy_mii_clk : std_ulogic;
signal ft245_data : std_logic_vector (7 downto 0);
signal ft245_rdn : std_logic;
signal ft245_wr : std_logic;
signal ft245_rxfn : std_logic;
signal ft245_txen : std_logic;
signal ft245_pwrenn : std_logic;
signal plllock : std_ulogic;
signal txd1, rxd1 : std_ulogic;
--signal txd2, rxd2 : std_ulogic;
constant lresp : boolean := false;
signal sa : std_logic_vector(14 downto 0);
signal sd : std_logic_vector(31 downto 0);
component sram32 is
generic (
index : integer := 0; -- Byte lane (0 - 3)
abits: Positive := 10; -- Default 10 address bits (1Kx32)
echk : integer := 0; -- Generate EDAC checksum
tacc : integer := 10; -- access time (ns)
fname : string := "ram.dat"); -- File to read from
port (
a : in std_logic_vector(abits-1 downto 0);
d : inout std_logic_vector(31 downto 0);
lb : in std_logic;
ub : in std_logic;
ce : in std_logic;
we : in std_ulogic;
oe : in std_ulogic);
end component;
begin
-- clock and reset
-- 100 MHz
clk <= not clk after 5 ns;
-- ddr_clkin <= not clk after ct * 1 ns;
rst <= dsurst;
rxd1 <= '1';
-- ddr_dqs <= (others => 'L');
d3 : entity work.leon3mp generic map (fabtech, memtech, padtech,
ncpu, disas, dbguart, pclow )
port map (
resetn => rst,
clk => clk,
errorn => error,
fs_addr => fs_addr,
fs_data => fs_data,
io_cen => io_cen,
flash_cen => flash_cen,
flash_oen => flash_oen,
flash_wen => flash_wen,
ssram_cen => ssram_cen,
ssram_wen => ssram_wen,
ssram_bw => ssram_bw,
ssram_oen => ssram_oen,
ssram_clk => ssram_clk,
ssram_adscn => ssram_adscn,
ssram_adspn => ssram_adspn,
ssram_advn => ssram_advn,
ddr_clk => ddr_clk,
ddr_clkb => ddr_clkb,
ddr_cke => ddr_cke,
ddr_csb => ddr_csb,
ddr_odt => ddr_odt,
ddr_web => ddr_web, -- ddr write enable
ddr_rasb => ddr_rasb, -- ddr ras
ddr_casb => ddr_casb, -- ddr cas
ddr_dm => ddr_dm, -- ddr dm
ddr_dqs => ddr_dqs, -- ddr dqs
ddr_ad => ddr_ad, -- ddr address
ddr_ba => ddr_ba, -- ddr bank address
ddr_dq => ddr_dq, -- ddr data
phy_gtx_clk => phy_gtx_clk,
phy_mii_data => phy_mii_data,
phy_tx_clk => phy_tx_clk,
phy_rx_clk => phy_rx_clk,
phy_rx_data => phy_rx_data,
phy_dv => phy_dv,
phy_rx_er => phy_rx_er,
phy_col => phy_col,
phy_crs => phy_crs,
phy_tx_data => phy_tx_data,
phy_tx_en => phy_tx_en,
phy_tx_er => phy_tx_er,
phy_mii_clk => phy_mii_clk,
dsuact => dsuact,
rxd1 => rxd1,
txd1 => txd1,
gpio => gpio,
ft245_data => ft245_data,
ft245_rdn => ft245_rdn,
ft245_wr => ft245_wr,
ft245_rxfn => ft245_rxfn,
ft245_txen => ft245_txen,
ft245_pwrenn => ft245_pwrenn
);
datazz <= "HHHH";
ssram0 : cy7c1380d generic map (fname => sramfile)
port map(
ioDq(35 downto 32) => datazz, ioDq(31 downto 0) => fs_data,
iAddr => fs_addr(19 downto 1), iMode => gnd,
inGW => vcc, inBWE => ssram_wen, inADV => ssram_advn,
inADSP => ssram_adspn, inADSC => ssram_adscn,
iClk => ssram_clk,
inBwa => ssram_bw(3), inBwb => ssram_bw(2),
inBwc => ssram_bw(1), inBwd => ssram_bw(0),
inOE => ssram_oen, inCE1 => ssram_cen,
iCE2 => vcc, inCE3 => gnd, iZz => gnd);
-- 16 bit prom
flash_addr <= '0'&fs_addr(romdepth-1 downto 0);
prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile)
port map (a => flash_addr(romdepth-1 downto 0), d => fs_data(31 downto 16), lb => '0', ub => '0',
ce => flash_cen, we => flash_wen, oe => flash_oen);
-- prd(23 downto 0) <= (others => '0');
-- data mux
-- fs_data <= ssd when ssram_oen='0' and ssram_cen='0' else
-- prd when flash_oen='0' and flash_cen='0' else
-- (others => 'Z');
-- data <= buskeep(data), (others => 'H') after 250 ns;
test0 : grtestmod
port map ( rst, clk, error, fs_addr(20 downto 1), fs_data,
io_cen, flash_oen, flash_wen, open);
error <= 'H'; -- ERROR pull-up
ddr2delay : delay_wire
generic map(data_width => ddr_dq'length, delay_atob => 0.0, delay_btoa => 2.5)
port map(a => ddr_dq, b => ddr_dq2);
--DDR2
ddr2mem0: ddr2ram
generic map (
width => 64, abits => 14, babits => 2,
colbits => 10, implbanks => 1, fname => sdramfile
)
port map (
ck => ddr_clk(0), ckn => ddr_clkb(0), cke => ddr_cke(0), csn => ddr_csb(0), odt => ddr_odt(0),
rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web, dm => ddr_dm, ba => ddr_ba, a => ddr_ad,
dq => ddr_dq, dqs => ddr_dqs, dqsn => ddr_dqsn
);
-- ddr_dq <= buskeep(ddr_dq), (others => 'H') after 250 ns;
ddr_dqsn <= (others => 'U');
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
sd <= buskeep(sd), (others => 'H') after 250 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
| gpl-3.0 | 76deb9d1e1ca8117c289515ae4921c0a | 0.568562 | 3.073453 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/srmmu/mmuiface.vhd | 1 | 8,053 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mmuiface
-- File: mmuiface.vhd
-- Author: Konrad Eisele, Jiri Gaisler - Gaisler Research
-- Description: MMU interface types
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.mmuconfig.all;
library techmap;
use techmap.gencomp.all;
package mmuiface is
type mmutlbcam_in_type is record
mmctrl : mmctrl_type1;
tagin : tlbcam_tfp;
tagwrite : tlbcam_reg;
trans_op : std_logic;
flush_op : std_logic;
write_op : std_logic;
wb_op : std_logic;
mmuen : std_logic;
mset : std_logic;
end record;
type mmutlbcami_a is array (natural range <>) of mmutlbcam_in_type;
type mmutlbcam_out_type is record
pteout : std_logic_vector(31 downto 0);
LVL : std_logic_vector(1 downto 0); -- level in pth
hit : std_logic;
ctx : std_logic_vector(M_CTX_SZ-1 downto 0); -- for diagnostic access
valid : std_logic; -- for diagnostic access
vaddr : std_logic_vector(31 downto 0); -- for diagnostic access
NEEDSYNC : std_logic;
WBNEEDSYNC : std_logic;
end record;
type mmutlbcamo_a is array (natural range <>) of mmutlbcam_out_type;
-- mmu i/o
type mmuidc_data_in_type is record
data : std_logic_vector(31 downto 0);
su : std_logic;
read : std_logic;
isid : mmu_idcache;
wb_data : std_logic_vector(31 downto 0);
end record;
type mmuidc_data_out_type is record
finish : std_logic;
data : std_logic_vector(31 downto 0);
cache : std_logic;
accexc : std_logic;
end record;
constant mmuidco_zero : mmuidc_data_out_type := ('0', zero32, '0', '0');
type mmudc_in_type is record
trans_op : std_logic;
transdata : mmuidc_data_in_type;
-- dcache extra signals
flush_op : std_logic;
diag_op : std_logic;
wb_op : std_logic;
fsread : std_logic;
mmctrl1 : mmctrl_type1;
end record;
type mmudc_out_type is record
grant : std_logic;
transdata : mmuidc_data_out_type;
-- dcache extra signals
mmctrl2 : mmctrl_type2;
-- writebuffer out
wbtransdata : mmuidc_data_out_type;
tlbmiss : std_logic;
end record;
type mmuic_in_type is record
trans_op : std_logic;
transdata : mmuidc_data_in_type;
end record;
type mmuic_out_type is record
grant : std_logic;
transdata : mmuidc_data_out_type;
tlbmiss : std_logic;
end record;
constant mmudco_zero : mmudc_out_type := ('0', mmuidco_zero,
mmctrl2_zero, mmuidco_zero, '0');
constant mmuico_zero : mmuic_out_type := ('0', mmuidco_zero, '0');
--#lrue i/o
type mmulrue_in_type is record
touch : std_logic;
pos : std_logic_vector(M_ENT_MAX_LOG-1 downto 0);
clear : std_logic;
flush : std_logic;
left : std_logic_vector(M_ENT_MAX_LOG-1 downto 0);
fromleft : std_logic;
right : std_logic_vector(M_ENT_MAX_LOG-1 downto 0);
fromright : std_logic;
end record;
type mmulruei_a is array (natural range <>) of mmulrue_in_type;
type mmulrue_out_type is record
pos : std_logic_vector(M_ENT_MAX_LOG-1 downto 0);
movetop : std_logic;
end record;
constant mmulrue_out_none : mmulrue_out_type := (zero32(M_ENT_MAX_LOG-1 downto 0), '0');
type mmulrueo_a is array (natural range <>) of mmulrue_out_type;
--#lru i/o
type mmulru_in_type is record
touch : std_logic;
touchmin : std_logic;
flush : std_logic;
pos : std_logic_vector(M_ENT_MAX_LOG-1 downto 0);
mmctrl1 : mmctrl_type1;
end record;
type mmulru_out_type is record
pos : std_logic_vector(M_ENT_MAX_LOG-1 downto 0);
end record;
--#mmu: tw i/o
type memory_mm_in_type is record
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
burst : std_logic;
read : std_logic;
req : std_logic;
lock : std_logic;
end record;
constant mci_zero : memory_mm_in_type := (X"00000000", X"00000000",
"00", '0', '0', '0', '0');
type memory_mm_out_type is record
data : std_logic_vector(31 downto 0); -- memory data
ready : std_logic; -- cycle ready
grant : std_logic; --
retry : std_logic; --
mexc : std_logic; -- memory exception
werr : std_logic; -- memory write error
cache : std_logic; -- cacheable data
end record;
type mmutw_in_type is record
walk_op_ur : std_logic;
areq_ur : std_logic;
tlbmiss : std_logic;
data : std_logic_vector(31 downto 0);
adata : std_logic_vector(31 downto 0);
aaddr : std_logic_vector(31 downto 0);
end record;
type mmutwi_a is array (natural range <>) of mmutw_in_type;
type mmutw_out_type is record
finish : std_logic;
data : std_logic_vector(31 downto 0);
addr : std_logic_vector(31 downto 0);
lvl : std_logic_vector(1 downto 0);
fault_mexc : std_logic;
fault_trans : std_logic;
fault_inv : std_logic;
fault_lvl : std_logic_vector(1 downto 0);
end record;
type mmutwo_a is array (natural range <>) of mmutw_out_type;
-- mmu tlb i/o
type mmutlb_in_type is record
flush_op : std_logic;
wb_op : std_logic;
trans_op : std_logic;
transdata : mmuidc_data_in_type;
s2valid : std_logic;
mmctrl1 : mmctrl_type1;
end record;
type mmutlbi_a is array (natural range <>) of mmutlb_in_type;
type mmutlbfault_out_type is record
fault_pro : std_logic;
fault_pri : std_logic;
fault_access : std_logic;
fault_mexc : std_logic;
fault_trans : std_logic;
fault_inv : std_logic;
fault_lvl : std_logic_vector(1 downto 0);
fault_su : std_logic;
fault_read : std_logic;
fault_isid : mmu_idcache;
fault_addr : std_logic_vector(31 downto 0);
end record;
constant mmutlbfault_out_zero : mmutlbfault_out_type := (
fault_pro => '0',
fault_pri => '0',
fault_access => '0',
fault_mexc => '0',
fault_trans => '0',
fault_inv => '0',
fault_lvl => (others => '0'),
fault_su => '0',
fault_read => '0',
fault_isid => id_icache,
fault_addr => (others => '0'));
type mmutlb_out_type is record
transdata : mmuidc_data_out_type;
fault : mmutlbfault_out_type;
nexttrans : std_logic;
s1finished : std_logic;
-- writebuffer out
wbtransdata : mmuidc_data_out_type;
end record;
type mmutlbo_a is array (natural range <>) of mmutlb_out_type;
end;
| gpl-3.0 | 5bb31892124751c683836dc29283599e | 0.586986 | 3.407956 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/stratixii/stratixii_ddr_phy.vhd | 1 | 39,142 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: stratixii_ddr_phy
-- File: stratixii_ddr_phy.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: DDR PHY for Altera FPGAs
------------------------------------------------------------------------------
LIBRARY stratixii;
USE stratixii.all;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY altdqs_stxii IS
generic (width : integer := 2; MHz : integer := 100);
PORT
(
dqinclk : OUT STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_h : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_l : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_padio : INOUT STD_LOGIC_VECTOR (width-1 downto 0);
inclk : IN STD_LOGIC := '0';
oe : IN STD_LOGIC_VECTOR (width-1 downto 0) := (OTHERS => '1');
outclk : IN STD_LOGIC_VECTOR (width-1 downto 0)
);
END altdqs_stxii;
ARCHITECTURE RTL OF altdqs_stxii IS
COMPONENT stratixii_dll
GENERIC
(
DELAY_BUFFER_MODE : STRING := "none";
DELAY_CHAIN_LENGTH : NATURAL := 12;
DELAYCTRLOUT_MODE : STRING := "normal";
INPUT_FREQUENCY : STRING;
JITTER_REDUCTION : STRING := "false";
OFFSETCTRLOUT_MODE : STRING := "static";
SIM_LOOP_DELAY_INCREMENT : NATURAL := 0;
SIM_LOOP_INTRINSIC_DELAY : NATURAL := 0;
SIM_VALID_LOCK : NATURAL := 5;
SIM_VALID_LOCKCOUNT : NATURAL := 0;
STATIC_DELAY_CTRL : NATURAL := 0;
STATIC_OFFSET : STRING;
USE_UPNDNIN : STRING := "false";
USE_UPNDNINCLKENA : STRING := "false";
lpm_type : STRING := "stratixii_dll"
);
PORT
(
addnsub : IN STD_LOGIC := '1';
aload : IN STD_LOGIC := '0';
clk : IN STD_LOGIC;
delayctrlout : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
dqsupdate : OUT STD_LOGIC;
offset : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
offsetctrlout : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
upndnin : IN STD_LOGIC := '0';
upndninclkena : IN STD_LOGIC := '1';
upndnout : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT stratixii_io
GENERIC
(
BUS_HOLD : STRING := "false";
DDIO_MODE : STRING := "none";
DDIOINCLK_INPUT : STRING := "negated_inclk";
DQS_CTRL_LATCHES_ENABLE : STRING := "false";
DQS_DELAY_BUFFER_MODE : STRING := "none";
DQS_EDGE_DETECT_ENABLE : STRING := "false";
DQS_INPUT_FREQUENCY : STRING := "unused";
DQS_OFFSETCTRL_ENABLE : STRING := "false";
DQS_OUT_MODE : STRING := "none";
DQS_PHASE_SHIFT : NATURAL := 0;
EXTEND_OE_DISABLE : STRING := "false";
GATED_DQS : STRING := "false";
INCLK_INPUT : STRING := "normal";
INPUT_ASYNC_RESET : STRING := "none";
INPUT_POWER_UP : STRING := "low";
INPUT_REGISTER_MODE : STRING := "none";
INPUT_SYNC_RESET : STRING := "none";
OE_ASYNC_RESET : STRING := "none";
OE_POWER_UP : STRING := "low";
OE_REGISTER_MODE : STRING := "none";
OE_SYNC_RESET : STRING := "none";
OPEN_DRAIN_OUTPUT : STRING := "false";
OPERATION_MODE : STRING;
OUTPUT_ASYNC_RESET : STRING := "none";
OUTPUT_POWER_UP : STRING := "low";
OUTPUT_REGISTER_MODE : STRING := "none";
OUTPUT_SYNC_RESET : STRING := "none";
SIM_DQS_DELAY_INCREMENT : NATURAL := 0;
SIM_DQS_INTRINSIC_DELAY : NATURAL := 0;
SIM_DQS_OFFSET_INCREMENT : NATURAL := 0;
TIE_OFF_OE_CLOCK_ENABLE : STRING := "false";
TIE_OFF_OUTPUT_CLOCK_ENABLE : STRING := "false";
lpm_type : STRING := "stratixii_io"
);
PORT
(
areset : IN STD_LOGIC := '0';
combout : OUT STD_LOGIC;
datain : IN STD_LOGIC := '0';
ddiodatain : IN STD_LOGIC := '0';
ddioinclk : IN STD_LOGIC := '0';
ddioregout : OUT STD_LOGIC;
delayctrlin : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
dqsbusout : OUT STD_LOGIC;
dqsupdateen : IN STD_LOGIC := '1';
inclk : IN STD_LOGIC := '0';
inclkena : IN STD_LOGIC := '1';
linkin : IN STD_LOGIC := '0';
linkout : OUT STD_LOGIC;
oe : IN STD_LOGIC := '1';
offsetctrlin : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
outclk : IN STD_LOGIC := '0';
outclkena : IN STD_LOGIC := '1';
padio : INOUT STD_LOGIC;
regout : OUT STD_LOGIC;
sreset : IN STD_LOGIC := '0';
terminationcontrol : IN STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
SIGNAL dqs_busout : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL dqsbusout : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL delay_ctrl : STD_LOGIC_VECTOR (5 DOWNTO 0);
TYPE periodtype IS ARRAY(10 TO 20) of STRING(1 TO 6);
CONSTANT period : periodtype := (
"9999ps", "9090ps", "8333ps", "7692ps", -- 100-130 MHz
"7143ps", "6667ps", "6250ps", "5882ps", -- 140-170 MHz
"5556ps", "5263ps", "5000ps"); -- 180-200 MHz
FUNCTION buffer_mode(MHz : INTEGER) RETURN STRING IS
BEGIN
IF MHz > 175 THEN RETURN "high"; ELSE RETURN "low"; END IF;
END buffer_mode;
FUNCTION out_mode(MHz : INTEGER) RETURN STRING IS
BEGIN
IF MHz > 175 THEN RETURN "delay_chain4";
ELSE RETURN "delay_chain3"; END IF;
END out_mode;
FUNCTION chain_length(MHz : INTEGER) RETURN INTEGER IS
BEGIN
IF MHz > 175 THEN RETURN 16; ELSE RETURN 12; END IF;
END chain_length;
component global
port (
a_in : in std_logic;
a_out : out std_logic);
end component;
component stratixii_clkctrl
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "stratixii_clkctrl"
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
outclk : out std_logic
);
end component;
subtype v4 is std_logic_vector(3 downto 0);
type vv4 is array (width-1 downto 0) of v4;
signal dqslocal : vv4;
signal gnd : std_logic;
BEGIN
gnd <= '0';
dqinclk <= not dqs_busout;
stxii_dll1 : stratixii_dll
GENERIC MAP (
DELAY_BUFFER_MODE => buffer_mode(MHz),
DELAY_CHAIN_LENGTH => chain_length(MHz),
INPUT_FREQUENCY => period(MHz/10),
OFFSETCTRLOUT_MODE => "static",
DELAYCTRLOUT_MODE => "normal",
JITTER_REDUCTION => "false",
SIM_LOOP_DELAY_INCREMENT => 132,
SIM_LOOP_INTRINSIC_DELAY => 3840,
SIM_VALID_LOCK => 1,
SIM_VALID_LOCKCOUNT => 46,
STATIC_OFFSET => "0",
USE_UPNDNIN => "false",
USE_UPNDNINCLKENA => "false"
)
PORT MAP (
clk => inclk,
delayctrlout => delay_ctrl
);
loop0 : FOR i IN 0 TO width-1 GENERATE
stxii_io2a : stratixii_io
GENERIC MAP (
DDIO_MODE => "output",
DQS_CTRL_LATCHES_ENABLE => "false",
DQS_DELAY_BUFFER_MODE => buffer_mode(MHz),
DQS_EDGE_DETECT_ENABLE => "false",
DQS_INPUT_FREQUENCY => period(MHz/10),
DQS_OFFSETCTRL_ENABLE => "false",
DQS_OUT_MODE => out_mode(MHz),
DQS_PHASE_SHIFT => 9000,
EXTEND_OE_DISABLE => "true",
GATED_DQS => "false",
OE_ASYNC_RESET => "none",
OE_POWER_UP => "low",
OE_REGISTER_MODE => "register",
OE_SYNC_RESET => "none",
OPEN_DRAIN_OUTPUT => "false",
OPERATION_MODE => "bidir",
OUTPUT_ASYNC_RESET => "none",
OUTPUT_POWER_UP => "low",
OUTPUT_REGISTER_MODE => "register",
OUTPUT_SYNC_RESET => "none",
SIM_DQS_DELAY_INCREMENT => 36,
SIM_DQS_INTRINSIC_DELAY => 900,
SIM_DQS_OFFSET_INCREMENT => 0,
TIE_OFF_OE_CLOCK_ENABLE => "false",
TIE_OFF_OUTPUT_CLOCK_ENABLE => "false"
)
PORT MAP (
datain => dqs_datain_h(i),
ddiodatain => dqs_datain_l(i),
delayctrlin => delay_ctrl,
dqsbusout => dqs_busout(i),
oe => oe(i),
outclk => outclk(i),
padio => dqs_padio(i)
);
-- clkbuf : global
-- port map (a_in => dqsbusout(i), a_out => dqs_busout(i));
-- dqslocal(i) <= "000" & dqsbusout(i);
-- clkbuf : stratixii_clkctrl generic map (clock_type => "global clock")
-- port map (inclk => dqslocal(i), outclk => dqs_busout(i));
END GENERATE loop0;
END RTL; --altdqs_stxii
LIBRARY stratixii;
USE stratixii.all;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY altdq_stxii IS
generic (width : integer := 8);
PORT
(
datain_h : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
datain_l : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
dataout_h : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0);
dataout_l : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0);
inclock : IN STD_LOGIC;
oe : IN STD_LOGIC := '1';
outclock : IN STD_LOGIC;
padio : INOUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END altdq_stxii;
ARCHITECTURE RTL OF altdq_stxii IS
COMPONENT stratixii_io
GENERIC
(
BUS_HOLD : STRING := "false";
DDIO_MODE : STRING := "none";
DDIOINCLK_INPUT : STRING := "negated_inclk";
DQS_CTRL_LATCHES_ENABLE : STRING := "false";
DQS_DELAY_BUFFER_MODE : STRING := "none";
DQS_EDGE_DETECT_ENABLE : STRING := "false";
DQS_INPUT_FREQUENCY : STRING := "unused";
DQS_OFFSETCTRL_ENABLE : STRING := "false";
DQS_OUT_MODE : STRING := "none";
DQS_PHASE_SHIFT : NATURAL := 0;
EXTEND_OE_DISABLE : STRING := "false";
GATED_DQS : STRING := "false";
INCLK_INPUT : STRING := "normal";
INPUT_ASYNC_RESET : STRING := "none";
INPUT_POWER_UP : STRING := "low";
INPUT_REGISTER_MODE : STRING := "none";
INPUT_SYNC_RESET : STRING := "none";
OE_ASYNC_RESET : STRING := "none";
OE_POWER_UP : STRING := "low";
OE_REGISTER_MODE : STRING := "none";
OE_SYNC_RESET : STRING := "none";
OPEN_DRAIN_OUTPUT : STRING := "false";
OPERATION_MODE : STRING;
OUTPUT_ASYNC_RESET : STRING := "none";
OUTPUT_POWER_UP : STRING := "low";
OUTPUT_REGISTER_MODE : STRING := "none";
OUTPUT_SYNC_RESET : STRING := "none";
SIM_DQS_DELAY_INCREMENT : NATURAL := 0;
SIM_DQS_INTRINSIC_DELAY : NATURAL := 0;
SIM_DQS_OFFSET_INCREMENT : NATURAL := 0;
TIE_OFF_OE_CLOCK_ENABLE : STRING := "false";
TIE_OFF_OUTPUT_CLOCK_ENABLE : STRING := "false";
lpm_type : STRING := "stratixii_io"
);
PORT
(
areset : IN STD_LOGIC := '0';
combout : OUT STD_LOGIC;
datain : IN STD_LOGIC := '0';
ddiodatain : IN STD_LOGIC := '0';
ddioinclk : IN STD_LOGIC := '0';
ddioregout : OUT STD_LOGIC;
delayctrlin : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
dqsbusout : OUT STD_LOGIC;
dqsupdateen : IN STD_LOGIC := '1';
inclk : IN STD_LOGIC := '0';
inclkena : IN STD_LOGIC := '1';
linkin : IN STD_LOGIC := '0';
linkout : OUT STD_LOGIC;
oe : IN STD_LOGIC := '1';
offsetctrlin : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
outclk : IN STD_LOGIC := '0';
outclkena : IN STD_LOGIC := '1';
padio : INOUT STD_LOGIC;
regout : OUT STD_LOGIC;
sreset : IN STD_LOGIC := '0';
terminationcontrol : IN STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
BEGIN
loop0 : FOR i IN 0 TO width-1 GENERATE
dq_ioa : stratixii_io
GENERIC MAP (
DDIO_MODE => "bidir",
DDIOINCLK_INPUT => "negated_inclk",
EXTEND_OE_DISABLE => "false",
-- INCLK_INPUT => "dqs_bus",
INPUT_ASYNC_RESET => "none",
INPUT_POWER_UP => "low",
INPUT_REGISTER_MODE => "register",
OE_ASYNC_RESET => "none",
OE_POWER_UP => "low",
OE_REGISTER_MODE => "register",
OPERATION_MODE => "bidir",
OUTPUT_ASYNC_RESET => "none",
OUTPUT_POWER_UP => "low",
OUTPUT_REGISTER_MODE => "register"
)
PORT MAP (
datain => datain_h(i),
ddiodatain => datain_l(i),
ddioregout => dataout_l(i),
inclk => inclock,
oe => oe,
outclk => outclock,
padio => padio(i),
regout => dataout_h(i)
);
END GENERATE loop0;
END RTL; --altdq_stxii
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library altera;
library altera_mf;
--pragma translate_off
use altera_mf.altpll;
use altera_mf.altddio_out;
use altera_mf.altddio_bidir;
--pragma translate_on
------------------------------------------------------------------
-- STRATIX2 DDR PHY -----------------------------------------------
------------------------------------------------------------------
entity stratixii_ddr_phy is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end;
architecture rtl of stratixii_ddr_phy is
signal vcc, gnd, oe, lockl : std_logic;
signal ddr_clk_fb_outr : std_ulogic;
signal ddr_clk_fbl, fbclk : std_ulogic;
signal ddr_rasnr, ddr_casnr, ddr_wenr : std_ulogic;
signal ddr_clkl, ddr_clkbl : std_logic_vector(2 downto 0);
signal ddr_csnr, ddr_ckenr, ckel : std_logic_vector(1 downto 0);
signal clk_0r, clk_90r, clk_180r, clk_270r : std_ulogic;
signal clk0r, clk90r, clk180r, clk270r : std_ulogic;
signal locked, vlockl, ddrclkfbl : std_ulogic;
signal clk4, clk5 : std_logic;
signal ddr_dqin : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqout : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqoen : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_adr : std_logic_vector (13 downto 0); -- ddr address
signal ddr_bar : std_logic_vector (1 downto 0); -- ddr address
signal ddr_dmr : std_logic_vector (dbits/8-1 downto 0); -- ddr address
signal ddr_dqsin : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoen : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoutl : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsdel, dqsclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal da : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dqinl : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dllrst : std_logic_vector(0 to 3);
signal dll0rst : std_logic_vector(0 to 3);
signal mlock, mclkfb, mclk, mclkfx, mclk0 : std_ulogic;
signal gndv : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal pclkout : std_logic_vector (5 downto 1);
signal ddr_clkin : std_logic_vector(0 to 2);
signal dqinclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsoclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsnv : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
component stratixii_clkctrl
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "stratixii_clkctrl"
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
outclk : out std_logic
);
end component;
component altddio_out
generic (
width : positive; -- required parameter
power_up_high : string := "OFF";
oe_reg : string := "UNUSED";
extend_oe_disable : string := "UNUSED";
invert_output : string := "OFF";
intended_device_family : string := "MERCURY";
lpm_hint : string := "UNUSED";
lpm_type : string := "altddio_out" );
port (
datain_h : in std_logic_vector(width-1 downto 0);
datain_l : in std_logic_vector(width-1 downto 0);
outclock : in std_logic;
outclocken : in std_logic := '1';
aset : in std_logic := '0';
aclr : in std_logic := '0';
sset : in std_logic := '0';
sclr : in std_logic := '0';
oe : in std_logic := '1';
dataout : out std_logic_vector(width-1 downto 0));
end component;
component altddio_bidir
generic(
width : positive; -- required parameter
power_up_high : string := "OFF";
oe_reg : string := "UNUSED";
extend_oe_disable : string := "UNUSED";
implement_input_in_lcell : string := "UNUSED";
invert_output : string := "OFF";
intended_device_family : string := "MERCURY";
lpm_hint : string := "UNUSED";
lpm_type : string := "altddio_bidir" );
port (
datain_h : in std_logic_vector(width-1 downto 0);
datain_l : in std_logic_vector(width-1 downto 0);
inclock : in std_logic := '0';
inclocken : in std_logic := '1';
outclock : in std_logic;
outclocken : in std_logic := '1';
aset : in std_logic := '0';
aclr : in std_logic := '0';
sset : in std_logic := '0';
sclr : in std_logic := '0';
oe : in std_logic := '1';
dataout_h : out std_logic_vector(width-1 downto 0);
dataout_l : out std_logic_vector(width-1 downto 0);
padio : inout std_logic_vector(width-1 downto 0) );
end component;
component altdqs_stxii
generic (width : integer := 2; MHz : integer := 100);
PORT
(
dqs_datain_h : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_l : IN STD_LOGIC_VECTOR (width-1 downto 0);
inclk : IN STD_LOGIC ;
oe : IN STD_LOGIC_VECTOR (width-1 downto 0);
outclk : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqinclk : OUT STD_LOGIC_VECTOR (width-1 downto 0);
dqs_padio : INOUT STD_LOGIC_VECTOR (width-1 downto 0)
);
END component;
type phasevec is array (1 to 3) of string(1 to 4);
type phasevecarr is array (10 to 13) of phasevec;
constant phasearr : phasevecarr := (
("2500", "5000", "7500"), ("2273", "4545", "6818"), -- 100 & 110 MHz
("2083", "4167", "6250"), ("1923", "3846", "5769")); -- 120 & 130 MHz
component altpll
generic (
intended_device_family : string := "Stratix" ;
operation_mode : string := "NORMAL" ;
inclk0_input_frequency : positive;
inclk1_input_frequency : positive;
width_clock : positive := 6;
clk0_multiply_by : positive := 1;
clk0_divide_by : positive := 1;
clk1_multiply_by : positive := 1;
clk1_divide_by : positive := 1;
clk2_multiply_by : positive := 1;
clk2_divide_by : positive := 1;
clk3_multiply_by : positive := 1;
clk3_divide_by : positive := 1;
clk4_multiply_by : positive := 1;
clk4_divide_by : positive := 1;
clk3_phase_shift : string := "0";
clk2_phase_shift : string := "0";
clk1_phase_shift : string := "0";
clk0_phase_shift : string := "0"
);
port (
inclk : in std_logic_vector(1 downto 0);
clk : out std_logic_vector(width_clock-1 downto 0);
locked : out std_logic
);
end component;
begin
oe <= not oen; vcc <= '1'; gnd <= '0'; gndv <= (others => '0');
mclk <= clk;
-- clkout <= clk_270r;
-- clkout <= clk_0r when DDR_FREQ >= 110 else clk_270r;
clkout <= clk_90r when DDR_FREQ > 120 else clk_0r;
clk0r <= clk_270r; clk90r <= clk_0r;
clk180r <= clk_90r; clk270r <= clk_180r;
dll : altpll
generic map (
intended_device_family => "Stratix II",
operation_mode => "NORMAL",
inclk0_input_frequency => 1000000/MHz,
inclk1_input_frequency => 1000000/MHz,
clk4_multiply_by => clk_mul, clk4_divide_by => clk_div,
clk3_multiply_by => clk_mul, clk3_divide_by => clk_div,
clk2_multiply_by => clk_mul, clk2_divide_by => clk_div,
clk1_multiply_by => clk_mul, clk1_divide_by => clk_div,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk3_phase_shift => phasearr(DDR_FREQ/10)(3),
clk2_phase_shift => phasearr(DDR_FREQ/10)(2),
clk1_phase_shift => phasearr(DDR_FREQ/10)(1)
)
port map ( inclk(0) => mclk, inclk(1) => gnd, clk(0) => clk_0r,
clk(1) => clk_90r, clk(2) => clk_180r, clk(3) => clk_270r,
clk(4) => clk4, clk(5) => clk5, locked => lockl);
rstdel : process (mclk, rst)
begin
if rst = '0' then dllrst <= (others => '1');
elsif rising_edge(mclk) then
dllrst <= dllrst(1 to 3) & '0';
end if;
end process;
rdel : if rstdelay /= 0 generate
rcnt : process (clk_0r, lockl)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk_0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-- Generate external DDR clock
-- fbclkpad : altddio_out generic map (width => 1)
-- port map ( datain_h(0) => vcc, datain_l(0) => gnd,
-- outclock => clk90r, dataout(0) => ddr_clk_fb_out);
ddrclocks : for i in 0 to 2 generate
clkpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h(0) => vcc, datain_l(0) => gnd, oe => vcc,
outclock => clk90r, dataout(0) => ddr_clk(i));
clknpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h(0) => gnd, datain_l(0) => vcc, oe => vcc,
outclock => clk90r, dataout(0) => ddr_clkb(i));
end generate;
csnpads : altddio_out generic map (width => 2,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h => csn, datain_l => csn, oe => vcc,
outclock => clk0r, dataout => ddr_csb);
ckepads : altddio_out generic map (width => 2,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h => ckel, datain_l => ckel, oe => vcc,
outclock => clk0r, dataout => ddr_cke);
ddrbanks : for i in 0 to 1 generate
ckel(i) <= cke(i) and locked;
end generate;
rasnpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h(0) => rasn, datain_l(0) => rasn, oe => vcc,
outclock => clk0r, dataout(0) => ddr_rasb);
casnpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h(0) => casn, datain_l(0) => casn, oe => vcc,
outclock => clk0r, dataout(0) => ddr_casb);
wenpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h(0) => wen, datain_l(0) => wen, oe => vcc,
outclock => clk0r, dataout(0) => ddr_web);
dmpads : altddio_out generic map (width => dbits/8,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map (
datain_h => dm(dbits/8*2-1 downto dbits/8),
datain_l => dm(dbits/8-1 downto 0), oe => vcc,
outclock => clk0r, dataout => ddr_dm
);
bapads : altddio_out generic map (width => 2,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map (
datain_h => ba, datain_l => ba, oe => vcc,
outclock => clk0r, dataout => ddr_ba
);
addrpads : altddio_out generic map (width => 14,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map (
datain_h => addr, datain_l => addr, oe => vcc,
outclock => clk0r, dataout => ddr_ad
);
-- DQS generation
dqsoclk <= (others => clk90r);
altdqs : altdqs_stxii generic map (dbits/8, DDR_FREQ)
port map (dqs_datain_h => dqsnv, dqs_datain_l => gndv,
inclk => clk270r, oe => ddr_dqsoen, outclk => dqsoclk,
dqinclk => dqinclk, dqs_padio => ddr_dqs);
-- Data bus
dqgen : for i in 0 to dbits/8-1 generate
qi : altddio_bidir generic map (width => 8, oe_reg =>"REGISTERED",
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map (
datain_l => dqout(i*8+7 downto i*8),
datain_h => dqout(i*8+7+dbits downto dbits+i*8),
inclock => dqinclk(i), --clk270r,
outclock => clk0r, oe => oe,
dataout_h => dqin(i*8+7 downto i*8),
dataout_l => dqin(i*8+7+dbits downto dbits+i*8), --dqinl(i*8+7 downto i*8),
padio => ddr_dq(i*8+7 downto i*8));
end generate;
dqsreg : process(clk180r)
begin
if rising_edge(clk180r) then
dqsnv <= (others => oe);
end if;
end process;
oereg : process(clk0r)
begin
if rising_edge(clk0r) then
ddr_dqsoen(dbits/8-1 downto 0) <= (others => not dqsoen);
end if;
end process;
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library altera_mf;
--library stratixii;
use altera_mf.altera_mf_components.all;
--use stratixii.stratixii_pll;
------------------------------------------------------------------
-- STRATIX2 DDR2 PHY -----------------------------------------------
------------------------------------------------------------------
entity stratixii_ddr2_phy is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2;
clk_div : integer := 2; eightbanks : integer range 0 to 1 := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(1 downto 0);
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 2 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0);
cal_en : in std_logic_vector(dbits/8-1 downto 0);
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
cal_rst : in std_logic;
odt : in std_logic_vector(1 downto 0)
);
end;
architecture rtl of stratixii_ddr2_phy is
signal vcc, gnd : std_logic;
signal ckel, odtl : std_logic_vector(1 downto 0);
signal clk_0r, clk_90r, clk_120r, clk_180r, clk_270r : std_ulogic;
signal locked, lockl, vlockl : std_ulogic;
signal clk5 : std_ulogic;
signal dllrst : std_logic_vector(0 to 3);
signal gndv : std_logic_vector (dbits/8-1 downto 0);
signal dqsnv : std_logic_vector (dbits/8-1 downto 0);
signal dqsoe : std_logic_vector (dbits/8-1 downto 0);
signal dqsoclk : std_logic_vector (dbits/8-1 downto 0);
signal dqinclk : std_logic_vector (dbits/8-1 downto 0);
signal dqinl : std_logic_vector (dbits*2-1 downto 0);
signal dqoe : std_logic;
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
component altdqs_stxii
generic (width : integer := 2; Mhz : integer := 100);
PORT
(
dqs_datain_h : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_l : IN STD_LOGIC_VECTOR (width-1 downto 0);
inclk : IN STD_LOGIC ;
oe : IN STD_LOGIC_VECTOR (width-1 downto 0);
outclk : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqinclk : OUT STD_LOGIC_VECTOR (width-1 downto 0);
dqs_padio : INOUT STD_LOGIC_VECTOR (width-1 downto 0)
);
END component;
component altdq_stxii
generic (width : integer := 8);
PORT
(
datain_h : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
datain_l : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
dataout_h : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0);
dataout_l : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0);
inclock : IN STD_LOGIC;
oe : IN STD_LOGIC := '1';
outclock : IN STD_LOGIC;
padio : INOUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END component;
type phasevec is array (1 to 4) of string(1 to 4);
type phasevecarr is array (13 to 20) of phasevec;
constant phasearr : phasevecarr := (
("1923", "2564", "3846", "5769"), -- 130 MHz
("1786", "2381", "3571", "5357"), -- 140 MHz
("1667", "2222", "3333", "5000"), -- 150 MHz
("1562", "2083", "3125", "4687"), -- 160 MHz
("1471", "1961", "2941", "4412"), -- 160 MHz
("1389", "1852", "2778", "4167"), -- 180 MHz
("1316", "1754", "2632", "3947"), -- 190 MHz
("1250", "1667", "2500", "3750")); -- 200 MHz
component altpll
generic (
intended_device_family : string := "Stratix" ;
operation_mode : string := "NORMAL" ;
inclk0_input_frequency : positive;
inclk1_input_frequency : positive;
width_clock : positive := 6;
clk0_multiply_by : positive := 1;
clk0_divide_by : positive := 1;
clk1_multiply_by : positive := 1;
clk1_divide_by : positive := 1;
clk2_multiply_by : positive := 1;
clk2_divide_by : positive := 1;
clk3_multiply_by : positive := 1;
clk3_divide_by : positive := 1;
clk4_multiply_by : positive := 1;
clk4_divide_by : positive := 1;
clk4_phase_shift : string := "0";
clk3_phase_shift : string := "0";
clk2_phase_shift : string := "0";
clk1_phase_shift : string := "0";
clk0_phase_shift : string := "0"
);
port (
inclk : in std_logic_vector(1 downto 0);
clk : out std_logic_vector(width_clock-1 downto 0);
locked : out std_logic
);
end component;
component altddio_out
generic (
width : positive; -- required parameter
power_up_high : string := "OFF";
oe_reg : string := "UNUSED";
extend_oe_disable : string := "UNUSED";
invert_output : string := "OFF";
intended_device_family : string := "MERCURY";
lpm_hint : string := "UNUSED";
lpm_type : string := "altddio_out" );
port (
datain_h : in std_logic_vector(width-1 downto 0);
datain_l : in std_logic_vector(width-1 downto 0);
outclock : in std_logic;
outclocken : in std_logic := '1';
aset : in std_logic := '0';
aclr : in std_logic := '0';
sset : in std_logic := '0';
sclr : in std_logic := '0';
oe : in std_logic := '1';
dataout : out std_logic_vector(width-1 downto 0));
end component;
begin
clkout <= clk_0r;
vcc <= '1'; gnd <= '0'; gndv <= (others => '0');
dll : altpll
generic map (
intended_device_family => "Stratix II",
operation_mode => "NORMAL",
inclk0_input_frequency => 1000000/MHz,
inclk1_input_frequency => 1000000/MHz,
clk4_multiply_by => clk_mul, clk4_divide_by => clk_div,
clk3_multiply_by => clk_mul, clk3_divide_by => clk_div,
clk2_multiply_by => clk_mul, clk2_divide_by => clk_div,
clk1_multiply_by => clk_mul, clk1_divide_by => clk_div,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk4_phase_shift => phasearr(DDR_FREQ/10)(4),
clk3_phase_shift => phasearr(DDR_FREQ/10)(3),
clk2_phase_shift => phasearr(DDR_FREQ/10)(2),
clk1_phase_shift => phasearr(DDR_FREQ/10)(1)
)
port map ( inclk(0) => clk, inclk(1) => gnd, clk(0) => clk_0r,
clk(1) => clk_90r, clk(2) => clk_120r, clk(3) => clk_180r,
clk(4) => clk_270r, clk(5) => clk5, locked => lockl);
rstdel : process (clk, rst)
begin
if rst = '0' then dllrst <= (others => '1');
elsif rising_edge(clk) then
dllrst <= dllrst(1 to 3) & '0';
end if;
end process;
rdel : if rstdelay /= 0 generate
rcnt : process (clk_180r, lockl)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk_180r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
ddrbanks : for i in 0 to 1 generate
ckel(i) <= cke(i) and locked;
odtl(i) <= odt(i) and locked;
end generate;
dqsreg : process (clk_180r)
begin
if rising_edge(clk_180r) then
dqsoe <= (others => not dqsoen);
dqsnv <= (others => not oen);
end if;
end process;
dqinreg : process (clk_120r)
begin
if rising_edge(clk_120r) then
dqin <= dqinl;
end if;
end process;
ddrclocks : for i in 0 to 2 generate
clkpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h(0) => vcc, datain_l(0) => gnd, oe => vcc,
outclock => clk_0r, dataout(0) => ddr_clk(i));
clknpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h(0) => gnd, datain_l(0) => vcc, oe => vcc,
outclock => clk_0r, dataout(0) => ddr_clkb(i));
end generate;
-- Control signal pads
ckepads : altddio_out generic map (width => 2,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h => ckel, datain_l => ckel, oe => vcc,
outclock => clk_180r, dataout => ddr_cke);
csnpads : altddio_out generic map (width => 2,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h => csn, datain_l => csn, oe => vcc,
outclock => clk_180r, dataout => ddr_csb);
odtpads : altddio_out generic map (width => 2,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h => odtl, datain_l => odtl, oe => vcc,
outclock => clk_180r, dataout => ddr_odt);
rasnpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h(0) => rasn, datain_l(0) => rasn, oe => vcc,
outclock => clk_180r, dataout(0) => ddr_rasb);
casnpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h(0) => casn, datain_l(0) => casn, oe => vcc,
outclock => clk_180r, dataout(0) => ddr_casb);
wenpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h(0) => wen, datain_l(0) => wen, oe => vcc,
outclock => clk_180r, dataout(0) => ddr_web);
bapads : altddio_out generic map (width => 2+eightbanks,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map (
datain_h => ba(1+eightbanks downto 0),
datain_l => ba(1+eightbanks downto 0),
oe => vcc,
outclock => clk_180r, dataout => ddr_ba
);
addrpads : altddio_out generic map (width => 14,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map (
datain_h => addr, datain_l => addr, oe => vcc,
outclock => clk_180r, dataout => ddr_ad
);
-- DQS generation
dqsoclk <= (others => clk_0r);
altdqs : altdqs_stxii generic map (dbits/8, DDR_FREQ)
port map (dqs_datain_h => dqsnv, dqs_datain_l => gndv,
inclk => clk_0r, oe => dqsoe, outclk => dqsoclk,
dqinclk => dqinclk, dqs_padio => ddr_dqs);
-- Data bus
dqoe <= not oen;
dqgen : for i in 0 to dbits/8-1 generate
altdq : altdq_stxii generic map (width => 8)
port map (
datain_l => dqout(i*8+7 downto i*8),
datain_h => dqout(i*8+7+dbits downto dbits+i*8),
inclock => dqinclk(i),
outclock => clk_270r, oe => dqoe,
dataout_h => dqinl(i*8+7 downto i*8),
dataout_l => dqinl(i*8+7+dbits downto dbits+i*8),
padio => ddr_dq(i*8+7 downto i*8));
end generate;
-- Data mask
dmpads : altddio_out generic map (width => dbits/8,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map (
datain_h => dm(dbits/4-1 downto dbits/8),
datain_l => dm(dbits/8-1 downto 0), oe => vcc,
outclock => clk_270r, dataout => ddr_dm
);
end;
| gpl-3.0 | cd9196c9d551bbfb8ecee757a0d34b5d | 0.580604 | 3.128857 | false | false | false | false |
hoglet67/CoPro6502 | client/6809/100a/tuberom_6809.vhd | 1 | 86,726 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tuberom_6809 is
port (
CLK : in std_logic;
ADDR : in std_logic_vector(10 downto 0);
DATA : out std_logic_vector(7 downto 0)
);
end;
architecture RTL of tuberom_6809 is
signal rom_addr : std_logic_vector(11 downto 0);
begin
p_addr : process(ADDR)
begin
rom_addr <= (others => '0');
rom_addr(10 downto 0) <= ADDR;
end process;
p_rom : process
begin
wait until rising_edge(CLK);
DATA <= (others => '0');
case rom_addr is
when x"000" => DATA <= x"F8";
when x"001" => DATA <= x"2C";
when x"002" => DATA <= x"F8";
when x"003" => DATA <= x"71";
when x"004" => DATA <= x"FF";
when x"005" => DATA <= x"E0";
when x"006" => DATA <= x"F8";
when x"007" => DATA <= x"E0";
when x"008" => DATA <= x"F8";
when x"009" => DATA <= x"F4";
when x"00A" => DATA <= x"FF";
when x"00B" => DATA <= x"EE";
when x"00C" => DATA <= x"F8";
when x"00D" => DATA <= x"E9";
when x"00E" => DATA <= x"FF";
when x"00F" => DATA <= x"E7";
when x"010" => DATA <= x"F8";
when x"011" => DATA <= x"E6";
when x"012" => DATA <= x"F8";
when x"013" => DATA <= x"DF";
when x"014" => DATA <= x"20";
when x"015" => DATA <= x"5B";
when x"016" => DATA <= x"0D";
when x"017" => DATA <= x"36";
when x"018" => DATA <= x"38";
when x"019" => DATA <= x"30";
when x"01A" => DATA <= x"39";
when x"01B" => DATA <= x"20";
when x"01C" => DATA <= x"54";
when x"01D" => DATA <= x"55";
when x"01E" => DATA <= x"42";
when x"01F" => DATA <= x"45";
when x"020" => DATA <= x"20";
when x"021" => DATA <= x"36";
when x"022" => DATA <= x"34";
when x"023" => DATA <= x"4B";
when x"024" => DATA <= x"20";
when x"025" => DATA <= x"31";
when x"026" => DATA <= x"2E";
when x"027" => DATA <= x"30";
when x"028" => DATA <= x"30";
when x"029" => DATA <= x"20";
when x"02A" => DATA <= x"0D";
when x"02B" => DATA <= x"00";
when x"02C" => DATA <= x"1A";
when x"02D" => DATA <= x"50";
when x"02E" => DATA <= x"10";
when x"02F" => DATA <= x"CE";
when x"030" => DATA <= x"F8";
when x"031" => DATA <= x"00";
when x"032" => DATA <= x"1F";
when x"033" => DATA <= x"41";
when x"034" => DATA <= x"EC";
when x"035" => DATA <= x"84";
when x"036" => DATA <= x"ED";
when x"037" => DATA <= x"81";
when x"038" => DATA <= x"8C";
when x"039" => DATA <= x"FE";
when x"03A" => DATA <= x"C0";
when x"03B" => DATA <= x"26";
when x"03C" => DATA <= x"03";
when x"03D" => DATA <= x"8E";
when x"03E" => DATA <= x"FE";
when x"03F" => DATA <= x"F0";
when x"040" => DATA <= x"8C";
when x"041" => DATA <= x"FF";
when x"042" => DATA <= x"8C";
when x"043" => DATA <= x"26";
when x"044" => DATA <= x"03";
when x"045" => DATA <= x"8E";
when x"046" => DATA <= x"FF";
when x"047" => DATA <= x"94";
when x"048" => DATA <= x"8C";
when x"049" => DATA <= x"00";
when x"04A" => DATA <= x"00";
when x"04B" => DATA <= x"26";
when x"04C" => DATA <= x"E7";
when x"04D" => DATA <= x"B6";
when x"04E" => DATA <= x"FE";
when x"04F" => DATA <= x"E0";
when x"050" => DATA <= x"1A";
when x"051" => DATA <= x"50";
when x"052" => DATA <= x"10";
when x"053" => DATA <= x"CE";
when x"054" => DATA <= x"FF";
when x"055" => DATA <= x"28";
when x"056" => DATA <= x"8D";
when x"057" => DATA <= x"68";
when x"058" => DATA <= x"BE";
when x"059" => DATA <= x"FF";
when x"05A" => DATA <= x"90";
when x"05B" => DATA <= x"BF";
when x"05C" => DATA <= x"FF";
when x"05D" => DATA <= x"8E";
when x"05E" => DATA <= x"1C";
when x"05F" => DATA <= x"00";
when x"060" => DATA <= x"8E";
when x"061" => DATA <= x"F8";
when x"062" => DATA <= x"16";
when x"063" => DATA <= x"BD";
when x"064" => DATA <= x"F9";
when x"065" => DATA <= x"33";
when x"066" => DATA <= x"BD";
when x"067" => DATA <= x"FF";
when x"068" => DATA <= x"E7";
when x"069" => DATA <= x"4F";
when x"06A" => DATA <= x"BD";
when x"06B" => DATA <= x"FF";
when x"06C" => DATA <= x"EE";
when x"06D" => DATA <= x"4F";
when x"06E" => DATA <= x"BD";
when x"06F" => DATA <= x"FA";
when x"070" => DATA <= x"30";
when x"071" => DATA <= x"10";
when x"072" => DATA <= x"CE";
when x"073" => DATA <= x"FF";
when x"074" => DATA <= x"28";
when x"075" => DATA <= x"8D";
when x"076" => DATA <= x"49";
when x"077" => DATA <= x"10";
when x"078" => DATA <= x"FE";
when x"079" => DATA <= x"FF";
when x"07A" => DATA <= x"8A";
when x"07B" => DATA <= x"8E";
when x"07C" => DATA <= x"FF";
when x"07D" => DATA <= x"B9";
when x"07E" => DATA <= x"BF";
when x"07F" => DATA <= x"FF";
when x"080" => DATA <= x"90";
when x"081" => DATA <= x"1C";
when x"082" => DATA <= x"00";
when x"083" => DATA <= x"8E";
when x"084" => DATA <= x"F8";
when x"085" => DATA <= x"96";
when x"086" => DATA <= x"BD";
when x"087" => DATA <= x"F9";
when x"088" => DATA <= x"33";
when x"089" => DATA <= x"BD";
when x"08A" => DATA <= x"FF";
when x"08B" => DATA <= x"F1";
when x"08C" => DATA <= x"25";
when x"08D" => DATA <= x"14";
when x"08E" => DATA <= x"8E";
when x"08F" => DATA <= x"FF";
when x"090" => DATA <= x"28";
when x"091" => DATA <= x"BD";
when x"092" => DATA <= x"FF";
when x"093" => DATA <= x"F7";
when x"094" => DATA <= x"20";
when x"095" => DATA <= x"ED";
when x"096" => DATA <= x"36";
when x"097" => DATA <= x"38";
when x"098" => DATA <= x"30";
when x"099" => DATA <= x"39";
when x"09A" => DATA <= x"3E";
when x"09B" => DATA <= x"2A";
when x"09C" => DATA <= x"00";
when x"09D" => DATA <= x"FF";
when x"09E" => DATA <= x"28";
when x"09F" => DATA <= x"57";
when x"0A0" => DATA <= x"20";
when x"0A1" => DATA <= x"FF";
when x"0A2" => DATA <= x"86";
when x"0A3" => DATA <= x"7E";
when x"0A4" => DATA <= x"BD";
when x"0A5" => DATA <= x"FF";
when x"0A6" => DATA <= x"F4";
when x"0A7" => DATA <= x"3F";
when x"0A8" => DATA <= x"11";
when x"0A9" => DATA <= x"45";
when x"0AA" => DATA <= x"73";
when x"0AB" => DATA <= x"63";
when x"0AC" => DATA <= x"61";
when x"0AD" => DATA <= x"70";
when x"0AE" => DATA <= x"65";
when x"0AF" => DATA <= x"00";
when x"0B0" => DATA <= x"10";
when x"0B1" => DATA <= x"FE";
when x"0B2" => DATA <= x"FF";
when x"0B3" => DATA <= x"8A";
when x"0B4" => DATA <= x"BD";
when x"0B5" => DATA <= x"FF";
when x"0B6" => DATA <= x"E7";
when x"0B7" => DATA <= x"A6";
when x"0B8" => DATA <= x"80";
when x"0B9" => DATA <= x"8D";
when x"0BA" => DATA <= x"78";
when x"0BB" => DATA <= x"BD";
when x"0BC" => DATA <= x"FF";
when x"0BD" => DATA <= x"E7";
when x"0BE" => DATA <= x"20";
when x"0BF" => DATA <= x"C3";
when x"0C0" => DATA <= x"CC";
when x"0C1" => DATA <= x"00";
when x"0C2" => DATA <= x"00";
when x"0C3" => DATA <= x"FD";
when x"0C4" => DATA <= x"FF";
when x"0C5" => DATA <= x"88";
when x"0C6" => DATA <= x"CC";
when x"0C7" => DATA <= x"F8";
when x"0C8" => DATA <= x"00";
when x"0C9" => DATA <= x"FD";
when x"0CA" => DATA <= x"FF";
when x"0CB" => DATA <= x"8A";
when x"0CC" => DATA <= x"CC";
when x"0CD" => DATA <= x"F8";
when x"0CE" => DATA <= x"B0";
when x"0CF" => DATA <= x"FD";
when x"0D0" => DATA <= x"FF";
when x"0D1" => DATA <= x"FA";
when x"0D2" => DATA <= x"CC";
when x"0D3" => DATA <= x"FE";
when x"0D4" => DATA <= x"22";
when x"0D5" => DATA <= x"FD";
when x"0D6" => DATA <= x"FE";
when x"0D7" => DATA <= x"FA";
when x"0D8" => DATA <= x"8E";
when x"0D9" => DATA <= x"FF";
when x"0DA" => DATA <= x"FA";
when x"0DB" => DATA <= x"10";
when x"0DC" => DATA <= x"8E";
when x"0DD" => DATA <= x"FF";
when x"0DE" => DATA <= x"80";
when x"0DF" => DATA <= x"39";
when x"0E0" => DATA <= x"BD";
when x"0E1" => DATA <= x"FF";
when x"0E2" => DATA <= x"E0";
when x"0E3" => DATA <= x"7E";
when x"0E4" => DATA <= x"FF";
when x"0E5" => DATA <= x"EE";
when x"0E6" => DATA <= x"BD";
when x"0E7" => DATA <= x"FF";
when x"0E8" => DATA <= x"E7";
when x"0E9" => DATA <= x"A6";
when x"0EA" => DATA <= x"80";
when x"0EB" => DATA <= x"81";
when x"0EC" => DATA <= x"04";
when x"0ED" => DATA <= x"27";
when x"0EE" => DATA <= x"F0";
when x"0EF" => DATA <= x"BD";
when x"0F0" => DATA <= x"FF";
when x"0F1" => DATA <= x"EE";
when x"0F2" => DATA <= x"20";
when x"0F3" => DATA <= x"F5";
when x"0F4" => DATA <= x"34";
when x"0F5" => DATA <= x"32";
when x"0F6" => DATA <= x"86";
when x"0F7" => DATA <= x"80";
when x"0F8" => DATA <= x"8E";
when x"0F9" => DATA <= x"FF";
when x"0FA" => DATA <= x"FF";
when x"0FB" => DATA <= x"1F";
when x"0FC" => DATA <= x"12";
when x"0FD" => DATA <= x"BD";
when x"0FE" => DATA <= x"FF";
when x"0FF" => DATA <= x"F4";
when x"100" => DATA <= x"8C";
when x"101" => DATA <= x"00";
when x"102" => DATA <= x"00";
when x"103" => DATA <= x"35";
when x"104" => DATA <= x"B2";
when x"105" => DATA <= x"34";
when x"106" => DATA <= x"06";
when x"107" => DATA <= x"1F";
when x"108" => DATA <= x"10";
when x"109" => DATA <= x"8D";
when x"10A" => DATA <= x"06";
when x"10B" => DATA <= x"1F";
when x"10C" => DATA <= x"98";
when x"10D" => DATA <= x"8D";
when x"10E" => DATA <= x"02";
when x"10F" => DATA <= x"35";
when x"110" => DATA <= x"86";
when x"111" => DATA <= x"34";
when x"112" => DATA <= x"02";
when x"113" => DATA <= x"44";
when x"114" => DATA <= x"44";
when x"115" => DATA <= x"44";
when x"116" => DATA <= x"44";
when x"117" => DATA <= x"8D";
when x"118" => DATA <= x"06";
when x"119" => DATA <= x"A6";
when x"11A" => DATA <= x"E4";
when x"11B" => DATA <= x"8D";
when x"11C" => DATA <= x"02";
when x"11D" => DATA <= x"35";
when x"11E" => DATA <= x"82";
when x"11F" => DATA <= x"84";
when x"120" => DATA <= x"0F";
when x"121" => DATA <= x"81";
when x"122" => DATA <= x"0A";
when x"123" => DATA <= x"25";
when x"124" => DATA <= x"02";
when x"125" => DATA <= x"8B";
when x"126" => DATA <= x"07";
when x"127" => DATA <= x"8B";
when x"128" => DATA <= x"30";
when x"129" => DATA <= x"7E";
when x"12A" => DATA <= x"FF";
when x"12B" => DATA <= x"EE";
when x"12C" => DATA <= x"35";
when x"12D" => DATA <= x"10";
when x"12E" => DATA <= x"8D";
when x"12F" => DATA <= x"03";
when x"130" => DATA <= x"34";
when x"131" => DATA <= x"10";
when x"132" => DATA <= x"39";
when x"133" => DATA <= x"A6";
when x"134" => DATA <= x"80";
when x"135" => DATA <= x"27";
when x"136" => DATA <= x"FB";
when x"137" => DATA <= x"BD";
when x"138" => DATA <= x"FF";
when x"139" => DATA <= x"E3";
when x"13A" => DATA <= x"20";
when x"13B" => DATA <= x"F7";
when x"13C" => DATA <= x"10";
when x"13D" => DATA <= x"8E";
when x"13E" => DATA <= x"00";
when x"13F" => DATA <= x"00";
when x"140" => DATA <= x"A6";
when x"141" => DATA <= x"80";
when x"142" => DATA <= x"81";
when x"143" => DATA <= x"30";
when x"144" => DATA <= x"25";
when x"145" => DATA <= x"2B";
when x"146" => DATA <= x"81";
when x"147" => DATA <= x"3A";
when x"148" => DATA <= x"25";
when x"149" => DATA <= x"0A";
when x"14A" => DATA <= x"84";
when x"14B" => DATA <= x"DF";
when x"14C" => DATA <= x"80";
when x"14D" => DATA <= x"07";
when x"14E" => DATA <= x"25";
when x"14F" => DATA <= x"21";
when x"150" => DATA <= x"81";
when x"151" => DATA <= x"40";
when x"152" => DATA <= x"24";
when x"153" => DATA <= x"1D";
when x"154" => DATA <= x"84";
when x"155" => DATA <= x"0F";
when x"156" => DATA <= x"1E";
when x"157" => DATA <= x"02";
when x"158" => DATA <= x"58";
when x"159" => DATA <= x"49";
when x"15A" => DATA <= x"58";
when x"15B" => DATA <= x"49";
when x"15C" => DATA <= x"58";
when x"15D" => DATA <= x"49";
when x"15E" => DATA <= x"58";
when x"15F" => DATA <= x"49";
when x"160" => DATA <= x"1E";
when x"161" => DATA <= x"12";
when x"162" => DATA <= x"1E";
when x"163" => DATA <= x"01";
when x"164" => DATA <= x"1E";
when x"165" => DATA <= x"89";
when x"166" => DATA <= x"3A";
when x"167" => DATA <= x"1E";
when x"168" => DATA <= x"12";
when x"169" => DATA <= x"20";
when x"16A" => DATA <= x"D5";
when x"16B" => DATA <= x"A6";
when x"16C" => DATA <= x"80";
when x"16D" => DATA <= x"81";
when x"16E" => DATA <= x"20";
when x"16F" => DATA <= x"27";
when x"170" => DATA <= x"FA";
when x"171" => DATA <= x"30";
when x"172" => DATA <= x"1F";
when x"173" => DATA <= x"81";
when x"174" => DATA <= x"21";
when x"175" => DATA <= x"39";
when x"176" => DATA <= x"34";
when x"177" => DATA <= x"7C";
when x"178" => DATA <= x"11";
when x"179" => DATA <= x"8C";
when x"17A" => DATA <= x"F8";
when x"17B" => DATA <= x"00";
when x"17C" => DATA <= x"24";
when x"17D" => DATA <= x"08";
when x"17E" => DATA <= x"10";
when x"17F" => DATA <= x"FF";
when x"180" => DATA <= x"F9";
when x"181" => DATA <= x"8A";
when x"182" => DATA <= x"10";
when x"183" => DATA <= x"CE";
when x"184" => DATA <= x"FF";
when x"185" => DATA <= x"28";
when x"186" => DATA <= x"8D";
when x"187" => DATA <= x"0F";
when x"188" => DATA <= x"10";
when x"189" => DATA <= x"CE";
when x"18A" => DATA <= x"00";
when x"18B" => DATA <= x"00";
when x"18C" => DATA <= x"35";
when x"18D" => DATA <= x"FC";
when x"18E" => DATA <= x"48";
when x"18F" => DATA <= x"45";
when x"190" => DATA <= x"4C";
when x"191" => DATA <= x"50";
when x"192" => DATA <= x"80";
when x"193" => DATA <= x"47";
when x"194" => DATA <= x"4F";
when x"195" => DATA <= x"81";
when x"196" => DATA <= x"00";
when x"197" => DATA <= x"8D";
when x"198" => DATA <= x"D2";
when x"199" => DATA <= x"A6";
when x"19A" => DATA <= x"80";
when x"19B" => DATA <= x"81";
when x"19C" => DATA <= x"2A";
when x"19D" => DATA <= x"27";
when x"19E" => DATA <= x"F8";
when x"19F" => DATA <= x"30";
when x"1A0" => DATA <= x"1F";
when x"1A1" => DATA <= x"34";
when x"1A2" => DATA <= x"10";
when x"1A3" => DATA <= x"A6";
when x"1A4" => DATA <= x"80";
when x"1A5" => DATA <= x"81";
when x"1A6" => DATA <= x"21";
when x"1A7" => DATA <= x"24";
when x"1A8" => DATA <= x"FA";
when x"1A9" => DATA <= x"30";
when x"1AA" => DATA <= x"1F";
when x"1AB" => DATA <= x"8D";
when x"1AC" => DATA <= x"BE";
when x"1AD" => DATA <= x"BF";
when x"1AE" => DATA <= x"FF";
when x"1AF" => DATA <= x"86";
when x"1B0" => DATA <= x"10";
when x"1B1" => DATA <= x"8E";
when x"1B2" => DATA <= x"F9";
when x"1B3" => DATA <= x"8E";
when x"1B4" => DATA <= x"AE";
when x"1B5" => DATA <= x"E4";
when x"1B6" => DATA <= x"A6";
when x"1B7" => DATA <= x"84";
when x"1B8" => DATA <= x"81";
when x"1B9" => DATA <= x"41";
when x"1BA" => DATA <= x"25";
when x"1BB" => DATA <= x"68";
when x"1BC" => DATA <= x"A6";
when x"1BD" => DATA <= x"80";
when x"1BE" => DATA <= x"84";
when x"1BF" => DATA <= x"DF";
when x"1C0" => DATA <= x"A1";
when x"1C1" => DATA <= x"A0";
when x"1C2" => DATA <= x"27";
when x"1C3" => DATA <= x"F8";
when x"1C4" => DATA <= x"A6";
when x"1C5" => DATA <= x"A2";
when x"1C6" => DATA <= x"2B";
when x"1C7" => DATA <= x"16";
when x"1C8" => DATA <= x"A6";
when x"1C9" => DATA <= x"1F";
when x"1CA" => DATA <= x"81";
when x"1CB" => DATA <= x"2E";
when x"1CC" => DATA <= x"27";
when x"1CD" => DATA <= x"0A";
when x"1CE" => DATA <= x"A6";
when x"1CF" => DATA <= x"A0";
when x"1D0" => DATA <= x"2A";
when x"1D1" => DATA <= x"FC";
when x"1D2" => DATA <= x"A6";
when x"1D3" => DATA <= x"A4";
when x"1D4" => DATA <= x"26";
when x"1D5" => DATA <= x"DE";
when x"1D6" => DATA <= x"20";
when x"1D7" => DATA <= x"4C";
when x"1D8" => DATA <= x"A6";
when x"1D9" => DATA <= x"A0";
when x"1DA" => DATA <= x"2A";
when x"1DB" => DATA <= x"FC";
when x"1DC" => DATA <= x"20";
when x"1DD" => DATA <= x"06";
when x"1DE" => DATA <= x"E6";
when x"1DF" => DATA <= x"82";
when x"1E0" => DATA <= x"C1";
when x"1E1" => DATA <= x"21";
when x"1E2" => DATA <= x"24";
when x"1E3" => DATA <= x"40";
when x"1E4" => DATA <= x"81";
when x"1E5" => DATA <= x"80";
when x"1E6" => DATA <= x"27";
when x"1E7" => DATA <= x"2D";
when x"1E8" => DATA <= x"8D";
when x"1E9" => DATA <= x"81";
when x"1EA" => DATA <= x"10";
when x"1EB" => DATA <= x"BE";
when x"1EC" => DATA <= x"FF";
when x"1ED" => DATA <= x"90";
when x"1EE" => DATA <= x"81";
when x"1EF" => DATA <= x"0D";
when x"1F0" => DATA <= x"27";
when x"1F1" => DATA <= x"18";
when x"1F2" => DATA <= x"81";
when x"1F3" => DATA <= x"3B";
when x"1F4" => DATA <= x"27";
when x"1F5" => DATA <= x"12";
when x"1F6" => DATA <= x"BD";
when x"1F7" => DATA <= x"FF";
when x"1F8" => DATA <= x"A1";
when x"1F9" => DATA <= x"24";
when x"1FA" => DATA <= x"29";
when x"1FB" => DATA <= x"BD";
when x"1FC" => DATA <= x"F9";
when x"1FD" => DATA <= x"6B";
when x"1FE" => DATA <= x"81";
when x"1FF" => DATA <= x"3B";
when x"200" => DATA <= x"27";
when x"201" => DATA <= x"06";
when x"202" => DATA <= x"81";
when x"203" => DATA <= x"0D";
when x"204" => DATA <= x"26";
when x"205" => DATA <= x"1E";
when x"206" => DATA <= x"30";
when x"207" => DATA <= x"1F";
when x"208" => DATA <= x"30";
when x"209" => DATA <= x"01";
when x"20A" => DATA <= x"BF";
when x"20B" => DATA <= x"FF";
when x"20C" => DATA <= x"86";
when x"20D" => DATA <= x"35";
when x"20E" => DATA <= x"10";
when x"20F" => DATA <= x"1F";
when x"210" => DATA <= x"21";
when x"211" => DATA <= x"1A";
when x"212" => DATA <= x"01";
when x"213" => DATA <= x"20";
when x"214" => DATA <= x"23";
when x"215" => DATA <= x"BD";
when x"216" => DATA <= x"F9";
when x"217" => DATA <= x"6B";
when x"218" => DATA <= x"25";
when x"219" => DATA <= x"04";
when x"21A" => DATA <= x"81";
when x"21B" => DATA <= x"2E";
when x"21C" => DATA <= x"26";
when x"21D" => DATA <= x"06";
when x"21E" => DATA <= x"8E";
when x"21F" => DATA <= x"F8";
when x"220" => DATA <= x"16";
when x"221" => DATA <= x"BD";
when x"222" => DATA <= x"F9";
when x"223" => DATA <= x"33";
when x"224" => DATA <= x"35";
when x"225" => DATA <= x"10";
when x"226" => DATA <= x"86";
when x"227" => DATA <= x"02";
when x"228" => DATA <= x"BD";
when x"229" => DATA <= x"FC";
when x"22A" => DATA <= x"DE";
when x"22B" => DATA <= x"BD";
when x"22C" => DATA <= x"FC";
when x"22D" => DATA <= x"A2";
when x"22E" => DATA <= x"1A";
when x"22F" => DATA <= x"01";
when x"230" => DATA <= x"BD";
when x"231" => DATA <= x"FA";
when x"232" => DATA <= x"B4";
when x"233" => DATA <= x"2A";
when x"234" => DATA <= x"51";
when x"235" => DATA <= x"BE";
when x"236" => DATA <= x"FF";
when x"237" => DATA <= x"8E";
when x"238" => DATA <= x"34";
when x"239" => DATA <= x"01";
when x"23A" => DATA <= x"1F";
when x"23B" => DATA <= x"12";
when x"23C" => DATA <= x"E6";
when x"23D" => DATA <= x"07";
when x"23E" => DATA <= x"3A";
when x"23F" => DATA <= x"CE";
when x"240" => DATA <= x"FA";
when x"241" => DATA <= x"93";
when x"242" => DATA <= x"C6";
when x"243" => DATA <= x"04";
when x"244" => DATA <= x"A6";
when x"245" => DATA <= x"80";
when x"246" => DATA <= x"A1";
when x"247" => DATA <= x"C2";
when x"248" => DATA <= x"26";
when x"249" => DATA <= x"3D";
when x"24A" => DATA <= x"5A";
when x"24B" => DATA <= x"26";
when x"24C" => DATA <= x"F7";
when x"24D" => DATA <= x"A6";
when x"24E" => DATA <= x"26";
when x"24F" => DATA <= x"48";
when x"250" => DATA <= x"2A";
when x"251" => DATA <= x"41";
when x"252" => DATA <= x"84";
when x"253" => DATA <= x"1E";
when x"254" => DATA <= x"81";
when x"255" => DATA <= x"06";
when x"256" => DATA <= x"26";
when x"257" => DATA <= x"3B";
when x"258" => DATA <= x"30";
when x"259" => DATA <= x"1C";
when x"25A" => DATA <= x"BF";
when x"25B" => DATA <= x"FF";
when x"25C" => DATA <= x"82";
when x"25D" => DATA <= x"FE";
when x"25E" => DATA <= x"FF";
when x"25F" => DATA <= x"90";
when x"260" => DATA <= x"BE";
when x"261" => DATA <= x"FF";
when x"262" => DATA <= x"8A";
when x"263" => DATA <= x"35";
when x"264" => DATA <= x"02";
when x"265" => DATA <= x"34";
when x"266" => DATA <= x"50";
when x"267" => DATA <= x"10";
when x"268" => DATA <= x"8C";
when x"269" => DATA <= x"80";
when x"26A" => DATA <= x"00";
when x"26B" => DATA <= x"25";
when x"26C" => DATA <= x"04";
when x"26D" => DATA <= x"10";
when x"26E" => DATA <= x"BF";
when x"26F" => DATA <= x"FF";
when x"270" => DATA <= x"8A";
when x"271" => DATA <= x"46";
when x"272" => DATA <= x"10";
when x"273" => DATA <= x"BF";
when x"274" => DATA <= x"FF";
when x"275" => DATA <= x"90";
when x"276" => DATA <= x"BE";
when x"277" => DATA <= x"FF";
when x"278" => DATA <= x"86";
when x"279" => DATA <= x"86";
when x"27A" => DATA <= x"01";
when x"27B" => DATA <= x"AD";
when x"27C" => DATA <= x"A4";
when x"27D" => DATA <= x"35";
when x"27E" => DATA <= x"60";
when x"27F" => DATA <= x"10";
when x"280" => DATA <= x"BF";
when x"281" => DATA <= x"FF";
when x"282" => DATA <= x"8A";
when x"283" => DATA <= x"FF";
when x"284" => DATA <= x"FF";
when x"285" => DATA <= x"90";
when x"286" => DATA <= x"39";
when x"287" => DATA <= x"BE";
when x"288" => DATA <= x"FF";
when x"289" => DATA <= x"86";
when x"28A" => DATA <= x"4F";
when x"28B" => DATA <= x"35";
when x"28C" => DATA <= x"01";
when x"28D" => DATA <= x"6E";
when x"28E" => DATA <= x"A4";
when x"28F" => DATA <= x"29";
when x"290" => DATA <= x"43";
when x"291" => DATA <= x"28";
when x"292" => DATA <= x"00";
when x"293" => DATA <= x"35";
when x"294" => DATA <= x"01";
when x"295" => DATA <= x"10";
when x"296" => DATA <= x"24";
when x"297" => DATA <= x"05";
when x"298" => DATA <= x"20";
when x"299" => DATA <= x"BD";
when x"29A" => DATA <= x"F8";
when x"29B" => DATA <= x"CC";
when x"29C" => DATA <= x"3F";
when x"29D" => DATA <= x"F9";
when x"29E" => DATA <= x"4E";
when x"29F" => DATA <= x"6F";
when x"2A0" => DATA <= x"74";
when x"2A1" => DATA <= x"20";
when x"2A2" => DATA <= x"36";
when x"2A3" => DATA <= x"38";
when x"2A4" => DATA <= x"30";
when x"2A5" => DATA <= x"39";
when x"2A6" => DATA <= x"20";
when x"2A7" => DATA <= x"63";
when x"2A8" => DATA <= x"6F";
when x"2A9" => DATA <= x"64";
when x"2AA" => DATA <= x"65";
when x"2AB" => DATA <= x"00";
when x"2AC" => DATA <= x"4F";
when x"2AD" => DATA <= x"BD";
when x"2AE" => DATA <= x"FC";
when x"2AF" => DATA <= x"DE";
when x"2B0" => DATA <= x"8D";
when x"2B1" => DATA <= x"02";
when x"2B2" => DATA <= x"8B";
when x"2B3" => DATA <= x"80";
when x"2B4" => DATA <= x"B6";
when x"2B5" => DATA <= x"FE";
when x"2B6" => DATA <= x"E2";
when x"2B7" => DATA <= x"2A";
when x"2B8" => DATA <= x"FB";
when x"2B9" => DATA <= x"B6";
when x"2BA" => DATA <= x"FE";
when x"2BB" => DATA <= x"E3";
when x"2BC" => DATA <= x"39";
when x"2BD" => DATA <= x"34";
when x"2BE" => DATA <= x"06";
when x"2BF" => DATA <= x"4D";
when x"2C0" => DATA <= x"2B";
when x"2C1" => DATA <= x"23";
when x"2C2" => DATA <= x"86";
when x"2C3" => DATA <= x"04";
when x"2C4" => DATA <= x"BD";
when x"2C5" => DATA <= x"FC";
when x"2C6" => DATA <= x"DE";
when x"2C7" => DATA <= x"1F";
when x"2C8" => DATA <= x"10";
when x"2C9" => DATA <= x"BD";
when x"2CA" => DATA <= x"FC";
when x"2CB" => DATA <= x"DC";
when x"2CC" => DATA <= x"35";
when x"2CD" => DATA <= x"06";
when x"2CE" => DATA <= x"34";
when x"2CF" => DATA <= x"06";
when x"2D0" => DATA <= x"BD";
when x"2D1" => DATA <= x"FC";
when x"2D2" => DATA <= x"DE";
when x"2D3" => DATA <= x"8D";
when x"2D4" => DATA <= x"DF";
when x"2D5" => DATA <= x"1F";
when x"2D6" => DATA <= x"89";
when x"2D7" => DATA <= x"4F";
when x"2D8" => DATA <= x"1F";
when x"2D9" => DATA <= x"01";
when x"2DA" => DATA <= x"35";
when x"2DB" => DATA <= x"86";
when x"2DC" => DATA <= x"8E";
when x"2DD" => DATA <= x"F8";
when x"2DE" => DATA <= x"16";
when x"2DF" => DATA <= x"BF";
when x"2E0" => DATA <= x"FF";
when x"2E1" => DATA <= x"86";
when x"2E2" => DATA <= x"7E";
when x"2E3" => DATA <= x"FA";
when x"2E4" => DATA <= x"2E";
when x"2E5" => DATA <= x"81";
when x"2E6" => DATA <= x"82";
when x"2E7" => DATA <= x"27";
when x"2E8" => DATA <= x"39";
when x"2E9" => DATA <= x"81";
when x"2EA" => DATA <= x"83";
when x"2EB" => DATA <= x"27";
when x"2EC" => DATA <= x"37";
when x"2ED" => DATA <= x"81";
when x"2EE" => DATA <= x"84";
when x"2EF" => DATA <= x"27";
when x"2F0" => DATA <= x"33";
when x"2F1" => DATA <= x"86";
when x"2F2" => DATA <= x"06";
when x"2F3" => DATA <= x"BD";
when x"2F4" => DATA <= x"FC";
when x"2F5" => DATA <= x"DE";
when x"2F6" => DATA <= x"1F";
when x"2F7" => DATA <= x"10";
when x"2F8" => DATA <= x"BD";
when x"2F9" => DATA <= x"FC";
when x"2FA" => DATA <= x"DC";
when x"2FB" => DATA <= x"BD";
when x"2FC" => DATA <= x"FC";
when x"2FD" => DATA <= x"DA";
when x"2FE" => DATA <= x"35";
when x"2FF" => DATA <= x"06";
when x"300" => DATA <= x"BD";
when x"301" => DATA <= x"FC";
when x"302" => DATA <= x"DE";
when x"303" => DATA <= x"81";
when x"304" => DATA <= x"9D";
when x"305" => DATA <= x"27";
when x"306" => DATA <= x"B5";
when x"307" => DATA <= x"81";
when x"308" => DATA <= x"8E";
when x"309" => DATA <= x"27";
when x"30A" => DATA <= x"D1";
when x"30B" => DATA <= x"34";
when x"30C" => DATA <= x"06";
when x"30D" => DATA <= x"8D";
when x"30E" => DATA <= x"A5";
when x"30F" => DATA <= x"8B";
when x"310" => DATA <= x"80";
when x"311" => DATA <= x"34";
when x"312" => DATA <= x"01";
when x"313" => DATA <= x"8D";
when x"314" => DATA <= x"9F";
when x"315" => DATA <= x"1F";
when x"316" => DATA <= x"89";
when x"317" => DATA <= x"4F";
when x"318" => DATA <= x"1F";
when x"319" => DATA <= x"02";
when x"31A" => DATA <= x"8D";
when x"31B" => DATA <= x"98";
when x"31C" => DATA <= x"1E";
when x"31D" => DATA <= x"89";
when x"31E" => DATA <= x"1F";
when x"31F" => DATA <= x"01";
when x"320" => DATA <= x"35";
when x"321" => DATA <= x"87";
when x"322" => DATA <= x"86";
when x"323" => DATA <= x"85";
when x"324" => DATA <= x"48";
when x"325" => DATA <= x"8E";
when x"326" => DATA <= x"FF";
when x"327" => DATA <= x"82";
when x"328" => DATA <= x"EC";
when x"329" => DATA <= x"84";
when x"32A" => DATA <= x"1F";
when x"32B" => DATA <= x"01";
when x"32C" => DATA <= x"1F";
when x"32D" => DATA <= x"89";
when x"32E" => DATA <= x"4F";
when x"32F" => DATA <= x"1F";
when x"330" => DATA <= x"02";
when x"331" => DATA <= x"35";
when x"332" => DATA <= x"86";
when x"333" => DATA <= x"4D";
when x"334" => DATA <= x"27";
when x"335" => DATA <= x"5C";
when x"336" => DATA <= x"34";
when x"337" => DATA <= x"26";
when x"338" => DATA <= x"34";
when x"339" => DATA <= x"10";
when x"33A" => DATA <= x"1F";
when x"33B" => DATA <= x"89";
when x"33C" => DATA <= x"86";
when x"33D" => DATA <= x"08";
when x"33E" => DATA <= x"BD";
when x"33F" => DATA <= x"FC";
when x"340" => DATA <= x"DE";
when x"341" => DATA <= x"BD";
when x"342" => DATA <= x"FC";
when x"343" => DATA <= x"DC";
when x"344" => DATA <= x"5D";
when x"345" => DATA <= x"2A";
when x"346" => DATA <= x"04";
when x"347" => DATA <= x"A6";
when x"348" => DATA <= x"84";
when x"349" => DATA <= x"20";
when x"34A" => DATA <= x"0C";
when x"34B" => DATA <= x"86";
when x"34C" => DATA <= x"10";
when x"34D" => DATA <= x"C1";
when x"34E" => DATA <= x"15";
when x"34F" => DATA <= x"24";
when x"350" => DATA <= x"06";
when x"351" => DATA <= x"8E";
when x"352" => DATA <= x"FB";
when x"353" => DATA <= x"C1";
when x"354" => DATA <= x"3A";
when x"355" => DATA <= x"A6";
when x"356" => DATA <= x"84";
when x"357" => DATA <= x"35";
when x"358" => DATA <= x"10";
when x"359" => DATA <= x"BD";
when x"35A" => DATA <= x"FC";
when x"35B" => DATA <= x"DE";
when x"35C" => DATA <= x"1F";
when x"35D" => DATA <= x"02";
when x"35E" => DATA <= x"1E";
when x"35F" => DATA <= x"89";
when x"360" => DATA <= x"4F";
when x"361" => DATA <= x"1E";
when x"362" => DATA <= x"02";
when x"363" => DATA <= x"4A";
when x"364" => DATA <= x"2B";
when x"365" => DATA <= x"03";
when x"366" => DATA <= x"BD";
when x"367" => DATA <= x"FC";
when x"368" => DATA <= x"AB";
when x"369" => DATA <= x"34";
when x"36A" => DATA <= x"10";
when x"36B" => DATA <= x"5D";
when x"36C" => DATA <= x"2A";
when x"36D" => DATA <= x"04";
when x"36E" => DATA <= x"A6";
when x"36F" => DATA <= x"01";
when x"370" => DATA <= x"20";
when x"371" => DATA <= x"0C";
when x"372" => DATA <= x"86";
when x"373" => DATA <= x"10";
when x"374" => DATA <= x"C1";
when x"375" => DATA <= x"15";
when x"376" => DATA <= x"24";
when x"377" => DATA <= x"06";
when x"378" => DATA <= x"8E";
when x"379" => DATA <= x"FB";
when x"37A" => DATA <= x"D5";
when x"37B" => DATA <= x"3A";
when x"37C" => DATA <= x"A6";
when x"37D" => DATA <= x"84";
when x"37E" => DATA <= x"35";
when x"37F" => DATA <= x"10";
when x"380" => DATA <= x"BD";
when x"381" => DATA <= x"FC";
when x"382" => DATA <= x"DE";
when x"383" => DATA <= x"1F";
when x"384" => DATA <= x"02";
when x"385" => DATA <= x"1E";
when x"386" => DATA <= x"89";
when x"387" => DATA <= x"4F";
when x"388" => DATA <= x"1E";
when x"389" => DATA <= x"02";
when x"38A" => DATA <= x"4A";
when x"38B" => DATA <= x"2B";
when x"38C" => DATA <= x"03";
when x"38D" => DATA <= x"BD";
when x"38E" => DATA <= x"FC";
when x"38F" => DATA <= x"BB";
when x"390" => DATA <= x"35";
when x"391" => DATA <= x"A6";
when x"392" => DATA <= x"86";
when x"393" => DATA <= x"0A";
when x"394" => DATA <= x"BD";
when x"395" => DATA <= x"FC";
when x"396" => DATA <= x"DE";
when x"397" => DATA <= x"30";
when x"398" => DATA <= x"02";
when x"399" => DATA <= x"10";
when x"39A" => DATA <= x"8E";
when x"39B" => DATA <= x"00";
when x"39C" => DATA <= x"03";
when x"39D" => DATA <= x"BD";
when x"39E" => DATA <= x"FC";
when x"39F" => DATA <= x"AB";
when x"3A0" => DATA <= x"30";
when x"3A1" => DATA <= x"1E";
when x"3A2" => DATA <= x"86";
when x"3A3" => DATA <= x"07";
when x"3A4" => DATA <= x"BD";
when x"3A5" => DATA <= x"FC";
when x"3A6" => DATA <= x"DE";
when x"3A7" => DATA <= x"4F";
when x"3A8" => DATA <= x"BD";
when x"3A9" => DATA <= x"FC";
when x"3AA" => DATA <= x"DE";
when x"3AB" => DATA <= x"BD";
when x"3AC" => DATA <= x"FA";
when x"3AD" => DATA <= x"B4";
when x"3AE" => DATA <= x"8B";
when x"3AF" => DATA <= x"80";
when x"3B0" => DATA <= x"25";
when x"3B1" => DATA <= x"0F";
when x"3B2" => DATA <= x"AE";
when x"3B3" => DATA <= x"84";
when x"3B4" => DATA <= x"BD";
when x"3B5" => DATA <= x"FA";
when x"3B6" => DATA <= x"B4";
when x"3B7" => DATA <= x"A7";
when x"3B8" => DATA <= x"80";
when x"3B9" => DATA <= x"31";
when x"3BA" => DATA <= x"21";
when x"3BB" => DATA <= x"81";
when x"3BC" => DATA <= x"0D";
when x"3BD" => DATA <= x"26";
when x"3BE" => DATA <= x"F5";
when x"3BF" => DATA <= x"31";
when x"3C0" => DATA <= x"3F";
when x"3C1" => DATA <= x"39";
when x"3C2" => DATA <= x"00";
when x"3C3" => DATA <= x"05";
when x"3C4" => DATA <= x"00";
when x"3C5" => DATA <= x"05";
when x"3C6" => DATA <= x"04";
when x"3C7" => DATA <= x"05";
when x"3C8" => DATA <= x"08";
when x"3C9" => DATA <= x"0E";
when x"3CA" => DATA <= x"04";
when x"3CB" => DATA <= x"01";
when x"3CC" => DATA <= x"01";
when x"3CD" => DATA <= x"05";
when x"3CE" => DATA <= x"00";
when x"3CF" => DATA <= x"10";
when x"3D0" => DATA <= x"20";
when x"3D1" => DATA <= x"10";
when x"3D2" => DATA <= x"0D";
when x"3D3" => DATA <= x"00";
when x"3D4" => DATA <= x"04";
when x"3D5" => DATA <= x"80";
when x"3D6" => DATA <= x"05";
when x"3D7" => DATA <= x"00";
when x"3D8" => DATA <= x"05";
when x"3D9" => DATA <= x"00";
when x"3DA" => DATA <= x"05";
when x"3DB" => DATA <= x"00";
when x"3DC" => DATA <= x"00";
when x"3DD" => DATA <= x"00";
when x"3DE" => DATA <= x"05";
when x"3DF" => DATA <= x"09";
when x"3E0" => DATA <= x"05";
when x"3E1" => DATA <= x"00";
when x"3E2" => DATA <= x"08";
when x"3E3" => DATA <= x"19";
when x"3E4" => DATA <= x"00";
when x"3E5" => DATA <= x"01";
when x"3E6" => DATA <= x"0D";
when x"3E7" => DATA <= x"80";
when x"3E8" => DATA <= x"04";
when x"3E9" => DATA <= x"80";
when x"3EA" => DATA <= x"34";
when x"3EB" => DATA <= x"26";
when x"3EC" => DATA <= x"86";
when x"3ED" => DATA <= x"0C";
when x"3EE" => DATA <= x"BD";
when x"3EF" => DATA <= x"FC";
when x"3F0" => DATA <= x"DE";
when x"3F1" => DATA <= x"BD";
when x"3F2" => DATA <= x"FC";
when x"3F3" => DATA <= x"DA";
when x"3F4" => DATA <= x"10";
when x"3F5" => DATA <= x"8E";
when x"3F6" => DATA <= x"00";
when x"3F7" => DATA <= x"04";
when x"3F8" => DATA <= x"BD";
when x"3F9" => DATA <= x"FC";
when x"3FA" => DATA <= x"AB";
when x"3FB" => DATA <= x"35";
when x"3FC" => DATA <= x"06";
when x"3FD" => DATA <= x"BD";
when x"3FE" => DATA <= x"FC";
when x"3FF" => DATA <= x"DE";
when x"400" => DATA <= x"BD";
when x"401" => DATA <= x"FA";
when x"402" => DATA <= x"B4";
when x"403" => DATA <= x"34";
when x"404" => DATA <= x"02";
when x"405" => DATA <= x"10";
when x"406" => DATA <= x"8E";
when x"407" => DATA <= x"00";
when x"408" => DATA <= x"04";
when x"409" => DATA <= x"BD";
when x"40A" => DATA <= x"FC";
when x"40B" => DATA <= x"BB";
when x"40C" => DATA <= x"35";
when x"40D" => DATA <= x"A2";
when x"40E" => DATA <= x"34";
when x"40F" => DATA <= x"04";
when x"410" => DATA <= x"86";
when x"411" => DATA <= x"0E";
when x"412" => DATA <= x"BD";
when x"413" => DATA <= x"FC";
when x"414" => DATA <= x"DE";
when x"415" => DATA <= x"BD";
when x"416" => DATA <= x"FC";
when x"417" => DATA <= x"DA";
when x"418" => DATA <= x"35";
when x"419" => DATA <= x"04";
when x"41A" => DATA <= x"7E";
when x"41B" => DATA <= x"FA";
when x"41C" => DATA <= x"B0";
when x"41D" => DATA <= x"34";
when x"41E" => DATA <= x"06";
when x"41F" => DATA <= x"86";
when x"420" => DATA <= x"10";
when x"421" => DATA <= x"BD";
when x"422" => DATA <= x"FC";
when x"423" => DATA <= x"DE";
when x"424" => DATA <= x"BD";
when x"425" => DATA <= x"FC";
when x"426" => DATA <= x"DA";
when x"427" => DATA <= x"35";
when x"428" => DATA <= x"06";
when x"429" => DATA <= x"34";
when x"42A" => DATA <= x"06";
when x"42B" => DATA <= x"BD";
when x"42C" => DATA <= x"FC";
when x"42D" => DATA <= x"DE";
when x"42E" => DATA <= x"BD";
when x"42F" => DATA <= x"FA";
when x"430" => DATA <= x"B4";
when x"431" => DATA <= x"35";
when x"432" => DATA <= x"86";
when x"433" => DATA <= x"34";
when x"434" => DATA <= x"06";
when x"435" => DATA <= x"86";
when x"436" => DATA <= x"12";
when x"437" => DATA <= x"BD";
when x"438" => DATA <= x"FC";
when x"439" => DATA <= x"DE";
when x"43A" => DATA <= x"35";
when x"43B" => DATA <= x"06";
when x"43C" => DATA <= x"BD";
when x"43D" => DATA <= x"FC";
when x"43E" => DATA <= x"DE";
when x"43F" => DATA <= x"4D";
when x"440" => DATA <= x"27";
when x"441" => DATA <= x"06";
when x"442" => DATA <= x"BD";
when x"443" => DATA <= x"FC";
when x"444" => DATA <= x"A2";
when x"445" => DATA <= x"7E";
when x"446" => DATA <= x"FA";
when x"447" => DATA <= x"B4";
when x"448" => DATA <= x"34";
when x"449" => DATA <= x"04";
when x"44A" => DATA <= x"BD";
when x"44B" => DATA <= x"FC";
when x"44C" => DATA <= x"DA";
when x"44D" => DATA <= x"BD";
when x"44E" => DATA <= x"FA";
when x"44F" => DATA <= x"B4";
when x"450" => DATA <= x"4F";
when x"451" => DATA <= x"35";
when x"452" => DATA <= x"84";
when x"453" => DATA <= x"34";
when x"454" => DATA <= x"32";
when x"455" => DATA <= x"86";
when x"456" => DATA <= x"14";
when x"457" => DATA <= x"BD";
when x"458" => DATA <= x"FC";
when x"459" => DATA <= x"DE";
when x"45A" => DATA <= x"30";
when x"45B" => DATA <= x"02";
when x"45C" => DATA <= x"10";
when x"45D" => DATA <= x"8E";
when x"45E" => DATA <= x"00";
when x"45F" => DATA <= x"10";
when x"460" => DATA <= x"BD";
when x"461" => DATA <= x"FC";
when x"462" => DATA <= x"AB";
when x"463" => DATA <= x"30";
when x"464" => DATA <= x"1E";
when x"465" => DATA <= x"AE";
when x"466" => DATA <= x"84";
when x"467" => DATA <= x"BD";
when x"468" => DATA <= x"FC";
when x"469" => DATA <= x"A2";
when x"46A" => DATA <= x"35";
when x"46B" => DATA <= x"02";
when x"46C" => DATA <= x"BD";
when x"46D" => DATA <= x"FC";
when x"46E" => DATA <= x"DE";
when x"46F" => DATA <= x"BD";
when x"470" => DATA <= x"FA";
when x"471" => DATA <= x"B4";
when x"472" => DATA <= x"35";
when x"473" => DATA <= x"10";
when x"474" => DATA <= x"34";
when x"475" => DATA <= x"02";
when x"476" => DATA <= x"30";
when x"477" => DATA <= x"02";
when x"478" => DATA <= x"10";
when x"479" => DATA <= x"8E";
when x"47A" => DATA <= x"00";
when x"47B" => DATA <= x"10";
when x"47C" => DATA <= x"BD";
when x"47D" => DATA <= x"FC";
when x"47E" => DATA <= x"BB";
when x"47F" => DATA <= x"30";
when x"480" => DATA <= x"1E";
when x"481" => DATA <= x"35";
when x"482" => DATA <= x"A2";
when x"483" => DATA <= x"34";
when x"484" => DATA <= x"22";
when x"485" => DATA <= x"86";
when x"486" => DATA <= x"16";
when x"487" => DATA <= x"BD";
when x"488" => DATA <= x"FC";
when x"489" => DATA <= x"DE";
when x"48A" => DATA <= x"10";
when x"48B" => DATA <= x"8E";
when x"48C" => DATA <= x"00";
when x"48D" => DATA <= x"0D";
when x"48E" => DATA <= x"BD";
when x"48F" => DATA <= x"FC";
when x"490" => DATA <= x"AB";
when x"491" => DATA <= x"35";
when x"492" => DATA <= x"02";
when x"493" => DATA <= x"BD";
when x"494" => DATA <= x"FC";
when x"495" => DATA <= x"DE";
when x"496" => DATA <= x"10";
when x"497" => DATA <= x"8E";
when x"498" => DATA <= x"00";
when x"499" => DATA <= x"0D";
when x"49A" => DATA <= x"BD";
when x"49B" => DATA <= x"FC";
when x"49C" => DATA <= x"BB";
when x"49D" => DATA <= x"35";
when x"49E" => DATA <= x"20";
when x"49F" => DATA <= x"7E";
when x"4A0" => DATA <= x"FA";
when x"4A1" => DATA <= x"B0";
when x"4A2" => DATA <= x"A6";
when x"4A3" => DATA <= x"80";
when x"4A4" => DATA <= x"8D";
when x"4A5" => DATA <= x"38";
when x"4A6" => DATA <= x"81";
when x"4A7" => DATA <= x"0D";
when x"4A8" => DATA <= x"26";
when x"4A9" => DATA <= x"F8";
when x"4AA" => DATA <= x"39";
when x"4AB" => DATA <= x"34";
when x"4AC" => DATA <= x"04";
when x"4AD" => DATA <= x"1F";
when x"4AE" => DATA <= x"20";
when x"4AF" => DATA <= x"3A";
when x"4B0" => DATA <= x"35";
when x"4B1" => DATA <= x"04";
when x"4B2" => DATA <= x"A6";
when x"4B3" => DATA <= x"82";
when x"4B4" => DATA <= x"8D";
when x"4B5" => DATA <= x"28";
when x"4B6" => DATA <= x"31";
when x"4B7" => DATA <= x"3F";
when x"4B8" => DATA <= x"26";
when x"4B9" => DATA <= x"F8";
when x"4BA" => DATA <= x"39";
when x"4BB" => DATA <= x"34";
when x"4BC" => DATA <= x"04";
when x"4BD" => DATA <= x"1F";
when x"4BE" => DATA <= x"20";
when x"4BF" => DATA <= x"3A";
when x"4C0" => DATA <= x"35";
when x"4C1" => DATA <= x"04";
when x"4C2" => DATA <= x"BD";
when x"4C3" => DATA <= x"FA";
when x"4C4" => DATA <= x"B4";
when x"4C5" => DATA <= x"A7";
when x"4C6" => DATA <= x"82";
when x"4C7" => DATA <= x"31";
when x"4C8" => DATA <= x"3F";
when x"4C9" => DATA <= x"26";
when x"4CA" => DATA <= x"F7";
when x"4CB" => DATA <= x"39";
when x"4CC" => DATA <= x"34";
when x"4CD" => DATA <= x"02";
when x"4CE" => DATA <= x"B6";
when x"4CF" => DATA <= x"FE";
when x"4D0" => DATA <= x"E0";
when x"4D1" => DATA <= x"48";
when x"4D2" => DATA <= x"2A";
when x"4D3" => DATA <= x"FA";
when x"4D4" => DATA <= x"35";
when x"4D5" => DATA <= x"02";
when x"4D6" => DATA <= x"B7";
when x"4D7" => DATA <= x"FE";
when x"4D8" => DATA <= x"E1";
when x"4D9" => DATA <= x"39";
when x"4DA" => DATA <= x"1F";
when x"4DB" => DATA <= x"20";
when x"4DC" => DATA <= x"1F";
when x"4DD" => DATA <= x"98";
when x"4DE" => DATA <= x"34";
when x"4DF" => DATA <= x"02";
when x"4E0" => DATA <= x"B6";
when x"4E1" => DATA <= x"FE";
when x"4E2" => DATA <= x"E2";
when x"4E3" => DATA <= x"48";
when x"4E4" => DATA <= x"2A";
when x"4E5" => DATA <= x"FA";
when x"4E6" => DATA <= x"35";
when x"4E7" => DATA <= x"02";
when x"4E8" => DATA <= x"B7";
when x"4E9" => DATA <= x"FE";
when x"4EA" => DATA <= x"E3";
when x"4EB" => DATA <= x"39";
when x"4EC" => DATA <= x"34";
when x"4ED" => DATA <= x"02";
when x"4EE" => DATA <= x"B6";
when x"4EF" => DATA <= x"FE";
when x"4F0" => DATA <= x"E6";
when x"4F1" => DATA <= x"2B";
when x"4F2" => DATA <= x"51";
when x"4F3" => DATA <= x"B6";
when x"4F4" => DATA <= x"FE";
when x"4F5" => DATA <= x"E0";
when x"4F6" => DATA <= x"2B";
when x"4F7" => DATA <= x"06";
when x"4F8" => DATA <= x"35";
when x"4F9" => DATA <= x"02";
when x"4FA" => DATA <= x"6E";
when x"4FB" => DATA <= x"9F";
when x"4FC" => DATA <= x"FF";
when x"4FD" => DATA <= x"B1";
when x"4FE" => DATA <= x"B6";
when x"4FF" => DATA <= x"FE";
when x"500" => DATA <= x"E1";
when x"501" => DATA <= x"2B";
when x"502" => DATA <= x"1B";
when x"503" => DATA <= x"35";
when x"504" => DATA <= x"02";
when x"505" => DATA <= x"34";
when x"506" => DATA <= x"76";
when x"507" => DATA <= x"8D";
when x"508" => DATA <= x"1C";
when x"509" => DATA <= x"1F";
when x"50A" => DATA <= x"89";
when x"50B" => DATA <= x"4F";
when x"50C" => DATA <= x"1F";
when x"50D" => DATA <= x"02";
when x"50E" => DATA <= x"8D";
when x"50F" => DATA <= x"15";
when x"510" => DATA <= x"1F";
when x"511" => DATA <= x"89";
when x"512" => DATA <= x"4F";
when x"513" => DATA <= x"1F";
when x"514" => DATA <= x"01";
when x"515" => DATA <= x"8D";
when x"516" => DATA <= x"0E";
when x"517" => DATA <= x"AD";
when x"518" => DATA <= x"9F";
when x"519" => DATA <= x"FF";
when x"51A" => DATA <= x"FC";
when x"51B" => DATA <= x"35";
when x"51C" => DATA <= x"76";
when x"51D" => DATA <= x"3B";
when x"51E" => DATA <= x"48";
when x"51F" => DATA <= x"B7";
when x"520" => DATA <= x"FF";
when x"521" => DATA <= x"80";
when x"522" => DATA <= x"35";
when x"523" => DATA <= x"02";
when x"524" => DATA <= x"3B";
when x"525" => DATA <= x"B6";
when x"526" => DATA <= x"FE";
when x"527" => DATA <= x"E6";
when x"528" => DATA <= x"2B";
when x"529" => DATA <= x"02";
when x"52A" => DATA <= x"8D";
when x"52B" => DATA <= x"12";
when x"52C" => DATA <= x"B6";
when x"52D" => DATA <= x"FE";
when x"52E" => DATA <= x"E0";
when x"52F" => DATA <= x"2A";
when x"530" => DATA <= x"F4";
when x"531" => DATA <= x"B6";
when x"532" => DATA <= x"FE";
when x"533" => DATA <= x"E1";
when x"534" => DATA <= x"39";
when x"535" => DATA <= x"B6";
when x"536" => DATA <= x"FE";
when x"537" => DATA <= x"E6";
when x"538" => DATA <= x"2A";
when x"539" => DATA <= x"FB";
when x"53A" => DATA <= x"B6";
when x"53B" => DATA <= x"FE";
when x"53C" => DATA <= x"E7";
when x"53D" => DATA <= x"39";
when x"53E" => DATA <= x"1C";
when x"53F" => DATA <= x"7F";
when x"540" => DATA <= x"34";
when x"541" => DATA <= x"01";
when x"542" => DATA <= x"34";
when x"543" => DATA <= x"02";
when x"544" => DATA <= x"35";
when x"545" => DATA <= x"02";
when x"546" => DATA <= x"34";
when x"547" => DATA <= x"16";
when x"548" => DATA <= x"B6";
when x"549" => DATA <= x"FE";
when x"54A" => DATA <= x"E7";
when x"54B" => DATA <= x"2A";
when x"54C" => DATA <= x"22";
when x"54D" => DATA <= x"10";
when x"54E" => DATA <= x"CE";
when x"54F" => DATA <= x"FF";
when x"550" => DATA <= x"80";
when x"551" => DATA <= x"8E";
when x"552" => DATA <= x"FF";
when x"553" => DATA <= x"00";
when x"554" => DATA <= x"BD";
when x"555" => DATA <= x"FA";
when x"556" => DATA <= x"B4";
when x"557" => DATA <= x"86";
when x"558" => DATA <= x"3F";
when x"559" => DATA <= x"A7";
when x"55A" => DATA <= x"80";
when x"55B" => DATA <= x"BD";
when x"55C" => DATA <= x"FA";
when x"55D" => DATA <= x"B4";
when x"55E" => DATA <= x"A7";
when x"55F" => DATA <= x"80";
when x"560" => DATA <= x"BD";
when x"561" => DATA <= x"FA";
when x"562" => DATA <= x"B4";
when x"563" => DATA <= x"A7";
when x"564" => DATA <= x"80";
when x"565" => DATA <= x"26";
when x"566" => DATA <= x"F9";
when x"567" => DATA <= x"8E";
when x"568" => DATA <= x"FF";
when x"569" => DATA <= x"01";
when x"56A" => DATA <= x"34";
when x"56B" => DATA <= x"10";
when x"56C" => DATA <= x"7E";
when x"56D" => DATA <= x"FF";
when x"56E" => DATA <= x"BC";
when x"56F" => DATA <= x"34";
when x"570" => DATA <= x"02";
when x"571" => DATA <= x"8D";
when x"572" => DATA <= x"C2";
when x"573" => DATA <= x"35";
when x"574" => DATA <= x"02";
when x"575" => DATA <= x"81";
when x"576" => DATA <= x"05";
when x"577" => DATA <= x"26";
when x"578" => DATA <= x"06";
when x"579" => DATA <= x"7F";
when x"57A" => DATA <= x"FF";
when x"57B" => DATA <= x"94";
when x"57C" => DATA <= x"35";
when x"57D" => DATA <= x"16";
when x"57E" => DATA <= x"3B";
when x"57F" => DATA <= x"34";
when x"580" => DATA <= x"02";
when x"581" => DATA <= x"8D";
when x"582" => DATA <= x"B2";
when x"583" => DATA <= x"B7";
when x"584" => DATA <= x"FF";
when x"585" => DATA <= x"8C";
when x"586" => DATA <= x"8D";
when x"587" => DATA <= x"AD";
when x"588" => DATA <= x"B7";
when x"589" => DATA <= x"FF";
when x"58A" => DATA <= x"8D";
when x"58B" => DATA <= x"8D";
when x"58C" => DATA <= x"A8";
when x"58D" => DATA <= x"B7";
when x"58E" => DATA <= x"FF";
when x"58F" => DATA <= x"8E";
when x"590" => DATA <= x"8D";
when x"591" => DATA <= x"A3";
when x"592" => DATA <= x"B7";
when x"593" => DATA <= x"FF";
when x"594" => DATA <= x"8F";
when x"595" => DATA <= x"8D";
when x"596" => DATA <= x"9E";
when x"597" => DATA <= x"86";
when x"598" => DATA <= x"FF";
when x"599" => DATA <= x"B7";
when x"59A" => DATA <= x"FF";
when x"59B" => DATA <= x"94";
when x"59C" => DATA <= x"1C";
when x"59D" => DATA <= x"BF";
when x"59E" => DATA <= x"BE";
when x"59F" => DATA <= x"FF";
when x"5A0" => DATA <= x"8E";
when x"5A1" => DATA <= x"A6";
when x"5A2" => DATA <= x"E0";
when x"5A3" => DATA <= x"27";
when x"5A4" => DATA <= x"6C";
when x"5A5" => DATA <= x"81";
when x"5A6" => DATA <= x"02";
when x"5A7" => DATA <= x"25";
when x"5A8" => DATA <= x"5B";
when x"5A9" => DATA <= x"27";
when x"5AA" => DATA <= x"49";
when x"5AB" => DATA <= x"81";
when x"5AC" => DATA <= x"04";
when x"5AD" => DATA <= x"25";
when x"5AE" => DATA <= x"35";
when x"5AF" => DATA <= x"27";
when x"5B0" => DATA <= x"6E";
when x"5B1" => DATA <= x"5F";
when x"5B2" => DATA <= x"81";
when x"5B3" => DATA <= x"07";
when x"5B4" => DATA <= x"25";
when x"5B5" => DATA <= x"11";
when x"5B6" => DATA <= x"26";
when x"5B7" => DATA <= x"67";
when x"5B8" => DATA <= x"B6";
when x"5B9" => DATA <= x"FE";
when x"5BA" => DATA <= x"E4";
when x"5BB" => DATA <= x"2A";
when x"5BC" => DATA <= x"FB";
when x"5BD" => DATA <= x"B6";
when x"5BE" => DATA <= x"FE";
when x"5BF" => DATA <= x"E5";
when x"5C0" => DATA <= x"A7";
when x"5C1" => DATA <= x"85";
when x"5C2" => DATA <= x"5C";
when x"5C3" => DATA <= x"26";
when x"5C4" => DATA <= x"F3";
when x"5C5" => DATA <= x"20";
when x"5C6" => DATA <= x"17";
when x"5C7" => DATA <= x"B6";
when x"5C8" => DATA <= x"FE";
when x"5C9" => DATA <= x"E4";
when x"5CA" => DATA <= x"48";
when x"5CB" => DATA <= x"2A";
when x"5CC" => DATA <= x"FA";
when x"5CD" => DATA <= x"A6";
when x"5CE" => DATA <= x"85";
when x"5CF" => DATA <= x"B7";
when x"5D0" => DATA <= x"FE";
when x"5D1" => DATA <= x"E5";
when x"5D2" => DATA <= x"5C";
when x"5D3" => DATA <= x"26";
when x"5D4" => DATA <= x"F2";
when x"5D5" => DATA <= x"B6";
when x"5D6" => DATA <= x"FE";
when x"5D7" => DATA <= x"E4";
when x"5D8" => DATA <= x"48";
when x"5D9" => DATA <= x"2A";
when x"5DA" => DATA <= x"FA";
when x"5DB" => DATA <= x"B7";
when x"5DC" => DATA <= x"FE";
when x"5DD" => DATA <= x"E5";
when x"5DE" => DATA <= x"30";
when x"5DF" => DATA <= x"89";
when x"5E0" => DATA <= x"01";
when x"5E1" => DATA <= x"00";
when x"5E2" => DATA <= x"20";
when x"5E3" => DATA <= x"38";
when x"5E4" => DATA <= x"13";
when x"5E5" => DATA <= x"B6";
when x"5E6" => DATA <= x"FE";
when x"5E7" => DATA <= x"E5";
when x"5E8" => DATA <= x"F6";
when x"5E9" => DATA <= x"FE";
when x"5EA" => DATA <= x"E5";
when x"5EB" => DATA <= x"ED";
when x"5EC" => DATA <= x"81";
when x"5ED" => DATA <= x"B6";
when x"5EE" => DATA <= x"FF";
when x"5EF" => DATA <= x"94";
when x"5F0" => DATA <= x"26";
when x"5F1" => DATA <= x"F2";
when x"5F2" => DATA <= x"20";
when x"5F3" => DATA <= x"28";
when x"5F4" => DATA <= x"13";
when x"5F5" => DATA <= x"EC";
when x"5F6" => DATA <= x"81";
when x"5F7" => DATA <= x"B7";
when x"5F8" => DATA <= x"FE";
when x"5F9" => DATA <= x"E5";
when x"5FA" => DATA <= x"F7";
when x"5FB" => DATA <= x"FE";
when x"5FC" => DATA <= x"E5";
when x"5FD" => DATA <= x"B6";
when x"5FE" => DATA <= x"FF";
when x"5FF" => DATA <= x"94";
when x"600" => DATA <= x"26";
when x"601" => DATA <= x"F2";
when x"602" => DATA <= x"20";
when x"603" => DATA <= x"18";
when x"604" => DATA <= x"13";
when x"605" => DATA <= x"B6";
when x"606" => DATA <= x"FE";
when x"607" => DATA <= x"E5";
when x"608" => DATA <= x"A7";
when x"609" => DATA <= x"80";
when x"60A" => DATA <= x"B6";
when x"60B" => DATA <= x"FF";
when x"60C" => DATA <= x"94";
when x"60D" => DATA <= x"26";
when x"60E" => DATA <= x"F5";
when x"60F" => DATA <= x"20";
when x"610" => DATA <= x"0B";
when x"611" => DATA <= x"13";
when x"612" => DATA <= x"A6";
when x"613" => DATA <= x"80";
when x"614" => DATA <= x"B7";
when x"615" => DATA <= x"FE";
when x"616" => DATA <= x"E5";
when x"617" => DATA <= x"B6";
when x"618" => DATA <= x"FF";
when x"619" => DATA <= x"94";
when x"61A" => DATA <= x"26";
when x"61B" => DATA <= x"F5";
when x"61C" => DATA <= x"BF";
when x"61D" => DATA <= x"FF";
when x"61E" => DATA <= x"8E";
when x"61F" => DATA <= x"35";
when x"620" => DATA <= x"16";
when x"621" => DATA <= x"3B";
when x"622" => DATA <= x"32";
when x"623" => DATA <= x"6A";
when x"624" => DATA <= x"35";
when x"625" => DATA <= x"10";
when x"626" => DATA <= x"BF";
when x"627" => DATA <= x"FF";
when x"628" => DATA <= x"82";
when x"629" => DATA <= x"1C";
when x"62A" => DATA <= x"00";
when x"62B" => DATA <= x"6E";
when x"62C" => DATA <= x"9F";
when x"62D" => DATA <= x"FF";
when x"62E" => DATA <= x"FA";
when x"62F" => DATA <= x"FF";
when x"630" => DATA <= x"FF";
when x"631" => DATA <= x"FF";
when x"632" => DATA <= x"FF";
when x"633" => DATA <= x"FF";
when x"634" => DATA <= x"FF";
when x"635" => DATA <= x"FF";
when x"636" => DATA <= x"FF";
when x"637" => DATA <= x"FF";
when x"638" => DATA <= x"FF";
when x"639" => DATA <= x"FF";
when x"63A" => DATA <= x"FF";
when x"63B" => DATA <= x"FF";
when x"63C" => DATA <= x"FF";
when x"63D" => DATA <= x"FF";
when x"63E" => DATA <= x"FF";
when x"63F" => DATA <= x"FF";
when x"640" => DATA <= x"FF";
when x"641" => DATA <= x"FF";
when x"642" => DATA <= x"FF";
when x"643" => DATA <= x"FF";
when x"644" => DATA <= x"FF";
when x"645" => DATA <= x"FF";
when x"646" => DATA <= x"FF";
when x"647" => DATA <= x"FF";
when x"648" => DATA <= x"FF";
when x"649" => DATA <= x"FF";
when x"64A" => DATA <= x"FF";
when x"64B" => DATA <= x"FF";
when x"64C" => DATA <= x"FF";
when x"64D" => DATA <= x"FF";
when x"64E" => DATA <= x"FF";
when x"64F" => DATA <= x"FF";
when x"650" => DATA <= x"FF";
when x"651" => DATA <= x"FF";
when x"652" => DATA <= x"FF";
when x"653" => DATA <= x"FF";
when x"654" => DATA <= x"FF";
when x"655" => DATA <= x"FF";
when x"656" => DATA <= x"FF";
when x"657" => DATA <= x"FF";
when x"658" => DATA <= x"FF";
when x"659" => DATA <= x"FF";
when x"65A" => DATA <= x"FF";
when x"65B" => DATA <= x"FF";
when x"65C" => DATA <= x"FF";
when x"65D" => DATA <= x"FF";
when x"65E" => DATA <= x"FF";
when x"65F" => DATA <= x"FF";
when x"660" => DATA <= x"FF";
when x"661" => DATA <= x"FF";
when x"662" => DATA <= x"FF";
when x"663" => DATA <= x"FF";
when x"664" => DATA <= x"FF";
when x"665" => DATA <= x"FF";
when x"666" => DATA <= x"FF";
when x"667" => DATA <= x"FF";
when x"668" => DATA <= x"FF";
when x"669" => DATA <= x"FF";
when x"66A" => DATA <= x"FF";
when x"66B" => DATA <= x"FF";
when x"66C" => DATA <= x"FF";
when x"66D" => DATA <= x"FF";
when x"66E" => DATA <= x"FF";
when x"66F" => DATA <= x"FF";
when x"670" => DATA <= x"FF";
when x"671" => DATA <= x"FF";
when x"672" => DATA <= x"FF";
when x"673" => DATA <= x"FF";
when x"674" => DATA <= x"FF";
when x"675" => DATA <= x"FF";
when x"676" => DATA <= x"FF";
when x"677" => DATA <= x"FF";
when x"678" => DATA <= x"FF";
when x"679" => DATA <= x"FF";
when x"67A" => DATA <= x"FF";
when x"67B" => DATA <= x"FF";
when x"67C" => DATA <= x"FF";
when x"67D" => DATA <= x"FF";
when x"67E" => DATA <= x"FF";
when x"67F" => DATA <= x"FF";
when x"680" => DATA <= x"FF";
when x"681" => DATA <= x"FF";
when x"682" => DATA <= x"FF";
when x"683" => DATA <= x"FF";
when x"684" => DATA <= x"FF";
when x"685" => DATA <= x"FF";
when x"686" => DATA <= x"FF";
when x"687" => DATA <= x"FF";
when x"688" => DATA <= x"FF";
when x"689" => DATA <= x"FF";
when x"68A" => DATA <= x"FF";
when x"68B" => DATA <= x"FF";
when x"68C" => DATA <= x"FF";
when x"68D" => DATA <= x"FF";
when x"68E" => DATA <= x"FF";
when x"68F" => DATA <= x"FF";
when x"690" => DATA <= x"FF";
when x"691" => DATA <= x"FF";
when x"692" => DATA <= x"FF";
when x"693" => DATA <= x"FF";
when x"694" => DATA <= x"FF";
when x"695" => DATA <= x"FF";
when x"696" => DATA <= x"FF";
when x"697" => DATA <= x"FF";
when x"698" => DATA <= x"FF";
when x"699" => DATA <= x"FF";
when x"69A" => DATA <= x"FF";
when x"69B" => DATA <= x"FF";
when x"69C" => DATA <= x"FF";
when x"69D" => DATA <= x"FF";
when x"69E" => DATA <= x"FF";
when x"69F" => DATA <= x"FF";
when x"6A0" => DATA <= x"FF";
when x"6A1" => DATA <= x"FF";
when x"6A2" => DATA <= x"FF";
when x"6A3" => DATA <= x"FF";
when x"6A4" => DATA <= x"FF";
when x"6A5" => DATA <= x"FF";
when x"6A6" => DATA <= x"FF";
when x"6A7" => DATA <= x"FF";
when x"6A8" => DATA <= x"FF";
when x"6A9" => DATA <= x"FF";
when x"6AA" => DATA <= x"FF";
when x"6AB" => DATA <= x"FF";
when x"6AC" => DATA <= x"FF";
when x"6AD" => DATA <= x"FF";
when x"6AE" => DATA <= x"FF";
when x"6AF" => DATA <= x"FF";
when x"6B0" => DATA <= x"FF";
when x"6B1" => DATA <= x"FF";
when x"6B2" => DATA <= x"FF";
when x"6B3" => DATA <= x"FF";
when x"6B4" => DATA <= x"FF";
when x"6B5" => DATA <= x"FF";
when x"6B6" => DATA <= x"FF";
when x"6B7" => DATA <= x"FF";
when x"6B8" => DATA <= x"FF";
when x"6B9" => DATA <= x"FF";
when x"6BA" => DATA <= x"FF";
when x"6BB" => DATA <= x"FF";
when x"6BC" => DATA <= x"FF";
when x"6BD" => DATA <= x"FF";
when x"6BE" => DATA <= x"FF";
when x"6BF" => DATA <= x"FF";
when x"6C0" => DATA <= x"FF";
when x"6C1" => DATA <= x"FF";
when x"6C2" => DATA <= x"FF";
when x"6C3" => DATA <= x"FF";
when x"6C4" => DATA <= x"FF";
when x"6C5" => DATA <= x"FF";
when x"6C6" => DATA <= x"FF";
when x"6C7" => DATA <= x"FF";
when x"6C8" => DATA <= x"FF";
when x"6C9" => DATA <= x"FF";
when x"6CA" => DATA <= x"FF";
when x"6CB" => DATA <= x"FF";
when x"6CC" => DATA <= x"FF";
when x"6CD" => DATA <= x"FF";
when x"6CE" => DATA <= x"FF";
when x"6CF" => DATA <= x"FF";
when x"6D0" => DATA <= x"FF";
when x"6D1" => DATA <= x"FF";
when x"6D2" => DATA <= x"FF";
when x"6D3" => DATA <= x"FF";
when x"6D4" => DATA <= x"FF";
when x"6D5" => DATA <= x"FF";
when x"6D6" => DATA <= x"FF";
when x"6D7" => DATA <= x"FF";
when x"6D8" => DATA <= x"FF";
when x"6D9" => DATA <= x"FF";
when x"6DA" => DATA <= x"FF";
when x"6DB" => DATA <= x"FF";
when x"6DC" => DATA <= x"FF";
when x"6DD" => DATA <= x"FF";
when x"6DE" => DATA <= x"FF";
when x"6DF" => DATA <= x"FF";
when x"6E0" => DATA <= x"00";
when x"6E1" => DATA <= x"00";
when x"6E2" => DATA <= x"00";
when x"6E3" => DATA <= x"00";
when x"6E4" => DATA <= x"00";
when x"6E5" => DATA <= x"00";
when x"6E6" => DATA <= x"00";
when x"6E7" => DATA <= x"00";
when x"6E8" => DATA <= x"FF";
when x"6E9" => DATA <= x"FF";
when x"6EA" => DATA <= x"FF";
when x"6EB" => DATA <= x"FF";
when x"6EC" => DATA <= x"FF";
when x"6ED" => DATA <= x"FF";
when x"6EE" => DATA <= x"FF";
when x"6EF" => DATA <= x"FF";
when x"6F0" => DATA <= x"FE";
when x"6F1" => DATA <= x"21";
when x"6F2" => DATA <= x"FE";
when x"6F3" => DATA <= x"21";
when x"6F4" => DATA <= x"FE";
when x"6F5" => DATA <= x"21";
when x"6F6" => DATA <= x"FC";
when x"6F7" => DATA <= x"EC";
when x"6F8" => DATA <= x"FE";
when x"6F9" => DATA <= x"21";
when x"6FA" => DATA <= x"FE";
when x"6FB" => DATA <= x"22";
when x"6FC" => DATA <= x"FE";
when x"6FD" => DATA <= x"21";
when x"6FE" => DATA <= x"F8";
when x"6FF" => DATA <= x"2C";
when x"700" => DATA <= x"00";
when x"701" => DATA <= x"00";
when x"702" => DATA <= x"00";
when x"703" => DATA <= x"00";
when x"704" => DATA <= x"00";
when x"705" => DATA <= x"00";
when x"706" => DATA <= x"00";
when x"707" => DATA <= x"00";
when x"708" => DATA <= x"00";
when x"709" => DATA <= x"00";
when x"70A" => DATA <= x"00";
when x"70B" => DATA <= x"00";
when x"70C" => DATA <= x"00";
when x"70D" => DATA <= x"00";
when x"70E" => DATA <= x"00";
when x"70F" => DATA <= x"00";
when x"710" => DATA <= x"00";
when x"711" => DATA <= x"00";
when x"712" => DATA <= x"00";
when x"713" => DATA <= x"00";
when x"714" => DATA <= x"00";
when x"715" => DATA <= x"00";
when x"716" => DATA <= x"00";
when x"717" => DATA <= x"00";
when x"718" => DATA <= x"00";
when x"719" => DATA <= x"00";
when x"71A" => DATA <= x"00";
when x"71B" => DATA <= x"00";
when x"71C" => DATA <= x"00";
when x"71D" => DATA <= x"00";
when x"71E" => DATA <= x"00";
when x"71F" => DATA <= x"00";
when x"720" => DATA <= x"00";
when x"721" => DATA <= x"00";
when x"722" => DATA <= x"00";
when x"723" => DATA <= x"00";
when x"724" => DATA <= x"00";
when x"725" => DATA <= x"00";
when x"726" => DATA <= x"00";
when x"727" => DATA <= x"00";
when x"728" => DATA <= x"00";
when x"729" => DATA <= x"00";
when x"72A" => DATA <= x"00";
when x"72B" => DATA <= x"00";
when x"72C" => DATA <= x"00";
when x"72D" => DATA <= x"00";
when x"72E" => DATA <= x"00";
when x"72F" => DATA <= x"00";
when x"730" => DATA <= x"00";
when x"731" => DATA <= x"00";
when x"732" => DATA <= x"00";
when x"733" => DATA <= x"00";
when x"734" => DATA <= x"00";
when x"735" => DATA <= x"00";
when x"736" => DATA <= x"00";
when x"737" => DATA <= x"00";
when x"738" => DATA <= x"00";
when x"739" => DATA <= x"00";
when x"73A" => DATA <= x"00";
when x"73B" => DATA <= x"00";
when x"73C" => DATA <= x"00";
when x"73D" => DATA <= x"00";
when x"73E" => DATA <= x"00";
when x"73F" => DATA <= x"00";
when x"740" => DATA <= x"00";
when x"741" => DATA <= x"00";
when x"742" => DATA <= x"00";
when x"743" => DATA <= x"00";
when x"744" => DATA <= x"00";
when x"745" => DATA <= x"00";
when x"746" => DATA <= x"00";
when x"747" => DATA <= x"00";
when x"748" => DATA <= x"00";
when x"749" => DATA <= x"00";
when x"74A" => DATA <= x"00";
when x"74B" => DATA <= x"00";
when x"74C" => DATA <= x"00";
when x"74D" => DATA <= x"00";
when x"74E" => DATA <= x"00";
when x"74F" => DATA <= x"00";
when x"750" => DATA <= x"00";
when x"751" => DATA <= x"00";
when x"752" => DATA <= x"00";
when x"753" => DATA <= x"00";
when x"754" => DATA <= x"00";
when x"755" => DATA <= x"00";
when x"756" => DATA <= x"00";
when x"757" => DATA <= x"00";
when x"758" => DATA <= x"00";
when x"759" => DATA <= x"00";
when x"75A" => DATA <= x"00";
when x"75B" => DATA <= x"00";
when x"75C" => DATA <= x"00";
when x"75D" => DATA <= x"00";
when x"75E" => DATA <= x"00";
when x"75F" => DATA <= x"00";
when x"760" => DATA <= x"00";
when x"761" => DATA <= x"00";
when x"762" => DATA <= x"00";
when x"763" => DATA <= x"00";
when x"764" => DATA <= x"00";
when x"765" => DATA <= x"00";
when x"766" => DATA <= x"00";
when x"767" => DATA <= x"00";
when x"768" => DATA <= x"00";
when x"769" => DATA <= x"00";
when x"76A" => DATA <= x"00";
when x"76B" => DATA <= x"00";
when x"76C" => DATA <= x"00";
when x"76D" => DATA <= x"00";
when x"76E" => DATA <= x"00";
when x"76F" => DATA <= x"00";
when x"770" => DATA <= x"00";
when x"771" => DATA <= x"00";
when x"772" => DATA <= x"00";
when x"773" => DATA <= x"00";
when x"774" => DATA <= x"00";
when x"775" => DATA <= x"00";
when x"776" => DATA <= x"00";
when x"777" => DATA <= x"00";
when x"778" => DATA <= x"00";
when x"779" => DATA <= x"00";
when x"77A" => DATA <= x"00";
when x"77B" => DATA <= x"00";
when x"77C" => DATA <= x"00";
when x"77D" => DATA <= x"00";
when x"77E" => DATA <= x"00";
when x"77F" => DATA <= x"00";
when x"780" => DATA <= x"00";
when x"781" => DATA <= x"00";
when x"782" => DATA <= x"F8";
when x"783" => DATA <= x"16";
when x"784" => DATA <= x"F8";
when x"785" => DATA <= x"B0";
when x"786" => DATA <= x"F8";
when x"787" => DATA <= x"16";
when x"788" => DATA <= x"00";
when x"789" => DATA <= x"00";
when x"78A" => DATA <= x"F8";
when x"78B" => DATA <= x"00";
when x"78C" => DATA <= x"00";
when x"78D" => DATA <= x"00";
when x"78E" => DATA <= x"00";
when x"78F" => DATA <= x"00";
when x"790" => DATA <= x"FF";
when x"791" => DATA <= x"B9";
when x"792" => DATA <= x"FF";
when x"793" => DATA <= x"00";
when x"794" => DATA <= x"00";
when x"795" => DATA <= x"7E";
when x"796" => DATA <= x"FA";
when x"797" => DATA <= x"86";
when x"798" => DATA <= x"7E";
when x"799" => DATA <= x"F8";
when x"79A" => DATA <= x"2C";
when x"79B" => DATA <= x"7E";
when x"79C" => DATA <= x"FA";
when x"79D" => DATA <= x"86";
when x"79E" => DATA <= x"7E";
when x"79F" => DATA <= x"FA";
when x"7A0" => DATA <= x"86";
when x"7A1" => DATA <= x"7E";
when x"7A2" => DATA <= x"F9";
when x"7A3" => DATA <= x"3C";
when x"7A4" => DATA <= x"7E";
when x"7A5" => DATA <= x"FA";
when x"7A6" => DATA <= x"86";
when x"7A7" => DATA <= x"7E";
when x"7A8" => DATA <= x"F8";
when x"7A9" => DATA <= x"71";
when x"7AA" => DATA <= x"7E";
when x"7AB" => DATA <= x"F9";
when x"7AC" => DATA <= x"11";
when x"7AD" => DATA <= x"7E";
when x"7AE" => DATA <= x"F9";
when x"7AF" => DATA <= x"05";
when x"7B0" => DATA <= x"7E";
when x"7B1" => DATA <= x"FE";
when x"7B2" => DATA <= x"21";
when x"7B3" => DATA <= x"7E";
when x"7B4" => DATA <= x"F9";
when x"7B5" => DATA <= x"2C";
when x"7B6" => DATA <= x"7E";
when x"7B7" => DATA <= x"FA";
when x"7B8" => DATA <= x"86";
when x"7B9" => DATA <= x"7E";
when x"7BA" => DATA <= x"F8";
when x"7BB" => DATA <= x"71";
when x"7BC" => DATA <= x"7E";
when x"7BD" => DATA <= x"FE";
when x"7BE" => DATA <= x"24";
when x"7BF" => DATA <= x"7E";
when x"7C0" => DATA <= x"F8";
when x"7C1" => DATA <= x"D2";
when x"7C2" => DATA <= x"7E";
when x"7C3" => DATA <= x"FA";
when x"7C4" => DATA <= x"86";
when x"7C5" => DATA <= x"7E";
when x"7C6" => DATA <= x"F9";
when x"7C7" => DATA <= x"33";
when x"7C8" => DATA <= x"7E";
when x"7C9" => DATA <= x"FA";
when x"7CA" => DATA <= x"86";
when x"7CB" => DATA <= x"7E";
when x"7CC" => DATA <= x"FA";
when x"7CD" => DATA <= x"86";
when x"7CE" => DATA <= x"7E";
when x"7CF" => DATA <= x"FC";
when x"7D0" => DATA <= x"33";
when x"7D1" => DATA <= x"7E";
when x"7D2" => DATA <= x"FC";
when x"7D3" => DATA <= x"83";
when x"7D4" => DATA <= x"7E";
when x"7D5" => DATA <= x"FC";
when x"7D6" => DATA <= x"1D";
when x"7D7" => DATA <= x"7E";
when x"7D8" => DATA <= x"FC";
when x"7D9" => DATA <= x"0E";
when x"7DA" => DATA <= x"7E";
when x"7DB" => DATA <= x"FB";
when x"7DC" => DATA <= x"EA";
when x"7DD" => DATA <= x"7E";
when x"7DE" => DATA <= x"FC";
when x"7DF" => DATA <= x"53";
when x"7E0" => DATA <= x"7E";
when x"7E1" => DATA <= x"FA";
when x"7E2" => DATA <= x"AC";
when x"7E3" => DATA <= x"81";
when x"7E4" => DATA <= x"0D";
when x"7E5" => DATA <= x"26";
when x"7E6" => DATA <= x"07";
when x"7E7" => DATA <= x"86";
when x"7E8" => DATA <= x"0A";
when x"7E9" => DATA <= x"BD";
when x"7EA" => DATA <= x"FF";
when x"7EB" => DATA <= x"EE";
when x"7EC" => DATA <= x"86";
when x"7ED" => DATA <= x"0D";
when x"7EE" => DATA <= x"7E";
when x"7EF" => DATA <= x"FC";
when x"7F0" => DATA <= x"CC";
when x"7F1" => DATA <= x"7E";
when x"7F2" => DATA <= x"FB";
when x"7F3" => DATA <= x"33";
when x"7F4" => DATA <= x"7E";
when x"7F5" => DATA <= x"FA";
when x"7F6" => DATA <= x"BD";
when x"7F7" => DATA <= x"7E";
when x"7F8" => DATA <= x"F9";
when x"7F9" => DATA <= x"76";
when x"7FA" => DATA <= x"F8";
when x"7FB" => DATA <= x"B0";
when x"7FC" => DATA <= x"FA";
when x"7FD" => DATA <= x"86";
when x"7FE" => DATA <= x"F8";
when x"7FF" => DATA <= x"2C";
when others => DATA <= (others => '0');
end case;
end process;
end RTL;
| gpl-3.0 | 95879023fd961b878da1f3e01d78aa3b | 0.358739 | 2.978535 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/maps/allddr.vhd | 1 | 50,533 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: allddr
-- File: allddr.vhd
-- Author: David Lindh, Jiri Gaisler - Gaisler Research
-- Description: DDR input/output registers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
package allddr is
component rhumc_iddr_reg is
port(
Q1 : out std_ulogic;
Q2 : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
component unisim_iddr_reg is
generic ( tech : integer := virtex4; arch : integer := 0);
port(
Q1 : out std_ulogic;
Q2 : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
component gen_iddr_reg
generic (scantest: integer; noasync: integer);
port (
Q1 : out std_ulogic;
Q2 : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic;
testen: in std_ulogic;
testrst: in std_ulogic);
end component;
component rhumc_oddr_reg
port (
Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component ec_oddr_reg
port (
Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component unisim_oddr_reg
generic (tech : integer := virtex4; arch : integer := 0);
port (
Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component gen_oddr_reg
generic (scantest: integer; noasync: integer);
port (
Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic;
testen: in std_ulogic;
testrst: in std_ulogic);
end component;
component axcel_oddr_reg is
port(
Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component axcel_iddr_reg is
port(
Q1 : out std_ulogic;
Q2 : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component nextreme_oddr_reg
port(
CK : in std_ulogic;
DH : in std_ulogic;
DL : in std_ulogic;
DOE : in std_ulogic;
Q : out std_ulogic;
OE : out std_ulogic;
RSTB : in std_ulogic);
end component;
component nextreme_iddr_reg
port(
CK : in std_ulogic;
D : in std_ulogic;
QH : out std_ulogic;
QL : out std_ulogic;
RSTB : in std_ulogic);
end component;
component apa3_oddr_reg is
port(
Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component apa3_iddr_reg is
port(
Q1 : out std_ulogic;
Q2 : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component apa3e_oddr_reg is
port(
Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component apa3e_iddr_reg is
port(
Q1 : out std_ulogic;
Q2 : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component apa3l_oddr_reg is
port(
Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component apa3l_iddr_reg is
port(
Q1 : out std_ulogic;
Q2 : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component igloo2_oddr_reg is
port(
Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component igloo2_iddr_reg is
port(
Q1 : out std_ulogic;
Q2 : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component spartan3e_ddr_phy
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- DDR state clock
clkread : out std_ulogic; -- DDR read clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end component;
component virtex4_ddr_phy
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0; phyiconf : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0);
ck : in std_logic_vector(2 downto 0)
);
end component;
component virtex2_ddr_phy
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end component;
component stratixii_ddr_phy
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end component;
component cycloneiii_ddr_phy
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end component;
component generic_ddr_phy_wo_pads
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0; mobile : integer := 0;
abits: integer := 14; nclk: integer := 3; ncs: integer := 2);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clk0r : in std_ulogic;
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (abits-1 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
ck : in std_logic_vector(nclk-1 downto 0);
moben : in std_logic
);
end component;
component tsmc90_tci_ddr_phy
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clk90_sigi_0 : in std_logic;
rclk_sigi_1 : in std_logic;
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
--ddr_clk_fb_out : out std_logic;
--ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqsin : in std_logic_vector (dbits/8-1 downto 0);-- ddr dqs
ddr_dqsout : out std_logic_vector (dbits/8-1 downto 0);-- ddr dqs
ddr_dqsoen : out std_logic_vector (dbits/8-1 downto 0);-- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dqin : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dqout : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dqoen : out std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- ddr address
ba : in std_logic_vector ( 1 downto 0); -- ddr bank address
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr output data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0);
ck : in std_logic_vector(2 downto 0);
moben : in std_logic;
conf : in std_logic_vector(63 downto 0);
tstclkout : out std_logic_vector(3 downto 0)
);
end component;
component virtex5_ddr2_phy_wo_pads
generic (
MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ; clk_div : integer := 2;
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
ddelayb6 : integer := 0; ddelayb7 : integer := 0; ddelayb8: integer := 0;
ddelayb9 : integer := 0; ddelayb10 : integer := 0; ddelayb11: integer := 0;
numidelctrl : integer := 4; norefclk : integer := 0;
tech : integer := virtex5; eightbanks : integer range 0 to 1 := 0;
dqsse : integer range 0 to 1 := 0;
abits : integer := 14; nclk : integer := 3; ncs : integer := 2);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref200 : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
addr : in std_logic_vector (abits-1 downto 0); -- ddr addr
ba : in std_logic_vector ( 2 downto 0); -- ddr bank address
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
cal_en : in std_logic_vector(dbits/8-1 downto 0);
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
cal_rst : in std_logic;
odt : in std_logic_vector(ncs-1 downto 0)
);
end component;
component stratixii_ddr2_phy
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; eightbanks : integer range 0 to 1 := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- PLL locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(1 downto 0);
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 2 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0);
cal_en : in std_logic_vector(dbits/8-1 downto 0);
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
cal_rst : in std_logic;
odt : in std_logic_vector(1 downto 0)
);
end component;
component stratixiii_ddr2_phy
generic (
MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ; clk_div : integer := 2;
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
ddelayb6 : integer := 0; ddelayb7 : integer := 0;
numidelctrl : integer := 4; norefclk : integer := 0;
tech : integer := stratix3; rskew : integer := 0;
eightbanks : integer range 0 to 1 := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref200 : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqsn
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(1 downto 0);
addr : in std_logic_vector (13 downto 0); -- ddr addrees
ba : in std_logic_vector ( 2 downto 0); -- ddr bank address
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0);
cal_en : in std_logic_vector(dbits/8-1 downto 0);
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
cal_pll : in std_logic_vector(1 downto 0);
cal_rst : in std_logic;
odt : in std_logic_vector(1 downto 0);
oct : in std_logic
);
end component;
component spartan3a_ddr2_phy
generic (MHz : integer := 125; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2;
clk_div : integer := 2; tech : integer := spartan3;
rskew : integer := 0; eightbanks : integer range 0 to 1 := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqsn
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(1 downto 0);
addr : in std_logic_vector (13 downto 0);
ba : in std_logic_vector ( 2 downto 0);
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0);
cal_pll : in std_logic_vector(1 downto 0);
odt : in std_logic_vector(1 downto 0)
);
end component;
component easic90_ddr2_phy
generic (
tech : integer;
MHz : integer;
clk_mul : integer;
clk_div : integer;
dbits : integer;
rstdelay : integer := 200;
eightbanks : integer range 0 to 1 := 0);
port (
rstn : in std_logic;
clk : in std_logic;
clkout : out std_ulogic;
lock : out std_ulogic;
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_ulogic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic;
ddr_rasb : out std_ulogic;
ddr_casb : out std_ulogic;
ddr_dm : out std_logic_vector (dbits/8-1 downto 0);
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0);
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0);
ddr_ad : out std_logic_vector (13 downto 0);
ddr_ba : out std_logic_vector (1+eightbanks downto 0);
ddr_dq : inout std_logic_vector (dbits-1 downto 0);
ddr_odt : out std_logic_vector(1 downto 0);
addr : in std_logic_vector (13 downto 0);
ba : in std_logic_vector ( 2 downto 0);
dqin : out std_logic_vector (dbits*2-1 downto 0);
dqout : in std_logic_vector (dbits*2-1 downto 0);
dm : in std_logic_vector (dbits/4-1 downto 0);
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0);
odt : in std_logic_vector(1 downto 0);
dqs_gate : in std_ulogic);
end component;
component spartan6_ddr2_phy_wo_pads
generic (MHz : integer := 125; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2;
clk_div : integer := 2; tech : integer := spartan6;
rskew : integer := 0; eightbanks : integer range 0 to 1 := 0;
abits : integer := 14;
nclk : integer := 3; ncs : integer := 2 );
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0);
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0);
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0);
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits-1 downto 0);
ddr_dq_out : out std_logic_vector (dbits-1 downto 0);
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0);
ddr_odt : out std_logic_vector(ncs-1 downto 0);
addr : in std_logic_vector (abits-1 downto 0);
ba : in std_logic_vector ( 2 downto 0);
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
cal_en : in std_logic_vector(dbits/8-1 downto 0);
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
cal_rst : in std_logic;
odt : in std_logic_vector(1 downto 0)
);
end component;
component generic_ddr2_phy_wo_pads is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0;
eightbanks: integer := 0; abits: integer := 14;
nclk: integer := 3; ncs: integer := 2);
port(
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clk0r : in std_ulogic; -- system clock returned
--clkread : out std_ulogic;
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(1 downto 0); -- ddr odt
addr : in std_logic_vector (abits-1 downto 0); -- data mask
ba : in std_logic_vector (2 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0);
ck : in std_logic_vector(2 downto 0);
odt : in std_logic_vector(1 downto 0)
);
end component;
component n2x_ddr2_phy is
generic (
MHz : integer := 100;
rstdelay : integer := 200;
dbits : integer := 16;
clk_mul : integer := 2;
clk_div : integer := 2;
norefclk : integer := 0;
eightbanks : integer range 0 to 1 := 0;
dqsse : integer range 0 to 1 := 0;
abits : integer := 14;
nclk : integer := 3;
ncs : integer := 2;
ctrl2en : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clk270d : in std_logic; -- input clock shifted 270 degrees
-- for operating without PLL
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqsn
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
rden_pad : inout std_logic_vector(dbits/8-1 downto 0); -- pad delay comp. dummy I/O
addr : in std_logic_vector (abits-1 downto 0); -- ddr address
ba : in std_logic_vector ( 2 downto 0); -- ddr bank address
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
noen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
odt : in std_logic_vector(ncs-1 downto 0);
read_pend : in std_logic_vector(7 downto 0);
regwdata : in std_logic_vector(63 downto 0);
regwrite : in std_logic_vector(1 downto 0);
regrdata : out std_logic_vector(63 downto 0);
dqin_valid : out std_logic;
-- Copy of control signals for 2nd DIMM
ddr_web2 : out std_ulogic; -- ddr write enable
ddr_rasb2 : out std_ulogic; -- ddr ras
ddr_casb2 : out std_ulogic; -- ddr cas
ddr_ad2 : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba2 : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
-- Pass through to pads
dq_control : in std_logic_vector(17 downto 0);
dqs_control : in std_logic_vector(17 downto 0);
ck_control : in std_logic_vector(17 downto 0);
cmd_control : in std_logic_vector(17 downto 0);
compen : in std_logic;
compupd : in std_logic
);
end component;
component ut90nhbd_ddr_phy_wo_pads is
generic (
MHz: integer := 100;
abits: integer := 15;
dbits: integer := 96;
nclk: integer := 3;
ncs: integer := 2);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (abits-1 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
ck : in std_logic_vector(nclk-1 downto 0);
moben : in std_ulogic;
dqvalid : out std_ulogic;
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end component;
component generic_lpddr2phy_wo_pads is
generic (
tech : integer := 0;
dbits : integer := 16;
nclk: integer := 3;
ncs: integer := 2;
clkratio: integer := 1;
scantest: integer := 0);
port (
rst : in std_ulogic;
clkin : in std_ulogic;
clkin2 : in std_ulogic;
clkout : out std_ulogic;
clkoutret : in std_ulogic; -- clkout returned
clkout2 : out std_ulogic;
lock : out std_ulogic;
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_ca : out std_logic_vector(9 downto 0);
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
ca : in std_logic_vector (10*2*clkratio-1 downto 0);
cke : in std_logic_vector (ncs*clkratio-1 downto 0);
csn : in std_logic_vector (ncs*clkratio-1 downto 0);
dqin : out std_logic_vector (dbits*2*clkratio-1 downto 0); -- ddr output data
dqout : in std_logic_vector (dbits*2*clkratio-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4*clkratio-1 downto 0); -- data mask
ckstop : in std_ulogic;
boot : in std_ulogic;
wrpend : in std_logic_vector(7 downto 0);
rdpend : in std_logic_vector(7 downto 0);
wrreq : out std_logic_vector(clkratio-1 downto 0);
rdvalid : out std_logic_vector(clkratio-1 downto 0);
refcal : in std_ulogic;
refcalwu : in std_ulogic;
refcaldone : out std_ulogic;
phycmd : in std_logic_vector(7 downto 0);
phycmden : in std_ulogic;
phycmdin : in std_logic_vector(31 downto 0);
phycmdout : out std_logic_vector(31 downto 0);
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end component;
component uniphy_ddr2_phy is
generic (
MHz : integer := 100;
rstdelay : integer := 200;
dbits : integer := 16;
clk_mul : integer := 2;
clk_div : integer := 2;
eightbanks : integer range 0 to 1 := 0;
abits : integer := 14;
nclk : integer := 3;
ncs : integer := 2);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
-- for operating without PLL
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqsn
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
addr : in std_logic_vector (abits-1 downto 0); -- ddr address
ba : in std_logic_vector ( 2 downto 0); -- ddr bank address
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
odt : in std_logic_vector(ncs-1 downto 0);
read_pend : in std_logic_vector(7 downto 0);
regwdata : in std_logic_vector(63 downto 0);
regwrite : in std_logic_vector(1 downto 0);
regrdata : out std_logic_vector(63 downto 0);
dqin_valid : out std_ulogic;
oct_rdn : in std_logic := '0';
oct_rup : in std_logic := '0'
);
end component;
end;
| gpl-3.0 | a95035706d889dd52c65eb0388e5261a | 0.538143 | 3.306917 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/sim/ser_phy.vhd | 1 | 5,790 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
----------------------------------------------------------------------------
-- Entity: ser_phy
-- File: ser_phy.vhd
-- Description: Serial wrapper for simulation model of an Ethernet PHY
-- Author: Andrea Gianarro
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
library grlib;
library gaisler;
use ieee.std_logic_1164.all;
use grlib.stdlib.all;
use gaisler.net.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
entity ser_phy is
generic(
address : integer range 0 to 31 := 0;
extended_regs : integer range 0 to 1 := 1;
aneg : integer range 0 to 1 := 1;
base100_t4 : integer range 0 to 1 := 0;
base100_x_fd : integer range 0 to 1 := 1;
base100_x_hd : integer range 0 to 1 := 1;
fd_10 : integer range 0 to 1 := 1;
hd_10 : integer range 0 to 1 := 1;
base100_t2_fd : integer range 0 to 1 := 1;
base100_t2_hd : integer range 0 to 1 := 1;
base1000_x_fd : integer range 0 to 1 := 0;
base1000_x_hd : integer range 0 to 1 := 0;
base1000_t_fd : integer range 0 to 1 := 1;
base1000_t_hd : integer range 0 to 1 := 1;
rmii : integer range 0 to 1 := 0;
rgmii : integer range 0 to 1 := 0;
fabtech : integer := 0;
memtech : integer := 0;
transtech : integer := 0
);
port(
rstn : in std_logic;
clk_125 : in std_logic;
rst_125 : in std_logic;
eth_rx_p : out std_logic;
eth_rx_n : out std_logic;
eth_tx_p : in std_logic;
eth_tx_n : in std_logic := '0';
mdio : inout std_logic;
mdc : in std_logic;
-- added for igloo2_serdes
apbin : in apb_in_serdes := apb_in_serdes_none;
apbout : out apb_out_serdes;
m2gl_padin : in pad_in_serdes := pad_in_serdes_none;
m2gl_padout : out pad_out_serdes;
serdes_clk125 : out std_logic;
rx_aligned : out std_logic
);
end;
architecture behavioral of ser_phy is
signal int_tx_rstn : std_logic;
signal int_rx_rstn : std_logic;
signal phy_ethi : eth_in_type;
signal pcs_ethi : eth_in_type;
signal phy_etho : eth_out_type;
signal pcs_etho : eth_out_type;
begin
p0: phy
generic map(
address => address,
extended_regs => extended_regs,
aneg => aneg,
fd_10 => fd_10,
hd_10 => hd_10,
base100_t4 => base100_t4,
base100_x_fd => base100_x_fd,
base100_x_hd => base100_x_hd,
base100_t2_fd => base100_t2_fd,
base100_t2_hd => base100_t2_hd,
base1000_x_fd => base1000_x_fd,
base1000_x_hd => base1000_x_hd,
base1000_t_fd => base1000_t_fd,
base1000_t_hd => base1000_t_hd,
rmii => 0,
rgmii => 0
)
port map(
rstn => rstn,
mdio => mdio,
tx_clk => open,
rx_clk => open,
rxd => phy_etho.txd,
rx_dv => phy_etho.tx_en,
rx_er => phy_etho.tx_er,
rx_col => open,
rx_crs => open,
txd => phy_ethi.rxd,
tx_en => phy_ethi.rx_dv,
tx_er => phy_ethi.rx_er,
mdc => mdc,
gtx_clk => phy_ethi.gtx_clk
);
-- GMII to MII adapter fixed to Gigabit mode (disabled)
phy_etho.gbit <= '1';
phy_etho.speed <= '0';
adapt_10_100_0: gmii_to_mii
port map (
tx_rstn => int_tx_rstn,
rx_rstn => int_rx_rstn,
gmiii => phy_ethi, -- OUT
gmiio => phy_etho, -- IN
miii => pcs_ethi, -- IN
miio => pcs_etho -- OUT
);
pcs0: sgmii
generic map (
fabtech => fabtech,
memtech => memtech,
transtech => transtech
)
port map(
clk_125 => clk_125,
rst_125 => rst_125,
ser_rx_p => eth_tx_p,
ser_rx_n => eth_tx_n,
ser_tx_p => eth_rx_p,
ser_tx_n => eth_rx_n,
txd => pcs_etho.txd,
tx_en => pcs_etho.tx_en,
tx_er => pcs_etho.tx_er,
tx_clk => pcs_ethi.gtx_clk,
tx_rstn => int_tx_rstn,
rxd => pcs_ethi.rxd,
rx_dv => pcs_ethi.rx_dv,
rx_er => pcs_ethi.rx_er,
rx_col => pcs_ethi.rx_col,
rx_crs => pcs_ethi.rx_crs,
rx_clk => pcs_ethi.rx_clk,
rx_rstn => int_rx_rstn,
mdc => mdc,
-- added for igloo2_serdes
apbin => apbin,
apbout => apbout,
m2gl_padin => m2gl_padin,
m2gl_padout => m2gl_padout,
serdes_clk125 => serdes_clk125,
rx_aligned => rx_aligned
);
end architecture;
-- pragma translate_on
| gpl-3.0 | aecadb52b8fe61a5960c9b75e3f3e233 | 0.523316 | 3.310463 | false | false | false | false |
yishinli/emc2 | src/hal/drivers/m5i20/hostmot5_src/new3phf.vhd | 1 | 5,865 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity new3ph is
Port (
clk: in STD_LOGIC;
pwmrefcnt: in STD_LOGIC_VECTOR(9 downto 0);
ibus: in STD_LOGIC_VECTOR (15 downto 0);
obus: out STD_LOGIC_VECTOR (15 downto 0);
writestb: in STD_LOGIC;
readstb: in STD_LOGIC;
addr: in STD_LOGIC_VECTOR (1 downto 0);
outa: out STD_LOGIC;
outb: out STD_LOGIC;
outc: out STD_LOGIC
);
end new3ph;
architecture behavioral of new3ph is
signal creg: STD_LOGIC_VECTOR (2 downto 0);
alias refmsb: std_logic is pwmrefcnt(9);
signal oldrefmsb: std_logic;
signal FIFORead: std_logic;
signal Start: std_logic;
signal HostStart: std_logic;
signal PopData: STD_LOGIC_VECTOR (15 downto 0);
alias PWMPtr: STD_LOGIC_VECTOR (1 downto 0) is PopData(1 downto 0);
alias Aflag: std_logic is PopData(4);
signal PushData: STD_LOGIC_VECTOR (15 downto 0);
signal FIFOdatawr: STD_LOGIC;
signal IncDataCount: STD_LOGIC;
signal IncDataCountp: STD_LOGIC;
signal PushPtr: STD_LOGIC_VECTOR (7 downto 0);
signal PopPtr: STD_LOGIC_VECTOR (7 downto 0);
signal FPopPtr: STD_LOGIC_VECTOR (7 downto 0);
signal DataCount: STD_LOGIC_VECTOR (8 downto 0);
signal pwma: STD_LOGIC_VECTOR (9 downto 0);
signal pwmb: STD_LOGIC_VECTOR (9 downto 0);
signal pwmc: STD_LOGIC_VECTOR (9 downto 0);
signal pwmouta: STD_LOGIC;
signal pwmoutb: STD_LOGIC;
signal pwmoutc: STD_LOGIC;
component FIFOMem IS
port (
addra: IN std_logic_VECTOR(7 downto 0);
addrb: IN std_logic_VECTOR(7 downto 0);
clka: IN std_logic;
clkb: IN std_logic;
dina: IN std_logic_VECTOR(15 downto 0);
dinb: IN std_logic_VECTOR(15 downto 0);
douta: OUT std_logic_VECTOR(15 downto 0);
doutb: OUT std_logic_VECTOR(15 downto 0);
wea: IN std_logic;
web: IN std_logic);
end component FIFOMem;
begin
AFIFO: FIFOMem port map (
addra => FPopPtr,
addrb => PushPtr,
clka => clk,
clkb => clk,
dina => x"0000",
dinb => ibus,
douta => PopData,
doutb => PushData,
wea => '0',
web => FIFOdatawr
);
athreephase: process (clk,addr,readstb,writestb,
creg, pwmouta, pwmoutb, pwmoutc
)
begin
if clk'event and clk = '1' then
IncDataCount <= IncDataCountP;
if (IncDataCount = '1') and (FIFOREAD = '0') then
IncDataCount <= '0';
IncDataCountP <= '0';
DataCount <= DataCount + 1;
end if;
if (UNSIGNED(pwmrefcnt) < UNSIGNED(pwma)) then
pwmouta <= '1';
else
pwmouta <= '0';
end if;
if (UNSIGNED(pwmrefcnt) < UNSIGNED(pwmb)) then
pwmoutb <= '1';
else
pwmoutb <= '0';
end if;
if (UNSIGNED(pwmrefcnt) < UNSIGNED(pwmc)) then
pwmoutc <= '1';
else
pwmoutc <= '0';
end if;
oldrefmsb <= refmsb;
if FIFORead = '1' and DataCount /= 0 then
case PWMPtr is
when "00" =>
pwma <= PopData(15 downto 6);
when "01" =>
pwmb <= PopData(15 downto 6);
when "10" =>
pwmc <= PopData(15 downto 6);
when others => null;
end case;
PopPtr <= FPopPtr;
DataCount <= DataCount -1;
end if;
if writestb = '1' then
case addr is
when "00" => PushPtr <= PushPtr + 1;
IncDataCountp <= '1';
when "01" => creg <= ibus(2 downto 0);
when "10" => Datacount <= (others => '0');
PopPtr <= (others => '0');
PushPtr <= (others => '0');
when others => null;
end case;
end if;
end if; -- clk
if ((Start = '1') or (AFlag = '0')) and (DataCount /= 0) then
FIFORead <= '1';
FPopPtr <= PopPtr +1;
else
FIFORead <= '0';
FPopPtr <= PopPtr;
end if;
if writestb = '1' and addr = "11" then
HostStart <= '1';
else
HostStart <= '0';
end if;
if writestb = '1' and addr = "00" then
FIFOdataWr <= '1';
else
FIFODataWr <= '0';
end if;
if (oldrefmsb = '1' and refmsb = '0' and AFlag = '1' and creg(0) = '1') or (Hoststart = '1' ) then
Start <= '1';
else
Start <= '0';
end if;
obus <= "ZZZZZZZZZZZZZZZZ";
if readstb = '1' then
case addr is
when "00" => obus <= PopData;
when "01" => obus <= (2 => creg(2),1 => creg(1),0 =>creg(0), others => '0');
when "10" => obus(8 downto 0) <= DataCount;
when others => obus <= "ZZZZZZZZZZZZZZZZ";
end case;
else
obus <= "ZZZZZZZZZZZZZZZZ";
end if;
if creg(1) = '1' then
if creg(2) = '0' then
outa <= pwmouta;
outb <= pwmoutb;
outc <= pwmoutc;
else
outa <= pwmoutb;
outb <= pwmouta;
outc <= pwmoutc;
end if;
else
outa <= 'Z';
outb <= 'Z';
outc <= 'Z';
end if;
end process;
end behavioral;
| lgpl-2.1 | be60b19bddaefc557f4c1862809b7690 | 0.471782 | 3.493151 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-gr-xc6s/leon3mp.vhd | 1 | 50,410 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2011 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.i2c.all;
use gaisler.can.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.spacewire.all;
-- pragma translate_off
use gaisler.sim.all;
library unisim;
use unisim.all;
-- pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_ulogic;
clk : in std_ulogic; -- 50 MHz main clock
clk2 : in std_ulogic; -- User clock
clk125 : in std_ulogic; -- 125 MHz clock from PHY
wdogn : out std_ulogic;
address : out std_logic_vector(24 downto 0);
data : inout std_logic_vector(31 downto 24);
oen : out std_ulogic;
writen : out std_ulogic;
romsn : out std_logic;
ddr_clk : out std_logic;
ddr_clkb : out std_logic;
ddr_cke : out std_logic;
ddr_odt : out std_logic;
ddr_we : out std_ulogic; -- ddr write enable
ddr_ras : out std_ulogic; -- ddr ras
ddr_csn : out std_ulogic; -- ddr csn
ddr_cas : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (1 downto 0); -- ddr dqs n
ddr_ad : out std_logic_vector (12 downto 0); -- ddr address
ddr_ba : out std_logic_vector (2 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (15 downto 0); -- ddr data
ddr_rzq : inout std_ulogic;
ddr_zio : inout std_ulogic;
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
ctsn1 : in std_ulogic; -- UART1 ctsn
rtsn1 : out std_ulogic; -- UART1 trsn
txd2 : out std_ulogic; -- UART2 tx data
rxd2 : in std_ulogic; -- UART2 rx data
ctsn2 : in std_ulogic; -- UART2 ctsn
rtsn2 : out std_ulogic; -- UART2 rtsn
pio : inout std_logic_vector(17 downto 0); -- I/O port
genio : inout std_logic_vector(59 downto 0); -- I/O port
switch : in std_logic_vector(9 downto 0); -- I/O port
led : out std_logic_vector(3 downto 0); -- I/O port
erx_clk : in std_ulogic;
emdio : inout std_logic; -- ethernet PHY interface
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_ulogic;
emdint : in std_ulogic;
etx_clk : out std_ulogic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_ulogic;
emdc : out std_ulogic;
ps2clk : inout std_logic_vector(1 downto 0);
ps2data : inout std_logic_vector(1 downto 0);
iic_scl : inout std_ulogic;
iic_sda : inout std_ulogic;
ddc_scl : inout std_ulogic;
ddc_sda : inout std_ulogic;
dvi_iic_scl : inout std_logic;
dvi_iic_sda : inout std_logic;
tft_lcd_data : out std_logic_vector(11 downto 0);
tft_lcd_clk_p : out std_ulogic;
tft_lcd_clk_n : out std_ulogic;
tft_lcd_hsync : out std_ulogic;
tft_lcd_vsync : out std_ulogic;
tft_lcd_de : out std_ulogic;
tft_lcd_reset_b : out std_ulogic;
spw_clk : in std_ulogic;
spw_rxdp : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxdn : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxsp : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxsn : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txdp : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txdn : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txsp : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txsn : out std_logic_vector(0 to CFG_SPW_NUM-1);
-- SPI flash
spi_sel_n : inout std_ulogic;
spi_clk : out std_ulogic;
spi_mosi : out std_ulogic
);
end;
architecture rtl of leon3mp is
component BUFG port (O : out std_logic; I : in std_logic); end component;
component IODELAY2
generic (
COUNTER_WRAPAROUND : string := "WRAPAROUND";
DATA_RATE : string := "SDR";
DELAY_SRC : string := "IO";
IDELAY2_VALUE : integer := 0;
IDELAY_MODE : string := "NORMAL";
IDELAY_TYPE : string := "DEFAULT";
IDELAY_VALUE : integer := 0;
ODELAY_VALUE : integer := 0;
SERDES_MODE : string := "NONE";
SIM_TAPDELAY_VALUE : integer := 75
);
port (
BUSY : out std_ulogic;
DATAOUT : out std_ulogic;
DATAOUT2 : out std_ulogic;
DOUT : out std_ulogic;
TOUT : out std_ulogic;
CAL : in std_ulogic;
CE : in std_ulogic;
CLK : in std_ulogic;
IDATAIN : in std_ulogic;
INC : in std_ulogic;
IOCLK0 : in std_ulogic;
IOCLK1 : in std_ulogic;
ODATAIN : in std_ulogic;
RST : in std_ulogic;
T : in std_ulogic
);
end component;
attribute syn_netlist_hierarchy : boolean;
attribute syn_netlist_hierarchy of rtl : architecture is false;
constant use_eth_input_delay : integer := 1;
constant use_eth_output_delay : integer := 1;
constant use_eth_data_output_delay : integer := 1;
constant use_eth_input_delay_clk : integer := 0;
constant use_gtx_clk : integer := 0;
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := CFG_NCPU+CFG_AHB_UART+CFG_GRETH+
CFG_AHB_JTAG+CFG_SPW_NUM*CFG_SPW_EN;
signal vcc, gnd : std_logic;
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal apbi, apbi2 : apb_slv_in_type;
signal apbo, apbo2 : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal vahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal vahbmo : ahb_mst_out_type;
signal clkm, rstn, rstraw, sdclkl : std_ulogic;
signal clk_200 : std_ulogic;
signal clk25, clk40, clk65 : std_ulogic;
signal cgi, cgi2, cgi3 : clkgen_in_type;
signal cgo, cgo2, cgo3 : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gmiii, rgmiii, rgmiii_buf, rgmii_pad : eth_in_type;
signal gmiio, rgmiio : eth_out_type;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal gpioi2 : gpio_in_type;
signal gpioo2 : gpio_out_type;
signal gpioi3 : gpio_in_type;
signal gpioo3 : gpio_out_type;
signal can_lrx, can_ltx : std_logic_vector(0 to 7);
signal lock, calib_done, clkml, lclk, rst, ndsuact, wdogl : std_ulogic := '0';
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal ethclk, ddr2clk : std_ulogic;
signal kbdi : ps2_in_type;
signal kbdo : ps2_out_type;
signal moui : ps2_in_type;
signal mouo : ps2_out_type;
signal vgao : apbvga_out_type;
signal lcd_datal : std_logic_vector(11 downto 0);
signal lcd_hsyncl, lcd_vsyncl, lcd_del, lcd_reset_bl : std_ulogic;
signal i2ci, dvi_i2ci : i2c_in_type;
signal i2co, dvi_i2co : i2c_out_type;
signal spmi : spimctrl_in_type;
signal spmo : spimctrl_out_type;
signal spmi2 : spimctrl_in_type;
signal spmo2 : spimctrl_out_type;
constant BOARD_FREQ : integer := 50000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := CFG_CAN;
constant DDR2_FREQ : integer := 200000; -- DDR2 input frequency in KHz
signal spwi : grspw_in_type_vector(0 to CFG_SPW_NUM-1);
signal spwo : grspw_out_type_vector(0 to CFG_SPW_NUM-1);
signal dtmp : std_logic_vector(CFG_SPW_NUM*CFG_SPW_PORTS-1 downto 0);
signal stmp : std_logic_vector(CFG_SPW_NUM*CFG_SPW_PORTS-1 downto 0);
signal spw_rxtxclk : std_ulogic;
signal spw_rxclkn : std_ulogic;
signal spw_rxclk : std_logic_vector(0 to CFG_SPW_NUM*CFG_SPW_PORTS);
signal spw_rstn : std_ulogic;
signal spw_rstn_sync : std_ulogic;
signal stati : ahbstat_in_type;
signal fpi : grfpu_in_vector_type;
signal fpo : grfpu_out_vector_type;
signal rstgtxn : std_logic;
signal idelay_reset_cnt : std_logic_vector(3 downto 0);
signal idelay_cal_cnt : std_logic_vector(3 downto 0);
signal idelayctrl_reset : std_logic;
signal idelayctrl_cal : std_logic;
signal rgmiii_rx_clk_n : std_logic;
signal rgmiii_rx_clk_n_buf : std_logic;
signal rgmiio_tx_clk,rgmiio_tx_en : std_logic;
signal rgmiio_txd : std_logic_vector(3 downto 0);
-- Used for connecting input/output signals to the DDR2 controller
signal core_ddr_clk : std_logic_vector(2 downto 0);
signal core_ddr_clkb : std_logic_vector(2 downto 0);
signal core_ddr_cke : std_logic_vector(1 downto 0);
signal core_ddr_csb : std_logic_vector(1 downto 0);
signal core_ddr_ad : std_logic_vector(13 downto 0);
signal core_ddr_odt : std_logic_vector(1 downto 0);
constant SPW_LOOP_BACK : integer := 0;
signal video_clk, clk50, clk100, spw100 : std_logic; -- signals to vga_clkgen.
signal clk_sel : std_logic_vector(1 downto 0);
signal clkvga, clkvga_p, clkvga_n : std_ulogic;
signal clk_125, clk_125_pll, clk_125_bufg : std_ulogic;
signal nerror : std_ulogic;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of clk50 : signal is true;
attribute syn_preserve of clk50 : signal is true;
attribute keep of clk50 : signal is true;
attribute syn_keep of video_clk : signal is true;
attribute syn_preserve of video_clk : signal is true;
attribute keep of video_clk : signal is true;
attribute syn_preserve of ddr2clk : signal is true;
attribute keep of ddr2clk : signal is true;
attribute syn_keep of ddr2clk : signal is true;
attribute syn_preserve of spw100 : signal is true;
attribute keep of spw100 : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute keep of clkm : signal is true;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1'; gnd <= '0';
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
ddr2clk <= lclk;
ethclk <= lclk;
no_clk_mig : if CFG_MIG_DDR2 = 0 generate
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
CFG_CLK_NOFB, 0, 0, 0, BOARD_FREQ)
port map (lclk, lclk, clkm, open, open, sdclkl, open, cgi, cgo, open, clk50, clk100);
rst0 : rstgen -- reset generator
generic map(syncin => 1)
port map (rst, clkm, lock, rstn, rstraw);
end generate;
clk_mig : if CFG_MIG_DDR2 = 1 generate
clk50 <= clkm;
rstraw <= rst;
cgo.clklock <= '1';
end generate;
resetn_pad : inpad generic map (tech => padtech) port map (resetn, rst);
lock <= cgo.clklock and calib_done;
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 16)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
nosh : if CFG_GRFPUSH = 0 generate
cpu : for i in 0 to CFG_NCPU-1 generate
l3ft : if CFG_LEON3FT_EN /= 0 generate
leon3ft0 : leon3ft -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ,
CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE, CFG_BP,
CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clkm);
end generate;
l3s : if CFG_LEON3FT_EN = 0 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
end generate;
end generate;
sh : if CFG_GRFPUSH = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
l3ft : if CFG_LEON3FT_EN /= 0 generate
leon3ft0 : leon3ftsh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ,
CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE,
CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clkm, fpi(i), fpo(i));
end generate;
l3s : if CFG_LEON3FT_EN = 0 generate
u0 : leon3sh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), fpi(i), fpo(i));
end generate;
end generate;
grfpush0 : grfpushwx generic map ((CFG_FPU-1), CFG_NCPU, fabtech)
port map (clkm, rstn, fpi, fpo);
end generate;
nerror <= dbgo(0).error;
led1_pad : odpad generic map (tech => padtech) port map (led(1), nerror);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsuen_pad : inpad generic map (tech => padtech) port map (switch(7), dsui.enable);
dsubre_pad : inpad generic map (tech => padtech) port map (switch(8), dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (led(0), ndsuact);
ndsuact <= not dsuo.active;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0'; ahbso(2) <= ahbs_none;
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (rxd2, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (txd2, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd);
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "00";
memi.brdyn <= '0'; memi.bexcn <= '1';
mctrl0 : if CFG_MCTRL_LEON2 /= 0 generate
mctrl0 : mctrl generic map (hindex => 0, pindex => 0,
paddr => 0, srbanks => 2, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN,
invclk => CFG_CLK_NOFB, sepbus => CFG_MCTRL_SEPBUS,
pageburst => CFG_MCTRL_PAGE, rammask => 0, iomask => 0)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
addr_pad : outpadv generic map (width => 25, tech => padtech)
port map (address, memo.address(24 downto 0));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
bdr : for i in 0 to 0 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
end generate;
end generate;
nomctrl : if CFG_MCTRL_LEON2 = 0 generate
romsn <= '1'; ahbso(0) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0 : ahbrep generic map (hindex => 6, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(6));
-- pragma translate_on
----------------------------------------------------------------------
--- DDR2 memory controller ------------------------------------------
----------------------------------------------------------------------
ddr_csn <= '0';
mig_gen : if (CFG_MIG_DDR2 = 1) generate
ddrc : entity work.ahb2mig_grxc6s_2p
generic map(
hindex => 4, haddr => 16#400#, hmask => 16#F80#,
pindex => 0, paddr => 0, vgamst => CFG_SVGA_ENABLE, vgaburst => 64,
clkdiv => 10)
port map(
mcb3_dram_dq => ddr_dq,
mcb3_dram_a => ddr_ad,
mcb3_dram_ba => ddr_ba,
mcb3_dram_ras_n => ddr_ras,
mcb3_dram_cas_n => ddr_cas,
mcb3_dram_we_n => ddr_we,
mcb3_dram_odt => ddr_odt,
mcb3_dram_cke => ddr_cke,
mcb3_dram_dm => ddr_dm(0),
mcb3_dram_udqs => ddr_dqs(1),
mcb3_dram_udqs_n => ddr_dqsn(1),
mcb3_rzq => ddr_rzq,
mcb3_zio => ddr_zio,
mcb3_dram_udm => ddr_dm(1),
mcb3_dram_dqs => ddr_dqs(0),
mcb3_dram_dqs_n => ddr_dqsn(0),
mcb3_dram_ck => ddr_clk,
mcb3_dram_ck_n => ddr_clkb,
ahbsi => ahbsi,
ahbso => ahbso(4),
ahbmi => vahbmi,
ahbmo => vahbmo,
apbi => apbi2,
apbo => apbo2(0),
calib_done => calib_done,
rst_n_syn => rstn,
rst_n_async => rstraw,
clk_amba => clkm,
clk_mem_n => ddr2clk,
clk_mem_p => ddr2clk,
test_error => open,
clk_125 => clk_125,
clk_100 => clk100
);
end generate;
noddr : if (CFG_DDR2SP+CFG_MIG_DDR2) = 0 generate calib_done <= '1'; end generate;
----------------------------------------------------------------------
--- SPI Memory Controller--------------------------------------------
----------------------------------------------------------------------
spimc: if CFG_SPICTRL_ENABLE = 0 and CFG_SPIMCTRL = 1 generate
spimctrl0 : spimctrl -- SPI Memory Controller
generic map (hindex => 3, hirq => 7, faddr => 16#e00#, fmask => 16#ff8#,
ioaddr => 16#002#, iomask => 16#fff#,
spliten => CFG_SPLIT, oepol => 0,
sdcard => CFG_SPIMCTRL_SDCARD,
readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => CFG_SPIMCTRL_DUALOUTPUT,
scaler => CFG_SPIMCTRL_SCALER,
altscaler => CFG_SPIMCTRL_ASCALER,
pwrupcnt => CFG_SPIMCTRL_PWRUPCNT)
port map (rstn, clkm, ahbsi, ahbso(3), spmi, spmo);
-- MISO is shared with Flash data 0
spmi.miso <= memi.data(24);
mosi_pad : outpad generic map (tech => padtech)
port map (spi_mosi, spmo.mosi);
sck_pad : outpad generic map (tech => padtech)
port map (spi_clk, spmo.sck);
slvsel0_pad : odpad generic map (tech => padtech)
port map (spi_sel_n, spmo.csn);
end generate;
nospimc: if ((CFG_SPICTRL_ENABLE = 0 and CFG_SPIMCTRL = 0) or
(CFG_SPICTRL_ENABLE = 1 and CFG_SPIMCTRL = 1) or
(CFG_SPICTRL_ENABLE = 1 and CFG_SPIMCTRL = 0))generate
mosi_pad : outpad generic map (tech => padtech)
port map (spi_mosi, '0');
sck_pad : outpad generic map (tech => padtech)
port map (spi_clk, '0');
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
apb1 : apbctrl -- AHB/APB bridge
generic map (hindex => 13, haddr => CFG_APBADDR+1, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(13), apbi2, apbo2 );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0';
rxd1_pad : inpad generic map (tech => padtech) port map (rxd1, u1i.rxd);
txd1_pad : outpad generic map (tech => padtech) port map (txd1, u1o.txd);
cts1_pad : inpad generic map (tech => padtech) port map (ctsn1, u1i.ctsn);
rts1_pad : outpad generic map (tech => padtech) port map (rtsn1, u1o.rtsn);
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
rts1_pad : outpad generic map (tech => padtech) port map (rtsn2, '0');
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW, wdog => CFG_GPT_WDOGEN*CFG_GPT_WDOG)
port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
gpti <= gpti_dhalt_drive(dsuo.tstop);
end generate;
wden : if CFG_GPT_WDOGEN /= 0 generate
wdogl <= gpto.wdogn or not rstn;
--wdogn_pad : odpad generic map (tech => padtech) port map (wdogn, wdogl);
wdogn_pad : outpad generic map (tech => padtech) port map (wdogn, wdogl);
end generate;
wddis : if CFG_GPT_WDOGEN = 0 generate
--wdogn_pad : odpad generic map (tech => padtech) port map (wdogn, vcc);
wdogn_pad : outpad generic map (tech => padtech) port map (wdogn, vcc);
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
kbd : if CFG_KBD_ENABLE /= 0 generate
ps21 : apbps2 generic map(pindex => 4, paddr => 4, pirq => 4)
port map(rstn, clkm, apbi, apbo(4), moui, mouo);
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
end generate;
nokbd : if CFG_KBD_ENABLE = 0 generate
apbo(4) <= apb_none; mouo <= ps2o_none;
apbo(5) <= apb_none; kbdo <= ps2o_none;
end generate;
kbdclk_pad : iopad generic map (tech => padtech)
port map (ps2clk(1),kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
kbdata_pad : iopad generic map (tech => padtech)
port map (ps2data(1), kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
mouclk_pad : iopad generic map (tech => padtech)
port map (ps2clk(0),mouo.ps2_clk_o, mouo.ps2_clk_oe, moui.ps2_clk_i);
mouata_pad : iopad generic map (tech => padtech)
port map (ps2data(0), mouo.ps2_data_o, mouo.ps2_data_oe, moui.ps2_data_i);
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, ethclk, apbi, apbo(6), vgao);
video_clk <= not ethclk;
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
clk0 => 20000, clk1 => 0, --1000000000/((BOARD_FREQ * CFG_CLKMUL)/CFG_CLKDIV),
clk2 => 0, clk3 => 0, burstlen => 6)
port map(rstn, clkm, video_clk, apbi, apbo(6), vgao, vahbmi,
vahbmo, clk_sel);
end generate;
--b0 : techbuf generic map (2, fabtech) port map (clk50, video_clk);
video_clk <= clk50;
vgadvi : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) /= 0 generate
dvi0 : entity work.svga2ch7301c generic map (tech => fabtech, dynamic => 1)
port map (clkm, vgao, video_clk, clkvga_p, clkvga_n,
lcd_datal, lcd_hsyncl, lcd_vsyncl, lcd_del);
i2cdvi : i2cmst
generic map (pindex => 9, paddr => 9, pmask => 16#FFF#, pirq => 3)
port map (rstn, clkm, apbi, apbo(9), dvi_i2ci, dvi_i2co);
end generate;
novga : if (CFG_VGA_ENABLE = 0 and CFG_SVGA_ENABLE = 0) generate
apbo(6) <= apb_none; vgao <= vgao_none;
end generate;
tft_lcd_data_pad : outpadv generic map (width => 12, tech => padtech)
port map (tft_lcd_data, lcd_datal);
tft_lcd_clkp_pad : outpad generic map (tech => padtech)
port map (tft_lcd_clk_p, clkvga_p);
tft_lcd_clkn_pad : outpad generic map (tech => padtech)
port map (tft_lcd_clk_n, clkvga_n);
tft_lcd_hsync_pad : outpad generic map (tech => padtech)
port map (tft_lcd_hsync, lcd_hsyncl);
tft_lcd_vsync_pad : outpad generic map (tech => padtech)
port map (tft_lcd_vsync, lcd_vsyncl);
tft_lcd_de_pad : outpad generic map (tech => padtech)
port map (tft_lcd_de, lcd_del);
tft_lcd_reset_pad : outpad generic map (tech => padtech)
port map (tft_lcd_reset_b, rstn);
dvi_i2c_scl_pad : iopad generic map (tech => padtech)
port map (dvi_iic_scl, dvi_i2co.scl, dvi_i2co.scloen, dvi_i2ci.scl);
dvi_i2c_sda_pad : iopad generic map (tech => padtech)
port map (dvi_iic_sda, dvi_i2co.sda, dvi_i2co.sdaoen, dvi_i2ci.sda);
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 10, paddr => 10, imask => CFG_GRGPIO_IMASK, nbits => 16)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(10),
gpioi => gpioi, gpioo => gpioo);
p0 : if (CFG_CAN = 0) or (CFG_CAN_NUM = 1) generate
pio_pads : for i in 1 to 2 generate
pio_pad : iopad generic map (tech => padtech)
port map (pio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
p1 : if (CFG_CAN = 0) generate
pio_pads : for i in 4 to 5 generate
pio_pad : iopad generic map (tech => padtech)
port map (pio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
pio_pad0 : iopad generic map (tech => padtech)
port map (pio(0), gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
pio_pad1 : iopad generic map (tech => padtech)
port map (pio(3), gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
pio_pads : for i in 6 to 15 generate
pio_pad : iopad generic map (tech => padtech)
port map (pio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
-- make an additonal 32 bit GPIO port for genio(31..0)
gpio1 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio1: grgpio
generic map(pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 32)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(11),
gpioi => gpioi2, gpioo => gpioo2);
pio_pads : for i in 0 to 31 generate
pio_pad : iopad generic map (tech => padtech)
port map (genio(i), gpioo2.dout(i), gpioo2.oen(i), gpioi2.din(i));
end generate;
end generate;
gpio2 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio2: grgpio
generic map(pindex => 12, paddr => 12, imask => CFG_GRGPIO_IMASK, nbits => 28)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(12),
gpioi => gpioi3, gpioo => gpioo3);
pio_pads : for i in 0 to 27 generate
pio_pad : iopad generic map (tech => padtech)
port map (genio(i+32), gpioo3.dout(i), gpioo3.oen(i), gpioi3.din(i));
end generate;
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
stati <= ahbstat_in_none;
ahbstat0 : ahbstat generic map (pindex => 13, paddr => 13, pirq => 1,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(13));
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 14, paddr => 14, pirq => 6, memtech => memtech,
mdcscaler => CPU_FREQ/1000, rmii => 0, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 2, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF, phyrstadr => 1,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, enable_mdint => 1,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL,
giga => CFG_GRETH1G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
apbi => apbi, apbo => apbo(14), ethi => gmiii, etho => gmiio);
end generate;
led(3 downto 2) <= not (gmiio.gbit & gmiio.speed);
noethindelay0 : if (use_eth_input_delay = 0) generate
rgmiii.rx_dv <= rgmiii_buf.rx_dv;
rgmiii.rxd <= rgmiii_buf.rxd;
end generate;
noethoutdelay0 : if (use_eth_output_delay = 0) generate
rgmiio_tx_clk <= rgmiio.tx_clk;
end generate;
noethdataoutdelay0 : if (use_eth_data_output_delay = 0) generate
rgmiio_tx_en <= rgmiio.tx_en;
rgmiio_txd <= rgmiio.txd(3 downto 0);
end generate;
ethindelay0 : if (use_eth_input_delay /= 0) generate
erx_clk0 : if (use_eth_input_delay_clk /= 0) generate
delay_rgmii_rx_clk : IODELAY2 generic map(
DELAY_SRC => "IDATAIN",
IDELAY_TYPE => "FIXED",
DATA_RATE => "DDR",
IDELAY_VALUE => 0 -- (See table 39 in Xilinx ds162.pdf)
)
port map(
IDATAIN => rgmiii_buf.rx_clk,
T => '1',
ODATAIN => '0',
CAL => '0',
IOCLK0 => '0',
IOCLK1 => '0',
CLK => '0',
INC => '0',
CE => '0',
RST => '0',
BUSY => OPEN,
DATAOUT => rgmiii.rx_clk,
DATAOUT2 => OPEN,
TOUT => OPEN,
DOUT => OPEN
);
end generate;
delay_rgmii_rx_ctl0 : IODELAY2 generic map(
DELAY_SRC => "IDATAIN",
IDELAY_TYPE => "FIXED",
DATA_RATE => "DDR",
IDELAY_VALUE => 80 -- (See table 39 in Xilinx ds162.pdf)
)
port map(
IDATAIN => rgmiii_buf.rx_dv,
T => '1',
ODATAIN => '0',
CAL => '0',
IOCLK0 => '0',
IOCLK1 => '0',
CLK => '0',
INC => '0',
CE => '0',
RST => '0',
BUSY => OPEN,
DATAOUT => rgmiii.rx_dv,
DATAOUT2 => OPEN,
TOUT => OPEN,
DOUT => OPEN
);
rgmii_rxd : for i in 0 to 3 generate
delay_rgmii_rxd0 : IODELAY2 generic map(
DELAY_SRC => "IDATAIN",
IDELAY_TYPE => "FIXED",
DATA_RATE => "DDR",
IDELAY_VALUE => 80 -- (See table 39 in Xilinx ds162.pdf)
)
port map(
IDATAIN => rgmiii_buf.rxd(i),
T => '1',
ODATAIN => '0',
CAL => '0',
IOCLK0 => '0',
IOCLK1 => '0',
CLK => '0',
INC => '0',
CE => '0',
RST => '0',
BUSY => OPEN,
DATAOUT => rgmiii.rxd(i),
DATAOUT2 => OPEN,
TOUT => OPEN,
DOUT => OPEN
);
end generate;
end generate;
ethoutdelay0 : if (use_eth_output_delay /= 0) generate
delay_rgmii_tx_clk0 : IODELAY2 generic map(
DELAY_SRC => "ODATAIN",
IDELAY_TYPE => "FIXED",
DATA_RATE => "DDR",
ODELAY_VALUE => 30 -- (See table 39 in Xilinx ds162.pdf)
)
port map(
IDATAIN => '0',
T => '1',
ODATAIN => rgmiio.tx_clk,
CAL => '0',
IOCLK0 => '0',
IOCLK1 => '0',
CLK => '0',
INC => '0',
CE => '0',
RST => '0',
BUSY => OPEN,
DATAOUT => OPEN,
DATAOUT2 => OPEN,
TOUT => OPEN,
DOUT => rgmiio_tx_clk
);
end generate;
ethoutdatadelay0 : if (use_eth_data_output_delay /= 0) generate
delay_rgmii_tx_en0 : IODELAY2 generic map(
DELAY_SRC => "ODATAIN",
IDELAY_TYPE => "FIXED",
DATA_RATE => "DDR",
ODELAY_VALUE => 0
)
port map(
IDATAIN => '0',
T => '1',
ODATAIN => rgmiio.tx_en,
CAL => '0',
IOCLK0 => '0',
IOCLK1 => '0',
CLK => '0',
INC => '0',
CE => '0',
RST => '0',
BUSY => OPEN,
DATAOUT => OPEN,
DATAOUT2 => OPEN,
TOUT => OPEN,
DOUT => rgmiio_tx_en
);
rgmii_txd : for i in 0 to 3 generate
delay_rgmii_txd0 : IODELAY2 generic map(
DELAY_SRC => "ODATAIN",
IDELAY_TYPE => "FIXED",
DATA_RATE => "DDR",
ODELAY_VALUE => 0
)
port map(
IDATAIN => '0',
T => '1',
ODATAIN => rgmiio.txd(i),
CAL => '0',
IOCLK0 => '0',
IOCLK1 => '0',
CLK => '0',
INC => '0',
CE => '0',
RST => '0',
BUSY => OPEN,
DATAOUT => OPEN,
DATAOUT2 => OPEN,
TOUT => OPEN,
DOUT => rgmiio_txd(i)
);
end generate;
end generate;
rgmii0 : rgmii generic map (pindex => 15, paddr => 16#010#, pmask => 16#ff0#, tech => fabtech,
gmii => CFG_GRETH1G, debugmem => 1, abits => 8, no_clk_mux => 0,
pirq => 15, use90degtxclk => 0)
port map (rstn, gmiii, gmiio, rgmiii, rgmiio, clkm, rstn, apbi, apbo(15));
ethpads : if (CFG_GRETH = 1) generate -- eth pads
etxc_pad : outpad generic map (tech => padtech)
port map (etx_clk, rgmiio_tx_clk);
erx_clk1 : if (use_eth_input_delay_clk = 0) generate
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (erx_clk, rgmiii.rx_clk);
end generate;
erx_clk2 : if (use_eth_input_delay_clk /= 0) generate
erxc_pad : inpad generic map (tech => padtech)
port map (erx_clk, rgmii_pad.rx_clk);
erxc_bufg0 : BUFG port map (O => rgmiii_buf.rx_clk, I => rgmii_pad.rx_clk);
end generate;
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, rgmiii_buf.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, rgmiii_buf.rx_dv);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, rgmiio_txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( etx_en, rgmiio_tx_en);
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, rgmiio.mdio_o, rgmiio.mdio_oe, rgmiii.mdio_i);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, rgmiio.mdc);
emdint_pad : inpad generic map (tech => padtech)
port map (emdint, rgmiii.mdint);
gtx_clk0 : if (use_gtx_clk = 0) generate
-- Use MIG PLL
-- Add to UCF (only if there is no BUFG left):
-- PIN "ethpads.gtx_clk0.clk_125_bufg0.O" CLOCK_DEDICATED_ROUTE = FALSE;
clk_125_bufg0 : BUFG port map (O => clk_125_bufg, I => clk_125);
rgmiii.gtx_clk <= clk_125_bufg;
end generate;
gtx_clk1 : if (use_gtx_clk = 1) generate
-- Incoming 125Mhz ref clock
clk125_pad : clkpad generic map (tech => padtech, arch => 3)
port map (clk125, rgmiii.gtx_clk);
end generate;
gtx_clk2 : if (use_gtx_clk = 2) generate
-- Use Separate PLL
-- Add to UCF (only if there is no BUFG left):
-- PIN "ethpads.gtx_clk2.clkgen0/xc3s.v/bufg0.O" CLOCK_DEDICATED_ROUTE =FALSE;
-- PIN "ethpads.gtx_clk2.clk_125_bufg0.O" CLOCK_DEDICATED_ROUTE = FALSE;
cgi2.pllctrl <= "00"; cgi2.pllrst <= rstraw;
clkgen0 : clkgen -- clock generator
generic map (clktech, 5, 2, CFG_MCTRL_SDEN,CFG_CLK_NOFB, 0, 0, 0, BOARD_FREQ)
port map (clkm, clkm, clk_125_pll, open, open, open, open, cgi2, cgo2, open, open, open);
clk_125_bufg0 : BUFG port map (O => clk_125_bufg, I => clk_125_pll);
rgmiii.gtx_clk <= clk_125_bufg;
end generate;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- Multi-core CAN ---------------------------------------------------
-----------------------------------------------------------------------
can0 : if CFG_CAN = 1 generate
can0 : can_mc generic map (slvndx => 4, ioaddr => CFG_CANIO,
iomask => 16#FF0#, irq => CFG_CANIRQ, memtech => memtech,
ncores => CFG_CAN_NUM, sepirq => CFG_CANSEPIRQ)
port map (rstn, clkm, ahbsi, ahbso(4), can_lrx, can_ltx );
can_tx_pad1 : iopad generic map (tech => padtech)
port map (pio(5), can_ltx(0), gnd, gpioi.din(5));
can_rx_pad1 : iopad generic map (tech => padtech)
port map (pio(4), gnd, vcc, can_lrx(0));
canpas : if CFG_CAN_NUM = 2 generate
can_tx_pad2 : iopad generic map (tech => padtech)
port map (pio(2), can_ltx(1), gnd, gpioi.din(2));
can_rx_pad2 : iopad generic map (tech => padtech)
port map (pio(1), gnd, vcc, can_lrx(1));
end generate;
end generate;
-- standby controlled by pio(3) and pio(0)
-----------------------------------------------------------------------
--- SPACEWIRE -------------------------------------------------------
-----------------------------------------------------------------------
-- temporary, just to make sure the SPW pins are instantiated correctly
no_spw : if CFG_SPW_EN = 0 generate
pad_gen: for i in 0 to CFG_SPW_NUM-1 generate
spw_rxd_pad : inpad_ds generic map (padtech, lvds, x33v)
port map (spw_rxdp(i), spw_rxdn(i), dtmp(i));
spw_rxs_pad : inpad_ds generic map (padtech, lvds, x33v)
port map (spw_rxsp(i), spw_rxsn(i), stmp(i));
spw_txd_pad : outpad_ds generic map (padtech, lvds, x33v)
port map (spw_txdp(i), spw_txdn(i), dtmp(i), gnd);
spw_txs_pad : outpad_ds generic map (padtech, lvds, x33v)
port map (spw_txsp(i), spw_txsn(i), stmp(i), gnd);
end generate;
end generate;
spw : if CFG_SPW_EN > 0 generate
core0: if CFG_SPW_GRSPW = 1 generate
spw_rxtxclk <= clkm;
spw_rstn <= rstn;
end generate;
core1 : if CFG_SPW_GRSPW = 2 generate
spw_rxtxclk <= clk100;
spw_rstn_sync_proc : process(rstn,spw_rxtxclk)
begin
if rstn = '0' then
spw_rstn_sync <= '0';
spw_rstn <= '0';
elsif rising_edge(spw_rxtxclk) then
spw_rstn_sync <= '1';
spw_rstn <= spw_rstn_sync;
end if;
end process spw_rstn_sync_proc;
end generate;
spw_rxclkn <= not spw_rxtxclk;
swloop : for i in 0 to CFG_SPW_NUM-1 generate
-- GRSPW2 PHY
spw2_input : if CFG_SPW_GRSPW = 2 generate
spw_inputloop: for j in 0 to CFG_SPW_PORTS-1 generate
spw_phy0 : grspw2_phy
generic map(
scantest => 0,
tech => fabtech,
input_type => CFG_SPW_INPUT,
rxclkbuftype => 2)
port map(
rstn => spw_rstn,
rxclki => spw_rxtxclk,
rxclkin => spw_rxclkn,
nrxclki => spw_rxtxclk,
di => dtmp(i*CFG_SPW_PORTS+j),
si => stmp(i*CFG_SPW_PORTS+j),
do => spwi(i).d(j*2+1 downto j*2),
dov => spwi(i).dv(j*2+1 downto j*2),
dconnect => spwi(i).dconnect(j*2+1 downto j*2),
rxclko => spw_rxclk(i*CFG_SPW_PORTS+j));
end generate;
oneport : if CFG_SPW_PORTS = 1 generate
spwi(i).d(3 downto 2) <= "00"; -- For second port
spwi(i).dv(3 downto 2) <= "00"; -- For second port
spwi(i).dconnect(3 downto 2) <= "00"; -- For second port
end generate;
spwi(i).nd <= (others => '0'); -- Only used in GRSPW
end generate;
spw1_input: if CFG_SPW_GRSPW = 1 generate
spw_inputloop: for j in 0 to CFG_SPW_PORTS-1 generate
spw_phy0 : grspw_phy
generic map(
tech => fabtech,
rxclkbuftype => 2,
scantest => 0)
port map(
rxrst => spwo(i).rxrst,
di => dtmp(i*CFG_SPW_PORTS+j),
si => stmp(i*CFG_SPW_PORTS+j),
rxclko => spw_rxclk(i*CFG_SPW_PORTS+j),
do => spwi(i).d(j),
ndo => spwi(i).nd(j*5+4 downto j*5),
dconnect => spwi(i).dconnect(j*2+1 downto j*2));
end generate spw_inputloop;
oneport : if CFG_SPW_PORTS = 1 generate
spwi(i).d(1) <= '0'; -- For second port
spwi(i).d(3 downto 2) <= "00"; -- For GRSPW2 second port
spwi(i).nd(9 downto 5) <= "00000"; -- For second port
spwi(i).dconnect(3 downto 2) <= "00"; -- For second port
end generate;
spwi(i).dv <= (others => '0'); -- Only used in GRSPW2
end generate spw1_input;
sw0 : grspwm generic map(tech => memtech,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+i,
sysfreq => CPU_FREQ, usegen => 1,
pindex => 10+i, paddr => 10+i, pirq => 10+i,
nsync => 1, rmap => CFG_SPW_RMAP, rxunaligned => CFG_SPW_RXUNAL,
rmapcrc => CFG_SPW_RMAPCRC, fifosize1 => CFG_SPW_AHBFIFO,
fifosize2 => CFG_SPW_RXFIFO, rxclkbuftype => 2, dmachan => CFG_SPW_DMACHAN,
rmapbufs => CFG_SPW_RMAPBUF, ft => CFG_SPW_FT, ports => CFG_SPW_PORTS,
spwcore => CFG_SPW_GRSPW, netlist => CFG_SPW_NETLIST,
rxtx_sameclk => CFG_SPW_RTSAME, input_type => CFG_SPW_INPUT,
output_type => CFG_SPW_OUTPUT)
port map(rstn, clkm, spw_rxclk(i*CFG_SPW_PORTS), spw_rxclk(i*CFG_SPW_PORTS+1),
spw_rxtxclk, spw_rxtxclk, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+i),
apbi2, apbo2(10+i), spwi(i), spwo(i));
spwi(i).tickin <= '0'; spwi(i).rmapen <= '1';
spwi(i).clkdiv10 <= conv_std_logic_vector(CPU_FREQ/10000-1, 8) when CFG_SPW_GRSPW = 1
else conv_std_logic_vector(10-1, 8);
spwi(i).tickinraw <= '0';
spwi(i).timein <= (others => '0');
spwi(i).dcrstval <= (others => '0');
spwi(i).timerrstval <= (others => '0');
swportloop1: for j in 0 to CFG_SPW_PORTS-1 generate
spwlb0 : if SPW_LOOP_BACK = 1 generate
dtmp(i*CFG_SPW_PORTS+j) <= spwo(i).d(j); stmp(i*CFG_SPW_PORTS+j) <= spwo(i).s(j);
end generate;
nospwlb0 : if SPW_LOOP_BACK = 0 generate
spw_rxd_pad : inpad_ds generic map (padtech, lvds, x33v, 1)
port map (spw_rxdp(i*CFG_SPW_PORTS+j), spw_rxdn(i*CFG_SPW_PORTS+j), dtmp(i*CFG_SPW_PORTS+j));
spw_rxs_pad : inpad_ds generic map (padtech, lvds, x33v, 1)
port map (spw_rxsp(i*CFG_SPW_PORTS+j), spw_rxsn(i*CFG_SPW_PORTS+j), stmp(i*CFG_SPW_PORTS+j));
spw_txd_pad : outpad_ds generic map (padtech, lvds, x33v)
port map (spw_txdp(i*CFG_SPW_PORTS+j), spw_txdn(i*CFG_SPW_PORTS+j), spwo(i).d(j), gnd);
spw_txs_pad : outpad_ds generic map (padtech, lvds, x33v)
port map (spw_txsp(i*CFG_SPW_PORTS+j), spw_txsn(i*CFG_SPW_PORTS+j), spwo(i).s(j), gnd);
end generate;
end generate;
end generate;
end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 GR-XC6S-LX75 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-3.0 | 9df6bc636b0cc5f0aebe0895b47fbbd0 | 0.552033 | 3.427853 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/ddr/ahb2avl_async_be.vhd | 1 | 10,981 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahb2avl_async_be
-- File: ahb2avl_async_be.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Avalon clock domain part of ahb2avl_async
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.ddrpkg.all;
use gaisler.ddrintpkg.all;
entity ahb2avl_async_be is
generic (
avldbits : integer := 32;
avlabits : integer := 20;
ahbbits : integer := ahbdw;
burstlen : integer := 8;
nosync : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
avlsi : out ddravl_slv_in_type;
avlso : in ddravl_slv_out_type;
request: in ddr_request_type;
start_tog: in std_ulogic;
response: out ddr_response_type;
wbraddr : out std_logic_vector(log2((32*burstlen)/avldbits) downto 0);
wbrdata : in std_logic_vector(avldbits-1 downto 0);
rbwaddr : out std_logic_vector(log2((32*burstlen)/avldbits)-1 downto 0);
rbwdata : out std_logic_vector(avldbits-1 downto 0);
rbwrite : out std_logic
);
end;
architecture rtl of ahb2avl_async_be is
constant avlbl: integer := (burstlen*32) / avldbits;
constant onev: std_logic_vector(15 downto 0) := (others => '1');
type be_state is (idle,acc1,acc2,rdwait);
type be_regs is record
req1,req2 : ddr_request_type;
start1,start2: std_ulogic;
resp: ddr_response_type;
s: be_state;
ramaddr: std_logic_vector(log2(avlbl)-1 downto 0);
beginburst: std_ulogic;
wr: std_ulogic;
rd: std_ulogic;
reading: std_ulogic;
rdata_valid_prev: std_ulogic;
wmaskmode: std_ulogic;
rstarted: std_ulogic;
end record;
signal r,nr: be_regs;
begin
comb: process(r,rst,request,start_tog,avlso,wbrdata)
variable v: be_regs;
variable vstart: std_logic;
variable vreq: ddr_request_type;
variable startmask,endmask,mask,mask16,mask8: std_logic_vector(avldbits/8-1 downto 0);
variable ad32: std_logic_vector(3 downto 2);
variable nwmaskmode: std_ulogic;
variable rbw: std_ulogic;
variable slvi: ddravl_slv_in_type;
variable rddone: std_ulogic;
variable inc_ramaddr: std_ulogic;
variable aendaddr: std_logic_vector(9 downto 0);
begin
v := r;
slvi := ddravl_slv_in_none;
slvi.burstbegin := r.beginburst;
slvi.addr(avlabits-1 downto log2(avlbl)) :=
vreq.startaddr(avlabits-1-log2(avlbl)+log2(burstlen*4) downto log2(burstlen*4));
slvi.addr(log2(avlbl)-1 downto 0) := r.ramaddr;
slvi.wdata(avldbits-1 downto 0) := wbrdata;
slvi.write_req := r.wr;
slvi.size := std_logic_vector(to_unsigned(avlbl, slvi.size'length));
-- fix for accesses wider than 32-b word
aendaddr := request.endaddr; --(log2(4*burstlen)-1 downto 2);
if request.hsize(1 downto 0)="11" and request.hio='0' then
aendaddr(2):='1';
end if;
if ahbbits > 64 and request.hsize(2)='1' then
aendaddr(3 downto 2) := "11";
if ahbbits > 128 and request.hsize(0)='1' then
aendaddr(4) := '1';
end if;
end if;
v.req1 := request;
v.req1.endaddr := aendaddr;
v.req2 := r.req1;
v.start1 := start_tog;
v.start2 := r.start1;
vstart:=r.start2; vreq:=r.req2;
if nosync /= 0 then vstart:=start_tog; vreq:=r.req1; end if;
startmask := (others => '1'); endmask := (others => '1');
mask16 := (others => '1'); mask8 := (others => '1');
case avldbits is
when 32 =>
if vreq.startaddr(1)='0' then mask16:="1100"; else mask16:="0011"; end if;
if vreq.startaddr(0)='0' then mask8:="1010"; else mask8:="0101"; end if;
when 64 =>
if vreq.startaddr(2)='0' then startmask:="11111111";
else startmask:="00001111";
end if;
if vreq.endaddr(2)='0' then endmask:="11110000";
else endmask:="11111111";
end if;
if vreq.startaddr(1)='0' then mask16:="11001100"; else mask16:="00110011"; end if;
if vreq.startaddr(0)='0' then mask8:="10101010"; else mask8:="01010101"; end if;
when 128 =>
ad32 := vreq.startaddr(3 downto 2);
case ad32 is
when "00" => startmask:="1111111111111111";
when "01" => startmask:="0000111111111111";
when "10" => startmask:="0000000011111111";
when others => startmask:="0000000000001111";
end case;
ad32 := vreq.endaddr(3 downto 2);
case ad32 is
when "00" => endmask:="1111000000000000";
when "01" => endmask:="1111111100000000";
when "10" => endmask:="1111111111110000";
when others => endmask:="1111111111111111";
end case;
if vreq.startaddr(1)='0' then mask16:="1100110011001100"; else mask16:="0011001100110011"; end if;
if vreq.startaddr(0)='0' then mask8:="1010101010101010"; else mask8:="0101010101010101"; end if;
when 256 =>
case vreq.startaddr(4 downto 2) is
when "000" => startmask:="11111111111111111111111111111111";
when "001" => startmask:="00001111111111111111111111111111";
when "010" => startmask:="00000000111111111111111111111111";
when "011" => startmask:="00000000000011111111111111111111";
when "100" => startmask:="00000000000000001111111111111111";
when "101" => startmask:="00000000000000000000111111111111";
when "110" => startmask:="00000000000000000000000011111111";
when others => startmask:="00000000000000000000000000001111";
end case;
case vreq.endaddr(4 downto 2) is
when "000" => endmask:="11110000000000000000000000000000";
when "001" => endmask:="11111111000000000000000000000000";
when "010" => endmask:="11111111111100000000000000000000";
when "011" => endmask:="11111111111111110000000000000000";
when "100" => endmask:="11111111111111111111000000000000";
when "101" => endmask:="11111111111111111111111100000000";
when "110" => endmask:="11111111111111111111111111110000";
when others => endmask:="11111111111111111111111111111111";
end case;
if vreq.startaddr(1)='0' then mask16:="11001100110011001100110011001100"; else mask16:="00110011001100110011001100110011"; end if;
if vreq.startaddr(0)='0' then mask8:="10101010101010101010101010101010"; else mask8:="01010101010101010101010101010101"; end if;
when others =>
--pragma translate_off
assert false report "Unsupported data bus width" severity failure;
--pragma translate_on
end case;
mask := (others => r.wmaskmode);
nwmaskmode := r.wmaskmode;
if r.wmaskmode='0' then
if r.ramaddr=vreq.startaddr(log2(burstlen*4)-1 downto log2(avldbits/8)) then
mask := startmask;
nwmaskmode:='1';
if r.reading='1' then v.rstarted := '1'; end if;
end if;
end if;
if r.ramaddr=vreq.endaddr(log2(burstlen*4)-1 downto log2(avldbits/8)) then
mask := mask and endmask;
nwmaskmode:='0';
end if;
if vreq.hsize(2 downto 1)="00" then
mask := mask and mask16;
if vreq.hsize(0)='0' then
mask := mask and mask8;
end if;
end if;
rddone := '0';
inc_ramaddr := '0';
rbw := '0';
if r.reading /= '0' then
if avlso.rdata_valid='1' then
rbw := '1';
inc_ramaddr := '1';
if v.rstarted='1' then
v.resp.rctr_gray(log2(avlbl)-1 downto 0) := nextgray(r.resp.rctr_gray(log2(avlbl)-1 downto 0));
end if;
if r.ramaddr=(r.ramaddr'range => '1') then
rddone:='1';
end if;
end if;
else
v.resp.rctr_gray := (others => '0');
end if;
v.beginburst := '0';
case r.s is
when idle =>
if vstart /= r.resp.done_tog then
v.s := acc1;
v.beginburst := '1';
end if;
v.reading := '0';
v.rstarted := '0';
v.wmaskmode := '0';
v.rd := '0';
v.wr := '0';
when acc1 =>
v.wr := vreq.hwrite;
v.rd := not vreq.hwrite;
v.reading := not vreq.hwrite;
if vreq.hwrite='1' then
slvi.write_req := '1';
end if;
if vreq.hwrite/='0' then
v.s := acc2;
end if;
if vreq.hwrite='0' and avlso.ready='1' then
v.s := rdwait;
end if;
if vreq.hwrite = '0' then
mask := (others => '1');
end if;
if avlso.ready='1' and vreq.hwrite/='0' then
inc_ramaddr := '1';
end if;
when acc2 =>
if avlso.ready='1' then
inc_ramaddr := '1';
if r.ramaddr=onev(r.ramaddr'length-1 downto 0) then
v.wr := '0';
v.resp.done_tog := not r.resp.done_tog;
v.s := idle;
end if;
end if;
when rdwait =>
v.rd := '0';
if rddone='1' then
v.resp.done_tog := not r.resp.done_tog;
v.s := idle;
end if;
end case;
if inc_ramaddr/='0' then
v.ramaddr := std_logic_vector(unsigned(r.ramaddr)+1);
v.wmaskmode := nwmaskmode;
end if;
if v.s=idle then
v.ramaddr := (others => '0');
end if;
slvi.read_req := v.rd;
slvi.be(avldbits/8-1 downto 0) := mask;
if rst='0' then
v.s := idle;
v.resp := ddr_response_none;
end if;
nr <= v;
response <= r.resp;
wbraddr <= r.resp.done_tog & v.ramaddr;
rbwaddr <= r.ramaddr;
rbwdata <= avlso.rdata(avldbits-1 downto 0);
rbwrite <= rbw;
avlsi <= slvi;
end process;
regs: process(clk)
begin
if rising_edge(clk) then
r <= nr;
end if;
end process;
end;
| gpl-3.0 | 9671380d200faaf698ff6ce7340f8a36 | 0.583462 | 3.747782 | false | false | false | false |
yishinli/emc2 | src/hal/drivers/m5i20/hostmot5_src/hostmot5-4e.vhd | 1 | 25,099 | library IEEE;
use IEEE.std_logic_1164.all; -- defines std_logic types
-- 4 axis version with 48 I/O bits
entity HostMot5_4 is
port
(
LRD: in STD_LOGIC;
LWR: in STD_LOGIC;
LW_R: in STD_LOGIC;
ALE: in STD_LOGIC;
ADS: in STD_LOGIC;
BLAST: in STD_LOGIC;
WAITO: in STD_LOGIC;
LOCKO: in STD_LOGIC;
CS0: in STD_LOGIC;
CS1: in STD_LOGIC;
READY: out STD_LOGIC;
INT: out STD_LOGIC;
LAD: inout STD_LOGIC_VECTOR (31 downto 0); -- data/address bus
LA: in STD_LOGIC_VECTOR (8 downto 2); -- non-muxed address bus
lBE: in STD_LOGIC_VECTOR (3 downto 0); -- byte enables
SYNCLK: in STD_LOGIC;
LCLK: in STD_LOGIC;
-- I/O signals
A: in STD_LOGIC_VECTOR (3 downto 0);
B: in STD_LOGIC_VECTOR (3 downto 0);
IDX: in STD_LOGIC_VECTOR (3 downto 0);
PWM: inout STD_LOGIC_VECTOR (3 downto 0);
ENA: out STD_LOGIC_VECTOR (3 downto 0);
DIR: inout STD_LOGIC_VECTOR (3 downto 0);
IOBITSA: inout STD_LOGIC_VECTOR (23 downto 0);
IOBITSB: inout STD_LOGIC_VECTOR (23 downto 0);
-- led bits
LEDS: out STD_LOGIC_VECTOR(7 downto 0)
);
end HostMot5_4; -- for 5I20 or 4I65
architecture dataflow of Hostmot5_4 is
alias BLE: STD_LOGIC is LBE(0); -- 16 bit mode
alias BHE: STD_LOGIC is LBE(3); -- 16 bit mode
alias LA1: STD_LOGIC is LBE(1); -- 8/16 bit mode
alias LA0: STD_LOGIC is LBE(0); -- 8 bit mode
-- misc global signals --
signal D: STD_LOGIC_VECTOR (31 downto 0); -- internal data bus
signal LatchedA: STD_LOGIC_VECTOR (15 downto 0);
signal LatchedLBE: STD_LOGIC_VECTOR (3 downto 0);
signal PreFastRead: STD_LOGIC;
signal FastRead: STD_LOGIC;
-- Version specific constants --
constant counters :integer := 4;
constant HMID : STD_LOGIC_VECTOR (31 downto 0) := x"AA010004"; -- MSW = rev 1, LSW = 4 axis
constant MasterClock : STD_LOGIC_VECTOR (31 downto 0) := x"01FCA055"; -- = 33.3333 MHz
-- misc global signals --
signal CardSelect: STD_LOGIC; -- card select decode
signal LEDView: STD_LOGIC_VECTOR (7 downto 0); -- index register
-- irq related signals
signal IRQSource: STD_LOGIC;
signal IRQLatch: STD_LOGIC;
signal IRQMask: STD_LOGIC;
signal MissedIRQ: STD_LOGIC;
signal StopOnMissedIRQ: STD_LOGIC;
signal ClearMissedIRQ: STD_LOGIC;
signal LatchOnInterrupt: STD_LOGIC;
-- timeout related signals
signal ReloadWDCmd: STD_LOGIC;
signal StopOnTimeout: STD_LOGIC;
signal WDTimeOut: STD_LOGIC;
-- LEDView and id reg signals
signal LoadLEDViewCmd: STD_LOGIC;
signal ReadLEDViewCmd: STD_LOGIC;
signal Enasigs :STD_LOGIC_VECTOR (counters-1 downto 0);
signal IDSel: STD_LOGIC;
signal ReadIDCmd: STD_LOGIC;
signal MCSel: STD_LOGIC;
signal ReadMCCmd: STD_LOGIC;
-- irqdiv reg signals
signal ReadIRQDivCmd: STD_LOGIC;
signal LoadIRQDivCmd: STD_LOGIC;
signal ClearIRQCmd: STD_LOGIC;
-- irq sel reg signals
signal loadGCRCmd: STD_LOGIC;
signal LoadGMRCmd: STD_LOGIC;
signal ReadGMRCmd: STD_LOGIC;
-- timeout reg signals
signal loadTimeoutCmd: STD_LOGIC;
signal ReadTimeoutCmd: STD_LOGIC;
signal ReadTimerCmd: STD_LOGIC;
-- phase accumulator signals
signal ReadPhaseCmd: STD_LOGIC;
signal LoadPhaseCmd: STD_LOGIC;
-- counter signals --
signal CounterRead: STD_LOGIC_VECTOR (counters-1 downto 0); -- read counter
signal GlobalCounterEnable: STD_LOGIC; -- enable counting
signal GlobalCountLatchcmd: STD_LOGIC; -- command to latch counter value
signal GlobalCountLatch: STD_LOGIC; -- command + irq generated latch count
signal CountLatchEdge1: STD_LOGIC;
signal CountLatchEdge2: STD_LOGIC;
signal CCRLoadCmds: STD_LOGIC_VECTOR (counters-1 downto 0); -- counter control reg loads
signal CCRReadCmds: STD_LOGIC_VECTOR (counters-1 downto 0); -- counter control reg reads
signal GlobalCounterClear: STD_LOGIC; -- clear counter
-- secondary counter signals --
signal SCounterRead: STD_LOGIC_VECTOR (counters-1 downto 0); -- read counter
signal SCCRLoadCmds: STD_LOGIC_VECTOR (counters-1 downto 0); -- counter control reg loads
signal SCCRReadCmds: STD_LOGIC_VECTOR (counters-1 downto 0); -- counter control reg reads
-- pwm generator signals --
signal RefCountBus: STD_LOGIC_VECTOR (9 downto 0);
signal LoadPWM: STD_LOGIC_VECTOR (counters-1 downto 0);
signal ReadPWM: STD_LOGIC_VECTOR (counters-1 downto 0);
signal PCRLoadCmds: STD_LOGIC_VECTOR (counters-1 downto 0);
signal PCRReadCmds: STD_LOGIC_VECTOR (counters-1 downto 0);
signal GlobalPWMEnable: STD_LOGIC;
signal GlobalClearPWM: STD_LOGIC;
signal GlobalClearPWMCmd: STD_LOGIC;
signal StopPWM: STD_LOGIC;
-- misc i/o signals
signal PortASel: STD_LOGIC;
signal DDRASel: STD_LOGIC;
signal LoadPortA: STD_LOGIC;
signal LoadDDRA: STD_LOGIC;
signal ReadDDRA: STD_LOGIC;
signal ReadPortA: STD_LOGIC;
signal PortBSel: STD_LOGIC;
signal DDRBSel: STD_LOGIC;
signal LoadPortB: STD_LOGIC;
signal LoadDDRB: STD_LOGIC;
signal ReadDDRB: STD_LOGIC;
signal ReadPortB: STD_LOGIC;
-- decodes --
signal LEDViewSel: STD_LOGIC;
signal IndexSel: STD_LOGIC;
signal GCRSel: STD_LOGIC;
signal GMRSel: STD_LOGIC;
signal CCRSel: STD_LOGIC;
signal SCCRSel: STD_LOGIC;
signal PCRSel: STD_LOGIC;
signal TimeOutSel: STD_LOGIC;
signal TimerSel: STD_LOGIC;
signal IRQDIVSel: STD_LOGIC;
signal PWMValSel: STD_LOGIC;
signal PhaseSel: STD_LOGIC;
signal CounterSel: STD_LOGIC;
signal SCounterSel: STD_LOGIC;
function OneOfFourDecode(ena : std_logic; dec : std_logic_vector(1 downto 0)) return std_logic_vector is
variable result : std_logic_vector(counters-1 downto 0);
begin
if ena = '1' then
case dec is
when "00" => result := "0001";
when "01" => result := "0010";
when "10" => result := "0100";
when "11" => result := "1000";
when others => result := "0000";
end case;
else
result := "0000";
end if;
return result;
end OneOfFourDecode;
function OneOfFourMux(sel: std_logic_vector (1 downto 0); input: std_logic_vector(counters-1 downto 0)) return std_logic is
variable result : std_logic;
begin
case sel is
when "00" => result := input(0);
when "01" => result := input(1);
when "10" => result := input(2);
when "11" => result := input(3);
when others => result := '0';
end case;
return result;
end OneOfFourMux;
component indexreg
port (
clk: in STD_LOGIC;
ibus: in STD_LOGIC_VECTOR (15 downto 0);
obus: out STD_LOGIC_VECTOR (15 downto 0);
loadindex: in STD_LOGIC;
readindex: in STD_LOGIC;
index: out STD_LOGIC_VECTOR (7 downto 0)
);
end component;
component counter
port (
obus: out STD_LOGIC_VECTOR (31 downto 0);
ibus: in STD_LOGIC_VECTOR (31 downto 0);
quada: in STD_LOGIC;
quadb: in STD_LOGIC;
index: in STD_LOGIC;
ccrloadcmd: in STD_LOGIC;
ccrreadcmd: in STD_LOGIC;
countoutreadcmd: in STD_LOGIC;
countlatchcmd: in STD_LOGIC;
countclearcmd: in STD_LOGIC;
countenable: in STD_LOGIC;
indexmask: in STD_LOGIC;
nads: in STD_LOGIC;
clk: in STD_LOGIC
);
end component;
component pwmgen
port (
clk: in STD_LOGIC;
refcount: in STD_LOGIC_VECTOR (9 downto 0);
ibus: in STD_LOGIC_VECTOR (15 downto 0);
obus: out STD_LOGIC_VECTOR (15 downto 0);
loadpwmval: in STD_LOGIC;
readpwmval: in STD_LOGIC;
clearpwmval: in STD_LOGIC;
pcrloadcmd: STD_LOGIC;
pcrreadcmd: STD_LOGIC;
pwmout: out STD_LOGIC;
dirio: inout STD_LOGIC;
enablein: in STD_LOGIC;
enableout: out STD_LOGIC
);
end component pwmgen;
component pwmref is
port (
clk: in STD_LOGIC;
refcount: out STD_LOGIC_VECTOR (9 downto 0);
irqgen: out STD_LOGIC;
ibus: in STD_LOGIC_VECTOR (15 downto 0);
obus: out STD_LOGIC_VECTOR (15 downto 0);
irqdivload: in STD_LOGIC;
irqdivread: in STD_LOGIC;
phaseload: in STD_LOGIC;
phaseread: in STD_LOGIC
);
end component pwmref;
component globalcontrolreg is
port (
clk: in STD_LOGIC;
ibus: in STD_LOGIC_VECTOR (15 downto 0);
reset: in STD_LOGIC;
loadgcr: in STD_LOGIC;
ctrclear: out STD_LOGIC;
ctrlatch: out STD_LOGIC;
pwmclear: out STD_LOGIC;
irqclear: out STD_LOGIC;
reloadwd: out STD_LOGIC
);
end component globalcontrolreg;
component globalmodereg is
port (
clk: in STD_LOGIC;
ibus: in STD_LOGIC_VECTOR (15 downto 0);
obus: out STD_LOGIC_VECTOR (15 downto 0);
reset: in STD_LOGIC;
loadglobalmode: in STD_LOGIC;
readglobalmode: in STD_LOGIC;
ctrena: out STD_LOGIC;
pwmena: out STD_LOGIC;
clearpwmena: in STD_LOGIC;
loi: out STD_LOGIC;
som: out STD_LOGIC;
sot: out STD_LOGIC;
miout: out STD_LOGIC;
miin: in STD_LOGIC;
irqmask: out STD_LOGIC;
irqstatus: in STD_LOGIC
);
end component globalmodereg;
component WordPR24 is
port (
clear: in STD_LOGIC;
clk: in STD_LOGIC;
ibus: in STD_LOGIC_VECTOR (23 downto 0);
obus: out STD_LOGIC_VECTOR (23 downto 0);
loadport: in STD_LOGIC;
loadddr: in STD_LOGIC;
readddr: in STD_LOGIC;
portdata: out STD_LOGIC_VECTOR (23 downto 0)
);
end component WordPR24;
component Word24RB is
Port (
obus: out STD_LOGIC_VECTOR (23 downto 0);
readport: in STD_LOGIC;
portdata: in STD_LOGIC_VECTOR (23 downto 0) );
end component Word24RB;
component Timeout is
Port ( clk : in std_logic;
ibus : in std_logic_vector(15 downto 0);
obus : out std_logic_vector(15 downto 0);
timeoutload : in std_logic;
timeoutread : in std_logic;
timerread : in std_logic;
reload : in std_logic;
timerz : out std_logic);
end component Timeout;
component idreadback is
Generic ( id : std_logic_vector(31 downto 0);
mc : std_logic_vector(31 downto 0));
Port ( readid : in std_logic;
readmc : in std_logic;
obus : out std_logic_vector(31 downto 0));
end component idreadback;
begin
makecounters: for i in 0 to (counters -1) generate
counterx: counter port map (
obus => D,
ibus => LAD,
quada => A(i),
quadb => B(i),
index => Idx(i),
ccrloadcmd => CCRLoadCmds(i),
ccrreadcmd => CCRReadCmds(i),
countoutreadcmd => CounterRead(i),
countlatchcmd => GlobalCountLatch,
countclearcmd => GlobalCounterClear,
countenable => GlobalCounterEnable,
indexmask => IOBITSA(16 + i),
nads => ADS,
clk => LClk
);
end generate;
makescounters: for i in 0 to (counters -1) generate
counterx: counter port map (
obus => D,
ibus => LAD,
quada => IOBITSA((i*4)),
quadb => IOBITSA((i*4)+1),
index => IOBITSA((i*4)+2),
ccrloadcmd => SCCRLoadCmds(i),
ccrreadcmd => SCCRReadCmds(i),
countoutreadcmd => SCounterRead(i),
countlatchcmd => GlobalCountLatch,
countclearcmd => GlobalCounterClear,
countenable => GlobalCounterEnable,
indexmask => IOBITSA((i*4) +3),
nads => ADS,
clk => LClk
);
end generate;
makepwmgen: for i in 0 to (counters -1) generate
pwmgenx: pwmgen port map (
clk => LClk,
refcount => RefCountBus,
ibus => LAD(15 downto 0),
obus => D(15 downto 0),
loadpwmval => LoadPWM(i),
readpwmval => ReadPWM(i),
clearpwmval => GlobalClearPWM,
pcrloadcmd => PCRLoadCmds(i),
pcrreadcmd => PCRReadCmds(i),
pwmout => PWM(i),
dirio => Dir(i),
enablein => GlobalPWMEnable,
enableout =>EnaSigs(i)
);
end generate;
oporta: WordPR24 port map (
clear => '0',
clk => LClk,
ibus => LAD(23 downto 0),
obus => D(23 downto 0),
loadport => LoadPortA,
loadddr => LoadDDRA,
readddr => ReadDDRA,
portdata => IOBITSA
);
iporta: Word24RB port map (
obus => D(23 downto 0),
readport => ReadPortA,
portdata => IOBITSA
);
oportb: WordPR24 port map (
clear => '0',
clk => LClk,
ibus => LAD(23 downto 0),
obus => D(23 downto 0),
loadport => LoadPortB,
loadddr => LoadDDRB,
readddr => ReadDDRB,
portdata => IOBITSB
);
iportb: Word24RB port map (
obus => D(23 downto 0),
readport => ReadPortB,
portdata => IOBitsB
);
pwmrefcount: pwmref port map (
clk => LClk,
refcount => RefCountBus,
irqgen => IRQSource,
ibus => LAD(15 downto 0),
obus => D(15 downto 0),
irqdivload => LoadIRQDivCmd,
irqdivread => ReadIRQDivCmd,
phaseload => LoadPhaseCmd,
phaseread => ReadPhaseCmd
);
gLedreg: indexreg port map (
clk => LClk,
ibus => LAD(15 downto 0),
obus => D(15 downto 0),
loadindex => LoadLEDViewCmd,
readindex => ReadLEDViewCmd,
index => LEDView
);
ggcontrolreg: globalcontrolreg port map (
clk => LClk,
ibus => LAD(15 downto 0),
reset => '0',
loadgcr => LoadGCRCmd,
ctrclear => GlobalCounterClear,
ctrlatch => GlobalCountLatchCmd,
pwmclear => GlobalClearPWMCmd,
irqclear => ClearIRQCmd,
reloadwd => ReloadWDCmd
);
gglobalmodereg: globalmodereg port map (
clk => LClk,
ibus => LAD(15 downto 0),
obus => D(15 downto 0),
reset => '0',
loadglobalmode => loadGMRCmd,
readglobalmode => ReadGMRCmd,
ctrena => GlobalCounterEnable,
pwmena => GlobalPWMEnable,
clearpwmena => StopPWM,
loi => LatchOnInterrupt,
som => StopOnMissedIRQ,
sot => StopOnTimeout,
miout => ClearMissedIRQ,
miin => MissedIRQ,
irqmask => IRQMask,
irqstatus => IRQLatch
);
atimeout: timeout port map (
clk => LClk,
ibus => LAD(15 downto 0),
obus => D(15 downto 0),
timeoutload => loadTimeOutCmd,
timeoutread => ReadTimeOutCmd,
timerread => ReadTimerCmd,
reload => ReLoadWDCmd,
timerz => WDTimeout
);
aidreadback: idreadback
generic map (
id => HMID,
mc => MasterClock
)
port map(
readid => ReadIDCmd,
readmc => ReadMCCmd,
obus => D
);
LADDrivers: process (D,FastRead)
begin
if FastRead ='1' then
LAD <= D;
else
LAD <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
end if;
end process LADDrivers;
AddressLatch: process (lclk)
begin
if lclk'event and LClk = '1' then
if ADS = '0' then
LatchedA <= LAD(15 downto 0);
LatchedLBE <= LBE;
end if;
end if;
end process AddressLatch;
-- we generate an early read from ADS and LR_W
-- since the 10 nS LRD delay and 5 nS setup time
-- only give us 15 nS to provide data to the PLX chip
MakeFastRead: process (lclk,PreFastread,LRD)
begin
if lclk'event and LClk = '1' then
if ADS = '0' and LW_R = '0'then
PreFastRead <= '1';
else
PreFastRead <= '0';
end if;
end if;
FastRead <= PreFastRead or (not LRD);
end process MakeFastRead;
Decode: process (LatchedA)
begin
if LatchedA(7 downto 5) = "000" then -- 32 bit access
CounterSel <= '1';
else
CounterSel <= '0';
end if;
if LatchedA(7 downto 5) = "001" then -- 32 bit access
SCounterSel <= '1';
else
SCounterSel <= '0';
end if;
if LatchedA(7 downto 4) = "0100" then -- 16 bit access
CCRSel <= '1';
else
CCRSel <= '0';
end if;
if LatchedA(7 downto 4) = "0101" then -- 16 bit access
SCCRSel <= '1';
else
SCCRSel <= '0';
end if;
if LatchedA(7 downto 5) = "011" then -- 16 bit access
PWMValSel <= '1';
else
PWMValSel <= '0';
end if;
if LatchedA(7 downto 5) = "100" then -- 16 bit access
PCRSel <= '1';
else
PCRSel <= '0';
end if;
if LatchedA(7 downto 2) = "101000" then -- 32 bit access
PortASel <= '1';
else
PortASel <= '0';
end if;
if LatchedA(7 downto 2) = "101001" then -- 32 bit access
DDRASel <= '1';
else
DDRASel <= '0';
end if;
if LatchedA(7 downto 2) = "101010" then -- 32 bit access
PortBSel <= '1';
else
PortBSel <= '0';
end if;
if LatchedA(7 downto 2) = "101011" then -- 32 bit access
DDRBSel <= '1';
else
DDRBSel <= '0';
end if;
if LatchedA(7 downto 2) = "110100" then -- 32 bit access D0
IDSel <= '1';
else
IDSel <= '0';
end if;
if LatchedA(7 downto 2) = "110101" then -- 32 bit access D4
MCSel <= '1';
else
MCSel <= '0';
end if;
if LatchedA(7 downto 1) = "1100000" then -- 16 bit access
GCRSel <= '1';
else
GCRSel <= '0';
end if;
if LatchedA(7 downto 1) = "1100001" then -- 16 bit access
GMRSel <= '1';
else
GMRSel <= '0';
end if;
if LatchedA(7 downto 1) = "1100010"then -- 16 bit access
IRQDivSel <= '1';
else
IRQDivSel <= '0';
end if;
if LatchedA(7 downto 1) = "1100011"then -- 16 bit access
PhaseSel <= '1';
else
PhaseSel <= '0';
end if;
if LatchedA(7 downto 1) = "1100100" then -- 16 bit access
TimeOutSel <= '1';
else
TimeOutSel <= '0';
end if;
if LatchedA(7 downto 1) = "1100101" then -- 16 bit access
TimerSel <= '1';
else
TimerSel <= '0';
end if;
if LatchedA(7 downto 1) = "1100110" then -- 16 bit access
LEDViewSel <= '1';
else
LEDViewSel <= '0';
end if;
end process;
SigsOut: process (EnaSigs)
begin
Ena <= EnaSigs;
end process;
CounterDecode: process (CounterSel, Fastread, LatchedA)
begin
if FastRead = '1' then
CounterRead <= OneOfFourDecode(CounterSel,LatchedA(3 downto 2));
else
CounterRead <= (others => '0');
end if;
end process;
SCounterDecode: process (SCounterSel, Fastread, LatchedA)
begin
if FastRead = '1' then
SCounterRead <= OneOfFourDecode(SCounterSel,LatchedA(3 downto 2));
else
SCounterRead <= (others => '0');
end if;
end process;
CCRegs: process (CCRSel, FastRead, LWR, LatchedA)
begin
if FastRead = '1' then
CCRReadCmds <= OneOfFourDecode(CCRSel,LatchedA(2 downto 1));
else
CCRReadCmds <= (others => '0');
end if;
if LWR = '0' then
CCRLoadCmds <= OneOfFourDecode(CCRSel,LatchedA(2 downto 1));
else
CCRLoadCmds <= (others => '0');
end if;
end process;
SCCRegs: process (SCCRSel, FastRead, LWR, LatchedA)
begin
if FastRead = '1' then
SCCRReadCmds <= OneOfFourDecode(SCCRSel,LatchedA(2 downto 1));
else
SCCRReadCmds <= (others => '0');
end if;
if LWR = '0' then
SCCRLoadCmds <= OneOfFourDecode(SCCRSel,LatchedA(2 downto 1));
else
SCCRLoadCmds <= (others => '0');
end if;
end process;
PWMdecode: process (PWMValSel,Fastread, LWR, LatchedA)
begin
if FastRead = '1' then
ReadPWM <= OneOfFourDecode(PWMValSel,LatchedA(2 downto 1));
else
ReadPWM <= (others => '0');
end if;
if LWR = '0' then
LoadPWM <= OneOfFourDecode(PWMValSel,LatchedA(2 downto 1));
else
LoadPWM <= (others => '0');
end if;
end process;
PCRegs: process (PCRSel,Fastread, LWR, LatchedA)
begin
if FastRead = '1' then
PCRReadCmds <= OneOfFourDecode(PCRSel,LatchedA(2 downto 1));
else
PCRReadCmds <= (others => '0');
end if;
if LWR = '0' then
PCRLoadCmds <= OneOfFourDecode(PCRSel,LatchedA(2 downto 1));
else
PCRLoadCmds <= (others => '0');
end if;
end process;
PortADecode: process (PortASel,FastRead,LWR)
begin
if PortASel = '1' and LWR = '0' then
LoadPortA <= '1';
else
LoadPortA <= '0';
end if;
if PortASel = '1' and FastRead = '1' then
ReadPortA <= '1';
else
ReadPortA <= '0';
end if;
end process PortADecode;
DDRADecode: process (DDRASel,FastRead,LWR)
begin
if DDRASel = '1' and LWR = '0' then
LoadDDRA <= '1';
else
LoadDDRA <= '0';
end if;
if DDRASel = '1' and FastRead = '1' then
ReadDDRA <= '1';
else
ReadDDRA <= '0';
end if;
end process DDRADecode;
PortBDecode: process (PortBSel,FastRead,LWR)
begin
if PortBSel = '1' and LWR = '0' then
LoadPortB <= '1';
else
LoadPortB <= '0';
end if;
if PortBSel = '1' and FastRead = '1' then
ReadPortB <= '1';
else
ReadPortB <= '0';
end if;
end process PortBDecode;
DDRBDecode: process (DDRBSel,FastRead,LWR)
begin
if DDRBSel = '1' and LWR = '0' then
LoadDDRB <= '1';
else
LoadDDRB <= '0';
end if;
if DDRBSel = '1' and FastRead = '1' then
ReadDDRB <= '1';
else
ReadDDRB <= '0';
end if;
end process DDRBDecode;
GCRDecode: process (GCRSel,LWR)
begin
if GCRSel = '1' and LWR = '0' then
LoadGCRCmd <= '1';
else
LoadGCRCmd <= '0';
end if;
end process GCRDecode;
GMRDecode: process (GMRSel,FastRead,LWR)
begin
if GMRSel = '1' and LWR = '0' then
LoadGMRCmd <= '1';
else
LoadGMRCmd <= '0';
end if;
if GMRSel = '1' and FastRead = '1' then
ReadGMRCmd <= '1';
else
ReadGMRCmd <= '0';
end if;
end process GMRDecode;
TimeOutDecode: process (TimeOutSel,FastRead,LWR)
begin
if TimeoutSel = '1' and LWR = '0' then
LoadTimeOutCmd <= '1';
else
LoadTimeOutCmd <= '0';
end if;
if TimeOutSel = '1' and FastRead = '1' then
ReadTimeOutCmd <= '1';
else
ReadTimeOutCmd <= '0';
end if;
end process TimeOutDecode;
TimerDecode: process (TimerSel,FastRead,LWR)
begin
if TimerSel = '1' and FastRead = '1' then
ReadTimerCmd <= '1';
else
ReadTimerCmd <= '0';
end if;
end process TimerDecode;
LEDViewDecode: process (LedViewSel,FastRead,LWR)
begin
if LEDViewSel = '1' and LWR = '0' then
LoadLEDViewCmd <= '1';
else
LoadLEDViewCmd <= '0';
end if;
if LEDViewSel = '1' and FastRead= '1' then
ReadLEDViewCmd <= '1';
else
ReadLEDViewCmd <= '0';
end if;
end process LEDViewDecode;
IRQDivDecode: process (IRQDivSel,FastRead,LWR)
begin
if IRQDivSel = '1' and LWR = '0' then
LoadIRQDivCmd <= '1';
else
LoadIRQDivCmd <= '0';
end if;
if IRQDivSel = '1' and FastRead = '1' then
ReadIRQDivCmd <= '1';
else
ReadIRQDivCmd <= '0';
end if;
end process IrqDivDecode;
PhaseDecode: process (PhaseSel,FastRead,LWR)
begin
if PhaseSel = '1' and LWR = '0' then
LoadPhaseCmd <= '1';
else
LoadPhaseCmd <= '0';
end if;
if PhaseSel = '1' and FastRead = '1' then
ReadPhaseCmd <= '1';
else
ReadPhaseCmd <= '0';
end if;
end process PhaseDecode;
IDDecode: process (IDSel,FastRead)
begin
if IDSel = '1' and FastRead = '1' then
ReadIDCmd <= '1';
else
ReadIDCmd <= '0';
end if;
end process IDDecode;
MCDecode: process (MCSel,FastRead)
begin
if MCSel = '1' and FastRead = '1' then
ReadMCCmd <= '1';
else
ReadMCCmd <= '0';
end if;
end process MCDecode;
irqlogic: process (CardSelect,
IRQSource,
IrqLatch,
ClearMissedIRQ,
MissedIRQ,
StopOnMissedIRQ,
LatchOnInterrupt,
GlobalCountLatchCmd,
GlobalClearPWMCmd,
ClearIRQCmd)
begin
if IrqSource'event and IRQsource = '1' then
IRQLatch <= '1';
if IRQLatch = '1' then -- if IRQLatch is set and we get the next interrupt
MissedIRQ <= '1'; -- set Missed IRQ latch
end if;
end if;
if LClk'event and LClk = '1' then
if ((IRQLatch = '1') and (LatchOnInterrupt = '1')) or (GlobalCountLatchCmd = '1') then
CountLatchEdge1 <= '1';
else
CountLatchEdge1 <= '0';
end if;
CountLatchEdge2 <= CountLatchEdge1;
if CountLatchEdge2 = '0' and CountLatchEdge1 = '1' then
GlobalCountLatch <= '1';
else
GlobalCountLatch <= '0';
end if;
end if;
if ClearMissedIRQ = '1' then
MissedIRQ <= '0';
end if;
if ((MissedIRQ = '1') and (StopOnMissedIRQ = '1')) or
((WDTimeOut = '1') and (StopOnTimeout = '1')) then
StopPWM <= '1';
else
StopPWM <= '0';
end if;
if (StopPWM = '1') or (GlobalClearPWMCmd = '1') then -- either stop on pwm or global clear reset pwm gens
GlobalClearPWM <= '1';
else
GlobalClearPWM <= '0';
end if;
if ClearIRQCmd = '1' then -- clear IRQ
IRQLatch <= '0';
end if;
Int <= not (IRQLatch and IRQMask); -- drive our (active low) interrupt pin
Ready <= '0'; -- We're always ready
end process;
LEDDrive: process (A,B,Idx,Dir,PWM,IRQLatch,LedView)
begin
LEDS(7) <= not IRQLatch;
LEDS(6) <= not OneOfFourMux(LEDView(1 downto 0),A);
LEDS(5) <= not OneOfFourMux(LEDView(1 downto 0),B);
LEDS(4) <= not OneOfFourMux(LEDView(1 downto 0),Idx);
LEDS(3) <= not OneOfFourMux(LEDView(1 downto 0),Dir);
LEDS(2) <= not OneOfFourMux(LEDView(1 downto 0),PWM);
LEDS(1) <= OneOfFourMux(LEDView(1 downto 0),EnaSigs);
LEDS(0) <= not WDTimeout;
end process leddrive;
end dataflow;
| lgpl-2.1 | e9e124a4ccf0bb4f2c37f55957ccb8cc | 0.612773 | 2.968188 | false | false | false | false |
pwsoft/fpga_examples | rtl/video/iq_mixer.vhd | 1 | 3,388 | -- -----------------------------------------------------------------------
--
-- Syntiac VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2017 by Peter Wendrich ([email protected])
-- http://www.syntiac.com
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
--
-- IQ_Mixer for PAL and NTSC video encoding.
-- Requires clk to be exactly 16 times the color-burst frequency.
-- PAL needs some additional logic to rotate phase on each line.
--
-- This design has a 3 clock cycle latency from inputs to video output.
--
--
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
-- -----------------------------------------------------------------------
entity iq_mixer is
generic (
black_level : unsigned(7 downto 0);
sync_level : unsigned(7 downto 0) := "00000000"
);
port (
clk : in std_logic;
phase_i : in unsigned(3 downto 0);
phase_q : in unsigned(3 downto 0);
in_y : in unsigned(7 downto 0);
in_i : in signed(7 downto 0);
in_q : in signed(7 downto 0);
black : in std_logic;
sync : in std_logic;
video : out unsigned(7 downto 0)
);
end entity;
-- -----------------------------------------------------------------------
architecture rtl of iq_mixer is
type sintable_t is array(integer range 0 to 15) of signed(7 downto 0);
constant sintable : sintable_t := (
X"00", X"31", X"5A", X"75", X"7F", X"75", X"5A", X"31",
X"00", X"CF", X"A6", X"8B", X"81", X"8B", X"A6", X"CF");
signal iq_i_sin : signed(15 downto 0) := (others => '0');
signal iq_q_sin : signed(15 downto 0) := (others => '0');
signal video_tmp : signed(9 downto 0) := (others => '0');
signal black_dly : std_logic := '0';
signal sync_dly : std_logic := '0';
begin
process(clk)
begin
if rising_edge(clk) then
iq_i_sin <= sintable(to_integer(phase_i)) * in_i;
iq_q_sin <= sintable(to_integer(phase_q)) * in_q;
black_dly <= black;
sync_dly <= sync;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
video_tmp <= signed("00" & in_y) + iq_i_sin(15 downto 6) + iq_q_sin(15 downto 6);
if black_dly = '1' then
video_tmp <= signed("00" & black_level);
end if;
if sync_dly = '1' then
video_tmp <= signed("00" & sync_level);
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
if video_tmp < 0 then
-- Underflow color signal
video <= "00000000";
elsif video_tmp > "0011111111" then
-- Overflow color signal
video <= "11111111";
else
video <= unsigned(video_tmp(7 downto 0));
end if;
end if;
end process;
end architecture; | lgpl-2.1 | 9047d267984d52cbaa86d4523e6317d7 | 0.570838 | 3.371144 | false | false | false | false |
18545/FPGA | src/clocking.vhd | 1 | 8,208 | -- file: clocking.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____50.000______0.000______50.0______151.636_____98.575
-- CLK_OUT2____25.000______0.000______50.0______175.402_____98.575
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary_________100.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clking is
port
(-- Clock in ports
CLK_100 : in std_logic;
-- Clock out ports
CLK_50 : out std_logic;
CLK_25 : out std_logic
);
end clking;
architecture xilinx of clking is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clking,clk_wiz_v3_6,{component_name=clking,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=2,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkfbout_buf : std_logic;
signal clkfboutb_unused : std_logic;
signal clkout0 : std_logic;
signal clkout0b_unused : std_logic;
signal clkout1 : std_logic;
signal clkout1b_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout2b_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout3b_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
signal clkout6_unused : std_logic;
-- Dynamic programming unused signals
signal do_unused : std_logic_vector(15 downto 0);
signal drdy_unused : std_logic;
-- Dynamic phase shift unused signals
signal psdone_unused : std_logic;
-- Unused status signals
signal locked_unused : std_logic;
signal clkfbstopped_unused : std_logic;
signal clkinstopped_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_100);
-- Clocking primitive
--------------------------------------
-- Instantiation of the MMCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
mmcm_adv_inst : MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => 10.000,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 20.000,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKOUT1_DIVIDE => 40,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT1_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => 10.000,
REF_JITTER1 => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKFBOUTB => clkfboutb_unused,
CLKOUT0 => clkout0,
CLKOUT0B => clkout0b_unused,
CLKOUT1 => clkout1,
CLKOUT1B => clkout1b_unused,
CLKOUT2 => clkout2_unused,
CLKOUT2B => clkout2b_unused,
CLKOUT3 => clkout3_unused,
CLKOUT3B => clkout3b_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
CLKOUT6 => clkout6_unused,
-- Input clock control
CLKFBIN => clkfbout_buf,
CLKIN1 => clkin1,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => do_unused,
DRDY => drdy_unused,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => psdone_unused,
-- Other control and status signals
LOCKED => locked_unused,
CLKINSTOPPED => clkinstopped_unused,
CLKFBSTOPPED => clkfbstopped_unused,
PWRDWN => '0',
RST => '0');
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfbout_buf,
I => clkfbout);
clkout1_buf : BUFG
port map
(O => CLK_50,
I => clkout0);
clkout2_buf : BUFG
port map
(O => CLK_25,
I => clkout1);
end xilinx;
| mit | 8f0e39c4e9412f60ff03baf59ce74141 | 0.566399 | 4.108108 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/grlib/amba/apbctrlsp.vhd | 1 | 3,453 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: apbctrl
-- File: apbctrl.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AMBA AHB/APB bridge with plug&play support
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
entity apbctrlsp is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
nslaves : integer range 1 to NAPBSLV := NAPBSLV;
wprot : integer range 0 to 1 := 0;
debug : integer range 0 to 2 := 2;
icheck : integer range 0 to 1 := 1;
enbusmon : integer range 0 to 1 := 0;
asserterr : integer range 0 to 1 := 0;
assertwarn : integer range 0 to 1 := 0;
pslvdisable : integer := 0;
mcheck : integer range 0 to 1 := 1;
ccheck : integer range 0 to 1 := 1
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbi : in ahb_slv_in_type;
ahbo : out ahb_slv_out_type;
apbi : out apb_slv_in_type;
apbo : in apb_slv_out_vector;
wp : in std_logic := '0';
wpv : in std_logic_vector((256*1)-1 downto 0) := (others => '0')
);
end;
architecture struct of apbctrlsp is
signal lahbi : ahb_slv_in_vector_type(0 to 0);
signal lahbo : ahb_slv_out_vector_type(0 to 0);
signal lapbi : apb_slv_in_vector;
signal lwp : std_logic_vector(0 to 0);
begin
lahbi(0) <= ahbi;
ahbo <= lahbo(0);
apbi <= lapbi(0);
lwp(0) <= wp;
apbx : apbctrlx
generic map(
hindex0 => hindex,
haddr0 => haddr,
hmask0 => hmask,
hindex1 => 0,
haddr1 => 0,
hmask1 => 0,
nslaves => nslaves,
nports => 1,
wprot => wprot,
debug => debug,
icheck => icheck,
enbusmon => enbusmon,
asserterr => asserterr,
assertwarn => assertwarn,
pslvdisable => pslvdisable,
mcheck => mcheck,
ccheck => ccheck)
port map(
rst => rst,
clk => clk,
ahbi => lahbi,
ahbo => lahbo,
apbi => lapbi,
apbo => apbo,
wp => lwp,
wpv => wpv);
end;
| gpl-3.0 | 1278a5f4f95d2fca63b0faebf39eec13 | 0.539531 | 3.836667 | false | false | false | false |
pwsoft/fpga_examples | rtl/general/gen_filter_tb.vhd | 1 | 2,395 | -- -----------------------------------------------------------------------
--
-- Syntiac's generic VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2010 by Peter Wendrich ([email protected])
-- http://www.syntiac.com/fpga64.html
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
--
-- gen_filter_tb.vhd
--
-- -----------------------------------------------------------------------
--
-- Testbench for signal filter
--
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- -----------------------------------------------------------------------
entity gen_filter_tb is
end entity;
-- -----------------------------------------------------------------------
architecture rtl of gen_filter_tb is
signal clk : std_logic := '0';
signal stop : std_logic := '0';
signal d : std_logic := '0';
signal q : std_logic;
procedure waitRisingEdge is
begin
wait until clk = '0';
wait until clk = '1';
wait for 0.5 ns;
end procedure;
procedure waitCheck(expected:integer) is
begin
waitRisingEdge;
assert(to_integer(unsigned'("" & q)) = expected);
end procedure;
begin
filter_inst : entity work.gen_filter
generic map (
steps => 4
)
port map (
clk => clk,
d => d,
q => q
);
clk <= (not stop) and (not clk) after 5 ns;
process
begin
d <= '0';
waitCheck(0);
d <= '1';
waitCheck(0);
waitCheck(0);
waitCheck(0);
waitCheck(0);
waitCheck(1);
d <= '0';
waitCheck(1);
waitCheck(1);
waitCheck(1);
waitCheck(1);
waitCheck(0);
stop <= '1';
wait;
end process;
end architecture;
| lgpl-2.1 | 85e1f7c68a0fe9be4c153a2a606c26f7 | 0.523591 | 3.832 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-arrow-bemicro-sdk/config.vhd | 1 | 6,898 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2011 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := cyclone3;
constant CFG_MEMTECH : integer := cyclone3;
constant CFG_PADTECH : integer := cyclone3;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := cyclone3;
constant CFG_CLKMUL : integer := (5);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 1;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 1;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 1*2 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 0 + 0 + 0;
constant CFG_ETH_BUF : integer := 1;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000009#;
-- DDR controller
constant CFG_DDRSP : integer := 1;
constant CFG_DDRSP_INIT : integer := 1;
constant CFG_DDRSP_FREQ : integer := (100);
constant CFG_DDRSP_COL : integer := (10);
constant CFG_DDRSP_SIZE : integer := (64);
constant CFG_DDRSP_RSKEW : integer := (0);
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 1;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#0b#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 1;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := (1);
constant CFG_SPIMCTRL_ASCALER : integer := (2);
constant CFG_SPIMCTRL_PWRUPCNT : integer := (0);
constant CFG_SPIMCTRL_OFFSET : integer := 16#50000#;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 16;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (4);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0#;
constant CFG_GRGPIO_WIDTH : integer := (6);
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 1;
constant CFG_SPICTRL_NUM : integer := (2);
constant CFG_SPICTRL_SLVS : integer := (1);
constant CFG_SPICTRL_FIFO : integer := (2);
constant CFG_SPICTRL_SLVREG : integer := 1;
constant CFG_SPICTRL_ODMODE : integer := 0;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 1;
constant CFG_SPICTRL_TWEN : integer := 1;
constant CFG_SPICTRL_MAXWLEN : integer := (0);
constant CFG_SPICTRL_SYNCRAM : integer := 0;
constant CFG_SPICTRL_FT : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-3.0 | 92b0e4daf129c94c908f2cf13ef8cf8e | 0.647579 | 3.649735 | false | false | false | false |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.